Version:  2.0.40 2.2.26 2.4.37 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

Linux/drivers/tty/serial/xilinx_uartps.c

  1 /*
  2  * Cadence UART driver (found in Xilinx Zynq)
  3  *
  4  * 2011 - 2014 (C) Xilinx Inc.
  5  *
  6  * This program is free software; you can redistribute it
  7  * and/or modify it under the terms of the GNU General Public
  8  * License as published by the Free Software Foundation;
  9  * either version 2 of the License, or (at your option) any
 10  * later version.
 11  *
 12  * This driver has originally been pushed by Xilinx using a Zynq-branding. This
 13  * still shows in the naming of this file, the kconfig symbols and some symbols
 14  * in the code.
 15  */
 16 
 17 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 18 #define SUPPORT_SYSRQ
 19 #endif
 20 
 21 #include <linux/platform_device.h>
 22 #include <linux/serial.h>
 23 #include <linux/console.h>
 24 #include <linux/serial_core.h>
 25 #include <linux/slab.h>
 26 #include <linux/tty.h>
 27 #include <linux/tty_flip.h>
 28 #include <linux/clk.h>
 29 #include <linux/irq.h>
 30 #include <linux/io.h>
 31 #include <linux/of.h>
 32 #include <linux/module.h>
 33 
 34 #define CDNS_UART_TTY_NAME      "ttyPS"
 35 #define CDNS_UART_NAME          "xuartps"
 36 #define CDNS_UART_MAJOR         0       /* use dynamic node allocation */
 37 #define CDNS_UART_MINOR         0       /* works best with devtmpfs */
 38 #define CDNS_UART_NR_PORTS      2
 39 #define CDNS_UART_FIFO_SIZE     64      /* FIFO size */
 40 #define CDNS_UART_REGISTER_SPACE        0x1000
 41 
 42 /* Rx Trigger level */
 43 static int rx_trigger_level = 56;
 44 module_param(rx_trigger_level, uint, S_IRUGO);
 45 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
 46 
 47 /* Rx Timeout */
 48 static int rx_timeout = 10;
 49 module_param(rx_timeout, uint, S_IRUGO);
 50 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
 51 
 52 /* Register offsets for the UART. */
 53 #define CDNS_UART_CR            0x00  /* Control Register */
 54 #define CDNS_UART_MR            0x04  /* Mode Register */
 55 #define CDNS_UART_IER           0x08  /* Interrupt Enable */
 56 #define CDNS_UART_IDR           0x0C  /* Interrupt Disable */
 57 #define CDNS_UART_IMR           0x10  /* Interrupt Mask */
 58 #define CDNS_UART_ISR           0x14  /* Interrupt Status */
 59 #define CDNS_UART_BAUDGEN       0x18  /* Baud Rate Generator */
 60 #define CDNS_UART_RXTOUT        0x1C  /* RX Timeout */
 61 #define CDNS_UART_RXWM          0x20  /* RX FIFO Trigger Level */
 62 #define CDNS_UART_MODEMCR       0x24  /* Modem Control */
 63 #define CDNS_UART_MODEMSR       0x28  /* Modem Status */
 64 #define CDNS_UART_SR            0x2C  /* Channel Status */
 65 #define CDNS_UART_FIFO          0x30  /* FIFO */
 66 #define CDNS_UART_BAUDDIV       0x34  /* Baud Rate Divider */
 67 #define CDNS_UART_FLOWDEL       0x38  /* Flow Delay */
 68 #define CDNS_UART_IRRX_PWIDTH   0x3C  /* IR Min Received Pulse Width */
 69 #define CDNS_UART_IRTX_PWIDTH   0x40  /* IR Transmitted pulse Width */
 70 #define CDNS_UART_TXWM          0x44  /* TX FIFO Trigger Level */
 71 #define CDNS_UART_RXBS          0x48  /* RX FIFO byte status register */
 72 
 73 /* Control Register Bit Definitions */
 74 #define CDNS_UART_CR_STOPBRK    0x00000100  /* Stop TX break */
 75 #define CDNS_UART_CR_STARTBRK   0x00000080  /* Set TX break */
 76 #define CDNS_UART_CR_TX_DIS     0x00000020  /* TX disabled. */
 77 #define CDNS_UART_CR_TX_EN      0x00000010  /* TX enabled */
 78 #define CDNS_UART_CR_RX_DIS     0x00000008  /* RX disabled. */
 79 #define CDNS_UART_CR_RX_EN      0x00000004  /* RX enabled */
 80 #define CDNS_UART_CR_TXRST      0x00000002  /* TX logic reset */
 81 #define CDNS_UART_CR_RXRST      0x00000001  /* RX logic reset */
 82 #define CDNS_UART_CR_RST_TO     0x00000040  /* Restart Timeout Counter */
 83 #define CDNS_UART_RXBS_PARITY    0x00000001 /* Parity error status */
 84 #define CDNS_UART_RXBS_FRAMING   0x00000002 /* Framing error status */
 85 #define CDNS_UART_RXBS_BRK       0x00000004 /* Overrun error status */
 86 
 87 /*
 88  * Mode Register:
 89  * The mode register (MR) defines the mode of transfer as well as the data
 90  * format. If this register is modified during transmission or reception,
 91  * data validity cannot be guaranteed.
 92  */
 93 #define CDNS_UART_MR_CLKSEL             0x00000001  /* Pre-scalar selection */
 94 #define CDNS_UART_MR_CHMODE_L_LOOP      0x00000200  /* Local loop back mode */
 95 #define CDNS_UART_MR_CHMODE_NORM        0x00000000  /* Normal mode */
 96 
 97 #define CDNS_UART_MR_STOPMODE_2_BIT     0x00000080  /* 2 stop bits */
 98 #define CDNS_UART_MR_STOPMODE_1_BIT     0x00000000  /* 1 stop bit */
 99 
100 #define CDNS_UART_MR_PARITY_NONE        0x00000020  /* No parity mode */
101 #define CDNS_UART_MR_PARITY_MARK        0x00000018  /* Mark parity mode */
102 #define CDNS_UART_MR_PARITY_SPACE       0x00000010  /* Space parity mode */
103 #define CDNS_UART_MR_PARITY_ODD         0x00000008  /* Odd parity mode */
104 #define CDNS_UART_MR_PARITY_EVEN        0x00000000  /* Even parity mode */
105 
106 #define CDNS_UART_MR_CHARLEN_6_BIT      0x00000006  /* 6 bits data */
107 #define CDNS_UART_MR_CHARLEN_7_BIT      0x00000004  /* 7 bits data */
108 #define CDNS_UART_MR_CHARLEN_8_BIT      0x00000000  /* 8 bits data */
109 
110 /*
111  * Interrupt Registers:
112  * Interrupt control logic uses the interrupt enable register (IER) and the
113  * interrupt disable register (IDR) to set the value of the bits in the
114  * interrupt mask register (IMR). The IMR determines whether to pass an
115  * interrupt to the interrupt status register (ISR).
116  * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
117  * interrupt. IMR and ISR are read only, and IER and IDR are write only.
118  * Reading either IER or IDR returns 0x00.
119  * All four registers have the same bit definitions.
120  */
121 #define CDNS_UART_IXR_TOUT      0x00000100 /* RX Timeout error interrupt */
122 #define CDNS_UART_IXR_PARITY    0x00000080 /* Parity error interrupt */
123 #define CDNS_UART_IXR_FRAMING   0x00000040 /* Framing error interrupt */
124 #define CDNS_UART_IXR_OVERRUN   0x00000020 /* Overrun error interrupt */
125 #define CDNS_UART_IXR_TXFULL    0x00000010 /* TX FIFO Full interrupt */
126 #define CDNS_UART_IXR_TXEMPTY   0x00000008 /* TX FIFO empty interrupt */
127 #define CDNS_UART_ISR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt */
128 #define CDNS_UART_IXR_RXTRIG    0x00000001 /* RX FIFO trigger interrupt */
129 #define CDNS_UART_IXR_RXFULL    0x00000004 /* RX FIFO full interrupt. */
130 #define CDNS_UART_IXR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt. */
131 #define CDNS_UART_IXR_MASK      0x00001FFF /* Valid bit mask */
132 
133         /*
134          * Do not enable parity error interrupt for the following
135          * reason: When parity error interrupt is enabled, each Rx
136          * parity error always results in 2 events. The first one
137          * being parity error interrupt and the second one with a
138          * proper Rx interrupt with the incoming data.  Disabling
139          * parity error interrupt ensures better handling of parity
140          * error events. With this change, for a parity error case, we
141          * get a Rx interrupt with parity error set in ISR register
142          * and we still handle parity errors in the desired way.
143          */
144 
145 #define CDNS_UART_RX_IRQS       (CDNS_UART_IXR_FRAMING | \
146                                  CDNS_UART_IXR_OVERRUN | \
147                                  CDNS_UART_IXR_RXTRIG |  \
148                                  CDNS_UART_IXR_TOUT)
149 
150 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
151 #define CDNS_UART_IXR_BRK       0x00002000
152 
153 #define CDNS_UART_RXBS_SUPPORT BIT(1)
154 /*
155  * Modem Control register:
156  * The read/write Modem Control register controls the interface with the modem
157  * or data set, or a peripheral device emulating a modem.
158  */
159 #define CDNS_UART_MODEMCR_FCM   0x00000020 /* Automatic flow control mode */
160 #define CDNS_UART_MODEMCR_RTS   0x00000002 /* Request to send output control */
161 #define CDNS_UART_MODEMCR_DTR   0x00000001 /* Data Terminal Ready */
162 
163 /*
164  * Channel Status Register:
165  * The channel status register (CSR) is provided to enable the control logic
166  * to monitor the status of bits in the channel interrupt status register,
167  * even if these are masked out by the interrupt mask register.
168  */
169 #define CDNS_UART_SR_RXEMPTY    0x00000002 /* RX FIFO empty */
170 #define CDNS_UART_SR_TXEMPTY    0x00000008 /* TX FIFO empty */
171 #define CDNS_UART_SR_TXFULL     0x00000010 /* TX FIFO full */
172 #define CDNS_UART_SR_RXTRIG     0x00000001 /* Rx Trigger */
173 
174 /* baud dividers min/max values */
175 #define CDNS_UART_BDIV_MIN      4
176 #define CDNS_UART_BDIV_MAX      255
177 #define CDNS_UART_CD_MAX        65535
178 
179 /**
180  * struct cdns_uart - device data
181  * @port:               Pointer to the UART port
182  * @uartclk:            Reference clock
183  * @pclk:               APB clock
184  * @baud:               Current baud rate
185  * @clk_rate_change_nb: Notifier block for clock changes
186  */
187 struct cdns_uart {
188         struct uart_port        *port;
189         struct clk              *uartclk;
190         struct clk              *pclk;
191         unsigned int            baud;
192         struct notifier_block   clk_rate_change_nb;
193         u32                     quirks;
194 };
195 struct cdns_platform_data {
196         u32 quirks;
197 };
198 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
199                 clk_rate_change_nb);
200 
201 /**
202  * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
203  * @dev_id: Id of the UART port
204  * @isrstatus: The interrupt status register value as read
205  * Return: None
206  */
207 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
208 {
209         struct uart_port *port = (struct uart_port *)dev_id;
210         struct cdns_uart *cdns_uart = port->private_data;
211         unsigned int data;
212         unsigned int rxbs_status = 0;
213         unsigned int status_mask;
214         unsigned int framerrprocessed = 0;
215         char status = TTY_NORMAL;
216         bool is_rxbs_support;
217 
218         is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
219 
220         while ((readl(port->membase + CDNS_UART_SR) &
221                 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
222                 if (is_rxbs_support)
223                         rxbs_status = readl(port->membase + CDNS_UART_RXBS);
224                 data = readl(port->membase + CDNS_UART_FIFO);
225                 port->icount.rx++;
226                 /*
227                  * There is no hardware break detection in Zynq, so we interpret
228                  * framing error with all-zeros data as a break sequence.
229                  * Most of the time, there's another non-zero byte at the
230                  * end of the sequence.
231                  */
232                 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
233                         if (!data) {
234                                 port->read_status_mask |= CDNS_UART_IXR_BRK;
235                                 framerrprocessed = 1;
236                                 continue;
237                         }
238                 }
239                 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
240                         port->icount.brk++;
241                         status = TTY_BREAK;
242                         if (uart_handle_break(port))
243                                 continue;
244                 }
245 
246                 isrstatus &= port->read_status_mask;
247                 isrstatus &= ~port->ignore_status_mask;
248                 status_mask = port->read_status_mask;
249                 status_mask &= ~port->ignore_status_mask;
250 
251                 if (data &&
252                     (port->read_status_mask & CDNS_UART_IXR_BRK)) {
253                         port->read_status_mask &= ~CDNS_UART_IXR_BRK;
254                         port->icount.brk++;
255                         if (uart_handle_break(port))
256                                 continue;
257                 }
258 
259                 if (uart_handle_sysrq_char(port, data))
260                         continue;
261 
262                 if (is_rxbs_support) {
263                         if ((rxbs_status & CDNS_UART_RXBS_PARITY)
264                             && (status_mask & CDNS_UART_IXR_PARITY)) {
265                                 port->icount.parity++;
266                                 status = TTY_PARITY;
267                         }
268                         if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
269                             && (status_mask & CDNS_UART_IXR_PARITY)) {
270                                 port->icount.frame++;
271                                 status = TTY_FRAME;
272                         }
273                 } else {
274                         if (isrstatus & CDNS_UART_IXR_PARITY) {
275                                 port->icount.parity++;
276                                 status = TTY_PARITY;
277                         }
278                         if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
279                             !framerrprocessed) {
280                                 port->icount.frame++;
281                                 status = TTY_FRAME;
282                         }
283                 }
284                 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
285                         port->icount.overrun++;
286                         tty_insert_flip_char(&port->state->port, 0,
287                                              TTY_OVERRUN);
288                 }
289                 tty_insert_flip_char(&port->state->port, data, status);
290                 isrstatus = 0;
291         }
292         spin_unlock(&port->lock);
293         tty_flip_buffer_push(&port->state->port);
294         spin_lock(&port->lock);
295 }
296 
297 /**
298  * cdns_uart_handle_tx - Handle the bytes to be Txed.
299  * @dev_id: Id of the UART port
300  * Return: None
301  */
302 static void cdns_uart_handle_tx(void *dev_id)
303 {
304         struct uart_port *port = (struct uart_port *)dev_id;
305         unsigned int numbytes;
306 
307         if (uart_circ_empty(&port->state->xmit)) {
308                 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
309         } else {
310                 numbytes = port->fifosize;
311                 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
312                        !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
313                         /*
314                          * Get the data from the UART circular buffer
315                          * and write it to the cdns_uart's TX_FIFO
316                          * register.
317                          */
318                         writel(
319                                 port->state->xmit.buf[port->state->xmit.
320                                 tail], port->membase + CDNS_UART_FIFO);
321 
322                         port->icount.tx++;
323 
324                         /*
325                          * Adjust the tail of the UART buffer and wrap
326                          * the buffer if it reaches limit.
327                          */
328                         port->state->xmit.tail =
329                                 (port->state->xmit.tail + 1) &
330                                         (UART_XMIT_SIZE - 1);
331 
332                         numbytes--;
333                 }
334 
335                 if (uart_circ_chars_pending(
336                                 &port->state->xmit) < WAKEUP_CHARS)
337                         uart_write_wakeup(port);
338         }
339 }
340 
341 /**
342  * cdns_uart_isr - Interrupt handler
343  * @irq: Irq number
344  * @dev_id: Id of the port
345  *
346  * Return: IRQHANDLED
347  */
348 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
349 {
350         struct uart_port *port = (struct uart_port *)dev_id;
351         unsigned int isrstatus;
352 
353         spin_lock(&port->lock);
354 
355         /* Read the interrupt status register to determine which
356          * interrupt(s) is/are active and clear them.
357          */
358         isrstatus = readl(port->membase + CDNS_UART_ISR);
359         writel(isrstatus, port->membase + CDNS_UART_ISR);
360 
361         if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
362                 cdns_uart_handle_tx(dev_id);
363                 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
364         }
365         if (isrstatus & CDNS_UART_IXR_MASK)
366                 cdns_uart_handle_rx(dev_id, isrstatus);
367 
368         spin_unlock(&port->lock);
369         return IRQ_HANDLED;
370 }
371 
372 /**
373  * cdns_uart_calc_baud_divs - Calculate baud rate divisors
374  * @clk: UART module input clock
375  * @baud: Desired baud rate
376  * @rbdiv: BDIV value (return value)
377  * @rcd: CD value (return value)
378  * @div8: Value for clk_sel bit in mod (return value)
379  * Return: baud rate, requested baud when possible, or actual baud when there
380  *      was too much error, zero if no valid divisors are found.
381  *
382  * Formula to obtain baud rate is
383  *      baud_tx/rx rate = clk/CD * (BDIV + 1)
384  *      input_clk = (Uart User Defined Clock or Apb Clock)
385  *              depends on UCLKEN in MR Reg
386  *      clk = input_clk or input_clk/8;
387  *              depends on CLKS in MR reg
388  *      CD and BDIV depends on values in
389  *                      baud rate generate register
390  *                      baud rate clock divisor register
391  */
392 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
393                 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
394 {
395         u32 cd, bdiv;
396         unsigned int calc_baud;
397         unsigned int bestbaud = 0;
398         unsigned int bauderror;
399         unsigned int besterror = ~0;
400 
401         if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
402                 *div8 = 1;
403                 clk /= 8;
404         } else {
405                 *div8 = 0;
406         }
407 
408         for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
409                 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
410                 if (cd < 1 || cd > CDNS_UART_CD_MAX)
411                         continue;
412 
413                 calc_baud = clk / (cd * (bdiv + 1));
414 
415                 if (baud > calc_baud)
416                         bauderror = baud - calc_baud;
417                 else
418                         bauderror = calc_baud - baud;
419 
420                 if (besterror > bauderror) {
421                         *rbdiv = bdiv;
422                         *rcd = cd;
423                         bestbaud = calc_baud;
424                         besterror = bauderror;
425                 }
426         }
427         /* use the values when percent error is acceptable */
428         if (((besterror * 100) / baud) < 3)
429                 bestbaud = baud;
430 
431         return bestbaud;
432 }
433 
434 /**
435  * cdns_uart_set_baud_rate - Calculate and set the baud rate
436  * @port: Handle to the uart port structure
437  * @baud: Baud rate to set
438  * Return: baud rate, requested baud when possible, or actual baud when there
439  *         was too much error, zero if no valid divisors are found.
440  */
441 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
442                 unsigned int baud)
443 {
444         unsigned int calc_baud;
445         u32 cd = 0, bdiv = 0;
446         u32 mreg;
447         int div8;
448         struct cdns_uart *cdns_uart = port->private_data;
449 
450         calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
451                         &div8);
452 
453         /* Write new divisors to hardware */
454         mreg = readl(port->membase + CDNS_UART_MR);
455         if (div8)
456                 mreg |= CDNS_UART_MR_CLKSEL;
457         else
458                 mreg &= ~CDNS_UART_MR_CLKSEL;
459         writel(mreg, port->membase + CDNS_UART_MR);
460         writel(cd, port->membase + CDNS_UART_BAUDGEN);
461         writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
462         cdns_uart->baud = baud;
463 
464         return calc_baud;
465 }
466 
467 #ifdef CONFIG_COMMON_CLK
468 /**
469  * cdns_uart_clk_notitifer_cb - Clock notifier callback
470  * @nb:         Notifier block
471  * @event:      Notify event
472  * @data:       Notifier data
473  * Return:      NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
474  */
475 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
476                 unsigned long event, void *data)
477 {
478         u32 ctrl_reg;
479         struct uart_port *port;
480         int locked = 0;
481         struct clk_notifier_data *ndata = data;
482         unsigned long flags = 0;
483         struct cdns_uart *cdns_uart = to_cdns_uart(nb);
484 
485         port = cdns_uart->port;
486         if (port->suspended)
487                 return NOTIFY_OK;
488 
489         switch (event) {
490         case PRE_RATE_CHANGE:
491         {
492                 u32 bdiv, cd;
493                 int div8;
494 
495                 /*
496                  * Find out if current baud-rate can be achieved with new clock
497                  * frequency.
498                  */
499                 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
500                                         &bdiv, &cd, &div8)) {
501                         dev_warn(port->dev, "clock rate change rejected\n");
502                         return NOTIFY_BAD;
503                 }
504 
505                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
506 
507                 /* Disable the TX and RX to set baud rate */
508                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
509                 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
510                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
511 
512                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
513 
514                 return NOTIFY_OK;
515         }
516         case POST_RATE_CHANGE:
517                 /*
518                  * Set clk dividers to generate correct baud with new clock
519                  * frequency.
520                  */
521 
522                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
523 
524                 locked = 1;
525                 port->uartclk = ndata->new_rate;
526 
527                 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
528                                 cdns_uart->baud);
529                 /* fall through */
530         case ABORT_RATE_CHANGE:
531                 if (!locked)
532                         spin_lock_irqsave(&cdns_uart->port->lock, flags);
533 
534                 /* Set TX/RX Reset */
535                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
536                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
537                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
538 
539                 while (readl(port->membase + CDNS_UART_CR) &
540                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
541                         cpu_relax();
542 
543                 /*
544                  * Clear the RX disable and TX disable bits and then set the TX
545                  * enable bit and RX enable bit to enable the transmitter and
546                  * receiver.
547                  */
548                 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
549                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
550                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
551                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
552                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
553 
554                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
555 
556                 return NOTIFY_OK;
557         default:
558                 return NOTIFY_DONE;
559         }
560 }
561 #endif
562 
563 /**
564  * cdns_uart_start_tx -  Start transmitting bytes
565  * @port: Handle to the uart port structure
566  */
567 static void cdns_uart_start_tx(struct uart_port *port)
568 {
569         unsigned int status;
570 
571         if (uart_tx_stopped(port))
572                 return;
573 
574         /*
575          * Set the TX enable bit and clear the TX disable bit to enable the
576          * transmitter.
577          */
578         status = readl(port->membase + CDNS_UART_CR);
579         status &= ~CDNS_UART_CR_TX_DIS;
580         status |= CDNS_UART_CR_TX_EN;
581         writel(status, port->membase + CDNS_UART_CR);
582 
583         if (uart_circ_empty(&port->state->xmit))
584                 return;
585 
586         cdns_uart_handle_tx(port);
587 
588         writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
589         /* Enable the TX Empty interrupt */
590         writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
591 }
592 
593 /**
594  * cdns_uart_stop_tx - Stop TX
595  * @port: Handle to the uart port structure
596  */
597 static void cdns_uart_stop_tx(struct uart_port *port)
598 {
599         unsigned int regval;
600 
601         regval = readl(port->membase + CDNS_UART_CR);
602         regval |= CDNS_UART_CR_TX_DIS;
603         /* Disable the transmitter */
604         writel(regval, port->membase + CDNS_UART_CR);
605 }
606 
607 /**
608  * cdns_uart_stop_rx - Stop RX
609  * @port: Handle to the uart port structure
610  */
611 static void cdns_uart_stop_rx(struct uart_port *port)
612 {
613         unsigned int regval;
614 
615         /* Disable RX IRQs */
616         writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
617 
618         /* Disable the receiver */
619         regval = readl(port->membase + CDNS_UART_CR);
620         regval |= CDNS_UART_CR_RX_DIS;
621         writel(regval, port->membase + CDNS_UART_CR);
622 }
623 
624 /**
625  * cdns_uart_tx_empty -  Check whether TX is empty
626  * @port: Handle to the uart port structure
627  *
628  * Return: TIOCSER_TEMT on success, 0 otherwise
629  */
630 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
631 {
632         unsigned int status;
633 
634         status = readl(port->membase + CDNS_UART_SR) &
635                                 CDNS_UART_SR_TXEMPTY;
636         return status ? TIOCSER_TEMT : 0;
637 }
638 
639 /**
640  * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
641  *                      transmitting char breaks
642  * @port: Handle to the uart port structure
643  * @ctl: Value based on which start or stop decision is taken
644  */
645 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
646 {
647         unsigned int status;
648         unsigned long flags;
649 
650         spin_lock_irqsave(&port->lock, flags);
651 
652         status = readl(port->membase + CDNS_UART_CR);
653 
654         if (ctl == -1)
655                 writel(CDNS_UART_CR_STARTBRK | status,
656                                 port->membase + CDNS_UART_CR);
657         else {
658                 if ((status & CDNS_UART_CR_STOPBRK) == 0)
659                         writel(CDNS_UART_CR_STOPBRK | status,
660                                         port->membase + CDNS_UART_CR);
661         }
662         spin_unlock_irqrestore(&port->lock, flags);
663 }
664 
665 /**
666  * cdns_uart_set_termios - termios operations, handling data length, parity,
667  *                              stop bits, flow control, baud rate
668  * @port: Handle to the uart port structure
669  * @termios: Handle to the input termios structure
670  * @old: Values of the previously saved termios structure
671  */
672 static void cdns_uart_set_termios(struct uart_port *port,
673                                 struct ktermios *termios, struct ktermios *old)
674 {
675         unsigned int cval = 0;
676         unsigned int baud, minbaud, maxbaud;
677         unsigned long flags;
678         unsigned int ctrl_reg, mode_reg;
679 
680         spin_lock_irqsave(&port->lock, flags);
681 
682         /* Wait for the transmit FIFO to empty before making changes */
683         if (!(readl(port->membase + CDNS_UART_CR) &
684                                 CDNS_UART_CR_TX_DIS)) {
685                 while (!(readl(port->membase + CDNS_UART_SR) &
686                                 CDNS_UART_SR_TXEMPTY)) {
687                         cpu_relax();
688                 }
689         }
690 
691         /* Disable the TX and RX to set baud rate */
692         ctrl_reg = readl(port->membase + CDNS_UART_CR);
693         ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
694         writel(ctrl_reg, port->membase + CDNS_UART_CR);
695 
696         /*
697          * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
698          * min and max baud should be calculated here based on port->uartclk.
699          * this way we get a valid baud and can safely call set_baud()
700          */
701         minbaud = port->uartclk /
702                         ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
703         maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
704         baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
705         baud = cdns_uart_set_baud_rate(port, baud);
706         if (tty_termios_baud_rate(termios))
707                 tty_termios_encode_baud_rate(termios, baud, baud);
708 
709         /* Update the per-port timeout. */
710         uart_update_timeout(port, termios->c_cflag, baud);
711 
712         /* Set TX/RX Reset */
713         ctrl_reg = readl(port->membase + CDNS_UART_CR);
714         ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
715         writel(ctrl_reg, port->membase + CDNS_UART_CR);
716 
717         while (readl(port->membase + CDNS_UART_CR) &
718                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
719                 cpu_relax();
720 
721         /*
722          * Clear the RX disable and TX disable bits and then set the TX enable
723          * bit and RX enable bit to enable the transmitter and receiver.
724          */
725         ctrl_reg = readl(port->membase + CDNS_UART_CR);
726         ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
727         ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
728         writel(ctrl_reg, port->membase + CDNS_UART_CR);
729 
730         writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
731 
732         port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
733                         CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
734         port->ignore_status_mask = 0;
735 
736         if (termios->c_iflag & INPCK)
737                 port->read_status_mask |= CDNS_UART_IXR_PARITY |
738                 CDNS_UART_IXR_FRAMING;
739 
740         if (termios->c_iflag & IGNPAR)
741                 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
742                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
743 
744         /* ignore all characters if CREAD is not set */
745         if ((termios->c_cflag & CREAD) == 0)
746                 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
747                         CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
748                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
749 
750         mode_reg = readl(port->membase + CDNS_UART_MR);
751 
752         /* Handling Data Size */
753         switch (termios->c_cflag & CSIZE) {
754         case CS6:
755                 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
756                 break;
757         case CS7:
758                 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
759                 break;
760         default:
761         case CS8:
762                 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
763                 termios->c_cflag &= ~CSIZE;
764                 termios->c_cflag |= CS8;
765                 break;
766         }
767 
768         /* Handling Parity and Stop Bits length */
769         if (termios->c_cflag & CSTOPB)
770                 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
771         else
772                 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
773 
774         if (termios->c_cflag & PARENB) {
775                 /* Mark or Space parity */
776                 if (termios->c_cflag & CMSPAR) {
777                         if (termios->c_cflag & PARODD)
778                                 cval |= CDNS_UART_MR_PARITY_MARK;
779                         else
780                                 cval |= CDNS_UART_MR_PARITY_SPACE;
781                 } else {
782                         if (termios->c_cflag & PARODD)
783                                 cval |= CDNS_UART_MR_PARITY_ODD;
784                         else
785                                 cval |= CDNS_UART_MR_PARITY_EVEN;
786                 }
787         } else {
788                 cval |= CDNS_UART_MR_PARITY_NONE;
789         }
790         cval |= mode_reg & 1;
791         writel(cval, port->membase + CDNS_UART_MR);
792 
793         spin_unlock_irqrestore(&port->lock, flags);
794 }
795 
796 /**
797  * cdns_uart_startup - Called when an application opens a cdns_uart port
798  * @port: Handle to the uart port structure
799  *
800  * Return: 0 on success, negative errno otherwise
801  */
802 static int cdns_uart_startup(struct uart_port *port)
803 {
804         struct cdns_uart *cdns_uart = port->private_data;
805         bool is_brk_support;
806         int ret;
807         unsigned long flags;
808         unsigned int status = 0;
809 
810         is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
811 
812         spin_lock_irqsave(&port->lock, flags);
813 
814         /* Disable the TX and RX */
815         writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
816                         port->membase + CDNS_UART_CR);
817 
818         /* Set the Control Register with TX/RX Enable, TX/RX Reset,
819          * no break chars.
820          */
821         writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
822                         port->membase + CDNS_UART_CR);
823 
824         while (readl(port->membase + CDNS_UART_CR) &
825                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
826                 cpu_relax();
827 
828         /*
829          * Clear the RX disable bit and then set the RX enable bit to enable
830          * the receiver.
831          */
832         status = readl(port->membase + CDNS_UART_CR);
833         status &= CDNS_UART_CR_RX_DIS;
834         status |= CDNS_UART_CR_RX_EN;
835         writel(status, port->membase + CDNS_UART_CR);
836 
837         /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
838          * no parity.
839          */
840         writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
841                 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
842                 port->membase + CDNS_UART_MR);
843 
844         /*
845          * Set the RX FIFO Trigger level to use most of the FIFO, but it
846          * can be tuned with a module parameter
847          */
848         writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
849 
850         /*
851          * Receive Timeout register is enabled but it
852          * can be tuned with a module parameter
853          */
854         writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
855 
856         /* Clear out any pending interrupts before enabling them */
857         writel(readl(port->membase + CDNS_UART_ISR),
858                         port->membase + CDNS_UART_ISR);
859 
860         spin_unlock_irqrestore(&port->lock, flags);
861 
862         ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
863         if (ret) {
864                 dev_err(port->dev, "request_irq '%d' failed with %d\n",
865                         port->irq, ret);
866                 return ret;
867         }
868 
869         /* Set the Interrupt Registers with desired interrupts */
870         if (is_brk_support)
871                 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
872                                         port->membase + CDNS_UART_IER);
873         else
874                 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
875 
876         return 0;
877 }
878 
879 /**
880  * cdns_uart_shutdown - Called when an application closes a cdns_uart port
881  * @port: Handle to the uart port structure
882  */
883 static void cdns_uart_shutdown(struct uart_port *port)
884 {
885         int status;
886         unsigned long flags;
887 
888         spin_lock_irqsave(&port->lock, flags);
889 
890         /* Disable interrupts */
891         status = readl(port->membase + CDNS_UART_IMR);
892         writel(status, port->membase + CDNS_UART_IDR);
893         writel(0xffffffff, port->membase + CDNS_UART_ISR);
894 
895         /* Disable the TX and RX */
896         writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
897                         port->membase + CDNS_UART_CR);
898 
899         spin_unlock_irqrestore(&port->lock, flags);
900 
901         free_irq(port->irq, port);
902 }
903 
904 /**
905  * cdns_uart_type - Set UART type to cdns_uart port
906  * @port: Handle to the uart port structure
907  *
908  * Return: string on success, NULL otherwise
909  */
910 static const char *cdns_uart_type(struct uart_port *port)
911 {
912         return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
913 }
914 
915 /**
916  * cdns_uart_verify_port - Verify the port params
917  * @port: Handle to the uart port structure
918  * @ser: Handle to the structure whose members are compared
919  *
920  * Return: 0 on success, negative errno otherwise.
921  */
922 static int cdns_uart_verify_port(struct uart_port *port,
923                                         struct serial_struct *ser)
924 {
925         if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
926                 return -EINVAL;
927         if (port->irq != ser->irq)
928                 return -EINVAL;
929         if (ser->io_type != UPIO_MEM)
930                 return -EINVAL;
931         if (port->iobase != ser->port)
932                 return -EINVAL;
933         if (ser->hub6 != 0)
934                 return -EINVAL;
935         return 0;
936 }
937 
938 /**
939  * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
940  *                              called when the driver adds a cdns_uart port via
941  *                              uart_add_one_port()
942  * @port: Handle to the uart port structure
943  *
944  * Return: 0 on success, negative errno otherwise.
945  */
946 static int cdns_uart_request_port(struct uart_port *port)
947 {
948         if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
949                                          CDNS_UART_NAME)) {
950                 return -ENOMEM;
951         }
952 
953         port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
954         if (!port->membase) {
955                 dev_err(port->dev, "Unable to map registers\n");
956                 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
957                 return -ENOMEM;
958         }
959         return 0;
960 }
961 
962 /**
963  * cdns_uart_release_port - Release UART port
964  * @port: Handle to the uart port structure
965  *
966  * Release the memory region attached to a cdns_uart port. Called when the
967  * driver removes a cdns_uart port via uart_remove_one_port().
968  */
969 static void cdns_uart_release_port(struct uart_port *port)
970 {
971         release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
972         iounmap(port->membase);
973         port->membase = NULL;
974 }
975 
976 /**
977  * cdns_uart_config_port - Configure UART port
978  * @port: Handle to the uart port structure
979  * @flags: If any
980  */
981 static void cdns_uart_config_port(struct uart_port *port, int flags)
982 {
983         if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
984                 port->type = PORT_XUARTPS;
985 }
986 
987 /**
988  * cdns_uart_get_mctrl - Get the modem control state
989  * @port: Handle to the uart port structure
990  *
991  * Return: the modem control state
992  */
993 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
994 {
995         return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
996 }
997 
998 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
999 {
1000         u32 val;
1001 
1002         val = readl(port->membase + CDNS_UART_MODEMCR);
1003 
1004         val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1005 
1006         if (mctrl & TIOCM_RTS)
1007                 val |= CDNS_UART_MODEMCR_RTS;
1008         if (mctrl & TIOCM_DTR)
1009                 val |= CDNS_UART_MODEMCR_DTR;
1010 
1011         writel(val, port->membase + CDNS_UART_MODEMCR);
1012 }
1013 
1014 #ifdef CONFIG_CONSOLE_POLL
1015 static int cdns_uart_poll_get_char(struct uart_port *port)
1016 {
1017         int c;
1018         unsigned long flags;
1019 
1020         spin_lock_irqsave(&port->lock, flags);
1021 
1022         /* Check if FIFO is empty */
1023         if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1024                 c = NO_POLL_CHAR;
1025         else /* Read a character */
1026                 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1027 
1028         spin_unlock_irqrestore(&port->lock, flags);
1029 
1030         return c;
1031 }
1032 
1033 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1034 {
1035         unsigned long flags;
1036 
1037         spin_lock_irqsave(&port->lock, flags);
1038 
1039         /* Wait until FIFO is empty */
1040         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1041                 cpu_relax();
1042 
1043         /* Write a character */
1044         writel(c, port->membase + CDNS_UART_FIFO);
1045 
1046         /* Wait until FIFO is empty */
1047         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1048                 cpu_relax();
1049 
1050         spin_unlock_irqrestore(&port->lock, flags);
1051 
1052         return;
1053 }
1054 #endif
1055 
1056 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1057                    unsigned int oldstate)
1058 {
1059         struct cdns_uart *cdns_uart = port->private_data;
1060 
1061         switch (state) {
1062         case UART_PM_STATE_OFF:
1063                 clk_disable(cdns_uart->uartclk);
1064                 clk_disable(cdns_uart->pclk);
1065                 break;
1066         default:
1067                 clk_enable(cdns_uart->pclk);
1068                 clk_enable(cdns_uart->uartclk);
1069                 break;
1070         }
1071 }
1072 
1073 static const struct uart_ops cdns_uart_ops = {
1074         .set_mctrl      = cdns_uart_set_mctrl,
1075         .get_mctrl      = cdns_uart_get_mctrl,
1076         .start_tx       = cdns_uart_start_tx,
1077         .stop_tx        = cdns_uart_stop_tx,
1078         .stop_rx        = cdns_uart_stop_rx,
1079         .tx_empty       = cdns_uart_tx_empty,
1080         .break_ctl      = cdns_uart_break_ctl,
1081         .set_termios    = cdns_uart_set_termios,
1082         .startup        = cdns_uart_startup,
1083         .shutdown       = cdns_uart_shutdown,
1084         .pm             = cdns_uart_pm,
1085         .type           = cdns_uart_type,
1086         .verify_port    = cdns_uart_verify_port,
1087         .request_port   = cdns_uart_request_port,
1088         .release_port   = cdns_uart_release_port,
1089         .config_port    = cdns_uart_config_port,
1090 #ifdef CONFIG_CONSOLE_POLL
1091         .poll_get_char  = cdns_uart_poll_get_char,
1092         .poll_put_char  = cdns_uart_poll_put_char,
1093 #endif
1094 };
1095 
1096 static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS];
1097 
1098 /**
1099  * cdns_uart_get_port - Configure the port from platform device resource info
1100  * @id: Port id
1101  *
1102  * Return: a pointer to a uart_port or NULL for failure
1103  */
1104 static struct uart_port *cdns_uart_get_port(int id)
1105 {
1106         struct uart_port *port;
1107 
1108         /* Try the given port id if failed use default method */
1109         if (cdns_uart_port[id].mapbase != 0) {
1110                 /* Find the next unused port */
1111                 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1112                         if (cdns_uart_port[id].mapbase == 0)
1113                                 break;
1114         }
1115 
1116         if (id >= CDNS_UART_NR_PORTS)
1117                 return NULL;
1118 
1119         port = &cdns_uart_port[id];
1120 
1121         /* At this point, we've got an empty uart_port struct, initialize it */
1122         spin_lock_init(&port->lock);
1123         port->membase   = NULL;
1124         port->irq       = 0;
1125         port->type      = PORT_UNKNOWN;
1126         port->iotype    = UPIO_MEM32;
1127         port->flags     = UPF_BOOT_AUTOCONF;
1128         port->ops       = &cdns_uart_ops;
1129         port->fifosize  = CDNS_UART_FIFO_SIZE;
1130         port->line      = id;
1131         port->dev       = NULL;
1132         return port;
1133 }
1134 
1135 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1136 /**
1137  * cdns_uart_console_wait_tx - Wait for the TX to be full
1138  * @port: Handle to the uart port structure
1139  */
1140 static void cdns_uart_console_wait_tx(struct uart_port *port)
1141 {
1142         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1143                 barrier();
1144 }
1145 
1146 /**
1147  * cdns_uart_console_putchar - write the character to the FIFO buffer
1148  * @port: Handle to the uart port structure
1149  * @ch: Character to be written
1150  */
1151 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1152 {
1153         cdns_uart_console_wait_tx(port);
1154         writel(ch, port->membase + CDNS_UART_FIFO);
1155 }
1156 
1157 static void __init cdns_early_write(struct console *con, const char *s,
1158                                     unsigned n)
1159 {
1160         struct earlycon_device *dev = con->data;
1161 
1162         uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1163 }
1164 
1165 static int __init cdns_early_console_setup(struct earlycon_device *device,
1166                                            const char *opt)
1167 {
1168         struct uart_port *port = &device->port;
1169 
1170         if (!port->membase)
1171                 return -ENODEV;
1172 
1173         /* initialise control register */
1174         writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1175                port->membase + CDNS_UART_CR);
1176 
1177         /* only set baud if specified on command line - otherwise
1178          * assume it has been initialized by a boot loader.
1179          */
1180         if (device->baud) {
1181                 u32 cd = 0, bdiv = 0;
1182                 u32 mr;
1183                 int div8;
1184 
1185                 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1186                                          &bdiv, &cd, &div8);
1187                 mr = CDNS_UART_MR_PARITY_NONE;
1188                 if (div8)
1189                         mr |= CDNS_UART_MR_CLKSEL;
1190 
1191                 writel(mr,   port->membase + CDNS_UART_MR);
1192                 writel(cd,   port->membase + CDNS_UART_BAUDGEN);
1193                 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1194         }
1195 
1196         device->con->write = cdns_early_write;
1197 
1198         return 0;
1199 }
1200 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1201 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1202 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1203 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1204 
1205 /**
1206  * cdns_uart_console_write - perform write operation
1207  * @co: Console handle
1208  * @s: Pointer to character array
1209  * @count: No of characters
1210  */
1211 static void cdns_uart_console_write(struct console *co, const char *s,
1212                                 unsigned int count)
1213 {
1214         struct uart_port *port = &cdns_uart_port[co->index];
1215         unsigned long flags;
1216         unsigned int imr, ctrl;
1217         int locked = 1;
1218 
1219         if (port->sysrq)
1220                 locked = 0;
1221         else if (oops_in_progress)
1222                 locked = spin_trylock_irqsave(&port->lock, flags);
1223         else
1224                 spin_lock_irqsave(&port->lock, flags);
1225 
1226         /* save and disable interrupt */
1227         imr = readl(port->membase + CDNS_UART_IMR);
1228         writel(imr, port->membase + CDNS_UART_IDR);
1229 
1230         /*
1231          * Make sure that the tx part is enabled. Set the TX enable bit and
1232          * clear the TX disable bit to enable the transmitter.
1233          */
1234         ctrl = readl(port->membase + CDNS_UART_CR);
1235         ctrl &= ~CDNS_UART_CR_TX_DIS;
1236         ctrl |= CDNS_UART_CR_TX_EN;
1237         writel(ctrl, port->membase + CDNS_UART_CR);
1238 
1239         uart_console_write(port, s, count, cdns_uart_console_putchar);
1240         cdns_uart_console_wait_tx(port);
1241 
1242         writel(ctrl, port->membase + CDNS_UART_CR);
1243 
1244         /* restore interrupt state */
1245         writel(imr, port->membase + CDNS_UART_IER);
1246 
1247         if (locked)
1248                 spin_unlock_irqrestore(&port->lock, flags);
1249 }
1250 
1251 /**
1252  * cdns_uart_console_setup - Initialize the uart to default config
1253  * @co: Console handle
1254  * @options: Initial settings of uart
1255  *
1256  * Return: 0 on success, negative errno otherwise.
1257  */
1258 static int __init cdns_uart_console_setup(struct console *co, char *options)
1259 {
1260         struct uart_port *port = &cdns_uart_port[co->index];
1261         int baud = 9600;
1262         int bits = 8;
1263         int parity = 'n';
1264         int flow = 'n';
1265 
1266         if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1267                 return -EINVAL;
1268 
1269         if (!port->membase) {
1270                 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1271                          co->index);
1272                 return -ENODEV;
1273         }
1274 
1275         if (options)
1276                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1277 
1278         return uart_set_options(port, co, baud, parity, bits, flow);
1279 }
1280 
1281 static struct uart_driver cdns_uart_uart_driver;
1282 
1283 static struct console cdns_uart_console = {
1284         .name   = CDNS_UART_TTY_NAME,
1285         .write  = cdns_uart_console_write,
1286         .device = uart_console_device,
1287         .setup  = cdns_uart_console_setup,
1288         .flags  = CON_PRINTBUFFER,
1289         .index  = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1290         .data   = &cdns_uart_uart_driver,
1291 };
1292 
1293 /**
1294  * cdns_uart_console_init - Initialization call
1295  *
1296  * Return: 0 on success, negative errno otherwise
1297  */
1298 static int __init cdns_uart_console_init(void)
1299 {
1300         register_console(&cdns_uart_console);
1301         return 0;
1302 }
1303 
1304 console_initcall(cdns_uart_console_init);
1305 
1306 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1307 
1308 static struct uart_driver cdns_uart_uart_driver = {
1309         .owner          = THIS_MODULE,
1310         .driver_name    = CDNS_UART_NAME,
1311         .dev_name       = CDNS_UART_TTY_NAME,
1312         .major          = CDNS_UART_MAJOR,
1313         .minor          = CDNS_UART_MINOR,
1314         .nr             = CDNS_UART_NR_PORTS,
1315 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1316         .cons           = &cdns_uart_console,
1317 #endif
1318 };
1319 
1320 #ifdef CONFIG_PM_SLEEP
1321 /**
1322  * cdns_uart_suspend - suspend event
1323  * @device: Pointer to the device structure
1324  *
1325  * Return: 0
1326  */
1327 static int cdns_uart_suspend(struct device *device)
1328 {
1329         struct uart_port *port = dev_get_drvdata(device);
1330         struct tty_struct *tty;
1331         struct device *tty_dev;
1332         int may_wake = 0;
1333 
1334         /* Get the tty which could be NULL so don't assume it's valid */
1335         tty = tty_port_tty_get(&port->state->port);
1336         if (tty) {
1337                 tty_dev = tty->dev;
1338                 may_wake = device_may_wakeup(tty_dev);
1339                 tty_kref_put(tty);
1340         }
1341 
1342         /*
1343          * Call the API provided in serial_core.c file which handles
1344          * the suspend.
1345          */
1346         uart_suspend_port(&cdns_uart_uart_driver, port);
1347         if (console_suspend_enabled && !may_wake) {
1348                 struct cdns_uart *cdns_uart = port->private_data;
1349 
1350                 clk_disable(cdns_uart->uartclk);
1351                 clk_disable(cdns_uart->pclk);
1352         } else {
1353                 unsigned long flags = 0;
1354 
1355                 spin_lock_irqsave(&port->lock, flags);
1356                 /* Empty the receive FIFO 1st before making changes */
1357                 while (!(readl(port->membase + CDNS_UART_SR) &
1358                                         CDNS_UART_SR_RXEMPTY))
1359                         readl(port->membase + CDNS_UART_FIFO);
1360                 /* set RX trigger level to 1 */
1361                 writel(1, port->membase + CDNS_UART_RXWM);
1362                 /* disable RX timeout interrups */
1363                 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1364                 spin_unlock_irqrestore(&port->lock, flags);
1365         }
1366 
1367         return 0;
1368 }
1369 
1370 /**
1371  * cdns_uart_resume - Resume after a previous suspend
1372  * @device: Pointer to the device structure
1373  *
1374  * Return: 0
1375  */
1376 static int cdns_uart_resume(struct device *device)
1377 {
1378         struct uart_port *port = dev_get_drvdata(device);
1379         unsigned long flags = 0;
1380         u32 ctrl_reg;
1381         struct tty_struct *tty;
1382         struct device *tty_dev;
1383         int may_wake = 0;
1384 
1385         /* Get the tty which could be NULL so don't assume it's valid */
1386         tty = tty_port_tty_get(&port->state->port);
1387         if (tty) {
1388                 tty_dev = tty->dev;
1389                 may_wake = device_may_wakeup(tty_dev);
1390                 tty_kref_put(tty);
1391         }
1392 
1393         if (console_suspend_enabled && !may_wake) {
1394                 struct cdns_uart *cdns_uart = port->private_data;
1395 
1396                 clk_enable(cdns_uart->pclk);
1397                 clk_enable(cdns_uart->uartclk);
1398 
1399                 spin_lock_irqsave(&port->lock, flags);
1400 
1401                 /* Set TX/RX Reset */
1402                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1403                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1404                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1405                 while (readl(port->membase + CDNS_UART_CR) &
1406                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1407                         cpu_relax();
1408 
1409                 /* restore rx timeout value */
1410                 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1411                 /* Enable Tx/Rx */
1412                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1413                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1414                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1415                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1416 
1417                 spin_unlock_irqrestore(&port->lock, flags);
1418         } else {
1419                 spin_lock_irqsave(&port->lock, flags);
1420                 /* restore original rx trigger level */
1421                 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1422                 /* enable RX timeout interrupt */
1423                 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1424                 spin_unlock_irqrestore(&port->lock, flags);
1425         }
1426 
1427         return uart_resume_port(&cdns_uart_uart_driver, port);
1428 }
1429 #endif /* ! CONFIG_PM_SLEEP */
1430 
1431 static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend,
1432                 cdns_uart_resume);
1433 
1434 static const struct cdns_platform_data zynqmp_uart_def = {
1435                                 .quirks = CDNS_UART_RXBS_SUPPORT, };
1436 
1437 /* Match table for of_platform binding */
1438 static const struct of_device_id cdns_uart_of_match[] = {
1439         { .compatible = "xlnx,xuartps", },
1440         { .compatible = "cdns,uart-r1p8", },
1441         { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1442         { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1443         {}
1444 };
1445 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1446 
1447 /**
1448  * cdns_uart_probe - Platform driver probe
1449  * @pdev: Pointer to the platform device structure
1450  *
1451  * Return: 0 on success, negative errno otherwise
1452  */
1453 static int cdns_uart_probe(struct platform_device *pdev)
1454 {
1455         int rc, id, irq;
1456         struct uart_port *port;
1457         struct resource *res;
1458         struct cdns_uart *cdns_uart_data;
1459         const struct of_device_id *match;
1460 
1461         cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1462                         GFP_KERNEL);
1463         if (!cdns_uart_data)
1464                 return -ENOMEM;
1465 
1466         match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1467         if (match && match->data) {
1468                 const struct cdns_platform_data *data = match->data;
1469 
1470                 cdns_uart_data->quirks = data->quirks;
1471         }
1472 
1473         cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1474         if (IS_ERR(cdns_uart_data->pclk)) {
1475                 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1476                 if (!IS_ERR(cdns_uart_data->pclk))
1477                         dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1478         }
1479         if (IS_ERR(cdns_uart_data->pclk)) {
1480                 dev_err(&pdev->dev, "pclk clock not found.\n");
1481                 return PTR_ERR(cdns_uart_data->pclk);
1482         }
1483 
1484         cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1485         if (IS_ERR(cdns_uart_data->uartclk)) {
1486                 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1487                 if (!IS_ERR(cdns_uart_data->uartclk))
1488                         dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1489         }
1490         if (IS_ERR(cdns_uart_data->uartclk)) {
1491                 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1492                 return PTR_ERR(cdns_uart_data->uartclk);
1493         }
1494 
1495         rc = clk_prepare(cdns_uart_data->pclk);
1496         if (rc) {
1497                 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1498                 return rc;
1499         }
1500         rc = clk_prepare(cdns_uart_data->uartclk);
1501         if (rc) {
1502                 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1503                 goto err_out_clk_dis_pclk;
1504         }
1505 
1506         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1507         if (!res) {
1508                 rc = -ENODEV;
1509                 goto err_out_clk_disable;
1510         }
1511 
1512         irq = platform_get_irq(pdev, 0);
1513         if (irq <= 0) {
1514                 rc = -ENXIO;
1515                 goto err_out_clk_disable;
1516         }
1517 
1518 #ifdef CONFIG_COMMON_CLK
1519         cdns_uart_data->clk_rate_change_nb.notifier_call =
1520                         cdns_uart_clk_notifier_cb;
1521         if (clk_notifier_register(cdns_uart_data->uartclk,
1522                                 &cdns_uart_data->clk_rate_change_nb))
1523                 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1524 #endif
1525         /* Look for a serialN alias */
1526         id = of_alias_get_id(pdev->dev.of_node, "serial");
1527         if (id < 0)
1528                 id = 0;
1529 
1530         /* Initialize the port structure */
1531         port = cdns_uart_get_port(id);
1532 
1533         if (!port) {
1534                 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1535                 rc = -ENODEV;
1536                 goto err_out_notif_unreg;
1537         }
1538 
1539         /*
1540          * Register the port.
1541          * This function also registers this device with the tty layer
1542          * and triggers invocation of the config_port() entry point.
1543          */
1544         port->mapbase = res->start;
1545         port->irq = irq;
1546         port->dev = &pdev->dev;
1547         port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1548         port->private_data = cdns_uart_data;
1549         cdns_uart_data->port = port;
1550         platform_set_drvdata(pdev, port);
1551 
1552         rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1553         if (rc) {
1554                 dev_err(&pdev->dev,
1555                         "uart_add_one_port() failed; err=%i\n", rc);
1556                 goto err_out_notif_unreg;
1557         }
1558 
1559         return 0;
1560 
1561 err_out_notif_unreg:
1562 #ifdef CONFIG_COMMON_CLK
1563         clk_notifier_unregister(cdns_uart_data->uartclk,
1564                         &cdns_uart_data->clk_rate_change_nb);
1565 #endif
1566 err_out_clk_disable:
1567         clk_unprepare(cdns_uart_data->uartclk);
1568 err_out_clk_dis_pclk:
1569         clk_unprepare(cdns_uart_data->pclk);
1570 
1571         return rc;
1572 }
1573 
1574 /**
1575  * cdns_uart_remove - called when the platform driver is unregistered
1576  * @pdev: Pointer to the platform device structure
1577  *
1578  * Return: 0 on success, negative errno otherwise
1579  */
1580 static int cdns_uart_remove(struct platform_device *pdev)
1581 {
1582         struct uart_port *port = platform_get_drvdata(pdev);
1583         struct cdns_uart *cdns_uart_data = port->private_data;
1584         int rc;
1585 
1586         /* Remove the cdns_uart port from the serial core */
1587 #ifdef CONFIG_COMMON_CLK
1588         clk_notifier_unregister(cdns_uart_data->uartclk,
1589                         &cdns_uart_data->clk_rate_change_nb);
1590 #endif
1591         rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1592         port->mapbase = 0;
1593         clk_unprepare(cdns_uart_data->uartclk);
1594         clk_unprepare(cdns_uart_data->pclk);
1595         return rc;
1596 }
1597 
1598 static struct platform_driver cdns_uart_platform_driver = {
1599         .probe   = cdns_uart_probe,
1600         .remove  = cdns_uart_remove,
1601         .driver  = {
1602                 .name = CDNS_UART_NAME,
1603                 .of_match_table = cdns_uart_of_match,
1604                 .pm = &cdns_uart_dev_pm_ops,
1605                 },
1606 };
1607 
1608 static int __init cdns_uart_init(void)
1609 {
1610         int retval = 0;
1611 
1612         /* Register the cdns_uart driver with the serial core */
1613         retval = uart_register_driver(&cdns_uart_uart_driver);
1614         if (retval)
1615                 return retval;
1616 
1617         /* Register the platform driver */
1618         retval = platform_driver_register(&cdns_uart_platform_driver);
1619         if (retval)
1620                 uart_unregister_driver(&cdns_uart_uart_driver);
1621 
1622         return retval;
1623 }
1624 
1625 static void __exit cdns_uart_exit(void)
1626 {
1627         /* Unregister the platform driver */
1628         platform_driver_unregister(&cdns_uart_platform_driver);
1629 
1630         /* Unregister the cdns_uart driver */
1631         uart_unregister_driver(&cdns_uart_uart_driver);
1632 }
1633 
1634 module_init(cdns_uart_init);
1635 module_exit(cdns_uart_exit);
1636 
1637 MODULE_DESCRIPTION("Driver for Cadence UART");
1638 MODULE_AUTHOR("Xilinx Inc.");
1639 MODULE_LICENSE("GPL");
1640 

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