Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/tty/serial/xilinx_uartps.c

  1 /*
  2  * Cadence UART driver (found in Xilinx Zynq)
  3  *
  4  * 2011 - 2014 (C) Xilinx Inc.
  5  *
  6  * This program is free software; you can redistribute it
  7  * and/or modify it under the terms of the GNU General Public
  8  * License as published by the Free Software Foundation;
  9  * either version 2 of the License, or (at your option) any
 10  * later version.
 11  *
 12  * This driver has originally been pushed by Xilinx using a Zynq-branding. This
 13  * still shows in the naming of this file, the kconfig symbols and some symbols
 14  * in the code.
 15  */
 16 
 17 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 18 #define SUPPORT_SYSRQ
 19 #endif
 20 
 21 #include <linux/platform_device.h>
 22 #include <linux/serial.h>
 23 #include <linux/console.h>
 24 #include <linux/serial_core.h>
 25 #include <linux/slab.h>
 26 #include <linux/tty.h>
 27 #include <linux/tty_flip.h>
 28 #include <linux/clk.h>
 29 #include <linux/irq.h>
 30 #include <linux/io.h>
 31 #include <linux/of.h>
 32 #include <linux/module.h>
 33 
 34 #define CDNS_UART_TTY_NAME      "ttyPS"
 35 #define CDNS_UART_NAME          "xuartps"
 36 #define CDNS_UART_MAJOR         0       /* use dynamic node allocation */
 37 #define CDNS_UART_MINOR         0       /* works best with devtmpfs */
 38 #define CDNS_UART_NR_PORTS      2
 39 #define CDNS_UART_FIFO_SIZE     64      /* FIFO size */
 40 #define CDNS_UART_REGISTER_SPACE        0xFFF
 41 
 42 #define cdns_uart_readl(offset)         ioread32(port->membase + offset)
 43 #define cdns_uart_writel(val, offset)   iowrite32(val, port->membase + offset)
 44 
 45 /* Rx Trigger level */
 46 static int rx_trigger_level = 56;
 47 module_param(rx_trigger_level, uint, S_IRUGO);
 48 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
 49 
 50 /* Rx Timeout */
 51 static int rx_timeout = 10;
 52 module_param(rx_timeout, uint, S_IRUGO);
 53 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
 54 
 55 /* Register offsets for the UART. */
 56 #define CDNS_UART_CR_OFFSET             0x00  /* Control Register */
 57 #define CDNS_UART_MR_OFFSET             0x04  /* Mode Register */
 58 #define CDNS_UART_IER_OFFSET            0x08  /* Interrupt Enable */
 59 #define CDNS_UART_IDR_OFFSET            0x0C  /* Interrupt Disable */
 60 #define CDNS_UART_IMR_OFFSET            0x10  /* Interrupt Mask */
 61 #define CDNS_UART_ISR_OFFSET            0x14  /* Interrupt Status */
 62 #define CDNS_UART_BAUDGEN_OFFSET        0x18  /* Baud Rate Generator */
 63 #define CDNS_UART_RXTOUT_OFFSET         0x1C  /* RX Timeout */
 64 #define CDNS_UART_RXWM_OFFSET           0x20  /* RX FIFO Trigger Level */
 65 #define CDNS_UART_MODEMCR_OFFSET        0x24  /* Modem Control */
 66 #define CDNS_UART_MODEMSR_OFFSET        0x28  /* Modem Status */
 67 #define CDNS_UART_SR_OFFSET             0x2C  /* Channel Status */
 68 #define CDNS_UART_FIFO_OFFSET           0x30  /* FIFO */
 69 #define CDNS_UART_BAUDDIV_OFFSET        0x34  /* Baud Rate Divider */
 70 #define CDNS_UART_FLOWDEL_OFFSET        0x38  /* Flow Delay */
 71 #define CDNS_UART_IRRX_PWIDTH_OFFSET    0x3C  /* IR Min Received Pulse Width */
 72 #define CDNS_UART_IRTX_PWIDTH_OFFSET    0x40  /* IR Transmitted pulse Width */
 73 #define CDNS_UART_TXWM_OFFSET           0x44  /* TX FIFO Trigger Level */
 74 
 75 /* Control Register Bit Definitions */
 76 #define CDNS_UART_CR_STOPBRK    0x00000100  /* Stop TX break */
 77 #define CDNS_UART_CR_STARTBRK   0x00000080  /* Set TX break */
 78 #define CDNS_UART_CR_TX_DIS     0x00000020  /* TX disabled. */
 79 #define CDNS_UART_CR_TX_EN      0x00000010  /* TX enabled */
 80 #define CDNS_UART_CR_RX_DIS     0x00000008  /* RX disabled. */
 81 #define CDNS_UART_CR_RX_EN      0x00000004  /* RX enabled */
 82 #define CDNS_UART_CR_TXRST      0x00000002  /* TX logic reset */
 83 #define CDNS_UART_CR_RXRST      0x00000001  /* RX logic reset */
 84 #define CDNS_UART_CR_RST_TO     0x00000040  /* Restart Timeout Counter */
 85 
 86 /*
 87  * Mode Register:
 88  * The mode register (MR) defines the mode of transfer as well as the data
 89  * format. If this register is modified during transmission or reception,
 90  * data validity cannot be guaranteed.
 91  */
 92 #define CDNS_UART_MR_CLKSEL             0x00000001  /* Pre-scalar selection */
 93 #define CDNS_UART_MR_CHMODE_L_LOOP      0x00000200  /* Local loop back mode */
 94 #define CDNS_UART_MR_CHMODE_NORM        0x00000000  /* Normal mode */
 95 
 96 #define CDNS_UART_MR_STOPMODE_2_BIT     0x00000080  /* 2 stop bits */
 97 #define CDNS_UART_MR_STOPMODE_1_BIT     0x00000000  /* 1 stop bit */
 98 
 99 #define CDNS_UART_MR_PARITY_NONE        0x00000020  /* No parity mode */
100 #define CDNS_UART_MR_PARITY_MARK        0x00000018  /* Mark parity mode */
101 #define CDNS_UART_MR_PARITY_SPACE       0x00000010  /* Space parity mode */
102 #define CDNS_UART_MR_PARITY_ODD         0x00000008  /* Odd parity mode */
103 #define CDNS_UART_MR_PARITY_EVEN        0x00000000  /* Even parity mode */
104 
105 #define CDNS_UART_MR_CHARLEN_6_BIT      0x00000006  /* 6 bits data */
106 #define CDNS_UART_MR_CHARLEN_7_BIT      0x00000004  /* 7 bits data */
107 #define CDNS_UART_MR_CHARLEN_8_BIT      0x00000000  /* 8 bits data */
108 
109 /*
110  * Interrupt Registers:
111  * Interrupt control logic uses the interrupt enable register (IER) and the
112  * interrupt disable register (IDR) to set the value of the bits in the
113  * interrupt mask register (IMR). The IMR determines whether to pass an
114  * interrupt to the interrupt status register (ISR).
115  * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
116  * interrupt. IMR and ISR are read only, and IER and IDR are write only.
117  * Reading either IER or IDR returns 0x00.
118  * All four registers have the same bit definitions.
119  */
120 #define CDNS_UART_IXR_TOUT      0x00000100 /* RX Timeout error interrupt */
121 #define CDNS_UART_IXR_PARITY    0x00000080 /* Parity error interrupt */
122 #define CDNS_UART_IXR_FRAMING   0x00000040 /* Framing error interrupt */
123 #define CDNS_UART_IXR_OVERRUN   0x00000020 /* Overrun error interrupt */
124 #define CDNS_UART_IXR_TXFULL    0x00000010 /* TX FIFO Full interrupt */
125 #define CDNS_UART_IXR_TXEMPTY   0x00000008 /* TX FIFO empty interrupt */
126 #define CDNS_UART_ISR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt */
127 #define CDNS_UART_IXR_RXTRIG    0x00000001 /* RX FIFO trigger interrupt */
128 #define CDNS_UART_IXR_RXFULL    0x00000004 /* RX FIFO full interrupt. */
129 #define CDNS_UART_IXR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt. */
130 #define CDNS_UART_IXR_MASK      0x00001FFF /* Valid bit mask */
131 
132 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
133 #define CDNS_UART_IXR_BRK       0x80000000
134 
135 /*
136  * Channel Status Register:
137  * The channel status register (CSR) is provided to enable the control logic
138  * to monitor the status of bits in the channel interrupt status register,
139  * even if these are masked out by the interrupt mask register.
140  */
141 #define CDNS_UART_SR_RXEMPTY    0x00000002 /* RX FIFO empty */
142 #define CDNS_UART_SR_TXEMPTY    0x00000008 /* TX FIFO empty */
143 #define CDNS_UART_SR_TXFULL     0x00000010 /* TX FIFO full */
144 #define CDNS_UART_SR_RXTRIG     0x00000001 /* Rx Trigger */
145 
146 /* baud dividers min/max values */
147 #define CDNS_UART_BDIV_MIN      4
148 #define CDNS_UART_BDIV_MAX      255
149 #define CDNS_UART_CD_MAX        65535
150 
151 /**
152  * struct cdns_uart - device data
153  * @port:               Pointer to the UART port
154  * @uartclk:            Reference clock
155  * @pclk:               APB clock
156  * @baud:               Current baud rate
157  * @clk_rate_change_nb: Notifier block for clock changes
158  */
159 struct cdns_uart {
160         struct uart_port        *port;
161         struct clk              *uartclk;
162         struct clk              *pclk;
163         unsigned int            baud;
164         struct notifier_block   clk_rate_change_nb;
165 };
166 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
167                 clk_rate_change_nb);
168 
169 /**
170  * cdns_uart_isr - Interrupt handler
171  * @irq: Irq number
172  * @dev_id: Id of the port
173  *
174  * Return: IRQHANDLED
175  */
176 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
177 {
178         struct uart_port *port = (struct uart_port *)dev_id;
179         unsigned long flags;
180         unsigned int isrstatus, numbytes;
181         unsigned int data;
182         char status = TTY_NORMAL;
183 
184         spin_lock_irqsave(&port->lock, flags);
185 
186         /* Read the interrupt status register to determine which
187          * interrupt(s) is/are active.
188          */
189         isrstatus = cdns_uart_readl(CDNS_UART_ISR_OFFSET);
190 
191         /*
192          * There is no hardware break detection, so we interpret framing
193          * error with all-zeros data as a break sequence. Most of the time,
194          * there's another non-zero byte at the end of the sequence.
195          */
196         if (isrstatus & CDNS_UART_IXR_FRAMING) {
197                 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) &
198                                         CDNS_UART_SR_RXEMPTY)) {
199                         if (!cdns_uart_readl(CDNS_UART_FIFO_OFFSET)) {
200                                 port->read_status_mask |= CDNS_UART_IXR_BRK;
201                                 isrstatus &= ~CDNS_UART_IXR_FRAMING;
202                         }
203                 }
204                 cdns_uart_writel(CDNS_UART_IXR_FRAMING, CDNS_UART_ISR_OFFSET);
205         }
206 
207         /* drop byte with parity error if IGNPAR specified */
208         if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY)
209                 isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT);
210 
211         isrstatus &= port->read_status_mask;
212         isrstatus &= ~port->ignore_status_mask;
213 
214         if ((isrstatus & CDNS_UART_IXR_TOUT) ||
215                 (isrstatus & CDNS_UART_IXR_RXTRIG)) {
216                 /* Receive Timeout Interrupt */
217                 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
218                         CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
219                         data = cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
220 
221                         /* Non-NULL byte after BREAK is garbage (99%) */
222                         if (data && (port->read_status_mask &
223                                                 CDNS_UART_IXR_BRK)) {
224                                 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
225                                 port->icount.brk++;
226                                 if (uart_handle_break(port))
227                                         continue;
228                         }
229 
230 #ifdef SUPPORT_SYSRQ
231                         /*
232                          * uart_handle_sysrq_char() doesn't work if
233                          * spinlocked, for some reason
234                          */
235                          if (port->sysrq) {
236                                 spin_unlock(&port->lock);
237                                 if (uart_handle_sysrq_char(port,
238                                                         (unsigned char)data)) {
239                                         spin_lock(&port->lock);
240                                         continue;
241                                 }
242                                 spin_lock(&port->lock);
243                         }
244 #endif
245 
246                         port->icount.rx++;
247 
248                         if (isrstatus & CDNS_UART_IXR_PARITY) {
249                                 port->icount.parity++;
250                                 status = TTY_PARITY;
251                         } else if (isrstatus & CDNS_UART_IXR_FRAMING) {
252                                 port->icount.frame++;
253                                 status = TTY_FRAME;
254                         } else if (isrstatus & CDNS_UART_IXR_OVERRUN) {
255                                 port->icount.overrun++;
256                         }
257 
258                         uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN,
259                                         data, status);
260                 }
261                 spin_unlock(&port->lock);
262                 tty_flip_buffer_push(&port->state->port);
263                 spin_lock(&port->lock);
264         }
265 
266         /* Dispatch an appropriate handler */
267         if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY) {
268                 if (uart_circ_empty(&port->state->xmit)) {
269                         cdns_uart_writel(CDNS_UART_IXR_TXEMPTY,
270                                                 CDNS_UART_IDR_OFFSET);
271                 } else {
272                         numbytes = port->fifosize;
273                         /* Break if no more data available in the UART buffer */
274                         while (numbytes--) {
275                                 if (uart_circ_empty(&port->state->xmit))
276                                         break;
277                                 /* Get the data from the UART circular buffer
278                                  * and write it to the cdns_uart's TX_FIFO
279                                  * register.
280                                  */
281                                 cdns_uart_writel(
282                                         port->state->xmit.buf[port->state->xmit.
283                                         tail], CDNS_UART_FIFO_OFFSET);
284 
285                                 port->icount.tx++;
286 
287                                 /* Adjust the tail of the UART buffer and wrap
288                                  * the buffer if it reaches limit.
289                                  */
290                                 port->state->xmit.tail =
291                                         (port->state->xmit.tail + 1) &
292                                                 (UART_XMIT_SIZE - 1);
293                         }
294 
295                         if (uart_circ_chars_pending(
296                                         &port->state->xmit) < WAKEUP_CHARS)
297                                 uart_write_wakeup(port);
298                 }
299         }
300 
301         cdns_uart_writel(isrstatus, CDNS_UART_ISR_OFFSET);
302 
303         /* be sure to release the lock and tty before leaving */
304         spin_unlock_irqrestore(&port->lock, flags);
305 
306         return IRQ_HANDLED;
307 }
308 
309 /**
310  * cdns_uart_calc_baud_divs - Calculate baud rate divisors
311  * @clk: UART module input clock
312  * @baud: Desired baud rate
313  * @rbdiv: BDIV value (return value)
314  * @rcd: CD value (return value)
315  * @div8: Value for clk_sel bit in mod (return value)
316  * Return: baud rate, requested baud when possible, or actual baud when there
317  *      was too much error, zero if no valid divisors are found.
318  *
319  * Formula to obtain baud rate is
320  *      baud_tx/rx rate = clk/CD * (BDIV + 1)
321  *      input_clk = (Uart User Defined Clock or Apb Clock)
322  *              depends on UCLKEN in MR Reg
323  *      clk = input_clk or input_clk/8;
324  *              depends on CLKS in MR reg
325  *      CD and BDIV depends on values in
326  *                      baud rate generate register
327  *                      baud rate clock divisor register
328  */
329 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
330                 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
331 {
332         u32 cd, bdiv;
333         unsigned int calc_baud;
334         unsigned int bestbaud = 0;
335         unsigned int bauderror;
336         unsigned int besterror = ~0;
337 
338         if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
339                 *div8 = 1;
340                 clk /= 8;
341         } else {
342                 *div8 = 0;
343         }
344 
345         for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
346                 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
347                 if (cd < 1 || cd > CDNS_UART_CD_MAX)
348                         continue;
349 
350                 calc_baud = clk / (cd * (bdiv + 1));
351 
352                 if (baud > calc_baud)
353                         bauderror = baud - calc_baud;
354                 else
355                         bauderror = calc_baud - baud;
356 
357                 if (besterror > bauderror) {
358                         *rbdiv = bdiv;
359                         *rcd = cd;
360                         bestbaud = calc_baud;
361                         besterror = bauderror;
362                 }
363         }
364         /* use the values when percent error is acceptable */
365         if (((besterror * 100) / baud) < 3)
366                 bestbaud = baud;
367 
368         return bestbaud;
369 }
370 
371 /**
372  * cdns_uart_set_baud_rate - Calculate and set the baud rate
373  * @port: Handle to the uart port structure
374  * @baud: Baud rate to set
375  * Return: baud rate, requested baud when possible, or actual baud when there
376  *         was too much error, zero if no valid divisors are found.
377  */
378 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
379                 unsigned int baud)
380 {
381         unsigned int calc_baud;
382         u32 cd = 0, bdiv = 0;
383         u32 mreg;
384         int div8;
385         struct cdns_uart *cdns_uart = port->private_data;
386 
387         calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
388                         &div8);
389 
390         /* Write new divisors to hardware */
391         mreg = cdns_uart_readl(CDNS_UART_MR_OFFSET);
392         if (div8)
393                 mreg |= CDNS_UART_MR_CLKSEL;
394         else
395                 mreg &= ~CDNS_UART_MR_CLKSEL;
396         cdns_uart_writel(mreg, CDNS_UART_MR_OFFSET);
397         cdns_uart_writel(cd, CDNS_UART_BAUDGEN_OFFSET);
398         cdns_uart_writel(bdiv, CDNS_UART_BAUDDIV_OFFSET);
399         cdns_uart->baud = baud;
400 
401         return calc_baud;
402 }
403 
404 #ifdef CONFIG_COMMON_CLK
405 /**
406  * cdns_uart_clk_notitifer_cb - Clock notifier callback
407  * @nb:         Notifier block
408  * @event:      Notify event
409  * @data:       Notifier data
410  * Return:      NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
411  */
412 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
413                 unsigned long event, void *data)
414 {
415         u32 ctrl_reg;
416         struct uart_port *port;
417         int locked = 0;
418         struct clk_notifier_data *ndata = data;
419         unsigned long flags = 0;
420         struct cdns_uart *cdns_uart = to_cdns_uart(nb);
421 
422         port = cdns_uart->port;
423         if (port->suspended)
424                 return NOTIFY_OK;
425 
426         switch (event) {
427         case PRE_RATE_CHANGE:
428         {
429                 u32 bdiv, cd;
430                 int div8;
431 
432                 /*
433                  * Find out if current baud-rate can be achieved with new clock
434                  * frequency.
435                  */
436                 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
437                                         &bdiv, &cd, &div8)) {
438                         dev_warn(port->dev, "clock rate change rejected\n");
439                         return NOTIFY_BAD;
440                 }
441 
442                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
443 
444                 /* Disable the TX and RX to set baud rate */
445                 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
446                 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
447                 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
448 
449                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
450 
451                 return NOTIFY_OK;
452         }
453         case POST_RATE_CHANGE:
454                 /*
455                  * Set clk dividers to generate correct baud with new clock
456                  * frequency.
457                  */
458 
459                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
460 
461                 locked = 1;
462                 port->uartclk = ndata->new_rate;
463 
464                 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
465                                 cdns_uart->baud);
466                 /* fall through */
467         case ABORT_RATE_CHANGE:
468                 if (!locked)
469                         spin_lock_irqsave(&cdns_uart->port->lock, flags);
470 
471                 /* Set TX/RX Reset */
472                 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
473                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
474                 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
475 
476                 while (cdns_uart_readl(CDNS_UART_CR_OFFSET) &
477                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
478                         cpu_relax();
479 
480                 /*
481                  * Clear the RX disable and TX disable bits and then set the TX
482                  * enable bit and RX enable bit to enable the transmitter and
483                  * receiver.
484                  */
485                 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
486                 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
487                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
488                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
489                 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
490 
491                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
492 
493                 return NOTIFY_OK;
494         default:
495                 return NOTIFY_DONE;
496         }
497 }
498 #endif
499 
500 /**
501  * cdns_uart_start_tx -  Start transmitting bytes
502  * @port: Handle to the uart port structure
503  */
504 static void cdns_uart_start_tx(struct uart_port *port)
505 {
506         unsigned int status, numbytes = port->fifosize;
507 
508         if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
509                 return;
510 
511         status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
512         /* Set the TX enable bit and clear the TX disable bit to enable the
513          * transmitter.
514          */
515         cdns_uart_writel((status & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN,
516                 CDNS_UART_CR_OFFSET);
517 
518         while (numbytes-- && ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
519                                 CDNS_UART_SR_TXFULL)) != CDNS_UART_SR_TXFULL) {
520                 /* Break if no more data available in the UART buffer */
521                 if (uart_circ_empty(&port->state->xmit))
522                         break;
523 
524                 /* Get the data from the UART circular buffer and
525                  * write it to the cdns_uart's TX_FIFO register.
526                  */
527                 cdns_uart_writel(
528                         port->state->xmit.buf[port->state->xmit.tail],
529                         CDNS_UART_FIFO_OFFSET);
530                 port->icount.tx++;
531 
532                 /* Adjust the tail of the UART buffer and wrap
533                  * the buffer if it reaches limit.
534                  */
535                 port->state->xmit.tail = (port->state->xmit.tail + 1) &
536                                         (UART_XMIT_SIZE - 1);
537         }
538         cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_ISR_OFFSET);
539         /* Enable the TX Empty interrupt */
540         cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_IER_OFFSET);
541 
542         if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
543                 uart_write_wakeup(port);
544 }
545 
546 /**
547  * cdns_uart_stop_tx - Stop TX
548  * @port: Handle to the uart port structure
549  */
550 static void cdns_uart_stop_tx(struct uart_port *port)
551 {
552         unsigned int regval;
553 
554         regval = cdns_uart_readl(CDNS_UART_CR_OFFSET);
555         regval |= CDNS_UART_CR_TX_DIS;
556         /* Disable the transmitter */
557         cdns_uart_writel(regval, CDNS_UART_CR_OFFSET);
558 }
559 
560 /**
561  * cdns_uart_stop_rx - Stop RX
562  * @port: Handle to the uart port structure
563  */
564 static void cdns_uart_stop_rx(struct uart_port *port)
565 {
566         unsigned int regval;
567 
568         regval = cdns_uart_readl(CDNS_UART_CR_OFFSET);
569         regval |= CDNS_UART_CR_RX_DIS;
570         /* Disable the receiver */
571         cdns_uart_writel(regval, CDNS_UART_CR_OFFSET);
572 }
573 
574 /**
575  * cdns_uart_tx_empty -  Check whether TX is empty
576  * @port: Handle to the uart port structure
577  *
578  * Return: TIOCSER_TEMT on success, 0 otherwise
579  */
580 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
581 {
582         unsigned int status;
583 
584         status = cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY;
585         return status ? TIOCSER_TEMT : 0;
586 }
587 
588 /**
589  * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
590  *                      transmitting char breaks
591  * @port: Handle to the uart port structure
592  * @ctl: Value based on which start or stop decision is taken
593  */
594 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
595 {
596         unsigned int status;
597         unsigned long flags;
598 
599         spin_lock_irqsave(&port->lock, flags);
600 
601         status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
602 
603         if (ctl == -1)
604                 cdns_uart_writel(CDNS_UART_CR_STARTBRK | status,
605                                         CDNS_UART_CR_OFFSET);
606         else {
607                 if ((status & CDNS_UART_CR_STOPBRK) == 0)
608                         cdns_uart_writel(CDNS_UART_CR_STOPBRK | status,
609                                          CDNS_UART_CR_OFFSET);
610         }
611         spin_unlock_irqrestore(&port->lock, flags);
612 }
613 
614 /**
615  * cdns_uart_set_termios - termios operations, handling data length, parity,
616  *                              stop bits, flow control, baud rate
617  * @port: Handle to the uart port structure
618  * @termios: Handle to the input termios structure
619  * @old: Values of the previously saved termios structure
620  */
621 static void cdns_uart_set_termios(struct uart_port *port,
622                                 struct ktermios *termios, struct ktermios *old)
623 {
624         unsigned int cval = 0;
625         unsigned int baud, minbaud, maxbaud;
626         unsigned long flags;
627         unsigned int ctrl_reg, mode_reg;
628 
629         spin_lock_irqsave(&port->lock, flags);
630 
631         /* Empty the receive FIFO 1st before making changes */
632         while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
633                  CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
634                 cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
635         }
636 
637         /* Disable the TX and RX to set baud rate */
638         ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
639         ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
640         cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
641 
642         /*
643          * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
644          * min and max baud should be calculated here based on port->uartclk.
645          * this way we get a valid baud and can safely call set_baud()
646          */
647         minbaud = port->uartclk /
648                         ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
649         maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
650         baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
651         baud = cdns_uart_set_baud_rate(port, baud);
652         if (tty_termios_baud_rate(termios))
653                 tty_termios_encode_baud_rate(termios, baud, baud);
654 
655         /* Update the per-port timeout. */
656         uart_update_timeout(port, termios->c_cflag, baud);
657 
658         /* Set TX/RX Reset */
659         ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
660         ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
661         cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
662 
663         /*
664          * Clear the RX disable and TX disable bits and then set the TX enable
665          * bit and RX enable bit to enable the transmitter and receiver.
666          */
667         ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
668         ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
669         ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
670         cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
671 
672         cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
673 
674         port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
675                         CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
676         port->ignore_status_mask = 0;
677 
678         if (termios->c_iflag & INPCK)
679                 port->read_status_mask |= CDNS_UART_IXR_PARITY |
680                 CDNS_UART_IXR_FRAMING;
681 
682         if (termios->c_iflag & IGNPAR)
683                 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
684                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
685 
686         /* ignore all characters if CREAD is not set */
687         if ((termios->c_cflag & CREAD) == 0)
688                 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
689                         CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
690                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
691 
692         mode_reg = cdns_uart_readl(CDNS_UART_MR_OFFSET);
693 
694         /* Handling Data Size */
695         switch (termios->c_cflag & CSIZE) {
696         case CS6:
697                 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
698                 break;
699         case CS7:
700                 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
701                 break;
702         default:
703         case CS8:
704                 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
705                 termios->c_cflag &= ~CSIZE;
706                 termios->c_cflag |= CS8;
707                 break;
708         }
709 
710         /* Handling Parity and Stop Bits length */
711         if (termios->c_cflag & CSTOPB)
712                 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
713         else
714                 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
715 
716         if (termios->c_cflag & PARENB) {
717                 /* Mark or Space parity */
718                 if (termios->c_cflag & CMSPAR) {
719                         if (termios->c_cflag & PARODD)
720                                 cval |= CDNS_UART_MR_PARITY_MARK;
721                         else
722                                 cval |= CDNS_UART_MR_PARITY_SPACE;
723                 } else {
724                         if (termios->c_cflag & PARODD)
725                                 cval |= CDNS_UART_MR_PARITY_ODD;
726                         else
727                                 cval |= CDNS_UART_MR_PARITY_EVEN;
728                 }
729         } else {
730                 cval |= CDNS_UART_MR_PARITY_NONE;
731         }
732         cval |= mode_reg & 1;
733         cdns_uart_writel(cval, CDNS_UART_MR_OFFSET);
734 
735         spin_unlock_irqrestore(&port->lock, flags);
736 }
737 
738 /**
739  * cdns_uart_startup - Called when an application opens a cdns_uart port
740  * @port: Handle to the uart port structure
741  *
742  * Return: 0 on success, negative errno otherwise
743  */
744 static int cdns_uart_startup(struct uart_port *port)
745 {
746         unsigned int retval = 0, status = 0;
747 
748         retval = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME,
749                                                                 (void *)port);
750         if (retval)
751                 return retval;
752 
753         /* Disable the TX and RX */
754         cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
755                                                 CDNS_UART_CR_OFFSET);
756 
757         /* Set the Control Register with TX/RX Enable, TX/RX Reset,
758          * no break chars.
759          */
760         cdns_uart_writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
761                                 CDNS_UART_CR_OFFSET);
762 
763         status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
764 
765         /* Clear the RX disable and TX disable bits and then set the TX enable
766          * bit and RX enable bit to enable the transmitter and receiver.
767          */
768         cdns_uart_writel((status & ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS))
769                         | (CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN |
770                         CDNS_UART_CR_STOPBRK), CDNS_UART_CR_OFFSET);
771 
772         /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
773          * no parity.
774          */
775         cdns_uart_writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
776                 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
777                  CDNS_UART_MR_OFFSET);
778 
779         /*
780          * Set the RX FIFO Trigger level to use most of the FIFO, but it
781          * can be tuned with a module parameter
782          */
783         cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET);
784 
785         /*
786          * Receive Timeout register is enabled but it
787          * can be tuned with a module parameter
788          */
789         cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
790 
791         /* Clear out any pending interrupts before enabling them */
792         cdns_uart_writel(cdns_uart_readl(CDNS_UART_ISR_OFFSET),
793                         CDNS_UART_ISR_OFFSET);
794 
795         /* Set the Interrupt Registers with desired interrupts */
796         cdns_uart_writel(CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_PARITY |
797                 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN |
798                 CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT,
799                 CDNS_UART_IER_OFFSET);
800 
801         return retval;
802 }
803 
804 /**
805  * cdns_uart_shutdown - Called when an application closes a cdns_uart port
806  * @port: Handle to the uart port structure
807  */
808 static void cdns_uart_shutdown(struct uart_port *port)
809 {
810         int status;
811 
812         /* Disable interrupts */
813         status = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
814         cdns_uart_writel(status, CDNS_UART_IDR_OFFSET);
815 
816         /* Disable the TX and RX */
817         cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
818                                  CDNS_UART_CR_OFFSET);
819         free_irq(port->irq, port);
820 }
821 
822 /**
823  * cdns_uart_type - Set UART type to cdns_uart port
824  * @port: Handle to the uart port structure
825  *
826  * Return: string on success, NULL otherwise
827  */
828 static const char *cdns_uart_type(struct uart_port *port)
829 {
830         return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
831 }
832 
833 /**
834  * cdns_uart_verify_port - Verify the port params
835  * @port: Handle to the uart port structure
836  * @ser: Handle to the structure whose members are compared
837  *
838  * Return: 0 on success, negative errno otherwise.
839  */
840 static int cdns_uart_verify_port(struct uart_port *port,
841                                         struct serial_struct *ser)
842 {
843         if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
844                 return -EINVAL;
845         if (port->irq != ser->irq)
846                 return -EINVAL;
847         if (ser->io_type != UPIO_MEM)
848                 return -EINVAL;
849         if (port->iobase != ser->port)
850                 return -EINVAL;
851         if (ser->hub6 != 0)
852                 return -EINVAL;
853         return 0;
854 }
855 
856 /**
857  * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
858  *                              called when the driver adds a cdns_uart port via
859  *                              uart_add_one_port()
860  * @port: Handle to the uart port structure
861  *
862  * Return: 0 on success, negative errno otherwise.
863  */
864 static int cdns_uart_request_port(struct uart_port *port)
865 {
866         if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
867                                          CDNS_UART_NAME)) {
868                 return -ENOMEM;
869         }
870 
871         port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
872         if (!port->membase) {
873                 dev_err(port->dev, "Unable to map registers\n");
874                 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
875                 return -ENOMEM;
876         }
877         return 0;
878 }
879 
880 /**
881  * cdns_uart_release_port - Release UART port
882  * @port: Handle to the uart port structure
883  *
884  * Release the memory region attached to a cdns_uart port. Called when the
885  * driver removes a cdns_uart port via uart_remove_one_port().
886  */
887 static void cdns_uart_release_port(struct uart_port *port)
888 {
889         release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
890         iounmap(port->membase);
891         port->membase = NULL;
892 }
893 
894 /**
895  * cdns_uart_config_port - Configure UART port
896  * @port: Handle to the uart port structure
897  * @flags: If any
898  */
899 static void cdns_uart_config_port(struct uart_port *port, int flags)
900 {
901         if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
902                 port->type = PORT_XUARTPS;
903 }
904 
905 /**
906  * cdns_uart_get_mctrl - Get the modem control state
907  * @port: Handle to the uart port structure
908  *
909  * Return: the modem control state
910  */
911 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
912 {
913         return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
914 }
915 
916 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
917 {
918         /* N/A */
919 }
920 
921 #ifdef CONFIG_CONSOLE_POLL
922 static int cdns_uart_poll_get_char(struct uart_port *port)
923 {
924         u32 imr;
925         int c;
926 
927         /* Disable all interrupts */
928         imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
929         cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
930 
931         /* Check if FIFO is empty */
932         if (cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY)
933                 c = NO_POLL_CHAR;
934         else /* Read a character */
935                 c = (unsigned char) cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
936 
937         /* Enable interrupts */
938         cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
939 
940         return c;
941 }
942 
943 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
944 {
945         u32 imr;
946 
947         /* Disable all interrupts */
948         imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
949         cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
950 
951         /* Wait until FIFO is empty */
952         while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY))
953                 cpu_relax();
954 
955         /* Write a character */
956         cdns_uart_writel(c, CDNS_UART_FIFO_OFFSET);
957 
958         /* Wait until FIFO is empty */
959         while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY))
960                 cpu_relax();
961 
962         /* Enable interrupts */
963         cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
964 
965         return;
966 }
967 #endif
968 
969 static struct uart_ops cdns_uart_ops = {
970         .set_mctrl      = cdns_uart_set_mctrl,
971         .get_mctrl      = cdns_uart_get_mctrl,
972         .start_tx       = cdns_uart_start_tx,
973         .stop_tx        = cdns_uart_stop_tx,
974         .stop_rx        = cdns_uart_stop_rx,
975         .tx_empty       = cdns_uart_tx_empty,
976         .break_ctl      = cdns_uart_break_ctl,
977         .set_termios    = cdns_uart_set_termios,
978         .startup        = cdns_uart_startup,
979         .shutdown       = cdns_uart_shutdown,
980         .type           = cdns_uart_type,
981         .verify_port    = cdns_uart_verify_port,
982         .request_port   = cdns_uart_request_port,
983         .release_port   = cdns_uart_release_port,
984         .config_port    = cdns_uart_config_port,
985 #ifdef CONFIG_CONSOLE_POLL
986         .poll_get_char  = cdns_uart_poll_get_char,
987         .poll_put_char  = cdns_uart_poll_put_char,
988 #endif
989 };
990 
991 static struct uart_port cdns_uart_port[2];
992 
993 /**
994  * cdns_uart_get_port - Configure the port from platform device resource info
995  * @id: Port id
996  *
997  * Return: a pointer to a uart_port or NULL for failure
998  */
999 static struct uart_port *cdns_uart_get_port(int id)
1000 {
1001         struct uart_port *port;
1002 
1003         /* Try the given port id if failed use default method */
1004         if (cdns_uart_port[id].mapbase != 0) {
1005                 /* Find the next unused port */
1006                 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1007                         if (cdns_uart_port[id].mapbase == 0)
1008                                 break;
1009         }
1010 
1011         if (id >= CDNS_UART_NR_PORTS)
1012                 return NULL;
1013 
1014         port = &cdns_uart_port[id];
1015 
1016         /* At this point, we've got an empty uart_port struct, initialize it */
1017         spin_lock_init(&port->lock);
1018         port->membase   = NULL;
1019         port->iobase    = 1; /* mark port in use */
1020         port->irq       = 0;
1021         port->type      = PORT_UNKNOWN;
1022         port->iotype    = UPIO_MEM32;
1023         port->flags     = UPF_BOOT_AUTOCONF;
1024         port->ops       = &cdns_uart_ops;
1025         port->fifosize  = CDNS_UART_FIFO_SIZE;
1026         port->line      = id;
1027         port->dev       = NULL;
1028         return port;
1029 }
1030 
1031 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1032 /**
1033  * cdns_uart_console_wait_tx - Wait for the TX to be full
1034  * @port: Handle to the uart port structure
1035  */
1036 static void cdns_uart_console_wait_tx(struct uart_port *port)
1037 {
1038         while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY)
1039                                 != CDNS_UART_SR_TXEMPTY)
1040                 barrier();
1041 }
1042 
1043 /**
1044  * cdns_uart_console_putchar - write the character to the FIFO buffer
1045  * @port: Handle to the uart port structure
1046  * @ch: Character to be written
1047  */
1048 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1049 {
1050         cdns_uart_console_wait_tx(port);
1051         cdns_uart_writel(ch, CDNS_UART_FIFO_OFFSET);
1052 }
1053 
1054 /**
1055  * cdns_uart_console_write - perform write operation
1056  * @co: Console handle
1057  * @s: Pointer to character array
1058  * @count: No of characters
1059  */
1060 static void cdns_uart_console_write(struct console *co, const char *s,
1061                                 unsigned int count)
1062 {
1063         struct uart_port *port = &cdns_uart_port[co->index];
1064         unsigned long flags;
1065         unsigned int imr, ctrl;
1066         int locked = 1;
1067 
1068         if (oops_in_progress)
1069                 locked = spin_trylock_irqsave(&port->lock, flags);
1070         else
1071                 spin_lock_irqsave(&port->lock, flags);
1072 
1073         /* save and disable interrupt */
1074         imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
1075         cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
1076 
1077         /*
1078          * Make sure that the tx part is enabled. Set the TX enable bit and
1079          * clear the TX disable bit to enable the transmitter.
1080          */
1081         ctrl = cdns_uart_readl(CDNS_UART_CR_OFFSET);
1082         cdns_uart_writel((ctrl & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN,
1083                 CDNS_UART_CR_OFFSET);
1084 
1085         uart_console_write(port, s, count, cdns_uart_console_putchar);
1086         cdns_uart_console_wait_tx(port);
1087 
1088         cdns_uart_writel(ctrl, CDNS_UART_CR_OFFSET);
1089 
1090         /* restore interrupt state */
1091         cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
1092 
1093         if (locked)
1094                 spin_unlock_irqrestore(&port->lock, flags);
1095 }
1096 
1097 /**
1098  * cdns_uart_console_setup - Initialize the uart to default config
1099  * @co: Console handle
1100  * @options: Initial settings of uart
1101  *
1102  * Return: 0 on success, negative errno otherwise.
1103  */
1104 static int __init cdns_uart_console_setup(struct console *co, char *options)
1105 {
1106         struct uart_port *port = &cdns_uart_port[co->index];
1107         int baud = 9600;
1108         int bits = 8;
1109         int parity = 'n';
1110         int flow = 'n';
1111 
1112         if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1113                 return -EINVAL;
1114 
1115         if (!port->mapbase) {
1116                 pr_debug("console on ttyPS%i not present\n", co->index);
1117                 return -ENODEV;
1118         }
1119 
1120         if (options)
1121                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1122 
1123         return uart_set_options(port, co, baud, parity, bits, flow);
1124 }
1125 
1126 static struct uart_driver cdns_uart_uart_driver;
1127 
1128 static struct console cdns_uart_console = {
1129         .name   = CDNS_UART_TTY_NAME,
1130         .write  = cdns_uart_console_write,
1131         .device = uart_console_device,
1132         .setup  = cdns_uart_console_setup,
1133         .flags  = CON_PRINTBUFFER,
1134         .index  = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1135         .data   = &cdns_uart_uart_driver,
1136 };
1137 
1138 /**
1139  * cdns_uart_console_init - Initialization call
1140  *
1141  * Return: 0 on success, negative errno otherwise
1142  */
1143 static int __init cdns_uart_console_init(void)
1144 {
1145         register_console(&cdns_uart_console);
1146         return 0;
1147 }
1148 
1149 console_initcall(cdns_uart_console_init);
1150 
1151 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1152 
1153 static struct uart_driver cdns_uart_uart_driver = {
1154         .owner          = THIS_MODULE,
1155         .driver_name    = CDNS_UART_NAME,
1156         .dev_name       = CDNS_UART_TTY_NAME,
1157         .major          = CDNS_UART_MAJOR,
1158         .minor          = CDNS_UART_MINOR,
1159         .nr             = CDNS_UART_NR_PORTS,
1160 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1161         .cons           = &cdns_uart_console,
1162 #endif
1163 };
1164 
1165 #ifdef CONFIG_PM_SLEEP
1166 /**
1167  * cdns_uart_suspend - suspend event
1168  * @device: Pointer to the device structure
1169  *
1170  * Return: 0
1171  */
1172 static int cdns_uart_suspend(struct device *device)
1173 {
1174         struct uart_port *port = dev_get_drvdata(device);
1175         struct tty_struct *tty;
1176         struct device *tty_dev;
1177         int may_wake = 0;
1178 
1179         /* Get the tty which could be NULL so don't assume it's valid */
1180         tty = tty_port_tty_get(&port->state->port);
1181         if (tty) {
1182                 tty_dev = tty->dev;
1183                 may_wake = device_may_wakeup(tty_dev);
1184                 tty_kref_put(tty);
1185         }
1186 
1187         /*
1188          * Call the API provided in serial_core.c file which handles
1189          * the suspend.
1190          */
1191         uart_suspend_port(&cdns_uart_uart_driver, port);
1192         if (console_suspend_enabled && !may_wake) {
1193                 struct cdns_uart *cdns_uart = port->private_data;
1194 
1195                 clk_disable(cdns_uart->uartclk);
1196                 clk_disable(cdns_uart->pclk);
1197         } else {
1198                 unsigned long flags = 0;
1199 
1200                 spin_lock_irqsave(&port->lock, flags);
1201                 /* Empty the receive FIFO 1st before making changes */
1202                 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) &
1203                                         CDNS_UART_SR_RXEMPTY))
1204                         cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
1205                 /* set RX trigger level to 1 */
1206                 cdns_uart_writel(1, CDNS_UART_RXWM_OFFSET);
1207                 /* disable RX timeout interrups */
1208                 cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IDR_OFFSET);
1209                 spin_unlock_irqrestore(&port->lock, flags);
1210         }
1211 
1212         return 0;
1213 }
1214 
1215 /**
1216  * cdns_uart_resume - Resume after a previous suspend
1217  * @device: Pointer to the device structure
1218  *
1219  * Return: 0
1220  */
1221 static int cdns_uart_resume(struct device *device)
1222 {
1223         struct uart_port *port = dev_get_drvdata(device);
1224         unsigned long flags = 0;
1225         u32 ctrl_reg;
1226         struct tty_struct *tty;
1227         struct device *tty_dev;
1228         int may_wake = 0;
1229 
1230         /* Get the tty which could be NULL so don't assume it's valid */
1231         tty = tty_port_tty_get(&port->state->port);
1232         if (tty) {
1233                 tty_dev = tty->dev;
1234                 may_wake = device_may_wakeup(tty_dev);
1235                 tty_kref_put(tty);
1236         }
1237 
1238         if (console_suspend_enabled && !may_wake) {
1239                 struct cdns_uart *cdns_uart = port->private_data;
1240 
1241                 clk_enable(cdns_uart->pclk);
1242                 clk_enable(cdns_uart->uartclk);
1243 
1244                 spin_lock_irqsave(&port->lock, flags);
1245 
1246                 /* Set TX/RX Reset */
1247                 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
1248                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1249                 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
1250                 while (cdns_uart_readl(CDNS_UART_CR_OFFSET) &
1251                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1252                         cpu_relax();
1253 
1254                 /* restore rx timeout value */
1255                 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
1256                 /* Enable Tx/Rx */
1257                 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
1258                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1259                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1260                 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
1261 
1262                 spin_unlock_irqrestore(&port->lock, flags);
1263         } else {
1264                 spin_lock_irqsave(&port->lock, flags);
1265                 /* restore original rx trigger level */
1266                 cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET);
1267                 /* enable RX timeout interrupt */
1268                 cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IER_OFFSET);
1269                 spin_unlock_irqrestore(&port->lock, flags);
1270         }
1271 
1272         return uart_resume_port(&cdns_uart_uart_driver, port);
1273 }
1274 #endif /* ! CONFIG_PM_SLEEP */
1275 
1276 static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend,
1277                 cdns_uart_resume);
1278 
1279 /**
1280  * cdns_uart_probe - Platform driver probe
1281  * @pdev: Pointer to the platform device structure
1282  *
1283  * Return: 0 on success, negative errno otherwise
1284  */
1285 static int cdns_uart_probe(struct platform_device *pdev)
1286 {
1287         int rc, id;
1288         struct uart_port *port;
1289         struct resource *res, *res2;
1290         struct cdns_uart *cdns_uart_data;
1291 
1292         cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1293                         GFP_KERNEL);
1294         if (!cdns_uart_data)
1295                 return -ENOMEM;
1296 
1297         cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1298         if (IS_ERR(cdns_uart_data->pclk)) {
1299                 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1300                 if (!IS_ERR(cdns_uart_data->pclk))
1301                         dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1302         }
1303         if (IS_ERR(cdns_uart_data->pclk)) {
1304                 dev_err(&pdev->dev, "pclk clock not found.\n");
1305                 return PTR_ERR(cdns_uart_data->pclk);
1306         }
1307 
1308         cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1309         if (IS_ERR(cdns_uart_data->uartclk)) {
1310                 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1311                 if (!IS_ERR(cdns_uart_data->uartclk))
1312                         dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1313         }
1314         if (IS_ERR(cdns_uart_data->uartclk)) {
1315                 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1316                 return PTR_ERR(cdns_uart_data->uartclk);
1317         }
1318 
1319         rc = clk_prepare_enable(cdns_uart_data->pclk);
1320         if (rc) {
1321                 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1322                 return rc;
1323         }
1324         rc = clk_prepare_enable(cdns_uart_data->uartclk);
1325         if (rc) {
1326                 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1327                 goto err_out_clk_dis_pclk;
1328         }
1329 
1330         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1331         if (!res) {
1332                 rc = -ENODEV;
1333                 goto err_out_clk_disable;
1334         }
1335 
1336         res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1337         if (!res2) {
1338                 rc = -ENODEV;
1339                 goto err_out_clk_disable;
1340         }
1341 
1342 #ifdef CONFIG_COMMON_CLK
1343         cdns_uart_data->clk_rate_change_nb.notifier_call =
1344                         cdns_uart_clk_notifier_cb;
1345         if (clk_notifier_register(cdns_uart_data->uartclk,
1346                                 &cdns_uart_data->clk_rate_change_nb))
1347                 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1348 #endif
1349         /* Look for a serialN alias */
1350         id = of_alias_get_id(pdev->dev.of_node, "serial");
1351         if (id < 0)
1352                 id = 0;
1353 
1354         /* Initialize the port structure */
1355         port = cdns_uart_get_port(id);
1356 
1357         if (!port) {
1358                 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1359                 rc = -ENODEV;
1360                 goto err_out_notif_unreg;
1361         } else {
1362                 /* Register the port.
1363                  * This function also registers this device with the tty layer
1364                  * and triggers invocation of the config_port() entry point.
1365                  */
1366                 port->mapbase = res->start;
1367                 port->irq = res2->start;
1368                 port->dev = &pdev->dev;
1369                 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1370                 port->private_data = cdns_uart_data;
1371                 cdns_uart_data->port = port;
1372                 platform_set_drvdata(pdev, port);
1373                 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1374                 if (rc) {
1375                         dev_err(&pdev->dev,
1376                                 "uart_add_one_port() failed; err=%i\n", rc);
1377                         goto err_out_notif_unreg;
1378                 }
1379                 return 0;
1380         }
1381 
1382 err_out_notif_unreg:
1383 #ifdef CONFIG_COMMON_CLK
1384         clk_notifier_unregister(cdns_uart_data->uartclk,
1385                         &cdns_uart_data->clk_rate_change_nb);
1386 #endif
1387 err_out_clk_disable:
1388         clk_disable_unprepare(cdns_uart_data->uartclk);
1389 err_out_clk_dis_pclk:
1390         clk_disable_unprepare(cdns_uart_data->pclk);
1391 
1392         return rc;
1393 }
1394 
1395 /**
1396  * cdns_uart_remove - called when the platform driver is unregistered
1397  * @pdev: Pointer to the platform device structure
1398  *
1399  * Return: 0 on success, negative errno otherwise
1400  */
1401 static int cdns_uart_remove(struct platform_device *pdev)
1402 {
1403         struct uart_port *port = platform_get_drvdata(pdev);
1404         struct cdns_uart *cdns_uart_data = port->private_data;
1405         int rc;
1406 
1407         /* Remove the cdns_uart port from the serial core */
1408 #ifdef CONFIG_COMMON_CLK
1409         clk_notifier_unregister(cdns_uart_data->uartclk,
1410                         &cdns_uart_data->clk_rate_change_nb);
1411 #endif
1412         rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1413         port->mapbase = 0;
1414         clk_disable_unprepare(cdns_uart_data->uartclk);
1415         clk_disable_unprepare(cdns_uart_data->pclk);
1416         return rc;
1417 }
1418 
1419 /* Match table for of_platform binding */
1420 static struct of_device_id cdns_uart_of_match[] = {
1421         { .compatible = "xlnx,xuartps", },
1422         { .compatible = "cdns,uart-r1p8", },
1423         {}
1424 };
1425 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1426 
1427 static struct platform_driver cdns_uart_platform_driver = {
1428         .probe   = cdns_uart_probe,
1429         .remove  = cdns_uart_remove,
1430         .driver  = {
1431                 .owner = THIS_MODULE,
1432                 .name = CDNS_UART_NAME,
1433                 .of_match_table = cdns_uart_of_match,
1434                 .pm = &cdns_uart_dev_pm_ops,
1435                 },
1436 };
1437 
1438 static int __init cdns_uart_init(void)
1439 {
1440         int retval = 0;
1441 
1442         /* Register the cdns_uart driver with the serial core */
1443         retval = uart_register_driver(&cdns_uart_uart_driver);
1444         if (retval)
1445                 return retval;
1446 
1447         /* Register the platform driver */
1448         retval = platform_driver_register(&cdns_uart_platform_driver);
1449         if (retval)
1450                 uart_unregister_driver(&cdns_uart_uart_driver);
1451 
1452         return retval;
1453 }
1454 
1455 static void __exit cdns_uart_exit(void)
1456 {
1457         /* Unregister the platform driver */
1458         platform_driver_unregister(&cdns_uart_platform_driver);
1459 
1460         /* Unregister the cdns_uart driver */
1461         uart_unregister_driver(&cdns_uart_uart_driver);
1462 }
1463 
1464 module_init(cdns_uart_init);
1465 module_exit(cdns_uart_exit);
1466 
1467 MODULE_DESCRIPTION("Driver for Cadence UART");
1468 MODULE_AUTHOR("Xilinx Inc.");
1469 MODULE_LICENSE("GPL");
1470 

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