Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/tty/serial/xilinx_uartps.c

  1 /*
  2  * Xilinx PS UART driver
  3  *
  4  * 2011 - 2013 (C) Xilinx Inc.
  5  *
  6  * This program is free software; you can redistribute it
  7  * and/or modify it under the terms of the GNU General Public
  8  * License as published by the Free Software Foundation;
  9  * either version 2 of the License, or (at your option) any
 10  * later version.
 11  *
 12  */
 13 
 14 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 15 #define SUPPORT_SYSRQ
 16 #endif
 17 
 18 #include <linux/platform_device.h>
 19 #include <linux/serial.h>
 20 #include <linux/console.h>
 21 #include <linux/serial_core.h>
 22 #include <linux/slab.h>
 23 #include <linux/tty.h>
 24 #include <linux/tty_flip.h>
 25 #include <linux/clk.h>
 26 #include <linux/irq.h>
 27 #include <linux/io.h>
 28 #include <linux/of.h>
 29 #include <linux/module.h>
 30 
 31 #define XUARTPS_TTY_NAME        "ttyPS"
 32 #define XUARTPS_NAME            "xuartps"
 33 #define XUARTPS_MAJOR           0       /* use dynamic node allocation */
 34 #define XUARTPS_MINOR           0       /* works best with devtmpfs */
 35 #define XUARTPS_NR_PORTS        2
 36 #define XUARTPS_FIFO_SIZE       64      /* FIFO size */
 37 #define XUARTPS_REGISTER_SPACE  0xFFF
 38 
 39 #define xuartps_readl(offset)           ioread32(port->membase + offset)
 40 #define xuartps_writel(val, offset)     iowrite32(val, port->membase + offset)
 41 
 42 /* Rx Trigger level */
 43 static int rx_trigger_level = 56;
 44 module_param(rx_trigger_level, uint, S_IRUGO);
 45 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
 46 
 47 /* Rx Timeout */
 48 static int rx_timeout = 10;
 49 module_param(rx_timeout, uint, S_IRUGO);
 50 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
 51 
 52 /********************************Register Map********************************/
 53 /** UART
 54  *
 55  * Register offsets for the UART.
 56  *
 57  */
 58 #define XUARTPS_CR_OFFSET       0x00  /* Control Register [8:0] */
 59 #define XUARTPS_MR_OFFSET       0x04  /* Mode Register [10:0] */
 60 #define XUARTPS_IER_OFFSET      0x08  /* Interrupt Enable [10:0] */
 61 #define XUARTPS_IDR_OFFSET      0x0C  /* Interrupt Disable [10:0] */
 62 #define XUARTPS_IMR_OFFSET      0x10  /* Interrupt Mask [10:0] */
 63 #define XUARTPS_ISR_OFFSET      0x14  /* Interrupt Status [10:0]*/
 64 #define XUARTPS_BAUDGEN_OFFSET  0x18  /* Baud Rate Generator [15:0] */
 65 #define XUARTPS_RXTOUT_OFFSET   0x1C  /* RX Timeout [7:0] */
 66 #define XUARTPS_RXWM_OFFSET     0x20  /* RX FIFO Trigger Level [5:0] */
 67 #define XUARTPS_MODEMCR_OFFSET  0x24  /* Modem Control [5:0] */
 68 #define XUARTPS_MODEMSR_OFFSET  0x28  /* Modem Status [8:0] */
 69 #define XUARTPS_SR_OFFSET       0x2C  /* Channel Status [11:0] */
 70 #define XUARTPS_FIFO_OFFSET     0x30  /* FIFO [15:0] or [7:0] */
 71 #define XUARTPS_BAUDDIV_OFFSET  0x34  /* Baud Rate Divider [7:0] */
 72 #define XUARTPS_FLOWDEL_OFFSET  0x38  /* Flow Delay [15:0] */
 73 #define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse
 74                                                 Width [15:0] */
 75 #define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse
 76                                                 Width [7:0] */
 77 #define XUARTPS_TXWM_OFFSET     0x44  /* TX FIFO Trigger Level [5:0] */
 78 
 79 /** Control Register
 80  *
 81  * The Control register (CR) controls the major functions of the device.
 82  *
 83  * Control Register Bit Definitions
 84  */
 85 #define XUARTPS_CR_STOPBRK      0x00000100  /* Stop TX break */
 86 #define XUARTPS_CR_STARTBRK     0x00000080  /* Set TX break */
 87 #define XUARTPS_CR_TX_DIS       0x00000020  /* TX disabled. */
 88 #define XUARTPS_CR_TX_EN        0x00000010  /* TX enabled */
 89 #define XUARTPS_CR_RX_DIS       0x00000008  /* RX disabled. */
 90 #define XUARTPS_CR_RX_EN        0x00000004  /* RX enabled */
 91 #define XUARTPS_CR_TXRST        0x00000002  /* TX logic reset */
 92 #define XUARTPS_CR_RXRST        0x00000001  /* RX logic reset */
 93 #define XUARTPS_CR_RST_TO       0x00000040  /* Restart Timeout Counter */
 94 
 95 /** Mode Register
 96  *
 97  * The mode register (MR) defines the mode of transfer as well as the data
 98  * format. If this register is modified during transmission or reception,
 99  * data validity cannot be guaranteed.
100  *
101  * Mode Register Bit Definitions
102  *
103  */
104 #define XUARTPS_MR_CLKSEL               0x00000001  /* Pre-scalar selection */
105 #define XUARTPS_MR_CHMODE_L_LOOP        0x00000200  /* Local loop back mode */
106 #define XUARTPS_MR_CHMODE_NORM          0x00000000  /* Normal mode */
107 
108 #define XUARTPS_MR_STOPMODE_2_BIT       0x00000080  /* 2 stop bits */
109 #define XUARTPS_MR_STOPMODE_1_BIT       0x00000000  /* 1 stop bit */
110 
111 #define XUARTPS_MR_PARITY_NONE          0x00000020  /* No parity mode */
112 #define XUARTPS_MR_PARITY_MARK          0x00000018  /* Mark parity mode */
113 #define XUARTPS_MR_PARITY_SPACE         0x00000010  /* Space parity mode */
114 #define XUARTPS_MR_PARITY_ODD           0x00000008  /* Odd parity mode */
115 #define XUARTPS_MR_PARITY_EVEN          0x00000000  /* Even parity mode */
116 
117 #define XUARTPS_MR_CHARLEN_6_BIT        0x00000006  /* 6 bits data */
118 #define XUARTPS_MR_CHARLEN_7_BIT        0x00000004  /* 7 bits data */
119 #define XUARTPS_MR_CHARLEN_8_BIT        0x00000000  /* 8 bits data */
120 
121 /** Interrupt Registers
122  *
123  * Interrupt control logic uses the interrupt enable register (IER) and the
124  * interrupt disable register (IDR) to set the value of the bits in the
125  * interrupt mask register (IMR). The IMR determines whether to pass an
126  * interrupt to the interrupt status register (ISR).
127  * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
128  * interrupt. IMR and ISR are read only, and IER and IDR are write only.
129  * Reading either IER or IDR returns 0x00.
130  *
131  * All four registers have the same bit definitions.
132  */
133 #define XUARTPS_IXR_TOUT        0x00000100 /* RX Timeout error interrupt */
134 #define XUARTPS_IXR_PARITY      0x00000080 /* Parity error interrupt */
135 #define XUARTPS_IXR_FRAMING     0x00000040 /* Framing error interrupt */
136 #define XUARTPS_IXR_OVERRUN     0x00000020 /* Overrun error interrupt */
137 #define XUARTPS_IXR_TXFULL      0x00000010 /* TX FIFO Full interrupt */
138 #define XUARTPS_IXR_TXEMPTY     0x00000008 /* TX FIFO empty interrupt */
139 #define XUARTPS_ISR_RXEMPTY     0x00000002 /* RX FIFO empty interrupt */
140 #define XUARTPS_IXR_RXTRIG      0x00000001 /* RX FIFO trigger interrupt */
141 #define XUARTPS_IXR_RXFULL      0x00000004 /* RX FIFO full interrupt. */
142 #define XUARTPS_IXR_RXEMPTY     0x00000002 /* RX FIFO empty interrupt. */
143 #define XUARTPS_IXR_MASK        0x00001FFF /* Valid bit mask */
144 
145 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
146 #define XUARTPS_IXR_BRK         0x80000000
147 
148 /** Channel Status Register
149  *
150  * The channel status register (CSR) is provided to enable the control logic
151  * to monitor the status of bits in the channel interrupt status register,
152  * even if these are masked out by the interrupt mask register.
153  */
154 #define XUARTPS_SR_RXEMPTY      0x00000002 /* RX FIFO empty */
155 #define XUARTPS_SR_TXEMPTY      0x00000008 /* TX FIFO empty */
156 #define XUARTPS_SR_TXFULL       0x00000010 /* TX FIFO full */
157 #define XUARTPS_SR_RXTRIG       0x00000001 /* Rx Trigger */
158 
159 /* baud dividers min/max values */
160 #define XUARTPS_BDIV_MIN        4
161 #define XUARTPS_BDIV_MAX        255
162 #define XUARTPS_CD_MAX          65535
163 
164 /**
165  * struct xuartps - device data
166  * @port                Pointer to the UART port
167  * @refclk              Reference clock
168  * @aperclk             APB clock
169  * @baud                Current baud rate
170  * @clk_rate_change_nb  Notifier block for clock changes
171  */
172 struct xuartps {
173         struct uart_port        *port;
174         struct clk              *refclk;
175         struct clk              *aperclk;
176         unsigned int            baud;
177         struct notifier_block   clk_rate_change_nb;
178 };
179 #define to_xuartps(_nb) container_of(_nb, struct xuartps, clk_rate_change_nb);
180 
181 /**
182  * xuartps_isr - Interrupt handler
183  * @irq: Irq number
184  * @dev_id: Id of the port
185  *
186  * Returns IRQHANDLED
187  **/
188 static irqreturn_t xuartps_isr(int irq, void *dev_id)
189 {
190         struct uart_port *port = (struct uart_port *)dev_id;
191         unsigned long flags;
192         unsigned int isrstatus, numbytes;
193         unsigned int data;
194         char status = TTY_NORMAL;
195 
196         spin_lock_irqsave(&port->lock, flags);
197 
198         /* Read the interrupt status register to determine which
199          * interrupt(s) is/are active.
200          */
201         isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET);
202 
203         /*
204          * There is no hardware break detection, so we interpret framing
205          * error with all-zeros data as a break sequence. Most of the time,
206          * there's another non-zero byte at the end of the sequence.
207          */
208 
209         if (isrstatus & XUARTPS_IXR_FRAMING) {
210                 while (!(xuartps_readl(XUARTPS_SR_OFFSET) &
211                                         XUARTPS_SR_RXEMPTY)) {
212                         if (!xuartps_readl(XUARTPS_FIFO_OFFSET)) {
213                                 port->read_status_mask |= XUARTPS_IXR_BRK;
214                                 isrstatus &= ~XUARTPS_IXR_FRAMING;
215                         }
216                 }
217                 xuartps_writel(XUARTPS_IXR_FRAMING, XUARTPS_ISR_OFFSET);
218         }
219 
220         /* drop byte with parity error if IGNPAR specified */
221         if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY)
222                 isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT);
223 
224         isrstatus &= port->read_status_mask;
225         isrstatus &= ~port->ignore_status_mask;
226 
227         if ((isrstatus & XUARTPS_IXR_TOUT) ||
228                 (isrstatus & XUARTPS_IXR_RXTRIG)) {
229                 /* Receive Timeout Interrupt */
230                 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
231                         XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
232                         data = xuartps_readl(XUARTPS_FIFO_OFFSET);
233 
234                         /* Non-NULL byte after BREAK is garbage (99%) */
235                         if (data && (port->read_status_mask &
236                                                 XUARTPS_IXR_BRK)) {
237                                 port->read_status_mask &= ~XUARTPS_IXR_BRK;
238                                 port->icount.brk++;
239                                 if (uart_handle_break(port))
240                                         continue;
241                         }
242 
243 #ifdef SUPPORT_SYSRQ
244                         /*
245                          * uart_handle_sysrq_char() doesn't work if
246                          * spinlocked, for some reason
247                          */
248                          if (port->sysrq) {
249                                 spin_unlock(&port->lock);
250                                 if (uart_handle_sysrq_char(port,
251                                                         (unsigned char)data)) {
252                                         spin_lock(&port->lock);
253                                         continue;
254                                 }
255                                 spin_lock(&port->lock);
256                         }
257 #endif
258 
259                         port->icount.rx++;
260 
261                         if (isrstatus & XUARTPS_IXR_PARITY) {
262                                 port->icount.parity++;
263                                 status = TTY_PARITY;
264                         } else if (isrstatus & XUARTPS_IXR_FRAMING) {
265                                 port->icount.frame++;
266                                 status = TTY_FRAME;
267                         } else if (isrstatus & XUARTPS_IXR_OVERRUN)
268                                 port->icount.overrun++;
269 
270                         uart_insert_char(port, isrstatus, XUARTPS_IXR_OVERRUN,
271                                         data, status);
272                 }
273                 spin_unlock(&port->lock);
274                 tty_flip_buffer_push(&port->state->port);
275                 spin_lock(&port->lock);
276         }
277 
278         /* Dispatch an appropriate handler */
279         if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) {
280                 if (uart_circ_empty(&port->state->xmit)) {
281                         xuartps_writel(XUARTPS_IXR_TXEMPTY,
282                                                 XUARTPS_IDR_OFFSET);
283                 } else {
284                         numbytes = port->fifosize;
285                         /* Break if no more data available in the UART buffer */
286                         while (numbytes--) {
287                                 if (uart_circ_empty(&port->state->xmit))
288                                         break;
289                                 /* Get the data from the UART circular buffer
290                                  * and write it to the xuartps's TX_FIFO
291                                  * register.
292                                  */
293                                 xuartps_writel(
294                                         port->state->xmit.buf[port->state->xmit.
295                                         tail], XUARTPS_FIFO_OFFSET);
296 
297                                 port->icount.tx++;
298 
299                                 /* Adjust the tail of the UART buffer and wrap
300                                  * the buffer if it reaches limit.
301                                  */
302                                 port->state->xmit.tail =
303                                         (port->state->xmit.tail + 1) & \
304                                                 (UART_XMIT_SIZE - 1);
305                         }
306 
307                         if (uart_circ_chars_pending(
308                                         &port->state->xmit) < WAKEUP_CHARS)
309                                 uart_write_wakeup(port);
310                 }
311         }
312 
313         xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET);
314 
315         /* be sure to release the lock and tty before leaving */
316         spin_unlock_irqrestore(&port->lock, flags);
317 
318         return IRQ_HANDLED;
319 }
320 
321 /**
322  * xuartps_calc_baud_divs - Calculate baud rate divisors
323  * @clk: UART module input clock
324  * @baud: Desired baud rate
325  * @rbdiv: BDIV value (return value)
326  * @rcd: CD value (return value)
327  * @div8: Value for clk_sel bit in mod (return value)
328  * Returns baud rate, requested baud when possible, or actual baud when there
329  *      was too much error, zero if no valid divisors are found.
330  *
331  * Formula to obtain baud rate is
332  *      baud_tx/rx rate = clk/CD * (BDIV + 1)
333  *      input_clk = (Uart User Defined Clock or Apb Clock)
334  *              depends on UCLKEN in MR Reg
335  *      clk = input_clk or input_clk/8;
336  *              depends on CLKS in MR reg
337  *      CD and BDIV depends on values in
338  *                      baud rate generate register
339  *                      baud rate clock divisor register
340  */
341 static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud,
342                 u32 *rbdiv, u32 *rcd, int *div8)
343 {
344         u32 cd, bdiv;
345         unsigned int calc_baud;
346         unsigned int bestbaud = 0;
347         unsigned int bauderror;
348         unsigned int besterror = ~0;
349 
350         if (baud < clk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX)) {
351                 *div8 = 1;
352                 clk /= 8;
353         } else {
354                 *div8 = 0;
355         }
356 
357         for (bdiv = XUARTPS_BDIV_MIN; bdiv <= XUARTPS_BDIV_MAX; bdiv++) {
358                 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
359                 if (cd < 1 || cd > XUARTPS_CD_MAX)
360                         continue;
361 
362                 calc_baud = clk / (cd * (bdiv + 1));
363 
364                 if (baud > calc_baud)
365                         bauderror = baud - calc_baud;
366                 else
367                         bauderror = calc_baud - baud;
368 
369                 if (besterror > bauderror) {
370                         *rbdiv = bdiv;
371                         *rcd = cd;
372                         bestbaud = calc_baud;
373                         besterror = bauderror;
374                 }
375         }
376         /* use the values when percent error is acceptable */
377         if (((besterror * 100) / baud) < 3)
378                 bestbaud = baud;
379 
380         return bestbaud;
381 }
382 
383 /**
384  * xuartps_set_baud_rate - Calculate and set the baud rate
385  * @port: Handle to the uart port structure
386  * @baud: Baud rate to set
387  * Returns baud rate, requested baud when possible, or actual baud when there
388  *         was too much error, zero if no valid divisors are found.
389  */
390 static unsigned int xuartps_set_baud_rate(struct uart_port *port,
391                 unsigned int baud)
392 {
393         unsigned int calc_baud;
394         u32 cd = 0, bdiv = 0;
395         u32 mreg;
396         int div8;
397         struct xuartps *xuartps = port->private_data;
398 
399         calc_baud = xuartps_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
400                         &div8);
401 
402         /* Write new divisors to hardware */
403         mreg = xuartps_readl(XUARTPS_MR_OFFSET);
404         if (div8)
405                 mreg |= XUARTPS_MR_CLKSEL;
406         else
407                 mreg &= ~XUARTPS_MR_CLKSEL;
408         xuartps_writel(mreg, XUARTPS_MR_OFFSET);
409         xuartps_writel(cd, XUARTPS_BAUDGEN_OFFSET);
410         xuartps_writel(bdiv, XUARTPS_BAUDDIV_OFFSET);
411         xuartps->baud = baud;
412 
413         return calc_baud;
414 }
415 
416 #ifdef CONFIG_COMMON_CLK
417 /**
418  * xuartps_clk_notitifer_cb - Clock notifier callback
419  * @nb:         Notifier block
420  * @event:      Notify event
421  * @data:       Notifier data
422  * Returns NOTIFY_OK on success, NOTIFY_BAD on error.
423  */
424 static int xuartps_clk_notifier_cb(struct notifier_block *nb,
425                 unsigned long event, void *data)
426 {
427         u32 ctrl_reg;
428         struct uart_port *port;
429         int locked = 0;
430         struct clk_notifier_data *ndata = data;
431         unsigned long flags = 0;
432         struct xuartps *xuartps = to_xuartps(nb);
433 
434         port = xuartps->port;
435         if (port->suspended)
436                 return NOTIFY_OK;
437 
438         switch (event) {
439         case PRE_RATE_CHANGE:
440         {
441                 u32 bdiv;
442                 u32 cd;
443                 int div8;
444 
445                 /*
446                  * Find out if current baud-rate can be achieved with new clock
447                  * frequency.
448                  */
449                 if (!xuartps_calc_baud_divs(ndata->new_rate, xuartps->baud,
450                                         &bdiv, &cd, &div8))
451                         return NOTIFY_BAD;
452 
453                 spin_lock_irqsave(&xuartps->port->lock, flags);
454 
455                 /* Disable the TX and RX to set baud rate */
456                 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
457                                 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS),
458                                 XUARTPS_CR_OFFSET);
459 
460                 spin_unlock_irqrestore(&xuartps->port->lock, flags);
461 
462                 return NOTIFY_OK;
463         }
464         case POST_RATE_CHANGE:
465                 /*
466                  * Set clk dividers to generate correct baud with new clock
467                  * frequency.
468                  */
469 
470                 spin_lock_irqsave(&xuartps->port->lock, flags);
471 
472                 locked = 1;
473                 port->uartclk = ndata->new_rate;
474 
475                 xuartps->baud = xuartps_set_baud_rate(xuartps->port,
476                                 xuartps->baud);
477                 /* fall through */
478         case ABORT_RATE_CHANGE:
479                 if (!locked)
480                         spin_lock_irqsave(&xuartps->port->lock, flags);
481 
482                 /* Set TX/RX Reset */
483                 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
484                                 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
485                                 XUARTPS_CR_OFFSET);
486 
487                 while (xuartps_readl(XUARTPS_CR_OFFSET) &
488                                 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST))
489                         cpu_relax();
490 
491                 /*
492                  * Clear the RX disable and TX disable bits and then set the TX
493                  * enable bit and RX enable bit to enable the transmitter and
494                  * receiver.
495                  */
496                 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
497                 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
498                 xuartps_writel(
499                         (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) |
500                         (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
501                         XUARTPS_CR_OFFSET);
502 
503                 spin_unlock_irqrestore(&xuartps->port->lock, flags);
504 
505                 return NOTIFY_OK;
506         default:
507                 return NOTIFY_DONE;
508         }
509 }
510 #endif
511 
512 /*----------------------Uart Operations---------------------------*/
513 
514 /**
515  * xuartps_start_tx -  Start transmitting bytes
516  * @port: Handle to the uart port structure
517  *
518  **/
519 static void xuartps_start_tx(struct uart_port *port)
520 {
521         unsigned int status, numbytes = port->fifosize;
522 
523         if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
524                 return;
525 
526         status = xuartps_readl(XUARTPS_CR_OFFSET);
527         /* Set the TX enable bit and clear the TX disable bit to enable the
528          * transmitter.
529          */
530         xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
531                 XUARTPS_CR_OFFSET);
532 
533         while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET)
534                 & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) {
535 
536                 /* Break if no more data available in the UART buffer */
537                 if (uart_circ_empty(&port->state->xmit))
538                         break;
539 
540                 /* Get the data from the UART circular buffer and
541                  * write it to the xuartps's TX_FIFO register.
542                  */
543                 xuartps_writel(
544                         port->state->xmit.buf[port->state->xmit.tail],
545                         XUARTPS_FIFO_OFFSET);
546                 port->icount.tx++;
547 
548                 /* Adjust the tail of the UART buffer and wrap
549                  * the buffer if it reaches limit.
550                  */
551                 port->state->xmit.tail = (port->state->xmit.tail + 1) &
552                                         (UART_XMIT_SIZE - 1);
553         }
554         xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_ISR_OFFSET);
555         /* Enable the TX Empty interrupt */
556         xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET);
557 
558         if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
559                 uart_write_wakeup(port);
560 }
561 
562 /**
563  * xuartps_stop_tx - Stop TX
564  * @port: Handle to the uart port structure
565  *
566  **/
567 static void xuartps_stop_tx(struct uart_port *port)
568 {
569         unsigned int regval;
570 
571         regval = xuartps_readl(XUARTPS_CR_OFFSET);
572         regval |= XUARTPS_CR_TX_DIS;
573         /* Disable the transmitter */
574         xuartps_writel(regval, XUARTPS_CR_OFFSET);
575 }
576 
577 /**
578  * xuartps_stop_rx - Stop RX
579  * @port: Handle to the uart port structure
580  *
581  **/
582 static void xuartps_stop_rx(struct uart_port *port)
583 {
584         unsigned int regval;
585 
586         regval = xuartps_readl(XUARTPS_CR_OFFSET);
587         regval |= XUARTPS_CR_RX_DIS;
588         /* Disable the receiver */
589         xuartps_writel(regval, XUARTPS_CR_OFFSET);
590 }
591 
592 /**
593  * xuartps_tx_empty -  Check whether TX is empty
594  * @port: Handle to the uart port structure
595  *
596  * Returns TIOCSER_TEMT on success, 0 otherwise
597  **/
598 static unsigned int xuartps_tx_empty(struct uart_port *port)
599 {
600         unsigned int status;
601 
602         status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY;
603         return status ? TIOCSER_TEMT : 0;
604 }
605 
606 /**
607  * xuartps_break_ctl - Based on the input ctl we have to start or stop
608  *                      transmitting char breaks
609  * @port: Handle to the uart port structure
610  * @ctl: Value based on which start or stop decision is taken
611  *
612  **/
613 static void xuartps_break_ctl(struct uart_port *port, int ctl)
614 {
615         unsigned int status;
616         unsigned long flags;
617 
618         spin_lock_irqsave(&port->lock, flags);
619 
620         status = xuartps_readl(XUARTPS_CR_OFFSET);
621 
622         if (ctl == -1)
623                 xuartps_writel(XUARTPS_CR_STARTBRK | status,
624                                         XUARTPS_CR_OFFSET);
625         else {
626                 if ((status & XUARTPS_CR_STOPBRK) == 0)
627                         xuartps_writel(XUARTPS_CR_STOPBRK | status,
628                                          XUARTPS_CR_OFFSET);
629         }
630         spin_unlock_irqrestore(&port->lock, flags);
631 }
632 
633 /**
634  * xuartps_set_termios - termios operations, handling data length, parity,
635  *                              stop bits, flow control, baud rate
636  * @port: Handle to the uart port structure
637  * @termios: Handle to the input termios structure
638  * @old: Values of the previously saved termios structure
639  *
640  **/
641 static void xuartps_set_termios(struct uart_port *port,
642                                 struct ktermios *termios, struct ktermios *old)
643 {
644         unsigned int cval = 0;
645         unsigned int baud, minbaud, maxbaud;
646         unsigned long flags;
647         unsigned int ctrl_reg, mode_reg;
648 
649         spin_lock_irqsave(&port->lock, flags);
650 
651         /* Empty the receive FIFO 1st before making changes */
652         while ((xuartps_readl(XUARTPS_SR_OFFSET) &
653                  XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
654                 xuartps_readl(XUARTPS_FIFO_OFFSET);
655         }
656 
657         /* Disable the TX and RX to set baud rate */
658         xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
659                         (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS),
660                         XUARTPS_CR_OFFSET);
661 
662         /*
663          * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
664          * min and max baud should be calculated here based on port->uartclk.
665          * this way we get a valid baud and can safely call set_baud()
666          */
667         minbaud = port->uartclk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX * 8);
668         maxbaud = port->uartclk / (XUARTPS_BDIV_MIN + 1);
669         baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
670         baud = xuartps_set_baud_rate(port, baud);
671         if (tty_termios_baud_rate(termios))
672                 tty_termios_encode_baud_rate(termios, baud, baud);
673 
674         /*
675          * Update the per-port timeout.
676          */
677         uart_update_timeout(port, termios->c_cflag, baud);
678 
679         /* Set TX/RX Reset */
680         xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
681                         (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
682                         XUARTPS_CR_OFFSET);
683 
684         ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
685 
686         /* Clear the RX disable and TX disable bits and then set the TX enable
687          * bit and RX enable bit to enable the transmitter and receiver.
688          */
689         xuartps_writel(
690                 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
691                         | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
692                         XUARTPS_CR_OFFSET);
693 
694         xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
695 
696         port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG |
697                         XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT;
698         port->ignore_status_mask = 0;
699 
700         if (termios->c_iflag & INPCK)
701                 port->read_status_mask |= XUARTPS_IXR_PARITY |
702                 XUARTPS_IXR_FRAMING;
703 
704         if (termios->c_iflag & IGNPAR)
705                 port->ignore_status_mask |= XUARTPS_IXR_PARITY |
706                         XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
707 
708         /* ignore all characters if CREAD is not set */
709         if ((termios->c_cflag & CREAD) == 0)
710                 port->ignore_status_mask |= XUARTPS_IXR_RXTRIG |
711                         XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY |
712                         XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
713 
714         mode_reg = xuartps_readl(XUARTPS_MR_OFFSET);
715 
716         /* Handling Data Size */
717         switch (termios->c_cflag & CSIZE) {
718         case CS6:
719                 cval |= XUARTPS_MR_CHARLEN_6_BIT;
720                 break;
721         case CS7:
722                 cval |= XUARTPS_MR_CHARLEN_7_BIT;
723                 break;
724         default:
725         case CS8:
726                 cval |= XUARTPS_MR_CHARLEN_8_BIT;
727                 termios->c_cflag &= ~CSIZE;
728                 termios->c_cflag |= CS8;
729                 break;
730         }
731 
732         /* Handling Parity and Stop Bits length */
733         if (termios->c_cflag & CSTOPB)
734                 cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */
735         else
736                 cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */
737 
738         if (termios->c_cflag & PARENB) {
739                 /* Mark or Space parity */
740                 if (termios->c_cflag & CMSPAR) {
741                         if (termios->c_cflag & PARODD)
742                                 cval |= XUARTPS_MR_PARITY_MARK;
743                         else
744                                 cval |= XUARTPS_MR_PARITY_SPACE;
745                 } else {
746                         if (termios->c_cflag & PARODD)
747                                 cval |= XUARTPS_MR_PARITY_ODD;
748                         else
749                                 cval |= XUARTPS_MR_PARITY_EVEN;
750                 }
751         } else {
752                 cval |= XUARTPS_MR_PARITY_NONE;
753         }
754         cval |= mode_reg & 1;
755         xuartps_writel(cval, XUARTPS_MR_OFFSET);
756 
757         spin_unlock_irqrestore(&port->lock, flags);
758 }
759 
760 /**
761  * xuartps_startup - Called when an application opens a xuartps port
762  * @port: Handle to the uart port structure
763  *
764  * Returns 0 on success, negative error otherwise
765  **/
766 static int xuartps_startup(struct uart_port *port)
767 {
768         unsigned int retval = 0, status = 0;
769 
770         retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME,
771                                                                 (void *)port);
772         if (retval)
773                 return retval;
774 
775         /* Disable the TX and RX */
776         xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
777                                                 XUARTPS_CR_OFFSET);
778 
779         /* Set the Control Register with TX/RX Enable, TX/RX Reset,
780          * no break chars.
781          */
782         xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST,
783                                 XUARTPS_CR_OFFSET);
784 
785         status = xuartps_readl(XUARTPS_CR_OFFSET);
786 
787         /* Clear the RX disable and TX disable bits and then set the TX enable
788          * bit and RX enable bit to enable the transmitter and receiver.
789          */
790         xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
791                         | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN |
792                         XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET);
793 
794         /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
795          * no parity.
796          */
797         xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT
798                 | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT,
799                  XUARTPS_MR_OFFSET);
800 
801         /*
802          * Set the RX FIFO Trigger level to use most of the FIFO, but it
803          * can be tuned with a module parameter
804          */
805         xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET);
806 
807         /*
808          * Receive Timeout register is enabled but it
809          * can be tuned with a module parameter
810          */
811         xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
812 
813         /* Clear out any pending interrupts before enabling them */
814         xuartps_writel(xuartps_readl(XUARTPS_ISR_OFFSET), XUARTPS_ISR_OFFSET);
815 
816         /* Set the Interrupt Registers with desired interrupts */
817         xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY |
818                 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN |
819                 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
820 
821         return retval;
822 }
823 
824 /**
825  * xuartps_shutdown - Called when an application closes a xuartps port
826  * @port: Handle to the uart port structure
827  *
828  **/
829 static void xuartps_shutdown(struct uart_port *port)
830 {
831         int status;
832 
833         /* Disable interrupts */
834         status = xuartps_readl(XUARTPS_IMR_OFFSET);
835         xuartps_writel(status, XUARTPS_IDR_OFFSET);
836 
837         /* Disable the TX and RX */
838         xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
839                                  XUARTPS_CR_OFFSET);
840         free_irq(port->irq, port);
841 }
842 
843 /**
844  * xuartps_type - Set UART type to xuartps port
845  * @port: Handle to the uart port structure
846  *
847  * Returns string on success, NULL otherwise
848  **/
849 static const char *xuartps_type(struct uart_port *port)
850 {
851         return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL;
852 }
853 
854 /**
855  * xuartps_verify_port - Verify the port params
856  * @port: Handle to the uart port structure
857  * @ser: Handle to the structure whose members are compared
858  *
859  * Returns 0 if success otherwise -EINVAL
860  **/
861 static int xuartps_verify_port(struct uart_port *port,
862                                         struct serial_struct *ser)
863 {
864         if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
865                 return -EINVAL;
866         if (port->irq != ser->irq)
867                 return -EINVAL;
868         if (ser->io_type != UPIO_MEM)
869                 return -EINVAL;
870         if (port->iobase != ser->port)
871                 return -EINVAL;
872         if (ser->hub6 != 0)
873                 return -EINVAL;
874         return 0;
875 }
876 
877 /**
878  * xuartps_request_port - Claim the memory region attached to xuartps port,
879  *                              called when the driver adds a xuartps port via
880  *                              uart_add_one_port()
881  * @port: Handle to the uart port structure
882  *
883  * Returns 0, -ENOMEM if request fails
884  **/
885 static int xuartps_request_port(struct uart_port *port)
886 {
887         if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE,
888                                          XUARTPS_NAME)) {
889                 return -ENOMEM;
890         }
891 
892         port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE);
893         if (!port->membase) {
894                 dev_err(port->dev, "Unable to map registers\n");
895                 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
896                 return -ENOMEM;
897         }
898         return 0;
899 }
900 
901 /**
902  * xuartps_release_port - Release the memory region attached to a xuartps
903  *                              port, called when the driver removes a xuartps
904  *                              port via uart_remove_one_port().
905  * @port: Handle to the uart port structure
906  *
907  **/
908 static void xuartps_release_port(struct uart_port *port)
909 {
910         release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
911         iounmap(port->membase);
912         port->membase = NULL;
913 }
914 
915 /**
916  * xuartps_config_port - Configure xuartps, called when the driver adds a
917  *                              xuartps port
918  * @port: Handle to the uart port structure
919  * @flags: If any
920  *
921  **/
922 static void xuartps_config_port(struct uart_port *port, int flags)
923 {
924         if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0)
925                 port->type = PORT_XUARTPS;
926 }
927 
928 /**
929  * xuartps_get_mctrl - Get the modem control state
930  *
931  * @port: Handle to the uart port structure
932  *
933  * Returns the modem control state
934  *
935  **/
936 static unsigned int xuartps_get_mctrl(struct uart_port *port)
937 {
938         return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
939 }
940 
941 static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl)
942 {
943         /* N/A */
944 }
945 
946 static void xuartps_enable_ms(struct uart_port *port)
947 {
948         /* N/A */
949 }
950 
951 #ifdef CONFIG_CONSOLE_POLL
952 static int xuartps_poll_get_char(struct uart_port *port)
953 {
954         u32 imr;
955         int c;
956 
957         /* Disable all interrupts */
958         imr = xuartps_readl(XUARTPS_IMR_OFFSET);
959         xuartps_writel(imr, XUARTPS_IDR_OFFSET);
960 
961         /* Check if FIFO is empty */
962         if (xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY)
963                 c = NO_POLL_CHAR;
964         else /* Read a character */
965                 c = (unsigned char) xuartps_readl(XUARTPS_FIFO_OFFSET);
966 
967         /* Enable interrupts */
968         xuartps_writel(imr, XUARTPS_IER_OFFSET);
969 
970         return c;
971 }
972 
973 static void xuartps_poll_put_char(struct uart_port *port, unsigned char c)
974 {
975         u32 imr;
976 
977         /* Disable all interrupts */
978         imr = xuartps_readl(XUARTPS_IMR_OFFSET);
979         xuartps_writel(imr, XUARTPS_IDR_OFFSET);
980 
981         /* Wait until FIFO is empty */
982         while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY))
983                 cpu_relax();
984 
985         /* Write a character */
986         xuartps_writel(c, XUARTPS_FIFO_OFFSET);
987 
988         /* Wait until FIFO is empty */
989         while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY))
990                 cpu_relax();
991 
992         /* Enable interrupts */
993         xuartps_writel(imr, XUARTPS_IER_OFFSET);
994 
995         return;
996 }
997 #endif
998 
999 /** The UART operations structure
1000  */
1001 static struct uart_ops xuartps_ops = {
1002         .set_mctrl      = xuartps_set_mctrl,
1003         .get_mctrl      = xuartps_get_mctrl,
1004         .enable_ms      = xuartps_enable_ms,
1005 
1006         .start_tx       = xuartps_start_tx,     /* Start transmitting */
1007         .stop_tx        = xuartps_stop_tx,      /* Stop transmission */
1008         .stop_rx        = xuartps_stop_rx,      /* Stop reception */
1009         .tx_empty       = xuartps_tx_empty,     /* Transmitter busy? */
1010         .break_ctl      = xuartps_break_ctl,    /* Start/stop
1011                                                  * transmitting break
1012                                                  */
1013         .set_termios    = xuartps_set_termios,  /* Set termios */
1014         .startup        = xuartps_startup,      /* App opens xuartps */
1015         .shutdown       = xuartps_shutdown,     /* App closes xuartps */
1016         .type           = xuartps_type,         /* Set UART type */
1017         .verify_port    = xuartps_verify_port,  /* Verification of port
1018                                                  * params
1019                                                  */
1020         .request_port   = xuartps_request_port, /* Claim resources
1021                                                  * associated with a
1022                                                  * xuartps port
1023                                                  */
1024         .release_port   = xuartps_release_port, /* Release resources
1025                                                  * associated with a
1026                                                  * xuartps port
1027                                                  */
1028         .config_port    = xuartps_config_port,  /* Configure when driver
1029                                                  * adds a xuartps port
1030                                                  */
1031 #ifdef CONFIG_CONSOLE_POLL
1032         .poll_get_char  = xuartps_poll_get_char,
1033         .poll_put_char  = xuartps_poll_put_char,
1034 #endif
1035 };
1036 
1037 static struct uart_port xuartps_port[2];
1038 
1039 /**
1040  * xuartps_get_port - Configure the port from the platform device resource
1041  *                      info
1042  *
1043  * Returns a pointer to a uart_port or NULL for failure
1044  **/
1045 static struct uart_port *xuartps_get_port(void)
1046 {
1047         struct uart_port *port;
1048         int id;
1049 
1050         /* Find the next unused port */
1051         for (id = 0; id < XUARTPS_NR_PORTS; id++)
1052                 if (xuartps_port[id].mapbase == 0)
1053                         break;
1054 
1055         if (id >= XUARTPS_NR_PORTS)
1056                 return NULL;
1057 
1058         port = &xuartps_port[id];
1059 
1060         /* At this point, we've got an empty uart_port struct, initialize it */
1061         spin_lock_init(&port->lock);
1062         port->membase   = NULL;
1063         port->iobase    = 1; /* mark port in use */
1064         port->irq       = 0;
1065         port->type      = PORT_UNKNOWN;
1066         port->iotype    = UPIO_MEM32;
1067         port->flags     = UPF_BOOT_AUTOCONF;
1068         port->ops       = &xuartps_ops;
1069         port->fifosize  = XUARTPS_FIFO_SIZE;
1070         port->line      = id;
1071         port->dev       = NULL;
1072         return port;
1073 }
1074 
1075 /*-----------------------Console driver operations--------------------------*/
1076 
1077 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1078 /**
1079  * xuartps_console_wait_tx - Wait for the TX to be full
1080  * @port: Handle to the uart port structure
1081  *
1082  **/
1083 static void xuartps_console_wait_tx(struct uart_port *port)
1084 {
1085         while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)
1086                                 != XUARTPS_SR_TXEMPTY)
1087                 barrier();
1088 }
1089 
1090 /**
1091  * xuartps_console_putchar - write the character to the FIFO buffer
1092  * @port: Handle to the uart port structure
1093  * @ch: Character to be written
1094  *
1095  **/
1096 static void xuartps_console_putchar(struct uart_port *port, int ch)
1097 {
1098         xuartps_console_wait_tx(port);
1099         xuartps_writel(ch, XUARTPS_FIFO_OFFSET);
1100 }
1101 
1102 /**
1103  * xuartps_console_write - perform write operation
1104  * @port: Handle to the uart port structure
1105  * @s: Pointer to character array
1106  * @count: No of characters
1107  **/
1108 static void xuartps_console_write(struct console *co, const char *s,
1109                                 unsigned int count)
1110 {
1111         struct uart_port *port = &xuartps_port[co->index];
1112         unsigned long flags;
1113         unsigned int imr, ctrl;
1114         int locked = 1;
1115 
1116         if (oops_in_progress)
1117                 locked = spin_trylock_irqsave(&port->lock, flags);
1118         else
1119                 spin_lock_irqsave(&port->lock, flags);
1120 
1121         /* save and disable interrupt */
1122         imr = xuartps_readl(XUARTPS_IMR_OFFSET);
1123         xuartps_writel(imr, XUARTPS_IDR_OFFSET);
1124 
1125         /*
1126          * Make sure that the tx part is enabled. Set the TX enable bit and
1127          * clear the TX disable bit to enable the transmitter.
1128          */
1129         ctrl = xuartps_readl(XUARTPS_CR_OFFSET);
1130         xuartps_writel((ctrl & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
1131                 XUARTPS_CR_OFFSET);
1132 
1133         uart_console_write(port, s, count, xuartps_console_putchar);
1134         xuartps_console_wait_tx(port);
1135 
1136         xuartps_writel(ctrl, XUARTPS_CR_OFFSET);
1137 
1138         /* restore interrupt state, it seems like there may be a h/w bug
1139          * in that the interrupt enable register should not need to be
1140          * written based on the data sheet
1141          */
1142         xuartps_writel(~imr, XUARTPS_IDR_OFFSET);
1143         xuartps_writel(imr, XUARTPS_IER_OFFSET);
1144 
1145         if (locked)
1146                 spin_unlock_irqrestore(&port->lock, flags);
1147 }
1148 
1149 /**
1150  * xuartps_console_setup - Initialize the uart to default config
1151  * @co: Console handle
1152  * @options: Initial settings of uart
1153  *
1154  * Returns 0, -ENODEV if no device
1155  **/
1156 static int __init xuartps_console_setup(struct console *co, char *options)
1157 {
1158         struct uart_port *port = &xuartps_port[co->index];
1159         int baud = 9600;
1160         int bits = 8;
1161         int parity = 'n';
1162         int flow = 'n';
1163 
1164         if (co->index < 0 || co->index >= XUARTPS_NR_PORTS)
1165                 return -EINVAL;
1166 
1167         if (!port->mapbase) {
1168                 pr_debug("console on ttyPS%i not present\n", co->index);
1169                 return -ENODEV;
1170         }
1171 
1172         if (options)
1173                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1174 
1175         return uart_set_options(port, co, baud, parity, bits, flow);
1176 }
1177 
1178 static struct uart_driver xuartps_uart_driver;
1179 
1180 static struct console xuartps_console = {
1181         .name   = XUARTPS_TTY_NAME,
1182         .write  = xuartps_console_write,
1183         .device = uart_console_device,
1184         .setup  = xuartps_console_setup,
1185         .flags  = CON_PRINTBUFFER,
1186         .index  = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1187         .data   = &xuartps_uart_driver,
1188 };
1189 
1190 /**
1191  * xuartps_console_init - Initialization call
1192  *
1193  * Returns 0 on success, negative error otherwise
1194  **/
1195 static int __init xuartps_console_init(void)
1196 {
1197         register_console(&xuartps_console);
1198         return 0;
1199 }
1200 
1201 console_initcall(xuartps_console_init);
1202 
1203 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1204 
1205 /** Structure Definitions
1206  */
1207 static struct uart_driver xuartps_uart_driver = {
1208         .owner          = THIS_MODULE,          /* Owner */
1209         .driver_name    = XUARTPS_NAME,         /* Driver name */
1210         .dev_name       = XUARTPS_TTY_NAME,     /* Node name */
1211         .major          = XUARTPS_MAJOR,        /* Major number */
1212         .minor          = XUARTPS_MINOR,        /* Minor number */
1213         .nr             = XUARTPS_NR_PORTS,     /* Number of UART ports */
1214 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1215         .cons           = &xuartps_console,     /* Console */
1216 #endif
1217 };
1218 
1219 #ifdef CONFIG_PM_SLEEP
1220 /**
1221  * xuartps_suspend - suspend event
1222  * @device: Pointer to the device structure
1223  *
1224  * Returns 0
1225  */
1226 static int xuartps_suspend(struct device *device)
1227 {
1228         struct uart_port *port = dev_get_drvdata(device);
1229         struct tty_struct *tty;
1230         struct device *tty_dev;
1231         int may_wake = 0;
1232 
1233         /* Get the tty which could be NULL so don't assume it's valid */
1234         tty = tty_port_tty_get(&port->state->port);
1235         if (tty) {
1236                 tty_dev = tty->dev;
1237                 may_wake = device_may_wakeup(tty_dev);
1238                 tty_kref_put(tty);
1239         }
1240 
1241         /*
1242          * Call the API provided in serial_core.c file which handles
1243          * the suspend.
1244          */
1245         uart_suspend_port(&xuartps_uart_driver, port);
1246         if (console_suspend_enabled && !may_wake) {
1247                 struct xuartps *xuartps = port->private_data;
1248 
1249                 clk_disable(xuartps->refclk);
1250                 clk_disable(xuartps->aperclk);
1251         } else {
1252                 unsigned long flags = 0;
1253 
1254                 spin_lock_irqsave(&port->lock, flags);
1255                 /* Empty the receive FIFO 1st before making changes */
1256                 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY))
1257                         xuartps_readl(XUARTPS_FIFO_OFFSET);
1258                 /* set RX trigger level to 1 */
1259                 xuartps_writel(1, XUARTPS_RXWM_OFFSET);
1260                 /* disable RX timeout interrups */
1261                 xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IDR_OFFSET);
1262                 spin_unlock_irqrestore(&port->lock, flags);
1263         }
1264 
1265         return 0;
1266 }
1267 
1268 /**
1269  * xuartps_resume - Resume after a previous suspend
1270  * @device: Pointer to the device structure
1271  *
1272  * Returns 0
1273  */
1274 static int xuartps_resume(struct device *device)
1275 {
1276         struct uart_port *port = dev_get_drvdata(device);
1277         unsigned long flags = 0;
1278         u32 ctrl_reg;
1279         struct tty_struct *tty;
1280         struct device *tty_dev;
1281         int may_wake = 0;
1282 
1283         /* Get the tty which could be NULL so don't assume it's valid */
1284         tty = tty_port_tty_get(&port->state->port);
1285         if (tty) {
1286                 tty_dev = tty->dev;
1287                 may_wake = device_may_wakeup(tty_dev);
1288                 tty_kref_put(tty);
1289         }
1290 
1291         if (console_suspend_enabled && !may_wake) {
1292                 struct xuartps *xuartps = port->private_data;
1293 
1294                 clk_enable(xuartps->aperclk);
1295                 clk_enable(xuartps->refclk);
1296 
1297                 spin_lock_irqsave(&port->lock, flags);
1298 
1299                 /* Set TX/RX Reset */
1300                 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
1301                                 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
1302                                 XUARTPS_CR_OFFSET);
1303                 while (xuartps_readl(XUARTPS_CR_OFFSET) &
1304                                 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST))
1305                         cpu_relax();
1306 
1307                 /* restore rx timeout value */
1308                 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
1309                 /* Enable Tx/Rx */
1310                 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
1311                 xuartps_writel(
1312                         (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) |
1313                         (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
1314                         XUARTPS_CR_OFFSET);
1315 
1316                 spin_unlock_irqrestore(&port->lock, flags);
1317         } else {
1318                 spin_lock_irqsave(&port->lock, flags);
1319                 /* restore original rx trigger level */
1320                 xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET);
1321                 /* enable RX timeout interrupt */
1322                 xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
1323                 spin_unlock_irqrestore(&port->lock, flags);
1324         }
1325 
1326         return uart_resume_port(&xuartps_uart_driver, port);
1327 }
1328 #endif /* ! CONFIG_PM_SLEEP */
1329 
1330 static SIMPLE_DEV_PM_OPS(xuartps_dev_pm_ops, xuartps_suspend, xuartps_resume);
1331 
1332 /* ---------------------------------------------------------------------
1333  * Platform bus binding
1334  */
1335 /**
1336  * xuartps_probe - Platform driver probe
1337  * @pdev: Pointer to the platform device structure
1338  *
1339  * Returns 0 on success, negative error otherwise
1340  **/
1341 static int xuartps_probe(struct platform_device *pdev)
1342 {
1343         int rc;
1344         struct uart_port *port;
1345         struct resource *res, *res2;
1346         struct xuartps *xuartps_data;
1347 
1348         xuartps_data = devm_kzalloc(&pdev->dev, sizeof(*xuartps_data),
1349                         GFP_KERNEL);
1350         if (!xuartps_data)
1351                 return -ENOMEM;
1352 
1353         xuartps_data->aperclk = devm_clk_get(&pdev->dev, "aper_clk");
1354         if (IS_ERR(xuartps_data->aperclk)) {
1355                 dev_err(&pdev->dev, "aper_clk clock not found.\n");
1356                 return PTR_ERR(xuartps_data->aperclk);
1357         }
1358         xuartps_data->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1359         if (IS_ERR(xuartps_data->refclk)) {
1360                 dev_err(&pdev->dev, "ref_clk clock not found.\n");
1361                 return PTR_ERR(xuartps_data->refclk);
1362         }
1363 
1364         rc = clk_prepare_enable(xuartps_data->aperclk);
1365         if (rc) {
1366                 dev_err(&pdev->dev, "Unable to enable APER clock.\n");
1367                 return rc;
1368         }
1369         rc = clk_prepare_enable(xuartps_data->refclk);
1370         if (rc) {
1371                 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1372                 goto err_out_clk_dis_aper;
1373         }
1374 
1375         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1376         if (!res) {
1377                 rc = -ENODEV;
1378                 goto err_out_clk_disable;
1379         }
1380 
1381         res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1382         if (!res2) {
1383                 rc = -ENODEV;
1384                 goto err_out_clk_disable;
1385         }
1386 
1387 #ifdef CONFIG_COMMON_CLK
1388         xuartps_data->clk_rate_change_nb.notifier_call =
1389                         xuartps_clk_notifier_cb;
1390         if (clk_notifier_register(xuartps_data->refclk,
1391                                 &xuartps_data->clk_rate_change_nb))
1392                 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1393 #endif
1394 
1395         /* Initialize the port structure */
1396         port = xuartps_get_port();
1397 
1398         if (!port) {
1399                 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1400                 rc = -ENODEV;
1401                 goto err_out_notif_unreg;
1402         } else {
1403                 /* Register the port.
1404                  * This function also registers this device with the tty layer
1405                  * and triggers invocation of the config_port() entry point.
1406                  */
1407                 port->mapbase = res->start;
1408                 port->irq = res2->start;
1409                 port->dev = &pdev->dev;
1410                 port->uartclk = clk_get_rate(xuartps_data->refclk);
1411                 port->private_data = xuartps_data;
1412                 xuartps_data->port = port;
1413                 platform_set_drvdata(pdev, port);
1414                 rc = uart_add_one_port(&xuartps_uart_driver, port);
1415                 if (rc) {
1416                         dev_err(&pdev->dev,
1417                                 "uart_add_one_port() failed; err=%i\n", rc);
1418                         goto err_out_notif_unreg;
1419                 }
1420                 return 0;
1421         }
1422 
1423 err_out_notif_unreg:
1424 #ifdef CONFIG_COMMON_CLK
1425         clk_notifier_unregister(xuartps_data->refclk,
1426                         &xuartps_data->clk_rate_change_nb);
1427 #endif
1428 err_out_clk_disable:
1429         clk_disable_unprepare(xuartps_data->refclk);
1430 err_out_clk_dis_aper:
1431         clk_disable_unprepare(xuartps_data->aperclk);
1432 
1433         return rc;
1434 }
1435 
1436 /**
1437  * xuartps_remove - called when the platform driver is unregistered
1438  * @pdev: Pointer to the platform device structure
1439  *
1440  * Returns 0 on success, negative error otherwise
1441  **/
1442 static int xuartps_remove(struct platform_device *pdev)
1443 {
1444         struct uart_port *port = platform_get_drvdata(pdev);
1445         struct xuartps *xuartps_data = port->private_data;
1446         int rc;
1447 
1448         /* Remove the xuartps port from the serial core */
1449 #ifdef CONFIG_COMMON_CLK
1450         clk_notifier_unregister(xuartps_data->refclk,
1451                         &xuartps_data->clk_rate_change_nb);
1452 #endif
1453         rc = uart_remove_one_port(&xuartps_uart_driver, port);
1454         port->mapbase = 0;
1455         clk_disable_unprepare(xuartps_data->refclk);
1456         clk_disable_unprepare(xuartps_data->aperclk);
1457         return rc;
1458 }
1459 
1460 /* Match table for of_platform binding */
1461 static struct of_device_id xuartps_of_match[] = {
1462         { .compatible = "xlnx,xuartps", },
1463         {}
1464 };
1465 MODULE_DEVICE_TABLE(of, xuartps_of_match);
1466 
1467 static struct platform_driver xuartps_platform_driver = {
1468         .probe   = xuartps_probe,               /* Probe method */
1469         .remove  = xuartps_remove,              /* Detach method */
1470         .driver  = {
1471                 .owner = THIS_MODULE,
1472                 .name = XUARTPS_NAME,           /* Driver name */
1473                 .of_match_table = xuartps_of_match,
1474                 .pm = &xuartps_dev_pm_ops,
1475                 },
1476 };
1477 
1478 /* ---------------------------------------------------------------------
1479  * Module Init and Exit
1480  */
1481 /**
1482  * xuartps_init - Initial driver registration call
1483  *
1484  * Returns whether the registration was successful or not
1485  **/
1486 static int __init xuartps_init(void)
1487 {
1488         int retval = 0;
1489 
1490         /* Register the xuartps driver with the serial core */
1491         retval = uart_register_driver(&xuartps_uart_driver);
1492         if (retval)
1493                 return retval;
1494 
1495         /* Register the platform driver */
1496         retval = platform_driver_register(&xuartps_platform_driver);
1497         if (retval)
1498                 uart_unregister_driver(&xuartps_uart_driver);
1499 
1500         return retval;
1501 }
1502 
1503 /**
1504  * xuartps_exit - Driver unregistration call
1505  **/
1506 static void __exit xuartps_exit(void)
1507 {
1508         /* The order of unregistration is important. Unregister the
1509          * UART driver before the platform driver crashes the system.
1510          */
1511 
1512         /* Unregister the platform driver */
1513         platform_driver_unregister(&xuartps_platform_driver);
1514 
1515         /* Unregister the xuartps driver */
1516         uart_unregister_driver(&xuartps_uart_driver);
1517 }
1518 
1519 module_init(xuartps_init);
1520 module_exit(xuartps_exit);
1521 
1522 MODULE_DESCRIPTION("Driver for PS UART");
1523 MODULE_AUTHOR("Xilinx Inc.");
1524 MODULE_LICENSE("GPL");
1525 

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