Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/tty/serial/sunsab.c

  1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
  2  *
  3  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
  4  * Copyright (C) 2002, 2006  David S. Miller (davem@davemloft.net)
  5  *
  6  * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
  7  *   Maxim Krasnyanskiy <maxk@qualcomm.com>
  8  *
  9  * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
 10  * rates to be programmed into the UART.  Also eliminated a lot of
 11  * duplicated code in the console setup.
 12  *   Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
 13  *
 14  * Ported to new 2.5.x UART layer.
 15  *   David S. Miller <davem@davemloft.net>
 16  */
 17 
 18 #include <linux/module.h>
 19 #include <linux/kernel.h>
 20 #include <linux/errno.h>
 21 #include <linux/tty.h>
 22 #include <linux/tty_flip.h>
 23 #include <linux/major.h>
 24 #include <linux/string.h>
 25 #include <linux/ptrace.h>
 26 #include <linux/ioport.h>
 27 #include <linux/circ_buf.h>
 28 #include <linux/serial.h>
 29 #include <linux/sysrq.h>
 30 #include <linux/console.h>
 31 #include <linux/spinlock.h>
 32 #include <linux/slab.h>
 33 #include <linux/delay.h>
 34 #include <linux/init.h>
 35 #include <linux/of_device.h>
 36 
 37 #include <asm/io.h>
 38 #include <asm/irq.h>
 39 #include <asm/prom.h>
 40 #include <asm/setup.h>
 41 
 42 #if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 43 #define SUPPORT_SYSRQ
 44 #endif
 45 
 46 #include <linux/serial_core.h>
 47 #include <linux/sunserialcore.h>
 48 
 49 #include "sunsab.h"
 50 
 51 struct uart_sunsab_port {
 52         struct uart_port                port;           /* Generic UART port    */
 53         union sab82532_async_regs       __iomem *regs;  /* Chip registers       */
 54         unsigned long                   irqflags;       /* IRQ state flags      */
 55         int                             dsr;            /* Current DSR state    */
 56         unsigned int                    cec_timeout;    /* Chip poll timeout... */
 57         unsigned int                    tec_timeout;    /* likewise             */
 58         unsigned char                   interrupt_mask0;/* ISR0 masking         */
 59         unsigned char                   interrupt_mask1;/* ISR1 masking         */
 60         unsigned char                   pvr_dtr_bit;    /* Which PVR bit is DTR */
 61         unsigned char                   pvr_dsr_bit;    /* Which PVR bit is DSR */
 62         unsigned int                    gis_shift;
 63         int                             type;           /* SAB82532 version     */
 64 
 65         /* Setting configuration bits while the transmitter is active
 66          * can cause garbage characters to get emitted by the chip.
 67          * Therefore, we cache such writes here and do the real register
 68          * write the next time the transmitter becomes idle.
 69          */
 70         unsigned int                    cached_ebrg;
 71         unsigned char                   cached_mode;
 72         unsigned char                   cached_pvr;
 73         unsigned char                   cached_dafo;
 74 };
 75 
 76 /*
 77  * This assumes you have a 29.4912 MHz clock for your UART.
 78  */
 79 #define SAB_BASE_BAUD ( 29491200 / 16 )
 80 
 81 static char *sab82532_version[16] = {
 82         "V1.0", "V2.0", "V3.2", "V(0x03)",
 83         "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
 84         "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
 85         "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
 86 };
 87 
 88 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
 89 #define SAB82532_MAX_CEC_TIMEOUT  50000 /* 2.5 TX CLKs (at 50 baud) */
 90 
 91 #define SAB82532_RECV_FIFO_SIZE 32      /* Standard async fifo sizes */
 92 #define SAB82532_XMIT_FIFO_SIZE 32
 93 
 94 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
 95 {
 96         int timeout = up->tec_timeout;
 97 
 98         while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
 99                 udelay(1);
100 }
101 
102 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
103 {
104         int timeout = up->cec_timeout;
105 
106         while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
107                 udelay(1);
108 }
109 
110 static struct tty_port *
111 receive_chars(struct uart_sunsab_port *up,
112               union sab82532_irq_status *stat)
113 {
114         struct tty_port *port = NULL;
115         unsigned char buf[32];
116         int saw_console_brk = 0;
117         int free_fifo = 0;
118         int count = 0;
119         int i;
120 
121         if (up->port.state != NULL)             /* Unopened serial console */
122                 port = &up->port.state->port;
123 
124         /* Read number of BYTES (Character + Status) available. */
125         if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
126                 count = SAB82532_RECV_FIFO_SIZE;
127                 free_fifo++;
128         }
129 
130         if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
131                 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
132                 free_fifo++;
133         }
134 
135         /* Issue a FIFO read command in case we where idle. */
136         if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
137                 sunsab_cec_wait(up);
138                 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
139                 return port;
140         }
141 
142         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
143                 free_fifo++;
144 
145         /* Read the FIFO. */
146         for (i = 0; i < count; i++)
147                 buf[i] = readb(&up->regs->r.rfifo[i]);
148 
149         /* Issue Receive Message Complete command. */
150         if (free_fifo) {
151                 sunsab_cec_wait(up);
152                 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
153         }
154 
155         /* Count may be zero for BRK, so we check for it here */
156         if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
157             (up->port.line == up->port.cons->index))
158                 saw_console_brk = 1;
159 
160         if (count == 0) {
161                 if (unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
162                         stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
163                                              SAB82532_ISR0_FERR);
164                         up->port.icount.brk++;
165                         uart_handle_break(&up->port);
166                 }
167         }
168 
169         for (i = 0; i < count; i++) {
170                 unsigned char ch = buf[i], flag;
171 
172                 flag = TTY_NORMAL;
173                 up->port.icount.rx++;
174 
175                 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
176                                                 SAB82532_ISR0_FERR |
177                                                 SAB82532_ISR0_RFO)) ||
178                     unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
179                         /*
180                          * For statistics only
181                          */
182                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
183                                 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
184                                                      SAB82532_ISR0_FERR);
185                                 up->port.icount.brk++;
186                                 /*
187                                  * We do the SysRQ and SAK checking
188                                  * here because otherwise the break
189                                  * may get masked by ignore_status_mask
190                                  * or read_status_mask.
191                                  */
192                                 if (uart_handle_break(&up->port))
193                                         continue;
194                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
195                                 up->port.icount.parity++;
196                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
197                                 up->port.icount.frame++;
198                         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
199                                 up->port.icount.overrun++;
200 
201                         /*
202                          * Mask off conditions which should be ingored.
203                          */
204                         stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
205                         stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
206 
207                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
208                                 flag = TTY_BREAK;
209                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
210                                 flag = TTY_PARITY;
211                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
212                                 flag = TTY_FRAME;
213                 }
214 
215                 if (uart_handle_sysrq_char(&up->port, ch) || !port)
216                         continue;
217 
218                 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
219                     (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
220                         tty_insert_flip_char(port, ch, flag);
221                 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
222                         tty_insert_flip_char(port, 0, TTY_OVERRUN);
223         }
224 
225         if (saw_console_brk)
226                 sun_do_break();
227 
228         return port;
229 }
230 
231 static void sunsab_stop_tx(struct uart_port *);
232 static void sunsab_tx_idle(struct uart_sunsab_port *);
233 
234 static void transmit_chars(struct uart_sunsab_port *up,
235                            union sab82532_irq_status *stat)
236 {
237         struct circ_buf *xmit = &up->port.state->xmit;
238         int i;
239 
240         if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
241                 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
242                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
243                 set_bit(SAB82532_ALLS, &up->irqflags);
244         }
245 
246 #if 0 /* bde@nwlink.com says this check causes problems */
247         if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
248                 return;
249 #endif
250 
251         if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
252                 return;
253 
254         set_bit(SAB82532_XPR, &up->irqflags);
255         sunsab_tx_idle(up);
256 
257         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
258                 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
259                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
260                 return;
261         }
262 
263         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
264         writeb(up->interrupt_mask1, &up->regs->w.imr1);
265         clear_bit(SAB82532_ALLS, &up->irqflags);
266 
267         /* Stuff 32 bytes into Transmit FIFO. */
268         clear_bit(SAB82532_XPR, &up->irqflags);
269         for (i = 0; i < up->port.fifosize; i++) {
270                 writeb(xmit->buf[xmit->tail],
271                        &up->regs->w.xfifo[i]);
272                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
273                 up->port.icount.tx++;
274                 if (uart_circ_empty(xmit))
275                         break;
276         }
277 
278         /* Issue a Transmit Frame command. */
279         sunsab_cec_wait(up);
280         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
281 
282         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
283                 uart_write_wakeup(&up->port);
284 
285         if (uart_circ_empty(xmit))
286                 sunsab_stop_tx(&up->port);
287 }
288 
289 static void check_status(struct uart_sunsab_port *up,
290                          union sab82532_irq_status *stat)
291 {
292         if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
293                 uart_handle_dcd_change(&up->port,
294                                        !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
295 
296         if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
297                 uart_handle_cts_change(&up->port,
298                                        (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
299 
300         if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
301                 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
302                 up->port.icount.dsr++;
303         }
304 
305         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
306 }
307 
308 static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
309 {
310         struct uart_sunsab_port *up = dev_id;
311         struct tty_port *port = NULL;
312         union sab82532_irq_status status;
313         unsigned long flags;
314         unsigned char gis;
315 
316         spin_lock_irqsave(&up->port.lock, flags);
317 
318         status.stat = 0;
319         gis = readb(&up->regs->r.gis) >> up->gis_shift;
320         if (gis & 1)
321                 status.sreg.isr0 = readb(&up->regs->r.isr0);
322         if (gis & 2)
323                 status.sreg.isr1 = readb(&up->regs->r.isr1);
324 
325         if (status.stat) {
326                 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
327                                          SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
328                     (status.sreg.isr1 & SAB82532_ISR1_BRK))
329                         port = receive_chars(up, &status);
330                 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
331                     (status.sreg.isr1 & SAB82532_ISR1_CSC))
332                         check_status(up, &status);
333                 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
334                         transmit_chars(up, &status);
335         }
336 
337         spin_unlock_irqrestore(&up->port.lock, flags);
338 
339         if (port)
340                 tty_flip_buffer_push(port);
341 
342         return IRQ_HANDLED;
343 }
344 
345 /* port->lock is not held.  */
346 static unsigned int sunsab_tx_empty(struct uart_port *port)
347 {
348         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
349         int ret;
350 
351         /* Do not need a lock for a state test like this.  */
352         if (test_bit(SAB82532_ALLS, &up->irqflags))
353                 ret = TIOCSER_TEMT;
354         else
355                 ret = 0;
356 
357         return ret;
358 }
359 
360 /* port->lock held by caller.  */
361 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
362 {
363         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
364 
365         if (mctrl & TIOCM_RTS) {
366                 up->cached_mode &= ~SAB82532_MODE_FRTS;
367                 up->cached_mode |= SAB82532_MODE_RTS;
368         } else {
369                 up->cached_mode |= (SAB82532_MODE_FRTS |
370                                     SAB82532_MODE_RTS);
371         }
372         if (mctrl & TIOCM_DTR) {
373                 up->cached_pvr &= ~(up->pvr_dtr_bit);
374         } else {
375                 up->cached_pvr |= up->pvr_dtr_bit;
376         }
377 
378         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
379         if (test_bit(SAB82532_XPR, &up->irqflags))
380                 sunsab_tx_idle(up);
381 }
382 
383 /* port->lock is held by caller and interrupts are disabled.  */
384 static unsigned int sunsab_get_mctrl(struct uart_port *port)
385 {
386         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
387         unsigned char val;
388         unsigned int result;
389 
390         result = 0;
391 
392         val = readb(&up->regs->r.pvr);
393         result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
394 
395         val = readb(&up->regs->r.vstr);
396         result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
397 
398         val = readb(&up->regs->r.star);
399         result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
400 
401         return result;
402 }
403 
404 /* port->lock held by caller.  */
405 static void sunsab_stop_tx(struct uart_port *port)
406 {
407         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
408 
409         up->interrupt_mask1 |= SAB82532_IMR1_XPR;
410         writeb(up->interrupt_mask1, &up->regs->w.imr1);
411 }
412 
413 /* port->lock held by caller.  */
414 static void sunsab_tx_idle(struct uart_sunsab_port *up)
415 {
416         if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
417                 u8 tmp;
418 
419                 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
420                 writeb(up->cached_mode, &up->regs->rw.mode);
421                 writeb(up->cached_pvr, &up->regs->rw.pvr);
422                 writeb(up->cached_dafo, &up->regs->w.dafo);
423 
424                 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
425                 tmp = readb(&up->regs->rw.ccr2);
426                 tmp &= ~0xc0;
427                 tmp |= (up->cached_ebrg >> 2) & 0xc0;
428                 writeb(tmp, &up->regs->rw.ccr2);
429         }
430 }
431 
432 /* port->lock held by caller.  */
433 static void sunsab_start_tx(struct uart_port *port)
434 {
435         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
436         struct circ_buf *xmit = &up->port.state->xmit;
437         int i;
438 
439         if (uart_circ_empty(xmit))
440                 return;
441 
442         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
443         writeb(up->interrupt_mask1, &up->regs->w.imr1);
444         
445         if (!test_bit(SAB82532_XPR, &up->irqflags))
446                 return;
447 
448         clear_bit(SAB82532_ALLS, &up->irqflags);
449         clear_bit(SAB82532_XPR, &up->irqflags);
450 
451         for (i = 0; i < up->port.fifosize; i++) {
452                 writeb(xmit->buf[xmit->tail],
453                        &up->regs->w.xfifo[i]);
454                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
455                 up->port.icount.tx++;
456                 if (uart_circ_empty(xmit))
457                         break;
458         }
459 
460         /* Issue a Transmit Frame command.  */
461         sunsab_cec_wait(up);
462         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
463 }
464 
465 /* port->lock is not held.  */
466 static void sunsab_send_xchar(struct uart_port *port, char ch)
467 {
468         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
469         unsigned long flags;
470 
471         spin_lock_irqsave(&up->port.lock, flags);
472 
473         sunsab_tec_wait(up);
474         writeb(ch, &up->regs->w.tic);
475 
476         spin_unlock_irqrestore(&up->port.lock, flags);
477 }
478 
479 /* port->lock held by caller.  */
480 static void sunsab_stop_rx(struct uart_port *port)
481 {
482         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
483 
484         up->interrupt_mask0 |= SAB82532_IMR0_TCD;
485         writeb(up->interrupt_mask1, &up->regs->w.imr0);
486 }
487 
488 /* port->lock is not held.  */
489 static void sunsab_break_ctl(struct uart_port *port, int break_state)
490 {
491         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
492         unsigned long flags;
493         unsigned char val;
494 
495         spin_lock_irqsave(&up->port.lock, flags);
496 
497         val = up->cached_dafo;
498         if (break_state)
499                 val |= SAB82532_DAFO_XBRK;
500         else
501                 val &= ~SAB82532_DAFO_XBRK;
502         up->cached_dafo = val;
503 
504         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
505         if (test_bit(SAB82532_XPR, &up->irqflags))
506                 sunsab_tx_idle(up);
507 
508         spin_unlock_irqrestore(&up->port.lock, flags);
509 }
510 
511 /* port->lock is not held.  */
512 static int sunsab_startup(struct uart_port *port)
513 {
514         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
515         unsigned long flags;
516         unsigned char tmp;
517         int err = request_irq(up->port.irq, sunsab_interrupt,
518                               IRQF_SHARED, "sab", up);
519         if (err)
520                 return err;
521 
522         spin_lock_irqsave(&up->port.lock, flags);
523 
524         /*
525          * Wait for any commands or immediate characters
526          */
527         sunsab_cec_wait(up);
528         sunsab_tec_wait(up);
529 
530         /*
531          * Clear the FIFO buffers.
532          */
533         writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
534         sunsab_cec_wait(up);
535         writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
536 
537         /*
538          * Clear the interrupt registers.
539          */
540         (void) readb(&up->regs->r.isr0);
541         (void) readb(&up->regs->r.isr1);
542 
543         /*
544          * Now, initialize the UART 
545          */
546         writeb(0, &up->regs->w.ccr0);                           /* power-down */
547         writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
548                SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
549         writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
550         writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
551                SAB82532_CCR2_TOE, &up->regs->w.ccr2);
552         writeb(0, &up->regs->w.ccr3);
553         writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
554         up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
555                            SAB82532_MODE_RAC);
556         writeb(up->cached_mode, &up->regs->w.mode);
557         writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
558         
559         tmp = readb(&up->regs->rw.ccr0);
560         tmp |= SAB82532_CCR0_PU;        /* power-up */
561         writeb(tmp, &up->regs->rw.ccr0);
562 
563         /*
564          * Finally, enable interrupts
565          */
566         up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
567                                SAB82532_IMR0_PLLA);
568         writeb(up->interrupt_mask0, &up->regs->w.imr0);
569         up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
570                                SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
571                                SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
572                                SAB82532_IMR1_XPR);
573         writeb(up->interrupt_mask1, &up->regs->w.imr1);
574         set_bit(SAB82532_ALLS, &up->irqflags);
575         set_bit(SAB82532_XPR, &up->irqflags);
576 
577         spin_unlock_irqrestore(&up->port.lock, flags);
578 
579         return 0;
580 }
581 
582 /* port->lock is not held.  */
583 static void sunsab_shutdown(struct uart_port *port)
584 {
585         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
586         unsigned long flags;
587 
588         spin_lock_irqsave(&up->port.lock, flags);
589 
590         /* Disable Interrupts */
591         up->interrupt_mask0 = 0xff;
592         writeb(up->interrupt_mask0, &up->regs->w.imr0);
593         up->interrupt_mask1 = 0xff;
594         writeb(up->interrupt_mask1, &up->regs->w.imr1);
595 
596         /* Disable break condition */
597         up->cached_dafo = readb(&up->regs->rw.dafo);
598         up->cached_dafo &= ~SAB82532_DAFO_XBRK;
599         writeb(up->cached_dafo, &up->regs->rw.dafo);
600 
601         /* Disable Receiver */  
602         up->cached_mode &= ~SAB82532_MODE_RAC;
603         writeb(up->cached_mode, &up->regs->rw.mode);
604 
605         /*
606          * XXX FIXME
607          *
608          * If the chip is powered down here the system hangs/crashes during
609          * reboot or shutdown.  This needs to be investigated further,
610          * similar behaviour occurs in 2.4 when the driver is configured
611          * as a module only.  One hint may be that data is sometimes
612          * transmitted at 9600 baud during shutdown (regardless of the
613          * speed the chip was configured for when the port was open).
614          */
615 #if 0
616         /* Power Down */        
617         tmp = readb(&up->regs->rw.ccr0);
618         tmp &= ~SAB82532_CCR0_PU;
619         writeb(tmp, &up->regs->rw.ccr0);
620 #endif
621 
622         spin_unlock_irqrestore(&up->port.lock, flags);
623         free_irq(up->port.irq, up);
624 }
625 
626 /*
627  * This is used to figure out the divisor speeds.
628  *
629  * The formula is:    Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
630  *
631  * with               0 <= N < 64 and 0 <= M < 16
632  */
633 
634 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
635 {
636         int     n, m;
637 
638         if (baud == 0) {
639                 *n_ret = 0;
640                 *m_ret = 0;
641                 return;
642         }
643      
644         /*
645          * We scale numbers by 10 so that we get better accuracy
646          * without having to use floating point.  Here we increment m
647          * until n is within the valid range.
648          */
649         n = (SAB_BASE_BAUD * 10) / baud;
650         m = 0;
651         while (n >= 640) {
652                 n = n / 2;
653                 m++;
654         }
655         n = (n+5) / 10;
656         /*
657          * We try very hard to avoid speeds with M == 0 since they may
658          * not work correctly for XTAL frequences above 10 MHz.
659          */
660         if ((m == 0) && ((n & 1) == 0)) {
661                 n = n / 2;
662                 m++;
663         }
664         *n_ret = n - 1;
665         *m_ret = m;
666 }
667 
668 /* Internal routine, port->lock is held and local interrupts are disabled.  */
669 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
670                                   unsigned int iflag, unsigned int baud,
671                                   unsigned int quot)
672 {
673         unsigned char dafo;
674         int bits, n, m;
675 
676         /* Byte size and parity */
677         switch (cflag & CSIZE) {
678               case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
679               case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
680               case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
681               case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
682               /* Never happens, but GCC is too dumb to figure it out */
683               default:  dafo = SAB82532_DAFO_CHL5; bits = 7; break;
684         }
685 
686         if (cflag & CSTOPB) {
687                 dafo |= SAB82532_DAFO_STOP;
688                 bits++;
689         }
690 
691         if (cflag & PARENB) {
692                 dafo |= SAB82532_DAFO_PARE;
693                 bits++;
694         }
695 
696         if (cflag & PARODD) {
697                 dafo |= SAB82532_DAFO_PAR_ODD;
698         } else {
699                 dafo |= SAB82532_DAFO_PAR_EVEN;
700         }
701         up->cached_dafo = dafo;
702 
703         calc_ebrg(baud, &n, &m);
704 
705         up->cached_ebrg = n | (m << 6);
706 
707         up->tec_timeout = (10 * 1000000) / baud;
708         up->cec_timeout = up->tec_timeout >> 2;
709 
710         /* CTS flow control flags */
711         /* We encode read_status_mask and ignore_status_mask like so:
712          *
713          * ---------------------
714          * | ... | ISR1 | ISR0 |
715          * ---------------------
716          *  ..    15   8 7    0
717          */
718 
719         up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
720                                      SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
721                                      SAB82532_ISR0_CDSC);
722         up->port.read_status_mask |= (SAB82532_ISR1_CSC |
723                                       SAB82532_ISR1_ALLS |
724                                       SAB82532_ISR1_XPR) << 8;
725         if (iflag & INPCK)
726                 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
727                                               SAB82532_ISR0_FERR);
728         if (iflag & (IGNBRK | BRKINT | PARMRK))
729                 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
730 
731         /*
732          * Characteres to ignore
733          */
734         up->port.ignore_status_mask = 0;
735         if (iflag & IGNPAR)
736                 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
737                                                 SAB82532_ISR0_FERR);
738         if (iflag & IGNBRK) {
739                 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
740                 /*
741                  * If we're ignoring parity and break indicators,
742                  * ignore overruns too (for real raw support).
743                  */
744                 if (iflag & IGNPAR)
745                         up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
746         }
747 
748         /*
749          * ignore all characters if CREAD is not set
750          */
751         if ((cflag & CREAD) == 0)
752                 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
753                                                 SAB82532_ISR0_TCD);
754 
755         uart_update_timeout(&up->port, cflag,
756                             (up->port.uartclk / (16 * quot)));
757 
758         /* Now schedule a register update when the chip's
759          * transmitter is idle.
760          */
761         up->cached_mode |= SAB82532_MODE_RAC;
762         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
763         if (test_bit(SAB82532_XPR, &up->irqflags))
764                 sunsab_tx_idle(up);
765 }
766 
767 /* port->lock is not held.  */
768 static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
769                                struct ktermios *old)
770 {
771         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
772         unsigned long flags;
773         unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
774         unsigned int quot = uart_get_divisor(port, baud);
775 
776         spin_lock_irqsave(&up->port.lock, flags);
777         sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
778         spin_unlock_irqrestore(&up->port.lock, flags);
779 }
780 
781 static const char *sunsab_type(struct uart_port *port)
782 {
783         struct uart_sunsab_port *up = (void *)port;
784         static char buf[36];
785         
786         sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
787         return buf;
788 }
789 
790 static void sunsab_release_port(struct uart_port *port)
791 {
792 }
793 
794 static int sunsab_request_port(struct uart_port *port)
795 {
796         return 0;
797 }
798 
799 static void sunsab_config_port(struct uart_port *port, int flags)
800 {
801 }
802 
803 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
804 {
805         return -EINVAL;
806 }
807 
808 static struct uart_ops sunsab_pops = {
809         .tx_empty       = sunsab_tx_empty,
810         .set_mctrl      = sunsab_set_mctrl,
811         .get_mctrl      = sunsab_get_mctrl,
812         .stop_tx        = sunsab_stop_tx,
813         .start_tx       = sunsab_start_tx,
814         .send_xchar     = sunsab_send_xchar,
815         .stop_rx        = sunsab_stop_rx,
816         .break_ctl      = sunsab_break_ctl,
817         .startup        = sunsab_startup,
818         .shutdown       = sunsab_shutdown,
819         .set_termios    = sunsab_set_termios,
820         .type           = sunsab_type,
821         .release_port   = sunsab_release_port,
822         .request_port   = sunsab_request_port,
823         .config_port    = sunsab_config_port,
824         .verify_port    = sunsab_verify_port,
825 };
826 
827 static struct uart_driver sunsab_reg = {
828         .owner                  = THIS_MODULE,
829         .driver_name            = "sunsab",
830         .dev_name               = "ttyS",
831         .major                  = TTY_MAJOR,
832 };
833 
834 static struct uart_sunsab_port *sunsab_ports;
835 
836 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
837 
838 static void sunsab_console_putchar(struct uart_port *port, int c)
839 {
840         struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
841 
842         sunsab_tec_wait(up);
843         writeb(c, &up->regs->w.tic);
844 }
845 
846 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
847 {
848         struct uart_sunsab_port *up = &sunsab_ports[con->index];
849         unsigned long flags;
850         int locked = 1;
851 
852         if (up->port.sysrq || oops_in_progress)
853                 locked = spin_trylock_irqsave(&up->port.lock, flags);
854         else
855                 spin_lock_irqsave(&up->port.lock, flags);
856 
857         uart_console_write(&up->port, s, n, sunsab_console_putchar);
858         sunsab_tec_wait(up);
859 
860         if (locked)
861                 spin_unlock_irqrestore(&up->port.lock, flags);
862 }
863 
864 static int sunsab_console_setup(struct console *con, char *options)
865 {
866         struct uart_sunsab_port *up = &sunsab_ports[con->index];
867         unsigned long flags;
868         unsigned int baud, quot;
869 
870         /*
871          * The console framework calls us for each and every port
872          * registered. Defer the console setup until the requested
873          * port has been properly discovered. A bit of a hack,
874          * though...
875          */
876         if (up->port.type != PORT_SUNSAB)
877                 return -1;
878 
879         printk("Console: ttyS%d (SAB82532)\n",
880                (sunsab_reg.minor - 64) + con->index);
881 
882         sunserial_console_termios(con, up->port.dev->of_node);
883 
884         switch (con->cflag & CBAUD) {
885         case B150: baud = 150; break;
886         case B300: baud = 300; break;
887         case B600: baud = 600; break;
888         case B1200: baud = 1200; break;
889         case B2400: baud = 2400; break;
890         case B4800: baud = 4800; break;
891         default: case B9600: baud = 9600; break;
892         case B19200: baud = 19200; break;
893         case B38400: baud = 38400; break;
894         case B57600: baud = 57600; break;
895         case B115200: baud = 115200; break;
896         case B230400: baud = 230400; break;
897         case B460800: baud = 460800; break;
898         }
899 
900         /*
901          * Temporary fix.
902          */
903         spin_lock_init(&up->port.lock);
904 
905         /*
906          * Initialize the hardware
907          */
908         sunsab_startup(&up->port);
909 
910         spin_lock_irqsave(&up->port.lock, flags);
911 
912         /*
913          * Finally, enable interrupts
914          */
915         up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
916                                 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
917         writeb(up->interrupt_mask0, &up->regs->w.imr0);
918         up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
919                                 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
920                                 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
921                                 SAB82532_IMR1_XPR;
922         writeb(up->interrupt_mask1, &up->regs->w.imr1);
923 
924         quot = uart_get_divisor(&up->port, baud);
925         sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
926         sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
927 
928         spin_unlock_irqrestore(&up->port.lock, flags);
929         
930         return 0;
931 }
932 
933 static struct console sunsab_console = {
934         .name   =       "ttyS",
935         .write  =       sunsab_console_write,
936         .device =       uart_console_device,
937         .setup  =       sunsab_console_setup,
938         .flags  =       CON_PRINTBUFFER,
939         .index  =       -1,
940         .data   =       &sunsab_reg,
941 };
942 
943 static inline struct console *SUNSAB_CONSOLE(void)
944 {
945         return &sunsab_console;
946 }
947 #else
948 #define SUNSAB_CONSOLE()        (NULL)
949 #define sunsab_console_init()   do { } while (0)
950 #endif
951 
952 static int sunsab_init_one(struct uart_sunsab_port *up,
953                                      struct platform_device *op,
954                                      unsigned long offset,
955                                      int line)
956 {
957         up->port.line = line;
958         up->port.dev = &op->dev;
959 
960         up->port.mapbase = op->resource[0].start + offset;
961         up->port.membase = of_ioremap(&op->resource[0], offset,
962                                       sizeof(union sab82532_async_regs),
963                                       "sab");
964         if (!up->port.membase)
965                 return -ENOMEM;
966         up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
967 
968         up->port.irq = op->archdata.irqs[0];
969 
970         up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
971         up->port.iotype = UPIO_MEM;
972 
973         writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
974 
975         up->port.ops = &sunsab_pops;
976         up->port.type = PORT_SUNSAB;
977         up->port.uartclk = SAB_BASE_BAUD;
978 
979         up->type = readb(&up->regs->r.vstr) & 0x0f;
980         writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
981         writeb(0xff, &up->regs->w.pim);
982         if ((up->port.line & 0x1) == 0) {
983                 up->pvr_dsr_bit = (1 << 0);
984                 up->pvr_dtr_bit = (1 << 1);
985                 up->gis_shift = 2;
986         } else {
987                 up->pvr_dsr_bit = (1 << 3);
988                 up->pvr_dtr_bit = (1 << 2);
989                 up->gis_shift = 0;
990         }
991         up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
992         writeb(up->cached_pvr, &up->regs->w.pvr);
993         up->cached_mode = readb(&up->regs->rw.mode);
994         up->cached_mode |= SAB82532_MODE_FRTS;
995         writeb(up->cached_mode, &up->regs->rw.mode);
996         up->cached_mode |= SAB82532_MODE_RTS;
997         writeb(up->cached_mode, &up->regs->rw.mode);
998 
999         up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1000         up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1001 
1002         return 0;
1003 }
1004 
1005 static int sab_probe(struct platform_device *op)
1006 {
1007         static int inst;
1008         struct uart_sunsab_port *up;
1009         int err;
1010 
1011         up = &sunsab_ports[inst * 2];
1012 
1013         err = sunsab_init_one(&up[0], op,
1014                               0,
1015                               (inst * 2) + 0);
1016         if (err)
1017                 goto out;
1018 
1019         err = sunsab_init_one(&up[1], op,
1020                               sizeof(union sab82532_async_regs),
1021                               (inst * 2) + 1);
1022         if (err)
1023                 goto out1;
1024 
1025         sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1026                                 &sunsab_reg, up[0].port.line,
1027                                 false);
1028 
1029         sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1030                                 &sunsab_reg, up[1].port.line,
1031                                 false);
1032 
1033         err = uart_add_one_port(&sunsab_reg, &up[0].port);
1034         if (err)
1035                 goto out2;
1036 
1037         err = uart_add_one_port(&sunsab_reg, &up[1].port);
1038         if (err)
1039                 goto out3;
1040 
1041         platform_set_drvdata(op, &up[0]);
1042 
1043         inst++;
1044 
1045         return 0;
1046 
1047 out3:
1048         uart_remove_one_port(&sunsab_reg, &up[0].port);
1049 out2:
1050         of_iounmap(&op->resource[0],
1051                    up[1].port.membase,
1052                    sizeof(union sab82532_async_regs));
1053 out1:
1054         of_iounmap(&op->resource[0],
1055                    up[0].port.membase,
1056                    sizeof(union sab82532_async_regs));
1057 out:
1058         return err;
1059 }
1060 
1061 static int sab_remove(struct platform_device *op)
1062 {
1063         struct uart_sunsab_port *up = platform_get_drvdata(op);
1064 
1065         uart_remove_one_port(&sunsab_reg, &up[1].port);
1066         uart_remove_one_port(&sunsab_reg, &up[0].port);
1067         of_iounmap(&op->resource[0],
1068                    up[1].port.membase,
1069                    sizeof(union sab82532_async_regs));
1070         of_iounmap(&op->resource[0],
1071                    up[0].port.membase,
1072                    sizeof(union sab82532_async_regs));
1073 
1074         return 0;
1075 }
1076 
1077 static const struct of_device_id sab_match[] = {
1078         {
1079                 .name = "se",
1080         },
1081         {
1082                 .name = "serial",
1083                 .compatible = "sab82532",
1084         },
1085         {},
1086 };
1087 MODULE_DEVICE_TABLE(of, sab_match);
1088 
1089 static struct platform_driver sab_driver = {
1090         .driver = {
1091                 .name = "sab",
1092                 .owner = THIS_MODULE,
1093                 .of_match_table = sab_match,
1094         },
1095         .probe          = sab_probe,
1096         .remove         = sab_remove,
1097 };
1098 
1099 static int __init sunsab_init(void)
1100 {
1101         struct device_node *dp;
1102         int err;
1103         int num_channels = 0;
1104 
1105         for_each_node_by_name(dp, "se")
1106                 num_channels += 2;
1107         for_each_node_by_name(dp, "serial") {
1108                 if (of_device_is_compatible(dp, "sab82532"))
1109                         num_channels += 2;
1110         }
1111 
1112         if (num_channels) {
1113                 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1114                                        num_channels, GFP_KERNEL);
1115                 if (!sunsab_ports)
1116                         return -ENOMEM;
1117 
1118                 err = sunserial_register_minors(&sunsab_reg, num_channels);
1119                 if (err) {
1120                         kfree(sunsab_ports);
1121                         sunsab_ports = NULL;
1122 
1123                         return err;
1124                 }
1125         }
1126 
1127         return platform_driver_register(&sab_driver);
1128 }
1129 
1130 static void __exit sunsab_exit(void)
1131 {
1132         platform_driver_unregister(&sab_driver);
1133         if (sunsab_reg.nr) {
1134                 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1135         }
1136 
1137         kfree(sunsab_ports);
1138         sunsab_ports = NULL;
1139 }
1140 
1141 module_init(sunsab_init);
1142 module_exit(sunsab_exit);
1143 
1144 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1145 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1146 MODULE_LICENSE("GPL");
1147 

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