Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/tty/serial/sunsab.c

  1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
  2  *
  3  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
  4  * Copyright (C) 2002, 2006  David S. Miller (davem@davemloft.net)
  5  *
  6  * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
  7  *   Maxim Krasnyanskiy <maxk@qualcomm.com>
  8  *
  9  * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
 10  * rates to be programmed into the UART.  Also eliminated a lot of
 11  * duplicated code in the console setup.
 12  *   Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
 13  *
 14  * Ported to new 2.5.x UART layer.
 15  *   David S. Miller <davem@davemloft.net>
 16  */
 17 
 18 #include <linux/module.h>
 19 #include <linux/kernel.h>
 20 #include <linux/errno.h>
 21 #include <linux/tty.h>
 22 #include <linux/tty_flip.h>
 23 #include <linux/major.h>
 24 #include <linux/string.h>
 25 #include <linux/ptrace.h>
 26 #include <linux/ioport.h>
 27 #include <linux/circ_buf.h>
 28 #include <linux/serial.h>
 29 #include <linux/sysrq.h>
 30 #include <linux/console.h>
 31 #include <linux/spinlock.h>
 32 #include <linux/slab.h>
 33 #include <linux/delay.h>
 34 #include <linux/init.h>
 35 #include <linux/of_device.h>
 36 
 37 #include <asm/io.h>
 38 #include <asm/irq.h>
 39 #include <asm/prom.h>
 40 #include <asm/setup.h>
 41 
 42 #if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 43 #define SUPPORT_SYSRQ
 44 #endif
 45 
 46 #include <linux/serial_core.h>
 47 #include <linux/sunserialcore.h>
 48 
 49 #include "sunsab.h"
 50 
 51 struct uart_sunsab_port {
 52         struct uart_port                port;           /* Generic UART port    */
 53         union sab82532_async_regs       __iomem *regs;  /* Chip registers       */
 54         unsigned long                   irqflags;       /* IRQ state flags      */
 55         int                             dsr;            /* Current DSR state    */
 56         unsigned int                    cec_timeout;    /* Chip poll timeout... */
 57         unsigned int                    tec_timeout;    /* likewise             */
 58         unsigned char                   interrupt_mask0;/* ISR0 masking         */
 59         unsigned char                   interrupt_mask1;/* ISR1 masking         */
 60         unsigned char                   pvr_dtr_bit;    /* Which PVR bit is DTR */
 61         unsigned char                   pvr_dsr_bit;    /* Which PVR bit is DSR */
 62         unsigned int                    gis_shift;
 63         int                             type;           /* SAB82532 version     */
 64 
 65         /* Setting configuration bits while the transmitter is active
 66          * can cause garbage characters to get emitted by the chip.
 67          * Therefore, we cache such writes here and do the real register
 68          * write the next time the transmitter becomes idle.
 69          */
 70         unsigned int                    cached_ebrg;
 71         unsigned char                   cached_mode;
 72         unsigned char                   cached_pvr;
 73         unsigned char                   cached_dafo;
 74 };
 75 
 76 /*
 77  * This assumes you have a 29.4912 MHz clock for your UART.
 78  */
 79 #define SAB_BASE_BAUD ( 29491200 / 16 )
 80 
 81 static char *sab82532_version[16] = {
 82         "V1.0", "V2.0", "V3.2", "V(0x03)",
 83         "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
 84         "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
 85         "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
 86 };
 87 
 88 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
 89 #define SAB82532_MAX_CEC_TIMEOUT  50000 /* 2.5 TX CLKs (at 50 baud) */
 90 
 91 #define SAB82532_RECV_FIFO_SIZE 32      /* Standard async fifo sizes */
 92 #define SAB82532_XMIT_FIFO_SIZE 32
 93 
 94 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
 95 {
 96         int timeout = up->tec_timeout;
 97 
 98         while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
 99                 udelay(1);
100 }
101 
102 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
103 {
104         int timeout = up->cec_timeout;
105 
106         while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
107                 udelay(1);
108 }
109 
110 static struct tty_port *
111 receive_chars(struct uart_sunsab_port *up,
112               union sab82532_irq_status *stat)
113 {
114         struct tty_port *port = NULL;
115         unsigned char buf[32];
116         int saw_console_brk = 0;
117         int free_fifo = 0;
118         int count = 0;
119         int i;
120 
121         if (up->port.state != NULL)             /* Unopened serial console */
122                 port = &up->port.state->port;
123 
124         /* Read number of BYTES (Character + Status) available. */
125         if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
126                 count = SAB82532_RECV_FIFO_SIZE;
127                 free_fifo++;
128         }
129 
130         if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
131                 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
132                 free_fifo++;
133         }
134 
135         /* Issue a FIFO read command in case we where idle. */
136         if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
137                 sunsab_cec_wait(up);
138                 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
139                 return port;
140         }
141 
142         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
143                 free_fifo++;
144 
145         /* Read the FIFO. */
146         for (i = 0; i < count; i++)
147                 buf[i] = readb(&up->regs->r.rfifo[i]);
148 
149         /* Issue Receive Message Complete command. */
150         if (free_fifo) {
151                 sunsab_cec_wait(up);
152                 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
153         }
154 
155         /* Count may be zero for BRK, so we check for it here */
156         if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
157             (up->port.line == up->port.cons->index))
158                 saw_console_brk = 1;
159 
160         for (i = 0; i < count; i++) {
161                 unsigned char ch = buf[i], flag;
162 
163                 flag = TTY_NORMAL;
164                 up->port.icount.rx++;
165 
166                 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
167                                                 SAB82532_ISR0_FERR |
168                                                 SAB82532_ISR0_RFO)) ||
169                     unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
170                         /*
171                          * For statistics only
172                          */
173                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
174                                 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
175                                                      SAB82532_ISR0_FERR);
176                                 up->port.icount.brk++;
177                                 /*
178                                  * We do the SysRQ and SAK checking
179                                  * here because otherwise the break
180                                  * may get masked by ignore_status_mask
181                                  * or read_status_mask.
182                                  */
183                                 if (uart_handle_break(&up->port))
184                                         continue;
185                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
186                                 up->port.icount.parity++;
187                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
188                                 up->port.icount.frame++;
189                         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
190                                 up->port.icount.overrun++;
191 
192                         /*
193                          * Mask off conditions which should be ingored.
194                          */
195                         stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
196                         stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
197 
198                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
199                                 flag = TTY_BREAK;
200                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
201                                 flag = TTY_PARITY;
202                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
203                                 flag = TTY_FRAME;
204                 }
205 
206                 if (uart_handle_sysrq_char(&up->port, ch) || !port)
207                         continue;
208 
209                 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
210                     (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
211                         tty_insert_flip_char(port, ch, flag);
212                 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
213                         tty_insert_flip_char(port, 0, TTY_OVERRUN);
214         }
215 
216         if (saw_console_brk)
217                 sun_do_break();
218 
219         return port;
220 }
221 
222 static void sunsab_stop_tx(struct uart_port *);
223 static void sunsab_tx_idle(struct uart_sunsab_port *);
224 
225 static void transmit_chars(struct uart_sunsab_port *up,
226                            union sab82532_irq_status *stat)
227 {
228         struct circ_buf *xmit = &up->port.state->xmit;
229         int i;
230 
231         if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
232                 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
233                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
234                 set_bit(SAB82532_ALLS, &up->irqflags);
235         }
236 
237 #if 0 /* bde@nwlink.com says this check causes problems */
238         if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
239                 return;
240 #endif
241 
242         if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
243                 return;
244 
245         set_bit(SAB82532_XPR, &up->irqflags);
246         sunsab_tx_idle(up);
247 
248         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
249                 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
250                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
251                 return;
252         }
253 
254         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
255         writeb(up->interrupt_mask1, &up->regs->w.imr1);
256         clear_bit(SAB82532_ALLS, &up->irqflags);
257 
258         /* Stuff 32 bytes into Transmit FIFO. */
259         clear_bit(SAB82532_XPR, &up->irqflags);
260         for (i = 0; i < up->port.fifosize; i++) {
261                 writeb(xmit->buf[xmit->tail],
262                        &up->regs->w.xfifo[i]);
263                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
264                 up->port.icount.tx++;
265                 if (uart_circ_empty(xmit))
266                         break;
267         }
268 
269         /* Issue a Transmit Frame command. */
270         sunsab_cec_wait(up);
271         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
272 
273         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
274                 uart_write_wakeup(&up->port);
275 
276         if (uart_circ_empty(xmit))
277                 sunsab_stop_tx(&up->port);
278 }
279 
280 static void check_status(struct uart_sunsab_port *up,
281                          union sab82532_irq_status *stat)
282 {
283         if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
284                 uart_handle_dcd_change(&up->port,
285                                        !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
286 
287         if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
288                 uart_handle_cts_change(&up->port,
289                                        (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
290 
291         if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
292                 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
293                 up->port.icount.dsr++;
294         }
295 
296         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
297 }
298 
299 static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
300 {
301         struct uart_sunsab_port *up = dev_id;
302         struct tty_port *port = NULL;
303         union sab82532_irq_status status;
304         unsigned long flags;
305         unsigned char gis;
306 
307         spin_lock_irqsave(&up->port.lock, flags);
308 
309         status.stat = 0;
310         gis = readb(&up->regs->r.gis) >> up->gis_shift;
311         if (gis & 1)
312                 status.sreg.isr0 = readb(&up->regs->r.isr0);
313         if (gis & 2)
314                 status.sreg.isr1 = readb(&up->regs->r.isr1);
315 
316         if (status.stat) {
317                 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
318                                          SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
319                     (status.sreg.isr1 & SAB82532_ISR1_BRK))
320                         port = receive_chars(up, &status);
321                 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
322                     (status.sreg.isr1 & SAB82532_ISR1_CSC))
323                         check_status(up, &status);
324                 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
325                         transmit_chars(up, &status);
326         }
327 
328         spin_unlock_irqrestore(&up->port.lock, flags);
329 
330         if (port)
331                 tty_flip_buffer_push(port);
332 
333         return IRQ_HANDLED;
334 }
335 
336 /* port->lock is not held.  */
337 static unsigned int sunsab_tx_empty(struct uart_port *port)
338 {
339         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
340         int ret;
341 
342         /* Do not need a lock for a state test like this.  */
343         if (test_bit(SAB82532_ALLS, &up->irqflags))
344                 ret = TIOCSER_TEMT;
345         else
346                 ret = 0;
347 
348         return ret;
349 }
350 
351 /* port->lock held by caller.  */
352 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
353 {
354         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
355 
356         if (mctrl & TIOCM_RTS) {
357                 up->cached_mode &= ~SAB82532_MODE_FRTS;
358                 up->cached_mode |= SAB82532_MODE_RTS;
359         } else {
360                 up->cached_mode |= (SAB82532_MODE_FRTS |
361                                     SAB82532_MODE_RTS);
362         }
363         if (mctrl & TIOCM_DTR) {
364                 up->cached_pvr &= ~(up->pvr_dtr_bit);
365         } else {
366                 up->cached_pvr |= up->pvr_dtr_bit;
367         }
368 
369         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
370         if (test_bit(SAB82532_XPR, &up->irqflags))
371                 sunsab_tx_idle(up);
372 }
373 
374 /* port->lock is held by caller and interrupts are disabled.  */
375 static unsigned int sunsab_get_mctrl(struct uart_port *port)
376 {
377         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
378         unsigned char val;
379         unsigned int result;
380 
381         result = 0;
382 
383         val = readb(&up->regs->r.pvr);
384         result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
385 
386         val = readb(&up->regs->r.vstr);
387         result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
388 
389         val = readb(&up->regs->r.star);
390         result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
391 
392         return result;
393 }
394 
395 /* port->lock held by caller.  */
396 static void sunsab_stop_tx(struct uart_port *port)
397 {
398         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
399 
400         up->interrupt_mask1 |= SAB82532_IMR1_XPR;
401         writeb(up->interrupt_mask1, &up->regs->w.imr1);
402 }
403 
404 /* port->lock held by caller.  */
405 static void sunsab_tx_idle(struct uart_sunsab_port *up)
406 {
407         if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
408                 u8 tmp;
409 
410                 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
411                 writeb(up->cached_mode, &up->regs->rw.mode);
412                 writeb(up->cached_pvr, &up->regs->rw.pvr);
413                 writeb(up->cached_dafo, &up->regs->w.dafo);
414 
415                 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
416                 tmp = readb(&up->regs->rw.ccr2);
417                 tmp &= ~0xc0;
418                 tmp |= (up->cached_ebrg >> 2) & 0xc0;
419                 writeb(tmp, &up->regs->rw.ccr2);
420         }
421 }
422 
423 /* port->lock held by caller.  */
424 static void sunsab_start_tx(struct uart_port *port)
425 {
426         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
427         struct circ_buf *xmit = &up->port.state->xmit;
428         int i;
429 
430         if (uart_circ_empty(xmit))
431                 return;
432 
433         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
434         writeb(up->interrupt_mask1, &up->regs->w.imr1);
435         
436         if (!test_bit(SAB82532_XPR, &up->irqflags))
437                 return;
438 
439         clear_bit(SAB82532_ALLS, &up->irqflags);
440         clear_bit(SAB82532_XPR, &up->irqflags);
441 
442         for (i = 0; i < up->port.fifosize; i++) {
443                 writeb(xmit->buf[xmit->tail],
444                        &up->regs->w.xfifo[i]);
445                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
446                 up->port.icount.tx++;
447                 if (uart_circ_empty(xmit))
448                         break;
449         }
450 
451         /* Issue a Transmit Frame command.  */
452         sunsab_cec_wait(up);
453         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
454 }
455 
456 /* port->lock is not held.  */
457 static void sunsab_send_xchar(struct uart_port *port, char ch)
458 {
459         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
460         unsigned long flags;
461 
462         spin_lock_irqsave(&up->port.lock, flags);
463 
464         sunsab_tec_wait(up);
465         writeb(ch, &up->regs->w.tic);
466 
467         spin_unlock_irqrestore(&up->port.lock, flags);
468 }
469 
470 /* port->lock held by caller.  */
471 static void sunsab_stop_rx(struct uart_port *port)
472 {
473         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
474 
475         up->interrupt_mask0 |= SAB82532_IMR0_TCD;
476         writeb(up->interrupt_mask1, &up->regs->w.imr0);
477 }
478 
479 /* port->lock held by caller.  */
480 static void sunsab_enable_ms(struct uart_port *port)
481 {
482         /* For now we always receive these interrupts.  */
483 }
484 
485 /* port->lock is not held.  */
486 static void sunsab_break_ctl(struct uart_port *port, int break_state)
487 {
488         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
489         unsigned long flags;
490         unsigned char val;
491 
492         spin_lock_irqsave(&up->port.lock, flags);
493 
494         val = up->cached_dafo;
495         if (break_state)
496                 val |= SAB82532_DAFO_XBRK;
497         else
498                 val &= ~SAB82532_DAFO_XBRK;
499         up->cached_dafo = val;
500 
501         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
502         if (test_bit(SAB82532_XPR, &up->irqflags))
503                 sunsab_tx_idle(up);
504 
505         spin_unlock_irqrestore(&up->port.lock, flags);
506 }
507 
508 /* port->lock is not held.  */
509 static int sunsab_startup(struct uart_port *port)
510 {
511         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
512         unsigned long flags;
513         unsigned char tmp;
514         int err = request_irq(up->port.irq, sunsab_interrupt,
515                               IRQF_SHARED, "sab", up);
516         if (err)
517                 return err;
518 
519         spin_lock_irqsave(&up->port.lock, flags);
520 
521         /*
522          * Wait for any commands or immediate characters
523          */
524         sunsab_cec_wait(up);
525         sunsab_tec_wait(up);
526 
527         /*
528          * Clear the FIFO buffers.
529          */
530         writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
531         sunsab_cec_wait(up);
532         writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
533 
534         /*
535          * Clear the interrupt registers.
536          */
537         (void) readb(&up->regs->r.isr0);
538         (void) readb(&up->regs->r.isr1);
539 
540         /*
541          * Now, initialize the UART 
542          */
543         writeb(0, &up->regs->w.ccr0);                           /* power-down */
544         writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
545                SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
546         writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
547         writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
548                SAB82532_CCR2_TOE, &up->regs->w.ccr2);
549         writeb(0, &up->regs->w.ccr3);
550         writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
551         up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
552                            SAB82532_MODE_RAC);
553         writeb(up->cached_mode, &up->regs->w.mode);
554         writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
555         
556         tmp = readb(&up->regs->rw.ccr0);
557         tmp |= SAB82532_CCR0_PU;        /* power-up */
558         writeb(tmp, &up->regs->rw.ccr0);
559 
560         /*
561          * Finally, enable interrupts
562          */
563         up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
564                                SAB82532_IMR0_PLLA);
565         writeb(up->interrupt_mask0, &up->regs->w.imr0);
566         up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
567                                SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
568                                SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
569                                SAB82532_IMR1_XPR);
570         writeb(up->interrupt_mask1, &up->regs->w.imr1);
571         set_bit(SAB82532_ALLS, &up->irqflags);
572         set_bit(SAB82532_XPR, &up->irqflags);
573 
574         spin_unlock_irqrestore(&up->port.lock, flags);
575 
576         return 0;
577 }
578 
579 /* port->lock is not held.  */
580 static void sunsab_shutdown(struct uart_port *port)
581 {
582         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
583         unsigned long flags;
584 
585         spin_lock_irqsave(&up->port.lock, flags);
586 
587         /* Disable Interrupts */
588         up->interrupt_mask0 = 0xff;
589         writeb(up->interrupt_mask0, &up->regs->w.imr0);
590         up->interrupt_mask1 = 0xff;
591         writeb(up->interrupt_mask1, &up->regs->w.imr1);
592 
593         /* Disable break condition */
594         up->cached_dafo = readb(&up->regs->rw.dafo);
595         up->cached_dafo &= ~SAB82532_DAFO_XBRK;
596         writeb(up->cached_dafo, &up->regs->rw.dafo);
597 
598         /* Disable Receiver */  
599         up->cached_mode &= ~SAB82532_MODE_RAC;
600         writeb(up->cached_mode, &up->regs->rw.mode);
601 
602         /*
603          * XXX FIXME
604          *
605          * If the chip is powered down here the system hangs/crashes during
606          * reboot or shutdown.  This needs to be investigated further,
607          * similar behaviour occurs in 2.4 when the driver is configured
608          * as a module only.  One hint may be that data is sometimes
609          * transmitted at 9600 baud during shutdown (regardless of the
610          * speed the chip was configured for when the port was open).
611          */
612 #if 0
613         /* Power Down */        
614         tmp = readb(&up->regs->rw.ccr0);
615         tmp &= ~SAB82532_CCR0_PU;
616         writeb(tmp, &up->regs->rw.ccr0);
617 #endif
618 
619         spin_unlock_irqrestore(&up->port.lock, flags);
620         free_irq(up->port.irq, up);
621 }
622 
623 /*
624  * This is used to figure out the divisor speeds.
625  *
626  * The formula is:    Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
627  *
628  * with               0 <= N < 64 and 0 <= M < 16
629  */
630 
631 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
632 {
633         int     n, m;
634 
635         if (baud == 0) {
636                 *n_ret = 0;
637                 *m_ret = 0;
638                 return;
639         }
640      
641         /*
642          * We scale numbers by 10 so that we get better accuracy
643          * without having to use floating point.  Here we increment m
644          * until n is within the valid range.
645          */
646         n = (SAB_BASE_BAUD * 10) / baud;
647         m = 0;
648         while (n >= 640) {
649                 n = n / 2;
650                 m++;
651         }
652         n = (n+5) / 10;
653         /*
654          * We try very hard to avoid speeds with M == 0 since they may
655          * not work correctly for XTAL frequences above 10 MHz.
656          */
657         if ((m == 0) && ((n & 1) == 0)) {
658                 n = n / 2;
659                 m++;
660         }
661         *n_ret = n - 1;
662         *m_ret = m;
663 }
664 
665 /* Internal routine, port->lock is held and local interrupts are disabled.  */
666 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
667                                   unsigned int iflag, unsigned int baud,
668                                   unsigned int quot)
669 {
670         unsigned char dafo;
671         int bits, n, m;
672 
673         /* Byte size and parity */
674         switch (cflag & CSIZE) {
675               case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
676               case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
677               case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
678               case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
679               /* Never happens, but GCC is too dumb to figure it out */
680               default:  dafo = SAB82532_DAFO_CHL5; bits = 7; break;
681         }
682 
683         if (cflag & CSTOPB) {
684                 dafo |= SAB82532_DAFO_STOP;
685                 bits++;
686         }
687 
688         if (cflag & PARENB) {
689                 dafo |= SAB82532_DAFO_PARE;
690                 bits++;
691         }
692 
693         if (cflag & PARODD) {
694                 dafo |= SAB82532_DAFO_PAR_ODD;
695         } else {
696                 dafo |= SAB82532_DAFO_PAR_EVEN;
697         }
698         up->cached_dafo = dafo;
699 
700         calc_ebrg(baud, &n, &m);
701 
702         up->cached_ebrg = n | (m << 6);
703 
704         up->tec_timeout = (10 * 1000000) / baud;
705         up->cec_timeout = up->tec_timeout >> 2;
706 
707         /* CTS flow control flags */
708         /* We encode read_status_mask and ignore_status_mask like so:
709          *
710          * ---------------------
711          * | ... | ISR1 | ISR0 |
712          * ---------------------
713          *  ..    15   8 7    0
714          */
715 
716         up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
717                                      SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
718                                      SAB82532_ISR0_CDSC);
719         up->port.read_status_mask |= (SAB82532_ISR1_CSC |
720                                       SAB82532_ISR1_ALLS |
721                                       SAB82532_ISR1_XPR) << 8;
722         if (iflag & INPCK)
723                 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
724                                               SAB82532_ISR0_FERR);
725         if (iflag & (IGNBRK | BRKINT | PARMRK))
726                 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
727 
728         /*
729          * Characteres to ignore
730          */
731         up->port.ignore_status_mask = 0;
732         if (iflag & IGNPAR)
733                 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
734                                                 SAB82532_ISR0_FERR);
735         if (iflag & IGNBRK) {
736                 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
737                 /*
738                  * If we're ignoring parity and break indicators,
739                  * ignore overruns too (for real raw support).
740                  */
741                 if (iflag & IGNPAR)
742                         up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
743         }
744 
745         /*
746          * ignore all characters if CREAD is not set
747          */
748         if ((cflag & CREAD) == 0)
749                 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
750                                                 SAB82532_ISR0_TCD);
751 
752         uart_update_timeout(&up->port, cflag,
753                             (up->port.uartclk / (16 * quot)));
754 
755         /* Now schedule a register update when the chip's
756          * transmitter is idle.
757          */
758         up->cached_mode |= SAB82532_MODE_RAC;
759         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
760         if (test_bit(SAB82532_XPR, &up->irqflags))
761                 sunsab_tx_idle(up);
762 }
763 
764 /* port->lock is not held.  */
765 static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
766                                struct ktermios *old)
767 {
768         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
769         unsigned long flags;
770         unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
771         unsigned int quot = uart_get_divisor(port, baud);
772 
773         spin_lock_irqsave(&up->port.lock, flags);
774         sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
775         spin_unlock_irqrestore(&up->port.lock, flags);
776 }
777 
778 static const char *sunsab_type(struct uart_port *port)
779 {
780         struct uart_sunsab_port *up = (void *)port;
781         static char buf[36];
782         
783         sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
784         return buf;
785 }
786 
787 static void sunsab_release_port(struct uart_port *port)
788 {
789 }
790 
791 static int sunsab_request_port(struct uart_port *port)
792 {
793         return 0;
794 }
795 
796 static void sunsab_config_port(struct uart_port *port, int flags)
797 {
798 }
799 
800 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
801 {
802         return -EINVAL;
803 }
804 
805 static struct uart_ops sunsab_pops = {
806         .tx_empty       = sunsab_tx_empty,
807         .set_mctrl      = sunsab_set_mctrl,
808         .get_mctrl      = sunsab_get_mctrl,
809         .stop_tx        = sunsab_stop_tx,
810         .start_tx       = sunsab_start_tx,
811         .send_xchar     = sunsab_send_xchar,
812         .stop_rx        = sunsab_stop_rx,
813         .enable_ms      = sunsab_enable_ms,
814         .break_ctl      = sunsab_break_ctl,
815         .startup        = sunsab_startup,
816         .shutdown       = sunsab_shutdown,
817         .set_termios    = sunsab_set_termios,
818         .type           = sunsab_type,
819         .release_port   = sunsab_release_port,
820         .request_port   = sunsab_request_port,
821         .config_port    = sunsab_config_port,
822         .verify_port    = sunsab_verify_port,
823 };
824 
825 static struct uart_driver sunsab_reg = {
826         .owner                  = THIS_MODULE,
827         .driver_name            = "sunsab",
828         .dev_name               = "ttyS",
829         .major                  = TTY_MAJOR,
830 };
831 
832 static struct uart_sunsab_port *sunsab_ports;
833 
834 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
835 
836 static void sunsab_console_putchar(struct uart_port *port, int c)
837 {
838         struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
839 
840         sunsab_tec_wait(up);
841         writeb(c, &up->regs->w.tic);
842 }
843 
844 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
845 {
846         struct uart_sunsab_port *up = &sunsab_ports[con->index];
847         unsigned long flags;
848         int locked = 1;
849 
850         if (up->port.sysrq || oops_in_progress)
851                 locked = spin_trylock_irqsave(&up->port.lock, flags);
852         else
853                 spin_lock_irqsave(&up->port.lock, flags);
854 
855         uart_console_write(&up->port, s, n, sunsab_console_putchar);
856         sunsab_tec_wait(up);
857 
858         if (locked)
859                 spin_unlock_irqrestore(&up->port.lock, flags);
860 }
861 
862 static int sunsab_console_setup(struct console *con, char *options)
863 {
864         struct uart_sunsab_port *up = &sunsab_ports[con->index];
865         unsigned long flags;
866         unsigned int baud, quot;
867 
868         /*
869          * The console framework calls us for each and every port
870          * registered. Defer the console setup until the requested
871          * port has been properly discovered. A bit of a hack,
872          * though...
873          */
874         if (up->port.type != PORT_SUNSAB)
875                 return -1;
876 
877         printk("Console: ttyS%d (SAB82532)\n",
878                (sunsab_reg.minor - 64) + con->index);
879 
880         sunserial_console_termios(con, up->port.dev->of_node);
881 
882         switch (con->cflag & CBAUD) {
883         case B150: baud = 150; break;
884         case B300: baud = 300; break;
885         case B600: baud = 600; break;
886         case B1200: baud = 1200; break;
887         case B2400: baud = 2400; break;
888         case B4800: baud = 4800; break;
889         default: case B9600: baud = 9600; break;
890         case B19200: baud = 19200; break;
891         case B38400: baud = 38400; break;
892         case B57600: baud = 57600; break;
893         case B115200: baud = 115200; break;
894         case B230400: baud = 230400; break;
895         case B460800: baud = 460800; break;
896         }
897 
898         /*
899          * Temporary fix.
900          */
901         spin_lock_init(&up->port.lock);
902 
903         /*
904          * Initialize the hardware
905          */
906         sunsab_startup(&up->port);
907 
908         spin_lock_irqsave(&up->port.lock, flags);
909 
910         /*
911          * Finally, enable interrupts
912          */
913         up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
914                                 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
915         writeb(up->interrupt_mask0, &up->regs->w.imr0);
916         up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
917                                 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
918                                 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
919                                 SAB82532_IMR1_XPR;
920         writeb(up->interrupt_mask1, &up->regs->w.imr1);
921 
922         quot = uart_get_divisor(&up->port, baud);
923         sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
924         sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
925 
926         spin_unlock_irqrestore(&up->port.lock, flags);
927         
928         return 0;
929 }
930 
931 static struct console sunsab_console = {
932         .name   =       "ttyS",
933         .write  =       sunsab_console_write,
934         .device =       uart_console_device,
935         .setup  =       sunsab_console_setup,
936         .flags  =       CON_PRINTBUFFER,
937         .index  =       -1,
938         .data   =       &sunsab_reg,
939 };
940 
941 static inline struct console *SUNSAB_CONSOLE(void)
942 {
943         return &sunsab_console;
944 }
945 #else
946 #define SUNSAB_CONSOLE()        (NULL)
947 #define sunsab_console_init()   do { } while (0)
948 #endif
949 
950 static int sunsab_init_one(struct uart_sunsab_port *up,
951                                      struct platform_device *op,
952                                      unsigned long offset,
953                                      int line)
954 {
955         up->port.line = line;
956         up->port.dev = &op->dev;
957 
958         up->port.mapbase = op->resource[0].start + offset;
959         up->port.membase = of_ioremap(&op->resource[0], offset,
960                                       sizeof(union sab82532_async_regs),
961                                       "sab");
962         if (!up->port.membase)
963                 return -ENOMEM;
964         up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
965 
966         up->port.irq = op->archdata.irqs[0];
967 
968         up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
969         up->port.iotype = UPIO_MEM;
970 
971         writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
972 
973         up->port.ops = &sunsab_pops;
974         up->port.type = PORT_SUNSAB;
975         up->port.uartclk = SAB_BASE_BAUD;
976 
977         up->type = readb(&up->regs->r.vstr) & 0x0f;
978         writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
979         writeb(0xff, &up->regs->w.pim);
980         if ((up->port.line & 0x1) == 0) {
981                 up->pvr_dsr_bit = (1 << 0);
982                 up->pvr_dtr_bit = (1 << 1);
983                 up->gis_shift = 2;
984         } else {
985                 up->pvr_dsr_bit = (1 << 3);
986                 up->pvr_dtr_bit = (1 << 2);
987                 up->gis_shift = 0;
988         }
989         up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
990         writeb(up->cached_pvr, &up->regs->w.pvr);
991         up->cached_mode = readb(&up->regs->rw.mode);
992         up->cached_mode |= SAB82532_MODE_FRTS;
993         writeb(up->cached_mode, &up->regs->rw.mode);
994         up->cached_mode |= SAB82532_MODE_RTS;
995         writeb(up->cached_mode, &up->regs->rw.mode);
996 
997         up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
998         up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
999 
1000         return 0;
1001 }
1002 
1003 static int sab_probe(struct platform_device *op)
1004 {
1005         static int inst;
1006         struct uart_sunsab_port *up;
1007         int err;
1008 
1009         up = &sunsab_ports[inst * 2];
1010 
1011         err = sunsab_init_one(&up[0], op,
1012                               0,
1013                               (inst * 2) + 0);
1014         if (err)
1015                 goto out;
1016 
1017         err = sunsab_init_one(&up[1], op,
1018                               sizeof(union sab82532_async_regs),
1019                               (inst * 2) + 1);
1020         if (err)
1021                 goto out1;
1022 
1023         sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1024                                 &sunsab_reg, up[0].port.line,
1025                                 false);
1026 
1027         sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1028                                 &sunsab_reg, up[1].port.line,
1029                                 false);
1030 
1031         err = uart_add_one_port(&sunsab_reg, &up[0].port);
1032         if (err)
1033                 goto out2;
1034 
1035         err = uart_add_one_port(&sunsab_reg, &up[1].port);
1036         if (err)
1037                 goto out3;
1038 
1039         platform_set_drvdata(op, &up[0]);
1040 
1041         inst++;
1042 
1043         return 0;
1044 
1045 out3:
1046         uart_remove_one_port(&sunsab_reg, &up[0].port);
1047 out2:
1048         of_iounmap(&op->resource[0],
1049                    up[1].port.membase,
1050                    sizeof(union sab82532_async_regs));
1051 out1:
1052         of_iounmap(&op->resource[0],
1053                    up[0].port.membase,
1054                    sizeof(union sab82532_async_regs));
1055 out:
1056         return err;
1057 }
1058 
1059 static int sab_remove(struct platform_device *op)
1060 {
1061         struct uart_sunsab_port *up = platform_get_drvdata(op);
1062 
1063         uart_remove_one_port(&sunsab_reg, &up[1].port);
1064         uart_remove_one_port(&sunsab_reg, &up[0].port);
1065         of_iounmap(&op->resource[0],
1066                    up[1].port.membase,
1067                    sizeof(union sab82532_async_regs));
1068         of_iounmap(&op->resource[0],
1069                    up[0].port.membase,
1070                    sizeof(union sab82532_async_regs));
1071 
1072         return 0;
1073 }
1074 
1075 static const struct of_device_id sab_match[] = {
1076         {
1077                 .name = "se",
1078         },
1079         {
1080                 .name = "serial",
1081                 .compatible = "sab82532",
1082         },
1083         {},
1084 };
1085 MODULE_DEVICE_TABLE(of, sab_match);
1086 
1087 static struct platform_driver sab_driver = {
1088         .driver = {
1089                 .name = "sab",
1090                 .owner = THIS_MODULE,
1091                 .of_match_table = sab_match,
1092         },
1093         .probe          = sab_probe,
1094         .remove         = sab_remove,
1095 };
1096 
1097 static int __init sunsab_init(void)
1098 {
1099         struct device_node *dp;
1100         int err;
1101         int num_channels = 0;
1102 
1103         for_each_node_by_name(dp, "se")
1104                 num_channels += 2;
1105         for_each_node_by_name(dp, "serial") {
1106                 if (of_device_is_compatible(dp, "sab82532"))
1107                         num_channels += 2;
1108         }
1109 
1110         if (num_channels) {
1111                 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1112                                        num_channels, GFP_KERNEL);
1113                 if (!sunsab_ports)
1114                         return -ENOMEM;
1115 
1116                 err = sunserial_register_minors(&sunsab_reg, num_channels);
1117                 if (err) {
1118                         kfree(sunsab_ports);
1119                         sunsab_ports = NULL;
1120 
1121                         return err;
1122                 }
1123         }
1124 
1125         return platform_driver_register(&sab_driver);
1126 }
1127 
1128 static void __exit sunsab_exit(void)
1129 {
1130         platform_driver_unregister(&sab_driver);
1131         if (sunsab_reg.nr) {
1132                 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1133         }
1134 
1135         kfree(sunsab_ports);
1136         sunsab_ports = NULL;
1137 }
1138 
1139 module_init(sunsab_init);
1140 module_exit(sunsab_exit);
1141 
1142 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1143 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1144 MODULE_LICENSE("GPL");
1145 

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