Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/tty/serial/sirfsoc_uart.c

  1 /*
  2  * Driver for CSR SiRFprimaII onboard UARTs.
  3  *
  4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
  5  *
  6  * Licensed under GPLv2 or later.
  7  */
  8 
  9 #include <linux/module.h>
 10 #include <linux/ioport.h>
 11 #include <linux/platform_device.h>
 12 #include <linux/init.h>
 13 #include <linux/sysrq.h>
 14 #include <linux/console.h>
 15 #include <linux/tty.h>
 16 #include <linux/tty_flip.h>
 17 #include <linux/serial_core.h>
 18 #include <linux/serial.h>
 19 #include <linux/clk.h>
 20 #include <linux/of.h>
 21 #include <linux/slab.h>
 22 #include <linux/io.h>
 23 #include <linux/of_gpio.h>
 24 #include <linux/dmaengine.h>
 25 #include <linux/dma-direction.h>
 26 #include <linux/dma-mapping.h>
 27 #include <asm/irq.h>
 28 #include <asm/mach/irq.h>
 29 
 30 #include "sirfsoc_uart.h"
 31 
 32 static unsigned int
 33 sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count);
 34 static unsigned int
 35 sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count);
 36 static struct uart_driver sirfsoc_uart_drv;
 37 
 38 static void sirfsoc_uart_tx_dma_complete_callback(void *param);
 39 static void sirfsoc_uart_start_next_rx_dma(struct uart_port *port);
 40 static void sirfsoc_uart_rx_dma_complete_callback(void *param);
 41 static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = {
 42         {4000000, 2359296},
 43         {3500000, 1310721},
 44         {3000000, 1572865},
 45         {2500000, 1245186},
 46         {2000000, 1572866},
 47         {1500000, 1245188},
 48         {1152000, 1638404},
 49         {1000000, 1572869},
 50         {921600, 1114120},
 51         {576000, 1245196},
 52         {500000, 1245198},
 53         {460800, 1572876},
 54         {230400, 1310750},
 55         {115200, 1310781},
 56         {57600, 1310843},
 57         {38400, 1114328},
 58         {19200, 1114545},
 59         {9600, 1114979},
 60 };
 61 
 62 static struct sirfsoc_uart_port sirfsoc_uart_ports[SIRFSOC_UART_NR] = {
 63         [0] = {
 64                 .port = {
 65                         .iotype         = UPIO_MEM,
 66                         .flags          = UPF_BOOT_AUTOCONF,
 67                         .line           = 0,
 68                 },
 69         },
 70         [1] = {
 71                 .port = {
 72                         .iotype         = UPIO_MEM,
 73                         .flags          = UPF_BOOT_AUTOCONF,
 74                         .line           = 1,
 75                 },
 76         },
 77         [2] = {
 78                 .port = {
 79                         .iotype         = UPIO_MEM,
 80                         .flags          = UPF_BOOT_AUTOCONF,
 81                         .line           = 2,
 82                 },
 83         },
 84         [3] = {
 85                 .port = {
 86                         .iotype         = UPIO_MEM,
 87                         .flags          = UPF_BOOT_AUTOCONF,
 88                         .line           = 3,
 89                 },
 90         },
 91         [4] = {
 92                 .port = {
 93                         .iotype         = UPIO_MEM,
 94                         .flags          = UPF_BOOT_AUTOCONF,
 95                         .line           = 4,
 96                 },
 97         },
 98         [5] = {
 99                 .port = {
100                         .iotype         = UPIO_MEM,
101                         .flags          = UPF_BOOT_AUTOCONF,
102                         .line           = 5,
103                 },
104         },
105 };
106 
107 static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port)
108 {
109         return container_of(port, struct sirfsoc_uart_port, port);
110 }
111 
112 static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port)
113 {
114         unsigned long reg;
115         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
116         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
117         struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
118         reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status);
119 
120         return (reg & ufifo_st->ff_empty(port->line)) ? TIOCSER_TEMT : 0;
121 }
122 
123 static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port)
124 {
125         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
126         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
127         if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
128                 goto cts_asserted;
129         if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
130                 if (!(rd_regl(port, ureg->sirfsoc_afc_ctrl) &
131                                                 SIRFUART_AFC_CTS_STATUS))
132                         goto cts_asserted;
133                 else
134                         goto cts_deasserted;
135         } else {
136                 if (!gpio_get_value(sirfport->cts_gpio))
137                         goto cts_asserted;
138                 else
139                         goto cts_deasserted;
140         }
141 cts_deasserted:
142         return TIOCM_CAR | TIOCM_DSR;
143 cts_asserted:
144         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
145 }
146 
147 static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
148 {
149         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
150         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
151         unsigned int assert = mctrl & TIOCM_RTS;
152         unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0;
153         unsigned int current_val;
154 
155         if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
156                 return;
157         if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
158                 current_val = rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0xFF;
159                 val |= current_val;
160                 wr_regl(port, ureg->sirfsoc_afc_ctrl, val);
161         } else {
162                 if (!val)
163                         gpio_set_value(sirfport->rts_gpio, 1);
164                 else
165                         gpio_set_value(sirfport->rts_gpio, 0);
166         }
167 }
168 
169 static void sirfsoc_uart_stop_tx(struct uart_port *port)
170 {
171         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
172         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
173         struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
174 
175         if (sirfport->tx_dma_chan) {
176                 if (sirfport->tx_dma_state == TX_DMA_RUNNING) {
177                         dmaengine_pause(sirfport->tx_dma_chan);
178                         sirfport->tx_dma_state = TX_DMA_PAUSE;
179                 } else {
180                         if (!sirfport->is_marco)
181                                 wr_regl(port, ureg->sirfsoc_int_en_reg,
182                                 rd_regl(port, ureg->sirfsoc_int_en_reg) &
183                                 ~uint_en->sirfsoc_txfifo_empty_en);
184                         else
185                                 wr_regl(port, SIRFUART_INT_EN_CLR,
186                                 uint_en->sirfsoc_txfifo_empty_en);
187                 }
188         } else {
189                 if (!sirfport->is_marco)
190                         wr_regl(port, ureg->sirfsoc_int_en_reg,
191                                 rd_regl(port, ureg->sirfsoc_int_en_reg) &
192                                 ~uint_en->sirfsoc_txfifo_empty_en);
193                 else
194                         wr_regl(port, SIRFUART_INT_EN_CLR,
195                                 uint_en->sirfsoc_txfifo_empty_en);
196         }
197 }
198 
199 static void sirfsoc_uart_tx_with_dma(struct sirfsoc_uart_port *sirfport)
200 {
201         struct uart_port *port = &sirfport->port;
202         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
203         struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
204         struct circ_buf *xmit = &port->state->xmit;
205         unsigned long tran_size;
206         unsigned long tran_start;
207         unsigned long pio_tx_size;
208 
209         tran_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
210         tran_start = (unsigned long)(xmit->buf + xmit->tail);
211         if (uart_circ_empty(xmit) || uart_tx_stopped(port) ||
212                         !tran_size)
213                 return;
214         if (sirfport->tx_dma_state == TX_DMA_PAUSE) {
215                 dmaengine_resume(sirfport->tx_dma_chan);
216                 return;
217         }
218         if (sirfport->tx_dma_state == TX_DMA_RUNNING)
219                 return;
220         if (!sirfport->is_marco)
221                 wr_regl(port, ureg->sirfsoc_int_en_reg,
222                                 rd_regl(port, ureg->sirfsoc_int_en_reg)&
223                                 ~(uint_en->sirfsoc_txfifo_empty_en));
224         else
225                 wr_regl(port, SIRFUART_INT_EN_CLR,
226                                 uint_en->sirfsoc_txfifo_empty_en);
227         /*
228          * DMA requires buffer address and buffer length are both aligned with
229          * 4 bytes, so we use PIO for
230          * 1. if address is not aligned with 4bytes, use PIO for the first 1~3
231          * bytes, and move to DMA for the left part aligned with 4bytes
232          * 2. if buffer length is not aligned with 4bytes, use DMA for aligned
233          * part first, move to PIO for the left 1~3 bytes
234          */
235         if (tran_size < 4 || BYTES_TO_ALIGN(tran_start)) {
236                 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
237                 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
238                         rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)|
239                         SIRFUART_IO_MODE);
240                 if (BYTES_TO_ALIGN(tran_start)) {
241                         pio_tx_size = sirfsoc_uart_pio_tx_chars(sirfport,
242                                 BYTES_TO_ALIGN(tran_start));
243                         tran_size -= pio_tx_size;
244                 }
245                 if (tran_size < 4)
246                         sirfsoc_uart_pio_tx_chars(sirfport, tran_size);
247                 if (!sirfport->is_marco)
248                         wr_regl(port, ureg->sirfsoc_int_en_reg,
249                                 rd_regl(port, ureg->sirfsoc_int_en_reg)|
250                                 uint_en->sirfsoc_txfifo_empty_en);
251                 else
252                         wr_regl(port, ureg->sirfsoc_int_en_reg,
253                                 uint_en->sirfsoc_txfifo_empty_en);
254                 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
255         } else {
256                 /* tx transfer mode switch into dma mode */
257                 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
258                 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
259                         rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)&
260                         ~SIRFUART_IO_MODE);
261                 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
262                 tran_size &= ~(0x3);
263 
264                 sirfport->tx_dma_addr = dma_map_single(port->dev,
265                         xmit->buf + xmit->tail,
266                         tran_size, DMA_TO_DEVICE);
267                 sirfport->tx_dma_desc = dmaengine_prep_slave_single(
268                         sirfport->tx_dma_chan, sirfport->tx_dma_addr,
269                         tran_size, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
270                 if (!sirfport->tx_dma_desc) {
271                         dev_err(port->dev, "DMA prep slave single fail\n");
272                         return;
273                 }
274                 sirfport->tx_dma_desc->callback =
275                         sirfsoc_uart_tx_dma_complete_callback;
276                 sirfport->tx_dma_desc->callback_param = (void *)sirfport;
277                 sirfport->transfer_size = tran_size;
278 
279                 dmaengine_submit(sirfport->tx_dma_desc);
280                 dma_async_issue_pending(sirfport->tx_dma_chan);
281                 sirfport->tx_dma_state = TX_DMA_RUNNING;
282         }
283 }
284 
285 static void sirfsoc_uart_start_tx(struct uart_port *port)
286 {
287         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
288         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
289         struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
290         if (sirfport->tx_dma_chan)
291                 sirfsoc_uart_tx_with_dma(sirfport);
292         else {
293                 sirfsoc_uart_pio_tx_chars(sirfport,
294                         SIRFSOC_UART_IO_TX_REASONABLE_CNT);
295                 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
296                 if (!sirfport->is_marco)
297                         wr_regl(port, ureg->sirfsoc_int_en_reg,
298                                         rd_regl(port, ureg->sirfsoc_int_en_reg)|
299                                         uint_en->sirfsoc_txfifo_empty_en);
300                 else
301                         wr_regl(port, ureg->sirfsoc_int_en_reg,
302                                         uint_en->sirfsoc_txfifo_empty_en);
303         }
304 }
305 
306 static void sirfsoc_uart_stop_rx(struct uart_port *port)
307 {
308         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
309         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
310         struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
311 
312         wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
313         if (sirfport->rx_dma_chan) {
314                 if (!sirfport->is_marco)
315                         wr_regl(port, ureg->sirfsoc_int_en_reg,
316                                 rd_regl(port, ureg->sirfsoc_int_en_reg) &
317                                 ~(SIRFUART_RX_DMA_INT_EN(port, uint_en) |
318                                 uint_en->sirfsoc_rx_done_en));
319                 else
320                         wr_regl(port, SIRFUART_INT_EN_CLR,
321                                         SIRFUART_RX_DMA_INT_EN(port, uint_en)|
322                                         uint_en->sirfsoc_rx_done_en);
323                 dmaengine_terminate_all(sirfport->rx_dma_chan);
324         } else {
325                 if (!sirfport->is_marco)
326                         wr_regl(port, ureg->sirfsoc_int_en_reg,
327                                 rd_regl(port, ureg->sirfsoc_int_en_reg)&
328                                 ~(SIRFUART_RX_IO_INT_EN(port, uint_en)));
329                 else
330                         wr_regl(port, SIRFUART_INT_EN_CLR,
331                                         SIRFUART_RX_IO_INT_EN(port, uint_en));
332         }
333 }
334 
335 static void sirfsoc_uart_disable_ms(struct uart_port *port)
336 {
337         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
338         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
339         struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
340 
341         if (!sirfport->hw_flow_ctrl)
342                 return;
343         sirfport->ms_enabled = false;
344         if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
345                 wr_regl(port, ureg->sirfsoc_afc_ctrl,
346                                 rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0x3FF);
347                 if (!sirfport->is_marco)
348                         wr_regl(port, ureg->sirfsoc_int_en_reg,
349                                         rd_regl(port, ureg->sirfsoc_int_en_reg)&
350                                         ~uint_en->sirfsoc_cts_en);
351                 else
352                         wr_regl(port, SIRFUART_INT_EN_CLR,
353                                         uint_en->sirfsoc_cts_en);
354         } else
355                 disable_irq(gpio_to_irq(sirfport->cts_gpio));
356 }
357 
358 static irqreturn_t sirfsoc_uart_usp_cts_handler(int irq, void *dev_id)
359 {
360         struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
361         struct uart_port *port = &sirfport->port;
362         spin_lock(&port->lock);
363         if (gpio_is_valid(sirfport->cts_gpio) && sirfport->ms_enabled)
364                 uart_handle_cts_change(port,
365                                 !gpio_get_value(sirfport->cts_gpio));
366         spin_unlock(&port->lock);
367         return IRQ_HANDLED;
368 }
369 
370 static void sirfsoc_uart_enable_ms(struct uart_port *port)
371 {
372         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
373         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
374         struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
375 
376         if (!sirfport->hw_flow_ctrl)
377                 return;
378         sirfport->ms_enabled = true;
379         if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
380                 wr_regl(port, ureg->sirfsoc_afc_ctrl,
381                                 rd_regl(port, ureg->sirfsoc_afc_ctrl) |
382                                 SIRFUART_AFC_TX_EN | SIRFUART_AFC_RX_EN);
383                 if (!sirfport->is_marco)
384                         wr_regl(port, ureg->sirfsoc_int_en_reg,
385                                         rd_regl(port, ureg->sirfsoc_int_en_reg)
386                                         | uint_en->sirfsoc_cts_en);
387                 else
388                         wr_regl(port, ureg->sirfsoc_int_en_reg,
389                                         uint_en->sirfsoc_cts_en);
390         } else
391                 enable_irq(gpio_to_irq(sirfport->cts_gpio));
392 }
393 
394 static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state)
395 {
396         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
397         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
398         if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
399                 unsigned long ulcon = rd_regl(port, ureg->sirfsoc_line_ctrl);
400                 if (break_state)
401                         ulcon |= SIRFUART_SET_BREAK;
402                 else
403                         ulcon &= ~SIRFUART_SET_BREAK;
404                 wr_regl(port, ureg->sirfsoc_line_ctrl, ulcon);
405         }
406 }
407 
408 static unsigned int
409 sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count)
410 {
411         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
412         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
413         struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
414         unsigned int ch, rx_count = 0;
415         struct tty_struct *tty;
416         tty = tty_port_tty_get(&port->state->port);
417         if (!tty)
418                 return -ENODEV;
419         while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
420                                         ufifo_st->ff_empty(port->line))) {
421                 ch = rd_regl(port, ureg->sirfsoc_rx_fifo_data) |
422                         SIRFUART_DUMMY_READ;
423                 if (unlikely(uart_handle_sysrq_char(port, ch)))
424                         continue;
425                 uart_insert_char(port, 0, 0, ch, TTY_NORMAL);
426                 rx_count++;
427                 if (rx_count >= max_rx_count)
428                         break;
429         }
430 
431         sirfport->rx_io_count += rx_count;
432         port->icount.rx += rx_count;
433 
434         return rx_count;
435 }
436 
437 static unsigned int
438 sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count)
439 {
440         struct uart_port *port = &sirfport->port;
441         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
442         struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
443         struct circ_buf *xmit = &port->state->xmit;
444         unsigned int num_tx = 0;
445         while (!uart_circ_empty(xmit) &&
446                 !(rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
447                                         ufifo_st->ff_full(port->line)) &&
448                 count--) {
449                 wr_regl(port, ureg->sirfsoc_tx_fifo_data,
450                                 xmit->buf[xmit->tail]);
451                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
452                 port->icount.tx++;
453                 num_tx++;
454         }
455         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
456                 uart_write_wakeup(port);
457         return num_tx;
458 }
459 
460 static void sirfsoc_uart_tx_dma_complete_callback(void *param)
461 {
462         struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param;
463         struct uart_port *port = &sirfport->port;
464         struct circ_buf *xmit = &port->state->xmit;
465         unsigned long flags;
466 
467         spin_lock_irqsave(&port->lock, flags);
468         xmit->tail = (xmit->tail + sirfport->transfer_size) &
469                                 (UART_XMIT_SIZE - 1);
470         port->icount.tx += sirfport->transfer_size;
471         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
472                 uart_write_wakeup(port);
473         if (sirfport->tx_dma_addr)
474                 dma_unmap_single(port->dev, sirfport->tx_dma_addr,
475                                 sirfport->transfer_size, DMA_TO_DEVICE);
476         sirfport->tx_dma_state = TX_DMA_IDLE;
477         sirfsoc_uart_tx_with_dma(sirfport);
478         spin_unlock_irqrestore(&port->lock, flags);
479 }
480 
481 static void sirfsoc_uart_insert_rx_buf_to_tty(
482                 struct sirfsoc_uart_port *sirfport, int count)
483 {
484         struct uart_port *port = &sirfport->port;
485         struct tty_port *tport = &port->state->port;
486         int inserted;
487 
488         inserted = tty_insert_flip_string(tport,
489                 sirfport->rx_dma_items[sirfport->rx_completed].xmit.buf, count);
490         port->icount.rx += inserted;
491 }
492 
493 static void sirfsoc_rx_submit_one_dma_desc(struct uart_port *port, int index)
494 {
495         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
496 
497         sirfport->rx_dma_items[index].xmit.tail =
498                 sirfport->rx_dma_items[index].xmit.head = 0;
499         sirfport->rx_dma_items[index].desc =
500                 dmaengine_prep_slave_single(sirfport->rx_dma_chan,
501                 sirfport->rx_dma_items[index].dma_addr, SIRFSOC_RX_DMA_BUF_SIZE,
502                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
503         if (!sirfport->rx_dma_items[index].desc) {
504                 dev_err(port->dev, "DMA slave single fail\n");
505                 return;
506         }
507         sirfport->rx_dma_items[index].desc->callback =
508                 sirfsoc_uart_rx_dma_complete_callback;
509         sirfport->rx_dma_items[index].desc->callback_param = sirfport;
510         sirfport->rx_dma_items[index].cookie =
511                 dmaengine_submit(sirfport->rx_dma_items[index].desc);
512         dma_async_issue_pending(sirfport->rx_dma_chan);
513 }
514 
515 static void sirfsoc_rx_tmo_process_tl(unsigned long param)
516 {
517         struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param;
518         struct uart_port *port = &sirfport->port;
519         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
520         struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
521         struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
522         unsigned int count;
523         unsigned long flags;
524         struct dma_tx_state tx_state;
525 
526         spin_lock_irqsave(&port->lock, flags);
527         while (DMA_COMPLETE == dmaengine_tx_status(sirfport->rx_dma_chan,
528                 sirfport->rx_dma_items[sirfport->rx_completed].cookie, &tx_state)) {
529                 sirfsoc_uart_insert_rx_buf_to_tty(sirfport,
530                                         SIRFSOC_RX_DMA_BUF_SIZE);
531                 sirfport->rx_completed++;
532                 sirfport->rx_completed %= SIRFSOC_RX_LOOP_BUF_CNT;
533         }
534         count = CIRC_CNT(sirfport->rx_dma_items[sirfport->rx_issued].xmit.head,
535                 sirfport->rx_dma_items[sirfport->rx_issued].xmit.tail,
536                 SIRFSOC_RX_DMA_BUF_SIZE);
537         if (count > 0)
538                 sirfsoc_uart_insert_rx_buf_to_tty(sirfport, count);
539         wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
540                         rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
541                         SIRFUART_IO_MODE);
542         sirfsoc_uart_pio_rx_chars(port, 4 - sirfport->rx_io_count);
543         if (sirfport->rx_io_count == 4) {
544                 sirfport->rx_io_count = 0;
545                 wr_regl(port, ureg->sirfsoc_int_st_reg,
546                                 uint_st->sirfsoc_rx_done);
547                 if (!sirfport->is_marco)
548                         wr_regl(port, ureg->sirfsoc_int_en_reg,
549                                 rd_regl(port, ureg->sirfsoc_int_en_reg) &
550                                 ~(uint_en->sirfsoc_rx_done_en));
551                 else
552                         wr_regl(port, SIRFUART_INT_EN_CLR,
553                                         uint_en->sirfsoc_rx_done_en);
554                 sirfsoc_uart_start_next_rx_dma(port);
555         } else {
556                 wr_regl(port, ureg->sirfsoc_int_st_reg,
557                                 uint_st->sirfsoc_rx_done);
558                 if (!sirfport->is_marco)
559                         wr_regl(port, ureg->sirfsoc_int_en_reg,
560                                 rd_regl(port, ureg->sirfsoc_int_en_reg) |
561                                 (uint_en->sirfsoc_rx_done_en));
562                 else
563                         wr_regl(port, ureg->sirfsoc_int_en_reg,
564                                         uint_en->sirfsoc_rx_done_en);
565         }
566         spin_unlock_irqrestore(&port->lock, flags);
567         tty_flip_buffer_push(&port->state->port);
568 }
569 
570 static void sirfsoc_uart_handle_rx_tmo(struct sirfsoc_uart_port *sirfport)
571 {
572         struct uart_port *port = &sirfport->port;
573         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
574         struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
575         struct dma_tx_state tx_state;
576         dmaengine_tx_status(sirfport->rx_dma_chan,
577                 sirfport->rx_dma_items[sirfport->rx_issued].cookie, &tx_state);
578         dmaengine_terminate_all(sirfport->rx_dma_chan);
579         sirfport->rx_dma_items[sirfport->rx_issued].xmit.head =
580                 SIRFSOC_RX_DMA_BUF_SIZE - tx_state.residue;
581         if (!sirfport->is_marco)
582                 wr_regl(port, ureg->sirfsoc_int_en_reg,
583                         rd_regl(port, ureg->sirfsoc_int_en_reg) &
584                         ~(uint_en->sirfsoc_rx_timeout_en));
585         else
586                 wr_regl(port, SIRFUART_INT_EN_CLR,
587                                 uint_en->sirfsoc_rx_timeout_en);
588         tasklet_schedule(&sirfport->rx_tmo_process_tasklet);
589 }
590 
591 static void sirfsoc_uart_handle_rx_done(struct sirfsoc_uart_port *sirfport)
592 {
593         struct uart_port *port = &sirfport->port;
594         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
595         struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
596         struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
597 
598         sirfsoc_uart_pio_rx_chars(port, 4 - sirfport->rx_io_count);
599         if (sirfport->rx_io_count == 4) {
600                 sirfport->rx_io_count = 0;
601                 if (!sirfport->is_marco)
602                         wr_regl(port, ureg->sirfsoc_int_en_reg,
603                                 rd_regl(port, ureg->sirfsoc_int_en_reg) &
604                                 ~(uint_en->sirfsoc_rx_done_en));
605                 else
606                         wr_regl(port, SIRFUART_INT_EN_CLR,
607                                         uint_en->sirfsoc_rx_done_en);
608                 wr_regl(port, ureg->sirfsoc_int_st_reg,
609                                 uint_st->sirfsoc_rx_timeout);
610                 sirfsoc_uart_start_next_rx_dma(port);
611         }
612 }
613 
614 static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
615 {
616         unsigned long intr_status;
617         unsigned long cts_status;
618         unsigned long flag = TTY_NORMAL;
619         struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
620         struct uart_port *port = &sirfport->port;
621         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
622         struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
623         struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
624         struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
625         struct uart_state *state = port->state;
626         struct circ_buf *xmit = &port->state->xmit;
627         spin_lock(&port->lock);
628         intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg);
629         wr_regl(port, ureg->sirfsoc_int_st_reg, intr_status);
630         intr_status &= rd_regl(port, ureg->sirfsoc_int_en_reg);
631         if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT(port, uint_st)))) {
632                 if (intr_status & uint_st->sirfsoc_rxd_brk) {
633                         port->icount.brk++;
634                         if (uart_handle_break(port))
635                                 goto recv_char;
636                 }
637                 if (intr_status & uint_st->sirfsoc_rx_oflow)
638                         port->icount.overrun++;
639                 if (intr_status & uint_st->sirfsoc_frm_err) {
640                         port->icount.frame++;
641                         flag = TTY_FRAME;
642                 }
643                 if (intr_status & uint_st->sirfsoc_parity_err)
644                         flag = TTY_PARITY;
645                 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
646                 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
647                 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
648                 intr_status &= port->read_status_mask;
649                 uart_insert_char(port, intr_status,
650                                         uint_en->sirfsoc_rx_oflow_en, 0, flag);
651         }
652 recv_char:
653         if ((sirfport->uart_reg->uart_type == SIRF_REAL_UART) &&
654                         (intr_status & SIRFUART_CTS_INT_ST(uint_st)) &&
655                         !sirfport->tx_dma_state) {
656                 cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) &
657                                         SIRFUART_AFC_CTS_STATUS;
658                 if (cts_status != 0)
659                         cts_status = 0;
660                 else
661                         cts_status = 1;
662                 uart_handle_cts_change(port, cts_status);
663                 wake_up_interruptible(&state->port.delta_msr_wait);
664         }
665         if (sirfport->rx_dma_chan) {
666                 if (intr_status & uint_st->sirfsoc_rx_timeout)
667                         sirfsoc_uart_handle_rx_tmo(sirfport);
668                 if (intr_status & uint_st->sirfsoc_rx_done)
669                         sirfsoc_uart_handle_rx_done(sirfport);
670         } else {
671                 if (intr_status & SIRFUART_RX_IO_INT_ST(uint_st))
672                         sirfsoc_uart_pio_rx_chars(port,
673                                         SIRFSOC_UART_IO_RX_MAX_CNT);
674         }
675         spin_unlock(&port->lock);
676         tty_flip_buffer_push(&state->port);
677         spin_lock(&port->lock);
678         if (intr_status & uint_st->sirfsoc_txfifo_empty) {
679                 if (sirfport->tx_dma_chan)
680                         sirfsoc_uart_tx_with_dma(sirfport);
681                 else {
682                         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
683                                 spin_unlock(&port->lock);
684                                 return IRQ_HANDLED;
685                         } else {
686                                 sirfsoc_uart_pio_tx_chars(sirfport,
687                                         SIRFSOC_UART_IO_TX_REASONABLE_CNT);
688                                 if ((uart_circ_empty(xmit)) &&
689                                 (rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
690                                 ufifo_st->ff_empty(port->line)))
691                                         sirfsoc_uart_stop_tx(port);
692                         }
693                 }
694         }
695         spin_unlock(&port->lock);
696 
697         return IRQ_HANDLED;
698 }
699 
700 static void sirfsoc_uart_rx_dma_complete_tl(unsigned long param)
701 {
702         struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param;
703         struct uart_port *port = &sirfport->port;
704         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
705         struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
706         unsigned long flags;
707         struct dma_tx_state tx_state;
708         spin_lock_irqsave(&port->lock, flags);
709         while (DMA_COMPLETE == dmaengine_tx_status(sirfport->rx_dma_chan,
710                         sirfport->rx_dma_items[sirfport->rx_completed].cookie, &tx_state)) {
711                 sirfsoc_uart_insert_rx_buf_to_tty(sirfport,
712                                         SIRFSOC_RX_DMA_BUF_SIZE);
713                 if (rd_regl(port, ureg->sirfsoc_int_en_reg) &
714                                 uint_en->sirfsoc_rx_timeout_en)
715                         sirfsoc_rx_submit_one_dma_desc(port,
716                                         sirfport->rx_completed++);
717                 else
718                         sirfport->rx_completed++;
719                 sirfport->rx_completed %= SIRFSOC_RX_LOOP_BUF_CNT;
720         }
721         spin_unlock_irqrestore(&port->lock, flags);
722         tty_flip_buffer_push(&port->state->port);
723 }
724 
725 static void sirfsoc_uart_rx_dma_complete_callback(void *param)
726 {
727         struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param;
728         unsigned long flags;
729 
730         spin_lock_irqsave(&sirfport->port.lock, flags);
731         sirfport->rx_issued++;
732         sirfport->rx_issued %= SIRFSOC_RX_LOOP_BUF_CNT;
733         tasklet_schedule(&sirfport->rx_dma_complete_tasklet);
734         spin_unlock_irqrestore(&sirfport->port.lock, flags);
735 }
736 
737 /* submit rx dma task into dmaengine */
738 static void sirfsoc_uart_start_next_rx_dma(struct uart_port *port)
739 {
740         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
741         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
742         struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
743         int i;
744         sirfport->rx_io_count = 0;
745         wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
746                 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
747                 ~SIRFUART_IO_MODE);
748         for (i = 0; i < SIRFSOC_RX_LOOP_BUF_CNT; i++)
749                 sirfsoc_rx_submit_one_dma_desc(port, i);
750         sirfport->rx_completed = sirfport->rx_issued = 0;
751         if (!sirfport->is_marco)
752                 wr_regl(port, ureg->sirfsoc_int_en_reg,
753                                 rd_regl(port, ureg->sirfsoc_int_en_reg) |
754                                 SIRFUART_RX_DMA_INT_EN(port, uint_en));
755         else
756                 wr_regl(port, ureg->sirfsoc_int_en_reg,
757                         SIRFUART_RX_DMA_INT_EN(port, uint_en));
758 }
759 
760 static void sirfsoc_uart_start_rx(struct uart_port *port)
761 {
762         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
763         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
764         struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
765 
766         sirfport->rx_io_count = 0;
767         wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
768         wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
769         wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
770         if (sirfport->rx_dma_chan)
771                 sirfsoc_uart_start_next_rx_dma(port);
772         else {
773                 if (!sirfport->is_marco)
774                         wr_regl(port, ureg->sirfsoc_int_en_reg,
775                                 rd_regl(port, ureg->sirfsoc_int_en_reg) |
776                                 SIRFUART_RX_IO_INT_EN(port, uint_en));
777                 else
778                         wr_regl(port, ureg->sirfsoc_int_en_reg,
779                                 SIRFUART_RX_IO_INT_EN(port, uint_en));
780         }
781 }
782 
783 static unsigned int
784 sirfsoc_usp_calc_sample_div(unsigned long set_rate,
785                 unsigned long ioclk_rate, unsigned long *sample_reg)
786 {
787         unsigned long min_delta = ~0UL;
788         unsigned short sample_div;
789         unsigned long ioclk_div = 0;
790         unsigned long temp_delta;
791 
792         for (sample_div = SIRF_MIN_SAMPLE_DIV;
793                         sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
794                 temp_delta = ioclk_rate -
795                 (ioclk_rate + (set_rate * sample_div) / 2)
796                 / (set_rate * sample_div) * set_rate * sample_div;
797 
798                 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
799                 if (temp_delta < min_delta) {
800                         ioclk_div = (2 * ioclk_rate /
801                                 (set_rate * sample_div) + 1) / 2 - 1;
802                         if (ioclk_div > SIRF_IOCLK_DIV_MAX)
803                                 continue;
804                         min_delta = temp_delta;
805                         *sample_reg = sample_div;
806                         if (!temp_delta)
807                                 break;
808                 }
809         }
810         return ioclk_div;
811 }
812 
813 static unsigned int
814 sirfsoc_uart_calc_sample_div(unsigned long baud_rate,
815                         unsigned long ioclk_rate, unsigned long *set_baud)
816 {
817         unsigned long min_delta = ~0UL;
818         unsigned short sample_div;
819         unsigned int regv = 0;
820         unsigned long ioclk_div;
821         unsigned long baud_tmp;
822         int temp_delta;
823 
824         for (sample_div = SIRF_MIN_SAMPLE_DIV;
825                         sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
826                 ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1;
827                 if (ioclk_div > SIRF_IOCLK_DIV_MAX)
828                         continue;
829                 baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1));
830                 temp_delta = baud_tmp - baud_rate;
831                 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
832                 if (temp_delta < min_delta) {
833                         regv = regv & (~SIRF_IOCLK_DIV_MASK);
834                         regv = regv | ioclk_div;
835                         regv = regv & (~SIRF_SAMPLE_DIV_MASK);
836                         regv = regv | (sample_div << SIRF_SAMPLE_DIV_SHIFT);
837                         min_delta = temp_delta;
838                         *set_baud = baud_tmp;
839                 }
840         }
841         return regv;
842 }
843 
844 static void sirfsoc_uart_set_termios(struct uart_port *port,
845                                        struct ktermios *termios,
846                                        struct ktermios *old)
847 {
848         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
849         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
850         struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
851         unsigned long   config_reg = 0;
852         unsigned long   baud_rate;
853         unsigned long   set_baud;
854         unsigned long   flags;
855         unsigned long   ic;
856         unsigned int    clk_div_reg = 0;
857         unsigned long   txfifo_op_reg, ioclk_rate;
858         unsigned long   rx_time_out;
859         int             threshold_div;
860         u32             data_bit_len, stop_bit_len, len_val;
861         unsigned long   sample_div_reg = 0xf;
862         ioclk_rate      = port->uartclk;
863 
864         switch (termios->c_cflag & CSIZE) {
865         default:
866         case CS8:
867                 data_bit_len = 8;
868                 config_reg |= SIRFUART_DATA_BIT_LEN_8;
869                 break;
870         case CS7:
871                 data_bit_len = 7;
872                 config_reg |= SIRFUART_DATA_BIT_LEN_7;
873                 break;
874         case CS6:
875                 data_bit_len = 6;
876                 config_reg |= SIRFUART_DATA_BIT_LEN_6;
877                 break;
878         case CS5:
879                 data_bit_len = 5;
880                 config_reg |= SIRFUART_DATA_BIT_LEN_5;
881                 break;
882         }
883         if (termios->c_cflag & CSTOPB) {
884                 config_reg |= SIRFUART_STOP_BIT_LEN_2;
885                 stop_bit_len = 2;
886         } else
887                 stop_bit_len = 1;
888 
889         spin_lock_irqsave(&port->lock, flags);
890         port->read_status_mask = uint_en->sirfsoc_rx_oflow_en;
891         port->ignore_status_mask = 0;
892         if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
893                 if (termios->c_iflag & INPCK)
894                         port->read_status_mask |= uint_en->sirfsoc_frm_err_en |
895                                 uint_en->sirfsoc_parity_err_en;
896         } else {
897                 if (termios->c_iflag & INPCK)
898                         port->read_status_mask |= uint_en->sirfsoc_frm_err_en;
899         }
900         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
901                         port->read_status_mask |= uint_en->sirfsoc_rxd_brk_en;
902         if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
903                 if (termios->c_iflag & IGNPAR)
904                         port->ignore_status_mask |=
905                                 uint_en->sirfsoc_frm_err_en |
906                                 uint_en->sirfsoc_parity_err_en;
907                 if (termios->c_cflag & PARENB) {
908                         if (termios->c_cflag & CMSPAR) {
909                                 if (termios->c_cflag & PARODD)
910                                         config_reg |= SIRFUART_STICK_BIT_MARK;
911                                 else
912                                         config_reg |= SIRFUART_STICK_BIT_SPACE;
913                         } else if (termios->c_cflag & PARODD) {
914                                 config_reg |= SIRFUART_STICK_BIT_ODD;
915                         } else {
916                                 config_reg |= SIRFUART_STICK_BIT_EVEN;
917                         }
918                 }
919         } else {
920                 if (termios->c_iflag & IGNPAR)
921                         port->ignore_status_mask |=
922                                 uint_en->sirfsoc_frm_err_en;
923                 if (termios->c_cflag & PARENB)
924                         dev_warn(port->dev,
925                                         "USP-UART not support parity err\n");
926         }
927         if (termios->c_iflag & IGNBRK) {
928                 port->ignore_status_mask |=
929                         uint_en->sirfsoc_rxd_brk_en;
930                 if (termios->c_iflag & IGNPAR)
931                         port->ignore_status_mask |=
932                                 uint_en->sirfsoc_rx_oflow_en;
933         }
934         if ((termios->c_cflag & CREAD) == 0)
935                 port->ignore_status_mask |= SIRFUART_DUMMY_READ;
936         /* Hardware Flow Control Settings */
937         if (UART_ENABLE_MS(port, termios->c_cflag)) {
938                 if (!sirfport->ms_enabled)
939                         sirfsoc_uart_enable_ms(port);
940         } else {
941                 if (sirfport->ms_enabled)
942                         sirfsoc_uart_disable_ms(port);
943         }
944         baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000);
945         if (ioclk_rate == 150000000) {
946                 for (ic = 0; ic < SIRF_BAUD_RATE_SUPPORT_NR; ic++)
947                         if (baud_rate == baudrate_to_regv[ic].baud_rate)
948                                 clk_div_reg = baudrate_to_regv[ic].reg_val;
949         }
950         set_baud = baud_rate;
951         if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
952                 if (unlikely(clk_div_reg == 0))
953                         clk_div_reg = sirfsoc_uart_calc_sample_div(baud_rate,
954                                         ioclk_rate, &set_baud);
955                 wr_regl(port, ureg->sirfsoc_divisor, clk_div_reg);
956         } else {
957                 clk_div_reg = sirfsoc_usp_calc_sample_div(baud_rate,
958                                 ioclk_rate, &sample_div_reg);
959                 sample_div_reg--;
960                 set_baud = ((ioclk_rate / (clk_div_reg+1) - 1) /
961                                 (sample_div_reg + 1));
962                 /* setting usp mode 2 */
963                 len_val = ((1 << SIRFSOC_USP_MODE2_RXD_DELAY_OFFSET) |
964                                 (1 << SIRFSOC_USP_MODE2_TXD_DELAY_OFFSET));
965                 len_val |= ((clk_div_reg & SIRFSOC_USP_MODE2_CLK_DIVISOR_MASK)
966                                 << SIRFSOC_USP_MODE2_CLK_DIVISOR_OFFSET);
967                 wr_regl(port, ureg->sirfsoc_mode2, len_val);
968         }
969         if (tty_termios_baud_rate(termios))
970                 tty_termios_encode_baud_rate(termios, set_baud, set_baud);
971         /* set receive timeout && data bits len */
972         rx_time_out = SIRFSOC_UART_RX_TIMEOUT(set_baud, 20000);
973         rx_time_out = SIRFUART_RECV_TIMEOUT_VALUE(rx_time_out);
974         txfifo_op_reg = rd_regl(port, ureg->sirfsoc_tx_fifo_op);
975         wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_STOP);
976         wr_regl(port, ureg->sirfsoc_tx_fifo_op,
977                         (txfifo_op_reg & ~SIRFUART_FIFO_START));
978         if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
979                 config_reg |= SIRFUART_RECV_TIMEOUT(port, rx_time_out);
980                 wr_regl(port, ureg->sirfsoc_line_ctrl, config_reg);
981         } else {
982                 /*tx frame ctrl*/
983                 len_val = (data_bit_len - 1) << SIRFSOC_USP_TX_DATA_LEN_OFFSET;
984                 len_val |= (data_bit_len + 1 + stop_bit_len - 1) <<
985                                 SIRFSOC_USP_TX_FRAME_LEN_OFFSET;
986                 len_val |= ((data_bit_len - 1) <<
987                                 SIRFSOC_USP_TX_SHIFTER_LEN_OFFSET);
988                 len_val |= (((clk_div_reg & 0xc00) >> 10) <<
989                                 SIRFSOC_USP_TX_CLK_DIVISOR_OFFSET);
990                 wr_regl(port, ureg->sirfsoc_tx_frame_ctrl, len_val);
991                 /*rx frame ctrl*/
992                 len_val = (data_bit_len - 1) << SIRFSOC_USP_RX_DATA_LEN_OFFSET;
993                 len_val |= (data_bit_len + 1 + stop_bit_len - 1) <<
994                                 SIRFSOC_USP_RX_FRAME_LEN_OFFSET;
995                 len_val |= (data_bit_len - 1) <<
996                                 SIRFSOC_USP_RX_SHIFTER_LEN_OFFSET;
997                 len_val |= (((clk_div_reg & 0xf000) >> 12) <<
998                                 SIRFSOC_USP_RX_CLK_DIVISOR_OFFSET);
999                 wr_regl(port, ureg->sirfsoc_rx_frame_ctrl, len_val);
1000                 /*async param*/
1001                 wr_regl(port, ureg->sirfsoc_async_param_reg,
1002                         (SIRFUART_RECV_TIMEOUT(port, rx_time_out)) |
1003                         (sample_div_reg & SIRFSOC_USP_ASYNC_DIV2_MASK) <<
1004                         SIRFSOC_USP_ASYNC_DIV2_OFFSET);
1005         }
1006         if (sirfport->tx_dma_chan)
1007                 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_DMA_MODE);
1008         else
1009                 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_IO_MODE);
1010         if (sirfport->rx_dma_chan)
1011                 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, SIRFUART_DMA_MODE);
1012         else
1013                 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, SIRFUART_IO_MODE);
1014         /* Reset Rx/Tx FIFO Threshold level for proper baudrate */
1015         if (set_baud < 1000000)
1016                 threshold_div = 1;
1017         else
1018                 threshold_div = 2;
1019         wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl,
1020                                 SIRFUART_FIFO_THD(port) / threshold_div);
1021         wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl,
1022                                 SIRFUART_FIFO_THD(port) / threshold_div);
1023         txfifo_op_reg |= SIRFUART_FIFO_START;
1024         wr_regl(port, ureg->sirfsoc_tx_fifo_op, txfifo_op_reg);
1025         uart_update_timeout(port, termios->c_cflag, set_baud);
1026         sirfsoc_uart_start_rx(port);
1027         wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_TX_EN | SIRFUART_RX_EN);
1028         spin_unlock_irqrestore(&port->lock, flags);
1029 }
1030 
1031 static void sirfsoc_uart_pm(struct uart_port *port, unsigned int state,
1032                               unsigned int oldstate)
1033 {
1034         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1035         if (!state)
1036                 clk_prepare_enable(sirfport->clk);
1037         else
1038                 clk_disable_unprepare(sirfport->clk);
1039 }
1040 
1041 static int sirfsoc_uart_startup(struct uart_port *port)
1042 {
1043         struct sirfsoc_uart_port *sirfport      = to_sirfport(port);
1044         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
1045         unsigned int index                      = port->line;
1046         int ret;
1047         set_irq_flags(port->irq, IRQF_VALID | IRQF_NOAUTOEN);
1048         ret = request_irq(port->irq,
1049                                 sirfsoc_uart_isr,
1050                                 0,
1051                                 SIRFUART_PORT_NAME,
1052                                 sirfport);
1053         if (ret != 0) {
1054                 dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n",
1055                                                         index, port->irq);
1056                 goto irq_err;
1057         }
1058 
1059         /* initial hardware settings */
1060         wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
1061                 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl) |
1062                 SIRFUART_IO_MODE);
1063         wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
1064                 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
1065                 SIRFUART_IO_MODE);
1066         wr_regl(port, ureg->sirfsoc_tx_dma_io_len, 0);
1067         wr_regl(port, ureg->sirfsoc_rx_dma_io_len, 0);
1068         wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_RX_EN | SIRFUART_TX_EN);
1069         if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
1070                 wr_regl(port, ureg->sirfsoc_mode1,
1071                         SIRFSOC_USP_ENDIAN_CTRL_LSBF |
1072                         SIRFSOC_USP_EN);
1073         wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_RESET);
1074         wr_regl(port, ureg->sirfsoc_tx_fifo_op, 0);
1075         wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
1076         wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
1077         wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, SIRFUART_FIFO_THD(port));
1078         wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, SIRFUART_FIFO_THD(port));
1079         if (sirfport->rx_dma_chan)
1080                 wr_regl(port, ureg->sirfsoc_rx_fifo_level_chk,
1081                         SIRFUART_RX_FIFO_CHK_SC(port->line, 0x4) |
1082                         SIRFUART_RX_FIFO_CHK_LC(port->line, 0xe) |
1083                         SIRFUART_RX_FIFO_CHK_HC(port->line, 0x1b));
1084         if (sirfport->tx_dma_chan) {
1085                 sirfport->tx_dma_state = TX_DMA_IDLE;
1086                 wr_regl(port, ureg->sirfsoc_tx_fifo_level_chk,
1087                                 SIRFUART_TX_FIFO_CHK_SC(port->line, 0x1b) |
1088                                 SIRFUART_TX_FIFO_CHK_LC(port->line, 0xe) |
1089                                 SIRFUART_TX_FIFO_CHK_HC(port->line, 0x4));
1090         }
1091         sirfport->ms_enabled = false;
1092         if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
1093                 sirfport->hw_flow_ctrl) {
1094                 set_irq_flags(gpio_to_irq(sirfport->cts_gpio),
1095                         IRQF_VALID | IRQF_NOAUTOEN);
1096                 ret = request_irq(gpio_to_irq(sirfport->cts_gpio),
1097                         sirfsoc_uart_usp_cts_handler, IRQF_TRIGGER_FALLING |
1098                         IRQF_TRIGGER_RISING, "usp_cts_irq", sirfport);
1099                 if (ret != 0) {
1100                         dev_err(port->dev, "UART-USP:request gpio irq fail\n");
1101                         goto init_rx_err;
1102                 }
1103         }
1104 
1105         enable_irq(port->irq);
1106 
1107         return 0;
1108 init_rx_err:
1109         free_irq(port->irq, sirfport);
1110 irq_err:
1111         return ret;
1112 }
1113 
1114 static void sirfsoc_uart_shutdown(struct uart_port *port)
1115 {
1116         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1117         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
1118         if (!sirfport->is_marco)
1119                 wr_regl(port, ureg->sirfsoc_int_en_reg, 0);
1120         else
1121                 wr_regl(port, SIRFUART_INT_EN_CLR, ~0UL);
1122 
1123         free_irq(port->irq, sirfport);
1124         if (sirfport->ms_enabled)
1125                 sirfsoc_uart_disable_ms(port);
1126         if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
1127                         sirfport->hw_flow_ctrl) {
1128                 gpio_set_value(sirfport->rts_gpio, 1);
1129                 free_irq(gpio_to_irq(sirfport->cts_gpio), sirfport);
1130         }
1131         if (sirfport->tx_dma_chan)
1132                 sirfport->tx_dma_state = TX_DMA_IDLE;
1133 }
1134 
1135 static const char *sirfsoc_uart_type(struct uart_port *port)
1136 {
1137         return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL;
1138 }
1139 
1140 static int sirfsoc_uart_request_port(struct uart_port *port)
1141 {
1142         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1143         struct sirfsoc_uart_param *uart_param = &sirfport->uart_reg->uart_param;
1144         void *ret;
1145         ret = request_mem_region(port->mapbase,
1146                 SIRFUART_MAP_SIZE, uart_param->port_name);
1147         return ret ? 0 : -EBUSY;
1148 }
1149 
1150 static void sirfsoc_uart_release_port(struct uart_port *port)
1151 {
1152         release_mem_region(port->mapbase, SIRFUART_MAP_SIZE);
1153 }
1154 
1155 static void sirfsoc_uart_config_port(struct uart_port *port, int flags)
1156 {
1157         if (flags & UART_CONFIG_TYPE) {
1158                 port->type = SIRFSOC_PORT_TYPE;
1159                 sirfsoc_uart_request_port(port);
1160         }
1161 }
1162 
1163 static struct uart_ops sirfsoc_uart_ops = {
1164         .tx_empty       = sirfsoc_uart_tx_empty,
1165         .get_mctrl      = sirfsoc_uart_get_mctrl,
1166         .set_mctrl      = sirfsoc_uart_set_mctrl,
1167         .stop_tx        = sirfsoc_uart_stop_tx,
1168         .start_tx       = sirfsoc_uart_start_tx,
1169         .stop_rx        = sirfsoc_uart_stop_rx,
1170         .enable_ms      = sirfsoc_uart_enable_ms,
1171         .break_ctl      = sirfsoc_uart_break_ctl,
1172         .startup        = sirfsoc_uart_startup,
1173         .shutdown       = sirfsoc_uart_shutdown,
1174         .set_termios    = sirfsoc_uart_set_termios,
1175         .pm             = sirfsoc_uart_pm,
1176         .type           = sirfsoc_uart_type,
1177         .release_port   = sirfsoc_uart_release_port,
1178         .request_port   = sirfsoc_uart_request_port,
1179         .config_port    = sirfsoc_uart_config_port,
1180 };
1181 
1182 #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
1183 static int __init
1184 sirfsoc_uart_console_setup(struct console *co, char *options)
1185 {
1186         unsigned int baud = 115200;
1187         unsigned int bits = 8;
1188         unsigned int parity = 'n';
1189         unsigned int flow = 'n';
1190         struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
1191         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1192         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
1193         if (co->index < 0 || co->index >= SIRFSOC_UART_NR)
1194                 return -EINVAL;
1195 
1196         if (!port->mapbase)
1197                 return -ENODEV;
1198 
1199         /* enable usp in mode1 register */
1200         if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
1201                 wr_regl(port, ureg->sirfsoc_mode1, SIRFSOC_USP_EN |
1202                                 SIRFSOC_USP_ENDIAN_CTRL_LSBF);
1203         if (options)
1204                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1205         port->cons = co;
1206 
1207         /* default console tx/rx transfer using io mode */
1208         sirfport->rx_dma_chan = NULL;
1209         sirfport->tx_dma_chan = NULL;
1210         return uart_set_options(port, co, baud, parity, bits, flow);
1211 }
1212 
1213 static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
1214 {
1215         struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1216         struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
1217         struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
1218         while (rd_regl(port,
1219                 ureg->sirfsoc_tx_fifo_status) & ufifo_st->ff_full(port->line))
1220                 cpu_relax();
1221         wr_regl(port, ureg->sirfsoc_tx_fifo_data, ch);
1222 }
1223 
1224 static void sirfsoc_uart_console_write(struct console *co, const char *s,
1225                                                         unsigned int count)
1226 {
1227         struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
1228         uart_console_write(port, s, count, sirfsoc_uart_console_putchar);
1229 }
1230 
1231 static struct console sirfsoc_uart_console = {
1232         .name           = SIRFSOC_UART_NAME,
1233         .device         = uart_console_device,
1234         .flags          = CON_PRINTBUFFER,
1235         .index          = -1,
1236         .write          = sirfsoc_uart_console_write,
1237         .setup          = sirfsoc_uart_console_setup,
1238         .data           = &sirfsoc_uart_drv,
1239 };
1240 
1241 static int __init sirfsoc_uart_console_init(void)
1242 {
1243         register_console(&sirfsoc_uart_console);
1244         return 0;
1245 }
1246 console_initcall(sirfsoc_uart_console_init);
1247 #endif
1248 
1249 static struct uart_driver sirfsoc_uart_drv = {
1250         .owner          = THIS_MODULE,
1251         .driver_name    = SIRFUART_PORT_NAME,
1252         .nr             = SIRFSOC_UART_NR,
1253         .dev_name       = SIRFSOC_UART_NAME,
1254         .major          = SIRFSOC_UART_MAJOR,
1255         .minor          = SIRFSOC_UART_MINOR,
1256 #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
1257         .cons                   = &sirfsoc_uart_console,
1258 #else
1259         .cons                   = NULL,
1260 #endif
1261 };
1262 
1263 static struct of_device_id sirfsoc_uart_ids[] = {
1264         { .compatible = "sirf,prima2-uart", .data = &sirfsoc_uart,},
1265         { .compatible = "sirf,marco-uart", .data = &sirfsoc_uart},
1266         { .compatible = "sirf,prima2-usp-uart", .data = &sirfsoc_usp},
1267         {}
1268 };
1269 MODULE_DEVICE_TABLE(of, sirfsoc_uart_ids);
1270 
1271 static int sirfsoc_uart_probe(struct platform_device *pdev)
1272 {
1273         struct sirfsoc_uart_port *sirfport;
1274         struct uart_port *port;
1275         struct resource *res;
1276         int ret;
1277         int i, j;
1278         struct dma_slave_config slv_cfg = {
1279                 .src_maxburst = 2,
1280         };
1281         struct dma_slave_config tx_slv_cfg = {
1282                 .dst_maxburst = 2,
1283         };
1284         const struct of_device_id *match;
1285 
1286         match = of_match_node(sirfsoc_uart_ids, pdev->dev.of_node);
1287         if (of_property_read_u32(pdev->dev.of_node, "cell-index", &pdev->id)) {
1288                 dev_err(&pdev->dev,
1289                         "Unable to find cell-index in uart node.\n");
1290                 ret = -EFAULT;
1291                 goto err;
1292         }
1293         if (of_device_is_compatible(pdev->dev.of_node, "sirf,prima2-usp-uart"))
1294                 pdev->id += ((struct sirfsoc_uart_register *)
1295                                 match->data)->uart_param.register_uart_nr;
1296         sirfport = &sirfsoc_uart_ports[pdev->id];
1297         port = &sirfport->port;
1298         port->dev = &pdev->dev;
1299         port->private_data = sirfport;
1300         sirfport->uart_reg = (struct sirfsoc_uart_register *)match->data;
1301 
1302         sirfport->hw_flow_ctrl = of_property_read_bool(pdev->dev.of_node,
1303                 "sirf,uart-has-rtscts");
1304         if (of_device_is_compatible(pdev->dev.of_node, "sirf,prima2-uart"))
1305                 sirfport->uart_reg->uart_type = SIRF_REAL_UART;
1306         if (of_device_is_compatible(pdev->dev.of_node, "sirf,prima2-usp-uart")) {
1307                 sirfport->uart_reg->uart_type = SIRF_USP_UART;
1308                 if (!sirfport->hw_flow_ctrl)
1309                         goto usp_no_flow_control;
1310                 if (of_find_property(pdev->dev.of_node, "cts-gpios", NULL))
1311                         sirfport->cts_gpio = of_get_named_gpio(
1312                                         pdev->dev.of_node, "cts-gpios", 0);
1313                 else
1314                         sirfport->cts_gpio = -1;
1315                 if (of_find_property(pdev->dev.of_node, "rts-gpios", NULL))
1316                         sirfport->rts_gpio = of_get_named_gpio(
1317                                         pdev->dev.of_node, "rts-gpios", 0);
1318                 else
1319                         sirfport->rts_gpio = -1;
1320 
1321                 if ((!gpio_is_valid(sirfport->cts_gpio) ||
1322                          !gpio_is_valid(sirfport->rts_gpio))) {
1323                         ret = -EINVAL;
1324                         dev_err(&pdev->dev,
1325                                 "Usp flow control must have cts and rts gpio");
1326                         goto err;
1327                 }
1328                 ret = devm_gpio_request(&pdev->dev, sirfport->cts_gpio,
1329                                 "usp-cts-gpio");
1330                 if (ret) {
1331                         dev_err(&pdev->dev, "Unable request cts gpio");
1332                         goto err;
1333                 }
1334                 gpio_direction_input(sirfport->cts_gpio);
1335                 ret = devm_gpio_request(&pdev->dev, sirfport->rts_gpio,
1336                                 "usp-rts-gpio");
1337                 if (ret) {
1338                         dev_err(&pdev->dev, "Unable request rts gpio");
1339                         goto err;
1340                 }
1341                 gpio_direction_output(sirfport->rts_gpio, 1);
1342         }
1343 usp_no_flow_control:
1344         if (of_device_is_compatible(pdev->dev.of_node, "sirf,marco-uart"))
1345                 sirfport->is_marco = true;
1346 
1347         if (of_property_read_u32(pdev->dev.of_node,
1348                         "fifosize",
1349                         &port->fifosize)) {
1350                 dev_err(&pdev->dev,
1351                         "Unable to find fifosize in uart node.\n");
1352                 ret = -EFAULT;
1353                 goto err;
1354         }
1355 
1356         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1357         if (res == NULL) {
1358                 dev_err(&pdev->dev, "Insufficient resources.\n");
1359                 ret = -EFAULT;
1360                 goto err;
1361         }
1362         tasklet_init(&sirfport->rx_dma_complete_tasklet,
1363                         sirfsoc_uart_rx_dma_complete_tl, (unsigned long)sirfport);
1364         tasklet_init(&sirfport->rx_tmo_process_tasklet,
1365                         sirfsoc_rx_tmo_process_tl, (unsigned long)sirfport);
1366         port->mapbase = res->start;
1367         port->membase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1368         if (!port->membase) {
1369                 dev_err(&pdev->dev, "Cannot remap resource.\n");
1370                 ret = -ENOMEM;
1371                 goto err;
1372         }
1373         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1374         if (res == NULL) {
1375                 dev_err(&pdev->dev, "Insufficient resources.\n");
1376                 ret = -EFAULT;
1377                 goto err;
1378         }
1379         port->irq = res->start;
1380 
1381         sirfport->clk = clk_get(&pdev->dev, NULL);
1382         if (IS_ERR(sirfport->clk)) {
1383                 ret = PTR_ERR(sirfport->clk);
1384                 goto err;
1385         }
1386         port->uartclk = clk_get_rate(sirfport->clk);
1387 
1388         port->ops = &sirfsoc_uart_ops;
1389         spin_lock_init(&port->lock);
1390 
1391         platform_set_drvdata(pdev, sirfport);
1392         ret = uart_add_one_port(&sirfsoc_uart_drv, port);
1393         if (ret != 0) {
1394                 dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id);
1395                 goto port_err;
1396         }
1397 
1398         sirfport->rx_dma_chan = dma_request_slave_channel(port->dev, "rx");
1399         for (i = 0; sirfport->rx_dma_chan && i < SIRFSOC_RX_LOOP_BUF_CNT; i++) {
1400                 sirfport->rx_dma_items[i].xmit.buf =
1401                         dma_alloc_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
1402                         &sirfport->rx_dma_items[i].dma_addr, GFP_KERNEL);
1403                 if (!sirfport->rx_dma_items[i].xmit.buf) {
1404                         dev_err(port->dev, "Uart alloc bufa failed\n");
1405                         ret = -ENOMEM;
1406                         goto alloc_coherent_err;
1407                 }
1408                 sirfport->rx_dma_items[i].xmit.head =
1409                         sirfport->rx_dma_items[i].xmit.tail = 0;
1410         }
1411         if (sirfport->rx_dma_chan)
1412                 dmaengine_slave_config(sirfport->rx_dma_chan, &slv_cfg);
1413         sirfport->tx_dma_chan = dma_request_slave_channel(port->dev, "tx");
1414         if (sirfport->tx_dma_chan)
1415                 dmaengine_slave_config(sirfport->tx_dma_chan, &tx_slv_cfg);
1416 
1417         return 0;
1418 alloc_coherent_err:
1419         for (j = 0; j < i; j++)
1420                 dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
1421                                 sirfport->rx_dma_items[j].xmit.buf,
1422                                 sirfport->rx_dma_items[j].dma_addr);
1423         dma_release_channel(sirfport->rx_dma_chan);
1424 port_err:
1425         clk_put(sirfport->clk);
1426 err:
1427         return ret;
1428 }
1429 
1430 static int sirfsoc_uart_remove(struct platform_device *pdev)
1431 {
1432         struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
1433         struct uart_port *port = &sirfport->port;
1434         clk_put(sirfport->clk);
1435         uart_remove_one_port(&sirfsoc_uart_drv, port);
1436         if (sirfport->rx_dma_chan) {
1437                 int i;
1438                 dmaengine_terminate_all(sirfport->rx_dma_chan);
1439                 dma_release_channel(sirfport->rx_dma_chan);
1440                 for (i = 0; i < SIRFSOC_RX_LOOP_BUF_CNT; i++)
1441                         dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
1442                                         sirfport->rx_dma_items[i].xmit.buf,
1443                                         sirfport->rx_dma_items[i].dma_addr);
1444         }
1445         if (sirfport->tx_dma_chan) {
1446                 dmaengine_terminate_all(sirfport->tx_dma_chan);
1447                 dma_release_channel(sirfport->tx_dma_chan);
1448         }
1449         return 0;
1450 }
1451 
1452 #ifdef CONFIG_PM_SLEEP
1453 static int
1454 sirfsoc_uart_suspend(struct device *pdev)
1455 {
1456         struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev);
1457         struct uart_port *port = &sirfport->port;
1458         uart_suspend_port(&sirfsoc_uart_drv, port);
1459         return 0;
1460 }
1461 
1462 static int sirfsoc_uart_resume(struct device *pdev)
1463 {
1464         struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev);
1465         struct uart_port *port = &sirfport->port;
1466         uart_resume_port(&sirfsoc_uart_drv, port);
1467         return 0;
1468 }
1469 #endif
1470 
1471 static const struct dev_pm_ops sirfsoc_uart_pm_ops = {
1472         SET_SYSTEM_SLEEP_PM_OPS(sirfsoc_uart_suspend, sirfsoc_uart_resume)
1473 };
1474 
1475 static struct platform_driver sirfsoc_uart_driver = {
1476         .probe          = sirfsoc_uart_probe,
1477         .remove         = sirfsoc_uart_remove,
1478         .driver         = {
1479                 .name   = SIRFUART_PORT_NAME,
1480                 .owner  = THIS_MODULE,
1481                 .of_match_table = sirfsoc_uart_ids,
1482                 .pm     = &sirfsoc_uart_pm_ops,
1483         },
1484 };
1485 
1486 static int __init sirfsoc_uart_init(void)
1487 {
1488         int ret = 0;
1489 
1490         ret = uart_register_driver(&sirfsoc_uart_drv);
1491         if (ret)
1492                 goto out;
1493 
1494         ret = platform_driver_register(&sirfsoc_uart_driver);
1495         if (ret)
1496                 uart_unregister_driver(&sirfsoc_uart_drv);
1497 out:
1498         return ret;
1499 }
1500 module_init(sirfsoc_uart_init);
1501 
1502 static void __exit sirfsoc_uart_exit(void)
1503 {
1504         platform_driver_unregister(&sirfsoc_uart_driver);
1505         uart_unregister_driver(&sirfsoc_uart_drv);
1506 }
1507 module_exit(sirfsoc_uart_exit);
1508 
1509 MODULE_LICENSE("GPL v2");
1510 MODULE_AUTHOR("Bin Shi <Bin.Shi@csr.com>, Rong Wang<Rong.Wang@csr.com>");
1511 MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver");
1512 

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