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Linux/drivers/tty/serial/sh-sci.c

  1 /*
  2  * SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
  3  *
  4  *  Copyright (C) 2002 - 2011  Paul Mundt
  5  *  Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
  6  *
  7  * based off of the old drivers/char/sh-sci.c by:
  8  *
  9  *   Copyright (C) 1999, 2000  Niibe Yutaka
 10  *   Copyright (C) 2000  Sugioka Toshinobu
 11  *   Modified to support multiple serial ports. Stuart Menefy (May 2000).
 12  *   Modified to support SecureEdge. David McCullough (2002)
 13  *   Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
 14  *   Removed SH7300 support (Jul 2007).
 15  *
 16  * This file is subject to the terms and conditions of the GNU General Public
 17  * License.  See the file "COPYING" in the main directory of this archive
 18  * for more details.
 19  */
 20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 21 #define SUPPORT_SYSRQ
 22 #endif
 23 
 24 #undef DEBUG
 25 
 26 #include <linux/clk.h>
 27 #include <linux/console.h>
 28 #include <linux/ctype.h>
 29 #include <linux/cpufreq.h>
 30 #include <linux/delay.h>
 31 #include <linux/dmaengine.h>
 32 #include <linux/dma-mapping.h>
 33 #include <linux/err.h>
 34 #include <linux/errno.h>
 35 #include <linux/init.h>
 36 #include <linux/interrupt.h>
 37 #include <linux/ioport.h>
 38 #include <linux/major.h>
 39 #include <linux/module.h>
 40 #include <linux/mm.h>
 41 #include <linux/notifier.h>
 42 #include <linux/of.h>
 43 #include <linux/platform_device.h>
 44 #include <linux/pm_runtime.h>
 45 #include <linux/scatterlist.h>
 46 #include <linux/serial.h>
 47 #include <linux/serial_sci.h>
 48 #include <linux/sh_dma.h>
 49 #include <linux/slab.h>
 50 #include <linux/string.h>
 51 #include <linux/sysrq.h>
 52 #include <linux/timer.h>
 53 #include <linux/tty.h>
 54 #include <linux/tty_flip.h>
 55 
 56 #ifdef CONFIG_SUPERH
 57 #include <asm/sh_bios.h>
 58 #endif
 59 
 60 #include "sh-sci.h"
 61 
 62 /* Offsets into the sci_port->irqs array */
 63 enum {
 64         SCIx_ERI_IRQ,
 65         SCIx_RXI_IRQ,
 66         SCIx_TXI_IRQ,
 67         SCIx_BRI_IRQ,
 68         SCIx_NR_IRQS,
 69 
 70         SCIx_MUX_IRQ = SCIx_NR_IRQS,    /* special case */
 71 };
 72 
 73 #define SCIx_IRQ_IS_MUXED(port)                 \
 74         ((port)->irqs[SCIx_ERI_IRQ] ==  \
 75          (port)->irqs[SCIx_RXI_IRQ]) || \
 76         ((port)->irqs[SCIx_ERI_IRQ] &&  \
 77          ((port)->irqs[SCIx_RXI_IRQ] < 0))
 78 
 79 struct sci_port {
 80         struct uart_port        port;
 81 
 82         /* Platform configuration */
 83         struct plat_sci_port    *cfg;
 84         unsigned int            overrun_reg;
 85         unsigned int            overrun_mask;
 86         unsigned int            error_mask;
 87         unsigned int            error_clear;
 88         unsigned int            sampling_rate;
 89         resource_size_t         reg_size;
 90 
 91         /* Break timer */
 92         struct timer_list       break_timer;
 93         int                     break_flag;
 94 
 95         /* Interface clock */
 96         struct clk              *iclk;
 97         /* Function clock */
 98         struct clk              *fclk;
 99 
100         int                     irqs[SCIx_NR_IRQS];
101         char                    *irqstr[SCIx_NR_IRQS];
102 
103         struct dma_chan                 *chan_tx;
104         struct dma_chan                 *chan_rx;
105 
106 #ifdef CONFIG_SERIAL_SH_SCI_DMA
107         dma_cookie_t                    cookie_tx;
108         dma_cookie_t                    cookie_rx[2];
109         dma_cookie_t                    active_rx;
110         dma_addr_t                      tx_dma_addr;
111         unsigned int                    tx_dma_len;
112         struct scatterlist              sg_rx[2];
113         void                            *rx_buf[2];
114         size_t                          buf_len_rx;
115         struct work_struct              work_tx;
116         struct timer_list               rx_timer;
117         unsigned int                    rx_timeout;
118 #endif
119 
120         struct notifier_block           freq_transition;
121 };
122 
123 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
124 
125 static struct sci_port sci_ports[SCI_NPORTS];
126 static struct uart_driver sci_uart_driver;
127 
128 static inline struct sci_port *
129 to_sci_port(struct uart_port *uart)
130 {
131         return container_of(uart, struct sci_port, port);
132 }
133 
134 struct plat_sci_reg {
135         u8 offset, size;
136 };
137 
138 /* Helper for invalidating specific entries of an inherited map. */
139 #define sci_reg_invalid { .offset = 0, .size = 0 }
140 
141 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
142         [SCIx_PROBE_REGTYPE] = {
143                 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
144         },
145 
146         /*
147          * Common SCI definitions, dependent on the port's regshift
148          * value.
149          */
150         [SCIx_SCI_REGTYPE] = {
151                 [SCSMR]         = { 0x00,  8 },
152                 [SCBRR]         = { 0x01,  8 },
153                 [SCSCR]         = { 0x02,  8 },
154                 [SCxTDR]        = { 0x03,  8 },
155                 [SCxSR]         = { 0x04,  8 },
156                 [SCxRDR]        = { 0x05,  8 },
157                 [SCFCR]         = sci_reg_invalid,
158                 [SCFDR]         = sci_reg_invalid,
159                 [SCTFDR]        = sci_reg_invalid,
160                 [SCRFDR]        = sci_reg_invalid,
161                 [SCSPTR]        = sci_reg_invalid,
162                 [SCLSR]         = sci_reg_invalid,
163                 [HSSRR]         = sci_reg_invalid,
164                 [SCPCR]         = sci_reg_invalid,
165                 [SCPDR]         = sci_reg_invalid,
166         },
167 
168         /*
169          * Common definitions for legacy IrDA ports, dependent on
170          * regshift value.
171          */
172         [SCIx_IRDA_REGTYPE] = {
173                 [SCSMR]         = { 0x00,  8 },
174                 [SCBRR]         = { 0x01,  8 },
175                 [SCSCR]         = { 0x02,  8 },
176                 [SCxTDR]        = { 0x03,  8 },
177                 [SCxSR]         = { 0x04,  8 },
178                 [SCxRDR]        = { 0x05,  8 },
179                 [SCFCR]         = { 0x06,  8 },
180                 [SCFDR]         = { 0x07, 16 },
181                 [SCTFDR]        = sci_reg_invalid,
182                 [SCRFDR]        = sci_reg_invalid,
183                 [SCSPTR]        = sci_reg_invalid,
184                 [SCLSR]         = sci_reg_invalid,
185                 [HSSRR]         = sci_reg_invalid,
186                 [SCPCR]         = sci_reg_invalid,
187                 [SCPDR]         = sci_reg_invalid,
188         },
189 
190         /*
191          * Common SCIFA definitions.
192          */
193         [SCIx_SCIFA_REGTYPE] = {
194                 [SCSMR]         = { 0x00, 16 },
195                 [SCBRR]         = { 0x04,  8 },
196                 [SCSCR]         = { 0x08, 16 },
197                 [SCxTDR]        = { 0x20,  8 },
198                 [SCxSR]         = { 0x14, 16 },
199                 [SCxRDR]        = { 0x24,  8 },
200                 [SCFCR]         = { 0x18, 16 },
201                 [SCFDR]         = { 0x1c, 16 },
202                 [SCTFDR]        = sci_reg_invalid,
203                 [SCRFDR]        = sci_reg_invalid,
204                 [SCSPTR]        = sci_reg_invalid,
205                 [SCLSR]         = sci_reg_invalid,
206                 [HSSRR]         = sci_reg_invalid,
207                 [SCPCR]         = { 0x30, 16 },
208                 [SCPDR]         = { 0x34, 16 },
209         },
210 
211         /*
212          * Common SCIFB definitions.
213          */
214         [SCIx_SCIFB_REGTYPE] = {
215                 [SCSMR]         = { 0x00, 16 },
216                 [SCBRR]         = { 0x04,  8 },
217                 [SCSCR]         = { 0x08, 16 },
218                 [SCxTDR]        = { 0x40,  8 },
219                 [SCxSR]         = { 0x14, 16 },
220                 [SCxRDR]        = { 0x60,  8 },
221                 [SCFCR]         = { 0x18, 16 },
222                 [SCFDR]         = sci_reg_invalid,
223                 [SCTFDR]        = { 0x38, 16 },
224                 [SCRFDR]        = { 0x3c, 16 },
225                 [SCSPTR]        = sci_reg_invalid,
226                 [SCLSR]         = sci_reg_invalid,
227                 [HSSRR]         = sci_reg_invalid,
228                 [SCPCR]         = { 0x30, 16 },
229                 [SCPDR]         = { 0x34, 16 },
230         },
231 
232         /*
233          * Common SH-2(A) SCIF definitions for ports with FIFO data
234          * count registers.
235          */
236         [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
237                 [SCSMR]         = { 0x00, 16 },
238                 [SCBRR]         = { 0x04,  8 },
239                 [SCSCR]         = { 0x08, 16 },
240                 [SCxTDR]        = { 0x0c,  8 },
241                 [SCxSR]         = { 0x10, 16 },
242                 [SCxRDR]        = { 0x14,  8 },
243                 [SCFCR]         = { 0x18, 16 },
244                 [SCFDR]         = { 0x1c, 16 },
245                 [SCTFDR]        = sci_reg_invalid,
246                 [SCRFDR]        = sci_reg_invalid,
247                 [SCSPTR]        = { 0x20, 16 },
248                 [SCLSR]         = { 0x24, 16 },
249                 [HSSRR]         = sci_reg_invalid,
250                 [SCPCR]         = sci_reg_invalid,
251                 [SCPDR]         = sci_reg_invalid,
252         },
253 
254         /*
255          * Common SH-3 SCIF definitions.
256          */
257         [SCIx_SH3_SCIF_REGTYPE] = {
258                 [SCSMR]         = { 0x00,  8 },
259                 [SCBRR]         = { 0x02,  8 },
260                 [SCSCR]         = { 0x04,  8 },
261                 [SCxTDR]        = { 0x06,  8 },
262                 [SCxSR]         = { 0x08, 16 },
263                 [SCxRDR]        = { 0x0a,  8 },
264                 [SCFCR]         = { 0x0c,  8 },
265                 [SCFDR]         = { 0x0e, 16 },
266                 [SCTFDR]        = sci_reg_invalid,
267                 [SCRFDR]        = sci_reg_invalid,
268                 [SCSPTR]        = sci_reg_invalid,
269                 [SCLSR]         = sci_reg_invalid,
270                 [HSSRR]         = sci_reg_invalid,
271                 [SCPCR]         = sci_reg_invalid,
272                 [SCPDR]         = sci_reg_invalid,
273         },
274 
275         /*
276          * Common SH-4(A) SCIF(B) definitions.
277          */
278         [SCIx_SH4_SCIF_REGTYPE] = {
279                 [SCSMR]         = { 0x00, 16 },
280                 [SCBRR]         = { 0x04,  8 },
281                 [SCSCR]         = { 0x08, 16 },
282                 [SCxTDR]        = { 0x0c,  8 },
283                 [SCxSR]         = { 0x10, 16 },
284                 [SCxRDR]        = { 0x14,  8 },
285                 [SCFCR]         = { 0x18, 16 },
286                 [SCFDR]         = { 0x1c, 16 },
287                 [SCTFDR]        = sci_reg_invalid,
288                 [SCRFDR]        = sci_reg_invalid,
289                 [SCSPTR]        = { 0x20, 16 },
290                 [SCLSR]         = { 0x24, 16 },
291                 [HSSRR]         = sci_reg_invalid,
292                 [SCPCR]         = sci_reg_invalid,
293                 [SCPDR]         = sci_reg_invalid,
294         },
295 
296         /*
297          * Common HSCIF definitions.
298          */
299         [SCIx_HSCIF_REGTYPE] = {
300                 [SCSMR]         = { 0x00, 16 },
301                 [SCBRR]         = { 0x04,  8 },
302                 [SCSCR]         = { 0x08, 16 },
303                 [SCxTDR]        = { 0x0c,  8 },
304                 [SCxSR]         = { 0x10, 16 },
305                 [SCxRDR]        = { 0x14,  8 },
306                 [SCFCR]         = { 0x18, 16 },
307                 [SCFDR]         = { 0x1c, 16 },
308                 [SCTFDR]        = sci_reg_invalid,
309                 [SCRFDR]        = sci_reg_invalid,
310                 [SCSPTR]        = { 0x20, 16 },
311                 [SCLSR]         = { 0x24, 16 },
312                 [HSSRR]         = { 0x40, 16 },
313                 [SCPCR]         = sci_reg_invalid,
314                 [SCPDR]         = sci_reg_invalid,
315         },
316 
317         /*
318          * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
319          * register.
320          */
321         [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
322                 [SCSMR]         = { 0x00, 16 },
323                 [SCBRR]         = { 0x04,  8 },
324                 [SCSCR]         = { 0x08, 16 },
325                 [SCxTDR]        = { 0x0c,  8 },
326                 [SCxSR]         = { 0x10, 16 },
327                 [SCxRDR]        = { 0x14,  8 },
328                 [SCFCR]         = { 0x18, 16 },
329                 [SCFDR]         = { 0x1c, 16 },
330                 [SCTFDR]        = sci_reg_invalid,
331                 [SCRFDR]        = sci_reg_invalid,
332                 [SCSPTR]        = sci_reg_invalid,
333                 [SCLSR]         = { 0x24, 16 },
334                 [HSSRR]         = sci_reg_invalid,
335                 [SCPCR]         = sci_reg_invalid,
336                 [SCPDR]         = sci_reg_invalid,
337         },
338 
339         /*
340          * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
341          * count registers.
342          */
343         [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
344                 [SCSMR]         = { 0x00, 16 },
345                 [SCBRR]         = { 0x04,  8 },
346                 [SCSCR]         = { 0x08, 16 },
347                 [SCxTDR]        = { 0x0c,  8 },
348                 [SCxSR]         = { 0x10, 16 },
349                 [SCxRDR]        = { 0x14,  8 },
350                 [SCFCR]         = { 0x18, 16 },
351                 [SCFDR]         = { 0x1c, 16 },
352                 [SCTFDR]        = { 0x1c, 16 }, /* aliased to SCFDR */
353                 [SCRFDR]        = { 0x20, 16 },
354                 [SCSPTR]        = { 0x24, 16 },
355                 [SCLSR]         = { 0x28, 16 },
356                 [HSSRR]         = sci_reg_invalid,
357                 [SCPCR]         = sci_reg_invalid,
358                 [SCPDR]         = sci_reg_invalid,
359         },
360 
361         /*
362          * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
363          * registers.
364          */
365         [SCIx_SH7705_SCIF_REGTYPE] = {
366                 [SCSMR]         = { 0x00, 16 },
367                 [SCBRR]         = { 0x04,  8 },
368                 [SCSCR]         = { 0x08, 16 },
369                 [SCxTDR]        = { 0x20,  8 },
370                 [SCxSR]         = { 0x14, 16 },
371                 [SCxRDR]        = { 0x24,  8 },
372                 [SCFCR]         = { 0x18, 16 },
373                 [SCFDR]         = { 0x1c, 16 },
374                 [SCTFDR]        = sci_reg_invalid,
375                 [SCRFDR]        = sci_reg_invalid,
376                 [SCSPTR]        = sci_reg_invalid,
377                 [SCLSR]         = sci_reg_invalid,
378                 [HSSRR]         = sci_reg_invalid,
379                 [SCPCR]         = sci_reg_invalid,
380                 [SCPDR]         = sci_reg_invalid,
381         },
382 };
383 
384 #define sci_getreg(up, offset)          (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
385 
386 /*
387  * The "offset" here is rather misleading, in that it refers to an enum
388  * value relative to the port mapping rather than the fixed offset
389  * itself, which needs to be manually retrieved from the platform's
390  * register map for the given port.
391  */
392 static unsigned int sci_serial_in(struct uart_port *p, int offset)
393 {
394         const struct plat_sci_reg *reg = sci_getreg(p, offset);
395 
396         if (reg->size == 8)
397                 return ioread8(p->membase + (reg->offset << p->regshift));
398         else if (reg->size == 16)
399                 return ioread16(p->membase + (reg->offset << p->regshift));
400         else
401                 WARN(1, "Invalid register access\n");
402 
403         return 0;
404 }
405 
406 static void sci_serial_out(struct uart_port *p, int offset, int value)
407 {
408         const struct plat_sci_reg *reg = sci_getreg(p, offset);
409 
410         if (reg->size == 8)
411                 iowrite8(value, p->membase + (reg->offset << p->regshift));
412         else if (reg->size == 16)
413                 iowrite16(value, p->membase + (reg->offset << p->regshift));
414         else
415                 WARN(1, "Invalid register access\n");
416 }
417 
418 static int sci_probe_regmap(struct plat_sci_port *cfg)
419 {
420         switch (cfg->type) {
421         case PORT_SCI:
422                 cfg->regtype = SCIx_SCI_REGTYPE;
423                 break;
424         case PORT_IRDA:
425                 cfg->regtype = SCIx_IRDA_REGTYPE;
426                 break;
427         case PORT_SCIFA:
428                 cfg->regtype = SCIx_SCIFA_REGTYPE;
429                 break;
430         case PORT_SCIFB:
431                 cfg->regtype = SCIx_SCIFB_REGTYPE;
432                 break;
433         case PORT_SCIF:
434                 /*
435                  * The SH-4 is a bit of a misnomer here, although that's
436                  * where this particular port layout originated. This
437                  * configuration (or some slight variation thereof)
438                  * remains the dominant model for all SCIFs.
439                  */
440                 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
441                 break;
442         case PORT_HSCIF:
443                 cfg->regtype = SCIx_HSCIF_REGTYPE;
444                 break;
445         default:
446                 pr_err("Can't probe register map for given port\n");
447                 return -EINVAL;
448         }
449 
450         return 0;
451 }
452 
453 static void sci_port_enable(struct sci_port *sci_port)
454 {
455         if (!sci_port->port.dev)
456                 return;
457 
458         pm_runtime_get_sync(sci_port->port.dev);
459 
460         clk_prepare_enable(sci_port->iclk);
461         sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
462         clk_prepare_enable(sci_port->fclk);
463 }
464 
465 static void sci_port_disable(struct sci_port *sci_port)
466 {
467         if (!sci_port->port.dev)
468                 return;
469 
470         /* Cancel the break timer to ensure that the timer handler will not try
471          * to access the hardware with clocks and power disabled. Reset the
472          * break flag to make the break debouncing state machine ready for the
473          * next break.
474          */
475         del_timer_sync(&sci_port->break_timer);
476         sci_port->break_flag = 0;
477 
478         clk_disable_unprepare(sci_port->fclk);
479         clk_disable_unprepare(sci_port->iclk);
480 
481         pm_runtime_put_sync(sci_port->port.dev);
482 }
483 
484 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
485 {
486         /*
487          * Not all ports (such as SCIFA) will support REIE. Rather than
488          * special-casing the port type, we check the port initialization
489          * IRQ enable mask to see whether the IRQ is desired at all. If
490          * it's unset, it's logically inferred that there's no point in
491          * testing for it.
492          */
493         return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
494 }
495 
496 static void sci_start_tx(struct uart_port *port)
497 {
498         struct sci_port *s = to_sci_port(port);
499         unsigned short ctrl;
500 
501 #ifdef CONFIG_SERIAL_SH_SCI_DMA
502         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
503                 u16 new, scr = serial_port_in(port, SCSCR);
504                 if (s->chan_tx)
505                         new = scr | SCSCR_TDRQE;
506                 else
507                         new = scr & ~SCSCR_TDRQE;
508                 if (new != scr)
509                         serial_port_out(port, SCSCR, new);
510         }
511 
512         if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
513             dma_submit_error(s->cookie_tx)) {
514                 s->cookie_tx = 0;
515                 schedule_work(&s->work_tx);
516         }
517 #endif
518 
519         if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
520                 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
521                 ctrl = serial_port_in(port, SCSCR);
522                 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
523         }
524 }
525 
526 static void sci_stop_tx(struct uart_port *port)
527 {
528         unsigned short ctrl;
529 
530         /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
531         ctrl = serial_port_in(port, SCSCR);
532 
533         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
534                 ctrl &= ~SCSCR_TDRQE;
535 
536         ctrl &= ~SCSCR_TIE;
537 
538         serial_port_out(port, SCSCR, ctrl);
539 }
540 
541 static void sci_start_rx(struct uart_port *port)
542 {
543         unsigned short ctrl;
544 
545         ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
546 
547         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
548                 ctrl &= ~SCSCR_RDRQE;
549 
550         serial_port_out(port, SCSCR, ctrl);
551 }
552 
553 static void sci_stop_rx(struct uart_port *port)
554 {
555         unsigned short ctrl;
556 
557         ctrl = serial_port_in(port, SCSCR);
558 
559         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
560                 ctrl &= ~SCSCR_RDRQE;
561 
562         ctrl &= ~port_rx_irq_mask(port);
563 
564         serial_port_out(port, SCSCR, ctrl);
565 }
566 
567 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
568 {
569         if (port->type == PORT_SCI) {
570                 /* Just store the mask */
571                 serial_port_out(port, SCxSR, mask);
572         } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
573                 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
574                 /* Only clear the status bits we want to clear */
575                 serial_port_out(port, SCxSR,
576                                 serial_port_in(port, SCxSR) & mask);
577         } else {
578                 /* Store the mask, clear parity/framing errors */
579                 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
580         }
581 }
582 
583 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
584 
585 #ifdef CONFIG_CONSOLE_POLL
586 static int sci_poll_get_char(struct uart_port *port)
587 {
588         unsigned short status;
589         int c;
590 
591         do {
592                 status = serial_port_in(port, SCxSR);
593                 if (status & SCxSR_ERRORS(port)) {
594                         sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
595                         continue;
596                 }
597                 break;
598         } while (1);
599 
600         if (!(status & SCxSR_RDxF(port)))
601                 return NO_POLL_CHAR;
602 
603         c = serial_port_in(port, SCxRDR);
604 
605         /* Dummy read */
606         serial_port_in(port, SCxSR);
607         sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
608 
609         return c;
610 }
611 #endif
612 
613 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
614 {
615         unsigned short status;
616 
617         do {
618                 status = serial_port_in(port, SCxSR);
619         } while (!(status & SCxSR_TDxE(port)));
620 
621         serial_port_out(port, SCxTDR, c);
622         sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
623 }
624 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
625 
626 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
627 {
628         struct sci_port *s = to_sci_port(port);
629         const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
630 
631         /*
632          * Use port-specific handler if provided.
633          */
634         if (s->cfg->ops && s->cfg->ops->init_pins) {
635                 s->cfg->ops->init_pins(port, cflag);
636                 return;
637         }
638 
639         /*
640          * For the generic path SCSPTR is necessary. Bail out if that's
641          * unavailable, too.
642          */
643         if (!reg->size)
644                 return;
645 
646         if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
647             ((!(cflag & CRTSCTS)))) {
648                 unsigned short status;
649 
650                 status = serial_port_in(port, SCSPTR);
651                 status &= ~SCSPTR_CTSIO;
652                 status |= SCSPTR_RTSIO;
653                 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
654         }
655 }
656 
657 static int sci_txfill(struct uart_port *port)
658 {
659         const struct plat_sci_reg *reg;
660 
661         reg = sci_getreg(port, SCTFDR);
662         if (reg->size)
663                 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
664 
665         reg = sci_getreg(port, SCFDR);
666         if (reg->size)
667                 return serial_port_in(port, SCFDR) >> 8;
668 
669         return !(serial_port_in(port, SCxSR) & SCI_TDRE);
670 }
671 
672 static int sci_txroom(struct uart_port *port)
673 {
674         return port->fifosize - sci_txfill(port);
675 }
676 
677 static int sci_rxfill(struct uart_port *port)
678 {
679         const struct plat_sci_reg *reg;
680 
681         reg = sci_getreg(port, SCRFDR);
682         if (reg->size)
683                 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
684 
685         reg = sci_getreg(port, SCFDR);
686         if (reg->size)
687                 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
688 
689         return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
690 }
691 
692 /*
693  * SCI helper for checking the state of the muxed port/RXD pins.
694  */
695 static inline int sci_rxd_in(struct uart_port *port)
696 {
697         struct sci_port *s = to_sci_port(port);
698 
699         if (s->cfg->port_reg <= 0)
700                 return 1;
701 
702         /* Cast for ARM damage */
703         return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
704 }
705 
706 /* ********************************************************************** *
707  *                   the interrupt related routines                       *
708  * ********************************************************************** */
709 
710 static void sci_transmit_chars(struct uart_port *port)
711 {
712         struct circ_buf *xmit = &port->state->xmit;
713         unsigned int stopped = uart_tx_stopped(port);
714         unsigned short status;
715         unsigned short ctrl;
716         int count;
717 
718         status = serial_port_in(port, SCxSR);
719         if (!(status & SCxSR_TDxE(port))) {
720                 ctrl = serial_port_in(port, SCSCR);
721                 if (uart_circ_empty(xmit))
722                         ctrl &= ~SCSCR_TIE;
723                 else
724                         ctrl |= SCSCR_TIE;
725                 serial_port_out(port, SCSCR, ctrl);
726                 return;
727         }
728 
729         count = sci_txroom(port);
730 
731         do {
732                 unsigned char c;
733 
734                 if (port->x_char) {
735                         c = port->x_char;
736                         port->x_char = 0;
737                 } else if (!uart_circ_empty(xmit) && !stopped) {
738                         c = xmit->buf[xmit->tail];
739                         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
740                 } else {
741                         break;
742                 }
743 
744                 serial_port_out(port, SCxTDR, c);
745 
746                 port->icount.tx++;
747         } while (--count > 0);
748 
749         sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
750 
751         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
752                 uart_write_wakeup(port);
753         if (uart_circ_empty(xmit)) {
754                 sci_stop_tx(port);
755         } else {
756                 ctrl = serial_port_in(port, SCSCR);
757 
758                 if (port->type != PORT_SCI) {
759                         serial_port_in(port, SCxSR); /* Dummy read */
760                         sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
761                 }
762 
763                 ctrl |= SCSCR_TIE;
764                 serial_port_out(port, SCSCR, ctrl);
765         }
766 }
767 
768 /* On SH3, SCIF may read end-of-break as a space->mark char */
769 #define STEPFN(c)  ({int __c = (c); (((__c-1)|(__c)) == -1); })
770 
771 static void sci_receive_chars(struct uart_port *port)
772 {
773         struct sci_port *sci_port = to_sci_port(port);
774         struct tty_port *tport = &port->state->port;
775         int i, count, copied = 0;
776         unsigned short status;
777         unsigned char flag;
778 
779         status = serial_port_in(port, SCxSR);
780         if (!(status & SCxSR_RDxF(port)))
781                 return;
782 
783         while (1) {
784                 /* Don't copy more bytes than there is room for in the buffer */
785                 count = tty_buffer_request_room(tport, sci_rxfill(port));
786 
787                 /* If for any reason we can't copy more data, we're done! */
788                 if (count == 0)
789                         break;
790 
791                 if (port->type == PORT_SCI) {
792                         char c = serial_port_in(port, SCxRDR);
793                         if (uart_handle_sysrq_char(port, c) ||
794                             sci_port->break_flag)
795                                 count = 0;
796                         else
797                                 tty_insert_flip_char(tport, c, TTY_NORMAL);
798                 } else {
799                         for (i = 0; i < count; i++) {
800                                 char c = serial_port_in(port, SCxRDR);
801 
802                                 status = serial_port_in(port, SCxSR);
803 #if defined(CONFIG_CPU_SH3)
804                                 /* Skip "chars" during break */
805                                 if (sci_port->break_flag) {
806                                         if ((c == 0) &&
807                                             (status & SCxSR_FER(port))) {
808                                                 count--; i--;
809                                                 continue;
810                                         }
811 
812                                         /* Nonzero => end-of-break */
813                                         dev_dbg(port->dev, "debounce<%02x>\n", c);
814                                         sci_port->break_flag = 0;
815 
816                                         if (STEPFN(c)) {
817                                                 count--; i--;
818                                                 continue;
819                                         }
820                                 }
821 #endif /* CONFIG_CPU_SH3 */
822                                 if (uart_handle_sysrq_char(port, c)) {
823                                         count--; i--;
824                                         continue;
825                                 }
826 
827                                 /* Store data and status */
828                                 if (status & SCxSR_FER(port)) {
829                                         flag = TTY_FRAME;
830                                         port->icount.frame++;
831                                         dev_notice(port->dev, "frame error\n");
832                                 } else if (status & SCxSR_PER(port)) {
833                                         flag = TTY_PARITY;
834                                         port->icount.parity++;
835                                         dev_notice(port->dev, "parity error\n");
836                                 } else
837                                         flag = TTY_NORMAL;
838 
839                                 tty_insert_flip_char(tport, c, flag);
840                         }
841                 }
842 
843                 serial_port_in(port, SCxSR); /* dummy read */
844                 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
845 
846                 copied += count;
847                 port->icount.rx += count;
848         }
849 
850         if (copied) {
851                 /* Tell the rest of the system the news. New characters! */
852                 tty_flip_buffer_push(tport);
853         } else {
854                 serial_port_in(port, SCxSR); /* dummy read */
855                 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
856         }
857 }
858 
859 #define SCI_BREAK_JIFFIES (HZ/20)
860 
861 /*
862  * The sci generates interrupts during the break,
863  * 1 per millisecond or so during the break period, for 9600 baud.
864  * So dont bother disabling interrupts.
865  * But dont want more than 1 break event.
866  * Use a kernel timer to periodically poll the rx line until
867  * the break is finished.
868  */
869 static inline void sci_schedule_break_timer(struct sci_port *port)
870 {
871         mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
872 }
873 
874 /* Ensure that two consecutive samples find the break over. */
875 static void sci_break_timer(unsigned long data)
876 {
877         struct sci_port *port = (struct sci_port *)data;
878 
879         if (sci_rxd_in(&port->port) == 0) {
880                 port->break_flag = 1;
881                 sci_schedule_break_timer(port);
882         } else if (port->break_flag == 1) {
883                 /* break is over. */
884                 port->break_flag = 2;
885                 sci_schedule_break_timer(port);
886         } else
887                 port->break_flag = 0;
888 }
889 
890 static int sci_handle_errors(struct uart_port *port)
891 {
892         int copied = 0;
893         unsigned short status = serial_port_in(port, SCxSR);
894         struct tty_port *tport = &port->state->port;
895         struct sci_port *s = to_sci_port(port);
896 
897         /* Handle overruns */
898         if (status & s->overrun_mask) {
899                 port->icount.overrun++;
900 
901                 /* overrun error */
902                 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
903                         copied++;
904 
905                 dev_notice(port->dev, "overrun error\n");
906         }
907 
908         if (status & SCxSR_FER(port)) {
909                 if (sci_rxd_in(port) == 0) {
910                         /* Notify of BREAK */
911                         struct sci_port *sci_port = to_sci_port(port);
912 
913                         if (!sci_port->break_flag) {
914                                 port->icount.brk++;
915 
916                                 sci_port->break_flag = 1;
917                                 sci_schedule_break_timer(sci_port);
918 
919                                 /* Do sysrq handling. */
920                                 if (uart_handle_break(port))
921                                         return 0;
922 
923                                 dev_dbg(port->dev, "BREAK detected\n");
924 
925                                 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
926                                         copied++;
927                         }
928 
929                 } else {
930                         /* frame error */
931                         port->icount.frame++;
932 
933                         if (tty_insert_flip_char(tport, 0, TTY_FRAME))
934                                 copied++;
935 
936                         dev_notice(port->dev, "frame error\n");
937                 }
938         }
939 
940         if (status & SCxSR_PER(port)) {
941                 /* parity error */
942                 port->icount.parity++;
943 
944                 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
945                         copied++;
946 
947                 dev_notice(port->dev, "parity error\n");
948         }
949 
950         if (copied)
951                 tty_flip_buffer_push(tport);
952 
953         return copied;
954 }
955 
956 static int sci_handle_fifo_overrun(struct uart_port *port)
957 {
958         struct tty_port *tport = &port->state->port;
959         struct sci_port *s = to_sci_port(port);
960         const struct plat_sci_reg *reg;
961         int copied = 0;
962         u16 status;
963 
964         reg = sci_getreg(port, s->overrun_reg);
965         if (!reg->size)
966                 return 0;
967 
968         status = serial_port_in(port, s->overrun_reg);
969         if (status & s->overrun_mask) {
970                 status &= ~s->overrun_mask;
971                 serial_port_out(port, s->overrun_reg, status);
972 
973                 port->icount.overrun++;
974 
975                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
976                 tty_flip_buffer_push(tport);
977 
978                 dev_dbg(port->dev, "overrun error\n");
979                 copied++;
980         }
981 
982         return copied;
983 }
984 
985 static int sci_handle_breaks(struct uart_port *port)
986 {
987         int copied = 0;
988         unsigned short status = serial_port_in(port, SCxSR);
989         struct tty_port *tport = &port->state->port;
990         struct sci_port *s = to_sci_port(port);
991 
992         if (uart_handle_break(port))
993                 return 0;
994 
995         if (!s->break_flag && status & SCxSR_BRK(port)) {
996 #if defined(CONFIG_CPU_SH3)
997                 /* Debounce break */
998                 s->break_flag = 1;
999 #endif
1000 
1001                 port->icount.brk++;
1002 
1003                 /* Notify of BREAK */
1004                 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1005                         copied++;
1006 
1007                 dev_dbg(port->dev, "BREAK detected\n");
1008         }
1009 
1010         if (copied)
1011                 tty_flip_buffer_push(tport);
1012 
1013         copied += sci_handle_fifo_overrun(port);
1014 
1015         return copied;
1016 }
1017 
1018 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1019 static void sci_dma_tx_complete(void *arg)
1020 {
1021         struct sci_port *s = arg;
1022         struct uart_port *port = &s->port;
1023         struct circ_buf *xmit = &port->state->xmit;
1024         unsigned long flags;
1025 
1026         dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1027 
1028         spin_lock_irqsave(&port->lock, flags);
1029 
1030         xmit->tail += s->tx_dma_len;
1031         xmit->tail &= UART_XMIT_SIZE - 1;
1032 
1033         port->icount.tx += s->tx_dma_len;
1034 
1035         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1036                 uart_write_wakeup(port);
1037 
1038         if (!uart_circ_empty(xmit)) {
1039                 s->cookie_tx = 0;
1040                 schedule_work(&s->work_tx);
1041         } else {
1042                 s->cookie_tx = -EINVAL;
1043                 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1044                         u16 ctrl = serial_port_in(port, SCSCR);
1045                         serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1046                 }
1047         }
1048 
1049         spin_unlock_irqrestore(&port->lock, flags);
1050 }
1051 
1052 /* Locking: called with port lock held */
1053 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1054 {
1055         struct uart_port *port = &s->port;
1056         struct tty_port *tport = &port->state->port;
1057         int copied;
1058 
1059         copied = tty_insert_flip_string(tport, buf, count);
1060         if (copied < count) {
1061                 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1062                          count - copied);
1063                 port->icount.buf_overrun++;
1064         }
1065 
1066         port->icount.rx += copied;
1067 
1068         return copied;
1069 }
1070 
1071 static int sci_dma_rx_find_active(struct sci_port *s)
1072 {
1073         unsigned int i;
1074 
1075         for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1076                 if (s->active_rx == s->cookie_rx[i])
1077                         return i;
1078 
1079         dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1080                 s->active_rx);
1081         return -1;
1082 }
1083 
1084 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1085 {
1086         struct dma_chan *chan = s->chan_rx;
1087         struct uart_port *port = &s->port;
1088         unsigned long flags;
1089 
1090         spin_lock_irqsave(&port->lock, flags);
1091         s->chan_rx = NULL;
1092         s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1093         spin_unlock_irqrestore(&port->lock, flags);
1094         dmaengine_terminate_all(chan);
1095         dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1096                           sg_dma_address(&s->sg_rx[0]));
1097         dma_release_channel(chan);
1098         if (enable_pio)
1099                 sci_start_rx(port);
1100 }
1101 
1102 static void sci_dma_rx_complete(void *arg)
1103 {
1104         struct sci_port *s = arg;
1105         struct dma_chan *chan = s->chan_rx;
1106         struct uart_port *port = &s->port;
1107         struct dma_async_tx_descriptor *desc;
1108         unsigned long flags;
1109         int active, count = 0;
1110 
1111         dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1112                 s->active_rx);
1113 
1114         spin_lock_irqsave(&port->lock, flags);
1115 
1116         active = sci_dma_rx_find_active(s);
1117         if (active >= 0)
1118                 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1119 
1120         mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1121 
1122         if (count)
1123                 tty_flip_buffer_push(&port->state->port);
1124 
1125         desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1126                                        DMA_DEV_TO_MEM,
1127                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1128         if (!desc)
1129                 goto fail;
1130 
1131         desc->callback = sci_dma_rx_complete;
1132         desc->callback_param = s;
1133         s->cookie_rx[active] = dmaengine_submit(desc);
1134         if (dma_submit_error(s->cookie_rx[active]))
1135                 goto fail;
1136 
1137         s->active_rx = s->cookie_rx[!active];
1138 
1139         dma_async_issue_pending(chan);
1140 
1141         dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1142                 __func__, s->cookie_rx[active], active, s->active_rx);
1143         spin_unlock_irqrestore(&port->lock, flags);
1144         return;
1145 
1146 fail:
1147         spin_unlock_irqrestore(&port->lock, flags);
1148         dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1149         sci_rx_dma_release(s, true);
1150 }
1151 
1152 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1153 {
1154         struct dma_chan *chan = s->chan_tx;
1155         struct uart_port *port = &s->port;
1156         unsigned long flags;
1157 
1158         spin_lock_irqsave(&port->lock, flags);
1159         s->chan_tx = NULL;
1160         s->cookie_tx = -EINVAL;
1161         spin_unlock_irqrestore(&port->lock, flags);
1162         dmaengine_terminate_all(chan);
1163         dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1164                          DMA_TO_DEVICE);
1165         dma_release_channel(chan);
1166         if (enable_pio)
1167                 sci_start_tx(port);
1168 }
1169 
1170 static void sci_submit_rx(struct sci_port *s)
1171 {
1172         struct dma_chan *chan = s->chan_rx;
1173         int i;
1174 
1175         for (i = 0; i < 2; i++) {
1176                 struct scatterlist *sg = &s->sg_rx[i];
1177                 struct dma_async_tx_descriptor *desc;
1178 
1179                 desc = dmaengine_prep_slave_sg(chan,
1180                         sg, 1, DMA_DEV_TO_MEM,
1181                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1182                 if (!desc)
1183                         goto fail;
1184 
1185                 desc->callback = sci_dma_rx_complete;
1186                 desc->callback_param = s;
1187                 s->cookie_rx[i] = dmaengine_submit(desc);
1188                 if (dma_submit_error(s->cookie_rx[i]))
1189                         goto fail;
1190 
1191                 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1192                         s->cookie_rx[i], i);
1193         }
1194 
1195         s->active_rx = s->cookie_rx[0];
1196 
1197         dma_async_issue_pending(chan);
1198         return;
1199 
1200 fail:
1201         if (i)
1202                 dmaengine_terminate_all(chan);
1203         for (i = 0; i < 2; i++)
1204                 s->cookie_rx[i] = -EINVAL;
1205         s->active_rx = -EINVAL;
1206         dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1207         sci_rx_dma_release(s, true);
1208 }
1209 
1210 static void work_fn_tx(struct work_struct *work)
1211 {
1212         struct sci_port *s = container_of(work, struct sci_port, work_tx);
1213         struct dma_async_tx_descriptor *desc;
1214         struct dma_chan *chan = s->chan_tx;
1215         struct uart_port *port = &s->port;
1216         struct circ_buf *xmit = &port->state->xmit;
1217         dma_addr_t buf;
1218 
1219         /*
1220          * DMA is idle now.
1221          * Port xmit buffer is already mapped, and it is one page... Just adjust
1222          * offsets and lengths. Since it is a circular buffer, we have to
1223          * transmit till the end, and then the rest. Take the port lock to get a
1224          * consistent xmit buffer state.
1225          */
1226         spin_lock_irq(&port->lock);
1227         buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1228         s->tx_dma_len = min_t(unsigned int,
1229                 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1230                 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1231         spin_unlock_irq(&port->lock);
1232 
1233         desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1234                                            DMA_MEM_TO_DEV,
1235                                            DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1236         if (!desc) {
1237                 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1238                 /* switch to PIO */
1239                 sci_tx_dma_release(s, true);
1240                 return;
1241         }
1242 
1243         dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1244                                    DMA_TO_DEVICE);
1245 
1246         spin_lock_irq(&port->lock);
1247         desc->callback = sci_dma_tx_complete;
1248         desc->callback_param = s;
1249         spin_unlock_irq(&port->lock);
1250         s->cookie_tx = dmaengine_submit(desc);
1251         if (dma_submit_error(s->cookie_tx)) {
1252                 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1253                 /* switch to PIO */
1254                 sci_tx_dma_release(s, true);
1255                 return;
1256         }
1257 
1258         dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1259                 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1260 
1261         dma_async_issue_pending(chan);
1262 }
1263 
1264 static void rx_timer_fn(unsigned long arg)
1265 {
1266         struct sci_port *s = (struct sci_port *)arg;
1267         struct dma_chan *chan = s->chan_rx;
1268         struct uart_port *port = &s->port;
1269         struct dma_tx_state state;
1270         enum dma_status status;
1271         unsigned long flags;
1272         unsigned int read;
1273         int active, count;
1274         u16 scr;
1275 
1276         spin_lock_irqsave(&port->lock, flags);
1277 
1278         dev_dbg(port->dev, "DMA Rx timed out\n");
1279 
1280         active = sci_dma_rx_find_active(s);
1281         if (active < 0) {
1282                 spin_unlock_irqrestore(&port->lock, flags);
1283                 return;
1284         }
1285 
1286         status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1287         if (status == DMA_COMPLETE) {
1288                 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1289                         s->active_rx, active);
1290                 spin_unlock_irqrestore(&port->lock, flags);
1291 
1292                 /* Let packet complete handler take care of the packet */
1293                 return;
1294         }
1295 
1296         dmaengine_pause(chan);
1297 
1298         /*
1299          * sometimes DMA transfer doesn't stop even if it is stopped and
1300          * data keeps on coming until transaction is complete so check
1301          * for DMA_COMPLETE again
1302          * Let packet complete handler take care of the packet
1303          */
1304         status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1305         if (status == DMA_COMPLETE) {
1306                 spin_unlock_irqrestore(&port->lock, flags);
1307                 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1308                 return;
1309         }
1310 
1311         /* Handle incomplete DMA receive */
1312         dmaengine_terminate_all(s->chan_rx);
1313         read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1314         dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1315                 s->active_rx);
1316 
1317         if (read) {
1318                 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1319                 if (count)
1320                         tty_flip_buffer_push(&port->state->port);
1321         }
1322 
1323         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1324                 sci_submit_rx(s);
1325 
1326         /* Direct new serial port interrupts back to CPU */
1327         scr = serial_port_in(port, SCSCR);
1328         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1329                 scr &= ~SCSCR_RDRQE;
1330                 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1331         }
1332         serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1333 
1334         spin_unlock_irqrestore(&port->lock, flags);
1335 }
1336 
1337 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1338                                              enum dma_transfer_direction dir,
1339                                              unsigned int id)
1340 {
1341         dma_cap_mask_t mask;
1342         struct dma_chan *chan;
1343         struct dma_slave_config cfg;
1344         int ret;
1345 
1346         dma_cap_zero(mask);
1347         dma_cap_set(DMA_SLAVE, mask);
1348 
1349         chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1350                                         (void *)(unsigned long)id, port->dev,
1351                                         dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1352         if (!chan) {
1353                 dev_warn(port->dev,
1354                          "dma_request_slave_channel_compat failed\n");
1355                 return NULL;
1356         }
1357 
1358         memset(&cfg, 0, sizeof(cfg));
1359         cfg.direction = dir;
1360         if (dir == DMA_MEM_TO_DEV) {
1361                 cfg.dst_addr = port->mapbase +
1362                         (sci_getreg(port, SCxTDR)->offset << port->regshift);
1363                 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1364         } else {
1365                 cfg.src_addr = port->mapbase +
1366                         (sci_getreg(port, SCxRDR)->offset << port->regshift);
1367                 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1368         }
1369 
1370         ret = dmaengine_slave_config(chan, &cfg);
1371         if (ret) {
1372                 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1373                 dma_release_channel(chan);
1374                 return NULL;
1375         }
1376 
1377         return chan;
1378 }
1379 
1380 static void sci_request_dma(struct uart_port *port)
1381 {
1382         struct sci_port *s = to_sci_port(port);
1383         struct dma_chan *chan;
1384 
1385         dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1386 
1387         if (!port->dev->of_node &&
1388             (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1389                 return;
1390 
1391         s->cookie_tx = -EINVAL;
1392         chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1393         dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1394         if (chan) {
1395                 s->chan_tx = chan;
1396                 /* UART circular tx buffer is an aligned page. */
1397                 s->tx_dma_addr = dma_map_single(chan->device->dev,
1398                                                 port->state->xmit.buf,
1399                                                 UART_XMIT_SIZE,
1400                                                 DMA_TO_DEVICE);
1401                 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1402                         dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1403                         dma_release_channel(chan);
1404                         s->chan_tx = NULL;
1405                 } else {
1406                         dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1407                                 __func__, UART_XMIT_SIZE,
1408                                 port->state->xmit.buf, &s->tx_dma_addr);
1409                 }
1410 
1411                 INIT_WORK(&s->work_tx, work_fn_tx);
1412         }
1413 
1414         chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1415         dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1416         if (chan) {
1417                 unsigned int i;
1418                 dma_addr_t dma;
1419                 void *buf;
1420 
1421                 s->chan_rx = chan;
1422 
1423                 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1424                 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1425                                          &dma, GFP_KERNEL);
1426                 if (!buf) {
1427                         dev_warn(port->dev,
1428                                  "Failed to allocate Rx dma buffer, using PIO\n");
1429                         dma_release_channel(chan);
1430                         s->chan_rx = NULL;
1431                         return;
1432                 }
1433 
1434                 for (i = 0; i < 2; i++) {
1435                         struct scatterlist *sg = &s->sg_rx[i];
1436 
1437                         sg_init_table(sg, 1);
1438                         s->rx_buf[i] = buf;
1439                         sg_dma_address(sg) = dma;
1440                         sg_dma_len(sg) = s->buf_len_rx;
1441 
1442                         buf += s->buf_len_rx;
1443                         dma += s->buf_len_rx;
1444                 }
1445 
1446                 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1447 
1448                 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1449                         sci_submit_rx(s);
1450         }
1451 }
1452 
1453 static void sci_free_dma(struct uart_port *port)
1454 {
1455         struct sci_port *s = to_sci_port(port);
1456 
1457         if (s->chan_tx)
1458                 sci_tx_dma_release(s, false);
1459         if (s->chan_rx)
1460                 sci_rx_dma_release(s, false);
1461 }
1462 #else
1463 static inline void sci_request_dma(struct uart_port *port)
1464 {
1465 }
1466 
1467 static inline void sci_free_dma(struct uart_port *port)
1468 {
1469 }
1470 #endif
1471 
1472 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1473 {
1474 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1475         struct uart_port *port = ptr;
1476         struct sci_port *s = to_sci_port(port);
1477 
1478         if (s->chan_rx) {
1479                 u16 scr = serial_port_in(port, SCSCR);
1480                 u16 ssr = serial_port_in(port, SCxSR);
1481 
1482                 /* Disable future Rx interrupts */
1483                 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1484                         disable_irq_nosync(irq);
1485                         scr |= SCSCR_RDRQE;
1486                 } else {
1487                         scr &= ~SCSCR_RIE;
1488                         sci_submit_rx(s);
1489                 }
1490                 serial_port_out(port, SCSCR, scr);
1491                 /* Clear current interrupt */
1492                 serial_port_out(port, SCxSR,
1493                                 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1494                 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1495                         jiffies, s->rx_timeout);
1496                 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1497 
1498                 return IRQ_HANDLED;
1499         }
1500 #endif
1501 
1502         /* I think sci_receive_chars has to be called irrespective
1503          * of whether the I_IXOFF is set, otherwise, how is the interrupt
1504          * to be disabled?
1505          */
1506         sci_receive_chars(ptr);
1507 
1508         return IRQ_HANDLED;
1509 }
1510 
1511 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1512 {
1513         struct uart_port *port = ptr;
1514         unsigned long flags;
1515 
1516         spin_lock_irqsave(&port->lock, flags);
1517         sci_transmit_chars(port);
1518         spin_unlock_irqrestore(&port->lock, flags);
1519 
1520         return IRQ_HANDLED;
1521 }
1522 
1523 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1524 {
1525         struct uart_port *port = ptr;
1526         struct sci_port *s = to_sci_port(port);
1527 
1528         /* Handle errors */
1529         if (port->type == PORT_SCI) {
1530                 if (sci_handle_errors(port)) {
1531                         /* discard character in rx buffer */
1532                         serial_port_in(port, SCxSR);
1533                         sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1534                 }
1535         } else {
1536                 sci_handle_fifo_overrun(port);
1537                 if (!s->chan_rx)
1538                         sci_receive_chars(ptr);
1539         }
1540 
1541         sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1542 
1543         /* Kick the transmission */
1544         if (!s->chan_tx)
1545                 sci_tx_interrupt(irq, ptr);
1546 
1547         return IRQ_HANDLED;
1548 }
1549 
1550 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1551 {
1552         struct uart_port *port = ptr;
1553 
1554         /* Handle BREAKs */
1555         sci_handle_breaks(port);
1556         sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1557 
1558         return IRQ_HANDLED;
1559 }
1560 
1561 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1562 {
1563         unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1564         struct uart_port *port = ptr;
1565         struct sci_port *s = to_sci_port(port);
1566         irqreturn_t ret = IRQ_NONE;
1567 
1568         ssr_status = serial_port_in(port, SCxSR);
1569         scr_status = serial_port_in(port, SCSCR);
1570         if (s->overrun_reg == SCxSR)
1571                 orer_status = ssr_status;
1572         else {
1573                 if (sci_getreg(port, s->overrun_reg)->size)
1574                         orer_status = serial_port_in(port, s->overrun_reg);
1575         }
1576 
1577         err_enabled = scr_status & port_rx_irq_mask(port);
1578 
1579         /* Tx Interrupt */
1580         if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1581             !s->chan_tx)
1582                 ret = sci_tx_interrupt(irq, ptr);
1583 
1584         /*
1585          * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1586          * DR flags
1587          */
1588         if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1589             (scr_status & SCSCR_RIE))
1590                 ret = sci_rx_interrupt(irq, ptr);
1591 
1592         /* Error Interrupt */
1593         if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1594                 ret = sci_er_interrupt(irq, ptr);
1595 
1596         /* Break Interrupt */
1597         if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1598                 ret = sci_br_interrupt(irq, ptr);
1599 
1600         /* Overrun Interrupt */
1601         if (orer_status & s->overrun_mask) {
1602                 sci_handle_fifo_overrun(port);
1603                 ret = IRQ_HANDLED;
1604         }
1605 
1606         return ret;
1607 }
1608 
1609 /*
1610  * Here we define a transition notifier so that we can update all of our
1611  * ports' baud rate when the peripheral clock changes.
1612  */
1613 static int sci_notifier(struct notifier_block *self,
1614                         unsigned long phase, void *p)
1615 {
1616         struct sci_port *sci_port;
1617         unsigned long flags;
1618 
1619         sci_port = container_of(self, struct sci_port, freq_transition);
1620 
1621         if (phase == CPUFREQ_POSTCHANGE) {
1622                 struct uart_port *port = &sci_port->port;
1623 
1624                 spin_lock_irqsave(&port->lock, flags);
1625                 port->uartclk = clk_get_rate(sci_port->iclk);
1626                 spin_unlock_irqrestore(&port->lock, flags);
1627         }
1628 
1629         return NOTIFY_OK;
1630 }
1631 
1632 static const struct sci_irq_desc {
1633         const char      *desc;
1634         irq_handler_t   handler;
1635 } sci_irq_desc[] = {
1636         /*
1637          * Split out handlers, the default case.
1638          */
1639         [SCIx_ERI_IRQ] = {
1640                 .desc = "rx err",
1641                 .handler = sci_er_interrupt,
1642         },
1643 
1644         [SCIx_RXI_IRQ] = {
1645                 .desc = "rx full",
1646                 .handler = sci_rx_interrupt,
1647         },
1648 
1649         [SCIx_TXI_IRQ] = {
1650                 .desc = "tx empty",
1651                 .handler = sci_tx_interrupt,
1652         },
1653 
1654         [SCIx_BRI_IRQ] = {
1655                 .desc = "break",
1656                 .handler = sci_br_interrupt,
1657         },
1658 
1659         /*
1660          * Special muxed handler.
1661          */
1662         [SCIx_MUX_IRQ] = {
1663                 .desc = "mux",
1664                 .handler = sci_mpxed_interrupt,
1665         },
1666 };
1667 
1668 static int sci_request_irq(struct sci_port *port)
1669 {
1670         struct uart_port *up = &port->port;
1671         int i, j, ret = 0;
1672 
1673         for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1674                 const struct sci_irq_desc *desc;
1675                 int irq;
1676 
1677                 if (SCIx_IRQ_IS_MUXED(port)) {
1678                         i = SCIx_MUX_IRQ;
1679                         irq = up->irq;
1680                 } else {
1681                         irq = port->irqs[i];
1682 
1683                         /*
1684                          * Certain port types won't support all of the
1685                          * available interrupt sources.
1686                          */
1687                         if (unlikely(irq < 0))
1688                                 continue;
1689                 }
1690 
1691                 desc = sci_irq_desc + i;
1692                 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1693                                             dev_name(up->dev), desc->desc);
1694                 if (!port->irqstr[j])
1695                         goto out_nomem;
1696 
1697                 ret = request_irq(irq, desc->handler, up->irqflags,
1698                                   port->irqstr[j], port);
1699                 if (unlikely(ret)) {
1700                         dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1701                         goto out_noirq;
1702                 }
1703         }
1704 
1705         return 0;
1706 
1707 out_noirq:
1708         while (--i >= 0)
1709                 free_irq(port->irqs[i], port);
1710 
1711 out_nomem:
1712         while (--j >= 0)
1713                 kfree(port->irqstr[j]);
1714 
1715         return ret;
1716 }
1717 
1718 static void sci_free_irq(struct sci_port *port)
1719 {
1720         int i;
1721 
1722         /*
1723          * Intentionally in reverse order so we iterate over the muxed
1724          * IRQ first.
1725          */
1726         for (i = 0; i < SCIx_NR_IRQS; i++) {
1727                 int irq = port->irqs[i];
1728 
1729                 /*
1730                  * Certain port types won't support all of the available
1731                  * interrupt sources.
1732                  */
1733                 if (unlikely(irq < 0))
1734                         continue;
1735 
1736                 free_irq(port->irqs[i], port);
1737                 kfree(port->irqstr[i]);
1738 
1739                 if (SCIx_IRQ_IS_MUXED(port)) {
1740                         /* If there's only one IRQ, we're done. */
1741                         return;
1742                 }
1743         }
1744 }
1745 
1746 static unsigned int sci_tx_empty(struct uart_port *port)
1747 {
1748         unsigned short status = serial_port_in(port, SCxSR);
1749         unsigned short in_tx_fifo = sci_txfill(port);
1750 
1751         return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1752 }
1753 
1754 /*
1755  * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1756  * CTS/RTS is supported in hardware by at least one port and controlled
1757  * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1758  * handled via the ->init_pins() op, which is a bit of a one-way street,
1759  * lacking any ability to defer pin control -- this will later be
1760  * converted over to the GPIO framework).
1761  *
1762  * Other modes (such as loopback) are supported generically on certain
1763  * port types, but not others. For these it's sufficient to test for the
1764  * existence of the support register and simply ignore the port type.
1765  */
1766 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1767 {
1768         if (mctrl & TIOCM_LOOP) {
1769                 const struct plat_sci_reg *reg;
1770 
1771                 /*
1772                  * Standard loopback mode for SCFCR ports.
1773                  */
1774                 reg = sci_getreg(port, SCFCR);
1775                 if (reg->size)
1776                         serial_port_out(port, SCFCR,
1777                                         serial_port_in(port, SCFCR) |
1778                                         SCFCR_LOOP);
1779         }
1780 }
1781 
1782 static unsigned int sci_get_mctrl(struct uart_port *port)
1783 {
1784         /*
1785          * CTS/RTS is handled in hardware when supported, while nothing
1786          * else is wired up. Keep it simple and simply assert DSR/CAR.
1787          */
1788         return TIOCM_DSR | TIOCM_CAR;
1789 }
1790 
1791 static void sci_break_ctl(struct uart_port *port, int break_state)
1792 {
1793         struct sci_port *s = to_sci_port(port);
1794         const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1795         unsigned short scscr, scsptr;
1796 
1797         /* check wheter the port has SCSPTR */
1798         if (!reg->size) {
1799                 /*
1800                  * Not supported by hardware. Most parts couple break and rx
1801                  * interrupts together, with break detection always enabled.
1802                  */
1803                 return;
1804         }
1805 
1806         scsptr = serial_port_in(port, SCSPTR);
1807         scscr = serial_port_in(port, SCSCR);
1808 
1809         if (break_state == -1) {
1810                 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1811                 scscr &= ~SCSCR_TE;
1812         } else {
1813                 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1814                 scscr |= SCSCR_TE;
1815         }
1816 
1817         serial_port_out(port, SCSPTR, scsptr);
1818         serial_port_out(port, SCSCR, scscr);
1819 }
1820 
1821 static int sci_startup(struct uart_port *port)
1822 {
1823         struct sci_port *s = to_sci_port(port);
1824         unsigned long flags;
1825         int ret;
1826 
1827         dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1828 
1829         ret = sci_request_irq(s);
1830         if (unlikely(ret < 0))
1831                 return ret;
1832 
1833         sci_request_dma(port);
1834 
1835         spin_lock_irqsave(&port->lock, flags);
1836         sci_start_tx(port);
1837         sci_start_rx(port);
1838         spin_unlock_irqrestore(&port->lock, flags);
1839 
1840         return 0;
1841 }
1842 
1843 static void sci_shutdown(struct uart_port *port)
1844 {
1845         struct sci_port *s = to_sci_port(port);
1846         unsigned long flags;
1847 
1848         dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1849 
1850         spin_lock_irqsave(&port->lock, flags);
1851         sci_stop_rx(port);
1852         sci_stop_tx(port);
1853         spin_unlock_irqrestore(&port->lock, flags);
1854 
1855 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1856         if (s->chan_rx) {
1857                 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1858                         port->line);
1859                 del_timer_sync(&s->rx_timer);
1860         }
1861 #endif
1862 
1863         sci_free_dma(port);
1864         sci_free_irq(s);
1865 }
1866 
1867 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1868                                    unsigned long freq)
1869 {
1870         if (s->sampling_rate)
1871                 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1872 
1873         /* Warn, but use a safe default */
1874         WARN_ON(1);
1875 
1876         return ((freq + 16 * bps) / (32 * bps) - 1);
1877 }
1878 
1879 /* calculate frame length from SMR */
1880 static int sci_baud_calc_frame_len(unsigned int smr_val)
1881 {
1882         int len = 10;
1883 
1884         if (smr_val & SCSMR_CHR)
1885                 len--;
1886         if (smr_val & SCSMR_PE)
1887                 len++;
1888         if (smr_val & SCSMR_STOP)
1889                 len++;
1890 
1891         return len;
1892 }
1893 
1894 
1895 /* calculate sample rate, BRR, and clock select for HSCIF */
1896 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1897                                 int *brr, unsigned int *srr,
1898                                 unsigned int *cks, int frame_len)
1899 {
1900         int sr, c, br, err, recv_margin;
1901         int min_err = 1000; /* 100% */
1902         int recv_max_margin = 0;
1903 
1904         /* Find the combination of sample rate and clock select with the
1905            smallest deviation from the desired baud rate. */
1906         for (sr = 8; sr <= 32; sr++) {
1907                 for (c = 0; c <= 3; c++) {
1908                         /* integerized formulas from HSCIF documentation */
1909                         br = DIV_ROUND_CLOSEST(freq, (sr *
1910                                               (1 << (2 * c + 1)) * bps)) - 1;
1911                         br = clamp(br, 0, 255);
1912                         err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1913                                                (1 << (2 * c + 1)) / 1000)) -
1914                                                1000;
1915                         /* Calc recv margin
1916                          * M: Receive margin (%)
1917                          * N: Ratio of bit rate to clock (N = sampling rate)
1918                          * D: Clock duty (D = 0 to 1.0)
1919                          * L: Frame length (L = 9 to 12)
1920                          * F: Absolute value of clock frequency deviation
1921                          *
1922                          *  M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1923                          *      (|D - 0.5| / N * (1 + F))|
1924                          *  NOTE: Usually, treat D for 0.5, F is 0 by this
1925                          *        calculation.
1926                          */
1927                         recv_margin = abs((500 -
1928                                         DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1929                         if (abs(min_err) > abs(err)) {
1930                                 min_err = err;
1931                                 recv_max_margin = recv_margin;
1932                         } else if ((min_err == err) &&
1933                                    (recv_margin > recv_max_margin))
1934                                 recv_max_margin = recv_margin;
1935                         else
1936                                 continue;
1937 
1938                         *brr = br;
1939                         *srr = sr - 1;
1940                         *cks = c;
1941                 }
1942         }
1943 
1944         if (min_err == 1000) {
1945                 WARN_ON(1);
1946                 /* use defaults */
1947                 *brr = 255;
1948                 *srr = 15;
1949                 *cks = 0;
1950         }
1951 }
1952 
1953 static void sci_reset(struct uart_port *port)
1954 {
1955         const struct plat_sci_reg *reg;
1956         unsigned int status;
1957 
1958         do {
1959                 status = serial_port_in(port, SCxSR);
1960         } while (!(status & SCxSR_TEND(port)));
1961 
1962         serial_port_out(port, SCSCR, 0x00);     /* TE=0, RE=0, CKE1=0 */
1963 
1964         reg = sci_getreg(port, SCFCR);
1965         if (reg->size)
1966                 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1967 }
1968 
1969 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1970                             struct ktermios *old)
1971 {
1972         struct sci_port *s = to_sci_port(port);
1973         const struct plat_sci_reg *reg;
1974         unsigned int baud, smr_val = 0, max_baud, cks = 0;
1975         int t = -1;
1976         unsigned int srr = 15;
1977 
1978         if ((termios->c_cflag & CSIZE) == CS7)
1979                 smr_val |= SCSMR_CHR;
1980         if (termios->c_cflag & PARENB)
1981                 smr_val |= SCSMR_PE;
1982         if (termios->c_cflag & PARODD)
1983                 smr_val |= SCSMR_PE | SCSMR_ODD;
1984         if (termios->c_cflag & CSTOPB)
1985                 smr_val |= SCSMR_STOP;
1986 
1987         /*
1988          * earlyprintk comes here early on with port->uartclk set to zero.
1989          * the clock framework is not up and running at this point so here
1990          * we assume that 115200 is the maximum baud rate. please note that
1991          * the baud rate is not programmed during earlyprintk - it is assumed
1992          * that the previous boot loader has enabled required clocks and
1993          * setup the baud rate generator hardware for us already.
1994          */
1995         max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1996 
1997         baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1998         if (likely(baud && port->uartclk)) {
1999                 if (s->cfg->type == PORT_HSCIF) {
2000                         int frame_len = sci_baud_calc_frame_len(smr_val);
2001                         sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
2002                                             &cks, frame_len);
2003                 } else {
2004                         t = sci_scbrr_calc(s, baud, port->uartclk);
2005                         for (cks = 0; t >= 256 && cks <= 3; cks++)
2006                                 t >>= 2;
2007                 }
2008         }
2009 
2010         sci_port_enable(s);
2011 
2012         sci_reset(port);
2013 
2014         smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
2015 
2016         uart_update_timeout(port, termios->c_cflag, baud);
2017 
2018         dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
2019                 __func__, smr_val, cks, t, s->cfg->scscr);
2020 
2021         if (t >= 0) {
2022                 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
2023                 serial_port_out(port, SCBRR, t);
2024                 reg = sci_getreg(port, HSSRR);
2025                 if (reg->size)
2026                         serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2027                 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
2028         } else
2029                 serial_port_out(port, SCSMR, smr_val);
2030 
2031         sci_init_pins(port, termios->c_cflag);
2032 
2033         reg = sci_getreg(port, SCFCR);
2034         if (reg->size) {
2035                 unsigned short ctrl = serial_port_in(port, SCFCR);
2036 
2037                 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
2038                         if (termios->c_cflag & CRTSCTS)
2039                                 ctrl |= SCFCR_MCE;
2040                         else
2041                                 ctrl &= ~SCFCR_MCE;
2042                 }
2043 
2044                 /*
2045                  * As we've done a sci_reset() above, ensure we don't
2046                  * interfere with the FIFOs while toggling MCE. As the
2047                  * reset values could still be set, simply mask them out.
2048                  */
2049                 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2050 
2051                 serial_port_out(port, SCFCR, ctrl);
2052         }
2053 
2054         serial_port_out(port, SCSCR, s->cfg->scscr);
2055 
2056 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2057         /*
2058          * Calculate delay for 2 DMA buffers (4 FIFO).
2059          * See serial_core.c::uart_update_timeout().
2060          * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2061          * function calculates 1 jiffie for the data plus 5 jiffies for the
2062          * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2063          * buffers (4 FIFO sizes), but when performing a faster transfer, the
2064          * value obtained by this formula is too small. Therefore, if the value
2065          * is smaller than 20ms, use 20ms as the timeout value for DMA.
2066          */
2067         if (s->chan_rx) {
2068                 unsigned int bits;
2069 
2070                 /* byte size and parity */
2071                 switch (termios->c_cflag & CSIZE) {
2072                 case CS5:
2073                         bits = 7;
2074                         break;
2075                 case CS6:
2076                         bits = 8;
2077                         break;
2078                 case CS7:
2079                         bits = 9;
2080                         break;
2081                 default:
2082                         bits = 10;
2083                         break;
2084                 }
2085 
2086                 if (termios->c_cflag & CSTOPB)
2087                         bits++;
2088                 if (termios->c_cflag & PARENB)
2089                         bits++;
2090                 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2091                                              (baud / 10), 10);
2092                 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2093                         s->rx_timeout * 1000 / HZ, port->timeout);
2094                 if (s->rx_timeout < msecs_to_jiffies(20))
2095                         s->rx_timeout = msecs_to_jiffies(20);
2096         }
2097 #endif
2098 
2099         if ((termios->c_cflag & CREAD) != 0)
2100                 sci_start_rx(port);
2101 
2102         sci_port_disable(s);
2103 }
2104 
2105 static void sci_pm(struct uart_port *port, unsigned int state,
2106                    unsigned int oldstate)
2107 {
2108         struct sci_port *sci_port = to_sci_port(port);
2109 
2110         switch (state) {
2111         case UART_PM_STATE_OFF:
2112                 sci_port_disable(sci_port);
2113                 break;
2114         default:
2115                 sci_port_enable(sci_port);
2116                 break;
2117         }
2118 }
2119 
2120 static const char *sci_type(struct uart_port *port)
2121 {
2122         switch (port->type) {
2123         case PORT_IRDA:
2124                 return "irda";
2125         case PORT_SCI:
2126                 return "sci";
2127         case PORT_SCIF:
2128                 return "scif";
2129         case PORT_SCIFA:
2130                 return "scifa";
2131         case PORT_SCIFB:
2132                 return "scifb";
2133         case PORT_HSCIF:
2134                 return "hscif";
2135         }
2136 
2137         return NULL;
2138 }
2139 
2140 static int sci_remap_port(struct uart_port *port)
2141 {
2142         struct sci_port *sport = to_sci_port(port);
2143 
2144         /*
2145          * Nothing to do if there's already an established membase.
2146          */
2147         if (port->membase)
2148                 return 0;
2149 
2150         if (port->flags & UPF_IOREMAP) {
2151                 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2152                 if (unlikely(!port->membase)) {
2153                         dev_err(port->dev, "can't remap port#%d\n", port->line);
2154                         return -ENXIO;
2155                 }
2156         } else {
2157                 /*
2158                  * For the simple (and majority of) cases where we don't
2159                  * need to do any remapping, just cast the cookie
2160                  * directly.
2161                  */
2162                 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2163         }
2164 
2165         return 0;
2166 }
2167 
2168 static void sci_release_port(struct uart_port *port)
2169 {
2170         struct sci_port *sport = to_sci_port(port);
2171 
2172         if (port->flags & UPF_IOREMAP) {
2173                 iounmap(port->membase);
2174                 port->membase = NULL;
2175         }
2176 
2177         release_mem_region(port->mapbase, sport->reg_size);
2178 }
2179 
2180 static int sci_request_port(struct uart_port *port)
2181 {
2182         struct resource *res;
2183         struct sci_port *sport = to_sci_port(port);
2184         int ret;
2185 
2186         res = request_mem_region(port->mapbase, sport->reg_size,
2187                                  dev_name(port->dev));
2188         if (unlikely(res == NULL)) {
2189                 dev_err(port->dev, "request_mem_region failed.");
2190                 return -EBUSY;
2191         }
2192 
2193         ret = sci_remap_port(port);
2194         if (unlikely(ret != 0)) {
2195                 release_resource(res);
2196                 return ret;
2197         }
2198 
2199         return 0;
2200 }
2201 
2202 static void sci_config_port(struct uart_port *port, int flags)
2203 {
2204         if (flags & UART_CONFIG_TYPE) {
2205                 struct sci_port *sport = to_sci_port(port);
2206 
2207                 port->type = sport->cfg->type;
2208                 sci_request_port(port);
2209         }
2210 }
2211 
2212 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2213 {
2214         if (ser->baud_base < 2400)
2215                 /* No paper tape reader for Mitch.. */
2216                 return -EINVAL;
2217 
2218         return 0;
2219 }
2220 
2221 static struct uart_ops sci_uart_ops = {
2222         .tx_empty       = sci_tx_empty,
2223         .set_mctrl      = sci_set_mctrl,
2224         .get_mctrl      = sci_get_mctrl,
2225         .start_tx       = sci_start_tx,
2226         .stop_tx        = sci_stop_tx,
2227         .stop_rx        = sci_stop_rx,
2228         .break_ctl      = sci_break_ctl,
2229         .startup        = sci_startup,
2230         .shutdown       = sci_shutdown,
2231         .set_termios    = sci_set_termios,
2232         .pm             = sci_pm,
2233         .type           = sci_type,
2234         .release_port   = sci_release_port,
2235         .request_port   = sci_request_port,
2236         .config_port    = sci_config_port,
2237         .verify_port    = sci_verify_port,
2238 #ifdef CONFIG_CONSOLE_POLL
2239         .poll_get_char  = sci_poll_get_char,
2240         .poll_put_char  = sci_poll_put_char,
2241 #endif
2242 };
2243 
2244 static int sci_init_single(struct platform_device *dev,
2245                            struct sci_port *sci_port, unsigned int index,
2246                            struct plat_sci_port *p, bool early)
2247 {
2248         struct uart_port *port = &sci_port->port;
2249         const struct resource *res;
2250         unsigned int i;
2251         int ret;
2252 
2253         sci_port->cfg   = p;
2254 
2255         port->ops       = &sci_uart_ops;
2256         port->iotype    = UPIO_MEM;
2257         port->line      = index;
2258 
2259         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2260         if (res == NULL)
2261                 return -ENOMEM;
2262 
2263         port->mapbase = res->start;
2264         sci_port->reg_size = resource_size(res);
2265 
2266         for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2267                 sci_port->irqs[i] = platform_get_irq(dev, i);
2268 
2269         /* The SCI generates several interrupts. They can be muxed together or
2270          * connected to different interrupt lines. In the muxed case only one
2271          * interrupt resource is specified. In the non-muxed case three or four
2272          * interrupt resources are specified, as the BRI interrupt is optional.
2273          */
2274         if (sci_port->irqs[0] < 0)
2275                 return -ENXIO;
2276 
2277         if (sci_port->irqs[1] < 0) {
2278                 sci_port->irqs[1] = sci_port->irqs[0];
2279                 sci_port->irqs[2] = sci_port->irqs[0];
2280                 sci_port->irqs[3] = sci_port->irqs[0];
2281         }
2282 
2283         if (p->regtype == SCIx_PROBE_REGTYPE) {
2284                 ret = sci_probe_regmap(p);
2285                 if (unlikely(ret))
2286                         return ret;
2287         }
2288 
2289         switch (p->type) {
2290         case PORT_SCIFB:
2291                 port->fifosize = 256;
2292                 sci_port->overrun_reg = SCxSR;
2293                 sci_port->overrun_mask = SCIFA_ORER;
2294                 sci_port->sampling_rate = 16;
2295                 break;
2296         case PORT_HSCIF:
2297                 port->fifosize = 128;
2298                 sci_port->overrun_reg = SCLSR;
2299                 sci_port->overrun_mask = SCLSR_ORER;
2300                 sci_port->sampling_rate = 0;
2301                 break;
2302         case PORT_SCIFA:
2303                 port->fifosize = 64;
2304                 sci_port->overrun_reg = SCxSR;
2305                 sci_port->overrun_mask = SCIFA_ORER;
2306                 sci_port->sampling_rate = 16;
2307                 break;
2308         case PORT_SCIF:
2309                 port->fifosize = 16;
2310                 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2311                         sci_port->overrun_reg = SCxSR;
2312                         sci_port->overrun_mask = SCIFA_ORER;
2313                         sci_port->sampling_rate = 16;
2314                 } else {
2315                         sci_port->overrun_reg = SCLSR;
2316                         sci_port->overrun_mask = SCLSR_ORER;
2317                         sci_port->sampling_rate = 32;
2318                 }
2319                 break;
2320         default:
2321                 port->fifosize = 1;
2322                 sci_port->overrun_reg = SCxSR;
2323                 sci_port->overrun_mask = SCI_ORER;
2324                 sci_port->sampling_rate = 32;
2325                 break;
2326         }
2327 
2328         /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2329          * match the SoC datasheet, this should be investigated. Let platform
2330          * data override the sampling rate for now.
2331          */
2332         if (p->sampling_rate)
2333                 sci_port->sampling_rate = p->sampling_rate;
2334 
2335         if (!early) {
2336                 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2337                 if (IS_ERR(sci_port->iclk)) {
2338                         sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2339                         if (IS_ERR(sci_port->iclk)) {
2340                                 dev_err(&dev->dev, "can't get iclk\n");
2341                                 return PTR_ERR(sci_port->iclk);
2342                         }
2343                 }
2344 
2345                 /*
2346                  * The function clock is optional, ignore it if we can't
2347                  * find it.
2348                  */
2349                 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2350                 if (IS_ERR(sci_port->fclk))
2351                         sci_port->fclk = NULL;
2352 
2353                 port->dev = &dev->dev;
2354 
2355                 pm_runtime_enable(&dev->dev);
2356         }
2357 
2358         sci_port->break_timer.data = (unsigned long)sci_port;
2359         sci_port->break_timer.function = sci_break_timer;
2360         init_timer(&sci_port->break_timer);
2361 
2362         /*
2363          * Establish some sensible defaults for the error detection.
2364          */
2365         if (p->type == PORT_SCI) {
2366                 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2367                 sci_port->error_clear = SCI_ERROR_CLEAR;
2368         } else {
2369                 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2370                 sci_port->error_clear = SCIF_ERROR_CLEAR;
2371         }
2372 
2373         /*
2374          * Make the error mask inclusive of overrun detection, if
2375          * supported.
2376          */
2377         if (sci_port->overrun_reg == SCxSR) {
2378                 sci_port->error_mask |= sci_port->overrun_mask;
2379                 sci_port->error_clear &= ~sci_port->overrun_mask;
2380         }
2381 
2382         port->type              = p->type;
2383         port->flags             = UPF_FIXED_PORT | p->flags;
2384         port->regshift          = p->regshift;
2385 
2386         /*
2387          * The UART port needs an IRQ value, so we peg this to the RX IRQ
2388          * for the multi-IRQ ports, which is where we are primarily
2389          * concerned with the shutdown path synchronization.
2390          *
2391          * For the muxed case there's nothing more to do.
2392          */
2393         port->irq               = sci_port->irqs[SCIx_RXI_IRQ];
2394         port->irqflags          = 0;
2395 
2396         port->serial_in         = sci_serial_in;
2397         port->serial_out        = sci_serial_out;
2398 
2399         if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2400                 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2401                         p->dma_slave_tx, p->dma_slave_rx);
2402 
2403         return 0;
2404 }
2405 
2406 static void sci_cleanup_single(struct sci_port *port)
2407 {
2408         clk_put(port->iclk);
2409         clk_put(port->fclk);
2410 
2411         pm_runtime_disable(port->port.dev);
2412 }
2413 
2414 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2415 static void serial_console_putchar(struct uart_port *port, int ch)
2416 {
2417         sci_poll_put_char(port, ch);
2418 }
2419 
2420 /*
2421  *      Print a string to the serial port trying not to disturb
2422  *      any possible real use of the port...
2423  */
2424 static void serial_console_write(struct console *co, const char *s,
2425                                  unsigned count)
2426 {
2427         struct sci_port *sci_port = &sci_ports[co->index];
2428         struct uart_port *port = &sci_port->port;
2429         unsigned short bits, ctrl;
2430         unsigned long flags;
2431         int locked = 1;
2432 
2433         local_irq_save(flags);
2434         if (port->sysrq)
2435                 locked = 0;
2436         else if (oops_in_progress)
2437                 locked = spin_trylock(&port->lock);
2438         else
2439                 spin_lock(&port->lock);
2440 
2441         /* first save the SCSCR then disable the interrupts */
2442         ctrl = serial_port_in(port, SCSCR);
2443         serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2444 
2445         uart_console_write(port, s, count, serial_console_putchar);
2446 
2447         /* wait until fifo is empty and last bit has been transmitted */
2448         bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2449         while ((serial_port_in(port, SCxSR) & bits) != bits)
2450                 cpu_relax();
2451 
2452         /* restore the SCSCR */
2453         serial_port_out(port, SCSCR, ctrl);
2454 
2455         if (locked)
2456                 spin_unlock(&port->lock);
2457         local_irq_restore(flags);
2458 }
2459 
2460 static int serial_console_setup(struct console *co, char *options)
2461 {
2462         struct sci_port *sci_port;
2463         struct uart_port *port;
2464         int baud = 115200;
2465         int bits = 8;
2466         int parity = 'n';
2467         int flow = 'n';
2468         int ret;
2469 
2470         /*
2471          * Refuse to handle any bogus ports.
2472          */
2473         if (co->index < 0 || co->index >= SCI_NPORTS)
2474                 return -ENODEV;
2475 
2476         sci_port = &sci_ports[co->index];
2477         port = &sci_port->port;
2478 
2479         /*
2480          * Refuse to handle uninitialized ports.
2481          */
2482         if (!port->ops)
2483                 return -ENODEV;
2484 
2485         ret = sci_remap_port(port);
2486         if (unlikely(ret != 0))
2487                 return ret;
2488 
2489         if (options)
2490                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2491 
2492         return uart_set_options(port, co, baud, parity, bits, flow);
2493 }
2494 
2495 static struct console serial_console = {
2496         .name           = "ttySC",
2497         .device         = uart_console_device,
2498         .write          = serial_console_write,
2499         .setup          = serial_console_setup,
2500         .flags          = CON_PRINTBUFFER,
2501         .index          = -1,
2502         .data           = &sci_uart_driver,
2503 };
2504 
2505 static struct console early_serial_console = {
2506         .name           = "early_ttySC",
2507         .write          = serial_console_write,
2508         .flags          = CON_PRINTBUFFER,
2509         .index          = -1,
2510 };
2511 
2512 static char early_serial_buf[32];
2513 
2514 static int sci_probe_earlyprintk(struct platform_device *pdev)
2515 {
2516         struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2517 
2518         if (early_serial_console.data)
2519                 return -EEXIST;
2520 
2521         early_serial_console.index = pdev->id;
2522 
2523         sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2524 
2525         serial_console_setup(&early_serial_console, early_serial_buf);
2526 
2527         if (!strstr(early_serial_buf, "keep"))
2528                 early_serial_console.flags |= CON_BOOT;
2529 
2530         register_console(&early_serial_console);
2531         return 0;
2532 }
2533 
2534 #define SCI_CONSOLE     (&serial_console)
2535 
2536 #else
2537 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2538 {
2539         return -EINVAL;
2540 }
2541 
2542 #define SCI_CONSOLE     NULL
2543 
2544 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2545 
2546 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2547 
2548 static struct uart_driver sci_uart_driver = {
2549         .owner          = THIS_MODULE,
2550         .driver_name    = "sci",
2551         .dev_name       = "ttySC",
2552         .major          = SCI_MAJOR,
2553         .minor          = SCI_MINOR_START,
2554         .nr             = SCI_NPORTS,
2555         .cons           = SCI_CONSOLE,
2556 };
2557 
2558 static int sci_remove(struct platform_device *dev)
2559 {
2560         struct sci_port *port = platform_get_drvdata(dev);
2561 
2562         cpufreq_unregister_notifier(&port->freq_transition,
2563                                     CPUFREQ_TRANSITION_NOTIFIER);
2564 
2565         uart_remove_one_port(&sci_uart_driver, &port->port);
2566 
2567         sci_cleanup_single(port);
2568 
2569         return 0;
2570 }
2571 
2572 struct sci_port_info {
2573         unsigned int type;
2574         unsigned int regtype;
2575 };
2576 
2577 static const struct of_device_id of_sci_match[] = {
2578         {
2579                 .compatible = "renesas,scif",
2580                 .data = &(const struct sci_port_info) {
2581                         .type = PORT_SCIF,
2582                         .regtype = SCIx_SH4_SCIF_REGTYPE,
2583                 },
2584         }, {
2585                 .compatible = "renesas,scifa",
2586                 .data = &(const struct sci_port_info) {
2587                         .type = PORT_SCIFA,
2588                         .regtype = SCIx_SCIFA_REGTYPE,
2589                 },
2590         }, {
2591                 .compatible = "renesas,scifb",
2592                 .data = &(const struct sci_port_info) {
2593                         .type = PORT_SCIFB,
2594                         .regtype = SCIx_SCIFB_REGTYPE,
2595                 },
2596         }, {
2597                 .compatible = "renesas,hscif",
2598                 .data = &(const struct sci_port_info) {
2599                         .type = PORT_HSCIF,
2600                         .regtype = SCIx_HSCIF_REGTYPE,
2601                 },
2602         }, {
2603                 .compatible = "renesas,sci",
2604                 .data = &(const struct sci_port_info) {
2605                         .type = PORT_SCI,
2606                         .regtype = SCIx_SCI_REGTYPE,
2607                 },
2608         }, {
2609                 /* Terminator */
2610         },
2611 };
2612 MODULE_DEVICE_TABLE(of, of_sci_match);
2613 
2614 static struct plat_sci_port *
2615 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2616 {
2617         struct device_node *np = pdev->dev.of_node;
2618         const struct of_device_id *match;
2619         const struct sci_port_info *info;
2620         struct plat_sci_port *p;
2621         int id;
2622 
2623         if (!IS_ENABLED(CONFIG_OF) || !np)
2624                 return NULL;
2625 
2626         match = of_match_node(of_sci_match, pdev->dev.of_node);
2627         if (!match)
2628                 return NULL;
2629 
2630         info = match->data;
2631 
2632         p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2633         if (!p)
2634                 return NULL;
2635 
2636         /* Get the line number for the aliases node. */
2637         id = of_alias_get_id(np, "serial");
2638         if (id < 0) {
2639                 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2640                 return NULL;
2641         }
2642 
2643         *dev_id = id;
2644 
2645         p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2646         p->type = info->type;
2647         p->regtype = info->regtype;
2648         p->scscr = SCSCR_RE | SCSCR_TE;
2649 
2650         return p;
2651 }
2652 
2653 static int sci_probe_single(struct platform_device *dev,
2654                                       unsigned int index,
2655                                       struct plat_sci_port *p,
2656                                       struct sci_port *sciport)
2657 {
2658         int ret;
2659 
2660         /* Sanity check */
2661         if (unlikely(index >= SCI_NPORTS)) {
2662                 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2663                            index+1, SCI_NPORTS);
2664                 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2665                 return -EINVAL;
2666         }
2667 
2668         ret = sci_init_single(dev, sciport, index, p, false);
2669         if (ret)
2670                 return ret;
2671 
2672         ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2673         if (ret) {
2674                 sci_cleanup_single(sciport);
2675                 return ret;
2676         }
2677 
2678         return 0;
2679 }
2680 
2681 static int sci_probe(struct platform_device *dev)
2682 {
2683         struct plat_sci_port *p;
2684         struct sci_port *sp;
2685         unsigned int dev_id;
2686         int ret;
2687 
2688         /*
2689          * If we've come here via earlyprintk initialization, head off to
2690          * the special early probe. We don't have sufficient device state
2691          * to make it beyond this yet.
2692          */
2693         if (is_early_platform_device(dev))
2694                 return sci_probe_earlyprintk(dev);
2695 
2696         if (dev->dev.of_node) {
2697                 p = sci_parse_dt(dev, &dev_id);
2698                 if (p == NULL)
2699                         return -EINVAL;
2700         } else {
2701                 p = dev->dev.platform_data;
2702                 if (p == NULL) {
2703                         dev_err(&dev->dev, "no platform data supplied\n");
2704                         return -EINVAL;
2705                 }
2706 
2707                 dev_id = dev->id;
2708         }
2709 
2710         sp = &sci_ports[dev_id];
2711         platform_set_drvdata(dev, sp);
2712 
2713         ret = sci_probe_single(dev, dev_id, p, sp);
2714         if (ret)
2715                 return ret;
2716 
2717         sp->freq_transition.notifier_call = sci_notifier;
2718 
2719         ret = cpufreq_register_notifier(&sp->freq_transition,
2720                                         CPUFREQ_TRANSITION_NOTIFIER);
2721         if (unlikely(ret < 0)) {
2722                 uart_remove_one_port(&sci_uart_driver, &sp->port);
2723                 sci_cleanup_single(sp);
2724                 return ret;
2725         }
2726 
2727 #ifdef CONFIG_SH_STANDARD_BIOS
2728         sh_bios_gdb_detach();
2729 #endif
2730 
2731         return 0;
2732 }
2733 
2734 static __maybe_unused int sci_suspend(struct device *dev)
2735 {
2736         struct sci_port *sport = dev_get_drvdata(dev);
2737 
2738         if (sport)
2739                 uart_suspend_port(&sci_uart_driver, &sport->port);
2740 
2741         return 0;
2742 }
2743 
2744 static __maybe_unused int sci_resume(struct device *dev)
2745 {
2746         struct sci_port *sport = dev_get_drvdata(dev);
2747 
2748         if (sport)
2749                 uart_resume_port(&sci_uart_driver, &sport->port);
2750 
2751         return 0;
2752 }
2753 
2754 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2755 
2756 static struct platform_driver sci_driver = {
2757         .probe          = sci_probe,
2758         .remove         = sci_remove,
2759         .driver         = {
2760                 .name   = "sh-sci",
2761                 .pm     = &sci_dev_pm_ops,
2762                 .of_match_table = of_match_ptr(of_sci_match),
2763         },
2764 };
2765 
2766 static int __init sci_init(void)
2767 {
2768         int ret;
2769 
2770         pr_info("%s\n", banner);
2771 
2772         ret = uart_register_driver(&sci_uart_driver);
2773         if (likely(ret == 0)) {
2774                 ret = platform_driver_register(&sci_driver);
2775                 if (unlikely(ret))
2776                         uart_unregister_driver(&sci_uart_driver);
2777         }
2778 
2779         return ret;
2780 }
2781 
2782 static void __exit sci_exit(void)
2783 {
2784         platform_driver_unregister(&sci_driver);
2785         uart_unregister_driver(&sci_uart_driver);
2786 }
2787 
2788 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2789 early_platform_init_buffer("earlyprintk", &sci_driver,
2790                            early_serial_buf, ARRAY_SIZE(early_serial_buf));
2791 #endif
2792 module_init(sci_init);
2793 module_exit(sci_exit);
2794 
2795 MODULE_LICENSE("GPL");
2796 MODULE_ALIAS("platform:sh-sci");
2797 MODULE_AUTHOR("Paul Mundt");
2798 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
2799 

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