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Linux/drivers/tty/serial/sh-sci.c

  1 /*
  2  * SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
  3  *
  4  *  Copyright (C) 2002 - 2011  Paul Mundt
  5  *  Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
  6  *
  7  * based off of the old drivers/char/sh-sci.c by:
  8  *
  9  *   Copyright (C) 1999, 2000  Niibe Yutaka
 10  *   Copyright (C) 2000  Sugioka Toshinobu
 11  *   Modified to support multiple serial ports. Stuart Menefy (May 2000).
 12  *   Modified to support SecureEdge. David McCullough (2002)
 13  *   Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
 14  *   Removed SH7300 support (Jul 2007).
 15  *
 16  * This file is subject to the terms and conditions of the GNU General Public
 17  * License.  See the file "COPYING" in the main directory of this archive
 18  * for more details.
 19  */
 20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 21 #define SUPPORT_SYSRQ
 22 #endif
 23 
 24 #undef DEBUG
 25 
 26 #include <linux/clk.h>
 27 #include <linux/console.h>
 28 #include <linux/ctype.h>
 29 #include <linux/cpufreq.h>
 30 #include <linux/delay.h>
 31 #include <linux/dmaengine.h>
 32 #include <linux/dma-mapping.h>
 33 #include <linux/err.h>
 34 #include <linux/errno.h>
 35 #include <linux/init.h>
 36 #include <linux/interrupt.h>
 37 #include <linux/ioport.h>
 38 #include <linux/major.h>
 39 #include <linux/module.h>
 40 #include <linux/mm.h>
 41 #include <linux/notifier.h>
 42 #include <linux/of.h>
 43 #include <linux/platform_device.h>
 44 #include <linux/pm_runtime.h>
 45 #include <linux/scatterlist.h>
 46 #include <linux/serial.h>
 47 #include <linux/serial_sci.h>
 48 #include <linux/sh_dma.h>
 49 #include <linux/slab.h>
 50 #include <linux/string.h>
 51 #include <linux/sysrq.h>
 52 #include <linux/timer.h>
 53 #include <linux/tty.h>
 54 #include <linux/tty_flip.h>
 55 
 56 #ifdef CONFIG_SUPERH
 57 #include <asm/sh_bios.h>
 58 #endif
 59 
 60 #include "sh-sci.h"
 61 
 62 /* Offsets into the sci_port->irqs array */
 63 enum {
 64         SCIx_ERI_IRQ,
 65         SCIx_RXI_IRQ,
 66         SCIx_TXI_IRQ,
 67         SCIx_BRI_IRQ,
 68         SCIx_NR_IRQS,
 69 
 70         SCIx_MUX_IRQ = SCIx_NR_IRQS,    /* special case */
 71 };
 72 
 73 #define SCIx_IRQ_IS_MUXED(port)                 \
 74         ((port)->irqs[SCIx_ERI_IRQ] ==  \
 75          (port)->irqs[SCIx_RXI_IRQ]) || \
 76         ((port)->irqs[SCIx_ERI_IRQ] &&  \
 77          ((port)->irqs[SCIx_RXI_IRQ] < 0))
 78 
 79 struct sci_port {
 80         struct uart_port        port;
 81 
 82         /* Platform configuration */
 83         struct plat_sci_port    *cfg;
 84         int                     overrun_bit;
 85         unsigned int            error_mask;
 86         unsigned int            sampling_rate;
 87 
 88 
 89         /* Break timer */
 90         struct timer_list       break_timer;
 91         int                     break_flag;
 92 
 93         /* Interface clock */
 94         struct clk              *iclk;
 95         /* Function clock */
 96         struct clk              *fclk;
 97 
 98         int                     irqs[SCIx_NR_IRQS];
 99         char                    *irqstr[SCIx_NR_IRQS];
100 
101         struct dma_chan                 *chan_tx;
102         struct dma_chan                 *chan_rx;
103 
104 #ifdef CONFIG_SERIAL_SH_SCI_DMA
105         struct dma_async_tx_descriptor  *desc_tx;
106         struct dma_async_tx_descriptor  *desc_rx[2];
107         dma_cookie_t                    cookie_tx;
108         dma_cookie_t                    cookie_rx[2];
109         dma_cookie_t                    active_rx;
110         struct scatterlist              sg_tx;
111         unsigned int                    sg_len_tx;
112         struct scatterlist              sg_rx[2];
113         size_t                          buf_len_rx;
114         struct sh_dmae_slave            param_tx;
115         struct sh_dmae_slave            param_rx;
116         struct work_struct              work_tx;
117         struct work_struct              work_rx;
118         struct timer_list               rx_timer;
119         unsigned int                    rx_timeout;
120 #endif
121 
122         struct notifier_block           freq_transition;
123 };
124 
125 /* Function prototypes */
126 static void sci_start_tx(struct uart_port *port);
127 static void sci_stop_tx(struct uart_port *port);
128 static void sci_start_rx(struct uart_port *port);
129 
130 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
131 
132 static struct sci_port sci_ports[SCI_NPORTS];
133 static struct uart_driver sci_uart_driver;
134 
135 static inline struct sci_port *
136 to_sci_port(struct uart_port *uart)
137 {
138         return container_of(uart, struct sci_port, port);
139 }
140 
141 struct plat_sci_reg {
142         u8 offset, size;
143 };
144 
145 /* Helper for invalidating specific entries of an inherited map. */
146 #define sci_reg_invalid { .offset = 0, .size = 0 }
147 
148 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
149         [SCIx_PROBE_REGTYPE] = {
150                 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
151         },
152 
153         /*
154          * Common SCI definitions, dependent on the port's regshift
155          * value.
156          */
157         [SCIx_SCI_REGTYPE] = {
158                 [SCSMR]         = { 0x00,  8 },
159                 [SCBRR]         = { 0x01,  8 },
160                 [SCSCR]         = { 0x02,  8 },
161                 [SCxTDR]        = { 0x03,  8 },
162                 [SCxSR]         = { 0x04,  8 },
163                 [SCxRDR]        = { 0x05,  8 },
164                 [SCFCR]         = sci_reg_invalid,
165                 [SCFDR]         = sci_reg_invalid,
166                 [SCTFDR]        = sci_reg_invalid,
167                 [SCRFDR]        = sci_reg_invalid,
168                 [SCSPTR]        = sci_reg_invalid,
169                 [SCLSR]         = sci_reg_invalid,
170                 [HSSRR]         = sci_reg_invalid,
171         },
172 
173         /*
174          * Common definitions for legacy IrDA ports, dependent on
175          * regshift value.
176          */
177         [SCIx_IRDA_REGTYPE] = {
178                 [SCSMR]         = { 0x00,  8 },
179                 [SCBRR]         = { 0x01,  8 },
180                 [SCSCR]         = { 0x02,  8 },
181                 [SCxTDR]        = { 0x03,  8 },
182                 [SCxSR]         = { 0x04,  8 },
183                 [SCxRDR]        = { 0x05,  8 },
184                 [SCFCR]         = { 0x06,  8 },
185                 [SCFDR]         = { 0x07, 16 },
186                 [SCTFDR]        = sci_reg_invalid,
187                 [SCRFDR]        = sci_reg_invalid,
188                 [SCSPTR]        = sci_reg_invalid,
189                 [SCLSR]         = sci_reg_invalid,
190                 [HSSRR]         = sci_reg_invalid,
191         },
192 
193         /*
194          * Common SCIFA definitions.
195          */
196         [SCIx_SCIFA_REGTYPE] = {
197                 [SCSMR]         = { 0x00, 16 },
198                 [SCBRR]         = { 0x04,  8 },
199                 [SCSCR]         = { 0x08, 16 },
200                 [SCxTDR]        = { 0x20,  8 },
201                 [SCxSR]         = { 0x14, 16 },
202                 [SCxRDR]        = { 0x24,  8 },
203                 [SCFCR]         = { 0x18, 16 },
204                 [SCFDR]         = { 0x1c, 16 },
205                 [SCTFDR]        = sci_reg_invalid,
206                 [SCRFDR]        = sci_reg_invalid,
207                 [SCSPTR]        = sci_reg_invalid,
208                 [SCLSR]         = sci_reg_invalid,
209                 [HSSRR]         = sci_reg_invalid,
210         },
211 
212         /*
213          * Common SCIFB definitions.
214          */
215         [SCIx_SCIFB_REGTYPE] = {
216                 [SCSMR]         = { 0x00, 16 },
217                 [SCBRR]         = { 0x04,  8 },
218                 [SCSCR]         = { 0x08, 16 },
219                 [SCxTDR]        = { 0x40,  8 },
220                 [SCxSR]         = { 0x14, 16 },
221                 [SCxRDR]        = { 0x60,  8 },
222                 [SCFCR]         = { 0x18, 16 },
223                 [SCFDR]         = sci_reg_invalid,
224                 [SCTFDR]        = { 0x38, 16 },
225                 [SCRFDR]        = { 0x3c, 16 },
226                 [SCSPTR]        = sci_reg_invalid,
227                 [SCLSR]         = sci_reg_invalid,
228                 [HSSRR]         = sci_reg_invalid,
229         },
230 
231         /*
232          * Common SH-2(A) SCIF definitions for ports with FIFO data
233          * count registers.
234          */
235         [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
236                 [SCSMR]         = { 0x00, 16 },
237                 [SCBRR]         = { 0x04,  8 },
238                 [SCSCR]         = { 0x08, 16 },
239                 [SCxTDR]        = { 0x0c,  8 },
240                 [SCxSR]         = { 0x10, 16 },
241                 [SCxRDR]        = { 0x14,  8 },
242                 [SCFCR]         = { 0x18, 16 },
243                 [SCFDR]         = { 0x1c, 16 },
244                 [SCTFDR]        = sci_reg_invalid,
245                 [SCRFDR]        = sci_reg_invalid,
246                 [SCSPTR]        = { 0x20, 16 },
247                 [SCLSR]         = { 0x24, 16 },
248                 [HSSRR]         = sci_reg_invalid,
249         },
250 
251         /*
252          * Common SH-3 SCIF definitions.
253          */
254         [SCIx_SH3_SCIF_REGTYPE] = {
255                 [SCSMR]         = { 0x00,  8 },
256                 [SCBRR]         = { 0x02,  8 },
257                 [SCSCR]         = { 0x04,  8 },
258                 [SCxTDR]        = { 0x06,  8 },
259                 [SCxSR]         = { 0x08, 16 },
260                 [SCxRDR]        = { 0x0a,  8 },
261                 [SCFCR]         = { 0x0c,  8 },
262                 [SCFDR]         = { 0x0e, 16 },
263                 [SCTFDR]        = sci_reg_invalid,
264                 [SCRFDR]        = sci_reg_invalid,
265                 [SCSPTR]        = sci_reg_invalid,
266                 [SCLSR]         = sci_reg_invalid,
267                 [HSSRR]         = sci_reg_invalid,
268         },
269 
270         /*
271          * Common SH-4(A) SCIF(B) definitions.
272          */
273         [SCIx_SH4_SCIF_REGTYPE] = {
274                 [SCSMR]         = { 0x00, 16 },
275                 [SCBRR]         = { 0x04,  8 },
276                 [SCSCR]         = { 0x08, 16 },
277                 [SCxTDR]        = { 0x0c,  8 },
278                 [SCxSR]         = { 0x10, 16 },
279                 [SCxRDR]        = { 0x14,  8 },
280                 [SCFCR]         = { 0x18, 16 },
281                 [SCFDR]         = { 0x1c, 16 },
282                 [SCTFDR]        = sci_reg_invalid,
283                 [SCRFDR]        = sci_reg_invalid,
284                 [SCSPTR]        = { 0x20, 16 },
285                 [SCLSR]         = { 0x24, 16 },
286                 [HSSRR]         = sci_reg_invalid,
287         },
288 
289         /*
290          * Common HSCIF definitions.
291          */
292         [SCIx_HSCIF_REGTYPE] = {
293                 [SCSMR]         = { 0x00, 16 },
294                 [SCBRR]         = { 0x04,  8 },
295                 [SCSCR]         = { 0x08, 16 },
296                 [SCxTDR]        = { 0x0c,  8 },
297                 [SCxSR]         = { 0x10, 16 },
298                 [SCxRDR]        = { 0x14,  8 },
299                 [SCFCR]         = { 0x18, 16 },
300                 [SCFDR]         = { 0x1c, 16 },
301                 [SCTFDR]        = sci_reg_invalid,
302                 [SCRFDR]        = sci_reg_invalid,
303                 [SCSPTR]        = { 0x20, 16 },
304                 [SCLSR]         = { 0x24, 16 },
305                 [HSSRR]         = { 0x40, 16 },
306         },
307 
308         /*
309          * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
310          * register.
311          */
312         [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
313                 [SCSMR]         = { 0x00, 16 },
314                 [SCBRR]         = { 0x04,  8 },
315                 [SCSCR]         = { 0x08, 16 },
316                 [SCxTDR]        = { 0x0c,  8 },
317                 [SCxSR]         = { 0x10, 16 },
318                 [SCxRDR]        = { 0x14,  8 },
319                 [SCFCR]         = { 0x18, 16 },
320                 [SCFDR]         = { 0x1c, 16 },
321                 [SCTFDR]        = sci_reg_invalid,
322                 [SCRFDR]        = sci_reg_invalid,
323                 [SCSPTR]        = sci_reg_invalid,
324                 [SCLSR]         = { 0x24, 16 },
325                 [HSSRR]         = sci_reg_invalid,
326         },
327 
328         /*
329          * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
330          * count registers.
331          */
332         [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
333                 [SCSMR]         = { 0x00, 16 },
334                 [SCBRR]         = { 0x04,  8 },
335                 [SCSCR]         = { 0x08, 16 },
336                 [SCxTDR]        = { 0x0c,  8 },
337                 [SCxSR]         = { 0x10, 16 },
338                 [SCxRDR]        = { 0x14,  8 },
339                 [SCFCR]         = { 0x18, 16 },
340                 [SCFDR]         = { 0x1c, 16 },
341                 [SCTFDR]        = { 0x1c, 16 }, /* aliased to SCFDR */
342                 [SCRFDR]        = { 0x20, 16 },
343                 [SCSPTR]        = { 0x24, 16 },
344                 [SCLSR]         = { 0x28, 16 },
345                 [HSSRR]         = sci_reg_invalid,
346         },
347 
348         /*
349          * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
350          * registers.
351          */
352         [SCIx_SH7705_SCIF_REGTYPE] = {
353                 [SCSMR]         = { 0x00, 16 },
354                 [SCBRR]         = { 0x04,  8 },
355                 [SCSCR]         = { 0x08, 16 },
356                 [SCxTDR]        = { 0x20,  8 },
357                 [SCxSR]         = { 0x14, 16 },
358                 [SCxRDR]        = { 0x24,  8 },
359                 [SCFCR]         = { 0x18, 16 },
360                 [SCFDR]         = { 0x1c, 16 },
361                 [SCTFDR]        = sci_reg_invalid,
362                 [SCRFDR]        = sci_reg_invalid,
363                 [SCSPTR]        = sci_reg_invalid,
364                 [SCLSR]         = sci_reg_invalid,
365                 [HSSRR]         = sci_reg_invalid,
366         },
367 };
368 
369 #define sci_getreg(up, offset)          (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
370 
371 /*
372  * The "offset" here is rather misleading, in that it refers to an enum
373  * value relative to the port mapping rather than the fixed offset
374  * itself, which needs to be manually retrieved from the platform's
375  * register map for the given port.
376  */
377 static unsigned int sci_serial_in(struct uart_port *p, int offset)
378 {
379         struct plat_sci_reg *reg = sci_getreg(p, offset);
380 
381         if (reg->size == 8)
382                 return ioread8(p->membase + (reg->offset << p->regshift));
383         else if (reg->size == 16)
384                 return ioread16(p->membase + (reg->offset << p->regshift));
385         else
386                 WARN(1, "Invalid register access\n");
387 
388         return 0;
389 }
390 
391 static void sci_serial_out(struct uart_port *p, int offset, int value)
392 {
393         struct plat_sci_reg *reg = sci_getreg(p, offset);
394 
395         if (reg->size == 8)
396                 iowrite8(value, p->membase + (reg->offset << p->regshift));
397         else if (reg->size == 16)
398                 iowrite16(value, p->membase + (reg->offset << p->regshift));
399         else
400                 WARN(1, "Invalid register access\n");
401 }
402 
403 static int sci_probe_regmap(struct plat_sci_port *cfg)
404 {
405         switch (cfg->type) {
406         case PORT_SCI:
407                 cfg->regtype = SCIx_SCI_REGTYPE;
408                 break;
409         case PORT_IRDA:
410                 cfg->regtype = SCIx_IRDA_REGTYPE;
411                 break;
412         case PORT_SCIFA:
413                 cfg->regtype = SCIx_SCIFA_REGTYPE;
414                 break;
415         case PORT_SCIFB:
416                 cfg->regtype = SCIx_SCIFB_REGTYPE;
417                 break;
418         case PORT_SCIF:
419                 /*
420                  * The SH-4 is a bit of a misnomer here, although that's
421                  * where this particular port layout originated. This
422                  * configuration (or some slight variation thereof)
423                  * remains the dominant model for all SCIFs.
424                  */
425                 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
426                 break;
427         case PORT_HSCIF:
428                 cfg->regtype = SCIx_HSCIF_REGTYPE;
429                 break;
430         default:
431                 pr_err("Can't probe register map for given port\n");
432                 return -EINVAL;
433         }
434 
435         return 0;
436 }
437 
438 static void sci_port_enable(struct sci_port *sci_port)
439 {
440         if (!sci_port->port.dev)
441                 return;
442 
443         pm_runtime_get_sync(sci_port->port.dev);
444 
445         clk_prepare_enable(sci_port->iclk);
446         sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
447         clk_prepare_enable(sci_port->fclk);
448 }
449 
450 static void sci_port_disable(struct sci_port *sci_port)
451 {
452         if (!sci_port->port.dev)
453                 return;
454 
455         /* Cancel the break timer to ensure that the timer handler will not try
456          * to access the hardware with clocks and power disabled. Reset the
457          * break flag to make the break debouncing state machine ready for the
458          * next break.
459          */
460         del_timer_sync(&sci_port->break_timer);
461         sci_port->break_flag = 0;
462 
463         clk_disable_unprepare(sci_port->fclk);
464         clk_disable_unprepare(sci_port->iclk);
465 
466         pm_runtime_put_sync(sci_port->port.dev);
467 }
468 
469 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
470 
471 #ifdef CONFIG_CONSOLE_POLL
472 static int sci_poll_get_char(struct uart_port *port)
473 {
474         unsigned short status;
475         int c;
476 
477         do {
478                 status = serial_port_in(port, SCxSR);
479                 if (status & SCxSR_ERRORS(port)) {
480                         serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
481                         continue;
482                 }
483                 break;
484         } while (1);
485 
486         if (!(status & SCxSR_RDxF(port)))
487                 return NO_POLL_CHAR;
488 
489         c = serial_port_in(port, SCxRDR);
490 
491         /* Dummy read */
492         serial_port_in(port, SCxSR);
493         serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
494 
495         return c;
496 }
497 #endif
498 
499 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
500 {
501         unsigned short status;
502 
503         do {
504                 status = serial_port_in(port, SCxSR);
505         } while (!(status & SCxSR_TDxE(port)));
506 
507         serial_port_out(port, SCxTDR, c);
508         serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
509 }
510 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
511 
512 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
513 {
514         struct sci_port *s = to_sci_port(port);
515         struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
516 
517         /*
518          * Use port-specific handler if provided.
519          */
520         if (s->cfg->ops && s->cfg->ops->init_pins) {
521                 s->cfg->ops->init_pins(port, cflag);
522                 return;
523         }
524 
525         /*
526          * For the generic path SCSPTR is necessary. Bail out if that's
527          * unavailable, too.
528          */
529         if (!reg->size)
530                 return;
531 
532         if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
533             ((!(cflag & CRTSCTS)))) {
534                 unsigned short status;
535 
536                 status = serial_port_in(port, SCSPTR);
537                 status &= ~SCSPTR_CTSIO;
538                 status |= SCSPTR_RTSIO;
539                 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
540         }
541 }
542 
543 static int sci_txfill(struct uart_port *port)
544 {
545         struct plat_sci_reg *reg;
546 
547         reg = sci_getreg(port, SCTFDR);
548         if (reg->size)
549                 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
550 
551         reg = sci_getreg(port, SCFDR);
552         if (reg->size)
553                 return serial_port_in(port, SCFDR) >> 8;
554 
555         return !(serial_port_in(port, SCxSR) & SCI_TDRE);
556 }
557 
558 static int sci_txroom(struct uart_port *port)
559 {
560         return port->fifosize - sci_txfill(port);
561 }
562 
563 static int sci_rxfill(struct uart_port *port)
564 {
565         struct plat_sci_reg *reg;
566 
567         reg = sci_getreg(port, SCRFDR);
568         if (reg->size)
569                 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
570 
571         reg = sci_getreg(port, SCFDR);
572         if (reg->size)
573                 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
574 
575         return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
576 }
577 
578 /*
579  * SCI helper for checking the state of the muxed port/RXD pins.
580  */
581 static inline int sci_rxd_in(struct uart_port *port)
582 {
583         struct sci_port *s = to_sci_port(port);
584 
585         if (s->cfg->port_reg <= 0)
586                 return 1;
587 
588         /* Cast for ARM damage */
589         return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
590 }
591 
592 /* ********************************************************************** *
593  *                   the interrupt related routines                       *
594  * ********************************************************************** */
595 
596 static void sci_transmit_chars(struct uart_port *port)
597 {
598         struct circ_buf *xmit = &port->state->xmit;
599         unsigned int stopped = uart_tx_stopped(port);
600         unsigned short status;
601         unsigned short ctrl;
602         int count;
603 
604         status = serial_port_in(port, SCxSR);
605         if (!(status & SCxSR_TDxE(port))) {
606                 ctrl = serial_port_in(port, SCSCR);
607                 if (uart_circ_empty(xmit))
608                         ctrl &= ~SCSCR_TIE;
609                 else
610                         ctrl |= SCSCR_TIE;
611                 serial_port_out(port, SCSCR, ctrl);
612                 return;
613         }
614 
615         count = sci_txroom(port);
616 
617         do {
618                 unsigned char c;
619 
620                 if (port->x_char) {
621                         c = port->x_char;
622                         port->x_char = 0;
623                 } else if (!uart_circ_empty(xmit) && !stopped) {
624                         c = xmit->buf[xmit->tail];
625                         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
626                 } else {
627                         break;
628                 }
629 
630                 serial_port_out(port, SCxTDR, c);
631 
632                 port->icount.tx++;
633         } while (--count > 0);
634 
635         serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
636 
637         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
638                 uart_write_wakeup(port);
639         if (uart_circ_empty(xmit)) {
640                 sci_stop_tx(port);
641         } else {
642                 ctrl = serial_port_in(port, SCSCR);
643 
644                 if (port->type != PORT_SCI) {
645                         serial_port_in(port, SCxSR); /* Dummy read */
646                         serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
647                 }
648 
649                 ctrl |= SCSCR_TIE;
650                 serial_port_out(port, SCSCR, ctrl);
651         }
652 }
653 
654 /* On SH3, SCIF may read end-of-break as a space->mark char */
655 #define STEPFN(c)  ({int __c = (c); (((__c-1)|(__c)) == -1); })
656 
657 static void sci_receive_chars(struct uart_port *port)
658 {
659         struct sci_port *sci_port = to_sci_port(port);
660         struct tty_port *tport = &port->state->port;
661         int i, count, copied = 0;
662         unsigned short status;
663         unsigned char flag;
664 
665         status = serial_port_in(port, SCxSR);
666         if (!(status & SCxSR_RDxF(port)))
667                 return;
668 
669         while (1) {
670                 /* Don't copy more bytes than there is room for in the buffer */
671                 count = tty_buffer_request_room(tport, sci_rxfill(port));
672 
673                 /* If for any reason we can't copy more data, we're done! */
674                 if (count == 0)
675                         break;
676 
677                 if (port->type == PORT_SCI) {
678                         char c = serial_port_in(port, SCxRDR);
679                         if (uart_handle_sysrq_char(port, c) ||
680                             sci_port->break_flag)
681                                 count = 0;
682                         else
683                                 tty_insert_flip_char(tport, c, TTY_NORMAL);
684                 } else {
685                         for (i = 0; i < count; i++) {
686                                 char c = serial_port_in(port, SCxRDR);
687 
688                                 status = serial_port_in(port, SCxSR);
689 #if defined(CONFIG_CPU_SH3)
690                                 /* Skip "chars" during break */
691                                 if (sci_port->break_flag) {
692                                         if ((c == 0) &&
693                                             (status & SCxSR_FER(port))) {
694                                                 count--; i--;
695                                                 continue;
696                                         }
697 
698                                         /* Nonzero => end-of-break */
699                                         dev_dbg(port->dev, "debounce<%02x>\n", c);
700                                         sci_port->break_flag = 0;
701 
702                                         if (STEPFN(c)) {
703                                                 count--; i--;
704                                                 continue;
705                                         }
706                                 }
707 #endif /* CONFIG_CPU_SH3 */
708                                 if (uart_handle_sysrq_char(port, c)) {
709                                         count--; i--;
710                                         continue;
711                                 }
712 
713                                 /* Store data and status */
714                                 if (status & SCxSR_FER(port)) {
715                                         flag = TTY_FRAME;
716                                         port->icount.frame++;
717                                         dev_notice(port->dev, "frame error\n");
718                                 } else if (status & SCxSR_PER(port)) {
719                                         flag = TTY_PARITY;
720                                         port->icount.parity++;
721                                         dev_notice(port->dev, "parity error\n");
722                                 } else
723                                         flag = TTY_NORMAL;
724 
725                                 tty_insert_flip_char(tport, c, flag);
726                         }
727                 }
728 
729                 serial_port_in(port, SCxSR); /* dummy read */
730                 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
731 
732                 copied += count;
733                 port->icount.rx += count;
734         }
735 
736         if (copied) {
737                 /* Tell the rest of the system the news. New characters! */
738                 tty_flip_buffer_push(tport);
739         } else {
740                 serial_port_in(port, SCxSR); /* dummy read */
741                 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
742         }
743 }
744 
745 #define SCI_BREAK_JIFFIES (HZ/20)
746 
747 /*
748  * The sci generates interrupts during the break,
749  * 1 per millisecond or so during the break period, for 9600 baud.
750  * So dont bother disabling interrupts.
751  * But dont want more than 1 break event.
752  * Use a kernel timer to periodically poll the rx line until
753  * the break is finished.
754  */
755 static inline void sci_schedule_break_timer(struct sci_port *port)
756 {
757         mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
758 }
759 
760 /* Ensure that two consecutive samples find the break over. */
761 static void sci_break_timer(unsigned long data)
762 {
763         struct sci_port *port = (struct sci_port *)data;
764 
765         if (sci_rxd_in(&port->port) == 0) {
766                 port->break_flag = 1;
767                 sci_schedule_break_timer(port);
768         } else if (port->break_flag == 1) {
769                 /* break is over. */
770                 port->break_flag = 2;
771                 sci_schedule_break_timer(port);
772         } else
773                 port->break_flag = 0;
774 }
775 
776 static int sci_handle_errors(struct uart_port *port)
777 {
778         int copied = 0;
779         unsigned short status = serial_port_in(port, SCxSR);
780         struct tty_port *tport = &port->state->port;
781         struct sci_port *s = to_sci_port(port);
782 
783         /* Handle overruns */
784         if (status & (1 << s->overrun_bit)) {
785                 port->icount.overrun++;
786 
787                 /* overrun error */
788                 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
789                         copied++;
790 
791                 dev_notice(port->dev, "overrun error\n");
792         }
793 
794         if (status & SCxSR_FER(port)) {
795                 if (sci_rxd_in(port) == 0) {
796                         /* Notify of BREAK */
797                         struct sci_port *sci_port = to_sci_port(port);
798 
799                         if (!sci_port->break_flag) {
800                                 port->icount.brk++;
801 
802                                 sci_port->break_flag = 1;
803                                 sci_schedule_break_timer(sci_port);
804 
805                                 /* Do sysrq handling. */
806                                 if (uart_handle_break(port))
807                                         return 0;
808 
809                                 dev_dbg(port->dev, "BREAK detected\n");
810 
811                                 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
812                                         copied++;
813                         }
814 
815                 } else {
816                         /* frame error */
817                         port->icount.frame++;
818 
819                         if (tty_insert_flip_char(tport, 0, TTY_FRAME))
820                                 copied++;
821 
822                         dev_notice(port->dev, "frame error\n");
823                 }
824         }
825 
826         if (status & SCxSR_PER(port)) {
827                 /* parity error */
828                 port->icount.parity++;
829 
830                 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
831                         copied++;
832 
833                 dev_notice(port->dev, "parity error\n");
834         }
835 
836         if (copied)
837                 tty_flip_buffer_push(tport);
838 
839         return copied;
840 }
841 
842 static int sci_handle_fifo_overrun(struct uart_port *port)
843 {
844         struct tty_port *tport = &port->state->port;
845         struct sci_port *s = to_sci_port(port);
846         struct plat_sci_reg *reg;
847         int copied = 0;
848 
849         reg = sci_getreg(port, SCLSR);
850         if (!reg->size)
851                 return 0;
852 
853         if ((serial_port_in(port, SCLSR) & (1 << s->overrun_bit))) {
854                 serial_port_out(port, SCLSR, 0);
855 
856                 port->icount.overrun++;
857 
858                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
859                 tty_flip_buffer_push(tport);
860 
861                 dev_dbg(port->dev, "overrun error\n");
862                 copied++;
863         }
864 
865         return copied;
866 }
867 
868 static int sci_handle_breaks(struct uart_port *port)
869 {
870         int copied = 0;
871         unsigned short status = serial_port_in(port, SCxSR);
872         struct tty_port *tport = &port->state->port;
873         struct sci_port *s = to_sci_port(port);
874 
875         if (uart_handle_break(port))
876                 return 0;
877 
878         if (!s->break_flag && status & SCxSR_BRK(port)) {
879 #if defined(CONFIG_CPU_SH3)
880                 /* Debounce break */
881                 s->break_flag = 1;
882 #endif
883 
884                 port->icount.brk++;
885 
886                 /* Notify of BREAK */
887                 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
888                         copied++;
889 
890                 dev_dbg(port->dev, "BREAK detected\n");
891         }
892 
893         if (copied)
894                 tty_flip_buffer_push(tport);
895 
896         copied += sci_handle_fifo_overrun(port);
897 
898         return copied;
899 }
900 
901 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
902 {
903 #ifdef CONFIG_SERIAL_SH_SCI_DMA
904         struct uart_port *port = ptr;
905         struct sci_port *s = to_sci_port(port);
906 
907         if (s->chan_rx) {
908                 u16 scr = serial_port_in(port, SCSCR);
909                 u16 ssr = serial_port_in(port, SCxSR);
910 
911                 /* Disable future Rx interrupts */
912                 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
913                         disable_irq_nosync(irq);
914                         scr |= SCSCR_RDRQE;
915                 } else {
916                         scr &= ~SCSCR_RIE;
917                 }
918                 serial_port_out(port, SCSCR, scr);
919                 /* Clear current interrupt */
920                 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
921                 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
922                         jiffies, s->rx_timeout);
923                 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
924 
925                 return IRQ_HANDLED;
926         }
927 #endif
928 
929         /* I think sci_receive_chars has to be called irrespective
930          * of whether the I_IXOFF is set, otherwise, how is the interrupt
931          * to be disabled?
932          */
933         sci_receive_chars(ptr);
934 
935         return IRQ_HANDLED;
936 }
937 
938 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
939 {
940         struct uart_port *port = ptr;
941         unsigned long flags;
942 
943         spin_lock_irqsave(&port->lock, flags);
944         sci_transmit_chars(port);
945         spin_unlock_irqrestore(&port->lock, flags);
946 
947         return IRQ_HANDLED;
948 }
949 
950 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
951 {
952         struct uart_port *port = ptr;
953 
954         /* Handle errors */
955         if (port->type == PORT_SCI) {
956                 if (sci_handle_errors(port)) {
957                         /* discard character in rx buffer */
958                         serial_port_in(port, SCxSR);
959                         serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
960                 }
961         } else {
962                 sci_handle_fifo_overrun(port);
963                 sci_rx_interrupt(irq, ptr);
964         }
965 
966         serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
967 
968         /* Kick the transmission */
969         sci_tx_interrupt(irq, ptr);
970 
971         return IRQ_HANDLED;
972 }
973 
974 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
975 {
976         struct uart_port *port = ptr;
977 
978         /* Handle BREAKs */
979         sci_handle_breaks(port);
980         serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
981 
982         return IRQ_HANDLED;
983 }
984 
985 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
986 {
987         /*
988          * Not all ports (such as SCIFA) will support REIE. Rather than
989          * special-casing the port type, we check the port initialization
990          * IRQ enable mask to see whether the IRQ is desired at all. If
991          * it's unset, it's logically inferred that there's no point in
992          * testing for it.
993          */
994         return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
995 }
996 
997 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
998 {
999         unsigned short ssr_status, scr_status, err_enabled;
1000         unsigned short slr_status = 0;
1001         struct uart_port *port = ptr;
1002         struct sci_port *s = to_sci_port(port);
1003         irqreturn_t ret = IRQ_NONE;
1004 
1005         ssr_status = serial_port_in(port, SCxSR);
1006         scr_status = serial_port_in(port, SCSCR);
1007         if (port->type == PORT_SCIF || port->type == PORT_HSCIF)
1008                 slr_status = serial_port_in(port, SCLSR);
1009         err_enabled = scr_status & port_rx_irq_mask(port);
1010 
1011         /* Tx Interrupt */
1012         if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1013             !s->chan_tx)
1014                 ret = sci_tx_interrupt(irq, ptr);
1015 
1016         /*
1017          * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1018          * DR flags
1019          */
1020         if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1021             (scr_status & SCSCR_RIE)) {
1022                 if (port->type == PORT_SCIF || port->type == PORT_HSCIF)
1023                         sci_handle_fifo_overrun(port);
1024                 ret = sci_rx_interrupt(irq, ptr);
1025         }
1026 
1027         /* Error Interrupt */
1028         if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1029                 ret = sci_er_interrupt(irq, ptr);
1030 
1031         /* Break Interrupt */
1032         if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1033                 ret = sci_br_interrupt(irq, ptr);
1034 
1035         /* Overrun Interrupt */
1036         if (port->type == PORT_SCIF || port->type == PORT_HSCIF) {
1037                 if (slr_status & 0x01)
1038                         sci_handle_fifo_overrun(port);
1039         }
1040 
1041         return ret;
1042 }
1043 
1044 /*
1045  * Here we define a transition notifier so that we can update all of our
1046  * ports' baud rate when the peripheral clock changes.
1047  */
1048 static int sci_notifier(struct notifier_block *self,
1049                         unsigned long phase, void *p)
1050 {
1051         struct sci_port *sci_port;
1052         unsigned long flags;
1053 
1054         sci_port = container_of(self, struct sci_port, freq_transition);
1055 
1056         if (phase == CPUFREQ_POSTCHANGE) {
1057                 struct uart_port *port = &sci_port->port;
1058 
1059                 spin_lock_irqsave(&port->lock, flags);
1060                 port->uartclk = clk_get_rate(sci_port->iclk);
1061                 spin_unlock_irqrestore(&port->lock, flags);
1062         }
1063 
1064         return NOTIFY_OK;
1065 }
1066 
1067 static struct sci_irq_desc {
1068         const char      *desc;
1069         irq_handler_t   handler;
1070 } sci_irq_desc[] = {
1071         /*
1072          * Split out handlers, the default case.
1073          */
1074         [SCIx_ERI_IRQ] = {
1075                 .desc = "rx err",
1076                 .handler = sci_er_interrupt,
1077         },
1078 
1079         [SCIx_RXI_IRQ] = {
1080                 .desc = "rx full",
1081                 .handler = sci_rx_interrupt,
1082         },
1083 
1084         [SCIx_TXI_IRQ] = {
1085                 .desc = "tx empty",
1086                 .handler = sci_tx_interrupt,
1087         },
1088 
1089         [SCIx_BRI_IRQ] = {
1090                 .desc = "break",
1091                 .handler = sci_br_interrupt,
1092         },
1093 
1094         /*
1095          * Special muxed handler.
1096          */
1097         [SCIx_MUX_IRQ] = {
1098                 .desc = "mux",
1099                 .handler = sci_mpxed_interrupt,
1100         },
1101 };
1102 
1103 static int sci_request_irq(struct sci_port *port)
1104 {
1105         struct uart_port *up = &port->port;
1106         int i, j, ret = 0;
1107 
1108         for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1109                 struct sci_irq_desc *desc;
1110                 int irq;
1111 
1112                 if (SCIx_IRQ_IS_MUXED(port)) {
1113                         i = SCIx_MUX_IRQ;
1114                         irq = up->irq;
1115                 } else {
1116                         irq = port->irqs[i];
1117 
1118                         /*
1119                          * Certain port types won't support all of the
1120                          * available interrupt sources.
1121                          */
1122                         if (unlikely(irq < 0))
1123                                 continue;
1124                 }
1125 
1126                 desc = sci_irq_desc + i;
1127                 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1128                                             dev_name(up->dev), desc->desc);
1129                 if (!port->irqstr[j]) {
1130                         dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1131                                 desc->desc);
1132                         goto out_nomem;
1133                 }
1134 
1135                 ret = request_irq(irq, desc->handler, up->irqflags,
1136                                   port->irqstr[j], port);
1137                 if (unlikely(ret)) {
1138                         dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1139                         goto out_noirq;
1140                 }
1141         }
1142 
1143         return 0;
1144 
1145 out_noirq:
1146         while (--i >= 0)
1147                 free_irq(port->irqs[i], port);
1148 
1149 out_nomem:
1150         while (--j >= 0)
1151                 kfree(port->irqstr[j]);
1152 
1153         return ret;
1154 }
1155 
1156 static void sci_free_irq(struct sci_port *port)
1157 {
1158         int i;
1159 
1160         /*
1161          * Intentionally in reverse order so we iterate over the muxed
1162          * IRQ first.
1163          */
1164         for (i = 0; i < SCIx_NR_IRQS; i++) {
1165                 int irq = port->irqs[i];
1166 
1167                 /*
1168                  * Certain port types won't support all of the available
1169                  * interrupt sources.
1170                  */
1171                 if (unlikely(irq < 0))
1172                         continue;
1173 
1174                 free_irq(port->irqs[i], port);
1175                 kfree(port->irqstr[i]);
1176 
1177                 if (SCIx_IRQ_IS_MUXED(port)) {
1178                         /* If there's only one IRQ, we're done. */
1179                         return;
1180                 }
1181         }
1182 }
1183 
1184 static unsigned int sci_tx_empty(struct uart_port *port)
1185 {
1186         unsigned short status = serial_port_in(port, SCxSR);
1187         unsigned short in_tx_fifo = sci_txfill(port);
1188 
1189         return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1190 }
1191 
1192 /*
1193  * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1194  * CTS/RTS is supported in hardware by at least one port and controlled
1195  * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1196  * handled via the ->init_pins() op, which is a bit of a one-way street,
1197  * lacking any ability to defer pin control -- this will later be
1198  * converted over to the GPIO framework).
1199  *
1200  * Other modes (such as loopback) are supported generically on certain
1201  * port types, but not others. For these it's sufficient to test for the
1202  * existence of the support register and simply ignore the port type.
1203  */
1204 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1205 {
1206         if (mctrl & TIOCM_LOOP) {
1207                 struct plat_sci_reg *reg;
1208 
1209                 /*
1210                  * Standard loopback mode for SCFCR ports.
1211                  */
1212                 reg = sci_getreg(port, SCFCR);
1213                 if (reg->size)
1214                         serial_port_out(port, SCFCR,
1215                                         serial_port_in(port, SCFCR) |
1216                                         SCFCR_LOOP);
1217         }
1218 }
1219 
1220 static unsigned int sci_get_mctrl(struct uart_port *port)
1221 {
1222         /*
1223          * CTS/RTS is handled in hardware when supported, while nothing
1224          * else is wired up. Keep it simple and simply assert DSR/CAR.
1225          */
1226         return TIOCM_DSR | TIOCM_CAR;
1227 }
1228 
1229 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1230 static void sci_dma_tx_complete(void *arg)
1231 {
1232         struct sci_port *s = arg;
1233         struct uart_port *port = &s->port;
1234         struct circ_buf *xmit = &port->state->xmit;
1235         unsigned long flags;
1236 
1237         dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1238 
1239         spin_lock_irqsave(&port->lock, flags);
1240 
1241         xmit->tail += sg_dma_len(&s->sg_tx);
1242         xmit->tail &= UART_XMIT_SIZE - 1;
1243 
1244         port->icount.tx += sg_dma_len(&s->sg_tx);
1245 
1246         async_tx_ack(s->desc_tx);
1247         s->desc_tx = NULL;
1248 
1249         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1250                 uart_write_wakeup(port);
1251 
1252         if (!uart_circ_empty(xmit)) {
1253                 s->cookie_tx = 0;
1254                 schedule_work(&s->work_tx);
1255         } else {
1256                 s->cookie_tx = -EINVAL;
1257                 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1258                         u16 ctrl = serial_port_in(port, SCSCR);
1259                         serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1260                 }
1261         }
1262 
1263         spin_unlock_irqrestore(&port->lock, flags);
1264 }
1265 
1266 /* Locking: called with port lock held */
1267 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1268 {
1269         struct uart_port *port = &s->port;
1270         struct tty_port *tport = &port->state->port;
1271         int i, active, room;
1272 
1273         room = tty_buffer_request_room(tport, count);
1274 
1275         if (s->active_rx == s->cookie_rx[0]) {
1276                 active = 0;
1277         } else if (s->active_rx == s->cookie_rx[1]) {
1278                 active = 1;
1279         } else {
1280                 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1281                 return 0;
1282         }
1283 
1284         if (room < count)
1285                 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1286                          count - room);
1287         if (!room)
1288                 return room;
1289 
1290         for (i = 0; i < room; i++)
1291                 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1292                                      TTY_NORMAL);
1293 
1294         port->icount.rx += room;
1295 
1296         return room;
1297 }
1298 
1299 static void sci_dma_rx_complete(void *arg)
1300 {
1301         struct sci_port *s = arg;
1302         struct uart_port *port = &s->port;
1303         unsigned long flags;
1304         int count;
1305 
1306         dev_dbg(port->dev, "%s(%d) active #%d\n",
1307                 __func__, port->line, s->active_rx);
1308 
1309         spin_lock_irqsave(&port->lock, flags);
1310 
1311         count = sci_dma_rx_push(s, s->buf_len_rx);
1312 
1313         mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1314 
1315         spin_unlock_irqrestore(&port->lock, flags);
1316 
1317         if (count)
1318                 tty_flip_buffer_push(&port->state->port);
1319 
1320         schedule_work(&s->work_rx);
1321 }
1322 
1323 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1324 {
1325         struct dma_chan *chan = s->chan_rx;
1326         struct uart_port *port = &s->port;
1327 
1328         s->chan_rx = NULL;
1329         s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1330         dma_release_channel(chan);
1331         if (sg_dma_address(&s->sg_rx[0]))
1332                 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1333                                   sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1334         if (enable_pio)
1335                 sci_start_rx(port);
1336 }
1337 
1338 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1339 {
1340         struct dma_chan *chan = s->chan_tx;
1341         struct uart_port *port = &s->port;
1342 
1343         s->chan_tx = NULL;
1344         s->cookie_tx = -EINVAL;
1345         dma_release_channel(chan);
1346         if (enable_pio)
1347                 sci_start_tx(port);
1348 }
1349 
1350 static void sci_submit_rx(struct sci_port *s)
1351 {
1352         struct dma_chan *chan = s->chan_rx;
1353         int i;
1354 
1355         for (i = 0; i < 2; i++) {
1356                 struct scatterlist *sg = &s->sg_rx[i];
1357                 struct dma_async_tx_descriptor *desc;
1358 
1359                 desc = dmaengine_prep_slave_sg(chan,
1360                         sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1361 
1362                 if (desc) {
1363                         s->desc_rx[i] = desc;
1364                         desc->callback = sci_dma_rx_complete;
1365                         desc->callback_param = s;
1366                         s->cookie_rx[i] = desc->tx_submit(desc);
1367                 }
1368 
1369                 if (!desc || s->cookie_rx[i] < 0) {
1370                         if (i) {
1371                                 async_tx_ack(s->desc_rx[0]);
1372                                 s->cookie_rx[0] = -EINVAL;
1373                         }
1374                         if (desc) {
1375                                 async_tx_ack(desc);
1376                                 s->cookie_rx[i] = -EINVAL;
1377                         }
1378                         dev_warn(s->port.dev,
1379                                  "failed to re-start DMA, using PIO\n");
1380                         sci_rx_dma_release(s, true);
1381                         return;
1382                 }
1383                 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n",
1384                         __func__, s->cookie_rx[i], i);
1385         }
1386 
1387         s->active_rx = s->cookie_rx[0];
1388 
1389         dma_async_issue_pending(chan);
1390 }
1391 
1392 static void work_fn_rx(struct work_struct *work)
1393 {
1394         struct sci_port *s = container_of(work, struct sci_port, work_rx);
1395         struct uart_port *port = &s->port;
1396         struct dma_async_tx_descriptor *desc;
1397         int new;
1398 
1399         if (s->active_rx == s->cookie_rx[0]) {
1400                 new = 0;
1401         } else if (s->active_rx == s->cookie_rx[1]) {
1402                 new = 1;
1403         } else {
1404                 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1405                 return;
1406         }
1407         desc = s->desc_rx[new];
1408 
1409         if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1410             DMA_COMPLETE) {
1411                 /* Handle incomplete DMA receive */
1412                 struct dma_chan *chan = s->chan_rx;
1413                 struct shdma_desc *sh_desc = container_of(desc,
1414                                         struct shdma_desc, async_tx);
1415                 unsigned long flags;
1416                 int count;
1417 
1418                 dmaengine_terminate_all(chan);
1419                 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
1420                         sh_desc->partial, sh_desc->cookie);
1421 
1422                 spin_lock_irqsave(&port->lock, flags);
1423                 count = sci_dma_rx_push(s, sh_desc->partial);
1424                 spin_unlock_irqrestore(&port->lock, flags);
1425 
1426                 if (count)
1427                         tty_flip_buffer_push(&port->state->port);
1428 
1429                 sci_submit_rx(s);
1430 
1431                 return;
1432         }
1433 
1434         s->cookie_rx[new] = desc->tx_submit(desc);
1435         if (s->cookie_rx[new] < 0) {
1436                 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1437                 sci_rx_dma_release(s, true);
1438                 return;
1439         }
1440 
1441         s->active_rx = s->cookie_rx[!new];
1442 
1443         dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n",
1444                 __func__, s->cookie_rx[new], new, s->active_rx);
1445 }
1446 
1447 static void work_fn_tx(struct work_struct *work)
1448 {
1449         struct sci_port *s = container_of(work, struct sci_port, work_tx);
1450         struct dma_async_tx_descriptor *desc;
1451         struct dma_chan *chan = s->chan_tx;
1452         struct uart_port *port = &s->port;
1453         struct circ_buf *xmit = &port->state->xmit;
1454         struct scatterlist *sg = &s->sg_tx;
1455 
1456         /*
1457          * DMA is idle now.
1458          * Port xmit buffer is already mapped, and it is one page... Just adjust
1459          * offsets and lengths. Since it is a circular buffer, we have to
1460          * transmit till the end, and then the rest. Take the port lock to get a
1461          * consistent xmit buffer state.
1462          */
1463         spin_lock_irq(&port->lock);
1464         sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1465         sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1466                 sg->offset;
1467         sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1468                 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1469         spin_unlock_irq(&port->lock);
1470 
1471         BUG_ON(!sg_dma_len(sg));
1472 
1473         desc = dmaengine_prep_slave_sg(chan,
1474                         sg, s->sg_len_tx, DMA_MEM_TO_DEV,
1475                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1476         if (!desc) {
1477                 /* switch to PIO */
1478                 sci_tx_dma_release(s, true);
1479                 return;
1480         }
1481 
1482         dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1483 
1484         spin_lock_irq(&port->lock);
1485         s->desc_tx = desc;
1486         desc->callback = sci_dma_tx_complete;
1487         desc->callback_param = s;
1488         spin_unlock_irq(&port->lock);
1489         s->cookie_tx = desc->tx_submit(desc);
1490         if (s->cookie_tx < 0) {
1491                 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1492                 /* switch to PIO */
1493                 sci_tx_dma_release(s, true);
1494                 return;
1495         }
1496 
1497         dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1498                 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1499 
1500         dma_async_issue_pending(chan);
1501 }
1502 #endif
1503 
1504 static void sci_start_tx(struct uart_port *port)
1505 {
1506         struct sci_port *s = to_sci_port(port);
1507         unsigned short ctrl;
1508 
1509 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1510         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1511                 u16 new, scr = serial_port_in(port, SCSCR);
1512                 if (s->chan_tx)
1513                         new = scr | SCSCR_TDRQE;
1514                 else
1515                         new = scr & ~SCSCR_TDRQE;
1516                 if (new != scr)
1517                         serial_port_out(port, SCSCR, new);
1518         }
1519 
1520         if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1521             s->cookie_tx < 0) {
1522                 s->cookie_tx = 0;
1523                 schedule_work(&s->work_tx);
1524         }
1525 #endif
1526 
1527         if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1528                 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1529                 ctrl = serial_port_in(port, SCSCR);
1530                 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1531         }
1532 }
1533 
1534 static void sci_stop_tx(struct uart_port *port)
1535 {
1536         unsigned short ctrl;
1537 
1538         /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1539         ctrl = serial_port_in(port, SCSCR);
1540 
1541         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1542                 ctrl &= ~SCSCR_TDRQE;
1543 
1544         ctrl &= ~SCSCR_TIE;
1545 
1546         serial_port_out(port, SCSCR, ctrl);
1547 }
1548 
1549 static void sci_start_rx(struct uart_port *port)
1550 {
1551         unsigned short ctrl;
1552 
1553         ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1554 
1555         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1556                 ctrl &= ~SCSCR_RDRQE;
1557 
1558         serial_port_out(port, SCSCR, ctrl);
1559 }
1560 
1561 static void sci_stop_rx(struct uart_port *port)
1562 {
1563         unsigned short ctrl;
1564 
1565         ctrl = serial_port_in(port, SCSCR);
1566 
1567         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1568                 ctrl &= ~SCSCR_RDRQE;
1569 
1570         ctrl &= ~port_rx_irq_mask(port);
1571 
1572         serial_port_out(port, SCSCR, ctrl);
1573 }
1574 
1575 static void sci_break_ctl(struct uart_port *port, int break_state)
1576 {
1577         struct sci_port *s = to_sci_port(port);
1578         struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1579         unsigned short scscr, scsptr;
1580 
1581         /* check wheter the port has SCSPTR */
1582         if (!reg->size) {
1583                 /*
1584                  * Not supported by hardware. Most parts couple break and rx
1585                  * interrupts together, with break detection always enabled.
1586                  */
1587                 return;
1588         }
1589 
1590         scsptr = serial_port_in(port, SCSPTR);
1591         scscr = serial_port_in(port, SCSCR);
1592 
1593         if (break_state == -1) {
1594                 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1595                 scscr &= ~SCSCR_TE;
1596         } else {
1597                 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1598                 scscr |= SCSCR_TE;
1599         }
1600 
1601         serial_port_out(port, SCSPTR, scsptr);
1602         serial_port_out(port, SCSCR, scscr);
1603 }
1604 
1605 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1606 static bool filter(struct dma_chan *chan, void *slave)
1607 {
1608         struct sh_dmae_slave *param = slave;
1609 
1610         dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1611                 __func__, param->shdma_slave.slave_id);
1612 
1613         chan->private = &param->shdma_slave;
1614         return true;
1615 }
1616 
1617 static void rx_timer_fn(unsigned long arg)
1618 {
1619         struct sci_port *s = (struct sci_port *)arg;
1620         struct uart_port *port = &s->port;
1621         u16 scr = serial_port_in(port, SCSCR);
1622 
1623         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1624                 scr &= ~SCSCR_RDRQE;
1625                 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1626         }
1627         serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1628         dev_dbg(port->dev, "DMA Rx timed out\n");
1629         schedule_work(&s->work_rx);
1630 }
1631 
1632 static void sci_request_dma(struct uart_port *port)
1633 {
1634         struct sci_port *s = to_sci_port(port);
1635         struct sh_dmae_slave *param;
1636         struct dma_chan *chan;
1637         dma_cap_mask_t mask;
1638         int nent;
1639 
1640         dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1641 
1642         if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1643                 return;
1644 
1645         dma_cap_zero(mask);
1646         dma_cap_set(DMA_SLAVE, mask);
1647 
1648         param = &s->param_tx;
1649 
1650         /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1651         param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1652 
1653         s->cookie_tx = -EINVAL;
1654         chan = dma_request_channel(mask, filter, param);
1655         dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1656         if (chan) {
1657                 s->chan_tx = chan;
1658                 sg_init_table(&s->sg_tx, 1);
1659                 /* UART circular tx buffer is an aligned page. */
1660                 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1661                 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1662                             UART_XMIT_SIZE,
1663                             (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1664                 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1665                 if (!nent)
1666                         sci_tx_dma_release(s, false);
1667                 else
1668                         dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n",
1669                                 __func__,
1670                                 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1671                                 &sg_dma_address(&s->sg_tx));
1672 
1673                 s->sg_len_tx = nent;
1674 
1675                 INIT_WORK(&s->work_tx, work_fn_tx);
1676         }
1677 
1678         param = &s->param_rx;
1679 
1680         /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1681         param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1682 
1683         chan = dma_request_channel(mask, filter, param);
1684         dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1685         if (chan) {
1686                 dma_addr_t dma[2];
1687                 void *buf[2];
1688                 int i;
1689 
1690                 s->chan_rx = chan;
1691 
1692                 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1693                 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1694                                             &dma[0], GFP_KERNEL);
1695 
1696                 if (!buf[0]) {
1697                         dev_warn(port->dev,
1698                                  "failed to allocate dma buffer, using PIO\n");
1699                         sci_rx_dma_release(s, true);
1700                         return;
1701                 }
1702 
1703                 buf[1] = buf[0] + s->buf_len_rx;
1704                 dma[1] = dma[0] + s->buf_len_rx;
1705 
1706                 for (i = 0; i < 2; i++) {
1707                         struct scatterlist *sg = &s->sg_rx[i];
1708 
1709                         sg_init_table(sg, 1);
1710                         sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1711                                     (uintptr_t)buf[i] & ~PAGE_MASK);
1712                         sg_dma_address(sg) = dma[i];
1713                 }
1714 
1715                 INIT_WORK(&s->work_rx, work_fn_rx);
1716                 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1717 
1718                 sci_submit_rx(s);
1719         }
1720 }
1721 
1722 static void sci_free_dma(struct uart_port *port)
1723 {
1724         struct sci_port *s = to_sci_port(port);
1725 
1726         if (s->chan_tx)
1727                 sci_tx_dma_release(s, false);
1728         if (s->chan_rx)
1729                 sci_rx_dma_release(s, false);
1730 }
1731 #else
1732 static inline void sci_request_dma(struct uart_port *port)
1733 {
1734 }
1735 
1736 static inline void sci_free_dma(struct uart_port *port)
1737 {
1738 }
1739 #endif
1740 
1741 static int sci_startup(struct uart_port *port)
1742 {
1743         struct sci_port *s = to_sci_port(port);
1744         unsigned long flags;
1745         int ret;
1746 
1747         dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1748 
1749         ret = sci_request_irq(s);
1750         if (unlikely(ret < 0))
1751                 return ret;
1752 
1753         sci_request_dma(port);
1754 
1755         spin_lock_irqsave(&port->lock, flags);
1756         sci_start_tx(port);
1757         sci_start_rx(port);
1758         spin_unlock_irqrestore(&port->lock, flags);
1759 
1760         return 0;
1761 }
1762 
1763 static void sci_shutdown(struct uart_port *port)
1764 {
1765         struct sci_port *s = to_sci_port(port);
1766         unsigned long flags;
1767 
1768         dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1769 
1770         spin_lock_irqsave(&port->lock, flags);
1771         sci_stop_rx(port);
1772         sci_stop_tx(port);
1773         spin_unlock_irqrestore(&port->lock, flags);
1774 
1775         sci_free_dma(port);
1776         sci_free_irq(s);
1777 }
1778 
1779 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1780                                    unsigned long freq)
1781 {
1782         if (s->sampling_rate)
1783                 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1784 
1785         /* Warn, but use a safe default */
1786         WARN_ON(1);
1787 
1788         return ((freq + 16 * bps) / (32 * bps) - 1);
1789 }
1790 
1791 /* calculate frame length from SMR */
1792 static int sci_baud_calc_frame_len(unsigned int smr_val)
1793 {
1794         int len = 10;
1795 
1796         if (smr_val & SCSMR_CHR)
1797                 len--;
1798         if (smr_val & SCSMR_PE)
1799                 len++;
1800         if (smr_val & SCSMR_STOP)
1801                 len++;
1802 
1803         return len;
1804 }
1805 
1806 
1807 /* calculate sample rate, BRR, and clock select for HSCIF */
1808 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1809                                 int *brr, unsigned int *srr,
1810                                 unsigned int *cks, int frame_len)
1811 {
1812         int sr, c, br, err, recv_margin;
1813         int min_err = 1000; /* 100% */
1814         int recv_max_margin = 0;
1815 
1816         /* Find the combination of sample rate and clock select with the
1817            smallest deviation from the desired baud rate. */
1818         for (sr = 8; sr <= 32; sr++) {
1819                 for (c = 0; c <= 3; c++) {
1820                         /* integerized formulas from HSCIF documentation */
1821                         br = DIV_ROUND_CLOSEST(freq, (sr *
1822                                               (1 << (2 * c + 1)) * bps)) - 1;
1823                         br = clamp(br, 0, 255);
1824                         err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1825                                                (1 << (2 * c + 1)) / 1000)) -
1826                                                1000;
1827                         /* Calc recv margin
1828                          * M: Receive margin (%)
1829                          * N: Ratio of bit rate to clock (N = sampling rate)
1830                          * D: Clock duty (D = 0 to 1.0)
1831                          * L: Frame length (L = 9 to 12)
1832                          * F: Absolute value of clock frequency deviation
1833                          *
1834                          *  M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1835                          *      (|D - 0.5| / N * (1 + F))|
1836                          *  NOTE: Usually, treat D for 0.5, F is 0 by this
1837                          *        calculation.
1838                          */
1839                         recv_margin = abs((500 -
1840                                         DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1841                         if (abs(min_err) > abs(err)) {
1842                                 min_err = err;
1843                                 recv_max_margin = recv_margin;
1844                         } else if ((min_err == err) &&
1845                                    (recv_margin > recv_max_margin))
1846                                 recv_max_margin = recv_margin;
1847                         else
1848                                 continue;
1849 
1850                         *brr = br;
1851                         *srr = sr - 1;
1852                         *cks = c;
1853                 }
1854         }
1855 
1856         if (min_err == 1000) {
1857                 WARN_ON(1);
1858                 /* use defaults */
1859                 *brr = 255;
1860                 *srr = 15;
1861                 *cks = 0;
1862         }
1863 }
1864 
1865 static void sci_reset(struct uart_port *port)
1866 {
1867         struct plat_sci_reg *reg;
1868         unsigned int status;
1869 
1870         do {
1871                 status = serial_port_in(port, SCxSR);
1872         } while (!(status & SCxSR_TEND(port)));
1873 
1874         serial_port_out(port, SCSCR, 0x00);     /* TE=0, RE=0, CKE1=0 */
1875 
1876         reg = sci_getreg(port, SCFCR);
1877         if (reg->size)
1878                 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1879 }
1880 
1881 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1882                             struct ktermios *old)
1883 {
1884         struct sci_port *s = to_sci_port(port);
1885         struct plat_sci_reg *reg;
1886         unsigned int baud, smr_val = 0, max_baud, cks = 0;
1887         int t = -1;
1888         unsigned int srr = 15;
1889 
1890         if ((termios->c_cflag & CSIZE) == CS7)
1891                 smr_val |= SCSMR_CHR;
1892         if (termios->c_cflag & PARENB)
1893                 smr_val |= SCSMR_PE;
1894         if (termios->c_cflag & PARODD)
1895                 smr_val |= SCSMR_PE | SCSMR_ODD;
1896         if (termios->c_cflag & CSTOPB)
1897                 smr_val |= SCSMR_STOP;
1898 
1899         /*
1900          * earlyprintk comes here early on with port->uartclk set to zero.
1901          * the clock framework is not up and running at this point so here
1902          * we assume that 115200 is the maximum baud rate. please note that
1903          * the baud rate is not programmed during earlyprintk - it is assumed
1904          * that the previous boot loader has enabled required clocks and
1905          * setup the baud rate generator hardware for us already.
1906          */
1907         max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1908 
1909         baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1910         if (likely(baud && port->uartclk)) {
1911                 if (s->cfg->type == PORT_HSCIF) {
1912                         int frame_len = sci_baud_calc_frame_len(smr_val);
1913                         sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1914                                             &cks, frame_len);
1915                 } else {
1916                         t = sci_scbrr_calc(s, baud, port->uartclk);
1917                         for (cks = 0; t >= 256 && cks <= 3; cks++)
1918                                 t >>= 2;
1919                 }
1920         }
1921 
1922         sci_port_enable(s);
1923 
1924         sci_reset(port);
1925 
1926         smr_val |= serial_port_in(port, SCSMR) & 3;
1927 
1928         uart_update_timeout(port, termios->c_cflag, baud);
1929 
1930         dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1931                 __func__, smr_val, cks, t, s->cfg->scscr);
1932 
1933         if (t >= 0) {
1934                 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
1935                 serial_port_out(port, SCBRR, t);
1936                 reg = sci_getreg(port, HSSRR);
1937                 if (reg->size)
1938                         serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1939                 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1940         } else
1941                 serial_port_out(port, SCSMR, smr_val);
1942 
1943         sci_init_pins(port, termios->c_cflag);
1944 
1945         reg = sci_getreg(port, SCFCR);
1946         if (reg->size) {
1947                 unsigned short ctrl = serial_port_in(port, SCFCR);
1948 
1949                 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1950                         if (termios->c_cflag & CRTSCTS)
1951                                 ctrl |= SCFCR_MCE;
1952                         else
1953                                 ctrl &= ~SCFCR_MCE;
1954                 }
1955 
1956                 /*
1957                  * As we've done a sci_reset() above, ensure we don't
1958                  * interfere with the FIFOs while toggling MCE. As the
1959                  * reset values could still be set, simply mask them out.
1960                  */
1961                 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1962 
1963                 serial_port_out(port, SCFCR, ctrl);
1964         }
1965 
1966         serial_port_out(port, SCSCR, s->cfg->scscr);
1967 
1968 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1969         /*
1970          * Calculate delay for 1.5 DMA buffers: see
1971          * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1972          * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1973          * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1974          * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1975          * sizes), but it has been found out experimentally, that this is not
1976          * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1977          * as a minimum seem to work perfectly.
1978          */
1979         if (s->chan_rx) {
1980                 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1981                         port->fifosize / 2;
1982                 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1983                         s->rx_timeout * 1000 / HZ, port->timeout);
1984                 if (s->rx_timeout < msecs_to_jiffies(20))
1985                         s->rx_timeout = msecs_to_jiffies(20);
1986         }
1987 #endif
1988 
1989         if ((termios->c_cflag & CREAD) != 0)
1990                 sci_start_rx(port);
1991 
1992         sci_port_disable(s);
1993 }
1994 
1995 static void sci_pm(struct uart_port *port, unsigned int state,
1996                    unsigned int oldstate)
1997 {
1998         struct sci_port *sci_port = to_sci_port(port);
1999 
2000         switch (state) {
2001         case UART_PM_STATE_OFF:
2002                 sci_port_disable(sci_port);
2003                 break;
2004         default:
2005                 sci_port_enable(sci_port);
2006                 break;
2007         }
2008 }
2009 
2010 static const char *sci_type(struct uart_port *port)
2011 {
2012         switch (port->type) {
2013         case PORT_IRDA:
2014                 return "irda";
2015         case PORT_SCI:
2016                 return "sci";
2017         case PORT_SCIF:
2018                 return "scif";
2019         case PORT_SCIFA:
2020                 return "scifa";
2021         case PORT_SCIFB:
2022                 return "scifb";
2023         case PORT_HSCIF:
2024                 return "hscif";
2025         }
2026 
2027         return NULL;
2028 }
2029 
2030 static inline unsigned long sci_port_size(struct uart_port *port)
2031 {
2032         /*
2033          * Pick an arbitrary size that encapsulates all of the base
2034          * registers by default. This can be optimized later, or derived
2035          * from platform resource data at such a time that ports begin to
2036          * behave more erratically.
2037          */
2038         if (port->type == PORT_HSCIF)
2039                 return 96;
2040         else
2041                 return 64;
2042 }
2043 
2044 static int sci_remap_port(struct uart_port *port)
2045 {
2046         unsigned long size = sci_port_size(port);
2047 
2048         /*
2049          * Nothing to do if there's already an established membase.
2050          */
2051         if (port->membase)
2052                 return 0;
2053 
2054         if (port->flags & UPF_IOREMAP) {
2055                 port->membase = ioremap_nocache(port->mapbase, size);
2056                 if (unlikely(!port->membase)) {
2057                         dev_err(port->dev, "can't remap port#%d\n", port->line);
2058                         return -ENXIO;
2059                 }
2060         } else {
2061                 /*
2062                  * For the simple (and majority of) cases where we don't
2063                  * need to do any remapping, just cast the cookie
2064                  * directly.
2065                  */
2066                 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2067         }
2068 
2069         return 0;
2070 }
2071 
2072 static void sci_release_port(struct uart_port *port)
2073 {
2074         if (port->flags & UPF_IOREMAP) {
2075                 iounmap(port->membase);
2076                 port->membase = NULL;
2077         }
2078 
2079         release_mem_region(port->mapbase, sci_port_size(port));
2080 }
2081 
2082 static int sci_request_port(struct uart_port *port)
2083 {
2084         unsigned long size = sci_port_size(port);
2085         struct resource *res;
2086         int ret;
2087 
2088         res = request_mem_region(port->mapbase, size, dev_name(port->dev));
2089         if (unlikely(res == NULL))
2090                 return -EBUSY;
2091 
2092         ret = sci_remap_port(port);
2093         if (unlikely(ret != 0)) {
2094                 release_resource(res);
2095                 return ret;
2096         }
2097 
2098         return 0;
2099 }
2100 
2101 static void sci_config_port(struct uart_port *port, int flags)
2102 {
2103         if (flags & UART_CONFIG_TYPE) {
2104                 struct sci_port *sport = to_sci_port(port);
2105 
2106                 port->type = sport->cfg->type;
2107                 sci_request_port(port);
2108         }
2109 }
2110 
2111 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2112 {
2113         if (ser->baud_base < 2400)
2114                 /* No paper tape reader for Mitch.. */
2115                 return -EINVAL;
2116 
2117         return 0;
2118 }
2119 
2120 static struct uart_ops sci_uart_ops = {
2121         .tx_empty       = sci_tx_empty,
2122         .set_mctrl      = sci_set_mctrl,
2123         .get_mctrl      = sci_get_mctrl,
2124         .start_tx       = sci_start_tx,
2125         .stop_tx        = sci_stop_tx,
2126         .stop_rx        = sci_stop_rx,
2127         .break_ctl      = sci_break_ctl,
2128         .startup        = sci_startup,
2129         .shutdown       = sci_shutdown,
2130         .set_termios    = sci_set_termios,
2131         .pm             = sci_pm,
2132         .type           = sci_type,
2133         .release_port   = sci_release_port,
2134         .request_port   = sci_request_port,
2135         .config_port    = sci_config_port,
2136         .verify_port    = sci_verify_port,
2137 #ifdef CONFIG_CONSOLE_POLL
2138         .poll_get_char  = sci_poll_get_char,
2139         .poll_put_char  = sci_poll_put_char,
2140 #endif
2141 };
2142 
2143 static int sci_init_single(struct platform_device *dev,
2144                            struct sci_port *sci_port, unsigned int index,
2145                            struct plat_sci_port *p, bool early)
2146 {
2147         struct uart_port *port = &sci_port->port;
2148         const struct resource *res;
2149         unsigned int sampling_rate;
2150         unsigned int i;
2151         int ret;
2152 
2153         sci_port->cfg   = p;
2154 
2155         port->ops       = &sci_uart_ops;
2156         port->iotype    = UPIO_MEM;
2157         port->line      = index;
2158 
2159         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2160         if (res == NULL)
2161                 return -ENOMEM;
2162 
2163         port->mapbase = res->start;
2164 
2165         for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2166                 sci_port->irqs[i] = platform_get_irq(dev, i);
2167 
2168         /* The SCI generates several interrupts. They can be muxed together or
2169          * connected to different interrupt lines. In the muxed case only one
2170          * interrupt resource is specified. In the non-muxed case three or four
2171          * interrupt resources are specified, as the BRI interrupt is optional.
2172          */
2173         if (sci_port->irqs[0] < 0)
2174                 return -ENXIO;
2175 
2176         if (sci_port->irqs[1] < 0) {
2177                 sci_port->irqs[1] = sci_port->irqs[0];
2178                 sci_port->irqs[2] = sci_port->irqs[0];
2179                 sci_port->irqs[3] = sci_port->irqs[0];
2180         }
2181 
2182         if (p->regtype == SCIx_PROBE_REGTYPE) {
2183                 ret = sci_probe_regmap(p);
2184                 if (unlikely(ret))
2185                         return ret;
2186         }
2187 
2188         switch (p->type) {
2189         case PORT_SCIFB:
2190                 port->fifosize = 256;
2191                 sci_port->overrun_bit = 9;
2192                 sampling_rate = 16;
2193                 break;
2194         case PORT_HSCIF:
2195                 port->fifosize = 128;
2196                 sampling_rate = 0;
2197                 sci_port->overrun_bit = 0;
2198                 break;
2199         case PORT_SCIFA:
2200                 port->fifosize = 64;
2201                 sci_port->overrun_bit = 9;
2202                 sampling_rate = 16;
2203                 break;
2204         case PORT_SCIF:
2205                 port->fifosize = 16;
2206                 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2207                         sci_port->overrun_bit = 9;
2208                         sampling_rate = 16;
2209                 } else {
2210                         sci_port->overrun_bit = 0;
2211                         sampling_rate = 32;
2212                 }
2213                 break;
2214         default:
2215                 port->fifosize = 1;
2216                 sci_port->overrun_bit = 5;
2217                 sampling_rate = 32;
2218                 break;
2219         }
2220 
2221         /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2222          * match the SoC datasheet, this should be investigated. Let platform
2223          * data override the sampling rate for now.
2224          */
2225         sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
2226                                 : sampling_rate;
2227 
2228         if (!early) {
2229                 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2230                 if (IS_ERR(sci_port->iclk)) {
2231                         sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2232                         if (IS_ERR(sci_port->iclk)) {
2233                                 dev_err(&dev->dev, "can't get iclk\n");
2234                                 return PTR_ERR(sci_port->iclk);
2235                         }
2236                 }
2237 
2238                 /*
2239                  * The function clock is optional, ignore it if we can't
2240                  * find it.
2241                  */
2242                 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2243                 if (IS_ERR(sci_port->fclk))
2244                         sci_port->fclk = NULL;
2245 
2246                 port->dev = &dev->dev;
2247 
2248                 pm_runtime_enable(&dev->dev);
2249         }
2250 
2251         sci_port->break_timer.data = (unsigned long)sci_port;
2252         sci_port->break_timer.function = sci_break_timer;
2253         init_timer(&sci_port->break_timer);
2254 
2255         /*
2256          * Establish some sensible defaults for the error detection.
2257          */
2258         sci_port->error_mask = (p->type == PORT_SCI) ?
2259                         SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2260 
2261         /*
2262          * Establish sensible defaults for the overrun detection, unless
2263          * the part has explicitly disabled support for it.
2264          */
2265 
2266         /*
2267          * Make the error mask inclusive of overrun detection, if
2268          * supported.
2269          */
2270         sci_port->error_mask |= 1 << sci_port->overrun_bit;
2271 
2272         port->type              = p->type;
2273         port->flags             = UPF_FIXED_PORT | p->flags;
2274         port->regshift          = p->regshift;
2275 
2276         /*
2277          * The UART port needs an IRQ value, so we peg this to the RX IRQ
2278          * for the multi-IRQ ports, which is where we are primarily
2279          * concerned with the shutdown path synchronization.
2280          *
2281          * For the muxed case there's nothing more to do.
2282          */
2283         port->irq               = sci_port->irqs[SCIx_RXI_IRQ];
2284         port->irqflags          = 0;
2285 
2286         port->serial_in         = sci_serial_in;
2287         port->serial_out        = sci_serial_out;
2288 
2289         if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2290                 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2291                         p->dma_slave_tx, p->dma_slave_rx);
2292 
2293         return 0;
2294 }
2295 
2296 static void sci_cleanup_single(struct sci_port *port)
2297 {
2298         clk_put(port->iclk);
2299         clk_put(port->fclk);
2300 
2301         pm_runtime_disable(port->port.dev);
2302 }
2303 
2304 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2305 static void serial_console_putchar(struct uart_port *port, int ch)
2306 {
2307         sci_poll_put_char(port, ch);
2308 }
2309 
2310 /*
2311  *      Print a string to the serial port trying not to disturb
2312  *      any possible real use of the port...
2313  */
2314 static void serial_console_write(struct console *co, const char *s,
2315                                  unsigned count)
2316 {
2317         struct sci_port *sci_port = &sci_ports[co->index];
2318         struct uart_port *port = &sci_port->port;
2319         unsigned short bits, ctrl;
2320         unsigned long flags;
2321         int locked = 1;
2322 
2323         local_irq_save(flags);
2324         if (port->sysrq)
2325                 locked = 0;
2326         else if (oops_in_progress)
2327                 locked = spin_trylock(&port->lock);
2328         else
2329                 spin_lock(&port->lock);
2330 
2331         /* first save the SCSCR then disable the interrupts */
2332         ctrl = serial_port_in(port, SCSCR);
2333         serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2334 
2335         uart_console_write(port, s, count, serial_console_putchar);
2336 
2337         /* wait until fifo is empty and last bit has been transmitted */
2338         bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2339         while ((serial_port_in(port, SCxSR) & bits) != bits)
2340                 cpu_relax();
2341 
2342         /* restore the SCSCR */
2343         serial_port_out(port, SCSCR, ctrl);
2344 
2345         if (locked)
2346                 spin_unlock(&port->lock);
2347         local_irq_restore(flags);
2348 }
2349 
2350 static int serial_console_setup(struct console *co, char *options)
2351 {
2352         struct sci_port *sci_port;
2353         struct uart_port *port;
2354         int baud = 115200;
2355         int bits = 8;
2356         int parity = 'n';
2357         int flow = 'n';
2358         int ret;
2359 
2360         /*
2361          * Refuse to handle any bogus ports.
2362          */
2363         if (co->index < 0 || co->index >= SCI_NPORTS)
2364                 return -ENODEV;
2365 
2366         sci_port = &sci_ports[co->index];
2367         port = &sci_port->port;
2368 
2369         /*
2370          * Refuse to handle uninitialized ports.
2371          */
2372         if (!port->ops)
2373                 return -ENODEV;
2374 
2375         ret = sci_remap_port(port);
2376         if (unlikely(ret != 0))
2377                 return ret;
2378 
2379         if (options)
2380                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2381 
2382         return uart_set_options(port, co, baud, parity, bits, flow);
2383 }
2384 
2385 static struct console serial_console = {
2386         .name           = "ttySC",
2387         .device         = uart_console_device,
2388         .write          = serial_console_write,
2389         .setup          = serial_console_setup,
2390         .flags          = CON_PRINTBUFFER,
2391         .index          = -1,
2392         .data           = &sci_uart_driver,
2393 };
2394 
2395 static struct console early_serial_console = {
2396         .name           = "early_ttySC",
2397         .write          = serial_console_write,
2398         .flags          = CON_PRINTBUFFER,
2399         .index          = -1,
2400 };
2401 
2402 static char early_serial_buf[32];
2403 
2404 static int sci_probe_earlyprintk(struct platform_device *pdev)
2405 {
2406         struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2407 
2408         if (early_serial_console.data)
2409                 return -EEXIST;
2410 
2411         early_serial_console.index = pdev->id;
2412 
2413         sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2414 
2415         serial_console_setup(&early_serial_console, early_serial_buf);
2416 
2417         if (!strstr(early_serial_buf, "keep"))
2418                 early_serial_console.flags |= CON_BOOT;
2419 
2420         register_console(&early_serial_console);
2421         return 0;
2422 }
2423 
2424 #define SCI_CONSOLE     (&serial_console)
2425 
2426 #else
2427 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2428 {
2429         return -EINVAL;
2430 }
2431 
2432 #define SCI_CONSOLE     NULL
2433 
2434 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2435 
2436 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2437 
2438 static struct uart_driver sci_uart_driver = {
2439         .owner          = THIS_MODULE,
2440         .driver_name    = "sci",
2441         .dev_name       = "ttySC",
2442         .major          = SCI_MAJOR,
2443         .minor          = SCI_MINOR_START,
2444         .nr             = SCI_NPORTS,
2445         .cons           = SCI_CONSOLE,
2446 };
2447 
2448 static int sci_remove(struct platform_device *dev)
2449 {
2450         struct sci_port *port = platform_get_drvdata(dev);
2451 
2452         cpufreq_unregister_notifier(&port->freq_transition,
2453                                     CPUFREQ_TRANSITION_NOTIFIER);
2454 
2455         uart_remove_one_port(&sci_uart_driver, &port->port);
2456 
2457         sci_cleanup_single(port);
2458 
2459         return 0;
2460 }
2461 
2462 struct sci_port_info {
2463         unsigned int type;
2464         unsigned int regtype;
2465 };
2466 
2467 static const struct of_device_id of_sci_match[] = {
2468         {
2469                 .compatible = "renesas,scif",
2470                 .data = &(const struct sci_port_info) {
2471                         .type = PORT_SCIF,
2472                         .regtype = SCIx_SH4_SCIF_REGTYPE,
2473                 },
2474         }, {
2475                 .compatible = "renesas,scifa",
2476                 .data = &(const struct sci_port_info) {
2477                         .type = PORT_SCIFA,
2478                         .regtype = SCIx_SCIFA_REGTYPE,
2479                 },
2480         }, {
2481                 .compatible = "renesas,scifb",
2482                 .data = &(const struct sci_port_info) {
2483                         .type = PORT_SCIFB,
2484                         .regtype = SCIx_SCIFB_REGTYPE,
2485                 },
2486         }, {
2487                 .compatible = "renesas,hscif",
2488                 .data = &(const struct sci_port_info) {
2489                         .type = PORT_HSCIF,
2490                         .regtype = SCIx_HSCIF_REGTYPE,
2491                 },
2492         }, {
2493                 /* Terminator */
2494         },
2495 };
2496 MODULE_DEVICE_TABLE(of, of_sci_match);
2497 
2498 static struct plat_sci_port *
2499 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2500 {
2501         struct device_node *np = pdev->dev.of_node;
2502         const struct of_device_id *match;
2503         const struct sci_port_info *info;
2504         struct plat_sci_port *p;
2505         int id;
2506 
2507         if (!IS_ENABLED(CONFIG_OF) || !np)
2508                 return NULL;
2509 
2510         match = of_match_node(of_sci_match, pdev->dev.of_node);
2511         if (!match)
2512                 return NULL;
2513 
2514         info = match->data;
2515 
2516         p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2517         if (!p) {
2518                 dev_err(&pdev->dev, "failed to allocate DT config data\n");
2519                 return NULL;
2520         }
2521 
2522         /* Get the line number for the aliases node. */
2523         id = of_alias_get_id(np, "serial");
2524         if (id < 0) {
2525                 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2526                 return NULL;
2527         }
2528 
2529         *dev_id = id;
2530 
2531         p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2532         p->type = info->type;
2533         p->regtype = info->regtype;
2534         p->scscr = SCSCR_RE | SCSCR_TE;
2535 
2536         return p;
2537 }
2538 
2539 static int sci_probe_single(struct platform_device *dev,
2540                                       unsigned int index,
2541                                       struct plat_sci_port *p,
2542                                       struct sci_port *sciport)
2543 {
2544         int ret;
2545 
2546         /* Sanity check */
2547         if (unlikely(index >= SCI_NPORTS)) {
2548                 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2549                            index+1, SCI_NPORTS);
2550                 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2551                 return -EINVAL;
2552         }
2553 
2554         ret = sci_init_single(dev, sciport, index, p, false);
2555         if (ret)
2556                 return ret;
2557 
2558         ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2559         if (ret) {
2560                 sci_cleanup_single(sciport);
2561                 return ret;
2562         }
2563 
2564         return 0;
2565 }
2566 
2567 static int sci_probe(struct platform_device *dev)
2568 {
2569         struct plat_sci_port *p;
2570         struct sci_port *sp;
2571         unsigned int dev_id;
2572         int ret;
2573 
2574         /*
2575          * If we've come here via earlyprintk initialization, head off to
2576          * the special early probe. We don't have sufficient device state
2577          * to make it beyond this yet.
2578          */
2579         if (is_early_platform_device(dev))
2580                 return sci_probe_earlyprintk(dev);
2581 
2582         if (dev->dev.of_node) {
2583                 p = sci_parse_dt(dev, &dev_id);
2584                 if (p == NULL)
2585                         return -EINVAL;
2586         } else {
2587                 p = dev->dev.platform_data;
2588                 if (p == NULL) {
2589                         dev_err(&dev->dev, "no platform data supplied\n");
2590                         return -EINVAL;
2591                 }
2592 
2593                 dev_id = dev->id;
2594         }
2595 
2596         sp = &sci_ports[dev_id];
2597         platform_set_drvdata(dev, sp);
2598 
2599         ret = sci_probe_single(dev, dev_id, p, sp);
2600         if (ret)
2601                 return ret;
2602 
2603         sp->freq_transition.notifier_call = sci_notifier;
2604 
2605         ret = cpufreq_register_notifier(&sp->freq_transition,
2606                                         CPUFREQ_TRANSITION_NOTIFIER);
2607         if (unlikely(ret < 0)) {
2608                 uart_remove_one_port(&sci_uart_driver, &sp->port);
2609                 sci_cleanup_single(sp);
2610                 return ret;
2611         }
2612 
2613 #ifdef CONFIG_SH_STANDARD_BIOS
2614         sh_bios_gdb_detach();
2615 #endif
2616 
2617         return 0;
2618 }
2619 
2620 static __maybe_unused int sci_suspend(struct device *dev)
2621 {
2622         struct sci_port *sport = dev_get_drvdata(dev);
2623 
2624         if (sport)
2625                 uart_suspend_port(&sci_uart_driver, &sport->port);
2626 
2627         return 0;
2628 }
2629 
2630 static __maybe_unused int sci_resume(struct device *dev)
2631 {
2632         struct sci_port *sport = dev_get_drvdata(dev);
2633 
2634         if (sport)
2635                 uart_resume_port(&sci_uart_driver, &sport->port);
2636 
2637         return 0;
2638 }
2639 
2640 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2641 
2642 static struct platform_driver sci_driver = {
2643         .probe          = sci_probe,
2644         .remove         = sci_remove,
2645         .driver         = {
2646                 .name   = "sh-sci",
2647                 .pm     = &sci_dev_pm_ops,
2648                 .of_match_table = of_match_ptr(of_sci_match),
2649         },
2650 };
2651 
2652 static int __init sci_init(void)
2653 {
2654         int ret;
2655 
2656         pr_info("%s\n", banner);
2657 
2658         ret = uart_register_driver(&sci_uart_driver);
2659         if (likely(ret == 0)) {
2660                 ret = platform_driver_register(&sci_driver);
2661                 if (unlikely(ret))
2662                         uart_unregister_driver(&sci_uart_driver);
2663         }
2664 
2665         return ret;
2666 }
2667 
2668 static void __exit sci_exit(void)
2669 {
2670         platform_driver_unregister(&sci_driver);
2671         uart_unregister_driver(&sci_uart_driver);
2672 }
2673 
2674 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2675 early_platform_init_buffer("earlyprintk", &sci_driver,
2676                            early_serial_buf, ARRAY_SIZE(early_serial_buf));
2677 #endif
2678 module_init(sci_init);
2679 module_exit(sci_exit);
2680 
2681 MODULE_LICENSE("GPL");
2682 MODULE_ALIAS("platform:sh-sci");
2683 MODULE_AUTHOR("Paul Mundt");
2684 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
2685 

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