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Linux/drivers/tty/serial/sh-sci.c

  1 /*
  2  * SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
  3  *
  4  *  Copyright (C) 2002 - 2011  Paul Mundt
  5  *  Copyright (C) 2015 Glider bvba
  6  *  Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
  7  *
  8  * based off of the old drivers/char/sh-sci.c by:
  9  *
 10  *   Copyright (C) 1999, 2000  Niibe Yutaka
 11  *   Copyright (C) 2000  Sugioka Toshinobu
 12  *   Modified to support multiple serial ports. Stuart Menefy (May 2000).
 13  *   Modified to support SecureEdge. David McCullough (2002)
 14  *   Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
 15  *   Removed SH7300 support (Jul 2007).
 16  *
 17  * This file is subject to the terms and conditions of the GNU General Public
 18  * License.  See the file "COPYING" in the main directory of this archive
 19  * for more details.
 20  */
 21 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 22 #define SUPPORT_SYSRQ
 23 #endif
 24 
 25 #undef DEBUG
 26 
 27 #include <linux/clk.h>
 28 #include <linux/console.h>
 29 #include <linux/ctype.h>
 30 #include <linux/cpufreq.h>
 31 #include <linux/delay.h>
 32 #include <linux/dmaengine.h>
 33 #include <linux/dma-mapping.h>
 34 #include <linux/err.h>
 35 #include <linux/errno.h>
 36 #include <linux/init.h>
 37 #include <linux/interrupt.h>
 38 #include <linux/ioport.h>
 39 #include <linux/major.h>
 40 #include <linux/module.h>
 41 #include <linux/mm.h>
 42 #include <linux/of.h>
 43 #include <linux/platform_device.h>
 44 #include <linux/pm_runtime.h>
 45 #include <linux/scatterlist.h>
 46 #include <linux/serial.h>
 47 #include <linux/serial_sci.h>
 48 #include <linux/sh_dma.h>
 49 #include <linux/slab.h>
 50 #include <linux/string.h>
 51 #include <linux/sysrq.h>
 52 #include <linux/timer.h>
 53 #include <linux/tty.h>
 54 #include <linux/tty_flip.h>
 55 
 56 #ifdef CONFIG_SUPERH
 57 #include <asm/sh_bios.h>
 58 #endif
 59 
 60 #include "serial_mctrl_gpio.h"
 61 #include "sh-sci.h"
 62 
 63 /* Offsets into the sci_port->irqs array */
 64 enum {
 65         SCIx_ERI_IRQ,
 66         SCIx_RXI_IRQ,
 67         SCIx_TXI_IRQ,
 68         SCIx_BRI_IRQ,
 69         SCIx_NR_IRQS,
 70 
 71         SCIx_MUX_IRQ = SCIx_NR_IRQS,    /* special case */
 72 };
 73 
 74 #define SCIx_IRQ_IS_MUXED(port)                 \
 75         ((port)->irqs[SCIx_ERI_IRQ] ==  \
 76          (port)->irqs[SCIx_RXI_IRQ]) || \
 77         ((port)->irqs[SCIx_ERI_IRQ] &&  \
 78          ((port)->irqs[SCIx_RXI_IRQ] < 0))
 79 
 80 enum SCI_CLKS {
 81         SCI_FCK,                /* Functional Clock */
 82         SCI_SCK,                /* Optional External Clock */
 83         SCI_BRG_INT,            /* Optional BRG Internal Clock Source */
 84         SCI_SCIF_CLK,           /* Optional BRG External Clock Source */
 85         SCI_NUM_CLKS
 86 };
 87 
 88 /* Bit x set means sampling rate x + 1 is supported */
 89 #define SCI_SR(x)               BIT((x) - 1)
 90 #define SCI_SR_RANGE(x, y)      GENMASK((y) - 1, (x) - 1)
 91 
 92 #define SCI_SR_SCIFAB           SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
 93                                 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
 94                                 SCI_SR(19) | SCI_SR(27)
 95 
 96 #define min_sr(_port)           ffs((_port)->sampling_rate_mask)
 97 #define max_sr(_port)           fls((_port)->sampling_rate_mask)
 98 
 99 /* Iterate over all supported sampling rates, from high to low */
100 #define for_each_sr(_sr, _port)                                         \
101         for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--)    \
102                 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
103 
104 struct sci_port {
105         struct uart_port        port;
106 
107         /* Platform configuration */
108         struct plat_sci_port    *cfg;
109         unsigned int            overrun_reg;
110         unsigned int            overrun_mask;
111         unsigned int            error_mask;
112         unsigned int            error_clear;
113         unsigned int            sampling_rate_mask;
114         resource_size_t         reg_size;
115         struct mctrl_gpios      *gpios;
116 
117         /* Break timer */
118         struct timer_list       break_timer;
119         int                     break_flag;
120 
121         /* Clocks */
122         struct clk              *clks[SCI_NUM_CLKS];
123         unsigned long           clk_rates[SCI_NUM_CLKS];
124 
125         int                     irqs[SCIx_NR_IRQS];
126         char                    *irqstr[SCIx_NR_IRQS];
127 
128         struct dma_chan                 *chan_tx;
129         struct dma_chan                 *chan_rx;
130 
131 #ifdef CONFIG_SERIAL_SH_SCI_DMA
132         dma_cookie_t                    cookie_tx;
133         dma_cookie_t                    cookie_rx[2];
134         dma_cookie_t                    active_rx;
135         dma_addr_t                      tx_dma_addr;
136         unsigned int                    tx_dma_len;
137         struct scatterlist              sg_rx[2];
138         void                            *rx_buf[2];
139         size_t                          buf_len_rx;
140         struct work_struct              work_tx;
141         struct timer_list               rx_timer;
142         unsigned int                    rx_timeout;
143 #endif
144 
145         bool autorts;
146 };
147 
148 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
149 
150 static struct sci_port sci_ports[SCI_NPORTS];
151 static struct uart_driver sci_uart_driver;
152 
153 static inline struct sci_port *
154 to_sci_port(struct uart_port *uart)
155 {
156         return container_of(uart, struct sci_port, port);
157 }
158 
159 struct plat_sci_reg {
160         u8 offset, size;
161 };
162 
163 /* Helper for invalidating specific entries of an inherited map. */
164 #define sci_reg_invalid { .offset = 0, .size = 0 }
165 
166 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
167         [SCIx_PROBE_REGTYPE] = {
168                 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
169         },
170 
171         /*
172          * Common SCI definitions, dependent on the port's regshift
173          * value.
174          */
175         [SCIx_SCI_REGTYPE] = {
176                 [SCSMR]         = { 0x00,  8 },
177                 [SCBRR]         = { 0x01,  8 },
178                 [SCSCR]         = { 0x02,  8 },
179                 [SCxTDR]        = { 0x03,  8 },
180                 [SCxSR]         = { 0x04,  8 },
181                 [SCxRDR]        = { 0x05,  8 },
182                 [SCFCR]         = sci_reg_invalid,
183                 [SCFDR]         = sci_reg_invalid,
184                 [SCTFDR]        = sci_reg_invalid,
185                 [SCRFDR]        = sci_reg_invalid,
186                 [SCSPTR]        = sci_reg_invalid,
187                 [SCLSR]         = sci_reg_invalid,
188                 [HSSRR]         = sci_reg_invalid,
189                 [SCPCR]         = sci_reg_invalid,
190                 [SCPDR]         = sci_reg_invalid,
191                 [SCDL]          = sci_reg_invalid,
192                 [SCCKS]         = sci_reg_invalid,
193         },
194 
195         /*
196          * Common definitions for legacy IrDA ports, dependent on
197          * regshift value.
198          */
199         [SCIx_IRDA_REGTYPE] = {
200                 [SCSMR]         = { 0x00,  8 },
201                 [SCBRR]         = { 0x01,  8 },
202                 [SCSCR]         = { 0x02,  8 },
203                 [SCxTDR]        = { 0x03,  8 },
204                 [SCxSR]         = { 0x04,  8 },
205                 [SCxRDR]        = { 0x05,  8 },
206                 [SCFCR]         = { 0x06,  8 },
207                 [SCFDR]         = { 0x07, 16 },
208                 [SCTFDR]        = sci_reg_invalid,
209                 [SCRFDR]        = sci_reg_invalid,
210                 [SCSPTR]        = sci_reg_invalid,
211                 [SCLSR]         = sci_reg_invalid,
212                 [HSSRR]         = sci_reg_invalid,
213                 [SCPCR]         = sci_reg_invalid,
214                 [SCPDR]         = sci_reg_invalid,
215                 [SCDL]          = sci_reg_invalid,
216                 [SCCKS]         = sci_reg_invalid,
217         },
218 
219         /*
220          * Common SCIFA definitions.
221          */
222         [SCIx_SCIFA_REGTYPE] = {
223                 [SCSMR]         = { 0x00, 16 },
224                 [SCBRR]         = { 0x04,  8 },
225                 [SCSCR]         = { 0x08, 16 },
226                 [SCxTDR]        = { 0x20,  8 },
227                 [SCxSR]         = { 0x14, 16 },
228                 [SCxRDR]        = { 0x24,  8 },
229                 [SCFCR]         = { 0x18, 16 },
230                 [SCFDR]         = { 0x1c, 16 },
231                 [SCTFDR]        = sci_reg_invalid,
232                 [SCRFDR]        = sci_reg_invalid,
233                 [SCSPTR]        = sci_reg_invalid,
234                 [SCLSR]         = sci_reg_invalid,
235                 [HSSRR]         = sci_reg_invalid,
236                 [SCPCR]         = { 0x30, 16 },
237                 [SCPDR]         = { 0x34, 16 },
238                 [SCDL]          = sci_reg_invalid,
239                 [SCCKS]         = sci_reg_invalid,
240         },
241 
242         /*
243          * Common SCIFB definitions.
244          */
245         [SCIx_SCIFB_REGTYPE] = {
246                 [SCSMR]         = { 0x00, 16 },
247                 [SCBRR]         = { 0x04,  8 },
248                 [SCSCR]         = { 0x08, 16 },
249                 [SCxTDR]        = { 0x40,  8 },
250                 [SCxSR]         = { 0x14, 16 },
251                 [SCxRDR]        = { 0x60,  8 },
252                 [SCFCR]         = { 0x18, 16 },
253                 [SCFDR]         = sci_reg_invalid,
254                 [SCTFDR]        = { 0x38, 16 },
255                 [SCRFDR]        = { 0x3c, 16 },
256                 [SCSPTR]        = sci_reg_invalid,
257                 [SCLSR]         = sci_reg_invalid,
258                 [HSSRR]         = sci_reg_invalid,
259                 [SCPCR]         = { 0x30, 16 },
260                 [SCPDR]         = { 0x34, 16 },
261                 [SCDL]          = sci_reg_invalid,
262                 [SCCKS]         = sci_reg_invalid,
263         },
264 
265         /*
266          * Common SH-2(A) SCIF definitions for ports with FIFO data
267          * count registers.
268          */
269         [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
270                 [SCSMR]         = { 0x00, 16 },
271                 [SCBRR]         = { 0x04,  8 },
272                 [SCSCR]         = { 0x08, 16 },
273                 [SCxTDR]        = { 0x0c,  8 },
274                 [SCxSR]         = { 0x10, 16 },
275                 [SCxRDR]        = { 0x14,  8 },
276                 [SCFCR]         = { 0x18, 16 },
277                 [SCFDR]         = { 0x1c, 16 },
278                 [SCTFDR]        = sci_reg_invalid,
279                 [SCRFDR]        = sci_reg_invalid,
280                 [SCSPTR]        = { 0x20, 16 },
281                 [SCLSR]         = { 0x24, 16 },
282                 [HSSRR]         = sci_reg_invalid,
283                 [SCPCR]         = sci_reg_invalid,
284                 [SCPDR]         = sci_reg_invalid,
285                 [SCDL]          = sci_reg_invalid,
286                 [SCCKS]         = sci_reg_invalid,
287         },
288 
289         /*
290          * Common SH-3 SCIF definitions.
291          */
292         [SCIx_SH3_SCIF_REGTYPE] = {
293                 [SCSMR]         = { 0x00,  8 },
294                 [SCBRR]         = { 0x02,  8 },
295                 [SCSCR]         = { 0x04,  8 },
296                 [SCxTDR]        = { 0x06,  8 },
297                 [SCxSR]         = { 0x08, 16 },
298                 [SCxRDR]        = { 0x0a,  8 },
299                 [SCFCR]         = { 0x0c,  8 },
300                 [SCFDR]         = { 0x0e, 16 },
301                 [SCTFDR]        = sci_reg_invalid,
302                 [SCRFDR]        = sci_reg_invalid,
303                 [SCSPTR]        = sci_reg_invalid,
304                 [SCLSR]         = sci_reg_invalid,
305                 [HSSRR]         = sci_reg_invalid,
306                 [SCPCR]         = sci_reg_invalid,
307                 [SCPDR]         = sci_reg_invalid,
308                 [SCDL]          = sci_reg_invalid,
309                 [SCCKS]         = sci_reg_invalid,
310         },
311 
312         /*
313          * Common SH-4(A) SCIF(B) definitions.
314          */
315         [SCIx_SH4_SCIF_REGTYPE] = {
316                 [SCSMR]         = { 0x00, 16 },
317                 [SCBRR]         = { 0x04,  8 },
318                 [SCSCR]         = { 0x08, 16 },
319                 [SCxTDR]        = { 0x0c,  8 },
320                 [SCxSR]         = { 0x10, 16 },
321                 [SCxRDR]        = { 0x14,  8 },
322                 [SCFCR]         = { 0x18, 16 },
323                 [SCFDR]         = { 0x1c, 16 },
324                 [SCTFDR]        = sci_reg_invalid,
325                 [SCRFDR]        = sci_reg_invalid,
326                 [SCSPTR]        = { 0x20, 16 },
327                 [SCLSR]         = { 0x24, 16 },
328                 [HSSRR]         = sci_reg_invalid,
329                 [SCPCR]         = sci_reg_invalid,
330                 [SCPDR]         = sci_reg_invalid,
331                 [SCDL]          = sci_reg_invalid,
332                 [SCCKS]         = sci_reg_invalid,
333         },
334 
335         /*
336          * Common SCIF definitions for ports with a Baud Rate Generator for
337          * External Clock (BRG).
338          */
339         [SCIx_SH4_SCIF_BRG_REGTYPE] = {
340                 [SCSMR]         = { 0x00, 16 },
341                 [SCBRR]         = { 0x04,  8 },
342                 [SCSCR]         = { 0x08, 16 },
343                 [SCxTDR]        = { 0x0c,  8 },
344                 [SCxSR]         = { 0x10, 16 },
345                 [SCxRDR]        = { 0x14,  8 },
346                 [SCFCR]         = { 0x18, 16 },
347                 [SCFDR]         = { 0x1c, 16 },
348                 [SCTFDR]        = sci_reg_invalid,
349                 [SCRFDR]        = sci_reg_invalid,
350                 [SCSPTR]        = { 0x20, 16 },
351                 [SCLSR]         = { 0x24, 16 },
352                 [HSSRR]         = sci_reg_invalid,
353                 [SCPCR]         = sci_reg_invalid,
354                 [SCPDR]         = sci_reg_invalid,
355                 [SCDL]          = { 0x30, 16 },
356                 [SCCKS]         = { 0x34, 16 },
357         },
358 
359         /*
360          * Common HSCIF definitions.
361          */
362         [SCIx_HSCIF_REGTYPE] = {
363                 [SCSMR]         = { 0x00, 16 },
364                 [SCBRR]         = { 0x04,  8 },
365                 [SCSCR]         = { 0x08, 16 },
366                 [SCxTDR]        = { 0x0c,  8 },
367                 [SCxSR]         = { 0x10, 16 },
368                 [SCxRDR]        = { 0x14,  8 },
369                 [SCFCR]         = { 0x18, 16 },
370                 [SCFDR]         = { 0x1c, 16 },
371                 [SCTFDR]        = sci_reg_invalid,
372                 [SCRFDR]        = sci_reg_invalid,
373                 [SCSPTR]        = { 0x20, 16 },
374                 [SCLSR]         = { 0x24, 16 },
375                 [HSSRR]         = { 0x40, 16 },
376                 [SCPCR]         = sci_reg_invalid,
377                 [SCPDR]         = sci_reg_invalid,
378                 [SCDL]          = { 0x30, 16 },
379                 [SCCKS]         = { 0x34, 16 },
380         },
381 
382         /*
383          * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
384          * register.
385          */
386         [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
387                 [SCSMR]         = { 0x00, 16 },
388                 [SCBRR]         = { 0x04,  8 },
389                 [SCSCR]         = { 0x08, 16 },
390                 [SCxTDR]        = { 0x0c,  8 },
391                 [SCxSR]         = { 0x10, 16 },
392                 [SCxRDR]        = { 0x14,  8 },
393                 [SCFCR]         = { 0x18, 16 },
394                 [SCFDR]         = { 0x1c, 16 },
395                 [SCTFDR]        = sci_reg_invalid,
396                 [SCRFDR]        = sci_reg_invalid,
397                 [SCSPTR]        = sci_reg_invalid,
398                 [SCLSR]         = { 0x24, 16 },
399                 [HSSRR]         = sci_reg_invalid,
400                 [SCPCR]         = sci_reg_invalid,
401                 [SCPDR]         = sci_reg_invalid,
402                 [SCDL]          = sci_reg_invalid,
403                 [SCCKS]         = sci_reg_invalid,
404         },
405 
406         /*
407          * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
408          * count registers.
409          */
410         [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
411                 [SCSMR]         = { 0x00, 16 },
412                 [SCBRR]         = { 0x04,  8 },
413                 [SCSCR]         = { 0x08, 16 },
414                 [SCxTDR]        = { 0x0c,  8 },
415                 [SCxSR]         = { 0x10, 16 },
416                 [SCxRDR]        = { 0x14,  8 },
417                 [SCFCR]         = { 0x18, 16 },
418                 [SCFDR]         = { 0x1c, 16 },
419                 [SCTFDR]        = { 0x1c, 16 }, /* aliased to SCFDR */
420                 [SCRFDR]        = { 0x20, 16 },
421                 [SCSPTR]        = { 0x24, 16 },
422                 [SCLSR]         = { 0x28, 16 },
423                 [HSSRR]         = sci_reg_invalid,
424                 [SCPCR]         = sci_reg_invalid,
425                 [SCPDR]         = sci_reg_invalid,
426                 [SCDL]          = sci_reg_invalid,
427                 [SCCKS]         = sci_reg_invalid,
428         },
429 
430         /*
431          * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
432          * registers.
433          */
434         [SCIx_SH7705_SCIF_REGTYPE] = {
435                 [SCSMR]         = { 0x00, 16 },
436                 [SCBRR]         = { 0x04,  8 },
437                 [SCSCR]         = { 0x08, 16 },
438                 [SCxTDR]        = { 0x20,  8 },
439                 [SCxSR]         = { 0x14, 16 },
440                 [SCxRDR]        = { 0x24,  8 },
441                 [SCFCR]         = { 0x18, 16 },
442                 [SCFDR]         = { 0x1c, 16 },
443                 [SCTFDR]        = sci_reg_invalid,
444                 [SCRFDR]        = sci_reg_invalid,
445                 [SCSPTR]        = sci_reg_invalid,
446                 [SCLSR]         = sci_reg_invalid,
447                 [HSSRR]         = sci_reg_invalid,
448                 [SCPCR]         = sci_reg_invalid,
449                 [SCPDR]         = sci_reg_invalid,
450                 [SCDL]          = sci_reg_invalid,
451                 [SCCKS]         = sci_reg_invalid,
452         },
453 };
454 
455 #define sci_getreg(up, offset)          (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
456 
457 /*
458  * The "offset" here is rather misleading, in that it refers to an enum
459  * value relative to the port mapping rather than the fixed offset
460  * itself, which needs to be manually retrieved from the platform's
461  * register map for the given port.
462  */
463 static unsigned int sci_serial_in(struct uart_port *p, int offset)
464 {
465         const struct plat_sci_reg *reg = sci_getreg(p, offset);
466 
467         if (reg->size == 8)
468                 return ioread8(p->membase + (reg->offset << p->regshift));
469         else if (reg->size == 16)
470                 return ioread16(p->membase + (reg->offset << p->regshift));
471         else
472                 WARN(1, "Invalid register access\n");
473 
474         return 0;
475 }
476 
477 static void sci_serial_out(struct uart_port *p, int offset, int value)
478 {
479         const struct plat_sci_reg *reg = sci_getreg(p, offset);
480 
481         if (reg->size == 8)
482                 iowrite8(value, p->membase + (reg->offset << p->regshift));
483         else if (reg->size == 16)
484                 iowrite16(value, p->membase + (reg->offset << p->regshift));
485         else
486                 WARN(1, "Invalid register access\n");
487 }
488 
489 static int sci_probe_regmap(struct plat_sci_port *cfg)
490 {
491         switch (cfg->type) {
492         case PORT_SCI:
493                 cfg->regtype = SCIx_SCI_REGTYPE;
494                 break;
495         case PORT_IRDA:
496                 cfg->regtype = SCIx_IRDA_REGTYPE;
497                 break;
498         case PORT_SCIFA:
499                 cfg->regtype = SCIx_SCIFA_REGTYPE;
500                 break;
501         case PORT_SCIFB:
502                 cfg->regtype = SCIx_SCIFB_REGTYPE;
503                 break;
504         case PORT_SCIF:
505                 /*
506                  * The SH-4 is a bit of a misnomer here, although that's
507                  * where this particular port layout originated. This
508                  * configuration (or some slight variation thereof)
509                  * remains the dominant model for all SCIFs.
510                  */
511                 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
512                 break;
513         case PORT_HSCIF:
514                 cfg->regtype = SCIx_HSCIF_REGTYPE;
515                 break;
516         default:
517                 pr_err("Can't probe register map for given port\n");
518                 return -EINVAL;
519         }
520 
521         return 0;
522 }
523 
524 static void sci_port_enable(struct sci_port *sci_port)
525 {
526         unsigned int i;
527 
528         if (!sci_port->port.dev)
529                 return;
530 
531         pm_runtime_get_sync(sci_port->port.dev);
532 
533         for (i = 0; i < SCI_NUM_CLKS; i++) {
534                 clk_prepare_enable(sci_port->clks[i]);
535                 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
536         }
537         sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
538 }
539 
540 static void sci_port_disable(struct sci_port *sci_port)
541 {
542         unsigned int i;
543 
544         if (!sci_port->port.dev)
545                 return;
546 
547         /* Cancel the break timer to ensure that the timer handler will not try
548          * to access the hardware with clocks and power disabled. Reset the
549          * break flag to make the break debouncing state machine ready for the
550          * next break.
551          */
552         del_timer_sync(&sci_port->break_timer);
553         sci_port->break_flag = 0;
554 
555         for (i = SCI_NUM_CLKS; i-- > 0; )
556                 clk_disable_unprepare(sci_port->clks[i]);
557 
558         pm_runtime_put_sync(sci_port->port.dev);
559 }
560 
561 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
562 {
563         /*
564          * Not all ports (such as SCIFA) will support REIE. Rather than
565          * special-casing the port type, we check the port initialization
566          * IRQ enable mask to see whether the IRQ is desired at all. If
567          * it's unset, it's logically inferred that there's no point in
568          * testing for it.
569          */
570         return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
571 }
572 
573 static void sci_start_tx(struct uart_port *port)
574 {
575         struct sci_port *s = to_sci_port(port);
576         unsigned short ctrl;
577 
578 #ifdef CONFIG_SERIAL_SH_SCI_DMA
579         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
580                 u16 new, scr = serial_port_in(port, SCSCR);
581                 if (s->chan_tx)
582                         new = scr | SCSCR_TDRQE;
583                 else
584                         new = scr & ~SCSCR_TDRQE;
585                 if (new != scr)
586                         serial_port_out(port, SCSCR, new);
587         }
588 
589         if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
590             dma_submit_error(s->cookie_tx)) {
591                 s->cookie_tx = 0;
592                 schedule_work(&s->work_tx);
593         }
594 #endif
595 
596         if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
597                 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
598                 ctrl = serial_port_in(port, SCSCR);
599                 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
600         }
601 }
602 
603 static void sci_stop_tx(struct uart_port *port)
604 {
605         unsigned short ctrl;
606 
607         /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
608         ctrl = serial_port_in(port, SCSCR);
609 
610         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
611                 ctrl &= ~SCSCR_TDRQE;
612 
613         ctrl &= ~SCSCR_TIE;
614 
615         serial_port_out(port, SCSCR, ctrl);
616 }
617 
618 static void sci_start_rx(struct uart_port *port)
619 {
620         unsigned short ctrl;
621 
622         ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
623 
624         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
625                 ctrl &= ~SCSCR_RDRQE;
626 
627         serial_port_out(port, SCSCR, ctrl);
628 }
629 
630 static void sci_stop_rx(struct uart_port *port)
631 {
632         unsigned short ctrl;
633 
634         ctrl = serial_port_in(port, SCSCR);
635 
636         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
637                 ctrl &= ~SCSCR_RDRQE;
638 
639         ctrl &= ~port_rx_irq_mask(port);
640 
641         serial_port_out(port, SCSCR, ctrl);
642 }
643 
644 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
645 {
646         if (port->type == PORT_SCI) {
647                 /* Just store the mask */
648                 serial_port_out(port, SCxSR, mask);
649         } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
650                 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
651                 /* Only clear the status bits we want to clear */
652                 serial_port_out(port, SCxSR,
653                                 serial_port_in(port, SCxSR) & mask);
654         } else {
655                 /* Store the mask, clear parity/framing errors */
656                 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
657         }
658 }
659 
660 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
661     defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
662 
663 #ifdef CONFIG_CONSOLE_POLL
664 static int sci_poll_get_char(struct uart_port *port)
665 {
666         unsigned short status;
667         int c;
668 
669         do {
670                 status = serial_port_in(port, SCxSR);
671                 if (status & SCxSR_ERRORS(port)) {
672                         sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
673                         continue;
674                 }
675                 break;
676         } while (1);
677 
678         if (!(status & SCxSR_RDxF(port)))
679                 return NO_POLL_CHAR;
680 
681         c = serial_port_in(port, SCxRDR);
682 
683         /* Dummy read */
684         serial_port_in(port, SCxSR);
685         sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
686 
687         return c;
688 }
689 #endif
690 
691 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
692 {
693         unsigned short status;
694 
695         do {
696                 status = serial_port_in(port, SCxSR);
697         } while (!(status & SCxSR_TDxE(port)));
698 
699         serial_port_out(port, SCxTDR, c);
700         sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
701 }
702 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
703           CONFIG_SERIAL_SH_SCI_EARLYCON */
704 
705 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
706 {
707         struct sci_port *s = to_sci_port(port);
708 
709         /*
710          * Use port-specific handler if provided.
711          */
712         if (s->cfg->ops && s->cfg->ops->init_pins) {
713                 s->cfg->ops->init_pins(port, cflag);
714                 return;
715         }
716 
717         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
718                 u16 ctrl = serial_port_in(port, SCPCR);
719 
720                 /* Enable RXD and TXD pin functions */
721                 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
722                 if (to_sci_port(port)->cfg->capabilities & SCIx_HAVE_RTSCTS) {
723                         /* RTS# is output, driven 1 */
724                         ctrl |= SCPCR_RTSC;
725                         serial_port_out(port, SCPDR,
726                                 serial_port_in(port, SCPDR) | SCPDR_RTSD);
727                         /* Enable CTS# pin function */
728                         ctrl &= ~SCPCR_CTSC;
729                 }
730                 serial_port_out(port, SCPCR, ctrl);
731         } else if (sci_getreg(port, SCSPTR)->size) {
732                 u16 status = serial_port_in(port, SCSPTR);
733 
734                 /* RTS# is output, driven 1 */
735                 status |= SCSPTR_RTSIO | SCSPTR_RTSDT;
736                 /* CTS# and SCK are inputs */
737                 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
738                 serial_port_out(port, SCSPTR, status);
739         }
740 }
741 
742 static int sci_txfill(struct uart_port *port)
743 {
744         const struct plat_sci_reg *reg;
745 
746         reg = sci_getreg(port, SCTFDR);
747         if (reg->size)
748                 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
749 
750         reg = sci_getreg(port, SCFDR);
751         if (reg->size)
752                 return serial_port_in(port, SCFDR) >> 8;
753 
754         return !(serial_port_in(port, SCxSR) & SCI_TDRE);
755 }
756 
757 static int sci_txroom(struct uart_port *port)
758 {
759         return port->fifosize - sci_txfill(port);
760 }
761 
762 static int sci_rxfill(struct uart_port *port)
763 {
764         const struct plat_sci_reg *reg;
765 
766         reg = sci_getreg(port, SCRFDR);
767         if (reg->size)
768                 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
769 
770         reg = sci_getreg(port, SCFDR);
771         if (reg->size)
772                 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
773 
774         return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
775 }
776 
777 /*
778  * SCI helper for checking the state of the muxed port/RXD pins.
779  */
780 static inline int sci_rxd_in(struct uart_port *port)
781 {
782         struct sci_port *s = to_sci_port(port);
783 
784         if (s->cfg->port_reg <= 0)
785                 return 1;
786 
787         /* Cast for ARM damage */
788         return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
789 }
790 
791 /* ********************************************************************** *
792  *                   the interrupt related routines                       *
793  * ********************************************************************** */
794 
795 static void sci_transmit_chars(struct uart_port *port)
796 {
797         struct circ_buf *xmit = &port->state->xmit;
798         unsigned int stopped = uart_tx_stopped(port);
799         unsigned short status;
800         unsigned short ctrl;
801         int count;
802 
803         status = serial_port_in(port, SCxSR);
804         if (!(status & SCxSR_TDxE(port))) {
805                 ctrl = serial_port_in(port, SCSCR);
806                 if (uart_circ_empty(xmit))
807                         ctrl &= ~SCSCR_TIE;
808                 else
809                         ctrl |= SCSCR_TIE;
810                 serial_port_out(port, SCSCR, ctrl);
811                 return;
812         }
813 
814         count = sci_txroom(port);
815 
816         do {
817                 unsigned char c;
818 
819                 if (port->x_char) {
820                         c = port->x_char;
821                         port->x_char = 0;
822                 } else if (!uart_circ_empty(xmit) && !stopped) {
823                         c = xmit->buf[xmit->tail];
824                         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
825                 } else {
826                         break;
827                 }
828 
829                 serial_port_out(port, SCxTDR, c);
830 
831                 port->icount.tx++;
832         } while (--count > 0);
833 
834         sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
835 
836         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
837                 uart_write_wakeup(port);
838         if (uart_circ_empty(xmit)) {
839                 sci_stop_tx(port);
840         } else {
841                 ctrl = serial_port_in(port, SCSCR);
842 
843                 if (port->type != PORT_SCI) {
844                         serial_port_in(port, SCxSR); /* Dummy read */
845                         sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
846                 }
847 
848                 ctrl |= SCSCR_TIE;
849                 serial_port_out(port, SCSCR, ctrl);
850         }
851 }
852 
853 /* On SH3, SCIF may read end-of-break as a space->mark char */
854 #define STEPFN(c)  ({int __c = (c); (((__c-1)|(__c)) == -1); })
855 
856 static void sci_receive_chars(struct uart_port *port)
857 {
858         struct sci_port *sci_port = to_sci_port(port);
859         struct tty_port *tport = &port->state->port;
860         int i, count, copied = 0;
861         unsigned short status;
862         unsigned char flag;
863 
864         status = serial_port_in(port, SCxSR);
865         if (!(status & SCxSR_RDxF(port)))
866                 return;
867 
868         while (1) {
869                 /* Don't copy more bytes than there is room for in the buffer */
870                 count = tty_buffer_request_room(tport, sci_rxfill(port));
871 
872                 /* If for any reason we can't copy more data, we're done! */
873                 if (count == 0)
874                         break;
875 
876                 if (port->type == PORT_SCI) {
877                         char c = serial_port_in(port, SCxRDR);
878                         if (uart_handle_sysrq_char(port, c) ||
879                             sci_port->break_flag)
880                                 count = 0;
881                         else
882                                 tty_insert_flip_char(tport, c, TTY_NORMAL);
883                 } else {
884                         for (i = 0; i < count; i++) {
885                                 char c = serial_port_in(port, SCxRDR);
886 
887                                 status = serial_port_in(port, SCxSR);
888 #if defined(CONFIG_CPU_SH3)
889                                 /* Skip "chars" during break */
890                                 if (sci_port->break_flag) {
891                                         if ((c == 0) &&
892                                             (status & SCxSR_FER(port))) {
893                                                 count--; i--;
894                                                 continue;
895                                         }
896 
897                                         /* Nonzero => end-of-break */
898                                         dev_dbg(port->dev, "debounce<%02x>\n", c);
899                                         sci_port->break_flag = 0;
900 
901                                         if (STEPFN(c)) {
902                                                 count--; i--;
903                                                 continue;
904                                         }
905                                 }
906 #endif /* CONFIG_CPU_SH3 */
907                                 if (uart_handle_sysrq_char(port, c)) {
908                                         count--; i--;
909                                         continue;
910                                 }
911 
912                                 /* Store data and status */
913                                 if (status & SCxSR_FER(port)) {
914                                         flag = TTY_FRAME;
915                                         port->icount.frame++;
916                                         dev_notice(port->dev, "frame error\n");
917                                 } else if (status & SCxSR_PER(port)) {
918                                         flag = TTY_PARITY;
919                                         port->icount.parity++;
920                                         dev_notice(port->dev, "parity error\n");
921                                 } else
922                                         flag = TTY_NORMAL;
923 
924                                 tty_insert_flip_char(tport, c, flag);
925                         }
926                 }
927 
928                 serial_port_in(port, SCxSR); /* dummy read */
929                 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
930 
931                 copied += count;
932                 port->icount.rx += count;
933         }
934 
935         if (copied) {
936                 /* Tell the rest of the system the news. New characters! */
937                 tty_flip_buffer_push(tport);
938         } else {
939                 serial_port_in(port, SCxSR); /* dummy read */
940                 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
941         }
942 }
943 
944 #define SCI_BREAK_JIFFIES (HZ/20)
945 
946 /*
947  * The sci generates interrupts during the break,
948  * 1 per millisecond or so during the break period, for 9600 baud.
949  * So dont bother disabling interrupts.
950  * But dont want more than 1 break event.
951  * Use a kernel timer to periodically poll the rx line until
952  * the break is finished.
953  */
954 static inline void sci_schedule_break_timer(struct sci_port *port)
955 {
956         mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
957 }
958 
959 /* Ensure that two consecutive samples find the break over. */
960 static void sci_break_timer(unsigned long data)
961 {
962         struct sci_port *port = (struct sci_port *)data;
963 
964         if (sci_rxd_in(&port->port) == 0) {
965                 port->break_flag = 1;
966                 sci_schedule_break_timer(port);
967         } else if (port->break_flag == 1) {
968                 /* break is over. */
969                 port->break_flag = 2;
970                 sci_schedule_break_timer(port);
971         } else
972                 port->break_flag = 0;
973 }
974 
975 static int sci_handle_errors(struct uart_port *port)
976 {
977         int copied = 0;
978         unsigned short status = serial_port_in(port, SCxSR);
979         struct tty_port *tport = &port->state->port;
980         struct sci_port *s = to_sci_port(port);
981 
982         /* Handle overruns */
983         if (status & s->overrun_mask) {
984                 port->icount.overrun++;
985 
986                 /* overrun error */
987                 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
988                         copied++;
989 
990                 dev_notice(port->dev, "overrun error\n");
991         }
992 
993         if (status & SCxSR_FER(port)) {
994                 if (sci_rxd_in(port) == 0) {
995                         /* Notify of BREAK */
996                         struct sci_port *sci_port = to_sci_port(port);
997 
998                         if (!sci_port->break_flag) {
999                                 port->icount.brk++;
1000 
1001                                 sci_port->break_flag = 1;
1002                                 sci_schedule_break_timer(sci_port);
1003 
1004                                 /* Do sysrq handling. */
1005                                 if (uart_handle_break(port))
1006                                         return 0;
1007 
1008                                 dev_dbg(port->dev, "BREAK detected\n");
1009 
1010                                 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1011                                         copied++;
1012                         }
1013 
1014                 } else {
1015                         /* frame error */
1016                         port->icount.frame++;
1017 
1018                         if (tty_insert_flip_char(tport, 0, TTY_FRAME))
1019                                 copied++;
1020 
1021                         dev_notice(port->dev, "frame error\n");
1022                 }
1023         }
1024 
1025         if (status & SCxSR_PER(port)) {
1026                 /* parity error */
1027                 port->icount.parity++;
1028 
1029                 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1030                         copied++;
1031 
1032                 dev_notice(port->dev, "parity error\n");
1033         }
1034 
1035         if (copied)
1036                 tty_flip_buffer_push(tport);
1037 
1038         return copied;
1039 }
1040 
1041 static int sci_handle_fifo_overrun(struct uart_port *port)
1042 {
1043         struct tty_port *tport = &port->state->port;
1044         struct sci_port *s = to_sci_port(port);
1045         const struct plat_sci_reg *reg;
1046         int copied = 0;
1047         u16 status;
1048 
1049         reg = sci_getreg(port, s->overrun_reg);
1050         if (!reg->size)
1051                 return 0;
1052 
1053         status = serial_port_in(port, s->overrun_reg);
1054         if (status & s->overrun_mask) {
1055                 status &= ~s->overrun_mask;
1056                 serial_port_out(port, s->overrun_reg, status);
1057 
1058                 port->icount.overrun++;
1059 
1060                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1061                 tty_flip_buffer_push(tport);
1062 
1063                 dev_dbg(port->dev, "overrun error\n");
1064                 copied++;
1065         }
1066 
1067         return copied;
1068 }
1069 
1070 static int sci_handle_breaks(struct uart_port *port)
1071 {
1072         int copied = 0;
1073         unsigned short status = serial_port_in(port, SCxSR);
1074         struct tty_port *tport = &port->state->port;
1075         struct sci_port *s = to_sci_port(port);
1076 
1077         if (uart_handle_break(port))
1078                 return 0;
1079 
1080         if (!s->break_flag && status & SCxSR_BRK(port)) {
1081 #if defined(CONFIG_CPU_SH3)
1082                 /* Debounce break */
1083                 s->break_flag = 1;
1084 #endif
1085 
1086                 port->icount.brk++;
1087 
1088                 /* Notify of BREAK */
1089                 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1090                         copied++;
1091 
1092                 dev_dbg(port->dev, "BREAK detected\n");
1093         }
1094 
1095         if (copied)
1096                 tty_flip_buffer_push(tport);
1097 
1098         copied += sci_handle_fifo_overrun(port);
1099 
1100         return copied;
1101 }
1102 
1103 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1104 static void sci_dma_tx_complete(void *arg)
1105 {
1106         struct sci_port *s = arg;
1107         struct uart_port *port = &s->port;
1108         struct circ_buf *xmit = &port->state->xmit;
1109         unsigned long flags;
1110 
1111         dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1112 
1113         spin_lock_irqsave(&port->lock, flags);
1114 
1115         xmit->tail += s->tx_dma_len;
1116         xmit->tail &= UART_XMIT_SIZE - 1;
1117 
1118         port->icount.tx += s->tx_dma_len;
1119 
1120         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1121                 uart_write_wakeup(port);
1122 
1123         if (!uart_circ_empty(xmit)) {
1124                 s->cookie_tx = 0;
1125                 schedule_work(&s->work_tx);
1126         } else {
1127                 s->cookie_tx = -EINVAL;
1128                 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1129                         u16 ctrl = serial_port_in(port, SCSCR);
1130                         serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1131                 }
1132         }
1133 
1134         spin_unlock_irqrestore(&port->lock, flags);
1135 }
1136 
1137 /* Locking: called with port lock held */
1138 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1139 {
1140         struct uart_port *port = &s->port;
1141         struct tty_port *tport = &port->state->port;
1142         int copied;
1143 
1144         copied = tty_insert_flip_string(tport, buf, count);
1145         if (copied < count)
1146                 port->icount.buf_overrun++;
1147 
1148         port->icount.rx += copied;
1149 
1150         return copied;
1151 }
1152 
1153 static int sci_dma_rx_find_active(struct sci_port *s)
1154 {
1155         unsigned int i;
1156 
1157         for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1158                 if (s->active_rx == s->cookie_rx[i])
1159                         return i;
1160 
1161         return -1;
1162 }
1163 
1164 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1165 {
1166         struct dma_chan *chan = s->chan_rx;
1167         struct uart_port *port = &s->port;
1168         unsigned long flags;
1169 
1170         spin_lock_irqsave(&port->lock, flags);
1171         s->chan_rx = NULL;
1172         s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1173         spin_unlock_irqrestore(&port->lock, flags);
1174         dmaengine_terminate_all(chan);
1175         dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1176                           sg_dma_address(&s->sg_rx[0]));
1177         dma_release_channel(chan);
1178         if (enable_pio)
1179                 sci_start_rx(port);
1180 }
1181 
1182 static void sci_dma_rx_complete(void *arg)
1183 {
1184         struct sci_port *s = arg;
1185         struct dma_chan *chan = s->chan_rx;
1186         struct uart_port *port = &s->port;
1187         struct dma_async_tx_descriptor *desc;
1188         unsigned long flags;
1189         int active, count = 0;
1190 
1191         dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1192                 s->active_rx);
1193 
1194         spin_lock_irqsave(&port->lock, flags);
1195 
1196         active = sci_dma_rx_find_active(s);
1197         if (active >= 0)
1198                 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1199 
1200         mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1201 
1202         if (count)
1203                 tty_flip_buffer_push(&port->state->port);
1204 
1205         desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1206                                        DMA_DEV_TO_MEM,
1207                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1208         if (!desc)
1209                 goto fail;
1210 
1211         desc->callback = sci_dma_rx_complete;
1212         desc->callback_param = s;
1213         s->cookie_rx[active] = dmaengine_submit(desc);
1214         if (dma_submit_error(s->cookie_rx[active]))
1215                 goto fail;
1216 
1217         s->active_rx = s->cookie_rx[!active];
1218 
1219         dma_async_issue_pending(chan);
1220 
1221         spin_unlock_irqrestore(&port->lock, flags);
1222         dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1223                 __func__, s->cookie_rx[active], active, s->active_rx);
1224         return;
1225 
1226 fail:
1227         spin_unlock_irqrestore(&port->lock, flags);
1228         dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1229         sci_rx_dma_release(s, true);
1230 }
1231 
1232 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1233 {
1234         struct dma_chan *chan = s->chan_tx;
1235         struct uart_port *port = &s->port;
1236         unsigned long flags;
1237 
1238         spin_lock_irqsave(&port->lock, flags);
1239         s->chan_tx = NULL;
1240         s->cookie_tx = -EINVAL;
1241         spin_unlock_irqrestore(&port->lock, flags);
1242         dmaengine_terminate_all(chan);
1243         dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1244                          DMA_TO_DEVICE);
1245         dma_release_channel(chan);
1246         if (enable_pio)
1247                 sci_start_tx(port);
1248 }
1249 
1250 static void sci_submit_rx(struct sci_port *s)
1251 {
1252         struct dma_chan *chan = s->chan_rx;
1253         int i;
1254 
1255         for (i = 0; i < 2; i++) {
1256                 struct scatterlist *sg = &s->sg_rx[i];
1257                 struct dma_async_tx_descriptor *desc;
1258 
1259                 desc = dmaengine_prep_slave_sg(chan,
1260                         sg, 1, DMA_DEV_TO_MEM,
1261                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1262                 if (!desc)
1263                         goto fail;
1264 
1265                 desc->callback = sci_dma_rx_complete;
1266                 desc->callback_param = s;
1267                 s->cookie_rx[i] = dmaengine_submit(desc);
1268                 if (dma_submit_error(s->cookie_rx[i]))
1269                         goto fail;
1270 
1271         }
1272 
1273         s->active_rx = s->cookie_rx[0];
1274 
1275         dma_async_issue_pending(chan);
1276         return;
1277 
1278 fail:
1279         if (i)
1280                 dmaengine_terminate_all(chan);
1281         for (i = 0; i < 2; i++)
1282                 s->cookie_rx[i] = -EINVAL;
1283         s->active_rx = -EINVAL;
1284         sci_rx_dma_release(s, true);
1285 }
1286 
1287 static void work_fn_tx(struct work_struct *work)
1288 {
1289         struct sci_port *s = container_of(work, struct sci_port, work_tx);
1290         struct dma_async_tx_descriptor *desc;
1291         struct dma_chan *chan = s->chan_tx;
1292         struct uart_port *port = &s->port;
1293         struct circ_buf *xmit = &port->state->xmit;
1294         dma_addr_t buf;
1295 
1296         /*
1297          * DMA is idle now.
1298          * Port xmit buffer is already mapped, and it is one page... Just adjust
1299          * offsets and lengths. Since it is a circular buffer, we have to
1300          * transmit till the end, and then the rest. Take the port lock to get a
1301          * consistent xmit buffer state.
1302          */
1303         spin_lock_irq(&port->lock);
1304         buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1305         s->tx_dma_len = min_t(unsigned int,
1306                 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1307                 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1308         spin_unlock_irq(&port->lock);
1309 
1310         desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1311                                            DMA_MEM_TO_DEV,
1312                                            DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1313         if (!desc) {
1314                 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1315                 /* switch to PIO */
1316                 sci_tx_dma_release(s, true);
1317                 return;
1318         }
1319 
1320         dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1321                                    DMA_TO_DEVICE);
1322 
1323         spin_lock_irq(&port->lock);
1324         desc->callback = sci_dma_tx_complete;
1325         desc->callback_param = s;
1326         spin_unlock_irq(&port->lock);
1327         s->cookie_tx = dmaengine_submit(desc);
1328         if (dma_submit_error(s->cookie_tx)) {
1329                 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1330                 /* switch to PIO */
1331                 sci_tx_dma_release(s, true);
1332                 return;
1333         }
1334 
1335         dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1336                 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1337 
1338         dma_async_issue_pending(chan);
1339 }
1340 
1341 static void rx_timer_fn(unsigned long arg)
1342 {
1343         struct sci_port *s = (struct sci_port *)arg;
1344         struct dma_chan *chan = s->chan_rx;
1345         struct uart_port *port = &s->port;
1346         struct dma_tx_state state;
1347         enum dma_status status;
1348         unsigned long flags;
1349         unsigned int read;
1350         int active, count;
1351         u16 scr;
1352 
1353         dev_dbg(port->dev, "DMA Rx timed out\n");
1354 
1355         spin_lock_irqsave(&port->lock, flags);
1356 
1357         active = sci_dma_rx_find_active(s);
1358         if (active < 0) {
1359                 spin_unlock_irqrestore(&port->lock, flags);
1360                 return;
1361         }
1362 
1363         status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1364         if (status == DMA_COMPLETE) {
1365                 spin_unlock_irqrestore(&port->lock, flags);
1366                 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1367                         s->active_rx, active);
1368 
1369                 /* Let packet complete handler take care of the packet */
1370                 return;
1371         }
1372 
1373         dmaengine_pause(chan);
1374 
1375         /*
1376          * sometimes DMA transfer doesn't stop even if it is stopped and
1377          * data keeps on coming until transaction is complete so check
1378          * for DMA_COMPLETE again
1379          * Let packet complete handler take care of the packet
1380          */
1381         status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1382         if (status == DMA_COMPLETE) {
1383                 spin_unlock_irqrestore(&port->lock, flags);
1384                 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1385                 return;
1386         }
1387 
1388         /* Handle incomplete DMA receive */
1389         dmaengine_terminate_all(s->chan_rx);
1390         read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1391 
1392         if (read) {
1393                 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1394                 if (count)
1395                         tty_flip_buffer_push(&port->state->port);
1396         }
1397 
1398         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1399                 sci_submit_rx(s);
1400 
1401         /* Direct new serial port interrupts back to CPU */
1402         scr = serial_port_in(port, SCSCR);
1403         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1404                 scr &= ~SCSCR_RDRQE;
1405                 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1406         }
1407         serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1408 
1409         spin_unlock_irqrestore(&port->lock, flags);
1410 }
1411 
1412 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1413                                              enum dma_transfer_direction dir,
1414                                              unsigned int id)
1415 {
1416         dma_cap_mask_t mask;
1417         struct dma_chan *chan;
1418         struct dma_slave_config cfg;
1419         int ret;
1420 
1421         dma_cap_zero(mask);
1422         dma_cap_set(DMA_SLAVE, mask);
1423 
1424         chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1425                                         (void *)(unsigned long)id, port->dev,
1426                                         dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1427         if (!chan) {
1428                 dev_warn(port->dev,
1429                          "dma_request_slave_channel_compat failed\n");
1430                 return NULL;
1431         }
1432 
1433         memset(&cfg, 0, sizeof(cfg));
1434         cfg.direction = dir;
1435         if (dir == DMA_MEM_TO_DEV) {
1436                 cfg.dst_addr = port->mapbase +
1437                         (sci_getreg(port, SCxTDR)->offset << port->regshift);
1438                 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1439         } else {
1440                 cfg.src_addr = port->mapbase +
1441                         (sci_getreg(port, SCxRDR)->offset << port->regshift);
1442                 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1443         }
1444 
1445         ret = dmaengine_slave_config(chan, &cfg);
1446         if (ret) {
1447                 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1448                 dma_release_channel(chan);
1449                 return NULL;
1450         }
1451 
1452         return chan;
1453 }
1454 
1455 static void sci_request_dma(struct uart_port *port)
1456 {
1457         struct sci_port *s = to_sci_port(port);
1458         struct dma_chan *chan;
1459 
1460         dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1461 
1462         if (!port->dev->of_node &&
1463             (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1464                 return;
1465 
1466         s->cookie_tx = -EINVAL;
1467         chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1468         dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1469         if (chan) {
1470                 s->chan_tx = chan;
1471                 /* UART circular tx buffer is an aligned page. */
1472                 s->tx_dma_addr = dma_map_single(chan->device->dev,
1473                                                 port->state->xmit.buf,
1474                                                 UART_XMIT_SIZE,
1475                                                 DMA_TO_DEVICE);
1476                 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1477                         dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1478                         dma_release_channel(chan);
1479                         s->chan_tx = NULL;
1480                 } else {
1481                         dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1482                                 __func__, UART_XMIT_SIZE,
1483                                 port->state->xmit.buf, &s->tx_dma_addr);
1484                 }
1485 
1486                 INIT_WORK(&s->work_tx, work_fn_tx);
1487         }
1488 
1489         chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1490         dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1491         if (chan) {
1492                 unsigned int i;
1493                 dma_addr_t dma;
1494                 void *buf;
1495 
1496                 s->chan_rx = chan;
1497 
1498                 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1499                 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1500                                          &dma, GFP_KERNEL);
1501                 if (!buf) {
1502                         dev_warn(port->dev,
1503                                  "Failed to allocate Rx dma buffer, using PIO\n");
1504                         dma_release_channel(chan);
1505                         s->chan_rx = NULL;
1506                         return;
1507                 }
1508 
1509                 for (i = 0; i < 2; i++) {
1510                         struct scatterlist *sg = &s->sg_rx[i];
1511 
1512                         sg_init_table(sg, 1);
1513                         s->rx_buf[i] = buf;
1514                         sg_dma_address(sg) = dma;
1515                         sg_dma_len(sg) = s->buf_len_rx;
1516 
1517                         buf += s->buf_len_rx;
1518                         dma += s->buf_len_rx;
1519                 }
1520 
1521                 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1522 
1523                 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1524                         sci_submit_rx(s);
1525         }
1526 }
1527 
1528 static void sci_free_dma(struct uart_port *port)
1529 {
1530         struct sci_port *s = to_sci_port(port);
1531 
1532         if (s->chan_tx)
1533                 sci_tx_dma_release(s, false);
1534         if (s->chan_rx)
1535                 sci_rx_dma_release(s, false);
1536 }
1537 #else
1538 static inline void sci_request_dma(struct uart_port *port)
1539 {
1540 }
1541 
1542 static inline void sci_free_dma(struct uart_port *port)
1543 {
1544 }
1545 #endif
1546 
1547 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1548 {
1549 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1550         struct uart_port *port = ptr;
1551         struct sci_port *s = to_sci_port(port);
1552 
1553         if (s->chan_rx) {
1554                 u16 scr = serial_port_in(port, SCSCR);
1555                 u16 ssr = serial_port_in(port, SCxSR);
1556 
1557                 /* Disable future Rx interrupts */
1558                 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1559                         disable_irq_nosync(irq);
1560                         scr |= SCSCR_RDRQE;
1561                 } else {
1562                         scr &= ~SCSCR_RIE;
1563                         sci_submit_rx(s);
1564                 }
1565                 serial_port_out(port, SCSCR, scr);
1566                 /* Clear current interrupt */
1567                 serial_port_out(port, SCxSR,
1568                                 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1569                 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1570                         jiffies, s->rx_timeout);
1571                 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1572 
1573                 return IRQ_HANDLED;
1574         }
1575 #endif
1576 
1577         /* I think sci_receive_chars has to be called irrespective
1578          * of whether the I_IXOFF is set, otherwise, how is the interrupt
1579          * to be disabled?
1580          */
1581         sci_receive_chars(ptr);
1582 
1583         return IRQ_HANDLED;
1584 }
1585 
1586 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1587 {
1588         struct uart_port *port = ptr;
1589         unsigned long flags;
1590 
1591         spin_lock_irqsave(&port->lock, flags);
1592         sci_transmit_chars(port);
1593         spin_unlock_irqrestore(&port->lock, flags);
1594 
1595         return IRQ_HANDLED;
1596 }
1597 
1598 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1599 {
1600         struct uart_port *port = ptr;
1601         struct sci_port *s = to_sci_port(port);
1602 
1603         /* Handle errors */
1604         if (port->type == PORT_SCI) {
1605                 if (sci_handle_errors(port)) {
1606                         /* discard character in rx buffer */
1607                         serial_port_in(port, SCxSR);
1608                         sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1609                 }
1610         } else {
1611                 sci_handle_fifo_overrun(port);
1612                 if (!s->chan_rx)
1613                         sci_receive_chars(ptr);
1614         }
1615 
1616         sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1617 
1618         /* Kick the transmission */
1619         if (!s->chan_tx)
1620                 sci_tx_interrupt(irq, ptr);
1621 
1622         return IRQ_HANDLED;
1623 }
1624 
1625 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1626 {
1627         struct uart_port *port = ptr;
1628 
1629         /* Handle BREAKs */
1630         sci_handle_breaks(port);
1631         sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1632 
1633         return IRQ_HANDLED;
1634 }
1635 
1636 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1637 {
1638         unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1639         struct uart_port *port = ptr;
1640         struct sci_port *s = to_sci_port(port);
1641         irqreturn_t ret = IRQ_NONE;
1642 
1643         ssr_status = serial_port_in(port, SCxSR);
1644         scr_status = serial_port_in(port, SCSCR);
1645         if (s->overrun_reg == SCxSR)
1646                 orer_status = ssr_status;
1647         else {
1648                 if (sci_getreg(port, s->overrun_reg)->size)
1649                         orer_status = serial_port_in(port, s->overrun_reg);
1650         }
1651 
1652         err_enabled = scr_status & port_rx_irq_mask(port);
1653 
1654         /* Tx Interrupt */
1655         if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1656             !s->chan_tx)
1657                 ret = sci_tx_interrupt(irq, ptr);
1658 
1659         /*
1660          * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1661          * DR flags
1662          */
1663         if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1664             (scr_status & SCSCR_RIE))
1665                 ret = sci_rx_interrupt(irq, ptr);
1666 
1667         /* Error Interrupt */
1668         if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1669                 ret = sci_er_interrupt(irq, ptr);
1670 
1671         /* Break Interrupt */
1672         if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1673                 ret = sci_br_interrupt(irq, ptr);
1674 
1675         /* Overrun Interrupt */
1676         if (orer_status & s->overrun_mask) {
1677                 sci_handle_fifo_overrun(port);
1678                 ret = IRQ_HANDLED;
1679         }
1680 
1681         return ret;
1682 }
1683 
1684 static const struct sci_irq_desc {
1685         const char      *desc;
1686         irq_handler_t   handler;
1687 } sci_irq_desc[] = {
1688         /*
1689          * Split out handlers, the default case.
1690          */
1691         [SCIx_ERI_IRQ] = {
1692                 .desc = "rx err",
1693                 .handler = sci_er_interrupt,
1694         },
1695 
1696         [SCIx_RXI_IRQ] = {
1697                 .desc = "rx full",
1698                 .handler = sci_rx_interrupt,
1699         },
1700 
1701         [SCIx_TXI_IRQ] = {
1702                 .desc = "tx empty",
1703                 .handler = sci_tx_interrupt,
1704         },
1705 
1706         [SCIx_BRI_IRQ] = {
1707                 .desc = "break",
1708                 .handler = sci_br_interrupt,
1709         },
1710 
1711         /*
1712          * Special muxed handler.
1713          */
1714         [SCIx_MUX_IRQ] = {
1715                 .desc = "mux",
1716                 .handler = sci_mpxed_interrupt,
1717         },
1718 };
1719 
1720 static int sci_request_irq(struct sci_port *port)
1721 {
1722         struct uart_port *up = &port->port;
1723         int i, j, ret = 0;
1724 
1725         for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1726                 const struct sci_irq_desc *desc;
1727                 int irq;
1728 
1729                 if (SCIx_IRQ_IS_MUXED(port)) {
1730                         i = SCIx_MUX_IRQ;
1731                         irq = up->irq;
1732                 } else {
1733                         irq = port->irqs[i];
1734 
1735                         /*
1736                          * Certain port types won't support all of the
1737                          * available interrupt sources.
1738                          */
1739                         if (unlikely(irq < 0))
1740                                 continue;
1741                 }
1742 
1743                 desc = sci_irq_desc + i;
1744                 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1745                                             dev_name(up->dev), desc->desc);
1746                 if (!port->irqstr[j])
1747                         goto out_nomem;
1748 
1749                 ret = request_irq(irq, desc->handler, up->irqflags,
1750                                   port->irqstr[j], port);
1751                 if (unlikely(ret)) {
1752                         dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1753                         goto out_noirq;
1754                 }
1755         }
1756 
1757         return 0;
1758 
1759 out_noirq:
1760         while (--i >= 0)
1761                 free_irq(port->irqs[i], port);
1762 
1763 out_nomem:
1764         while (--j >= 0)
1765                 kfree(port->irqstr[j]);
1766 
1767         return ret;
1768 }
1769 
1770 static void sci_free_irq(struct sci_port *port)
1771 {
1772         int i;
1773 
1774         /*
1775          * Intentionally in reverse order so we iterate over the muxed
1776          * IRQ first.
1777          */
1778         for (i = 0; i < SCIx_NR_IRQS; i++) {
1779                 int irq = port->irqs[i];
1780 
1781                 /*
1782                  * Certain port types won't support all of the available
1783                  * interrupt sources.
1784                  */
1785                 if (unlikely(irq < 0))
1786                         continue;
1787 
1788                 free_irq(port->irqs[i], port);
1789                 kfree(port->irqstr[i]);
1790 
1791                 if (SCIx_IRQ_IS_MUXED(port)) {
1792                         /* If there's only one IRQ, we're done. */
1793                         return;
1794                 }
1795         }
1796 }
1797 
1798 static unsigned int sci_tx_empty(struct uart_port *port)
1799 {
1800         unsigned short status = serial_port_in(port, SCxSR);
1801         unsigned short in_tx_fifo = sci_txfill(port);
1802 
1803         return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1804 }
1805 
1806 static void sci_set_rts(struct uart_port *port, bool state)
1807 {
1808         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1809                 u16 data = serial_port_in(port, SCPDR);
1810 
1811                 /* Active low */
1812                 if (state)
1813                         data &= ~SCPDR_RTSD;
1814                 else
1815                         data |= SCPDR_RTSD;
1816                 serial_port_out(port, SCPDR, data);
1817 
1818                 /* RTS# is output */
1819                 serial_port_out(port, SCPCR,
1820                                 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1821         } else if (sci_getreg(port, SCSPTR)->size) {
1822                 u16 ctrl = serial_port_in(port, SCSPTR);
1823 
1824                 /* Active low */
1825                 if (state)
1826                         ctrl &= ~SCSPTR_RTSDT;
1827                 else
1828                         ctrl |= SCSPTR_RTSDT;
1829                 serial_port_out(port, SCSPTR, ctrl);
1830         }
1831 }
1832 
1833 static bool sci_get_cts(struct uart_port *port)
1834 {
1835         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1836                 /* Active low */
1837                 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1838         } else if (sci_getreg(port, SCSPTR)->size) {
1839                 /* Active low */
1840                 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1841         }
1842 
1843         return true;
1844 }
1845 
1846 /*
1847  * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1848  * CTS/RTS is supported in hardware by at least one port and controlled
1849  * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1850  * handled via the ->init_pins() op, which is a bit of a one-way street,
1851  * lacking any ability to defer pin control -- this will later be
1852  * converted over to the GPIO framework).
1853  *
1854  * Other modes (such as loopback) are supported generically on certain
1855  * port types, but not others. For these it's sufficient to test for the
1856  * existence of the support register and simply ignore the port type.
1857  */
1858 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1859 {
1860         struct sci_port *s = to_sci_port(port);
1861 
1862         if (mctrl & TIOCM_LOOP) {
1863                 const struct plat_sci_reg *reg;
1864 
1865                 /*
1866                  * Standard loopback mode for SCFCR ports.
1867                  */
1868                 reg = sci_getreg(port, SCFCR);
1869                 if (reg->size)
1870                         serial_port_out(port, SCFCR,
1871                                         serial_port_in(port, SCFCR) |
1872                                         SCFCR_LOOP);
1873         }
1874 
1875         mctrl_gpio_set(s->gpios, mctrl);
1876 
1877         if (!(s->cfg->capabilities & SCIx_HAVE_RTSCTS))
1878                 return;
1879 
1880         if (!(mctrl & TIOCM_RTS)) {
1881                 /* Disable Auto RTS */
1882                 serial_port_out(port, SCFCR,
1883                                 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1884 
1885                 /* Clear RTS */
1886                 sci_set_rts(port, 0);
1887         } else if (s->autorts) {
1888                 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1889                         /* Enable RTS# pin function */
1890                         serial_port_out(port, SCPCR,
1891                                 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1892                 }
1893 
1894                 /* Enable Auto RTS */
1895                 serial_port_out(port, SCFCR,
1896                                 serial_port_in(port, SCFCR) | SCFCR_MCE);
1897         } else {
1898                 /* Set RTS */
1899                 sci_set_rts(port, 1);
1900         }
1901 }
1902 
1903 static unsigned int sci_get_mctrl(struct uart_port *port)
1904 {
1905         struct sci_port *s = to_sci_port(port);
1906         struct mctrl_gpios *gpios = s->gpios;
1907         unsigned int mctrl = 0;
1908 
1909         mctrl_gpio_get(gpios, &mctrl);
1910 
1911         /*
1912          * CTS/RTS is handled in hardware when supported, while nothing
1913          * else is wired up.
1914          */
1915         if (s->autorts) {
1916                 if (sci_get_cts(port))
1917                         mctrl |= TIOCM_CTS;
1918         } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
1919                 mctrl |= TIOCM_CTS;
1920         }
1921         if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
1922                 mctrl |= TIOCM_DSR;
1923         if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
1924                 mctrl |= TIOCM_CAR;
1925 
1926         return mctrl;
1927 }
1928 
1929 static void sci_enable_ms(struct uart_port *port)
1930 {
1931         mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1932 }
1933 
1934 static void sci_break_ctl(struct uart_port *port, int break_state)
1935 {
1936         unsigned short scscr, scsptr;
1937 
1938         /* check wheter the port has SCSPTR */
1939         if (!sci_getreg(port, SCSPTR)->size) {
1940                 /*
1941                  * Not supported by hardware. Most parts couple break and rx
1942                  * interrupts together, with break detection always enabled.
1943                  */
1944                 return;
1945         }
1946 
1947         scsptr = serial_port_in(port, SCSPTR);
1948         scscr = serial_port_in(port, SCSCR);
1949 
1950         if (break_state == -1) {
1951                 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1952                 scscr &= ~SCSCR_TE;
1953         } else {
1954                 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1955                 scscr |= SCSCR_TE;
1956         }
1957 
1958         serial_port_out(port, SCSPTR, scsptr);
1959         serial_port_out(port, SCSCR, scscr);
1960 }
1961 
1962 static int sci_startup(struct uart_port *port)
1963 {
1964         struct sci_port *s = to_sci_port(port);
1965         int ret;
1966 
1967         dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1968 
1969         ret = sci_request_irq(s);
1970         if (unlikely(ret < 0))
1971                 return ret;
1972 
1973         sci_request_dma(port);
1974 
1975         return 0;
1976 }
1977 
1978 static void sci_shutdown(struct uart_port *port)
1979 {
1980         struct sci_port *s = to_sci_port(port);
1981         unsigned long flags;
1982         u16 scr;
1983 
1984         dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1985 
1986         s->autorts = false;
1987         mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
1988 
1989         spin_lock_irqsave(&port->lock, flags);
1990         sci_stop_rx(port);
1991         sci_stop_tx(port);
1992         /* Stop RX and TX, disable related interrupts, keep clock source */
1993         scr = serial_port_in(port, SCSCR);
1994         serial_port_out(port, SCSCR, scr & (SCSCR_CKE1 | SCSCR_CKE0));
1995         spin_unlock_irqrestore(&port->lock, flags);
1996 
1997 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1998         if (s->chan_rx) {
1999                 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2000                         port->line);
2001                 del_timer_sync(&s->rx_timer);
2002         }
2003 #endif
2004 
2005         sci_free_dma(port);
2006         sci_free_irq(s);
2007 }
2008 
2009 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2010                         unsigned int *srr)
2011 {
2012         unsigned long freq = s->clk_rates[SCI_SCK];
2013         int err, min_err = INT_MAX;
2014         unsigned int sr;
2015 
2016         if (s->port.type != PORT_HSCIF)
2017                 freq *= 2;
2018 
2019         for_each_sr(sr, s) {
2020                 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2021                 if (abs(err) >= abs(min_err))
2022                         continue;
2023 
2024                 min_err = err;
2025                 *srr = sr - 1;
2026 
2027                 if (!err)
2028                         break;
2029         }
2030 
2031         dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2032                 *srr + 1);
2033         return min_err;
2034 }
2035 
2036 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2037                         unsigned long freq, unsigned int *dlr,
2038                         unsigned int *srr)
2039 {
2040         int err, min_err = INT_MAX;
2041         unsigned int sr, dl;
2042 
2043         if (s->port.type != PORT_HSCIF)
2044                 freq *= 2;
2045 
2046         for_each_sr(sr, s) {
2047                 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2048                 dl = clamp(dl, 1U, 65535U);
2049 
2050                 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2051                 if (abs(err) >= abs(min_err))
2052                         continue;
2053 
2054                 min_err = err;
2055                 *dlr = dl;
2056                 *srr = sr - 1;
2057 
2058                 if (!err)
2059                         break;
2060         }
2061 
2062         dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2063                 min_err, *dlr, *srr + 1);
2064         return min_err;
2065 }
2066 
2067 /* calculate sample rate, BRR, and clock select */
2068 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2069                           unsigned int *brr, unsigned int *srr,
2070                           unsigned int *cks)
2071 {
2072         unsigned long freq = s->clk_rates[SCI_FCK];
2073         unsigned int sr, br, prediv, scrate, c;
2074         int err, min_err = INT_MAX;
2075 
2076         if (s->port.type != PORT_HSCIF)
2077                 freq *= 2;
2078 
2079         /*
2080          * Find the combination of sample rate and clock select with the
2081          * smallest deviation from the desired baud rate.
2082          * Prefer high sample rates to maximise the receive margin.
2083          *
2084          * M: Receive margin (%)
2085          * N: Ratio of bit rate to clock (N = sampling rate)
2086          * D: Clock duty (D = 0 to 1.0)
2087          * L: Frame length (L = 9 to 12)
2088          * F: Absolute value of clock frequency deviation
2089          *
2090          *  M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2091          *      (|D - 0.5| / N * (1 + F))|
2092          *  NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2093          */
2094         for_each_sr(sr, s) {
2095                 for (c = 0; c <= 3; c++) {
2096                         /* integerized formulas from HSCIF documentation */
2097                         prediv = sr * (1 << (2 * c + 1));
2098 
2099                         /*
2100                          * We need to calculate:
2101                          *
2102                          *     br = freq / (prediv * bps) clamped to [1..256]
2103                          *     err = freq / (br * prediv) - bps
2104                          *
2105                          * Watch out for overflow when calculating the desired
2106                          * sampling clock rate!
2107                          */
2108                         if (bps > UINT_MAX / prediv)
2109                                 break;
2110 
2111                         scrate = prediv * bps;
2112                         br = DIV_ROUND_CLOSEST(freq, scrate);
2113                         br = clamp(br, 1U, 256U);
2114 
2115                         err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2116                         if (abs(err) >= abs(min_err))
2117                                 continue;
2118 
2119                         min_err = err;
2120                         *brr = br - 1;
2121                         *srr = sr - 1;
2122                         *cks = c;
2123 
2124                         if (!err)
2125                                 goto found;
2126                 }
2127         }
2128 
2129 found:
2130         dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2131                 min_err, *brr, *srr + 1, *cks);
2132         return min_err;
2133 }
2134 
2135 static void sci_reset(struct uart_port *port)
2136 {
2137         const struct plat_sci_reg *reg;
2138         unsigned int status;
2139 
2140         do {
2141                 status = serial_port_in(port, SCxSR);
2142         } while (!(status & SCxSR_TEND(port)));
2143 
2144         serial_port_out(port, SCSCR, 0x00);     /* TE=0, RE=0, CKE1=0 */
2145 
2146         reg = sci_getreg(port, SCFCR);
2147         if (reg->size)
2148                 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2149 
2150         sci_clear_SCxSR(port,
2151                         SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2152                         SCxSR_BREAK_CLEAR(port));
2153         if (sci_getreg(port, SCLSR)->size) {
2154                 status = serial_port_in(port, SCLSR);
2155                 status &= ~(SCLSR_TO | SCLSR_ORER);
2156                 serial_port_out(port, SCLSR, status);
2157         }
2158 }
2159 
2160 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2161                             struct ktermios *old)
2162 {
2163         unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i;
2164         unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2165         unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2166         struct sci_port *s = to_sci_port(port);
2167         const struct plat_sci_reg *reg;
2168         int min_err = INT_MAX, err;
2169         unsigned long max_freq = 0;
2170         int best_clk = -1;
2171 
2172         if ((termios->c_cflag & CSIZE) == CS7)
2173                 smr_val |= SCSMR_CHR;
2174         if (termios->c_cflag & PARENB)
2175                 smr_val |= SCSMR_PE;
2176         if (termios->c_cflag & PARODD)
2177                 smr_val |= SCSMR_PE | SCSMR_ODD;
2178         if (termios->c_cflag & CSTOPB)
2179                 smr_val |= SCSMR_STOP;
2180 
2181         /*
2182          * earlyprintk comes here early on with port->uartclk set to zero.
2183          * the clock framework is not up and running at this point so here
2184          * we assume that 115200 is the maximum baud rate. please note that
2185          * the baud rate is not programmed during earlyprintk - it is assumed
2186          * that the previous boot loader has enabled required clocks and
2187          * setup the baud rate generator hardware for us already.
2188          */
2189         if (!port->uartclk) {
2190                 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2191                 goto done;
2192         }
2193 
2194         for (i = 0; i < SCI_NUM_CLKS; i++)
2195                 max_freq = max(max_freq, s->clk_rates[i]);
2196 
2197         baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2198         if (!baud)
2199                 goto done;
2200 
2201         /*
2202          * There can be multiple sources for the sampling clock.  Find the one
2203          * that gives us the smallest deviation from the desired baud rate.
2204          */
2205 
2206         /* Optional Undivided External Clock */
2207         if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2208             port->type != PORT_SCIFB) {
2209                 err = sci_sck_calc(s, baud, &srr1);
2210                 if (abs(err) < abs(min_err)) {
2211                         best_clk = SCI_SCK;
2212                         scr_val = SCSCR_CKE1;
2213                         sccks = SCCKS_CKS;
2214                         min_err = err;
2215                         srr = srr1;
2216                         if (!err)
2217                                 goto done;
2218                 }
2219         }
2220 
2221         /* Optional BRG Frequency Divided External Clock */
2222         if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2223                 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2224                                    &srr1);
2225                 if (abs(err) < abs(min_err)) {
2226                         best_clk = SCI_SCIF_CLK;
2227                         scr_val = SCSCR_CKE1;
2228                         sccks = 0;
2229                         min_err = err;
2230                         dl = dl1;
2231                         srr = srr1;
2232                         if (!err)
2233                                 goto done;
2234                 }
2235         }
2236 
2237         /* Optional BRG Frequency Divided Internal Clock */
2238         if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2239                 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2240                                    &srr1);
2241                 if (abs(err) < abs(min_err)) {
2242                         best_clk = SCI_BRG_INT;
2243                         scr_val = SCSCR_CKE1;
2244                         sccks = SCCKS_XIN;
2245                         min_err = err;
2246                         dl = dl1;
2247                         srr = srr1;
2248                         if (!min_err)
2249                                 goto done;
2250                 }
2251         }
2252 
2253         /* Divided Functional Clock using standard Bit Rate Register */
2254         err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2255         if (abs(err) < abs(min_err)) {
2256                 best_clk = SCI_FCK;
2257                 scr_val = 0;
2258                 min_err = err;
2259                 brr = brr1;
2260                 srr = srr1;
2261                 cks = cks1;
2262         }
2263 
2264 done:
2265         if (best_clk >= 0)
2266                 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2267                         s->clks[best_clk], baud, min_err);
2268 
2269         sci_port_enable(s);
2270 
2271         /*
2272          * Program the optional External Baud Rate Generator (BRG) first.
2273          * It controls the mux to select (H)SCK or frequency divided clock.
2274          */
2275         if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2276                 serial_port_out(port, SCDL, dl);
2277                 serial_port_out(port, SCCKS, sccks);
2278         }
2279 
2280         sci_reset(port);
2281 
2282         uart_update_timeout(port, termios->c_cflag, baud);
2283 
2284         if (best_clk >= 0) {
2285                 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2286                         switch (srr + 1) {
2287                         case 5:  smr_val |= SCSMR_SRC_5;  break;
2288                         case 7:  smr_val |= SCSMR_SRC_7;  break;
2289                         case 11: smr_val |= SCSMR_SRC_11; break;
2290                         case 13: smr_val |= SCSMR_SRC_13; break;
2291                         case 16: smr_val |= SCSMR_SRC_16; break;
2292                         case 17: smr_val |= SCSMR_SRC_17; break;
2293                         case 19: smr_val |= SCSMR_SRC_19; break;
2294                         case 27: smr_val |= SCSMR_SRC_27; break;
2295                         }
2296                 smr_val |= cks;
2297                 dev_dbg(port->dev,
2298                          "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2299                          scr_val, smr_val, brr, sccks, dl, srr);
2300                 serial_port_out(port, SCSCR, scr_val);
2301                 serial_port_out(port, SCSMR, smr_val);
2302                 serial_port_out(port, SCBRR, brr);
2303                 if (sci_getreg(port, HSSRR)->size)
2304                         serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2305 
2306                 /* Wait one bit interval */
2307                 udelay((1000000 + (baud - 1)) / baud);
2308         } else {
2309                 /* Don't touch the bit rate configuration */
2310                 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2311                 smr_val |= serial_port_in(port, SCSMR) &
2312                            (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2313                 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2314                 serial_port_out(port, SCSCR, scr_val);
2315                 serial_port_out(port, SCSMR, smr_val);
2316         }
2317 
2318         sci_init_pins(port, termios->c_cflag);
2319 
2320         port->status &= ~UPSTAT_AUTOCTS;
2321         s->autorts = false;
2322         reg = sci_getreg(port, SCFCR);
2323         if (reg->size) {
2324                 unsigned short ctrl = serial_port_in(port, SCFCR);
2325 
2326                 if ((port->flags & UPF_HARD_FLOW) &&
2327                     (termios->c_cflag & CRTSCTS)) {
2328                         /* There is no CTS interrupt to restart the hardware */
2329                         port->status |= UPSTAT_AUTOCTS;
2330                         /* MCE is enabled when RTS is raised */
2331                         s->autorts = true;
2332                 }
2333 
2334                 /*
2335                  * As we've done a sci_reset() above, ensure we don't
2336                  * interfere with the FIFOs while toggling MCE. As the
2337                  * reset values could still be set, simply mask them out.
2338                  */
2339                 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2340 
2341                 serial_port_out(port, SCFCR, ctrl);
2342         }
2343 
2344         scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
2345         dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2346         serial_port_out(port, SCSCR, scr_val);
2347         if ((srr + 1 == 5) &&
2348             (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2349                 /*
2350                  * In asynchronous mode, when the sampling rate is 1/5, first
2351                  * received data may become invalid on some SCIFA and SCIFB.
2352                  * To avoid this problem wait more than 1 serial data time (1
2353                  * bit time x serial data number) after setting SCSCR.RE = 1.
2354                  */
2355                 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2356         }
2357 
2358 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2359         /*
2360          * Calculate delay for 2 DMA buffers (4 FIFO).
2361          * See serial_core.c::uart_update_timeout().
2362          * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2363          * function calculates 1 jiffie for the data plus 5 jiffies for the
2364          * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2365          * buffers (4 FIFO sizes), but when performing a faster transfer, the
2366          * value obtained by this formula is too small. Therefore, if the value
2367          * is smaller than 20ms, use 20ms as the timeout value for DMA.
2368          */
2369         if (s->chan_rx) {
2370                 unsigned int bits;
2371 
2372                 /* byte size and parity */
2373                 switch (termios->c_cflag & CSIZE) {
2374                 case CS5:
2375                         bits = 7;
2376                         break;
2377                 case CS6:
2378                         bits = 8;
2379                         break;
2380                 case CS7:
2381                         bits = 9;
2382                         break;
2383                 default:
2384                         bits = 10;
2385                         break;
2386                 }
2387 
2388                 if (termios->c_cflag & CSTOPB)
2389                         bits++;
2390                 if (termios->c_cflag & PARENB)
2391                         bits++;
2392                 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2393                                              (baud / 10), 10);
2394                 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2395                         s->rx_timeout * 1000 / HZ, port->timeout);
2396                 if (s->rx_timeout < msecs_to_jiffies(20))
2397                         s->rx_timeout = msecs_to_jiffies(20);
2398         }
2399 #endif
2400 
2401         if ((termios->c_cflag & CREAD) != 0)
2402                 sci_start_rx(port);
2403 
2404         sci_port_disable(s);
2405 
2406         if (UART_ENABLE_MS(port, termios->c_cflag))
2407                 sci_enable_ms(port);
2408 }
2409 
2410 static void sci_pm(struct uart_port *port, unsigned int state,
2411                    unsigned int oldstate)
2412 {
2413         struct sci_port *sci_port = to_sci_port(port);
2414 
2415         switch (state) {
2416         case UART_PM_STATE_OFF:
2417                 sci_port_disable(sci_port);
2418                 break;
2419         default:
2420                 sci_port_enable(sci_port);
2421                 break;
2422         }
2423 }
2424 
2425 static const char *sci_type(struct uart_port *port)
2426 {
2427         switch (port->type) {
2428         case PORT_IRDA:
2429                 return "irda";
2430         case PORT_SCI:
2431                 return "sci";
2432         case PORT_SCIF:
2433                 return "scif";
2434         case PORT_SCIFA:
2435                 return "scifa";
2436         case PORT_SCIFB:
2437                 return "scifb";
2438         case PORT_HSCIF:
2439                 return "hscif";
2440         }
2441 
2442         return NULL;
2443 }
2444 
2445 static int sci_remap_port(struct uart_port *port)
2446 {
2447         struct sci_port *sport = to_sci_port(port);
2448 
2449         /*
2450          * Nothing to do if there's already an established membase.
2451          */
2452         if (port->membase)
2453                 return 0;
2454 
2455         if (port->flags & UPF_IOREMAP) {
2456                 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2457                 if (unlikely(!port->membase)) {
2458                         dev_err(port->dev, "can't remap port#%d\n", port->line);
2459                         return -ENXIO;
2460                 }
2461         } else {
2462                 /*
2463                  * For the simple (and majority of) cases where we don't
2464                  * need to do any remapping, just cast the cookie
2465                  * directly.
2466                  */
2467                 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2468         }
2469 
2470         return 0;
2471 }
2472 
2473 static void sci_release_port(struct uart_port *port)
2474 {
2475         struct sci_port *sport = to_sci_port(port);
2476 
2477         if (port->flags & UPF_IOREMAP) {
2478                 iounmap(port->membase);
2479                 port->membase = NULL;
2480         }
2481 
2482         release_mem_region(port->mapbase, sport->reg_size);
2483 }
2484 
2485 static int sci_request_port(struct uart_port *port)
2486 {
2487         struct resource *res;
2488         struct sci_port *sport = to_sci_port(port);
2489         int ret;
2490 
2491         res = request_mem_region(port->mapbase, sport->reg_size,
2492                                  dev_name(port->dev));
2493         if (unlikely(res == NULL)) {
2494                 dev_err(port->dev, "request_mem_region failed.");
2495                 return -EBUSY;
2496         }
2497 
2498         ret = sci_remap_port(port);
2499         if (unlikely(ret != 0)) {
2500                 release_resource(res);
2501                 return ret;
2502         }
2503 
2504         return 0;
2505 }
2506 
2507 static void sci_config_port(struct uart_port *port, int flags)
2508 {
2509         if (flags & UART_CONFIG_TYPE) {
2510                 struct sci_port *sport = to_sci_port(port);
2511 
2512                 port->type = sport->cfg->type;
2513                 sci_request_port(port);
2514         }
2515 }
2516 
2517 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2518 {
2519         if (ser->baud_base < 2400)
2520                 /* No paper tape reader for Mitch.. */
2521                 return -EINVAL;
2522 
2523         return 0;
2524 }
2525 
2526 static const struct uart_ops sci_uart_ops = {
2527         .tx_empty       = sci_tx_empty,
2528         .set_mctrl      = sci_set_mctrl,
2529         .get_mctrl      = sci_get_mctrl,
2530         .start_tx       = sci_start_tx,
2531         .stop_tx        = sci_stop_tx,
2532         .stop_rx        = sci_stop_rx,
2533         .enable_ms      = sci_enable_ms,
2534         .break_ctl      = sci_break_ctl,
2535         .startup        = sci_startup,
2536         .shutdown       = sci_shutdown,
2537         .set_termios    = sci_set_termios,
2538         .pm             = sci_pm,
2539         .type           = sci_type,
2540         .release_port   = sci_release_port,
2541         .request_port   = sci_request_port,
2542         .config_port    = sci_config_port,
2543         .verify_port    = sci_verify_port,
2544 #ifdef CONFIG_CONSOLE_POLL
2545         .poll_get_char  = sci_poll_get_char,
2546         .poll_put_char  = sci_poll_put_char,
2547 #endif
2548 };
2549 
2550 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2551 {
2552         const char *clk_names[] = {
2553                 [SCI_FCK] = "fck",
2554                 [SCI_SCK] = "sck",
2555                 [SCI_BRG_INT] = "brg_int",
2556                 [SCI_SCIF_CLK] = "scif_clk",
2557         };
2558         struct clk *clk;
2559         unsigned int i;
2560 
2561         if (sci_port->cfg->type == PORT_HSCIF)
2562                 clk_names[SCI_SCK] = "hsck";
2563 
2564         for (i = 0; i < SCI_NUM_CLKS; i++) {
2565                 clk = devm_clk_get(dev, clk_names[i]);
2566                 if (PTR_ERR(clk) == -EPROBE_DEFER)
2567                         return -EPROBE_DEFER;
2568 
2569                 if (IS_ERR(clk) && i == SCI_FCK) {
2570                         /*
2571                          * "fck" used to be called "sci_ick", and we need to
2572                          * maintain DT backward compatibility.
2573                          */
2574                         clk = devm_clk_get(dev, "sci_ick");
2575                         if (PTR_ERR(clk) == -EPROBE_DEFER)
2576                                 return -EPROBE_DEFER;
2577 
2578                         if (!IS_ERR(clk))
2579                                 goto found;
2580 
2581                         /*
2582                          * Not all SH platforms declare a clock lookup entry
2583                          * for SCI devices, in which case we need to get the
2584                          * global "peripheral_clk" clock.
2585                          */
2586                         clk = devm_clk_get(dev, "peripheral_clk");
2587                         if (!IS_ERR(clk))
2588                                 goto found;
2589 
2590                         dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2591                                 PTR_ERR(clk));
2592                         return PTR_ERR(clk);
2593                 }
2594 
2595 found:
2596                 if (IS_ERR(clk))
2597                         dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2598                                 PTR_ERR(clk));
2599                 else
2600                         dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2601                                 clk, clk);
2602                 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2603         }
2604         return 0;
2605 }
2606 
2607 static int sci_init_single(struct platform_device *dev,
2608                            struct sci_port *sci_port, unsigned int index,
2609                            struct plat_sci_port *p, bool early)
2610 {
2611         struct uart_port *port = &sci_port->port;
2612         const struct resource *res;
2613         unsigned int i;
2614         int ret;
2615 
2616         sci_port->cfg   = p;
2617 
2618         port->ops       = &sci_uart_ops;
2619         port->iotype    = UPIO_MEM;
2620         port->line      = index;
2621 
2622         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2623         if (res == NULL)
2624                 return -ENOMEM;
2625 
2626         port->mapbase = res->start;
2627         sci_port->reg_size = resource_size(res);
2628 
2629         for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2630                 sci_port->irqs[i] = platform_get_irq(dev, i);
2631 
2632         /* The SCI generates several interrupts. They can be muxed together or
2633          * connected to different interrupt lines. In the muxed case only one
2634          * interrupt resource is specified. In the non-muxed case three or four
2635          * interrupt resources are specified, as the BRI interrupt is optional.
2636          */
2637         if (sci_port->irqs[0] < 0)
2638                 return -ENXIO;
2639 
2640         if (sci_port->irqs[1] < 0) {
2641                 sci_port->irqs[1] = sci_port->irqs[0];
2642                 sci_port->irqs[2] = sci_port->irqs[0];
2643                 sci_port->irqs[3] = sci_port->irqs[0];
2644         }
2645 
2646         if (p->regtype == SCIx_PROBE_REGTYPE) {
2647                 ret = sci_probe_regmap(p);
2648                 if (unlikely(ret))
2649                         return ret;
2650         }
2651 
2652         switch (p->type) {
2653         case PORT_SCIFB:
2654                 port->fifosize = 256;
2655                 sci_port->overrun_reg = SCxSR;
2656                 sci_port->overrun_mask = SCIFA_ORER;
2657                 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
2658                 break;
2659         case PORT_HSCIF:
2660                 port->fifosize = 128;
2661                 sci_port->overrun_reg = SCLSR;
2662                 sci_port->overrun_mask = SCLSR_ORER;
2663                 sci_port->sampling_rate_mask = SCI_SR_RANGE(8, 32);
2664                 break;
2665         case PORT_SCIFA:
2666                 port->fifosize = 64;
2667                 sci_port->overrun_reg = SCxSR;
2668                 sci_port->overrun_mask = SCIFA_ORER;
2669                 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
2670                 break;
2671         case PORT_SCIF:
2672                 port->fifosize = 16;
2673                 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2674                         sci_port->overrun_reg = SCxSR;
2675                         sci_port->overrun_mask = SCIFA_ORER;
2676                         sci_port->sampling_rate_mask = SCI_SR(16);
2677                 } else {
2678                         sci_port->overrun_reg = SCLSR;
2679                         sci_port->overrun_mask = SCLSR_ORER;
2680                         sci_port->sampling_rate_mask = SCI_SR(32);
2681                 }
2682                 break;
2683         default:
2684                 port->fifosize = 1;
2685                 sci_port->overrun_reg = SCxSR;
2686                 sci_port->overrun_mask = SCI_ORER;
2687                 sci_port->sampling_rate_mask = SCI_SR(32);
2688                 break;
2689         }
2690 
2691         /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2692          * match the SoC datasheet, this should be investigated. Let platform
2693          * data override the sampling rate for now.
2694          */
2695         if (p->sampling_rate)
2696                 sci_port->sampling_rate_mask = SCI_SR(p->sampling_rate);
2697 
2698         if (!early) {
2699                 ret = sci_init_clocks(sci_port, &dev->dev);
2700                 if (ret < 0)
2701                         return ret;
2702 
2703                 port->dev = &dev->dev;
2704 
2705                 pm_runtime_enable(&dev->dev);
2706         }
2707 
2708         sci_port->break_timer.data = (unsigned long)sci_port;
2709         sci_port->break_timer.function = sci_break_timer;
2710         init_timer(&sci_port->break_timer);
2711 
2712         /*
2713          * Establish some sensible defaults for the error detection.
2714          */
2715         if (p->type == PORT_SCI) {
2716                 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2717                 sci_port->error_clear = SCI_ERROR_CLEAR;
2718         } else {
2719                 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2720                 sci_port->error_clear = SCIF_ERROR_CLEAR;
2721         }
2722 
2723         /*
2724          * Make the error mask inclusive of overrun detection, if
2725          * supported.
2726          */
2727         if (sci_port->overrun_reg == SCxSR) {
2728                 sci_port->error_mask |= sci_port->overrun_mask;
2729                 sci_port->error_clear &= ~sci_port->overrun_mask;
2730         }
2731 
2732         port->type              = p->type;
2733         port->flags             = UPF_FIXED_PORT | p->flags;
2734         port->regshift          = p->regshift;
2735 
2736         /*
2737          * The UART port needs an IRQ value, so we peg this to the RX IRQ
2738          * for the multi-IRQ ports, which is where we are primarily
2739          * concerned with the shutdown path synchronization.
2740          *
2741          * For the muxed case there's nothing more to do.
2742          */
2743         port->irq               = sci_port->irqs[SCIx_RXI_IRQ];
2744         port->irqflags          = 0;
2745 
2746         port->serial_in         = sci_serial_in;
2747         port->serial_out        = sci_serial_out;
2748 
2749         if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2750                 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2751                         p->dma_slave_tx, p->dma_slave_rx);
2752 
2753         return 0;
2754 }
2755 
2756 static void sci_cleanup_single(struct sci_port *port)
2757 {
2758         pm_runtime_disable(port->port.dev);
2759 }
2760 
2761 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2762     defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2763 static void serial_console_putchar(struct uart_port *port, int ch)
2764 {
2765         sci_poll_put_char(port, ch);
2766 }
2767 
2768 /*
2769  *      Print a string to the serial port trying not to disturb
2770  *      any possible real use of the port...
2771  */
2772 static void serial_console_write(struct console *co, const char *s,
2773                                  unsigned count)
2774 {
2775         struct sci_port *sci_port = &sci_ports[co->index];
2776         struct uart_port *port = &sci_port->port;
2777         unsigned short bits, ctrl, ctrl_temp;
2778         unsigned long flags;
2779         int locked = 1;
2780 
2781         local_irq_save(flags);
2782 #if defined(SUPPORT_SYSRQ)
2783         if (port->sysrq)
2784                 locked = 0;
2785         else
2786 #endif
2787         if (oops_in_progress)
2788                 locked = spin_trylock(&port->lock);
2789         else
2790                 spin_lock(&port->lock);
2791 
2792         /* first save SCSCR then disable interrupts, keep clock source */
2793         ctrl = serial_port_in(port, SCSCR);
2794         ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2795                     (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2796         serial_port_out(port, SCSCR, ctrl_temp);
2797 
2798         uart_console_write(port, s, count, serial_console_putchar);
2799 
2800         /* wait until fifo is empty and last bit has been transmitted */
2801         bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2802         while ((serial_port_in(port, SCxSR) & bits) != bits)
2803                 cpu_relax();
2804 
2805         /* restore the SCSCR */
2806         serial_port_out(port, SCSCR, ctrl);
2807 
2808         if (locked)
2809                 spin_unlock(&port->lock);
2810         local_irq_restore(flags);
2811 }
2812 
2813 static int serial_console_setup(struct console *co, char *options)
2814 {
2815         struct sci_port *sci_port;
2816         struct uart_port *port;
2817         int baud = 115200;
2818         int bits = 8;
2819         int parity = 'n';
2820         int flow = 'n';
2821         int ret;
2822 
2823         /*
2824          * Refuse to handle any bogus ports.
2825          */
2826         if (co->index < 0 || co->index >= SCI_NPORTS)
2827                 return -ENODEV;
2828 
2829         sci_port = &sci_ports[co->index];
2830         port = &sci_port->port;
2831 
2832         /*
2833          * Refuse to handle uninitialized ports.
2834          */
2835         if (!port->ops)
2836                 return -ENODEV;
2837 
2838         ret = sci_remap_port(port);
2839         if (unlikely(ret != 0))
2840                 return ret;
2841 
2842         if (options)
2843                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2844 
2845         return uart_set_options(port, co, baud, parity, bits, flow);
2846 }
2847 
2848 static struct console serial_console = {
2849         .name           = "ttySC",
2850         .device         = uart_console_device,
2851         .write          = serial_console_write,
2852         .setup          = serial_console_setup,
2853         .flags          = CON_PRINTBUFFER,
2854         .index          = -1,
2855         .data           = &sci_uart_driver,
2856 };
2857 
2858 static struct console early_serial_console = {
2859         .name           = "early_ttySC",
2860         .write          = serial_console_write,
2861         .flags          = CON_PRINTBUFFER,
2862         .index          = -1,
2863 };
2864 
2865 static char early_serial_buf[32];
2866 
2867 static int sci_probe_earlyprintk(struct platform_device *pdev)
2868 {
2869         struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2870 
2871         if (early_serial_console.data)
2872                 return -EEXIST;
2873 
2874         early_serial_console.index = pdev->id;
2875 
2876         sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2877 
2878         serial_console_setup(&early_serial_console, early_serial_buf);
2879 
2880         if (!strstr(early_serial_buf, "keep"))
2881                 early_serial_console.flags |= CON_BOOT;
2882 
2883         register_console(&early_serial_console);
2884         return 0;
2885 }
2886 
2887 #define SCI_CONSOLE     (&serial_console)
2888 
2889 #else
2890 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2891 {
2892         return -EINVAL;
2893 }
2894 
2895 #define SCI_CONSOLE     NULL
2896 
2897 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
2898 
2899 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2900 
2901 static struct uart_driver sci_uart_driver = {
2902         .owner          = THIS_MODULE,
2903         .driver_name    = "sci",
2904         .dev_name       = "ttySC",
2905         .major          = SCI_MAJOR,
2906         .minor          = SCI_MINOR_START,
2907         .nr             = SCI_NPORTS,
2908         .cons           = SCI_CONSOLE,
2909 };
2910 
2911 static int sci_remove(struct platform_device *dev)
2912 {
2913         struct sci_port *port = platform_get_drvdata(dev);
2914 
2915         uart_remove_one_port(&sci_uart_driver, &port->port);
2916 
2917         sci_cleanup_single(port);
2918 
2919         return 0;
2920 }
2921 
2922 
2923 #define SCI_OF_DATA(type, regtype)      (void *)((type) << 16 | (regtype))
2924 #define SCI_OF_TYPE(data)               ((unsigned long)(data) >> 16)
2925 #define SCI_OF_REGTYPE(data)            ((unsigned long)(data) & 0xffff)
2926 
2927 static const struct of_device_id of_sci_match[] = {
2928         /* SoC-specific types */
2929         {
2930                 .compatible = "renesas,scif-r7s72100",
2931                 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2932         },
2933         /* Family-specific types */
2934         {
2935                 .compatible = "renesas,rcar-gen1-scif",
2936                 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2937         }, {
2938                 .compatible = "renesas,rcar-gen2-scif",
2939                 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2940         }, {
2941                 .compatible = "renesas,rcar-gen3-scif",
2942                 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2943         },
2944         /* Generic types */
2945         {
2946                 .compatible = "renesas,scif",
2947                 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
2948         }, {
2949                 .compatible = "renesas,scifa",
2950                 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
2951         }, {
2952                 .compatible = "renesas,scifb",
2953                 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
2954         }, {
2955                 .compatible = "renesas,hscif",
2956                 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
2957         }, {
2958                 .compatible = "renesas,sci",
2959                 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
2960         }, {
2961                 /* Terminator */
2962         },
2963 };
2964 MODULE_DEVICE_TABLE(of, of_sci_match);
2965 
2966 static struct plat_sci_port *
2967 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2968 {
2969         struct device_node *np = pdev->dev.of_node;
2970         const struct of_device_id *match;
2971         struct plat_sci_port *p;
2972         int id;
2973 
2974         if (!IS_ENABLED(CONFIG_OF) || !np)
2975                 return NULL;
2976 
2977         match = of_match_node(of_sci_match, np);
2978         if (!match)
2979                 return NULL;
2980 
2981         p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2982         if (!p)
2983                 return NULL;
2984 
2985         /* Get the line number from the aliases node. */
2986         id = of_alias_get_id(np, "serial");
2987         if (id < 0) {
2988                 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2989                 return NULL;
2990         }
2991 
2992         *dev_id = id;
2993 
2994         p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2995         p->type = SCI_OF_TYPE(match->data);
2996         p->regtype = SCI_OF_REGTYPE(match->data);
2997         p->scscr = SCSCR_RE | SCSCR_TE;
2998 
2999         if (of_find_property(np, "uart-has-rtscts", NULL))
3000                 p->capabilities |= SCIx_HAVE_RTSCTS;
3001 
3002         return p;
3003 }
3004 
3005 static int sci_probe_single(struct platform_device *dev,
3006                                       unsigned int index,
3007                                       struct plat_sci_port *p,
3008                                       struct sci_port *sciport)
3009 {
3010         int ret;
3011 
3012         /* Sanity check */
3013         if (unlikely(index >= SCI_NPORTS)) {
3014                 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3015                            index+1, SCI_NPORTS);
3016                 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3017                 return -EINVAL;
3018         }
3019 
3020         ret = sci_init_single(dev, sciport, index, p, false);
3021         if (ret)
3022                 return ret;
3023 
3024         sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3025         if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3026                 return PTR_ERR(sciport->gpios);
3027 
3028         if (p->capabilities & SCIx_HAVE_RTSCTS) {
3029                 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3030                                                         UART_GPIO_CTS)) ||
3031                     !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3032                                                         UART_GPIO_RTS))) {
3033                         dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3034                         return -EINVAL;
3035                 }
3036                 sciport->port.flags |= UPF_HARD_FLOW;
3037         }
3038 
3039         ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3040         if (ret) {
3041                 sci_cleanup_single(sciport);
3042                 return ret;
3043         }
3044 
3045         return 0;
3046 }
3047 
3048 static int sci_probe(struct platform_device *dev)
3049 {
3050         struct plat_sci_port *p;
3051         struct sci_port *sp;
3052         unsigned int dev_id;
3053         int ret;
3054 
3055         /*
3056          * If we've come here via earlyprintk initialization, head off to
3057          * the special early probe. We don't have sufficient device state
3058          * to make it beyond this yet.
3059          */
3060         if (is_early_platform_device(dev))
3061                 return sci_probe_earlyprintk(dev);
3062 
3063         if (dev->dev.of_node) {
3064                 p = sci_parse_dt(dev, &dev_id);
3065                 if (p == NULL)
3066                         return -EINVAL;
3067         } else {
3068                 p = dev->dev.platform_data;
3069                 if (p == NULL) {
3070                         dev_err(&dev->dev, "no platform data supplied\n");
3071                         return -EINVAL;
3072                 }
3073 
3074                 dev_id = dev->id;
3075         }
3076 
3077         sp = &sci_ports[dev_id];
3078         platform_set_drvdata(dev, sp);
3079 
3080         ret = sci_probe_single(dev, dev_id, p, sp);
3081         if (ret)
3082                 return ret;
3083 
3084 #ifdef CONFIG_SH_STANDARD_BIOS
3085         sh_bios_gdb_detach();
3086 #endif
3087 
3088         return 0;
3089 }
3090 
3091 static __maybe_unused int sci_suspend(struct device *dev)
3092 {
3093         struct sci_port *sport = dev_get_drvdata(dev);
3094 
3095         if (sport)
3096                 uart_suspend_port(&sci_uart_driver, &sport->port);
3097 
3098         return 0;
3099 }
3100 
3101 static __maybe_unused int sci_resume(struct device *dev)
3102 {
3103         struct sci_port *sport = dev_get_drvdata(dev);
3104 
3105         if (sport)
3106                 uart_resume_port(&sci_uart_driver, &sport->port);
3107 
3108         return 0;
3109 }
3110 
3111 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3112 
3113 static struct platform_driver sci_driver = {
3114         .probe          = sci_probe,
3115         .remove         = sci_remove,
3116         .driver         = {
3117                 .name   = "sh-sci",
3118                 .pm     = &sci_dev_pm_ops,
3119                 .of_match_table = of_match_ptr(of_sci_match),
3120         },
3121 };
3122 
3123 static int __init sci_init(void)
3124 {
3125         int ret;
3126 
3127         pr_info("%s\n", banner);
3128 
3129         ret = uart_register_driver(&sci_uart_driver);
3130         if (likely(ret == 0)) {
3131                 ret = platform_driver_register(&sci_driver);
3132                 if (unlikely(ret))
3133                         uart_unregister_driver(&sci_uart_driver);
3134         }
3135 
3136         return ret;
3137 }
3138 
3139 static void __exit sci_exit(void)
3140 {
3141         platform_driver_unregister(&sci_driver);
3142         uart_unregister_driver(&sci_uart_driver);
3143 }
3144 
3145 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3146 early_platform_init_buffer("earlyprintk", &sci_driver,
3147                            early_serial_buf, ARRAY_SIZE(early_serial_buf));
3148 #endif
3149 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3150 static struct __init plat_sci_port port_cfg;
3151 
3152 static int __init early_console_setup(struct earlycon_device *device,
3153                                       int type)
3154 {
3155         if (!device->port.membase)
3156                 return -ENODEV;
3157 
3158         device->port.serial_in = sci_serial_in;
3159         device->port.serial_out = sci_serial_out;
3160         device->port.type = type;
3161         memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3162         sci_ports[0].cfg = &port_cfg;
3163         sci_ports[0].cfg->type = type;
3164         sci_probe_regmap(sci_ports[0].cfg);
3165         port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR) |
3166                          SCSCR_RE | SCSCR_TE;
3167         sci_serial_out(&sci_ports[0].port, SCSCR, port_cfg.scscr);
3168 
3169         device->con->write = serial_console_write;
3170         return 0;
3171 }
3172 static int __init sci_early_console_setup(struct earlycon_device *device,
3173                                           const char *opt)
3174 {
3175         return early_console_setup(device, PORT_SCI);
3176 }
3177 static int __init scif_early_console_setup(struct earlycon_device *device,
3178                                           const char *opt)
3179 {
3180         return early_console_setup(device, PORT_SCIF);
3181 }
3182 static int __init scifa_early_console_setup(struct earlycon_device *device,
3183                                           const char *opt)
3184 {
3185         return early_console_setup(device, PORT_SCIFA);
3186 }
3187 static int __init scifb_early_console_setup(struct earlycon_device *device,
3188                                           const char *opt)
3189 {
3190         return early_console_setup(device, PORT_SCIFB);
3191 }
3192 static int __init hscif_early_console_setup(struct earlycon_device *device,
3193                                           const char *opt)
3194 {
3195         return early_console_setup(device, PORT_HSCIF);
3196 }
3197 
3198 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3199 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3200 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3201 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3202 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3203 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3204 
3205 module_init(sci_init);
3206 module_exit(sci_exit);
3207 
3208 MODULE_LICENSE("GPL");
3209 MODULE_ALIAS("platform:sh-sci");
3210 MODULE_AUTHOR("Paul Mundt");
3211 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
3212 

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