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Linux/drivers/tty/serial/sh-sci.c

  1 /*
  2  * SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
  3  *
  4  *  Copyright (C) 2002 - 2011  Paul Mundt
  5  *  Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
  6  *
  7  * based off of the old drivers/char/sh-sci.c by:
  8  *
  9  *   Copyright (C) 1999, 2000  Niibe Yutaka
 10  *   Copyright (C) 2000  Sugioka Toshinobu
 11  *   Modified to support multiple serial ports. Stuart Menefy (May 2000).
 12  *   Modified to support SecureEdge. David McCullough (2002)
 13  *   Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
 14  *   Removed SH7300 support (Jul 2007).
 15  *
 16  * This file is subject to the terms and conditions of the GNU General Public
 17  * License.  See the file "COPYING" in the main directory of this archive
 18  * for more details.
 19  */
 20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 21 #define SUPPORT_SYSRQ
 22 #endif
 23 
 24 #undef DEBUG
 25 
 26 #include <linux/clk.h>
 27 #include <linux/console.h>
 28 #include <linux/ctype.h>
 29 #include <linux/cpufreq.h>
 30 #include <linux/delay.h>
 31 #include <linux/dmaengine.h>
 32 #include <linux/dma-mapping.h>
 33 #include <linux/err.h>
 34 #include <linux/errno.h>
 35 #include <linux/init.h>
 36 #include <linux/interrupt.h>
 37 #include <linux/ioport.h>
 38 #include <linux/major.h>
 39 #include <linux/module.h>
 40 #include <linux/mm.h>
 41 #include <linux/notifier.h>
 42 #include <linux/of.h>
 43 #include <linux/platform_device.h>
 44 #include <linux/pm_runtime.h>
 45 #include <linux/scatterlist.h>
 46 #include <linux/serial.h>
 47 #include <linux/serial_sci.h>
 48 #include <linux/sh_dma.h>
 49 #include <linux/slab.h>
 50 #include <linux/string.h>
 51 #include <linux/sysrq.h>
 52 #include <linux/timer.h>
 53 #include <linux/tty.h>
 54 #include <linux/tty_flip.h>
 55 
 56 #ifdef CONFIG_SUPERH
 57 #include <asm/sh_bios.h>
 58 #endif
 59 
 60 #include "sh-sci.h"
 61 
 62 /* Offsets into the sci_port->irqs array */
 63 enum {
 64         SCIx_ERI_IRQ,
 65         SCIx_RXI_IRQ,
 66         SCIx_TXI_IRQ,
 67         SCIx_BRI_IRQ,
 68         SCIx_NR_IRQS,
 69 
 70         SCIx_MUX_IRQ = SCIx_NR_IRQS,    /* special case */
 71 };
 72 
 73 #define SCIx_IRQ_IS_MUXED(port)                 \
 74         ((port)->irqs[SCIx_ERI_IRQ] ==  \
 75          (port)->irqs[SCIx_RXI_IRQ]) || \
 76         ((port)->irqs[SCIx_ERI_IRQ] &&  \
 77          ((port)->irqs[SCIx_RXI_IRQ] < 0))
 78 
 79 struct sci_port {
 80         struct uart_port        port;
 81 
 82         /* Platform configuration */
 83         struct plat_sci_port    *cfg;
 84         int                     overrun_bit;
 85         unsigned int            error_mask;
 86         unsigned int            sampling_rate;
 87 
 88 
 89         /* Break timer */
 90         struct timer_list       break_timer;
 91         int                     break_flag;
 92 
 93         /* Interface clock */
 94         struct clk              *iclk;
 95         /* Function clock */
 96         struct clk              *fclk;
 97 
 98         int                     irqs[SCIx_NR_IRQS];
 99         char                    *irqstr[SCIx_NR_IRQS];
100 
101         struct dma_chan                 *chan_tx;
102         struct dma_chan                 *chan_rx;
103 
104 #ifdef CONFIG_SERIAL_SH_SCI_DMA
105         struct dma_async_tx_descriptor  *desc_tx;
106         struct dma_async_tx_descriptor  *desc_rx[2];
107         dma_cookie_t                    cookie_tx;
108         dma_cookie_t                    cookie_rx[2];
109         dma_cookie_t                    active_rx;
110         struct scatterlist              sg_tx;
111         unsigned int                    sg_len_tx;
112         struct scatterlist              sg_rx[2];
113         size_t                          buf_len_rx;
114         struct sh_dmae_slave            param_tx;
115         struct sh_dmae_slave            param_rx;
116         struct work_struct              work_tx;
117         struct work_struct              work_rx;
118         struct timer_list               rx_timer;
119         unsigned int                    rx_timeout;
120 #endif
121 
122         struct notifier_block           freq_transition;
123 };
124 
125 /* Function prototypes */
126 static void sci_start_tx(struct uart_port *port);
127 static void sci_stop_tx(struct uart_port *port);
128 static void sci_start_rx(struct uart_port *port);
129 
130 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
131 
132 static struct sci_port sci_ports[SCI_NPORTS];
133 static struct uart_driver sci_uart_driver;
134 
135 static inline struct sci_port *
136 to_sci_port(struct uart_port *uart)
137 {
138         return container_of(uart, struct sci_port, port);
139 }
140 
141 struct plat_sci_reg {
142         u8 offset, size;
143 };
144 
145 /* Helper for invalidating specific entries of an inherited map. */
146 #define sci_reg_invalid { .offset = 0, .size = 0 }
147 
148 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
149         [SCIx_PROBE_REGTYPE] = {
150                 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
151         },
152 
153         /*
154          * Common SCI definitions, dependent on the port's regshift
155          * value.
156          */
157         [SCIx_SCI_REGTYPE] = {
158                 [SCSMR]         = { 0x00,  8 },
159                 [SCBRR]         = { 0x01,  8 },
160                 [SCSCR]         = { 0x02,  8 },
161                 [SCxTDR]        = { 0x03,  8 },
162                 [SCxSR]         = { 0x04,  8 },
163                 [SCxRDR]        = { 0x05,  8 },
164                 [SCFCR]         = sci_reg_invalid,
165                 [SCFDR]         = sci_reg_invalid,
166                 [SCTFDR]        = sci_reg_invalid,
167                 [SCRFDR]        = sci_reg_invalid,
168                 [SCSPTR]        = sci_reg_invalid,
169                 [SCLSR]         = sci_reg_invalid,
170                 [HSSRR]         = sci_reg_invalid,
171         },
172 
173         /*
174          * Common definitions for legacy IrDA ports, dependent on
175          * regshift value.
176          */
177         [SCIx_IRDA_REGTYPE] = {
178                 [SCSMR]         = { 0x00,  8 },
179                 [SCBRR]         = { 0x01,  8 },
180                 [SCSCR]         = { 0x02,  8 },
181                 [SCxTDR]        = { 0x03,  8 },
182                 [SCxSR]         = { 0x04,  8 },
183                 [SCxRDR]        = { 0x05,  8 },
184                 [SCFCR]         = { 0x06,  8 },
185                 [SCFDR]         = { 0x07, 16 },
186                 [SCTFDR]        = sci_reg_invalid,
187                 [SCRFDR]        = sci_reg_invalid,
188                 [SCSPTR]        = sci_reg_invalid,
189                 [SCLSR]         = sci_reg_invalid,
190                 [HSSRR]         = sci_reg_invalid,
191         },
192 
193         /*
194          * Common SCIFA definitions.
195          */
196         [SCIx_SCIFA_REGTYPE] = {
197                 [SCSMR]         = { 0x00, 16 },
198                 [SCBRR]         = { 0x04,  8 },
199                 [SCSCR]         = { 0x08, 16 },
200                 [SCxTDR]        = { 0x20,  8 },
201                 [SCxSR]         = { 0x14, 16 },
202                 [SCxRDR]        = { 0x24,  8 },
203                 [SCFCR]         = { 0x18, 16 },
204                 [SCFDR]         = { 0x1c, 16 },
205                 [SCTFDR]        = sci_reg_invalid,
206                 [SCRFDR]        = sci_reg_invalid,
207                 [SCSPTR]        = sci_reg_invalid,
208                 [SCLSR]         = sci_reg_invalid,
209                 [HSSRR]         = sci_reg_invalid,
210         },
211 
212         /*
213          * Common SCIFB definitions.
214          */
215         [SCIx_SCIFB_REGTYPE] = {
216                 [SCSMR]         = { 0x00, 16 },
217                 [SCBRR]         = { 0x04,  8 },
218                 [SCSCR]         = { 0x08, 16 },
219                 [SCxTDR]        = { 0x40,  8 },
220                 [SCxSR]         = { 0x14, 16 },
221                 [SCxRDR]        = { 0x60,  8 },
222                 [SCFCR]         = { 0x18, 16 },
223                 [SCFDR]         = sci_reg_invalid,
224                 [SCTFDR]        = { 0x38, 16 },
225                 [SCRFDR]        = { 0x3c, 16 },
226                 [SCSPTR]        = sci_reg_invalid,
227                 [SCLSR]         = sci_reg_invalid,
228                 [HSSRR]         = sci_reg_invalid,
229         },
230 
231         /*
232          * Common SH-2(A) SCIF definitions for ports with FIFO data
233          * count registers.
234          */
235         [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
236                 [SCSMR]         = { 0x00, 16 },
237                 [SCBRR]         = { 0x04,  8 },
238                 [SCSCR]         = { 0x08, 16 },
239                 [SCxTDR]        = { 0x0c,  8 },
240                 [SCxSR]         = { 0x10, 16 },
241                 [SCxRDR]        = { 0x14,  8 },
242                 [SCFCR]         = { 0x18, 16 },
243                 [SCFDR]         = { 0x1c, 16 },
244                 [SCTFDR]        = sci_reg_invalid,
245                 [SCRFDR]        = sci_reg_invalid,
246                 [SCSPTR]        = { 0x20, 16 },
247                 [SCLSR]         = { 0x24, 16 },
248                 [HSSRR]         = sci_reg_invalid,
249         },
250 
251         /*
252          * Common SH-3 SCIF definitions.
253          */
254         [SCIx_SH3_SCIF_REGTYPE] = {
255                 [SCSMR]         = { 0x00,  8 },
256                 [SCBRR]         = { 0x02,  8 },
257                 [SCSCR]         = { 0x04,  8 },
258                 [SCxTDR]        = { 0x06,  8 },
259                 [SCxSR]         = { 0x08, 16 },
260                 [SCxRDR]        = { 0x0a,  8 },
261                 [SCFCR]         = { 0x0c,  8 },
262                 [SCFDR]         = { 0x0e, 16 },
263                 [SCTFDR]        = sci_reg_invalid,
264                 [SCRFDR]        = sci_reg_invalid,
265                 [SCSPTR]        = sci_reg_invalid,
266                 [SCLSR]         = sci_reg_invalid,
267                 [HSSRR]         = sci_reg_invalid,
268         },
269 
270         /*
271          * Common SH-4(A) SCIF(B) definitions.
272          */
273         [SCIx_SH4_SCIF_REGTYPE] = {
274                 [SCSMR]         = { 0x00, 16 },
275                 [SCBRR]         = { 0x04,  8 },
276                 [SCSCR]         = { 0x08, 16 },
277                 [SCxTDR]        = { 0x0c,  8 },
278                 [SCxSR]         = { 0x10, 16 },
279                 [SCxRDR]        = { 0x14,  8 },
280                 [SCFCR]         = { 0x18, 16 },
281                 [SCFDR]         = { 0x1c, 16 },
282                 [SCTFDR]        = sci_reg_invalid,
283                 [SCRFDR]        = sci_reg_invalid,
284                 [SCSPTR]        = { 0x20, 16 },
285                 [SCLSR]         = { 0x24, 16 },
286                 [HSSRR]         = sci_reg_invalid,
287         },
288 
289         /*
290          * Common HSCIF definitions.
291          */
292         [SCIx_HSCIF_REGTYPE] = {
293                 [SCSMR]         = { 0x00, 16 },
294                 [SCBRR]         = { 0x04,  8 },
295                 [SCSCR]         = { 0x08, 16 },
296                 [SCxTDR]        = { 0x0c,  8 },
297                 [SCxSR]         = { 0x10, 16 },
298                 [SCxRDR]        = { 0x14,  8 },
299                 [SCFCR]         = { 0x18, 16 },
300                 [SCFDR]         = { 0x1c, 16 },
301                 [SCTFDR]        = sci_reg_invalid,
302                 [SCRFDR]        = sci_reg_invalid,
303                 [SCSPTR]        = { 0x20, 16 },
304                 [SCLSR]         = { 0x24, 16 },
305                 [HSSRR]         = { 0x40, 16 },
306         },
307 
308         /*
309          * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
310          * register.
311          */
312         [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
313                 [SCSMR]         = { 0x00, 16 },
314                 [SCBRR]         = { 0x04,  8 },
315                 [SCSCR]         = { 0x08, 16 },
316                 [SCxTDR]        = { 0x0c,  8 },
317                 [SCxSR]         = { 0x10, 16 },
318                 [SCxRDR]        = { 0x14,  8 },
319                 [SCFCR]         = { 0x18, 16 },
320                 [SCFDR]         = { 0x1c, 16 },
321                 [SCTFDR]        = sci_reg_invalid,
322                 [SCRFDR]        = sci_reg_invalid,
323                 [SCSPTR]        = sci_reg_invalid,
324                 [SCLSR]         = { 0x24, 16 },
325                 [HSSRR]         = sci_reg_invalid,
326         },
327 
328         /*
329          * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
330          * count registers.
331          */
332         [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
333                 [SCSMR]         = { 0x00, 16 },
334                 [SCBRR]         = { 0x04,  8 },
335                 [SCSCR]         = { 0x08, 16 },
336                 [SCxTDR]        = { 0x0c,  8 },
337                 [SCxSR]         = { 0x10, 16 },
338                 [SCxRDR]        = { 0x14,  8 },
339                 [SCFCR]         = { 0x18, 16 },
340                 [SCFDR]         = { 0x1c, 16 },
341                 [SCTFDR]        = { 0x1c, 16 }, /* aliased to SCFDR */
342                 [SCRFDR]        = { 0x20, 16 },
343                 [SCSPTR]        = { 0x24, 16 },
344                 [SCLSR]         = { 0x28, 16 },
345                 [HSSRR]         = sci_reg_invalid,
346         },
347 
348         /*
349          * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
350          * registers.
351          */
352         [SCIx_SH7705_SCIF_REGTYPE] = {
353                 [SCSMR]         = { 0x00, 16 },
354                 [SCBRR]         = { 0x04,  8 },
355                 [SCSCR]         = { 0x08, 16 },
356                 [SCxTDR]        = { 0x20,  8 },
357                 [SCxSR]         = { 0x14, 16 },
358                 [SCxRDR]        = { 0x24,  8 },
359                 [SCFCR]         = { 0x18, 16 },
360                 [SCFDR]         = { 0x1c, 16 },
361                 [SCTFDR]        = sci_reg_invalid,
362                 [SCRFDR]        = sci_reg_invalid,
363                 [SCSPTR]        = sci_reg_invalid,
364                 [SCLSR]         = sci_reg_invalid,
365                 [HSSRR]         = sci_reg_invalid,
366         },
367 };
368 
369 #define sci_getreg(up, offset)          (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
370 
371 /*
372  * The "offset" here is rather misleading, in that it refers to an enum
373  * value relative to the port mapping rather than the fixed offset
374  * itself, which needs to be manually retrieved from the platform's
375  * register map for the given port.
376  */
377 static unsigned int sci_serial_in(struct uart_port *p, int offset)
378 {
379         struct plat_sci_reg *reg = sci_getreg(p, offset);
380 
381         if (reg->size == 8)
382                 return ioread8(p->membase + (reg->offset << p->regshift));
383         else if (reg->size == 16)
384                 return ioread16(p->membase + (reg->offset << p->regshift));
385         else
386                 WARN(1, "Invalid register access\n");
387 
388         return 0;
389 }
390 
391 static void sci_serial_out(struct uart_port *p, int offset, int value)
392 {
393         struct plat_sci_reg *reg = sci_getreg(p, offset);
394 
395         if (reg->size == 8)
396                 iowrite8(value, p->membase + (reg->offset << p->regshift));
397         else if (reg->size == 16)
398                 iowrite16(value, p->membase + (reg->offset << p->regshift));
399         else
400                 WARN(1, "Invalid register access\n");
401 }
402 
403 static int sci_probe_regmap(struct plat_sci_port *cfg)
404 {
405         switch (cfg->type) {
406         case PORT_SCI:
407                 cfg->regtype = SCIx_SCI_REGTYPE;
408                 break;
409         case PORT_IRDA:
410                 cfg->regtype = SCIx_IRDA_REGTYPE;
411                 break;
412         case PORT_SCIFA:
413                 cfg->regtype = SCIx_SCIFA_REGTYPE;
414                 break;
415         case PORT_SCIFB:
416                 cfg->regtype = SCIx_SCIFB_REGTYPE;
417                 break;
418         case PORT_SCIF:
419                 /*
420                  * The SH-4 is a bit of a misnomer here, although that's
421                  * where this particular port layout originated. This
422                  * configuration (or some slight variation thereof)
423                  * remains the dominant model for all SCIFs.
424                  */
425                 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
426                 break;
427         case PORT_HSCIF:
428                 cfg->regtype = SCIx_HSCIF_REGTYPE;
429                 break;
430         default:
431                 pr_err("Can't probe register map for given port\n");
432                 return -EINVAL;
433         }
434 
435         return 0;
436 }
437 
438 static void sci_port_enable(struct sci_port *sci_port)
439 {
440         if (!sci_port->port.dev)
441                 return;
442 
443         pm_runtime_get_sync(sci_port->port.dev);
444 
445         clk_prepare_enable(sci_port->iclk);
446         sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
447         clk_prepare_enable(sci_port->fclk);
448 }
449 
450 static void sci_port_disable(struct sci_port *sci_port)
451 {
452         if (!sci_port->port.dev)
453                 return;
454 
455         /* Cancel the break timer to ensure that the timer handler will not try
456          * to access the hardware with clocks and power disabled. Reset the
457          * break flag to make the break debouncing state machine ready for the
458          * next break.
459          */
460         del_timer_sync(&sci_port->break_timer);
461         sci_port->break_flag = 0;
462 
463         clk_disable_unprepare(sci_port->fclk);
464         clk_disable_unprepare(sci_port->iclk);
465 
466         pm_runtime_put_sync(sci_port->port.dev);
467 }
468 
469 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
470 
471 #ifdef CONFIG_CONSOLE_POLL
472 static int sci_poll_get_char(struct uart_port *port)
473 {
474         unsigned short status;
475         int c;
476 
477         do {
478                 status = serial_port_in(port, SCxSR);
479                 if (status & SCxSR_ERRORS(port)) {
480                         serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
481                         continue;
482                 }
483                 break;
484         } while (1);
485 
486         if (!(status & SCxSR_RDxF(port)))
487                 return NO_POLL_CHAR;
488 
489         c = serial_port_in(port, SCxRDR);
490 
491         /* Dummy read */
492         serial_port_in(port, SCxSR);
493         serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
494 
495         return c;
496 }
497 #endif
498 
499 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
500 {
501         unsigned short status;
502 
503         do {
504                 status = serial_port_in(port, SCxSR);
505         } while (!(status & SCxSR_TDxE(port)));
506 
507         serial_port_out(port, SCxTDR, c);
508         serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
509 }
510 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
511 
512 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
513 {
514         struct sci_port *s = to_sci_port(port);
515         struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
516 
517         /*
518          * Use port-specific handler if provided.
519          */
520         if (s->cfg->ops && s->cfg->ops->init_pins) {
521                 s->cfg->ops->init_pins(port, cflag);
522                 return;
523         }
524 
525         /*
526          * For the generic path SCSPTR is necessary. Bail out if that's
527          * unavailable, too.
528          */
529         if (!reg->size)
530                 return;
531 
532         if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
533             ((!(cflag & CRTSCTS)))) {
534                 unsigned short status;
535 
536                 status = serial_port_in(port, SCSPTR);
537                 status &= ~SCSPTR_CTSIO;
538                 status |= SCSPTR_RTSIO;
539                 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
540         }
541 }
542 
543 static int sci_txfill(struct uart_port *port)
544 {
545         struct plat_sci_reg *reg;
546 
547         reg = sci_getreg(port, SCTFDR);
548         if (reg->size)
549                 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
550 
551         reg = sci_getreg(port, SCFDR);
552         if (reg->size)
553                 return serial_port_in(port, SCFDR) >> 8;
554 
555         return !(serial_port_in(port, SCxSR) & SCI_TDRE);
556 }
557 
558 static int sci_txroom(struct uart_port *port)
559 {
560         return port->fifosize - sci_txfill(port);
561 }
562 
563 static int sci_rxfill(struct uart_port *port)
564 {
565         struct plat_sci_reg *reg;
566 
567         reg = sci_getreg(port, SCRFDR);
568         if (reg->size)
569                 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
570 
571         reg = sci_getreg(port, SCFDR);
572         if (reg->size)
573                 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
574 
575         return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
576 }
577 
578 /*
579  * SCI helper for checking the state of the muxed port/RXD pins.
580  */
581 static inline int sci_rxd_in(struct uart_port *port)
582 {
583         struct sci_port *s = to_sci_port(port);
584 
585         if (s->cfg->port_reg <= 0)
586                 return 1;
587 
588         /* Cast for ARM damage */
589         return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
590 }
591 
592 /* ********************************************************************** *
593  *                   the interrupt related routines                       *
594  * ********************************************************************** */
595 
596 static void sci_transmit_chars(struct uart_port *port)
597 {
598         struct circ_buf *xmit = &port->state->xmit;
599         unsigned int stopped = uart_tx_stopped(port);
600         unsigned short status;
601         unsigned short ctrl;
602         int count;
603 
604         status = serial_port_in(port, SCxSR);
605         if (!(status & SCxSR_TDxE(port))) {
606                 ctrl = serial_port_in(port, SCSCR);
607                 if (uart_circ_empty(xmit))
608                         ctrl &= ~SCSCR_TIE;
609                 else
610                         ctrl |= SCSCR_TIE;
611                 serial_port_out(port, SCSCR, ctrl);
612                 return;
613         }
614 
615         count = sci_txroom(port);
616 
617         do {
618                 unsigned char c;
619 
620                 if (port->x_char) {
621                         c = port->x_char;
622                         port->x_char = 0;
623                 } else if (!uart_circ_empty(xmit) && !stopped) {
624                         c = xmit->buf[xmit->tail];
625                         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
626                 } else {
627                         break;
628                 }
629 
630                 serial_port_out(port, SCxTDR, c);
631 
632                 port->icount.tx++;
633         } while (--count > 0);
634 
635         serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
636 
637         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
638                 uart_write_wakeup(port);
639         if (uart_circ_empty(xmit)) {
640                 sci_stop_tx(port);
641         } else {
642                 ctrl = serial_port_in(port, SCSCR);
643 
644                 if (port->type != PORT_SCI) {
645                         serial_port_in(port, SCxSR); /* Dummy read */
646                         serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
647                 }
648 
649                 ctrl |= SCSCR_TIE;
650                 serial_port_out(port, SCSCR, ctrl);
651         }
652 }
653 
654 /* On SH3, SCIF may read end-of-break as a space->mark char */
655 #define STEPFN(c)  ({int __c = (c); (((__c-1)|(__c)) == -1); })
656 
657 static void sci_receive_chars(struct uart_port *port)
658 {
659         struct sci_port *sci_port = to_sci_port(port);
660         struct tty_port *tport = &port->state->port;
661         int i, count, copied = 0;
662         unsigned short status;
663         unsigned char flag;
664 
665         status = serial_port_in(port, SCxSR);
666         if (!(status & SCxSR_RDxF(port)))
667                 return;
668 
669         while (1) {
670                 /* Don't copy more bytes than there is room for in the buffer */
671                 count = tty_buffer_request_room(tport, sci_rxfill(port));
672 
673                 /* If for any reason we can't copy more data, we're done! */
674                 if (count == 0)
675                         break;
676 
677                 if (port->type == PORT_SCI) {
678                         char c = serial_port_in(port, SCxRDR);
679                         if (uart_handle_sysrq_char(port, c) ||
680                             sci_port->break_flag)
681                                 count = 0;
682                         else
683                                 tty_insert_flip_char(tport, c, TTY_NORMAL);
684                 } else {
685                         for (i = 0; i < count; i++) {
686                                 char c = serial_port_in(port, SCxRDR);
687 
688                                 status = serial_port_in(port, SCxSR);
689 #if defined(CONFIG_CPU_SH3)
690                                 /* Skip "chars" during break */
691                                 if (sci_port->break_flag) {
692                                         if ((c == 0) &&
693                                             (status & SCxSR_FER(port))) {
694                                                 count--; i--;
695                                                 continue;
696                                         }
697 
698                                         /* Nonzero => end-of-break */
699                                         dev_dbg(port->dev, "debounce<%02x>\n", c);
700                                         sci_port->break_flag = 0;
701 
702                                         if (STEPFN(c)) {
703                                                 count--; i--;
704                                                 continue;
705                                         }
706                                 }
707 #endif /* CONFIG_CPU_SH3 */
708                                 if (uart_handle_sysrq_char(port, c)) {
709                                         count--; i--;
710                                         continue;
711                                 }
712 
713                                 /* Store data and status */
714                                 if (status & SCxSR_FER(port)) {
715                                         flag = TTY_FRAME;
716                                         port->icount.frame++;
717                                         dev_notice(port->dev, "frame error\n");
718                                 } else if (status & SCxSR_PER(port)) {
719                                         flag = TTY_PARITY;
720                                         port->icount.parity++;
721                                         dev_notice(port->dev, "parity error\n");
722                                 } else
723                                         flag = TTY_NORMAL;
724 
725                                 tty_insert_flip_char(tport, c, flag);
726                         }
727                 }
728 
729                 serial_port_in(port, SCxSR); /* dummy read */
730                 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
731 
732                 copied += count;
733                 port->icount.rx += count;
734         }
735 
736         if (copied) {
737                 /* Tell the rest of the system the news. New characters! */
738                 tty_flip_buffer_push(tport);
739         } else {
740                 serial_port_in(port, SCxSR); /* dummy read */
741                 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
742         }
743 }
744 
745 #define SCI_BREAK_JIFFIES (HZ/20)
746 
747 /*
748  * The sci generates interrupts during the break,
749  * 1 per millisecond or so during the break period, for 9600 baud.
750  * So dont bother disabling interrupts.
751  * But dont want more than 1 break event.
752  * Use a kernel timer to periodically poll the rx line until
753  * the break is finished.
754  */
755 static inline void sci_schedule_break_timer(struct sci_port *port)
756 {
757         mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
758 }
759 
760 /* Ensure that two consecutive samples find the break over. */
761 static void sci_break_timer(unsigned long data)
762 {
763         struct sci_port *port = (struct sci_port *)data;
764 
765         if (sci_rxd_in(&port->port) == 0) {
766                 port->break_flag = 1;
767                 sci_schedule_break_timer(port);
768         } else if (port->break_flag == 1) {
769                 /* break is over. */
770                 port->break_flag = 2;
771                 sci_schedule_break_timer(port);
772         } else
773                 port->break_flag = 0;
774 }
775 
776 static int sci_handle_errors(struct uart_port *port)
777 {
778         int copied = 0;
779         unsigned short status = serial_port_in(port, SCxSR);
780         struct tty_port *tport = &port->state->port;
781         struct sci_port *s = to_sci_port(port);
782 
783         /* Handle overruns */
784         if (status & (1 << s->overrun_bit)) {
785                 port->icount.overrun++;
786 
787                 /* overrun error */
788                 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
789                         copied++;
790 
791                 dev_notice(port->dev, "overrun error\n");
792         }
793 
794         if (status & SCxSR_FER(port)) {
795                 if (sci_rxd_in(port) == 0) {
796                         /* Notify of BREAK */
797                         struct sci_port *sci_port = to_sci_port(port);
798 
799                         if (!sci_port->break_flag) {
800                                 port->icount.brk++;
801 
802                                 sci_port->break_flag = 1;
803                                 sci_schedule_break_timer(sci_port);
804 
805                                 /* Do sysrq handling. */
806                                 if (uart_handle_break(port))
807                                         return 0;
808 
809                                 dev_dbg(port->dev, "BREAK detected\n");
810 
811                                 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
812                                         copied++;
813                         }
814 
815                 } else {
816                         /* frame error */
817                         port->icount.frame++;
818 
819                         if (tty_insert_flip_char(tport, 0, TTY_FRAME))
820                                 copied++;
821 
822                         dev_notice(port->dev, "frame error\n");
823                 }
824         }
825 
826         if (status & SCxSR_PER(port)) {
827                 /* parity error */
828                 port->icount.parity++;
829 
830                 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
831                         copied++;
832 
833                 dev_notice(port->dev, "parity error\n");
834         }
835 
836         if (copied)
837                 tty_flip_buffer_push(tport);
838 
839         return copied;
840 }
841 
842 static int sci_handle_fifo_overrun(struct uart_port *port)
843 {
844         struct tty_port *tport = &port->state->port;
845         struct sci_port *s = to_sci_port(port);
846         struct plat_sci_reg *reg;
847         int copied = 0, offset;
848         u16 status, bit;
849 
850         switch (port->type) {
851         case PORT_SCIF:
852         case PORT_HSCIF:
853                 offset = SCLSR;
854                 break;
855         case PORT_SCIFA:
856         case PORT_SCIFB:
857                 offset = SCxSR;
858                 break;
859         default:
860                 return 0;
861         }
862 
863         reg = sci_getreg(port, offset);
864         if (!reg->size)
865                 return 0;
866 
867         status = serial_port_in(port, offset);
868         bit = 1 << s->overrun_bit;
869 
870         if (status & bit) {
871                 status &= ~bit;
872                 serial_port_out(port, offset, status);
873 
874                 port->icount.overrun++;
875 
876                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
877                 tty_flip_buffer_push(tport);
878 
879                 dev_dbg(port->dev, "overrun error\n");
880                 copied++;
881         }
882 
883         return copied;
884 }
885 
886 static int sci_handle_breaks(struct uart_port *port)
887 {
888         int copied = 0;
889         unsigned short status = serial_port_in(port, SCxSR);
890         struct tty_port *tport = &port->state->port;
891         struct sci_port *s = to_sci_port(port);
892 
893         if (uart_handle_break(port))
894                 return 0;
895 
896         if (!s->break_flag && status & SCxSR_BRK(port)) {
897 #if defined(CONFIG_CPU_SH3)
898                 /* Debounce break */
899                 s->break_flag = 1;
900 #endif
901 
902                 port->icount.brk++;
903 
904                 /* Notify of BREAK */
905                 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
906                         copied++;
907 
908                 dev_dbg(port->dev, "BREAK detected\n");
909         }
910 
911         if (copied)
912                 tty_flip_buffer_push(tport);
913 
914         copied += sci_handle_fifo_overrun(port);
915 
916         return copied;
917 }
918 
919 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
920 {
921 #ifdef CONFIG_SERIAL_SH_SCI_DMA
922         struct uart_port *port = ptr;
923         struct sci_port *s = to_sci_port(port);
924 
925         if (s->chan_rx) {
926                 u16 scr = serial_port_in(port, SCSCR);
927                 u16 ssr = serial_port_in(port, SCxSR);
928 
929                 /* Disable future Rx interrupts */
930                 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
931                         disable_irq_nosync(irq);
932                         scr |= SCSCR_RDRQE;
933                 } else {
934                         scr &= ~SCSCR_RIE;
935                 }
936                 serial_port_out(port, SCSCR, scr);
937                 /* Clear current interrupt */
938                 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
939                 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
940                         jiffies, s->rx_timeout);
941                 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
942 
943                 return IRQ_HANDLED;
944         }
945 #endif
946 
947         /* I think sci_receive_chars has to be called irrespective
948          * of whether the I_IXOFF is set, otherwise, how is the interrupt
949          * to be disabled?
950          */
951         sci_receive_chars(ptr);
952 
953         return IRQ_HANDLED;
954 }
955 
956 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
957 {
958         struct uart_port *port = ptr;
959         unsigned long flags;
960 
961         spin_lock_irqsave(&port->lock, flags);
962         sci_transmit_chars(port);
963         spin_unlock_irqrestore(&port->lock, flags);
964 
965         return IRQ_HANDLED;
966 }
967 
968 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
969 {
970         struct uart_port *port = ptr;
971 
972         /* Handle errors */
973         if (port->type == PORT_SCI) {
974                 if (sci_handle_errors(port)) {
975                         /* discard character in rx buffer */
976                         serial_port_in(port, SCxSR);
977                         serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
978                 }
979         } else {
980                 sci_handle_fifo_overrun(port);
981                 sci_rx_interrupt(irq, ptr);
982         }
983 
984         serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
985 
986         /* Kick the transmission */
987         sci_tx_interrupt(irq, ptr);
988 
989         return IRQ_HANDLED;
990 }
991 
992 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
993 {
994         struct uart_port *port = ptr;
995 
996         /* Handle BREAKs */
997         sci_handle_breaks(port);
998         serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
999 
1000         return IRQ_HANDLED;
1001 }
1002 
1003 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
1004 {
1005         /*
1006          * Not all ports (such as SCIFA) will support REIE. Rather than
1007          * special-casing the port type, we check the port initialization
1008          * IRQ enable mask to see whether the IRQ is desired at all. If
1009          * it's unset, it's logically inferred that there's no point in
1010          * testing for it.
1011          */
1012         return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
1013 }
1014 
1015 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1016 {
1017         unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1018         struct uart_port *port = ptr;
1019         struct sci_port *s = to_sci_port(port);
1020         irqreturn_t ret = IRQ_NONE;
1021 
1022         ssr_status = serial_port_in(port, SCxSR);
1023         scr_status = serial_port_in(port, SCSCR);
1024         switch (port->type) {
1025         case PORT_SCIF:
1026         case PORT_HSCIF:
1027                 orer_status = serial_port_in(port, SCLSR);
1028                 break;
1029         case PORT_SCIFA:
1030         case PORT_SCIFB:
1031                 orer_status = ssr_status;
1032                 break;
1033         }
1034 
1035         err_enabled = scr_status & port_rx_irq_mask(port);
1036 
1037         /* Tx Interrupt */
1038         if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1039             !s->chan_tx)
1040                 ret = sci_tx_interrupt(irq, ptr);
1041 
1042         /*
1043          * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1044          * DR flags
1045          */
1046         if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1047             (scr_status & SCSCR_RIE)) {
1048                 if (port->type == PORT_SCIF || port->type == PORT_HSCIF)
1049                         sci_handle_fifo_overrun(port);
1050                 ret = sci_rx_interrupt(irq, ptr);
1051         }
1052 
1053         /* Error Interrupt */
1054         if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1055                 ret = sci_er_interrupt(irq, ptr);
1056 
1057         /* Break Interrupt */
1058         if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1059                 ret = sci_br_interrupt(irq, ptr);
1060 
1061         /* Overrun Interrupt */
1062         if (orer_status & (1 << s->overrun_bit))
1063                 sci_handle_fifo_overrun(port);
1064 
1065         return ret;
1066 }
1067 
1068 /*
1069  * Here we define a transition notifier so that we can update all of our
1070  * ports' baud rate when the peripheral clock changes.
1071  */
1072 static int sci_notifier(struct notifier_block *self,
1073                         unsigned long phase, void *p)
1074 {
1075         struct sci_port *sci_port;
1076         unsigned long flags;
1077 
1078         sci_port = container_of(self, struct sci_port, freq_transition);
1079 
1080         if (phase == CPUFREQ_POSTCHANGE) {
1081                 struct uart_port *port = &sci_port->port;
1082 
1083                 spin_lock_irqsave(&port->lock, flags);
1084                 port->uartclk = clk_get_rate(sci_port->iclk);
1085                 spin_unlock_irqrestore(&port->lock, flags);
1086         }
1087 
1088         return NOTIFY_OK;
1089 }
1090 
1091 static struct sci_irq_desc {
1092         const char      *desc;
1093         irq_handler_t   handler;
1094 } sci_irq_desc[] = {
1095         /*
1096          * Split out handlers, the default case.
1097          */
1098         [SCIx_ERI_IRQ] = {
1099                 .desc = "rx err",
1100                 .handler = sci_er_interrupt,
1101         },
1102 
1103         [SCIx_RXI_IRQ] = {
1104                 .desc = "rx full",
1105                 .handler = sci_rx_interrupt,
1106         },
1107 
1108         [SCIx_TXI_IRQ] = {
1109                 .desc = "tx empty",
1110                 .handler = sci_tx_interrupt,
1111         },
1112 
1113         [SCIx_BRI_IRQ] = {
1114                 .desc = "break",
1115                 .handler = sci_br_interrupt,
1116         },
1117 
1118         /*
1119          * Special muxed handler.
1120          */
1121         [SCIx_MUX_IRQ] = {
1122                 .desc = "mux",
1123                 .handler = sci_mpxed_interrupt,
1124         },
1125 };
1126 
1127 static int sci_request_irq(struct sci_port *port)
1128 {
1129         struct uart_port *up = &port->port;
1130         int i, j, ret = 0;
1131 
1132         for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1133                 struct sci_irq_desc *desc;
1134                 int irq;
1135 
1136                 if (SCIx_IRQ_IS_MUXED(port)) {
1137                         i = SCIx_MUX_IRQ;
1138                         irq = up->irq;
1139                 } else {
1140                         irq = port->irqs[i];
1141 
1142                         /*
1143                          * Certain port types won't support all of the
1144                          * available interrupt sources.
1145                          */
1146                         if (unlikely(irq < 0))
1147                                 continue;
1148                 }
1149 
1150                 desc = sci_irq_desc + i;
1151                 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1152                                             dev_name(up->dev), desc->desc);
1153                 if (!port->irqstr[j]) {
1154                         dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1155                                 desc->desc);
1156                         goto out_nomem;
1157                 }
1158 
1159                 ret = request_irq(irq, desc->handler, up->irqflags,
1160                                   port->irqstr[j], port);
1161                 if (unlikely(ret)) {
1162                         dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1163                         goto out_noirq;
1164                 }
1165         }
1166 
1167         return 0;
1168 
1169 out_noirq:
1170         while (--i >= 0)
1171                 free_irq(port->irqs[i], port);
1172 
1173 out_nomem:
1174         while (--j >= 0)
1175                 kfree(port->irqstr[j]);
1176 
1177         return ret;
1178 }
1179 
1180 static void sci_free_irq(struct sci_port *port)
1181 {
1182         int i;
1183 
1184         /*
1185          * Intentionally in reverse order so we iterate over the muxed
1186          * IRQ first.
1187          */
1188         for (i = 0; i < SCIx_NR_IRQS; i++) {
1189                 int irq = port->irqs[i];
1190 
1191                 /*
1192                  * Certain port types won't support all of the available
1193                  * interrupt sources.
1194                  */
1195                 if (unlikely(irq < 0))
1196                         continue;
1197 
1198                 free_irq(port->irqs[i], port);
1199                 kfree(port->irqstr[i]);
1200 
1201                 if (SCIx_IRQ_IS_MUXED(port)) {
1202                         /* If there's only one IRQ, we're done. */
1203                         return;
1204                 }
1205         }
1206 }
1207 
1208 static unsigned int sci_tx_empty(struct uart_port *port)
1209 {
1210         unsigned short status = serial_port_in(port, SCxSR);
1211         unsigned short in_tx_fifo = sci_txfill(port);
1212 
1213         return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1214 }
1215 
1216 /*
1217  * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1218  * CTS/RTS is supported in hardware by at least one port and controlled
1219  * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1220  * handled via the ->init_pins() op, which is a bit of a one-way street,
1221  * lacking any ability to defer pin control -- this will later be
1222  * converted over to the GPIO framework).
1223  *
1224  * Other modes (such as loopback) are supported generically on certain
1225  * port types, but not others. For these it's sufficient to test for the
1226  * existence of the support register and simply ignore the port type.
1227  */
1228 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1229 {
1230         if (mctrl & TIOCM_LOOP) {
1231                 struct plat_sci_reg *reg;
1232 
1233                 /*
1234                  * Standard loopback mode for SCFCR ports.
1235                  */
1236                 reg = sci_getreg(port, SCFCR);
1237                 if (reg->size)
1238                         serial_port_out(port, SCFCR,
1239                                         serial_port_in(port, SCFCR) |
1240                                         SCFCR_LOOP);
1241         }
1242 }
1243 
1244 static unsigned int sci_get_mctrl(struct uart_port *port)
1245 {
1246         /*
1247          * CTS/RTS is handled in hardware when supported, while nothing
1248          * else is wired up. Keep it simple and simply assert DSR/CAR.
1249          */
1250         return TIOCM_DSR | TIOCM_CAR;
1251 }
1252 
1253 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1254 static void sci_dma_tx_complete(void *arg)
1255 {
1256         struct sci_port *s = arg;
1257         struct uart_port *port = &s->port;
1258         struct circ_buf *xmit = &port->state->xmit;
1259         unsigned long flags;
1260 
1261         dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1262 
1263         spin_lock_irqsave(&port->lock, flags);
1264 
1265         xmit->tail += sg_dma_len(&s->sg_tx);
1266         xmit->tail &= UART_XMIT_SIZE - 1;
1267 
1268         port->icount.tx += sg_dma_len(&s->sg_tx);
1269 
1270         async_tx_ack(s->desc_tx);
1271         s->desc_tx = NULL;
1272 
1273         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1274                 uart_write_wakeup(port);
1275 
1276         if (!uart_circ_empty(xmit)) {
1277                 s->cookie_tx = 0;
1278                 schedule_work(&s->work_tx);
1279         } else {
1280                 s->cookie_tx = -EINVAL;
1281                 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1282                         u16 ctrl = serial_port_in(port, SCSCR);
1283                         serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1284                 }
1285         }
1286 
1287         spin_unlock_irqrestore(&port->lock, flags);
1288 }
1289 
1290 /* Locking: called with port lock held */
1291 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1292 {
1293         struct uart_port *port = &s->port;
1294         struct tty_port *tport = &port->state->port;
1295         int i, active, room;
1296 
1297         room = tty_buffer_request_room(tport, count);
1298 
1299         if (s->active_rx == s->cookie_rx[0]) {
1300                 active = 0;
1301         } else if (s->active_rx == s->cookie_rx[1]) {
1302                 active = 1;
1303         } else {
1304                 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1305                 return 0;
1306         }
1307 
1308         if (room < count)
1309                 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1310                          count - room);
1311         if (!room)
1312                 return room;
1313 
1314         for (i = 0; i < room; i++)
1315                 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1316                                      TTY_NORMAL);
1317 
1318         port->icount.rx += room;
1319 
1320         return room;
1321 }
1322 
1323 static void sci_dma_rx_complete(void *arg)
1324 {
1325         struct sci_port *s = arg;
1326         struct uart_port *port = &s->port;
1327         unsigned long flags;
1328         int count;
1329 
1330         dev_dbg(port->dev, "%s(%d) active #%d\n",
1331                 __func__, port->line, s->active_rx);
1332 
1333         spin_lock_irqsave(&port->lock, flags);
1334 
1335         count = sci_dma_rx_push(s, s->buf_len_rx);
1336 
1337         mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1338 
1339         spin_unlock_irqrestore(&port->lock, flags);
1340 
1341         if (count)
1342                 tty_flip_buffer_push(&port->state->port);
1343 
1344         schedule_work(&s->work_rx);
1345 }
1346 
1347 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1348 {
1349         struct dma_chan *chan = s->chan_rx;
1350         struct uart_port *port = &s->port;
1351 
1352         s->chan_rx = NULL;
1353         s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1354         dma_release_channel(chan);
1355         if (sg_dma_address(&s->sg_rx[0]))
1356                 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1357                                   sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1358         if (enable_pio)
1359                 sci_start_rx(port);
1360 }
1361 
1362 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1363 {
1364         struct dma_chan *chan = s->chan_tx;
1365         struct uart_port *port = &s->port;
1366 
1367         s->chan_tx = NULL;
1368         s->cookie_tx = -EINVAL;
1369         dma_release_channel(chan);
1370         if (enable_pio)
1371                 sci_start_tx(port);
1372 }
1373 
1374 static void sci_submit_rx(struct sci_port *s)
1375 {
1376         struct dma_chan *chan = s->chan_rx;
1377         int i;
1378 
1379         for (i = 0; i < 2; i++) {
1380                 struct scatterlist *sg = &s->sg_rx[i];
1381                 struct dma_async_tx_descriptor *desc;
1382 
1383                 desc = dmaengine_prep_slave_sg(chan,
1384                         sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1385 
1386                 if (desc) {
1387                         s->desc_rx[i] = desc;
1388                         desc->callback = sci_dma_rx_complete;
1389                         desc->callback_param = s;
1390                         s->cookie_rx[i] = desc->tx_submit(desc);
1391                 }
1392 
1393                 if (!desc || s->cookie_rx[i] < 0) {
1394                         if (i) {
1395                                 async_tx_ack(s->desc_rx[0]);
1396                                 s->cookie_rx[0] = -EINVAL;
1397                         }
1398                         if (desc) {
1399                                 async_tx_ack(desc);
1400                                 s->cookie_rx[i] = -EINVAL;
1401                         }
1402                         dev_warn(s->port.dev,
1403                                  "failed to re-start DMA, using PIO\n");
1404                         sci_rx_dma_release(s, true);
1405                         return;
1406                 }
1407                 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n",
1408                         __func__, s->cookie_rx[i], i);
1409         }
1410 
1411         s->active_rx = s->cookie_rx[0];
1412 
1413         dma_async_issue_pending(chan);
1414 }
1415 
1416 static void work_fn_rx(struct work_struct *work)
1417 {
1418         struct sci_port *s = container_of(work, struct sci_port, work_rx);
1419         struct uart_port *port = &s->port;
1420         struct dma_async_tx_descriptor *desc;
1421         int new;
1422 
1423         if (s->active_rx == s->cookie_rx[0]) {
1424                 new = 0;
1425         } else if (s->active_rx == s->cookie_rx[1]) {
1426                 new = 1;
1427         } else {
1428                 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1429                 return;
1430         }
1431         desc = s->desc_rx[new];
1432 
1433         if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1434             DMA_COMPLETE) {
1435                 /* Handle incomplete DMA receive */
1436                 struct dma_chan *chan = s->chan_rx;
1437                 struct shdma_desc *sh_desc = container_of(desc,
1438                                         struct shdma_desc, async_tx);
1439                 unsigned long flags;
1440                 int count;
1441 
1442                 dmaengine_terminate_all(chan);
1443                 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
1444                         sh_desc->partial, sh_desc->cookie);
1445 
1446                 spin_lock_irqsave(&port->lock, flags);
1447                 count = sci_dma_rx_push(s, sh_desc->partial);
1448                 spin_unlock_irqrestore(&port->lock, flags);
1449 
1450                 if (count)
1451                         tty_flip_buffer_push(&port->state->port);
1452 
1453                 sci_submit_rx(s);
1454 
1455                 return;
1456         }
1457 
1458         s->cookie_rx[new] = desc->tx_submit(desc);
1459         if (s->cookie_rx[new] < 0) {
1460                 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1461                 sci_rx_dma_release(s, true);
1462                 return;
1463         }
1464 
1465         s->active_rx = s->cookie_rx[!new];
1466 
1467         dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n",
1468                 __func__, s->cookie_rx[new], new, s->active_rx);
1469 }
1470 
1471 static void work_fn_tx(struct work_struct *work)
1472 {
1473         struct sci_port *s = container_of(work, struct sci_port, work_tx);
1474         struct dma_async_tx_descriptor *desc;
1475         struct dma_chan *chan = s->chan_tx;
1476         struct uart_port *port = &s->port;
1477         struct circ_buf *xmit = &port->state->xmit;
1478         struct scatterlist *sg = &s->sg_tx;
1479 
1480         /*
1481          * DMA is idle now.
1482          * Port xmit buffer is already mapped, and it is one page... Just adjust
1483          * offsets and lengths. Since it is a circular buffer, we have to
1484          * transmit till the end, and then the rest. Take the port lock to get a
1485          * consistent xmit buffer state.
1486          */
1487         spin_lock_irq(&port->lock);
1488         sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1489         sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1490                 sg->offset;
1491         sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1492                 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1493         spin_unlock_irq(&port->lock);
1494 
1495         BUG_ON(!sg_dma_len(sg));
1496 
1497         desc = dmaengine_prep_slave_sg(chan,
1498                         sg, s->sg_len_tx, DMA_MEM_TO_DEV,
1499                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1500         if (!desc) {
1501                 /* switch to PIO */
1502                 sci_tx_dma_release(s, true);
1503                 return;
1504         }
1505 
1506         dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1507 
1508         spin_lock_irq(&port->lock);
1509         s->desc_tx = desc;
1510         desc->callback = sci_dma_tx_complete;
1511         desc->callback_param = s;
1512         spin_unlock_irq(&port->lock);
1513         s->cookie_tx = desc->tx_submit(desc);
1514         if (s->cookie_tx < 0) {
1515                 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1516                 /* switch to PIO */
1517                 sci_tx_dma_release(s, true);
1518                 return;
1519         }
1520 
1521         dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1522                 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1523 
1524         dma_async_issue_pending(chan);
1525 }
1526 #endif
1527 
1528 static void sci_start_tx(struct uart_port *port)
1529 {
1530         struct sci_port *s = to_sci_port(port);
1531         unsigned short ctrl;
1532 
1533 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1534         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1535                 u16 new, scr = serial_port_in(port, SCSCR);
1536                 if (s->chan_tx)
1537                         new = scr | SCSCR_TDRQE;
1538                 else
1539                         new = scr & ~SCSCR_TDRQE;
1540                 if (new != scr)
1541                         serial_port_out(port, SCSCR, new);
1542         }
1543 
1544         if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1545             s->cookie_tx < 0) {
1546                 s->cookie_tx = 0;
1547                 schedule_work(&s->work_tx);
1548         }
1549 #endif
1550 
1551         if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1552                 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1553                 ctrl = serial_port_in(port, SCSCR);
1554                 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1555         }
1556 }
1557 
1558 static void sci_stop_tx(struct uart_port *port)
1559 {
1560         unsigned short ctrl;
1561 
1562         /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1563         ctrl = serial_port_in(port, SCSCR);
1564 
1565         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1566                 ctrl &= ~SCSCR_TDRQE;
1567 
1568         ctrl &= ~SCSCR_TIE;
1569 
1570         serial_port_out(port, SCSCR, ctrl);
1571 }
1572 
1573 static void sci_start_rx(struct uart_port *port)
1574 {
1575         unsigned short ctrl;
1576 
1577         ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1578 
1579         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1580                 ctrl &= ~SCSCR_RDRQE;
1581 
1582         serial_port_out(port, SCSCR, ctrl);
1583 }
1584 
1585 static void sci_stop_rx(struct uart_port *port)
1586 {
1587         unsigned short ctrl;
1588 
1589         ctrl = serial_port_in(port, SCSCR);
1590 
1591         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1592                 ctrl &= ~SCSCR_RDRQE;
1593 
1594         ctrl &= ~port_rx_irq_mask(port);
1595 
1596         serial_port_out(port, SCSCR, ctrl);
1597 }
1598 
1599 static void sci_break_ctl(struct uart_port *port, int break_state)
1600 {
1601         struct sci_port *s = to_sci_port(port);
1602         struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1603         unsigned short scscr, scsptr;
1604 
1605         /* check wheter the port has SCSPTR */
1606         if (!reg->size) {
1607                 /*
1608                  * Not supported by hardware. Most parts couple break and rx
1609                  * interrupts together, with break detection always enabled.
1610                  */
1611                 return;
1612         }
1613 
1614         scsptr = serial_port_in(port, SCSPTR);
1615         scscr = serial_port_in(port, SCSCR);
1616 
1617         if (break_state == -1) {
1618                 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1619                 scscr &= ~SCSCR_TE;
1620         } else {
1621                 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1622                 scscr |= SCSCR_TE;
1623         }
1624 
1625         serial_port_out(port, SCSPTR, scsptr);
1626         serial_port_out(port, SCSCR, scscr);
1627 }
1628 
1629 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1630 static bool filter(struct dma_chan *chan, void *slave)
1631 {
1632         struct sh_dmae_slave *param = slave;
1633 
1634         dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1635                 __func__, param->shdma_slave.slave_id);
1636 
1637         chan->private = &param->shdma_slave;
1638         return true;
1639 }
1640 
1641 static void rx_timer_fn(unsigned long arg)
1642 {
1643         struct sci_port *s = (struct sci_port *)arg;
1644         struct uart_port *port = &s->port;
1645         u16 scr = serial_port_in(port, SCSCR);
1646 
1647         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1648                 scr &= ~SCSCR_RDRQE;
1649                 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1650         }
1651         serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1652         dev_dbg(port->dev, "DMA Rx timed out\n");
1653         schedule_work(&s->work_rx);
1654 }
1655 
1656 static void sci_request_dma(struct uart_port *port)
1657 {
1658         struct sci_port *s = to_sci_port(port);
1659         struct sh_dmae_slave *param;
1660         struct dma_chan *chan;
1661         dma_cap_mask_t mask;
1662         int nent;
1663 
1664         dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1665 
1666         if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1667                 return;
1668 
1669         dma_cap_zero(mask);
1670         dma_cap_set(DMA_SLAVE, mask);
1671 
1672         param = &s->param_tx;
1673 
1674         /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1675         param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1676 
1677         s->cookie_tx = -EINVAL;
1678         chan = dma_request_channel(mask, filter, param);
1679         dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1680         if (chan) {
1681                 s->chan_tx = chan;
1682                 sg_init_table(&s->sg_tx, 1);
1683                 /* UART circular tx buffer is an aligned page. */
1684                 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1685                 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1686                             UART_XMIT_SIZE,
1687                             (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1688                 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1689                 if (!nent)
1690                         sci_tx_dma_release(s, false);
1691                 else
1692                         dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n",
1693                                 __func__,
1694                                 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1695                                 &sg_dma_address(&s->sg_tx));
1696 
1697                 s->sg_len_tx = nent;
1698 
1699                 INIT_WORK(&s->work_tx, work_fn_tx);
1700         }
1701 
1702         param = &s->param_rx;
1703 
1704         /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1705         param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1706 
1707         chan = dma_request_channel(mask, filter, param);
1708         dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1709         if (chan) {
1710                 dma_addr_t dma[2];
1711                 void *buf[2];
1712                 int i;
1713 
1714                 s->chan_rx = chan;
1715 
1716                 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1717                 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1718                                             &dma[0], GFP_KERNEL);
1719 
1720                 if (!buf[0]) {
1721                         dev_warn(port->dev,
1722                                  "failed to allocate dma buffer, using PIO\n");
1723                         sci_rx_dma_release(s, true);
1724                         return;
1725                 }
1726 
1727                 buf[1] = buf[0] + s->buf_len_rx;
1728                 dma[1] = dma[0] + s->buf_len_rx;
1729 
1730                 for (i = 0; i < 2; i++) {
1731                         struct scatterlist *sg = &s->sg_rx[i];
1732 
1733                         sg_init_table(sg, 1);
1734                         sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1735                                     (uintptr_t)buf[i] & ~PAGE_MASK);
1736                         sg_dma_address(sg) = dma[i];
1737                 }
1738 
1739                 INIT_WORK(&s->work_rx, work_fn_rx);
1740                 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1741 
1742                 sci_submit_rx(s);
1743         }
1744 }
1745 
1746 static void sci_free_dma(struct uart_port *port)
1747 {
1748         struct sci_port *s = to_sci_port(port);
1749 
1750         if (s->chan_tx)
1751                 sci_tx_dma_release(s, false);
1752         if (s->chan_rx)
1753                 sci_rx_dma_release(s, false);
1754 }
1755 #else
1756 static inline void sci_request_dma(struct uart_port *port)
1757 {
1758 }
1759 
1760 static inline void sci_free_dma(struct uart_port *port)
1761 {
1762 }
1763 #endif
1764 
1765 static int sci_startup(struct uart_port *port)
1766 {
1767         struct sci_port *s = to_sci_port(port);
1768         unsigned long flags;
1769         int ret;
1770 
1771         dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1772 
1773         ret = sci_request_irq(s);
1774         if (unlikely(ret < 0))
1775                 return ret;
1776 
1777         sci_request_dma(port);
1778 
1779         spin_lock_irqsave(&port->lock, flags);
1780         sci_start_tx(port);
1781         sci_start_rx(port);
1782         spin_unlock_irqrestore(&port->lock, flags);
1783 
1784         return 0;
1785 }
1786 
1787 static void sci_shutdown(struct uart_port *port)
1788 {
1789         struct sci_port *s = to_sci_port(port);
1790         unsigned long flags;
1791 
1792         dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1793 
1794         spin_lock_irqsave(&port->lock, flags);
1795         sci_stop_rx(port);
1796         sci_stop_tx(port);
1797         spin_unlock_irqrestore(&port->lock, flags);
1798 
1799         sci_free_dma(port);
1800         sci_free_irq(s);
1801 }
1802 
1803 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1804                                    unsigned long freq)
1805 {
1806         if (s->sampling_rate)
1807                 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1808 
1809         /* Warn, but use a safe default */
1810         WARN_ON(1);
1811 
1812         return ((freq + 16 * bps) / (32 * bps) - 1);
1813 }
1814 
1815 /* calculate frame length from SMR */
1816 static int sci_baud_calc_frame_len(unsigned int smr_val)
1817 {
1818         int len = 10;
1819 
1820         if (smr_val & SCSMR_CHR)
1821                 len--;
1822         if (smr_val & SCSMR_PE)
1823                 len++;
1824         if (smr_val & SCSMR_STOP)
1825                 len++;
1826 
1827         return len;
1828 }
1829 
1830 
1831 /* calculate sample rate, BRR, and clock select for HSCIF */
1832 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1833                                 int *brr, unsigned int *srr,
1834                                 unsigned int *cks, int frame_len)
1835 {
1836         int sr, c, br, err, recv_margin;
1837         int min_err = 1000; /* 100% */
1838         int recv_max_margin = 0;
1839 
1840         /* Find the combination of sample rate and clock select with the
1841            smallest deviation from the desired baud rate. */
1842         for (sr = 8; sr <= 32; sr++) {
1843                 for (c = 0; c <= 3; c++) {
1844                         /* integerized formulas from HSCIF documentation */
1845                         br = DIV_ROUND_CLOSEST(freq, (sr *
1846                                               (1 << (2 * c + 1)) * bps)) - 1;
1847                         br = clamp(br, 0, 255);
1848                         err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1849                                                (1 << (2 * c + 1)) / 1000)) -
1850                                                1000;
1851                         /* Calc recv margin
1852                          * M: Receive margin (%)
1853                          * N: Ratio of bit rate to clock (N = sampling rate)
1854                          * D: Clock duty (D = 0 to 1.0)
1855                          * L: Frame length (L = 9 to 12)
1856                          * F: Absolute value of clock frequency deviation
1857                          *
1858                          *  M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1859                          *      (|D - 0.5| / N * (1 + F))|
1860                          *  NOTE: Usually, treat D for 0.5, F is 0 by this
1861                          *        calculation.
1862                          */
1863                         recv_margin = abs((500 -
1864                                         DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1865                         if (abs(min_err) > abs(err)) {
1866                                 min_err = err;
1867                                 recv_max_margin = recv_margin;
1868                         } else if ((min_err == err) &&
1869                                    (recv_margin > recv_max_margin))
1870                                 recv_max_margin = recv_margin;
1871                         else
1872                                 continue;
1873 
1874                         *brr = br;
1875                         *srr = sr - 1;
1876                         *cks = c;
1877                 }
1878         }
1879 
1880         if (min_err == 1000) {
1881                 WARN_ON(1);
1882                 /* use defaults */
1883                 *brr = 255;
1884                 *srr = 15;
1885                 *cks = 0;
1886         }
1887 }
1888 
1889 static void sci_reset(struct uart_port *port)
1890 {
1891         struct plat_sci_reg *reg;
1892         unsigned int status;
1893 
1894         do {
1895                 status = serial_port_in(port, SCxSR);
1896         } while (!(status & SCxSR_TEND(port)));
1897 
1898         serial_port_out(port, SCSCR, 0x00);     /* TE=0, RE=0, CKE1=0 */
1899 
1900         reg = sci_getreg(port, SCFCR);
1901         if (reg->size)
1902                 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1903 }
1904 
1905 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1906                             struct ktermios *old)
1907 {
1908         struct sci_port *s = to_sci_port(port);
1909         struct plat_sci_reg *reg;
1910         unsigned int baud, smr_val = 0, max_baud, cks = 0;
1911         int t = -1;
1912         unsigned int srr = 15;
1913 
1914         if ((termios->c_cflag & CSIZE) == CS7)
1915                 smr_val |= SCSMR_CHR;
1916         if (termios->c_cflag & PARENB)
1917                 smr_val |= SCSMR_PE;
1918         if (termios->c_cflag & PARODD)
1919                 smr_val |= SCSMR_PE | SCSMR_ODD;
1920         if (termios->c_cflag & CSTOPB)
1921                 smr_val |= SCSMR_STOP;
1922 
1923         /*
1924          * earlyprintk comes here early on with port->uartclk set to zero.
1925          * the clock framework is not up and running at this point so here
1926          * we assume that 115200 is the maximum baud rate. please note that
1927          * the baud rate is not programmed during earlyprintk - it is assumed
1928          * that the previous boot loader has enabled required clocks and
1929          * setup the baud rate generator hardware for us already.
1930          */
1931         max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1932 
1933         baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1934         if (likely(baud && port->uartclk)) {
1935                 if (s->cfg->type == PORT_HSCIF) {
1936                         int frame_len = sci_baud_calc_frame_len(smr_val);
1937                         sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1938                                             &cks, frame_len);
1939                 } else {
1940                         t = sci_scbrr_calc(s, baud, port->uartclk);
1941                         for (cks = 0; t >= 256 && cks <= 3; cks++)
1942                                 t >>= 2;
1943                 }
1944         }
1945 
1946         sci_port_enable(s);
1947 
1948         sci_reset(port);
1949 
1950         smr_val |= serial_port_in(port, SCSMR) & 3;
1951 
1952         uart_update_timeout(port, termios->c_cflag, baud);
1953 
1954         dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1955                 __func__, smr_val, cks, t, s->cfg->scscr);
1956 
1957         if (t >= 0) {
1958                 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
1959                 serial_port_out(port, SCBRR, t);
1960                 reg = sci_getreg(port, HSSRR);
1961                 if (reg->size)
1962                         serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1963                 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1964         } else
1965                 serial_port_out(port, SCSMR, smr_val);
1966 
1967         sci_init_pins(port, termios->c_cflag);
1968 
1969         reg = sci_getreg(port, SCFCR);
1970         if (reg->size) {
1971                 unsigned short ctrl = serial_port_in(port, SCFCR);
1972 
1973                 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1974                         if (termios->c_cflag & CRTSCTS)
1975                                 ctrl |= SCFCR_MCE;
1976                         else
1977                                 ctrl &= ~SCFCR_MCE;
1978                 }
1979 
1980                 /*
1981                  * As we've done a sci_reset() above, ensure we don't
1982                  * interfere with the FIFOs while toggling MCE. As the
1983                  * reset values could still be set, simply mask them out.
1984                  */
1985                 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1986 
1987                 serial_port_out(port, SCFCR, ctrl);
1988         }
1989 
1990         serial_port_out(port, SCSCR, s->cfg->scscr);
1991 
1992 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1993         /*
1994          * Calculate delay for 2 DMA buffers (4 FIFO).
1995          * See drivers/serial/serial_core.c::uart_update_timeout(). With 10
1996          * bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1997          * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1998          * Then below we calculate 5 jiffies (20ms) for 2 DMA buffers (4 FIFO
1999          * sizes), but when performing a faster transfer, value obtained by
2000          * this formula is may not enough. Therefore, if value is smaller than
2001          * 20msec, this sets 20msec as timeout of DMA.
2002          */
2003         if (s->chan_rx) {
2004                 unsigned int bits;
2005 
2006                 /* byte size and parity */
2007                 switch (termios->c_cflag & CSIZE) {
2008                 case CS5:
2009                         bits = 7;
2010                         break;
2011                 case CS6:
2012                         bits = 8;
2013                         break;
2014                 case CS7:
2015                         bits = 9;
2016                         break;
2017                 default:
2018                         bits = 10;
2019                         break;
2020                 }
2021 
2022                 if (termios->c_cflag & CSTOPB)
2023                         bits++;
2024                 if (termios->c_cflag & PARENB)
2025                         bits++;
2026                 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2027                                              (baud / 10), 10);
2028                 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2029                         s->rx_timeout * 1000 / HZ, port->timeout);
2030                 if (s->rx_timeout < msecs_to_jiffies(20))
2031                         s->rx_timeout = msecs_to_jiffies(20);
2032         }
2033 #endif
2034 
2035         if ((termios->c_cflag & CREAD) != 0)
2036                 sci_start_rx(port);
2037 
2038         sci_port_disable(s);
2039 }
2040 
2041 static void sci_pm(struct uart_port *port, unsigned int state,
2042                    unsigned int oldstate)
2043 {
2044         struct sci_port *sci_port = to_sci_port(port);
2045 
2046         switch (state) {
2047         case UART_PM_STATE_OFF:
2048                 sci_port_disable(sci_port);
2049                 break;
2050         default:
2051                 sci_port_enable(sci_port);
2052                 break;
2053         }
2054 }
2055 
2056 static const char *sci_type(struct uart_port *port)
2057 {
2058         switch (port->type) {
2059         case PORT_IRDA:
2060                 return "irda";
2061         case PORT_SCI:
2062                 return "sci";
2063         case PORT_SCIF:
2064                 return "scif";
2065         case PORT_SCIFA:
2066                 return "scifa";
2067         case PORT_SCIFB:
2068                 return "scifb";
2069         case PORT_HSCIF:
2070                 return "hscif";
2071         }
2072 
2073         return NULL;
2074 }
2075 
2076 static inline unsigned long sci_port_size(struct uart_port *port)
2077 {
2078         /*
2079          * Pick an arbitrary size that encapsulates all of the base
2080          * registers by default. This can be optimized later, or derived
2081          * from platform resource data at such a time that ports begin to
2082          * behave more erratically.
2083          */
2084         if (port->type == PORT_HSCIF)
2085                 return 96;
2086         else
2087                 return 64;
2088 }
2089 
2090 static int sci_remap_port(struct uart_port *port)
2091 {
2092         unsigned long size = sci_port_size(port);
2093 
2094         /*
2095          * Nothing to do if there's already an established membase.
2096          */
2097         if (port->membase)
2098                 return 0;
2099 
2100         if (port->flags & UPF_IOREMAP) {
2101                 port->membase = ioremap_nocache(port->mapbase, size);
2102                 if (unlikely(!port->membase)) {
2103                         dev_err(port->dev, "can't remap port#%d\n", port->line);
2104                         return -ENXIO;
2105                 }
2106         } else {
2107                 /*
2108                  * For the simple (and majority of) cases where we don't
2109                  * need to do any remapping, just cast the cookie
2110                  * directly.
2111                  */
2112                 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2113         }
2114 
2115         return 0;
2116 }
2117 
2118 static void sci_release_port(struct uart_port *port)
2119 {
2120         if (port->flags & UPF_IOREMAP) {
2121                 iounmap(port->membase);
2122                 port->membase = NULL;
2123         }
2124 
2125         release_mem_region(port->mapbase, sci_port_size(port));
2126 }
2127 
2128 static int sci_request_port(struct uart_port *port)
2129 {
2130         unsigned long size = sci_port_size(port);
2131         struct resource *res;
2132         int ret;
2133 
2134         res = request_mem_region(port->mapbase, size, dev_name(port->dev));
2135         if (unlikely(res == NULL))
2136                 return -EBUSY;
2137 
2138         ret = sci_remap_port(port);
2139         if (unlikely(ret != 0)) {
2140                 release_resource(res);
2141                 return ret;
2142         }
2143 
2144         return 0;
2145 }
2146 
2147 static void sci_config_port(struct uart_port *port, int flags)
2148 {
2149         if (flags & UART_CONFIG_TYPE) {
2150                 struct sci_port *sport = to_sci_port(port);
2151 
2152                 port->type = sport->cfg->type;
2153                 sci_request_port(port);
2154         }
2155 }
2156 
2157 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2158 {
2159         if (ser->baud_base < 2400)
2160                 /* No paper tape reader for Mitch.. */
2161                 return -EINVAL;
2162 
2163         return 0;
2164 }
2165 
2166 static struct uart_ops sci_uart_ops = {
2167         .tx_empty       = sci_tx_empty,
2168         .set_mctrl      = sci_set_mctrl,
2169         .get_mctrl      = sci_get_mctrl,
2170         .start_tx       = sci_start_tx,
2171         .stop_tx        = sci_stop_tx,
2172         .stop_rx        = sci_stop_rx,
2173         .break_ctl      = sci_break_ctl,
2174         .startup        = sci_startup,
2175         .shutdown       = sci_shutdown,
2176         .set_termios    = sci_set_termios,
2177         .pm             = sci_pm,
2178         .type           = sci_type,
2179         .release_port   = sci_release_port,
2180         .request_port   = sci_request_port,
2181         .config_port    = sci_config_port,
2182         .verify_port    = sci_verify_port,
2183 #ifdef CONFIG_CONSOLE_POLL
2184         .poll_get_char  = sci_poll_get_char,
2185         .poll_put_char  = sci_poll_put_char,
2186 #endif
2187 };
2188 
2189 static int sci_init_single(struct platform_device *dev,
2190                            struct sci_port *sci_port, unsigned int index,
2191                            struct plat_sci_port *p, bool early)
2192 {
2193         struct uart_port *port = &sci_port->port;
2194         const struct resource *res;
2195         unsigned int sampling_rate;
2196         unsigned int i;
2197         int ret;
2198 
2199         sci_port->cfg   = p;
2200 
2201         port->ops       = &sci_uart_ops;
2202         port->iotype    = UPIO_MEM;
2203         port->line      = index;
2204 
2205         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2206         if (res == NULL)
2207                 return -ENOMEM;
2208 
2209         port->mapbase = res->start;
2210 
2211         for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2212                 sci_port->irqs[i] = platform_get_irq(dev, i);
2213 
2214         /* The SCI generates several interrupts. They can be muxed together or
2215          * connected to different interrupt lines. In the muxed case only one
2216          * interrupt resource is specified. In the non-muxed case three or four
2217          * interrupt resources are specified, as the BRI interrupt is optional.
2218          */
2219         if (sci_port->irqs[0] < 0)
2220                 return -ENXIO;
2221 
2222         if (sci_port->irqs[1] < 0) {
2223                 sci_port->irqs[1] = sci_port->irqs[0];
2224                 sci_port->irqs[2] = sci_port->irqs[0];
2225                 sci_port->irqs[3] = sci_port->irqs[0];
2226         }
2227 
2228         if (p->regtype == SCIx_PROBE_REGTYPE) {
2229                 ret = sci_probe_regmap(p);
2230                 if (unlikely(ret))
2231                         return ret;
2232         }
2233 
2234         switch (p->type) {
2235         case PORT_SCIFB:
2236                 port->fifosize = 256;
2237                 sci_port->overrun_bit = 9;
2238                 sampling_rate = 16;
2239                 break;
2240         case PORT_HSCIF:
2241                 port->fifosize = 128;
2242                 sampling_rate = 0;
2243                 sci_port->overrun_bit = 0;
2244                 break;
2245         case PORT_SCIFA:
2246                 port->fifosize = 64;
2247                 sci_port->overrun_bit = 9;
2248                 sampling_rate = 16;
2249                 break;
2250         case PORT_SCIF:
2251                 port->fifosize = 16;
2252                 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2253                         sci_port->overrun_bit = 9;
2254                         sampling_rate = 16;
2255                 } else {
2256                         sci_port->overrun_bit = 0;
2257                         sampling_rate = 32;
2258                 }
2259                 break;
2260         default:
2261                 port->fifosize = 1;
2262                 sci_port->overrun_bit = 5;
2263                 sampling_rate = 32;
2264                 break;
2265         }
2266 
2267         /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2268          * match the SoC datasheet, this should be investigated. Let platform
2269          * data override the sampling rate for now.
2270          */
2271         sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
2272                                 : sampling_rate;
2273 
2274         if (!early) {
2275                 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2276                 if (IS_ERR(sci_port->iclk)) {
2277                         sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2278                         if (IS_ERR(sci_port->iclk)) {
2279                                 dev_err(&dev->dev, "can't get iclk\n");
2280                                 return PTR_ERR(sci_port->iclk);
2281                         }
2282                 }
2283 
2284                 /*
2285                  * The function clock is optional, ignore it if we can't
2286                  * find it.
2287                  */
2288                 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2289                 if (IS_ERR(sci_port->fclk))
2290                         sci_port->fclk = NULL;
2291 
2292                 port->dev = &dev->dev;
2293 
2294                 pm_runtime_enable(&dev->dev);
2295         }
2296 
2297         sci_port->break_timer.data = (unsigned long)sci_port;
2298         sci_port->break_timer.function = sci_break_timer;
2299         init_timer(&sci_port->break_timer);
2300 
2301         /*
2302          * Establish some sensible defaults for the error detection.
2303          */
2304         sci_port->error_mask = (p->type == PORT_SCI) ?
2305                         SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2306 
2307         /*
2308          * Establish sensible defaults for the overrun detection, unless
2309          * the part has explicitly disabled support for it.
2310          */
2311 
2312         /*
2313          * Make the error mask inclusive of overrun detection, if
2314          * supported.
2315          */
2316         sci_port->error_mask |= 1 << sci_port->overrun_bit;
2317 
2318         port->type              = p->type;
2319         port->flags             = UPF_FIXED_PORT | p->flags;
2320         port->regshift          = p->regshift;
2321 
2322         /*
2323          * The UART port needs an IRQ value, so we peg this to the RX IRQ
2324          * for the multi-IRQ ports, which is where we are primarily
2325          * concerned with the shutdown path synchronization.
2326          *
2327          * For the muxed case there's nothing more to do.
2328          */
2329         port->irq               = sci_port->irqs[SCIx_RXI_IRQ];
2330         port->irqflags          = 0;
2331 
2332         port->serial_in         = sci_serial_in;
2333         port->serial_out        = sci_serial_out;
2334 
2335         if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2336                 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2337                         p->dma_slave_tx, p->dma_slave_rx);
2338 
2339         return 0;
2340 }
2341 
2342 static void sci_cleanup_single(struct sci_port *port)
2343 {
2344         clk_put(port->iclk);
2345         clk_put(port->fclk);
2346 
2347         pm_runtime_disable(port->port.dev);
2348 }
2349 
2350 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2351 static void serial_console_putchar(struct uart_port *port, int ch)
2352 {
2353         sci_poll_put_char(port, ch);
2354 }
2355 
2356 /*
2357  *      Print a string to the serial port trying not to disturb
2358  *      any possible real use of the port...
2359  */
2360 static void serial_console_write(struct console *co, const char *s,
2361                                  unsigned count)
2362 {
2363         struct sci_port *sci_port = &sci_ports[co->index];
2364         struct uart_port *port = &sci_port->port;
2365         unsigned short bits, ctrl;
2366         unsigned long flags;
2367         int locked = 1;
2368 
2369         local_irq_save(flags);
2370         if (port->sysrq)
2371                 locked = 0;
2372         else if (oops_in_progress)
2373                 locked = spin_trylock(&port->lock);
2374         else
2375                 spin_lock(&port->lock);
2376 
2377         /* first save the SCSCR then disable the interrupts */
2378         ctrl = serial_port_in(port, SCSCR);
2379         serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2380 
2381         uart_console_write(port, s, count, serial_console_putchar);
2382 
2383         /* wait until fifo is empty and last bit has been transmitted */
2384         bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2385         while ((serial_port_in(port, SCxSR) & bits) != bits)
2386                 cpu_relax();
2387 
2388         /* restore the SCSCR */
2389         serial_port_out(port, SCSCR, ctrl);
2390 
2391         if (locked)
2392                 spin_unlock(&port->lock);
2393         local_irq_restore(flags);
2394 }
2395 
2396 static int serial_console_setup(struct console *co, char *options)
2397 {
2398         struct sci_port *sci_port;
2399         struct uart_port *port;
2400         int baud = 115200;
2401         int bits = 8;
2402         int parity = 'n';
2403         int flow = 'n';
2404         int ret;
2405 
2406         /*
2407          * Refuse to handle any bogus ports.
2408          */
2409         if (co->index < 0 || co->index >= SCI_NPORTS)
2410                 return -ENODEV;
2411 
2412         sci_port = &sci_ports[co->index];
2413         port = &sci_port->port;
2414 
2415         /*
2416          * Refuse to handle uninitialized ports.
2417          */
2418         if (!port->ops)
2419                 return -ENODEV;
2420 
2421         ret = sci_remap_port(port);
2422         if (unlikely(ret != 0))
2423                 return ret;
2424 
2425         if (options)
2426                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2427 
2428         return uart_set_options(port, co, baud, parity, bits, flow);
2429 }
2430 
2431 static struct console serial_console = {
2432         .name           = "ttySC",
2433         .device         = uart_console_device,
2434         .write          = serial_console_write,
2435         .setup          = serial_console_setup,
2436         .flags          = CON_PRINTBUFFER,
2437         .index          = -1,
2438         .data           = &sci_uart_driver,
2439 };
2440 
2441 static struct console early_serial_console = {
2442         .name           = "early_ttySC",
2443         .write          = serial_console_write,
2444         .flags          = CON_PRINTBUFFER,
2445         .index          = -1,
2446 };
2447 
2448 static char early_serial_buf[32];
2449 
2450 static int sci_probe_earlyprintk(struct platform_device *pdev)
2451 {
2452         struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2453 
2454         if (early_serial_console.data)
2455                 return -EEXIST;
2456 
2457         early_serial_console.index = pdev->id;
2458 
2459         sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2460 
2461         serial_console_setup(&early_serial_console, early_serial_buf);
2462 
2463         if (!strstr(early_serial_buf, "keep"))
2464                 early_serial_console.flags |= CON_BOOT;
2465 
2466         register_console(&early_serial_console);
2467         return 0;
2468 }
2469 
2470 #define SCI_CONSOLE     (&serial_console)
2471 
2472 #else
2473 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2474 {
2475         return -EINVAL;
2476 }
2477 
2478 #define SCI_CONSOLE     NULL
2479 
2480 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2481 
2482 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2483 
2484 static struct uart_driver sci_uart_driver = {
2485         .owner          = THIS_MODULE,
2486         .driver_name    = "sci",
2487         .dev_name       = "ttySC",
2488         .major          = SCI_MAJOR,
2489         .minor          = SCI_MINOR_START,
2490         .nr             = SCI_NPORTS,
2491         .cons           = SCI_CONSOLE,
2492 };
2493 
2494 static int sci_remove(struct platform_device *dev)
2495 {
2496         struct sci_port *port = platform_get_drvdata(dev);
2497 
2498         cpufreq_unregister_notifier(&port->freq_transition,
2499                                     CPUFREQ_TRANSITION_NOTIFIER);
2500 
2501         uart_remove_one_port(&sci_uart_driver, &port->port);
2502 
2503         sci_cleanup_single(port);
2504 
2505         return 0;
2506 }
2507 
2508 struct sci_port_info {
2509         unsigned int type;
2510         unsigned int regtype;
2511 };
2512 
2513 static const struct of_device_id of_sci_match[] = {
2514         {
2515                 .compatible = "renesas,scif",
2516                 .data = &(const struct sci_port_info) {
2517                         .type = PORT_SCIF,
2518                         .regtype = SCIx_SH4_SCIF_REGTYPE,
2519                 },
2520         }, {
2521                 .compatible = "renesas,scifa",
2522                 .data = &(const struct sci_port_info) {
2523                         .type = PORT_SCIFA,
2524                         .regtype = SCIx_SCIFA_REGTYPE,
2525                 },
2526         }, {
2527                 .compatible = "renesas,scifb",
2528                 .data = &(const struct sci_port_info) {
2529                         .type = PORT_SCIFB,
2530                         .regtype = SCIx_SCIFB_REGTYPE,
2531                 },
2532         }, {
2533                 .compatible = "renesas,hscif",
2534                 .data = &(const struct sci_port_info) {
2535                         .type = PORT_HSCIF,
2536                         .regtype = SCIx_HSCIF_REGTYPE,
2537                 },
2538         }, {
2539                 /* Terminator */
2540         },
2541 };
2542 MODULE_DEVICE_TABLE(of, of_sci_match);
2543 
2544 static struct plat_sci_port *
2545 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2546 {
2547         struct device_node *np = pdev->dev.of_node;
2548         const struct of_device_id *match;
2549         const struct sci_port_info *info;
2550         struct plat_sci_port *p;
2551         int id;
2552 
2553         if (!IS_ENABLED(CONFIG_OF) || !np)
2554                 return NULL;
2555 
2556         match = of_match_node(of_sci_match, pdev->dev.of_node);
2557         if (!match)
2558                 return NULL;
2559 
2560         info = match->data;
2561 
2562         p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2563         if (!p) {
2564                 dev_err(&pdev->dev, "failed to allocate DT config data\n");
2565                 return NULL;
2566         }
2567 
2568         /* Get the line number for the aliases node. */
2569         id = of_alias_get_id(np, "serial");
2570         if (id < 0) {
2571                 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2572                 return NULL;
2573         }
2574 
2575         *dev_id = id;
2576 
2577         p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2578         p->type = info->type;
2579         p->regtype = info->regtype;
2580         p->scscr = SCSCR_RE | SCSCR_TE;
2581 
2582         return p;
2583 }
2584 
2585 static int sci_probe_single(struct platform_device *dev,
2586                                       unsigned int index,
2587                                       struct plat_sci_port *p,
2588                                       struct sci_port *sciport)
2589 {
2590         int ret;
2591 
2592         /* Sanity check */
2593         if (unlikely(index >= SCI_NPORTS)) {
2594                 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2595                            index+1, SCI_NPORTS);
2596                 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2597                 return -EINVAL;
2598         }
2599 
2600         ret = sci_init_single(dev, sciport, index, p, false);
2601         if (ret)
2602                 return ret;
2603 
2604         ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2605         if (ret) {
2606                 sci_cleanup_single(sciport);
2607                 return ret;
2608         }
2609 
2610         return 0;
2611 }
2612 
2613 static int sci_probe(struct platform_device *dev)
2614 {
2615         struct plat_sci_port *p;
2616         struct sci_port *sp;
2617         unsigned int dev_id;
2618         int ret;
2619 
2620         /*
2621          * If we've come here via earlyprintk initialization, head off to
2622          * the special early probe. We don't have sufficient device state
2623          * to make it beyond this yet.
2624          */
2625         if (is_early_platform_device(dev))
2626                 return sci_probe_earlyprintk(dev);
2627 
2628         if (dev->dev.of_node) {
2629                 p = sci_parse_dt(dev, &dev_id);
2630                 if (p == NULL)
2631                         return -EINVAL;
2632         } else {
2633                 p = dev->dev.platform_data;
2634                 if (p == NULL) {
2635                         dev_err(&dev->dev, "no platform data supplied\n");
2636                         return -EINVAL;
2637                 }
2638 
2639                 dev_id = dev->id;
2640         }
2641 
2642         sp = &sci_ports[dev_id];
2643         platform_set_drvdata(dev, sp);
2644 
2645         ret = sci_probe_single(dev, dev_id, p, sp);
2646         if (ret)
2647                 return ret;
2648 
2649         sp->freq_transition.notifier_call = sci_notifier;
2650 
2651         ret = cpufreq_register_notifier(&sp->freq_transition,
2652                                         CPUFREQ_TRANSITION_NOTIFIER);
2653         if (unlikely(ret < 0)) {
2654                 uart_remove_one_port(&sci_uart_driver, &sp->port);
2655                 sci_cleanup_single(sp);
2656                 return ret;
2657         }
2658 
2659 #ifdef CONFIG_SH_STANDARD_BIOS
2660         sh_bios_gdb_detach();
2661 #endif
2662 
2663         return 0;
2664 }
2665 
2666 static __maybe_unused int sci_suspend(struct device *dev)
2667 {
2668         struct sci_port *sport = dev_get_drvdata(dev);
2669 
2670         if (sport)
2671                 uart_suspend_port(&sci_uart_driver, &sport->port);
2672 
2673         return 0;
2674 }
2675 
2676 static __maybe_unused int sci_resume(struct device *dev)
2677 {
2678         struct sci_port *sport = dev_get_drvdata(dev);
2679 
2680         if (sport)
2681                 uart_resume_port(&sci_uart_driver, &sport->port);
2682 
2683         return 0;
2684 }
2685 
2686 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2687 
2688 static struct platform_driver sci_driver = {
2689         .probe          = sci_probe,
2690         .remove         = sci_remove,
2691         .driver         = {
2692                 .name   = "sh-sci",
2693                 .pm     = &sci_dev_pm_ops,
2694                 .of_match_table = of_match_ptr(of_sci_match),
2695         },
2696 };
2697 
2698 static int __init sci_init(void)
2699 {
2700         int ret;
2701 
2702         pr_info("%s\n", banner);
2703 
2704         ret = uart_register_driver(&sci_uart_driver);
2705         if (likely(ret == 0)) {
2706                 ret = platform_driver_register(&sci_driver);
2707                 if (unlikely(ret))
2708                         uart_unregister_driver(&sci_uart_driver);
2709         }
2710 
2711         return ret;
2712 }
2713 
2714 static void __exit sci_exit(void)
2715 {
2716         platform_driver_unregister(&sci_driver);
2717         uart_unregister_driver(&sci_uart_driver);
2718 }
2719 
2720 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2721 early_platform_init_buffer("earlyprintk", &sci_driver,
2722                            early_serial_buf, ARRAY_SIZE(early_serial_buf));
2723 #endif
2724 module_init(sci_init);
2725 module_exit(sci_exit);
2726 
2727 MODULE_LICENSE("GPL");
2728 MODULE_ALIAS("platform:sh-sci");
2729 MODULE_AUTHOR("Paul Mundt");
2730 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
2731 

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