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Linux/drivers/tty/serial/sh-sci.c

  1 /*
  2  * SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
  3  *
  4  *  Copyright (C) 2002 - 2011  Paul Mundt
  5  *  Copyright (C) 2015 Glider bvba
  6  *  Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
  7  *
  8  * based off of the old drivers/char/sh-sci.c by:
  9  *
 10  *   Copyright (C) 1999, 2000  Niibe Yutaka
 11  *   Copyright (C) 2000  Sugioka Toshinobu
 12  *   Modified to support multiple serial ports. Stuart Menefy (May 2000).
 13  *   Modified to support SecureEdge. David McCullough (2002)
 14  *   Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
 15  *   Removed SH7300 support (Jul 2007).
 16  *
 17  * This file is subject to the terms and conditions of the GNU General Public
 18  * License.  See the file "COPYING" in the main directory of this archive
 19  * for more details.
 20  */
 21 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 22 #define SUPPORT_SYSRQ
 23 #endif
 24 
 25 #undef DEBUG
 26 
 27 #include <linux/clk.h>
 28 #include <linux/console.h>
 29 #include <linux/ctype.h>
 30 #include <linux/cpufreq.h>
 31 #include <linux/delay.h>
 32 #include <linux/dmaengine.h>
 33 #include <linux/dma-mapping.h>
 34 #include <linux/err.h>
 35 #include <linux/errno.h>
 36 #include <linux/init.h>
 37 #include <linux/interrupt.h>
 38 #include <linux/ioport.h>
 39 #include <linux/major.h>
 40 #include <linux/module.h>
 41 #include <linux/mm.h>
 42 #include <linux/of.h>
 43 #include <linux/platform_device.h>
 44 #include <linux/pm_runtime.h>
 45 #include <linux/scatterlist.h>
 46 #include <linux/serial.h>
 47 #include <linux/serial_sci.h>
 48 #include <linux/sh_dma.h>
 49 #include <linux/slab.h>
 50 #include <linux/string.h>
 51 #include <linux/sysrq.h>
 52 #include <linux/timer.h>
 53 #include <linux/tty.h>
 54 #include <linux/tty_flip.h>
 55 
 56 #ifdef CONFIG_SUPERH
 57 #include <asm/sh_bios.h>
 58 #endif
 59 
 60 #include "sh-sci.h"
 61 
 62 /* Offsets into the sci_port->irqs array */
 63 enum {
 64         SCIx_ERI_IRQ,
 65         SCIx_RXI_IRQ,
 66         SCIx_TXI_IRQ,
 67         SCIx_BRI_IRQ,
 68         SCIx_NR_IRQS,
 69 
 70         SCIx_MUX_IRQ = SCIx_NR_IRQS,    /* special case */
 71 };
 72 
 73 #define SCIx_IRQ_IS_MUXED(port)                 \
 74         ((port)->irqs[SCIx_ERI_IRQ] ==  \
 75          (port)->irqs[SCIx_RXI_IRQ]) || \
 76         ((port)->irqs[SCIx_ERI_IRQ] &&  \
 77          ((port)->irqs[SCIx_RXI_IRQ] < 0))
 78 
 79 enum SCI_CLKS {
 80         SCI_FCK,                /* Functional Clock */
 81         SCI_SCK,                /* Optional External Clock */
 82         SCI_BRG_INT,            /* Optional BRG Internal Clock Source */
 83         SCI_SCIF_CLK,           /* Optional BRG External Clock Source */
 84         SCI_NUM_CLKS
 85 };
 86 
 87 struct sci_port {
 88         struct uart_port        port;
 89 
 90         /* Platform configuration */
 91         struct plat_sci_port    *cfg;
 92         unsigned int            overrun_reg;
 93         unsigned int            overrun_mask;
 94         unsigned int            error_mask;
 95         unsigned int            error_clear;
 96         unsigned int            sampling_rate;
 97         resource_size_t         reg_size;
 98 
 99         /* Break timer */
100         struct timer_list       break_timer;
101         int                     break_flag;
102 
103         /* Clocks */
104         struct clk              *clks[SCI_NUM_CLKS];
105         unsigned long           clk_rates[SCI_NUM_CLKS];
106 
107         int                     irqs[SCIx_NR_IRQS];
108         char                    *irqstr[SCIx_NR_IRQS];
109 
110         struct dma_chan                 *chan_tx;
111         struct dma_chan                 *chan_rx;
112 
113 #ifdef CONFIG_SERIAL_SH_SCI_DMA
114         dma_cookie_t                    cookie_tx;
115         dma_cookie_t                    cookie_rx[2];
116         dma_cookie_t                    active_rx;
117         dma_addr_t                      tx_dma_addr;
118         unsigned int                    tx_dma_len;
119         struct scatterlist              sg_rx[2];
120         void                            *rx_buf[2];
121         size_t                          buf_len_rx;
122         struct work_struct              work_tx;
123         struct timer_list               rx_timer;
124         unsigned int                    rx_timeout;
125 #endif
126 };
127 
128 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
129 
130 static struct sci_port sci_ports[SCI_NPORTS];
131 static struct uart_driver sci_uart_driver;
132 
133 static inline struct sci_port *
134 to_sci_port(struct uart_port *uart)
135 {
136         return container_of(uart, struct sci_port, port);
137 }
138 
139 struct plat_sci_reg {
140         u8 offset, size;
141 };
142 
143 /* Helper for invalidating specific entries of an inherited map. */
144 #define sci_reg_invalid { .offset = 0, .size = 0 }
145 
146 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
147         [SCIx_PROBE_REGTYPE] = {
148                 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
149         },
150 
151         /*
152          * Common SCI definitions, dependent on the port's regshift
153          * value.
154          */
155         [SCIx_SCI_REGTYPE] = {
156                 [SCSMR]         = { 0x00,  8 },
157                 [SCBRR]         = { 0x01,  8 },
158                 [SCSCR]         = { 0x02,  8 },
159                 [SCxTDR]        = { 0x03,  8 },
160                 [SCxSR]         = { 0x04,  8 },
161                 [SCxRDR]        = { 0x05,  8 },
162                 [SCFCR]         = sci_reg_invalid,
163                 [SCFDR]         = sci_reg_invalid,
164                 [SCTFDR]        = sci_reg_invalid,
165                 [SCRFDR]        = sci_reg_invalid,
166                 [SCSPTR]        = sci_reg_invalid,
167                 [SCLSR]         = sci_reg_invalid,
168                 [HSSRR]         = sci_reg_invalid,
169                 [SCPCR]         = sci_reg_invalid,
170                 [SCPDR]         = sci_reg_invalid,
171                 [SCDL]          = sci_reg_invalid,
172                 [SCCKS]         = sci_reg_invalid,
173         },
174 
175         /*
176          * Common definitions for legacy IrDA ports, dependent on
177          * regshift value.
178          */
179         [SCIx_IRDA_REGTYPE] = {
180                 [SCSMR]         = { 0x00,  8 },
181                 [SCBRR]         = { 0x01,  8 },
182                 [SCSCR]         = { 0x02,  8 },
183                 [SCxTDR]        = { 0x03,  8 },
184                 [SCxSR]         = { 0x04,  8 },
185                 [SCxRDR]        = { 0x05,  8 },
186                 [SCFCR]         = { 0x06,  8 },
187                 [SCFDR]         = { 0x07, 16 },
188                 [SCTFDR]        = sci_reg_invalid,
189                 [SCRFDR]        = sci_reg_invalid,
190                 [SCSPTR]        = sci_reg_invalid,
191                 [SCLSR]         = sci_reg_invalid,
192                 [HSSRR]         = sci_reg_invalid,
193                 [SCPCR]         = sci_reg_invalid,
194                 [SCPDR]         = sci_reg_invalid,
195                 [SCDL]          = sci_reg_invalid,
196                 [SCCKS]         = sci_reg_invalid,
197         },
198 
199         /*
200          * Common SCIFA definitions.
201          */
202         [SCIx_SCIFA_REGTYPE] = {
203                 [SCSMR]         = { 0x00, 16 },
204                 [SCBRR]         = { 0x04,  8 },
205                 [SCSCR]         = { 0x08, 16 },
206                 [SCxTDR]        = { 0x20,  8 },
207                 [SCxSR]         = { 0x14, 16 },
208                 [SCxRDR]        = { 0x24,  8 },
209                 [SCFCR]         = { 0x18, 16 },
210                 [SCFDR]         = { 0x1c, 16 },
211                 [SCTFDR]        = sci_reg_invalid,
212                 [SCRFDR]        = sci_reg_invalid,
213                 [SCSPTR]        = sci_reg_invalid,
214                 [SCLSR]         = sci_reg_invalid,
215                 [HSSRR]         = sci_reg_invalid,
216                 [SCPCR]         = { 0x30, 16 },
217                 [SCPDR]         = { 0x34, 16 },
218                 [SCDL]          = sci_reg_invalid,
219                 [SCCKS]         = sci_reg_invalid,
220         },
221 
222         /*
223          * Common SCIFB definitions.
224          */
225         [SCIx_SCIFB_REGTYPE] = {
226                 [SCSMR]         = { 0x00, 16 },
227                 [SCBRR]         = { 0x04,  8 },
228                 [SCSCR]         = { 0x08, 16 },
229                 [SCxTDR]        = { 0x40,  8 },
230                 [SCxSR]         = { 0x14, 16 },
231                 [SCxRDR]        = { 0x60,  8 },
232                 [SCFCR]         = { 0x18, 16 },
233                 [SCFDR]         = sci_reg_invalid,
234                 [SCTFDR]        = { 0x38, 16 },
235                 [SCRFDR]        = { 0x3c, 16 },
236                 [SCSPTR]        = sci_reg_invalid,
237                 [SCLSR]         = sci_reg_invalid,
238                 [HSSRR]         = sci_reg_invalid,
239                 [SCPCR]         = { 0x30, 16 },
240                 [SCPDR]         = { 0x34, 16 },
241                 [SCDL]          = sci_reg_invalid,
242                 [SCCKS]         = sci_reg_invalid,
243         },
244 
245         /*
246          * Common SH-2(A) SCIF definitions for ports with FIFO data
247          * count registers.
248          */
249         [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
250                 [SCSMR]         = { 0x00, 16 },
251                 [SCBRR]         = { 0x04,  8 },
252                 [SCSCR]         = { 0x08, 16 },
253                 [SCxTDR]        = { 0x0c,  8 },
254                 [SCxSR]         = { 0x10, 16 },
255                 [SCxRDR]        = { 0x14,  8 },
256                 [SCFCR]         = { 0x18, 16 },
257                 [SCFDR]         = { 0x1c, 16 },
258                 [SCTFDR]        = sci_reg_invalid,
259                 [SCRFDR]        = sci_reg_invalid,
260                 [SCSPTR]        = { 0x20, 16 },
261                 [SCLSR]         = { 0x24, 16 },
262                 [HSSRR]         = sci_reg_invalid,
263                 [SCPCR]         = sci_reg_invalid,
264                 [SCPDR]         = sci_reg_invalid,
265                 [SCDL]          = sci_reg_invalid,
266                 [SCCKS]         = sci_reg_invalid,
267         },
268 
269         /*
270          * Common SH-3 SCIF definitions.
271          */
272         [SCIx_SH3_SCIF_REGTYPE] = {
273                 [SCSMR]         = { 0x00,  8 },
274                 [SCBRR]         = { 0x02,  8 },
275                 [SCSCR]         = { 0x04,  8 },
276                 [SCxTDR]        = { 0x06,  8 },
277                 [SCxSR]         = { 0x08, 16 },
278                 [SCxRDR]        = { 0x0a,  8 },
279                 [SCFCR]         = { 0x0c,  8 },
280                 [SCFDR]         = { 0x0e, 16 },
281                 [SCTFDR]        = sci_reg_invalid,
282                 [SCRFDR]        = sci_reg_invalid,
283                 [SCSPTR]        = sci_reg_invalid,
284                 [SCLSR]         = sci_reg_invalid,
285                 [HSSRR]         = sci_reg_invalid,
286                 [SCPCR]         = sci_reg_invalid,
287                 [SCPDR]         = sci_reg_invalid,
288                 [SCDL]          = sci_reg_invalid,
289                 [SCCKS]         = sci_reg_invalid,
290         },
291 
292         /*
293          * Common SH-4(A) SCIF(B) definitions.
294          */
295         [SCIx_SH4_SCIF_REGTYPE] = {
296                 [SCSMR]         = { 0x00, 16 },
297                 [SCBRR]         = { 0x04,  8 },
298                 [SCSCR]         = { 0x08, 16 },
299                 [SCxTDR]        = { 0x0c,  8 },
300                 [SCxSR]         = { 0x10, 16 },
301                 [SCxRDR]        = { 0x14,  8 },
302                 [SCFCR]         = { 0x18, 16 },
303                 [SCFDR]         = { 0x1c, 16 },
304                 [SCTFDR]        = sci_reg_invalid,
305                 [SCRFDR]        = sci_reg_invalid,
306                 [SCSPTR]        = { 0x20, 16 },
307                 [SCLSR]         = { 0x24, 16 },
308                 [HSSRR]         = sci_reg_invalid,
309                 [SCPCR]         = sci_reg_invalid,
310                 [SCPDR]         = sci_reg_invalid,
311                 [SCDL]          = sci_reg_invalid,
312                 [SCCKS]         = sci_reg_invalid,
313         },
314 
315         /*
316          * Common SCIF definitions for ports with a Baud Rate Generator for
317          * External Clock (BRG).
318          */
319         [SCIx_SH4_SCIF_BRG_REGTYPE] = {
320                 [SCSMR]         = { 0x00, 16 },
321                 [SCBRR]         = { 0x04,  8 },
322                 [SCSCR]         = { 0x08, 16 },
323                 [SCxTDR]        = { 0x0c,  8 },
324                 [SCxSR]         = { 0x10, 16 },
325                 [SCxRDR]        = { 0x14,  8 },
326                 [SCFCR]         = { 0x18, 16 },
327                 [SCFDR]         = { 0x1c, 16 },
328                 [SCTFDR]        = sci_reg_invalid,
329                 [SCRFDR]        = sci_reg_invalid,
330                 [SCSPTR]        = { 0x20, 16 },
331                 [SCLSR]         = { 0x24, 16 },
332                 [HSSRR]         = sci_reg_invalid,
333                 [SCPCR]         = sci_reg_invalid,
334                 [SCPDR]         = sci_reg_invalid,
335                 [SCDL]          = { 0x30, 16 },
336                 [SCCKS]         = { 0x34, 16 },
337         },
338 
339         /*
340          * Common HSCIF definitions.
341          */
342         [SCIx_HSCIF_REGTYPE] = {
343                 [SCSMR]         = { 0x00, 16 },
344                 [SCBRR]         = { 0x04,  8 },
345                 [SCSCR]         = { 0x08, 16 },
346                 [SCxTDR]        = { 0x0c,  8 },
347                 [SCxSR]         = { 0x10, 16 },
348                 [SCxRDR]        = { 0x14,  8 },
349                 [SCFCR]         = { 0x18, 16 },
350                 [SCFDR]         = { 0x1c, 16 },
351                 [SCTFDR]        = sci_reg_invalid,
352                 [SCRFDR]        = sci_reg_invalid,
353                 [SCSPTR]        = { 0x20, 16 },
354                 [SCLSR]         = { 0x24, 16 },
355                 [HSSRR]         = { 0x40, 16 },
356                 [SCPCR]         = sci_reg_invalid,
357                 [SCPDR]         = sci_reg_invalid,
358                 [SCDL]          = { 0x30, 16 },
359                 [SCCKS]         = { 0x34, 16 },
360         },
361 
362         /*
363          * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
364          * register.
365          */
366         [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
367                 [SCSMR]         = { 0x00, 16 },
368                 [SCBRR]         = { 0x04,  8 },
369                 [SCSCR]         = { 0x08, 16 },
370                 [SCxTDR]        = { 0x0c,  8 },
371                 [SCxSR]         = { 0x10, 16 },
372                 [SCxRDR]        = { 0x14,  8 },
373                 [SCFCR]         = { 0x18, 16 },
374                 [SCFDR]         = { 0x1c, 16 },
375                 [SCTFDR]        = sci_reg_invalid,
376                 [SCRFDR]        = sci_reg_invalid,
377                 [SCSPTR]        = sci_reg_invalid,
378                 [SCLSR]         = { 0x24, 16 },
379                 [HSSRR]         = sci_reg_invalid,
380                 [SCPCR]         = sci_reg_invalid,
381                 [SCPDR]         = sci_reg_invalid,
382                 [SCDL]          = sci_reg_invalid,
383                 [SCCKS]         = sci_reg_invalid,
384         },
385 
386         /*
387          * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
388          * count registers.
389          */
390         [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
391                 [SCSMR]         = { 0x00, 16 },
392                 [SCBRR]         = { 0x04,  8 },
393                 [SCSCR]         = { 0x08, 16 },
394                 [SCxTDR]        = { 0x0c,  8 },
395                 [SCxSR]         = { 0x10, 16 },
396                 [SCxRDR]        = { 0x14,  8 },
397                 [SCFCR]         = { 0x18, 16 },
398                 [SCFDR]         = { 0x1c, 16 },
399                 [SCTFDR]        = { 0x1c, 16 }, /* aliased to SCFDR */
400                 [SCRFDR]        = { 0x20, 16 },
401                 [SCSPTR]        = { 0x24, 16 },
402                 [SCLSR]         = { 0x28, 16 },
403                 [HSSRR]         = sci_reg_invalid,
404                 [SCPCR]         = sci_reg_invalid,
405                 [SCPDR]         = sci_reg_invalid,
406                 [SCDL]          = sci_reg_invalid,
407                 [SCCKS]         = sci_reg_invalid,
408         },
409 
410         /*
411          * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
412          * registers.
413          */
414         [SCIx_SH7705_SCIF_REGTYPE] = {
415                 [SCSMR]         = { 0x00, 16 },
416                 [SCBRR]         = { 0x04,  8 },
417                 [SCSCR]         = { 0x08, 16 },
418                 [SCxTDR]        = { 0x20,  8 },
419                 [SCxSR]         = { 0x14, 16 },
420                 [SCxRDR]        = { 0x24,  8 },
421                 [SCFCR]         = { 0x18, 16 },
422                 [SCFDR]         = { 0x1c, 16 },
423                 [SCTFDR]        = sci_reg_invalid,
424                 [SCRFDR]        = sci_reg_invalid,
425                 [SCSPTR]        = sci_reg_invalid,
426                 [SCLSR]         = sci_reg_invalid,
427                 [HSSRR]         = sci_reg_invalid,
428                 [SCPCR]         = sci_reg_invalid,
429                 [SCPDR]         = sci_reg_invalid,
430                 [SCDL]          = sci_reg_invalid,
431                 [SCCKS]         = sci_reg_invalid,
432         },
433 };
434 
435 #define sci_getreg(up, offset)          (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
436 
437 /*
438  * The "offset" here is rather misleading, in that it refers to an enum
439  * value relative to the port mapping rather than the fixed offset
440  * itself, which needs to be manually retrieved from the platform's
441  * register map for the given port.
442  */
443 static unsigned int sci_serial_in(struct uart_port *p, int offset)
444 {
445         const struct plat_sci_reg *reg = sci_getreg(p, offset);
446 
447         if (reg->size == 8)
448                 return ioread8(p->membase + (reg->offset << p->regshift));
449         else if (reg->size == 16)
450                 return ioread16(p->membase + (reg->offset << p->regshift));
451         else
452                 WARN(1, "Invalid register access\n");
453 
454         return 0;
455 }
456 
457 static void sci_serial_out(struct uart_port *p, int offset, int value)
458 {
459         const struct plat_sci_reg *reg = sci_getreg(p, offset);
460 
461         if (reg->size == 8)
462                 iowrite8(value, p->membase + (reg->offset << p->regshift));
463         else if (reg->size == 16)
464                 iowrite16(value, p->membase + (reg->offset << p->regshift));
465         else
466                 WARN(1, "Invalid register access\n");
467 }
468 
469 static int sci_probe_regmap(struct plat_sci_port *cfg)
470 {
471         switch (cfg->type) {
472         case PORT_SCI:
473                 cfg->regtype = SCIx_SCI_REGTYPE;
474                 break;
475         case PORT_IRDA:
476                 cfg->regtype = SCIx_IRDA_REGTYPE;
477                 break;
478         case PORT_SCIFA:
479                 cfg->regtype = SCIx_SCIFA_REGTYPE;
480                 break;
481         case PORT_SCIFB:
482                 cfg->regtype = SCIx_SCIFB_REGTYPE;
483                 break;
484         case PORT_SCIF:
485                 /*
486                  * The SH-4 is a bit of a misnomer here, although that's
487                  * where this particular port layout originated. This
488                  * configuration (or some slight variation thereof)
489                  * remains the dominant model for all SCIFs.
490                  */
491                 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
492                 break;
493         case PORT_HSCIF:
494                 cfg->regtype = SCIx_HSCIF_REGTYPE;
495                 break;
496         default:
497                 pr_err("Can't probe register map for given port\n");
498                 return -EINVAL;
499         }
500 
501         return 0;
502 }
503 
504 static void sci_port_enable(struct sci_port *sci_port)
505 {
506         unsigned int i;
507 
508         if (!sci_port->port.dev)
509                 return;
510 
511         pm_runtime_get_sync(sci_port->port.dev);
512 
513         for (i = 0; i < SCI_NUM_CLKS; i++) {
514                 clk_prepare_enable(sci_port->clks[i]);
515                 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
516         }
517         sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
518 }
519 
520 static void sci_port_disable(struct sci_port *sci_port)
521 {
522         unsigned int i;
523 
524         if (!sci_port->port.dev)
525                 return;
526 
527         /* Cancel the break timer to ensure that the timer handler will not try
528          * to access the hardware with clocks and power disabled. Reset the
529          * break flag to make the break debouncing state machine ready for the
530          * next break.
531          */
532         del_timer_sync(&sci_port->break_timer);
533         sci_port->break_flag = 0;
534 
535         for (i = SCI_NUM_CLKS; i-- > 0; )
536                 clk_disable_unprepare(sci_port->clks[i]);
537 
538         pm_runtime_put_sync(sci_port->port.dev);
539 }
540 
541 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
542 {
543         /*
544          * Not all ports (such as SCIFA) will support REIE. Rather than
545          * special-casing the port type, we check the port initialization
546          * IRQ enable mask to see whether the IRQ is desired at all. If
547          * it's unset, it's logically inferred that there's no point in
548          * testing for it.
549          */
550         return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
551 }
552 
553 static void sci_start_tx(struct uart_port *port)
554 {
555         struct sci_port *s = to_sci_port(port);
556         unsigned short ctrl;
557 
558 #ifdef CONFIG_SERIAL_SH_SCI_DMA
559         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
560                 u16 new, scr = serial_port_in(port, SCSCR);
561                 if (s->chan_tx)
562                         new = scr | SCSCR_TDRQE;
563                 else
564                         new = scr & ~SCSCR_TDRQE;
565                 if (new != scr)
566                         serial_port_out(port, SCSCR, new);
567         }
568 
569         if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
570             dma_submit_error(s->cookie_tx)) {
571                 s->cookie_tx = 0;
572                 schedule_work(&s->work_tx);
573         }
574 #endif
575 
576         if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
577                 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
578                 ctrl = serial_port_in(port, SCSCR);
579                 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
580         }
581 }
582 
583 static void sci_stop_tx(struct uart_port *port)
584 {
585         unsigned short ctrl;
586 
587         /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
588         ctrl = serial_port_in(port, SCSCR);
589 
590         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
591                 ctrl &= ~SCSCR_TDRQE;
592 
593         ctrl &= ~SCSCR_TIE;
594 
595         serial_port_out(port, SCSCR, ctrl);
596 }
597 
598 static void sci_start_rx(struct uart_port *port)
599 {
600         unsigned short ctrl;
601 
602         ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
603 
604         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
605                 ctrl &= ~SCSCR_RDRQE;
606 
607         serial_port_out(port, SCSCR, ctrl);
608 }
609 
610 static void sci_stop_rx(struct uart_port *port)
611 {
612         unsigned short ctrl;
613 
614         ctrl = serial_port_in(port, SCSCR);
615 
616         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
617                 ctrl &= ~SCSCR_RDRQE;
618 
619         ctrl &= ~port_rx_irq_mask(port);
620 
621         serial_port_out(port, SCSCR, ctrl);
622 }
623 
624 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
625 {
626         if (port->type == PORT_SCI) {
627                 /* Just store the mask */
628                 serial_port_out(port, SCxSR, mask);
629         } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
630                 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
631                 /* Only clear the status bits we want to clear */
632                 serial_port_out(port, SCxSR,
633                                 serial_port_in(port, SCxSR) & mask);
634         } else {
635                 /* Store the mask, clear parity/framing errors */
636                 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
637         }
638 }
639 
640 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
641 
642 #ifdef CONFIG_CONSOLE_POLL
643 static int sci_poll_get_char(struct uart_port *port)
644 {
645         unsigned short status;
646         int c;
647 
648         do {
649                 status = serial_port_in(port, SCxSR);
650                 if (status & SCxSR_ERRORS(port)) {
651                         sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
652                         continue;
653                 }
654                 break;
655         } while (1);
656 
657         if (!(status & SCxSR_RDxF(port)))
658                 return NO_POLL_CHAR;
659 
660         c = serial_port_in(port, SCxRDR);
661 
662         /* Dummy read */
663         serial_port_in(port, SCxSR);
664         sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
665 
666         return c;
667 }
668 #endif
669 
670 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
671 {
672         unsigned short status;
673 
674         do {
675                 status = serial_port_in(port, SCxSR);
676         } while (!(status & SCxSR_TDxE(port)));
677 
678         serial_port_out(port, SCxTDR, c);
679         sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
680 }
681 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
682 
683 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
684 {
685         struct sci_port *s = to_sci_port(port);
686         const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
687 
688         /*
689          * Use port-specific handler if provided.
690          */
691         if (s->cfg->ops && s->cfg->ops->init_pins) {
692                 s->cfg->ops->init_pins(port, cflag);
693                 return;
694         }
695 
696         /*
697          * For the generic path SCSPTR is necessary. Bail out if that's
698          * unavailable, too.
699          */
700         if (!reg->size)
701                 return;
702 
703         if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
704             ((!(cflag & CRTSCTS)))) {
705                 unsigned short status;
706 
707                 status = serial_port_in(port, SCSPTR);
708                 status &= ~SCSPTR_CTSIO;
709                 status |= SCSPTR_RTSIO;
710                 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
711         }
712 }
713 
714 static int sci_txfill(struct uart_port *port)
715 {
716         const struct plat_sci_reg *reg;
717 
718         reg = sci_getreg(port, SCTFDR);
719         if (reg->size)
720                 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
721 
722         reg = sci_getreg(port, SCFDR);
723         if (reg->size)
724                 return serial_port_in(port, SCFDR) >> 8;
725 
726         return !(serial_port_in(port, SCxSR) & SCI_TDRE);
727 }
728 
729 static int sci_txroom(struct uart_port *port)
730 {
731         return port->fifosize - sci_txfill(port);
732 }
733 
734 static int sci_rxfill(struct uart_port *port)
735 {
736         const struct plat_sci_reg *reg;
737 
738         reg = sci_getreg(port, SCRFDR);
739         if (reg->size)
740                 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
741 
742         reg = sci_getreg(port, SCFDR);
743         if (reg->size)
744                 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
745 
746         return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
747 }
748 
749 /*
750  * SCI helper for checking the state of the muxed port/RXD pins.
751  */
752 static inline int sci_rxd_in(struct uart_port *port)
753 {
754         struct sci_port *s = to_sci_port(port);
755 
756         if (s->cfg->port_reg <= 0)
757                 return 1;
758 
759         /* Cast for ARM damage */
760         return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
761 }
762 
763 /* ********************************************************************** *
764  *                   the interrupt related routines                       *
765  * ********************************************************************** */
766 
767 static void sci_transmit_chars(struct uart_port *port)
768 {
769         struct circ_buf *xmit = &port->state->xmit;
770         unsigned int stopped = uart_tx_stopped(port);
771         unsigned short status;
772         unsigned short ctrl;
773         int count;
774 
775         status = serial_port_in(port, SCxSR);
776         if (!(status & SCxSR_TDxE(port))) {
777                 ctrl = serial_port_in(port, SCSCR);
778                 if (uart_circ_empty(xmit))
779                         ctrl &= ~SCSCR_TIE;
780                 else
781                         ctrl |= SCSCR_TIE;
782                 serial_port_out(port, SCSCR, ctrl);
783                 return;
784         }
785 
786         count = sci_txroom(port);
787 
788         do {
789                 unsigned char c;
790 
791                 if (port->x_char) {
792                         c = port->x_char;
793                         port->x_char = 0;
794                 } else if (!uart_circ_empty(xmit) && !stopped) {
795                         c = xmit->buf[xmit->tail];
796                         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
797                 } else {
798                         break;
799                 }
800 
801                 serial_port_out(port, SCxTDR, c);
802 
803                 port->icount.tx++;
804         } while (--count > 0);
805 
806         sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
807 
808         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
809                 uart_write_wakeup(port);
810         if (uart_circ_empty(xmit)) {
811                 sci_stop_tx(port);
812         } else {
813                 ctrl = serial_port_in(port, SCSCR);
814 
815                 if (port->type != PORT_SCI) {
816                         serial_port_in(port, SCxSR); /* Dummy read */
817                         sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
818                 }
819 
820                 ctrl |= SCSCR_TIE;
821                 serial_port_out(port, SCSCR, ctrl);
822         }
823 }
824 
825 /* On SH3, SCIF may read end-of-break as a space->mark char */
826 #define STEPFN(c)  ({int __c = (c); (((__c-1)|(__c)) == -1); })
827 
828 static void sci_receive_chars(struct uart_port *port)
829 {
830         struct sci_port *sci_port = to_sci_port(port);
831         struct tty_port *tport = &port->state->port;
832         int i, count, copied = 0;
833         unsigned short status;
834         unsigned char flag;
835 
836         status = serial_port_in(port, SCxSR);
837         if (!(status & SCxSR_RDxF(port)))
838                 return;
839 
840         while (1) {
841                 /* Don't copy more bytes than there is room for in the buffer */
842                 count = tty_buffer_request_room(tport, sci_rxfill(port));
843 
844                 /* If for any reason we can't copy more data, we're done! */
845                 if (count == 0)
846                         break;
847 
848                 if (port->type == PORT_SCI) {
849                         char c = serial_port_in(port, SCxRDR);
850                         if (uart_handle_sysrq_char(port, c) ||
851                             sci_port->break_flag)
852                                 count = 0;
853                         else
854                                 tty_insert_flip_char(tport, c, TTY_NORMAL);
855                 } else {
856                         for (i = 0; i < count; i++) {
857                                 char c = serial_port_in(port, SCxRDR);
858 
859                                 status = serial_port_in(port, SCxSR);
860 #if defined(CONFIG_CPU_SH3)
861                                 /* Skip "chars" during break */
862                                 if (sci_port->break_flag) {
863                                         if ((c == 0) &&
864                                             (status & SCxSR_FER(port))) {
865                                                 count--; i--;
866                                                 continue;
867                                         }
868 
869                                         /* Nonzero => end-of-break */
870                                         dev_dbg(port->dev, "debounce<%02x>\n", c);
871                                         sci_port->break_flag = 0;
872 
873                                         if (STEPFN(c)) {
874                                                 count--; i--;
875                                                 continue;
876                                         }
877                                 }
878 #endif /* CONFIG_CPU_SH3 */
879                                 if (uart_handle_sysrq_char(port, c)) {
880                                         count--; i--;
881                                         continue;
882                                 }
883 
884                                 /* Store data and status */
885                                 if (status & SCxSR_FER(port)) {
886                                         flag = TTY_FRAME;
887                                         port->icount.frame++;
888                                         dev_notice(port->dev, "frame error\n");
889                                 } else if (status & SCxSR_PER(port)) {
890                                         flag = TTY_PARITY;
891                                         port->icount.parity++;
892                                         dev_notice(port->dev, "parity error\n");
893                                 } else
894                                         flag = TTY_NORMAL;
895 
896                                 tty_insert_flip_char(tport, c, flag);
897                         }
898                 }
899 
900                 serial_port_in(port, SCxSR); /* dummy read */
901                 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
902 
903                 copied += count;
904                 port->icount.rx += count;
905         }
906 
907         if (copied) {
908                 /* Tell the rest of the system the news. New characters! */
909                 tty_flip_buffer_push(tport);
910         } else {
911                 serial_port_in(port, SCxSR); /* dummy read */
912                 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
913         }
914 }
915 
916 #define SCI_BREAK_JIFFIES (HZ/20)
917 
918 /*
919  * The sci generates interrupts during the break,
920  * 1 per millisecond or so during the break period, for 9600 baud.
921  * So dont bother disabling interrupts.
922  * But dont want more than 1 break event.
923  * Use a kernel timer to periodically poll the rx line until
924  * the break is finished.
925  */
926 static inline void sci_schedule_break_timer(struct sci_port *port)
927 {
928         mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
929 }
930 
931 /* Ensure that two consecutive samples find the break over. */
932 static void sci_break_timer(unsigned long data)
933 {
934         struct sci_port *port = (struct sci_port *)data;
935 
936         if (sci_rxd_in(&port->port) == 0) {
937                 port->break_flag = 1;
938                 sci_schedule_break_timer(port);
939         } else if (port->break_flag == 1) {
940                 /* break is over. */
941                 port->break_flag = 2;
942                 sci_schedule_break_timer(port);
943         } else
944                 port->break_flag = 0;
945 }
946 
947 static int sci_handle_errors(struct uart_port *port)
948 {
949         int copied = 0;
950         unsigned short status = serial_port_in(port, SCxSR);
951         struct tty_port *tport = &port->state->port;
952         struct sci_port *s = to_sci_port(port);
953 
954         /* Handle overruns */
955         if (status & s->overrun_mask) {
956                 port->icount.overrun++;
957 
958                 /* overrun error */
959                 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
960                         copied++;
961 
962                 dev_notice(port->dev, "overrun error\n");
963         }
964 
965         if (status & SCxSR_FER(port)) {
966                 if (sci_rxd_in(port) == 0) {
967                         /* Notify of BREAK */
968                         struct sci_port *sci_port = to_sci_port(port);
969 
970                         if (!sci_port->break_flag) {
971                                 port->icount.brk++;
972 
973                                 sci_port->break_flag = 1;
974                                 sci_schedule_break_timer(sci_port);
975 
976                                 /* Do sysrq handling. */
977                                 if (uart_handle_break(port))
978                                         return 0;
979 
980                                 dev_dbg(port->dev, "BREAK detected\n");
981 
982                                 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
983                                         copied++;
984                         }
985 
986                 } else {
987                         /* frame error */
988                         port->icount.frame++;
989 
990                         if (tty_insert_flip_char(tport, 0, TTY_FRAME))
991                                 copied++;
992 
993                         dev_notice(port->dev, "frame error\n");
994                 }
995         }
996 
997         if (status & SCxSR_PER(port)) {
998                 /* parity error */
999                 port->icount.parity++;
1000 
1001                 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1002                         copied++;
1003 
1004                 dev_notice(port->dev, "parity error\n");
1005         }
1006 
1007         if (copied)
1008                 tty_flip_buffer_push(tport);
1009 
1010         return copied;
1011 }
1012 
1013 static int sci_handle_fifo_overrun(struct uart_port *port)
1014 {
1015         struct tty_port *tport = &port->state->port;
1016         struct sci_port *s = to_sci_port(port);
1017         const struct plat_sci_reg *reg;
1018         int copied = 0;
1019         u16 status;
1020 
1021         reg = sci_getreg(port, s->overrun_reg);
1022         if (!reg->size)
1023                 return 0;
1024 
1025         status = serial_port_in(port, s->overrun_reg);
1026         if (status & s->overrun_mask) {
1027                 status &= ~s->overrun_mask;
1028                 serial_port_out(port, s->overrun_reg, status);
1029 
1030                 port->icount.overrun++;
1031 
1032                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1033                 tty_flip_buffer_push(tport);
1034 
1035                 dev_dbg(port->dev, "overrun error\n");
1036                 copied++;
1037         }
1038 
1039         return copied;
1040 }
1041 
1042 static int sci_handle_breaks(struct uart_port *port)
1043 {
1044         int copied = 0;
1045         unsigned short status = serial_port_in(port, SCxSR);
1046         struct tty_port *tport = &port->state->port;
1047         struct sci_port *s = to_sci_port(port);
1048 
1049         if (uart_handle_break(port))
1050                 return 0;
1051 
1052         if (!s->break_flag && status & SCxSR_BRK(port)) {
1053 #if defined(CONFIG_CPU_SH3)
1054                 /* Debounce break */
1055                 s->break_flag = 1;
1056 #endif
1057 
1058                 port->icount.brk++;
1059 
1060                 /* Notify of BREAK */
1061                 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1062                         copied++;
1063 
1064                 dev_dbg(port->dev, "BREAK detected\n");
1065         }
1066 
1067         if (copied)
1068                 tty_flip_buffer_push(tport);
1069 
1070         copied += sci_handle_fifo_overrun(port);
1071 
1072         return copied;
1073 }
1074 
1075 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1076 static void sci_dma_tx_complete(void *arg)
1077 {
1078         struct sci_port *s = arg;
1079         struct uart_port *port = &s->port;
1080         struct circ_buf *xmit = &port->state->xmit;
1081         unsigned long flags;
1082 
1083         dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1084 
1085         spin_lock_irqsave(&port->lock, flags);
1086 
1087         xmit->tail += s->tx_dma_len;
1088         xmit->tail &= UART_XMIT_SIZE - 1;
1089 
1090         port->icount.tx += s->tx_dma_len;
1091 
1092         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1093                 uart_write_wakeup(port);
1094 
1095         if (!uart_circ_empty(xmit)) {
1096                 s->cookie_tx = 0;
1097                 schedule_work(&s->work_tx);
1098         } else {
1099                 s->cookie_tx = -EINVAL;
1100                 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1101                         u16 ctrl = serial_port_in(port, SCSCR);
1102                         serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1103                 }
1104         }
1105 
1106         spin_unlock_irqrestore(&port->lock, flags);
1107 }
1108 
1109 /* Locking: called with port lock held */
1110 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1111 {
1112         struct uart_port *port = &s->port;
1113         struct tty_port *tport = &port->state->port;
1114         int copied;
1115 
1116         copied = tty_insert_flip_string(tport, buf, count);
1117         if (copied < count) {
1118                 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1119                          count - copied);
1120                 port->icount.buf_overrun++;
1121         }
1122 
1123         port->icount.rx += copied;
1124 
1125         return copied;
1126 }
1127 
1128 static int sci_dma_rx_find_active(struct sci_port *s)
1129 {
1130         unsigned int i;
1131 
1132         for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1133                 if (s->active_rx == s->cookie_rx[i])
1134                         return i;
1135 
1136         dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1137                 s->active_rx);
1138         return -1;
1139 }
1140 
1141 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1142 {
1143         struct dma_chan *chan = s->chan_rx;
1144         struct uart_port *port = &s->port;
1145         unsigned long flags;
1146 
1147         spin_lock_irqsave(&port->lock, flags);
1148         s->chan_rx = NULL;
1149         s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1150         spin_unlock_irqrestore(&port->lock, flags);
1151         dmaengine_terminate_all(chan);
1152         dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1153                           sg_dma_address(&s->sg_rx[0]));
1154         dma_release_channel(chan);
1155         if (enable_pio)
1156                 sci_start_rx(port);
1157 }
1158 
1159 static void sci_dma_rx_complete(void *arg)
1160 {
1161         struct sci_port *s = arg;
1162         struct dma_chan *chan = s->chan_rx;
1163         struct uart_port *port = &s->port;
1164         struct dma_async_tx_descriptor *desc;
1165         unsigned long flags;
1166         int active, count = 0;
1167 
1168         dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1169                 s->active_rx);
1170 
1171         spin_lock_irqsave(&port->lock, flags);
1172 
1173         active = sci_dma_rx_find_active(s);
1174         if (active >= 0)
1175                 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1176 
1177         mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1178 
1179         if (count)
1180                 tty_flip_buffer_push(&port->state->port);
1181 
1182         desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1183                                        DMA_DEV_TO_MEM,
1184                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1185         if (!desc)
1186                 goto fail;
1187 
1188         desc->callback = sci_dma_rx_complete;
1189         desc->callback_param = s;
1190         s->cookie_rx[active] = dmaengine_submit(desc);
1191         if (dma_submit_error(s->cookie_rx[active]))
1192                 goto fail;
1193 
1194         s->active_rx = s->cookie_rx[!active];
1195 
1196         dma_async_issue_pending(chan);
1197 
1198         dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1199                 __func__, s->cookie_rx[active], active, s->active_rx);
1200         spin_unlock_irqrestore(&port->lock, flags);
1201         return;
1202 
1203 fail:
1204         spin_unlock_irqrestore(&port->lock, flags);
1205         dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1206         sci_rx_dma_release(s, true);
1207 }
1208 
1209 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1210 {
1211         struct dma_chan *chan = s->chan_tx;
1212         struct uart_port *port = &s->port;
1213         unsigned long flags;
1214 
1215         spin_lock_irqsave(&port->lock, flags);
1216         s->chan_tx = NULL;
1217         s->cookie_tx = -EINVAL;
1218         spin_unlock_irqrestore(&port->lock, flags);
1219         dmaengine_terminate_all(chan);
1220         dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1221                          DMA_TO_DEVICE);
1222         dma_release_channel(chan);
1223         if (enable_pio)
1224                 sci_start_tx(port);
1225 }
1226 
1227 static void sci_submit_rx(struct sci_port *s)
1228 {
1229         struct dma_chan *chan = s->chan_rx;
1230         int i;
1231 
1232         for (i = 0; i < 2; i++) {
1233                 struct scatterlist *sg = &s->sg_rx[i];
1234                 struct dma_async_tx_descriptor *desc;
1235 
1236                 desc = dmaengine_prep_slave_sg(chan,
1237                         sg, 1, DMA_DEV_TO_MEM,
1238                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1239                 if (!desc)
1240                         goto fail;
1241 
1242                 desc->callback = sci_dma_rx_complete;
1243                 desc->callback_param = s;
1244                 s->cookie_rx[i] = dmaengine_submit(desc);
1245                 if (dma_submit_error(s->cookie_rx[i]))
1246                         goto fail;
1247 
1248                 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1249                         s->cookie_rx[i], i);
1250         }
1251 
1252         s->active_rx = s->cookie_rx[0];
1253 
1254         dma_async_issue_pending(chan);
1255         return;
1256 
1257 fail:
1258         if (i)
1259                 dmaengine_terminate_all(chan);
1260         for (i = 0; i < 2; i++)
1261                 s->cookie_rx[i] = -EINVAL;
1262         s->active_rx = -EINVAL;
1263         dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1264         sci_rx_dma_release(s, true);
1265 }
1266 
1267 static void work_fn_tx(struct work_struct *work)
1268 {
1269         struct sci_port *s = container_of(work, struct sci_port, work_tx);
1270         struct dma_async_tx_descriptor *desc;
1271         struct dma_chan *chan = s->chan_tx;
1272         struct uart_port *port = &s->port;
1273         struct circ_buf *xmit = &port->state->xmit;
1274         dma_addr_t buf;
1275 
1276         /*
1277          * DMA is idle now.
1278          * Port xmit buffer is already mapped, and it is one page... Just adjust
1279          * offsets and lengths. Since it is a circular buffer, we have to
1280          * transmit till the end, and then the rest. Take the port lock to get a
1281          * consistent xmit buffer state.
1282          */
1283         spin_lock_irq(&port->lock);
1284         buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1285         s->tx_dma_len = min_t(unsigned int,
1286                 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1287                 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1288         spin_unlock_irq(&port->lock);
1289 
1290         desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1291                                            DMA_MEM_TO_DEV,
1292                                            DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1293         if (!desc) {
1294                 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1295                 /* switch to PIO */
1296                 sci_tx_dma_release(s, true);
1297                 return;
1298         }
1299 
1300         dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1301                                    DMA_TO_DEVICE);
1302 
1303         spin_lock_irq(&port->lock);
1304         desc->callback = sci_dma_tx_complete;
1305         desc->callback_param = s;
1306         spin_unlock_irq(&port->lock);
1307         s->cookie_tx = dmaengine_submit(desc);
1308         if (dma_submit_error(s->cookie_tx)) {
1309                 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1310                 /* switch to PIO */
1311                 sci_tx_dma_release(s, true);
1312                 return;
1313         }
1314 
1315         dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1316                 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1317 
1318         dma_async_issue_pending(chan);
1319 }
1320 
1321 static void rx_timer_fn(unsigned long arg)
1322 {
1323         struct sci_port *s = (struct sci_port *)arg;
1324         struct dma_chan *chan = s->chan_rx;
1325         struct uart_port *port = &s->port;
1326         struct dma_tx_state state;
1327         enum dma_status status;
1328         unsigned long flags;
1329         unsigned int read;
1330         int active, count;
1331         u16 scr;
1332 
1333         spin_lock_irqsave(&port->lock, flags);
1334 
1335         dev_dbg(port->dev, "DMA Rx timed out\n");
1336 
1337         active = sci_dma_rx_find_active(s);
1338         if (active < 0) {
1339                 spin_unlock_irqrestore(&port->lock, flags);
1340                 return;
1341         }
1342 
1343         status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1344         if (status == DMA_COMPLETE) {
1345                 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1346                         s->active_rx, active);
1347                 spin_unlock_irqrestore(&port->lock, flags);
1348 
1349                 /* Let packet complete handler take care of the packet */
1350                 return;
1351         }
1352 
1353         dmaengine_pause(chan);
1354 
1355         /*
1356          * sometimes DMA transfer doesn't stop even if it is stopped and
1357          * data keeps on coming until transaction is complete so check
1358          * for DMA_COMPLETE again
1359          * Let packet complete handler take care of the packet
1360          */
1361         status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1362         if (status == DMA_COMPLETE) {
1363                 spin_unlock_irqrestore(&port->lock, flags);
1364                 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1365                 return;
1366         }
1367 
1368         /* Handle incomplete DMA receive */
1369         dmaengine_terminate_all(s->chan_rx);
1370         read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1371         dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1372                 s->active_rx);
1373 
1374         if (read) {
1375                 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1376                 if (count)
1377                         tty_flip_buffer_push(&port->state->port);
1378         }
1379 
1380         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1381                 sci_submit_rx(s);
1382 
1383         /* Direct new serial port interrupts back to CPU */
1384         scr = serial_port_in(port, SCSCR);
1385         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1386                 scr &= ~SCSCR_RDRQE;
1387                 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1388         }
1389         serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1390 
1391         spin_unlock_irqrestore(&port->lock, flags);
1392 }
1393 
1394 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1395                                              enum dma_transfer_direction dir,
1396                                              unsigned int id)
1397 {
1398         dma_cap_mask_t mask;
1399         struct dma_chan *chan;
1400         struct dma_slave_config cfg;
1401         int ret;
1402 
1403         dma_cap_zero(mask);
1404         dma_cap_set(DMA_SLAVE, mask);
1405 
1406         chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1407                                         (void *)(unsigned long)id, port->dev,
1408                                         dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1409         if (!chan) {
1410                 dev_warn(port->dev,
1411                          "dma_request_slave_channel_compat failed\n");
1412                 return NULL;
1413         }
1414 
1415         memset(&cfg, 0, sizeof(cfg));
1416         cfg.direction = dir;
1417         if (dir == DMA_MEM_TO_DEV) {
1418                 cfg.dst_addr = port->mapbase +
1419                         (sci_getreg(port, SCxTDR)->offset << port->regshift);
1420                 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1421         } else {
1422                 cfg.src_addr = port->mapbase +
1423                         (sci_getreg(port, SCxRDR)->offset << port->regshift);
1424                 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1425         }
1426 
1427         ret = dmaengine_slave_config(chan, &cfg);
1428         if (ret) {
1429                 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1430                 dma_release_channel(chan);
1431                 return NULL;
1432         }
1433 
1434         return chan;
1435 }
1436 
1437 static void sci_request_dma(struct uart_port *port)
1438 {
1439         struct sci_port *s = to_sci_port(port);
1440         struct dma_chan *chan;
1441 
1442         dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1443 
1444         if (!port->dev->of_node &&
1445             (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1446                 return;
1447 
1448         s->cookie_tx = -EINVAL;
1449         chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1450         dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1451         if (chan) {
1452                 s->chan_tx = chan;
1453                 /* UART circular tx buffer is an aligned page. */
1454                 s->tx_dma_addr = dma_map_single(chan->device->dev,
1455                                                 port->state->xmit.buf,
1456                                                 UART_XMIT_SIZE,
1457                                                 DMA_TO_DEVICE);
1458                 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1459                         dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1460                         dma_release_channel(chan);
1461                         s->chan_tx = NULL;
1462                 } else {
1463                         dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1464                                 __func__, UART_XMIT_SIZE,
1465                                 port->state->xmit.buf, &s->tx_dma_addr);
1466                 }
1467 
1468                 INIT_WORK(&s->work_tx, work_fn_tx);
1469         }
1470 
1471         chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1472         dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1473         if (chan) {
1474                 unsigned int i;
1475                 dma_addr_t dma;
1476                 void *buf;
1477 
1478                 s->chan_rx = chan;
1479 
1480                 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1481                 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1482                                          &dma, GFP_KERNEL);
1483                 if (!buf) {
1484                         dev_warn(port->dev,
1485                                  "Failed to allocate Rx dma buffer, using PIO\n");
1486                         dma_release_channel(chan);
1487                         s->chan_rx = NULL;
1488                         return;
1489                 }
1490 
1491                 for (i = 0; i < 2; i++) {
1492                         struct scatterlist *sg = &s->sg_rx[i];
1493 
1494                         sg_init_table(sg, 1);
1495                         s->rx_buf[i] = buf;
1496                         sg_dma_address(sg) = dma;
1497                         sg_dma_len(sg) = s->buf_len_rx;
1498 
1499                         buf += s->buf_len_rx;
1500                         dma += s->buf_len_rx;
1501                 }
1502 
1503                 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1504 
1505                 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1506                         sci_submit_rx(s);
1507         }
1508 }
1509 
1510 static void sci_free_dma(struct uart_port *port)
1511 {
1512         struct sci_port *s = to_sci_port(port);
1513 
1514         if (s->chan_tx)
1515                 sci_tx_dma_release(s, false);
1516         if (s->chan_rx)
1517                 sci_rx_dma_release(s, false);
1518 }
1519 #else
1520 static inline void sci_request_dma(struct uart_port *port)
1521 {
1522 }
1523 
1524 static inline void sci_free_dma(struct uart_port *port)
1525 {
1526 }
1527 #endif
1528 
1529 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1530 {
1531 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1532         struct uart_port *port = ptr;
1533         struct sci_port *s = to_sci_port(port);
1534 
1535         if (s->chan_rx) {
1536                 u16 scr = serial_port_in(port, SCSCR);
1537                 u16 ssr = serial_port_in(port, SCxSR);
1538 
1539                 /* Disable future Rx interrupts */
1540                 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1541                         disable_irq_nosync(irq);
1542                         scr |= SCSCR_RDRQE;
1543                 } else {
1544                         scr &= ~SCSCR_RIE;
1545                         sci_submit_rx(s);
1546                 }
1547                 serial_port_out(port, SCSCR, scr);
1548                 /* Clear current interrupt */
1549                 serial_port_out(port, SCxSR,
1550                                 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1551                 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1552                         jiffies, s->rx_timeout);
1553                 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1554 
1555                 return IRQ_HANDLED;
1556         }
1557 #endif
1558 
1559         /* I think sci_receive_chars has to be called irrespective
1560          * of whether the I_IXOFF is set, otherwise, how is the interrupt
1561          * to be disabled?
1562          */
1563         sci_receive_chars(ptr);
1564 
1565         return IRQ_HANDLED;
1566 }
1567 
1568 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1569 {
1570         struct uart_port *port = ptr;
1571         unsigned long flags;
1572 
1573         spin_lock_irqsave(&port->lock, flags);
1574         sci_transmit_chars(port);
1575         spin_unlock_irqrestore(&port->lock, flags);
1576 
1577         return IRQ_HANDLED;
1578 }
1579 
1580 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1581 {
1582         struct uart_port *port = ptr;
1583         struct sci_port *s = to_sci_port(port);
1584 
1585         /* Handle errors */
1586         if (port->type == PORT_SCI) {
1587                 if (sci_handle_errors(port)) {
1588                         /* discard character in rx buffer */
1589                         serial_port_in(port, SCxSR);
1590                         sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1591                 }
1592         } else {
1593                 sci_handle_fifo_overrun(port);
1594                 if (!s->chan_rx)
1595                         sci_receive_chars(ptr);
1596         }
1597 
1598         sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1599 
1600         /* Kick the transmission */
1601         if (!s->chan_tx)
1602                 sci_tx_interrupt(irq, ptr);
1603 
1604         return IRQ_HANDLED;
1605 }
1606 
1607 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1608 {
1609         struct uart_port *port = ptr;
1610 
1611         /* Handle BREAKs */
1612         sci_handle_breaks(port);
1613         sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1614 
1615         return IRQ_HANDLED;
1616 }
1617 
1618 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1619 {
1620         unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1621         struct uart_port *port = ptr;
1622         struct sci_port *s = to_sci_port(port);
1623         irqreturn_t ret = IRQ_NONE;
1624 
1625         ssr_status = serial_port_in(port, SCxSR);
1626         scr_status = serial_port_in(port, SCSCR);
1627         if (s->overrun_reg == SCxSR)
1628                 orer_status = ssr_status;
1629         else {
1630                 if (sci_getreg(port, s->overrun_reg)->size)
1631                         orer_status = serial_port_in(port, s->overrun_reg);
1632         }
1633 
1634         err_enabled = scr_status & port_rx_irq_mask(port);
1635 
1636         /* Tx Interrupt */
1637         if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1638             !s->chan_tx)
1639                 ret = sci_tx_interrupt(irq, ptr);
1640 
1641         /*
1642          * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1643          * DR flags
1644          */
1645         if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1646             (scr_status & SCSCR_RIE))
1647                 ret = sci_rx_interrupt(irq, ptr);
1648 
1649         /* Error Interrupt */
1650         if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1651                 ret = sci_er_interrupt(irq, ptr);
1652 
1653         /* Break Interrupt */
1654         if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1655                 ret = sci_br_interrupt(irq, ptr);
1656 
1657         /* Overrun Interrupt */
1658         if (orer_status & s->overrun_mask) {
1659                 sci_handle_fifo_overrun(port);
1660                 ret = IRQ_HANDLED;
1661         }
1662 
1663         return ret;
1664 }
1665 
1666 static const struct sci_irq_desc {
1667         const char      *desc;
1668         irq_handler_t   handler;
1669 } sci_irq_desc[] = {
1670         /*
1671          * Split out handlers, the default case.
1672          */
1673         [SCIx_ERI_IRQ] = {
1674                 .desc = "rx err",
1675                 .handler = sci_er_interrupt,
1676         },
1677 
1678         [SCIx_RXI_IRQ] = {
1679                 .desc = "rx full",
1680                 .handler = sci_rx_interrupt,
1681         },
1682 
1683         [SCIx_TXI_IRQ] = {
1684                 .desc = "tx empty",
1685                 .handler = sci_tx_interrupt,
1686         },
1687 
1688         [SCIx_BRI_IRQ] = {
1689                 .desc = "break",
1690                 .handler = sci_br_interrupt,
1691         },
1692 
1693         /*
1694          * Special muxed handler.
1695          */
1696         [SCIx_MUX_IRQ] = {
1697                 .desc = "mux",
1698                 .handler = sci_mpxed_interrupt,
1699         },
1700 };
1701 
1702 static int sci_request_irq(struct sci_port *port)
1703 {
1704         struct uart_port *up = &port->port;
1705         int i, j, ret = 0;
1706 
1707         for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1708                 const struct sci_irq_desc *desc;
1709                 int irq;
1710 
1711                 if (SCIx_IRQ_IS_MUXED(port)) {
1712                         i = SCIx_MUX_IRQ;
1713                         irq = up->irq;
1714                 } else {
1715                         irq = port->irqs[i];
1716 
1717                         /*
1718                          * Certain port types won't support all of the
1719                          * available interrupt sources.
1720                          */
1721                         if (unlikely(irq < 0))
1722                                 continue;
1723                 }
1724 
1725                 desc = sci_irq_desc + i;
1726                 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1727                                             dev_name(up->dev), desc->desc);
1728                 if (!port->irqstr[j])
1729                         goto out_nomem;
1730 
1731                 ret = request_irq(irq, desc->handler, up->irqflags,
1732                                   port->irqstr[j], port);
1733                 if (unlikely(ret)) {
1734                         dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1735                         goto out_noirq;
1736                 }
1737         }
1738 
1739         return 0;
1740 
1741 out_noirq:
1742         while (--i >= 0)
1743                 free_irq(port->irqs[i], port);
1744 
1745 out_nomem:
1746         while (--j >= 0)
1747                 kfree(port->irqstr[j]);
1748 
1749         return ret;
1750 }
1751 
1752 static void sci_free_irq(struct sci_port *port)
1753 {
1754         int i;
1755 
1756         /*
1757          * Intentionally in reverse order so we iterate over the muxed
1758          * IRQ first.
1759          */
1760         for (i = 0; i < SCIx_NR_IRQS; i++) {
1761                 int irq = port->irqs[i];
1762 
1763                 /*
1764                  * Certain port types won't support all of the available
1765                  * interrupt sources.
1766                  */
1767                 if (unlikely(irq < 0))
1768                         continue;
1769 
1770                 free_irq(port->irqs[i], port);
1771                 kfree(port->irqstr[i]);
1772 
1773                 if (SCIx_IRQ_IS_MUXED(port)) {
1774                         /* If there's only one IRQ, we're done. */
1775                         return;
1776                 }
1777         }
1778 }
1779 
1780 static unsigned int sci_tx_empty(struct uart_port *port)
1781 {
1782         unsigned short status = serial_port_in(port, SCxSR);
1783         unsigned short in_tx_fifo = sci_txfill(port);
1784 
1785         return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1786 }
1787 
1788 /*
1789  * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1790  * CTS/RTS is supported in hardware by at least one port and controlled
1791  * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1792  * handled via the ->init_pins() op, which is a bit of a one-way street,
1793  * lacking any ability to defer pin control -- this will later be
1794  * converted over to the GPIO framework).
1795  *
1796  * Other modes (such as loopback) are supported generically on certain
1797  * port types, but not others. For these it's sufficient to test for the
1798  * existence of the support register and simply ignore the port type.
1799  */
1800 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1801 {
1802         if (mctrl & TIOCM_LOOP) {
1803                 const struct plat_sci_reg *reg;
1804 
1805                 /*
1806                  * Standard loopback mode for SCFCR ports.
1807                  */
1808                 reg = sci_getreg(port, SCFCR);
1809                 if (reg->size)
1810                         serial_port_out(port, SCFCR,
1811                                         serial_port_in(port, SCFCR) |
1812                                         SCFCR_LOOP);
1813         }
1814 }
1815 
1816 static unsigned int sci_get_mctrl(struct uart_port *port)
1817 {
1818         /*
1819          * CTS/RTS is handled in hardware when supported, while nothing
1820          * else is wired up. Keep it simple and simply assert DSR/CAR.
1821          */
1822         return TIOCM_DSR | TIOCM_CAR;
1823 }
1824 
1825 static void sci_break_ctl(struct uart_port *port, int break_state)
1826 {
1827         struct sci_port *s = to_sci_port(port);
1828         const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1829         unsigned short scscr, scsptr;
1830 
1831         /* check wheter the port has SCSPTR */
1832         if (!reg->size) {
1833                 /*
1834                  * Not supported by hardware. Most parts couple break and rx
1835                  * interrupts together, with break detection always enabled.
1836                  */
1837                 return;
1838         }
1839 
1840         scsptr = serial_port_in(port, SCSPTR);
1841         scscr = serial_port_in(port, SCSCR);
1842 
1843         if (break_state == -1) {
1844                 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1845                 scscr &= ~SCSCR_TE;
1846         } else {
1847                 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1848                 scscr |= SCSCR_TE;
1849         }
1850 
1851         serial_port_out(port, SCSPTR, scsptr);
1852         serial_port_out(port, SCSCR, scscr);
1853 }
1854 
1855 static int sci_startup(struct uart_port *port)
1856 {
1857         struct sci_port *s = to_sci_port(port);
1858         unsigned long flags;
1859         int ret;
1860 
1861         dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1862 
1863         ret = sci_request_irq(s);
1864         if (unlikely(ret < 0))
1865                 return ret;
1866 
1867         sci_request_dma(port);
1868 
1869         spin_lock_irqsave(&port->lock, flags);
1870         sci_start_tx(port);
1871         sci_start_rx(port);
1872         spin_unlock_irqrestore(&port->lock, flags);
1873 
1874         return 0;
1875 }
1876 
1877 static void sci_shutdown(struct uart_port *port)
1878 {
1879         struct sci_port *s = to_sci_port(port);
1880         unsigned long flags;
1881 
1882         dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1883 
1884         spin_lock_irqsave(&port->lock, flags);
1885         sci_stop_rx(port);
1886         sci_stop_tx(port);
1887         spin_unlock_irqrestore(&port->lock, flags);
1888 
1889 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1890         if (s->chan_rx) {
1891                 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1892                         port->line);
1893                 del_timer_sync(&s->rx_timer);
1894         }
1895 #endif
1896 
1897         sci_free_dma(port);
1898         sci_free_irq(s);
1899 }
1900 
1901 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
1902                         unsigned int *srr)
1903 {
1904         unsigned long freq = s->clk_rates[SCI_SCK];
1905         unsigned int min_sr, max_sr, sr;
1906         int err, min_err = INT_MAX;
1907 
1908         if (s->sampling_rate) {
1909                 /* SCI(F) has a fixed sampling rate */
1910                 min_sr = max_sr = s->sampling_rate / 2;
1911         } else {
1912                 /* HSCIF has a variable 1/(8..32) sampling rate */
1913                 min_sr = 8;
1914                 max_sr = 32;
1915         }
1916 
1917         for (sr = max_sr; sr >= min_sr; sr--) {
1918                 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
1919                 if (abs(err) >= abs(min_err))
1920                         continue;
1921 
1922                 min_err = err;
1923                 *srr = sr - 1;
1924 
1925                 if (!err)
1926                         break;
1927         }
1928 
1929         dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
1930                 *srr + 1);
1931         return min_err;
1932 }
1933 
1934 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
1935                         unsigned long freq, unsigned int *dlr,
1936                         unsigned int *srr)
1937 {
1938         unsigned int min_sr, max_sr, sr, dl;
1939         int err, min_err = INT_MAX;
1940 
1941         if (s->sampling_rate) {
1942                 /* SCIF has a fixed sampling rate */
1943                 min_sr = max_sr = s->sampling_rate / 2;
1944         } else {
1945                 /* HSCIF has a variable 1/(8..32) sampling rate */
1946                 min_sr = 8;
1947                 max_sr = 32;
1948         }
1949 
1950         for (sr = max_sr; sr >= min_sr; sr--) {
1951                 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
1952                 dl = clamp(dl, 1U, 65535U);
1953 
1954                 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
1955                 if (abs(err) >= abs(min_err))
1956                         continue;
1957 
1958                 min_err = err;
1959                 *dlr = dl;
1960                 *srr = sr - 1;
1961 
1962                 if (!err)
1963                         break;
1964         }
1965 
1966         dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
1967                 min_err, *dlr, *srr + 1);
1968         return min_err;
1969 }
1970 
1971 /* calculate sample rate, BRR, and clock select */
1972 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1973                           unsigned int *brr, unsigned int *srr,
1974                           unsigned int *cks)
1975 {
1976         unsigned int min_sr, max_sr, shift, sr, br, prediv, scrate, c;
1977         unsigned long freq = s->clk_rates[SCI_FCK];
1978         int err, min_err = INT_MAX;
1979 
1980         if (s->sampling_rate) {
1981                 min_sr = max_sr = s->sampling_rate;
1982                 shift = 0;
1983         } else {
1984                 /* HSCIF has a variable sample rate */
1985                 min_sr = 8;
1986                 max_sr = 32;
1987                 shift = 1;
1988         }
1989 
1990         /*
1991          * Find the combination of sample rate and clock select with the
1992          * smallest deviation from the desired baud rate.
1993          * Prefer high sample rates to maximise the receive margin.
1994          *
1995          * M: Receive margin (%)
1996          * N: Ratio of bit rate to clock (N = sampling rate)
1997          * D: Clock duty (D = 0 to 1.0)
1998          * L: Frame length (L = 9 to 12)
1999          * F: Absolute value of clock frequency deviation
2000          *
2001          *  M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2002          *      (|D - 0.5| / N * (1 + F))|
2003          *  NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2004          */
2005         for (sr = max_sr; sr >= min_sr; sr--) {
2006                 for (c = 0; c <= 3; c++) {
2007                         /* integerized formulas from HSCIF documentation */
2008                         prediv = sr * (1 << (2 * c + shift));
2009 
2010                         /*
2011                          * We need to calculate:
2012                          *
2013                          *     br = freq / (prediv * bps) clamped to [1..256]
2014                          *     err = freq / (br * prediv) - bps
2015                          *
2016                          * Watch out for overflow when calculating the desired
2017                          * sampling clock rate!
2018                          */
2019                         if (bps > UINT_MAX / prediv)
2020                                 break;
2021 
2022                         scrate = prediv * bps;
2023                         br = DIV_ROUND_CLOSEST(freq, scrate);
2024                         br = clamp(br, 1U, 256U);
2025 
2026                         err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2027                         if (abs(err) >= abs(min_err))
2028                                 continue;
2029 
2030                         min_err = err;
2031                         *brr = br - 1;
2032                         *srr = sr - 1;
2033                         *cks = c;
2034 
2035                         if (!err)
2036                                 goto found;
2037                 }
2038         }
2039 
2040 found:
2041         dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2042                 min_err, *brr, *srr + 1, *cks);
2043         return min_err;
2044 }
2045 
2046 static void sci_reset(struct uart_port *port)
2047 {
2048         const struct plat_sci_reg *reg;
2049         unsigned int status;
2050 
2051         do {
2052                 status = serial_port_in(port, SCxSR);
2053         } while (!(status & SCxSR_TEND(port)));
2054 
2055         serial_port_out(port, SCSCR, 0x00);     /* TE=0, RE=0, CKE1=0 */
2056 
2057         reg = sci_getreg(port, SCFCR);
2058         if (reg->size)
2059                 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2060 }
2061 
2062 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2063                             struct ktermios *old)
2064 {
2065         unsigned int baud, smr_val = 0, scr_val = 0, i;
2066         unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2067         unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2068         struct sci_port *s = to_sci_port(port);
2069         const struct plat_sci_reg *reg;
2070         int min_err = INT_MAX, err;
2071         unsigned long max_freq = 0;
2072         int best_clk = -1;
2073 
2074         if ((termios->c_cflag & CSIZE) == CS7)
2075                 smr_val |= SCSMR_CHR;
2076         if (termios->c_cflag & PARENB)
2077                 smr_val |= SCSMR_PE;
2078         if (termios->c_cflag & PARODD)
2079                 smr_val |= SCSMR_PE | SCSMR_ODD;
2080         if (termios->c_cflag & CSTOPB)
2081                 smr_val |= SCSMR_STOP;
2082 
2083         /*
2084          * earlyprintk comes here early on with port->uartclk set to zero.
2085          * the clock framework is not up and running at this point so here
2086          * we assume that 115200 is the maximum baud rate. please note that
2087          * the baud rate is not programmed during earlyprintk - it is assumed
2088          * that the previous boot loader has enabled required clocks and
2089          * setup the baud rate generator hardware for us already.
2090          */
2091         if (!port->uartclk) {
2092                 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2093                 goto done;
2094         }
2095 
2096         for (i = 0; i < SCI_NUM_CLKS; i++)
2097                 max_freq = max(max_freq, s->clk_rates[i]);
2098 
2099         baud = uart_get_baud_rate(port, termios, old, 0,
2100                                   max_freq / max(s->sampling_rate, 8U));
2101         if (!baud)
2102                 goto done;
2103 
2104         /*
2105          * There can be multiple sources for the sampling clock.  Find the one
2106          * that gives us the smallest deviation from the desired baud rate.
2107          */
2108 
2109         /* Optional Undivided External Clock */
2110         if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2111             port->type != PORT_SCIFB) {
2112                 err = sci_sck_calc(s, baud, &srr1);
2113                 if (abs(err) < abs(min_err)) {
2114                         best_clk = SCI_SCK;
2115                         scr_val = SCSCR_CKE1;
2116                         sccks = SCCKS_CKS;
2117                         min_err = err;
2118                         srr = srr1;
2119                         if (!err)
2120                                 goto done;
2121                 }
2122         }
2123 
2124         /* Optional BRG Frequency Divided External Clock */
2125         if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2126                 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2127                                    &srr1);
2128                 if (abs(err) < abs(min_err)) {
2129                         best_clk = SCI_SCIF_CLK;
2130                         scr_val = SCSCR_CKE1;
2131                         sccks = 0;
2132                         min_err = err;
2133                         dl = dl1;
2134                         srr = srr1;
2135                         if (!err)
2136                                 goto done;
2137                 }
2138         }
2139 
2140         /* Optional BRG Frequency Divided Internal Clock */
2141         if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2142                 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2143                                    &srr1);
2144                 if (abs(err) < abs(min_err)) {
2145                         best_clk = SCI_BRG_INT;
2146                         scr_val = SCSCR_CKE1;
2147                         sccks = SCCKS_XIN;
2148                         min_err = err;
2149                         dl = dl1;
2150                         srr = srr1;
2151                         if (!min_err)
2152                                 goto done;
2153                 }
2154         }
2155 
2156         /* Divided Functional Clock using standard Bit Rate Register */
2157         err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2158         if (abs(err) < abs(min_err)) {
2159                 best_clk = SCI_FCK;
2160                 scr_val = 0;
2161                 min_err = err;
2162                 brr = brr1;
2163                 srr = srr1;
2164                 cks = cks1;
2165         }
2166 
2167 done:
2168         if (best_clk >= 0)
2169                 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2170                         s->clks[best_clk], baud, min_err);
2171 
2172         sci_port_enable(s);
2173 
2174         /*
2175          * Program the optional External Baud Rate Generator (BRG) first.
2176          * It controls the mux to select (H)SCK or frequency divided clock.
2177          */
2178         if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2179                 serial_port_out(port, SCDL, dl);
2180                 serial_port_out(port, SCCKS, sccks);
2181         }
2182 
2183         sci_reset(port);
2184 
2185         uart_update_timeout(port, termios->c_cflag, baud);
2186 
2187         if (best_clk >= 0) {
2188                 smr_val |= cks;
2189                 dev_dbg(port->dev,
2190                          "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2191                          scr_val, smr_val, brr, sccks, dl, srr);
2192                 serial_port_out(port, SCSCR, scr_val);
2193                 serial_port_out(port, SCSMR, smr_val);
2194                 serial_port_out(port, SCBRR, brr);
2195                 if (sci_getreg(port, HSSRR)->size)
2196                         serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2197 
2198                 /* Wait one bit interval */
2199                 udelay((1000000 + (baud - 1)) / baud);
2200         } else {
2201                 /* Don't touch the bit rate configuration */
2202                 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2203                 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
2204                 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2205                 serial_port_out(port, SCSCR, scr_val);
2206                 serial_port_out(port, SCSMR, smr_val);
2207         }
2208 
2209         sci_init_pins(port, termios->c_cflag);
2210 
2211         reg = sci_getreg(port, SCFCR);
2212         if (reg->size) {
2213                 unsigned short ctrl = serial_port_in(port, SCFCR);
2214 
2215                 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
2216                         if (termios->c_cflag & CRTSCTS)
2217                                 ctrl |= SCFCR_MCE;
2218                         else
2219                                 ctrl &= ~SCFCR_MCE;
2220                 }
2221 
2222                 /*
2223                  * As we've done a sci_reset() above, ensure we don't
2224                  * interfere with the FIFOs while toggling MCE. As the
2225                  * reset values could still be set, simply mask them out.
2226                  */
2227                 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2228 
2229                 serial_port_out(port, SCFCR, ctrl);
2230         }
2231 
2232         scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
2233         dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2234         serial_port_out(port, SCSCR, scr_val);
2235 
2236 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2237         /*
2238          * Calculate delay for 2 DMA buffers (4 FIFO).
2239          * See serial_core.c::uart_update_timeout().
2240          * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2241          * function calculates 1 jiffie for the data plus 5 jiffies for the
2242          * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2243          * buffers (4 FIFO sizes), but when performing a faster transfer, the
2244          * value obtained by this formula is too small. Therefore, if the value
2245          * is smaller than 20ms, use 20ms as the timeout value for DMA.
2246          */
2247         if (s->chan_rx) {
2248                 unsigned int bits;
2249 
2250                 /* byte size and parity */
2251                 switch (termios->c_cflag & CSIZE) {
2252                 case CS5:
2253                         bits = 7;
2254                         break;
2255                 case CS6:
2256                         bits = 8;
2257                         break;
2258                 case CS7:
2259                         bits = 9;
2260                         break;
2261                 default:
2262                         bits = 10;
2263                         break;
2264                 }
2265 
2266                 if (termios->c_cflag & CSTOPB)
2267                         bits++;
2268                 if (termios->c_cflag & PARENB)
2269                         bits++;
2270                 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2271                                              (baud / 10), 10);
2272                 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2273                         s->rx_timeout * 1000 / HZ, port->timeout);
2274                 if (s->rx_timeout < msecs_to_jiffies(20))
2275                         s->rx_timeout = msecs_to_jiffies(20);
2276         }
2277 #endif
2278 
2279         if ((termios->c_cflag & CREAD) != 0)
2280                 sci_start_rx(port);
2281 
2282         sci_port_disable(s);
2283 }
2284 
2285 static void sci_pm(struct uart_port *port, unsigned int state,
2286                    unsigned int oldstate)
2287 {
2288         struct sci_port *sci_port = to_sci_port(port);
2289 
2290         switch (state) {
2291         case UART_PM_STATE_OFF:
2292                 sci_port_disable(sci_port);
2293                 break;
2294         default:
2295                 sci_port_enable(sci_port);
2296                 break;
2297         }
2298 }
2299 
2300 static const char *sci_type(struct uart_port *port)
2301 {
2302         switch (port->type) {
2303         case PORT_IRDA:
2304                 return "irda";
2305         case PORT_SCI:
2306                 return "sci";
2307         case PORT_SCIF:
2308                 return "scif";
2309         case PORT_SCIFA:
2310                 return "scifa";
2311         case PORT_SCIFB:
2312                 return "scifb";
2313         case PORT_HSCIF:
2314                 return "hscif";
2315         }
2316 
2317         return NULL;
2318 }
2319 
2320 static int sci_remap_port(struct uart_port *port)
2321 {
2322         struct sci_port *sport = to_sci_port(port);
2323 
2324         /*
2325          * Nothing to do if there's already an established membase.
2326          */
2327         if (port->membase)
2328                 return 0;
2329 
2330         if (port->flags & UPF_IOREMAP) {
2331                 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2332                 if (unlikely(!port->membase)) {
2333                         dev_err(port->dev, "can't remap port#%d\n", port->line);
2334                         return -ENXIO;
2335                 }
2336         } else {
2337                 /*
2338                  * For the simple (and majority of) cases where we don't
2339                  * need to do any remapping, just cast the cookie
2340                  * directly.
2341                  */
2342                 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2343         }
2344 
2345         return 0;
2346 }
2347 
2348 static void sci_release_port(struct uart_port *port)
2349 {
2350         struct sci_port *sport = to_sci_port(port);
2351 
2352         if (port->flags & UPF_IOREMAP) {
2353                 iounmap(port->membase);
2354                 port->membase = NULL;
2355         }
2356 
2357         release_mem_region(port->mapbase, sport->reg_size);
2358 }
2359 
2360 static int sci_request_port(struct uart_port *port)
2361 {
2362         struct resource *res;
2363         struct sci_port *sport = to_sci_port(port);
2364         int ret;
2365 
2366         res = request_mem_region(port->mapbase, sport->reg_size,
2367                                  dev_name(port->dev));
2368         if (unlikely(res == NULL)) {
2369                 dev_err(port->dev, "request_mem_region failed.");
2370                 return -EBUSY;
2371         }
2372 
2373         ret = sci_remap_port(port);
2374         if (unlikely(ret != 0)) {
2375                 release_resource(res);
2376                 return ret;
2377         }
2378 
2379         return 0;
2380 }
2381 
2382 static void sci_config_port(struct uart_port *port, int flags)
2383 {
2384         if (flags & UART_CONFIG_TYPE) {
2385                 struct sci_port *sport = to_sci_port(port);
2386 
2387                 port->type = sport->cfg->type;
2388                 sci_request_port(port);
2389         }
2390 }
2391 
2392 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2393 {
2394         if (ser->baud_base < 2400)
2395                 /* No paper tape reader for Mitch.. */
2396                 return -EINVAL;
2397 
2398         return 0;
2399 }
2400 
2401 static struct uart_ops sci_uart_ops = {
2402         .tx_empty       = sci_tx_empty,
2403         .set_mctrl      = sci_set_mctrl,
2404         .get_mctrl      = sci_get_mctrl,
2405         .start_tx       = sci_start_tx,
2406         .stop_tx        = sci_stop_tx,
2407         .stop_rx        = sci_stop_rx,
2408         .break_ctl      = sci_break_ctl,
2409         .startup        = sci_startup,
2410         .shutdown       = sci_shutdown,
2411         .set_termios    = sci_set_termios,
2412         .pm             = sci_pm,
2413         .type           = sci_type,
2414         .release_port   = sci_release_port,
2415         .request_port   = sci_request_port,
2416         .config_port    = sci_config_port,
2417         .verify_port    = sci_verify_port,
2418 #ifdef CONFIG_CONSOLE_POLL
2419         .poll_get_char  = sci_poll_get_char,
2420         .poll_put_char  = sci_poll_put_char,
2421 #endif
2422 };
2423 
2424 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2425 {
2426         const char *clk_names[] = {
2427                 [SCI_FCK] = "fck",
2428                 [SCI_SCK] = "sck",
2429                 [SCI_BRG_INT] = "brg_int",
2430                 [SCI_SCIF_CLK] = "scif_clk",
2431         };
2432         struct clk *clk;
2433         unsigned int i;
2434 
2435         if (sci_port->cfg->type == PORT_HSCIF)
2436                 clk_names[SCI_SCK] = "hsck";
2437 
2438         for (i = 0; i < SCI_NUM_CLKS; i++) {
2439                 clk = devm_clk_get(dev, clk_names[i]);
2440                 if (PTR_ERR(clk) == -EPROBE_DEFER)
2441                         return -EPROBE_DEFER;
2442 
2443                 if (IS_ERR(clk) && i == SCI_FCK) {
2444                         /*
2445                          * "fck" used to be called "sci_ick", and we need to
2446                          * maintain DT backward compatibility.
2447                          */
2448                         clk = devm_clk_get(dev, "sci_ick");
2449                         if (PTR_ERR(clk) == -EPROBE_DEFER)
2450                                 return -EPROBE_DEFER;
2451 
2452                         if (!IS_ERR(clk))
2453                                 goto found;
2454 
2455                         /*
2456                          * Not all SH platforms declare a clock lookup entry
2457                          * for SCI devices, in which case we need to get the
2458                          * global "peripheral_clk" clock.
2459                          */
2460                         clk = devm_clk_get(dev, "peripheral_clk");
2461                         if (!IS_ERR(clk))
2462                                 goto found;
2463 
2464                         dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2465                                 PTR_ERR(clk));
2466                         return PTR_ERR(clk);
2467                 }
2468 
2469 found:
2470                 if (IS_ERR(clk))
2471                         dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2472                                 PTR_ERR(clk));
2473                 else
2474                         dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2475                                 clk, clk);
2476                 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2477         }
2478         return 0;
2479 }
2480 
2481 static int sci_init_single(struct platform_device *dev,
2482                            struct sci_port *sci_port, unsigned int index,
2483                            struct plat_sci_port *p, bool early)
2484 {
2485         struct uart_port *port = &sci_port->port;
2486         const struct resource *res;
2487         unsigned int i;
2488         int ret;
2489 
2490         sci_port->cfg   = p;
2491 
2492         port->ops       = &sci_uart_ops;
2493         port->iotype    = UPIO_MEM;
2494         port->line      = index;
2495 
2496         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2497         if (res == NULL)
2498                 return -ENOMEM;
2499 
2500         port->mapbase = res->start;
2501         sci_port->reg_size = resource_size(res);
2502 
2503         for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2504                 sci_port->irqs[i] = platform_get_irq(dev, i);
2505 
2506         /* The SCI generates several interrupts. They can be muxed together or
2507          * connected to different interrupt lines. In the muxed case only one
2508          * interrupt resource is specified. In the non-muxed case three or four
2509          * interrupt resources are specified, as the BRI interrupt is optional.
2510          */
2511         if (sci_port->irqs[0] < 0)
2512                 return -ENXIO;
2513 
2514         if (sci_port->irqs[1] < 0) {
2515                 sci_port->irqs[1] = sci_port->irqs[0];
2516                 sci_port->irqs[2] = sci_port->irqs[0];
2517                 sci_port->irqs[3] = sci_port->irqs[0];
2518         }
2519 
2520         if (p->regtype == SCIx_PROBE_REGTYPE) {
2521                 ret = sci_probe_regmap(p);
2522                 if (unlikely(ret))
2523                         return ret;
2524         }
2525 
2526         switch (p->type) {
2527         case PORT_SCIFB:
2528                 port->fifosize = 256;
2529                 sci_port->overrun_reg = SCxSR;
2530                 sci_port->overrun_mask = SCIFA_ORER;
2531                 sci_port->sampling_rate = 16;
2532                 break;
2533         case PORT_HSCIF:
2534                 port->fifosize = 128;
2535                 sci_port->overrun_reg = SCLSR;
2536                 sci_port->overrun_mask = SCLSR_ORER;
2537                 sci_port->sampling_rate = 0;
2538                 break;
2539         case PORT_SCIFA:
2540                 port->fifosize = 64;
2541                 sci_port->overrun_reg = SCxSR;
2542                 sci_port->overrun_mask = SCIFA_ORER;
2543                 sci_port->sampling_rate = 16;
2544                 break;
2545         case PORT_SCIF:
2546                 port->fifosize = 16;
2547                 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2548                         sci_port->overrun_reg = SCxSR;
2549                         sci_port->overrun_mask = SCIFA_ORER;
2550                         sci_port->sampling_rate = 16;
2551                 } else {
2552                         sci_port->overrun_reg = SCLSR;
2553                         sci_port->overrun_mask = SCLSR_ORER;
2554                         sci_port->sampling_rate = 32;
2555                 }
2556                 break;
2557         default:
2558                 port->fifosize = 1;
2559                 sci_port->overrun_reg = SCxSR;
2560                 sci_port->overrun_mask = SCI_ORER;
2561                 sci_port->sampling_rate = 32;
2562                 break;
2563         }
2564 
2565         /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2566          * match the SoC datasheet, this should be investigated. Let platform
2567          * data override the sampling rate for now.
2568          */
2569         if (p->sampling_rate)
2570                 sci_port->sampling_rate = p->sampling_rate;
2571 
2572         if (!early) {
2573                 ret = sci_init_clocks(sci_port, &dev->dev);
2574                 if (ret < 0)
2575                         return ret;
2576 
2577                 port->dev = &dev->dev;
2578 
2579                 pm_runtime_enable(&dev->dev);
2580         }
2581 
2582         sci_port->break_timer.data = (unsigned long)sci_port;
2583         sci_port->break_timer.function = sci_break_timer;
2584         init_timer(&sci_port->break_timer);
2585 
2586         /*
2587          * Establish some sensible defaults for the error detection.
2588          */
2589         if (p->type == PORT_SCI) {
2590                 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2591                 sci_port->error_clear = SCI_ERROR_CLEAR;
2592         } else {
2593                 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2594                 sci_port->error_clear = SCIF_ERROR_CLEAR;
2595         }
2596 
2597         /*
2598          * Make the error mask inclusive of overrun detection, if
2599          * supported.
2600          */
2601         if (sci_port->overrun_reg == SCxSR) {
2602                 sci_port->error_mask |= sci_port->overrun_mask;
2603                 sci_port->error_clear &= ~sci_port->overrun_mask;
2604         }
2605 
2606         port->type              = p->type;
2607         port->flags             = UPF_FIXED_PORT | p->flags;
2608         port->regshift          = p->regshift;
2609 
2610         /*
2611          * The UART port needs an IRQ value, so we peg this to the RX IRQ
2612          * for the multi-IRQ ports, which is where we are primarily
2613          * concerned with the shutdown path synchronization.
2614          *
2615          * For the muxed case there's nothing more to do.
2616          */
2617         port->irq               = sci_port->irqs[SCIx_RXI_IRQ];
2618         port->irqflags          = 0;
2619 
2620         port->serial_in         = sci_serial_in;
2621         port->serial_out        = sci_serial_out;
2622 
2623         if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2624                 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2625                         p->dma_slave_tx, p->dma_slave_rx);
2626 
2627         return 0;
2628 }
2629 
2630 static void sci_cleanup_single(struct sci_port *port)
2631 {
2632         pm_runtime_disable(port->port.dev);
2633 }
2634 
2635 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2636 static void serial_console_putchar(struct uart_port *port, int ch)
2637 {
2638         sci_poll_put_char(port, ch);
2639 }
2640 
2641 /*
2642  *      Print a string to the serial port trying not to disturb
2643  *      any possible real use of the port...
2644  */
2645 static void serial_console_write(struct console *co, const char *s,
2646                                  unsigned count)
2647 {
2648         struct sci_port *sci_port = &sci_ports[co->index];
2649         struct uart_port *port = &sci_port->port;
2650         unsigned short bits, ctrl, ctrl_temp;
2651         unsigned long flags;
2652         int locked = 1;
2653 
2654         local_irq_save(flags);
2655         if (port->sysrq)
2656                 locked = 0;
2657         else if (oops_in_progress)
2658                 locked = spin_trylock(&port->lock);
2659         else
2660                 spin_lock(&port->lock);
2661 
2662         /* first save SCSCR then disable interrupts, keep clock source */
2663         ctrl = serial_port_in(port, SCSCR);
2664         ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2665                     (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2666         serial_port_out(port, SCSCR, ctrl_temp);
2667 
2668         uart_console_write(port, s, count, serial_console_putchar);
2669 
2670         /* wait until fifo is empty and last bit has been transmitted */
2671         bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2672         while ((serial_port_in(port, SCxSR) & bits) != bits)
2673                 cpu_relax();
2674 
2675         /* restore the SCSCR */
2676         serial_port_out(port, SCSCR, ctrl);
2677 
2678         if (locked)
2679                 spin_unlock(&port->lock);
2680         local_irq_restore(flags);
2681 }
2682 
2683 static int serial_console_setup(struct console *co, char *options)
2684 {
2685         struct sci_port *sci_port;
2686         struct uart_port *port;
2687         int baud = 115200;
2688         int bits = 8;
2689         int parity = 'n';
2690         int flow = 'n';
2691         int ret;
2692 
2693         /*
2694          * Refuse to handle any bogus ports.
2695          */
2696         if (co->index < 0 || co->index >= SCI_NPORTS)
2697                 return -ENODEV;
2698 
2699         sci_port = &sci_ports[co->index];
2700         port = &sci_port->port;
2701 
2702         /*
2703          * Refuse to handle uninitialized ports.
2704          */
2705         if (!port->ops)
2706                 return -ENODEV;
2707 
2708         ret = sci_remap_port(port);
2709         if (unlikely(ret != 0))
2710                 return ret;
2711 
2712         if (options)
2713                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2714 
2715         return uart_set_options(port, co, baud, parity, bits, flow);
2716 }
2717 
2718 static struct console serial_console = {
2719         .name           = "ttySC",
2720         .device         = uart_console_device,
2721         .write          = serial_console_write,
2722         .setup          = serial_console_setup,
2723         .flags          = CON_PRINTBUFFER,
2724         .index          = -1,
2725         .data           = &sci_uart_driver,
2726 };
2727 
2728 static struct console early_serial_console = {
2729         .name           = "early_ttySC",
2730         .write          = serial_console_write,
2731         .flags          = CON_PRINTBUFFER,
2732         .index          = -1,
2733 };
2734 
2735 static char early_serial_buf[32];
2736 
2737 static int sci_probe_earlyprintk(struct platform_device *pdev)
2738 {
2739         struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2740 
2741         if (early_serial_console.data)
2742                 return -EEXIST;
2743 
2744         early_serial_console.index = pdev->id;
2745 
2746         sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2747 
2748         serial_console_setup(&early_serial_console, early_serial_buf);
2749 
2750         if (!strstr(early_serial_buf, "keep"))
2751                 early_serial_console.flags |= CON_BOOT;
2752 
2753         register_console(&early_serial_console);
2754         return 0;
2755 }
2756 
2757 #define SCI_CONSOLE     (&serial_console)
2758 
2759 #else
2760 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2761 {
2762         return -EINVAL;
2763 }
2764 
2765 #define SCI_CONSOLE     NULL
2766 
2767 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2768 
2769 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2770 
2771 static struct uart_driver sci_uart_driver = {
2772         .owner          = THIS_MODULE,
2773         .driver_name    = "sci",
2774         .dev_name       = "ttySC",
2775         .major          = SCI_MAJOR,
2776         .minor          = SCI_MINOR_START,
2777         .nr             = SCI_NPORTS,
2778         .cons           = SCI_CONSOLE,
2779 };
2780 
2781 static int sci_remove(struct platform_device *dev)
2782 {
2783         struct sci_port *port = platform_get_drvdata(dev);
2784 
2785         uart_remove_one_port(&sci_uart_driver, &port->port);
2786 
2787         sci_cleanup_single(port);
2788 
2789         return 0;
2790 }
2791 
2792 
2793 #define SCI_OF_DATA(type, regtype)      (void *)((type) << 16 | (regtype))
2794 #define SCI_OF_TYPE(data)               ((unsigned long)(data) >> 16)
2795 #define SCI_OF_REGTYPE(data)            ((unsigned long)(data) & 0xffff)
2796 
2797 static const struct of_device_id of_sci_match[] = {
2798         /* SoC-specific types */
2799         {
2800                 .compatible = "renesas,scif-r7s72100",
2801                 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2802         },
2803         /* Family-specific types */
2804         {
2805                 .compatible = "renesas,rcar-gen1-scif",
2806                 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2807         }, {
2808                 .compatible = "renesas,rcar-gen2-scif",
2809                 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2810         }, {
2811                 .compatible = "renesas,rcar-gen3-scif",
2812                 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2813         },
2814         /* Generic types */
2815         {
2816                 .compatible = "renesas,scif",
2817                 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
2818         }, {
2819                 .compatible = "renesas,scifa",
2820                 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
2821         }, {
2822                 .compatible = "renesas,scifb",
2823                 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
2824         }, {
2825                 .compatible = "renesas,hscif",
2826                 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
2827         }, {
2828                 .compatible = "renesas,sci",
2829                 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
2830         }, {
2831                 /* Terminator */
2832         },
2833 };
2834 MODULE_DEVICE_TABLE(of, of_sci_match);
2835 
2836 static struct plat_sci_port *
2837 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2838 {
2839         struct device_node *np = pdev->dev.of_node;
2840         const struct of_device_id *match;
2841         struct plat_sci_port *p;
2842         int id;
2843 
2844         if (!IS_ENABLED(CONFIG_OF) || !np)
2845                 return NULL;
2846 
2847         match = of_match_node(of_sci_match, np);
2848         if (!match)
2849                 return NULL;
2850 
2851         p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2852         if (!p)
2853                 return NULL;
2854 
2855         /* Get the line number from the aliases node. */
2856         id = of_alias_get_id(np, "serial");
2857         if (id < 0) {
2858                 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2859                 return NULL;
2860         }
2861 
2862         *dev_id = id;
2863 
2864         p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2865         p->type = SCI_OF_TYPE(match->data);
2866         p->regtype = SCI_OF_REGTYPE(match->data);
2867         p->scscr = SCSCR_RE | SCSCR_TE;
2868 
2869         return p;
2870 }
2871 
2872 static int sci_probe_single(struct platform_device *dev,
2873                                       unsigned int index,
2874                                       struct plat_sci_port *p,
2875                                       struct sci_port *sciport)
2876 {
2877         int ret;
2878 
2879         /* Sanity check */
2880         if (unlikely(index >= SCI_NPORTS)) {
2881                 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2882                            index+1, SCI_NPORTS);
2883                 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2884                 return -EINVAL;
2885         }
2886 
2887         ret = sci_init_single(dev, sciport, index, p, false);
2888         if (ret)
2889                 return ret;
2890 
2891         ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2892         if (ret) {
2893                 sci_cleanup_single(sciport);
2894                 return ret;
2895         }
2896 
2897         return 0;
2898 }
2899 
2900 static int sci_probe(struct platform_device *dev)
2901 {
2902         struct plat_sci_port *p;
2903         struct sci_port *sp;
2904         unsigned int dev_id;
2905         int ret;
2906 
2907         /*
2908          * If we've come here via earlyprintk initialization, head off to
2909          * the special early probe. We don't have sufficient device state
2910          * to make it beyond this yet.
2911          */
2912         if (is_early_platform_device(dev))
2913                 return sci_probe_earlyprintk(dev);
2914 
2915         if (dev->dev.of_node) {
2916                 p = sci_parse_dt(dev, &dev_id);
2917                 if (p == NULL)
2918                         return -EINVAL;
2919         } else {
2920                 p = dev->dev.platform_data;
2921                 if (p == NULL) {
2922                         dev_err(&dev->dev, "no platform data supplied\n");
2923                         return -EINVAL;
2924                 }
2925 
2926                 dev_id = dev->id;
2927         }
2928 
2929         sp = &sci_ports[dev_id];
2930         platform_set_drvdata(dev, sp);
2931 
2932         ret = sci_probe_single(dev, dev_id, p, sp);
2933         if (ret)
2934                 return ret;
2935 
2936 #ifdef CONFIG_SH_STANDARD_BIOS
2937         sh_bios_gdb_detach();
2938 #endif
2939 
2940         return 0;
2941 }
2942 
2943 static __maybe_unused int sci_suspend(struct device *dev)
2944 {
2945         struct sci_port *sport = dev_get_drvdata(dev);
2946 
2947         if (sport)
2948                 uart_suspend_port(&sci_uart_driver, &sport->port);
2949 
2950         return 0;
2951 }
2952 
2953 static __maybe_unused int sci_resume(struct device *dev)
2954 {
2955         struct sci_port *sport = dev_get_drvdata(dev);
2956 
2957         if (sport)
2958                 uart_resume_port(&sci_uart_driver, &sport->port);
2959 
2960         return 0;
2961 }
2962 
2963 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2964 
2965 static struct platform_driver sci_driver = {
2966         .probe          = sci_probe,
2967         .remove         = sci_remove,
2968         .driver         = {
2969                 .name   = "sh-sci",
2970                 .pm     = &sci_dev_pm_ops,
2971                 .of_match_table = of_match_ptr(of_sci_match),
2972         },
2973 };
2974 
2975 static int __init sci_init(void)
2976 {
2977         int ret;
2978 
2979         pr_info("%s\n", banner);
2980 
2981         ret = uart_register_driver(&sci_uart_driver);
2982         if (likely(ret == 0)) {
2983                 ret = platform_driver_register(&sci_driver);
2984                 if (unlikely(ret))
2985                         uart_unregister_driver(&sci_uart_driver);
2986         }
2987 
2988         return ret;
2989 }
2990 
2991 static void __exit sci_exit(void)
2992 {
2993         platform_driver_unregister(&sci_driver);
2994         uart_unregister_driver(&sci_uart_driver);
2995 }
2996 
2997 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2998 early_platform_init_buffer("earlyprintk", &sci_driver,
2999                            early_serial_buf, ARRAY_SIZE(early_serial_buf));
3000 #endif
3001 module_init(sci_init);
3002 module_exit(sci_exit);
3003 
3004 MODULE_LICENSE("GPL");
3005 MODULE_ALIAS("platform:sh-sci");
3006 MODULE_AUTHOR("Paul Mundt");
3007 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
3008 

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