Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/tty/serial/pch_uart.c

  1 /*
  2  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
  3  *
  4  *This program is free software; you can redistribute it and/or modify
  5  *it under the terms of the GNU General Public License as published by
  6  *the Free Software Foundation; version 2 of the License.
  7  *
  8  *This program is distributed in the hope that it will be useful,
  9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
 10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 11  *GNU General Public License for more details.
 12  *
 13  *You should have received a copy of the GNU General Public License
 14  *along with this program; if not, write to the Free Software
 15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
 16  */
 17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 18 #define SUPPORT_SYSRQ
 19 #endif
 20 #include <linux/kernel.h>
 21 #include <linux/serial_reg.h>
 22 #include <linux/slab.h>
 23 #include <linux/module.h>
 24 #include <linux/pci.h>
 25 #include <linux/console.h>
 26 #include <linux/serial_core.h>
 27 #include <linux/tty.h>
 28 #include <linux/tty_flip.h>
 29 #include <linux/interrupt.h>
 30 #include <linux/io.h>
 31 #include <linux/dmi.h>
 32 #include <linux/nmi.h>
 33 #include <linux/delay.h>
 34 
 35 #include <linux/debugfs.h>
 36 #include <linux/dmaengine.h>
 37 #include <linux/pch_dma.h>
 38 
 39 enum {
 40         PCH_UART_HANDLED_RX_INT_SHIFT,
 41         PCH_UART_HANDLED_TX_INT_SHIFT,
 42         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
 43         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
 44         PCH_UART_HANDLED_MS_INT_SHIFT,
 45         PCH_UART_HANDLED_LS_INT_SHIFT,
 46 };
 47 
 48 enum {
 49         PCH_UART_8LINE,
 50         PCH_UART_2LINE,
 51 };
 52 
 53 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
 54 
 55 /* Set the max number of UART port
 56  * Intel EG20T PCH: 4 port
 57  * LAPIS Semiconductor ML7213 IOH: 3 port
 58  * LAPIS Semiconductor ML7223 IOH: 2 port
 59 */
 60 #define PCH_UART_NR     4
 61 
 62 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
 63 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
 64 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
 65                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
 66 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
 67                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
 68 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
 69 
 70 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
 71 
 72 #define PCH_UART_RBR            0x00
 73 #define PCH_UART_THR            0x00
 74 
 75 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
 76                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
 77 #define PCH_UART_IER_ERBFI      0x00000001
 78 #define PCH_UART_IER_ETBEI      0x00000002
 79 #define PCH_UART_IER_ELSI       0x00000004
 80 #define PCH_UART_IER_EDSSI      0x00000008
 81 
 82 #define PCH_UART_IIR_IP                 0x00000001
 83 #define PCH_UART_IIR_IID                0x00000006
 84 #define PCH_UART_IIR_MSI                0x00000000
 85 #define PCH_UART_IIR_TRI                0x00000002
 86 #define PCH_UART_IIR_RRI                0x00000004
 87 #define PCH_UART_IIR_REI                0x00000006
 88 #define PCH_UART_IIR_TOI                0x00000008
 89 #define PCH_UART_IIR_FIFO256            0x00000020
 90 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
 91 #define PCH_UART_IIR_FE                 0x000000C0
 92 
 93 #define PCH_UART_FCR_FIFOE              0x00000001
 94 #define PCH_UART_FCR_RFR                0x00000002
 95 #define PCH_UART_FCR_TFR                0x00000004
 96 #define PCH_UART_FCR_DMS                0x00000008
 97 #define PCH_UART_FCR_FIFO256            0x00000020
 98 #define PCH_UART_FCR_RFTL               0x000000C0
 99 
100 #define PCH_UART_FCR_RFTL1              0x00000000
101 #define PCH_UART_FCR_RFTL64             0x00000040
102 #define PCH_UART_FCR_RFTL128            0x00000080
103 #define PCH_UART_FCR_RFTL224            0x000000C0
104 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
105 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
106 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
107 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
108 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
109 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
110 #define PCH_UART_FCR_RFTL_SHIFT         6
111 
112 #define PCH_UART_LCR_WLS        0x00000003
113 #define PCH_UART_LCR_STB        0x00000004
114 #define PCH_UART_LCR_PEN        0x00000008
115 #define PCH_UART_LCR_EPS        0x00000010
116 #define PCH_UART_LCR_SP         0x00000020
117 #define PCH_UART_LCR_SB         0x00000040
118 #define PCH_UART_LCR_DLAB       0x00000080
119 #define PCH_UART_LCR_NP         0x00000000
120 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
121 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
122 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
123 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
124                                 PCH_UART_LCR_SP)
125 
126 #define PCH_UART_LCR_5BIT       0x00000000
127 #define PCH_UART_LCR_6BIT       0x00000001
128 #define PCH_UART_LCR_7BIT       0x00000002
129 #define PCH_UART_LCR_8BIT       0x00000003
130 
131 #define PCH_UART_MCR_DTR        0x00000001
132 #define PCH_UART_MCR_RTS        0x00000002
133 #define PCH_UART_MCR_OUT        0x0000000C
134 #define PCH_UART_MCR_LOOP       0x00000010
135 #define PCH_UART_MCR_AFE        0x00000020
136 
137 #define PCH_UART_LSR_DR         0x00000001
138 #define PCH_UART_LSR_ERR        (1<<7)
139 
140 #define PCH_UART_MSR_DCTS       0x00000001
141 #define PCH_UART_MSR_DDSR       0x00000002
142 #define PCH_UART_MSR_TERI       0x00000004
143 #define PCH_UART_MSR_DDCD       0x00000008
144 #define PCH_UART_MSR_CTS        0x00000010
145 #define PCH_UART_MSR_DSR        0x00000020
146 #define PCH_UART_MSR_RI         0x00000040
147 #define PCH_UART_MSR_DCD        0x00000080
148 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
149                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
150 
151 #define PCH_UART_DLL            0x00
152 #define PCH_UART_DLM            0x01
153 
154 #define PCH_UART_BRCSR          0x0E
155 
156 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
157 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
158 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
159 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
160 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
161 
162 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
163 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
164 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
165 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
166 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
167 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
168 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
169 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
170 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
171 #define PCH_UART_HAL_STB1               0
172 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
173 
174 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
175 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
176 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
177                                         PCH_UART_HAL_CLR_RX_FIFO)
178 
179 #define PCH_UART_HAL_DMA_MODE0          0
180 #define PCH_UART_HAL_FIFO_DIS           0
181 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
182 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
183                                         PCH_UART_FCR_FIFO256)
184 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
185 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
186 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
187 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
188 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
189 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
190 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
191 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
192 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
193 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
194 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
195 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
196 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
197 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
198 
199 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
200 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
201 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
202 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
203 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
204 
205 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
206 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
207 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
208 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
209 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
210 
211 #define PCI_VENDOR_ID_ROHM              0x10DB
212 
213 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
214 
215 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
216 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
217 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
218 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
219 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
220 #define MINNOW_UARTCLK   50000000 /*  50.0000 MHz */
221 
222 struct pch_uart_buffer {
223         unsigned char *buf;
224         int size;
225 };
226 
227 struct eg20t_port {
228         struct uart_port port;
229         int port_type;
230         void __iomem *membase;
231         resource_size_t mapbase;
232         unsigned int iobase;
233         struct pci_dev *pdev;
234         int fifo_size;
235         unsigned int uartclk;
236         int start_tx;
237         int start_rx;
238         int tx_empty;
239         int trigger;
240         int trigger_level;
241         struct pch_uart_buffer rxbuf;
242         unsigned int dmsr;
243         unsigned int fcr;
244         unsigned int mcr;
245         unsigned int use_dma;
246         struct dma_async_tx_descriptor  *desc_tx;
247         struct dma_async_tx_descriptor  *desc_rx;
248         struct pch_dma_slave            param_tx;
249         struct pch_dma_slave            param_rx;
250         struct dma_chan                 *chan_tx;
251         struct dma_chan                 *chan_rx;
252         struct scatterlist              *sg_tx_p;
253         int                             nent;
254         struct scatterlist              sg_rx;
255         int                             tx_dma_use;
256         void                            *rx_buf_virt;
257         dma_addr_t                      rx_buf_dma;
258 
259         struct dentry   *debugfs;
260 #define IRQ_NAME_SIZE 17
261         char                            irq_name[IRQ_NAME_SIZE];
262 
263         /* protect the eg20t_port private structure and io access to membase */
264         spinlock_t lock;
265 };
266 
267 /**
268  * struct pch_uart_driver_data - private data structure for UART-DMA
269  * @port_type:                  The number of DMA channel
270  * @line_no:                    UART port line number (0, 1, 2...)
271  */
272 struct pch_uart_driver_data {
273         int port_type;
274         int line_no;
275 };
276 
277 enum pch_uart_num_t {
278         pch_et20t_uart0 = 0,
279         pch_et20t_uart1,
280         pch_et20t_uart2,
281         pch_et20t_uart3,
282         pch_ml7213_uart0,
283         pch_ml7213_uart1,
284         pch_ml7213_uart2,
285         pch_ml7223_uart0,
286         pch_ml7223_uart1,
287         pch_ml7831_uart0,
288         pch_ml7831_uart1,
289 };
290 
291 static struct pch_uart_driver_data drv_dat[] = {
292         [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
293         [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
294         [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
295         [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
296         [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
297         [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
298         [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
299         [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
300         [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
301         [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
302         [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
303 };
304 
305 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
306 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
307 #endif
308 static unsigned int default_baud = 9600;
309 static unsigned int user_uartclk = 0;
310 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
311 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
312 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
313 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
314 
315 #ifdef CONFIG_DEBUG_FS
316 
317 #define PCH_REGS_BUFSIZE        1024
318 
319 
320 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
321                                 size_t count, loff_t *ppos)
322 {
323         struct eg20t_port *priv = file->private_data;
324         char *buf;
325         u32 len = 0;
326         ssize_t ret;
327         unsigned char lcr;
328 
329         buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
330         if (!buf)
331                 return 0;
332 
333         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
334                         "PCH EG20T port[%d] regs:\n", priv->port.line);
335 
336         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
337                         "=================================\n");
338         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
339                         "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
340         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
341                         "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
342         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
343                         "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
344         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
345                         "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
346         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
347                         "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
348         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
349                         "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
350         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
351                         "BRCSR: \t0x%02x\n",
352                         ioread8(priv->membase + PCH_UART_BRCSR));
353 
354         lcr = ioread8(priv->membase + UART_LCR);
355         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
356         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
357                         "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
358         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
359                         "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
360         iowrite8(lcr, priv->membase + UART_LCR);
361 
362         if (len > PCH_REGS_BUFSIZE)
363                 len = PCH_REGS_BUFSIZE;
364 
365         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
366         kfree(buf);
367         return ret;
368 }
369 
370 static const struct file_operations port_regs_ops = {
371         .owner          = THIS_MODULE,
372         .open           = simple_open,
373         .read           = port_show_regs,
374         .llseek         = default_llseek,
375 };
376 #endif  /* CONFIG_DEBUG_FS */
377 
378 static struct dmi_system_id pch_uart_dmi_table[] = {
379         {
380                 .ident = "CM-iTC",
381                 {
382                         DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
383                 },
384                 (void *)CMITC_UARTCLK,
385         },
386         {
387                 .ident = "FRI2",
388                 {
389                         DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
390                 },
391                 (void *)FRI2_64_UARTCLK,
392         },
393         {
394                 .ident = "Fish River Island II",
395                 {
396                         DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
397                 },
398                 (void *)FRI2_48_UARTCLK,
399         },
400         {
401                 .ident = "COMe-mTT",
402                 {
403                         DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
404                 },
405                 (void *)NTC1_UARTCLK,
406         },
407         {
408                 .ident = "nanoETXexpress-TT",
409                 {
410                         DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
411                 },
412                 (void *)NTC1_UARTCLK,
413         },
414         {
415                 .ident = "MinnowBoard",
416                 {
417                         DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
418                 },
419                 (void *)MINNOW_UARTCLK,
420         },
421 };
422 
423 /* Return UART clock, checking for board specific clocks. */
424 static unsigned int pch_uart_get_uartclk(void)
425 {
426         const struct dmi_system_id *d;
427 
428         if (user_uartclk)
429                 return user_uartclk;
430 
431         d = dmi_first_match(pch_uart_dmi_table);
432         if (d)
433                 return (unsigned long)d->driver_data;
434 
435         return DEFAULT_UARTCLK;
436 }
437 
438 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
439                                           unsigned int flag)
440 {
441         u8 ier = ioread8(priv->membase + UART_IER);
442         ier |= flag & PCH_UART_IER_MASK;
443         iowrite8(ier, priv->membase + UART_IER);
444 }
445 
446 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
447                                            unsigned int flag)
448 {
449         u8 ier = ioread8(priv->membase + UART_IER);
450         ier &= ~(flag & PCH_UART_IER_MASK);
451         iowrite8(ier, priv->membase + UART_IER);
452 }
453 
454 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
455                                  unsigned int parity, unsigned int bits,
456                                  unsigned int stb)
457 {
458         unsigned int dll, dlm, lcr;
459         int div;
460 
461         div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
462         if (div < 0 || USHRT_MAX <= div) {
463                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
464                 return -EINVAL;
465         }
466 
467         dll = (unsigned int)div & 0x00FFU;
468         dlm = ((unsigned int)div >> 8) & 0x00FFU;
469 
470         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
471                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
472                 return -EINVAL;
473         }
474 
475         if (bits & ~PCH_UART_LCR_WLS) {
476                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
477                 return -EINVAL;
478         }
479 
480         if (stb & ~PCH_UART_LCR_STB) {
481                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
482                 return -EINVAL;
483         }
484 
485         lcr = parity;
486         lcr |= bits;
487         lcr |= stb;
488 
489         dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
490                  __func__, baud, div, lcr, jiffies);
491         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
492         iowrite8(dll, priv->membase + PCH_UART_DLL);
493         iowrite8(dlm, priv->membase + PCH_UART_DLM);
494         iowrite8(lcr, priv->membase + UART_LCR);
495 
496         return 0;
497 }
498 
499 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
500                                     unsigned int flag)
501 {
502         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
503                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
504                         __func__, flag);
505                 return -EINVAL;
506         }
507 
508         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
509         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
510                  priv->membase + UART_FCR);
511         iowrite8(priv->fcr, priv->membase + UART_FCR);
512 
513         return 0;
514 }
515 
516 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
517                                  unsigned int dmamode,
518                                  unsigned int fifo_size, unsigned int trigger)
519 {
520         u8 fcr;
521 
522         if (dmamode & ~PCH_UART_FCR_DMS) {
523                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
524                         __func__, dmamode);
525                 return -EINVAL;
526         }
527 
528         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
529                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
530                         __func__, fifo_size);
531                 return -EINVAL;
532         }
533 
534         if (trigger & ~PCH_UART_FCR_RFTL) {
535                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
536                         __func__, trigger);
537                 return -EINVAL;
538         }
539 
540         switch (priv->fifo_size) {
541         case 256:
542                 priv->trigger_level =
543                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
544                 break;
545         case 64:
546                 priv->trigger_level =
547                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
548                 break;
549         case 16:
550                 priv->trigger_level =
551                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
552                 break;
553         default:
554                 priv->trigger_level =
555                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
556                 break;
557         }
558         fcr =
559             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
560         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
561         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
562                  priv->membase + UART_FCR);
563         iowrite8(fcr, priv->membase + UART_FCR);
564         priv->fcr = fcr;
565 
566         return 0;
567 }
568 
569 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
570 {
571         unsigned int msr = ioread8(priv->membase + UART_MSR);
572         priv->dmsr = msr & PCH_UART_MSR_DELTA;
573         return (u8)msr;
574 }
575 
576 static void pch_uart_hal_write(struct eg20t_port *priv,
577                               const unsigned char *buf, int tx_size)
578 {
579         int i;
580         unsigned int thr;
581 
582         for (i = 0; i < tx_size;) {
583                 thr = buf[i++];
584                 iowrite8(thr, priv->membase + PCH_UART_THR);
585         }
586 }
587 
588 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
589                              int rx_size)
590 {
591         int i;
592         u8 rbr, lsr;
593         struct uart_port *port = &priv->port;
594 
595         lsr = ioread8(priv->membase + UART_LSR);
596         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
597              i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
598              lsr = ioread8(priv->membase + UART_LSR)) {
599                 rbr = ioread8(priv->membase + PCH_UART_RBR);
600 
601                 if (lsr & UART_LSR_BI) {
602                         port->icount.brk++;
603                         if (uart_handle_break(port))
604                                 continue;
605                 }
606 #ifdef SUPPORT_SYSRQ
607                 if (port->sysrq) {
608                         if (uart_handle_sysrq_char(port, rbr))
609                                 continue;
610                 }
611 #endif
612 
613                 buf[i++] = rbr;
614         }
615         return i;
616 }
617 
618 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
619 {
620         return ioread8(priv->membase + UART_IIR) &\
621                       (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
622 }
623 
624 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
625 {
626         return ioread8(priv->membase + UART_LSR);
627 }
628 
629 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
630 {
631         unsigned int lcr;
632 
633         lcr = ioread8(priv->membase + UART_LCR);
634         if (on)
635                 lcr |= PCH_UART_LCR_SB;
636         else
637                 lcr &= ~PCH_UART_LCR_SB;
638 
639         iowrite8(lcr, priv->membase + UART_LCR);
640 }
641 
642 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
643                    int size)
644 {
645         struct uart_port *port = &priv->port;
646         struct tty_port *tport = &port->state->port;
647 
648         tty_insert_flip_string(tport, buf, size);
649         tty_flip_buffer_push(tport);
650 
651         return 0;
652 }
653 
654 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
655 {
656         int ret = 0;
657         struct uart_port *port = &priv->port;
658 
659         if (port->x_char) {
660                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
661                         __func__, port->x_char, jiffies);
662                 buf[0] = port->x_char;
663                 port->x_char = 0;
664                 ret = 1;
665         }
666 
667         return ret;
668 }
669 
670 static int dma_push_rx(struct eg20t_port *priv, int size)
671 {
672         int room;
673         struct uart_port *port = &priv->port;
674         struct tty_port *tport = &port->state->port;
675 
676         room = tty_buffer_request_room(tport, size);
677 
678         if (room < size)
679                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
680                          size - room);
681         if (!room)
682                 return 0;
683 
684         tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
685 
686         port->icount.rx += room;
687 
688         return room;
689 }
690 
691 static void pch_free_dma(struct uart_port *port)
692 {
693         struct eg20t_port *priv;
694         priv = container_of(port, struct eg20t_port, port);
695 
696         if (priv->chan_tx) {
697                 dma_release_channel(priv->chan_tx);
698                 priv->chan_tx = NULL;
699         }
700         if (priv->chan_rx) {
701                 dma_release_channel(priv->chan_rx);
702                 priv->chan_rx = NULL;
703         }
704 
705         if (priv->rx_buf_dma) {
706                 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
707                                   priv->rx_buf_dma);
708                 priv->rx_buf_virt = NULL;
709                 priv->rx_buf_dma = 0;
710         }
711 
712         return;
713 }
714 
715 static bool filter(struct dma_chan *chan, void *slave)
716 {
717         struct pch_dma_slave *param = slave;
718 
719         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
720                                                   chan->device->dev)) {
721                 chan->private = param;
722                 return true;
723         } else {
724                 return false;
725         }
726 }
727 
728 static void pch_request_dma(struct uart_port *port)
729 {
730         dma_cap_mask_t mask;
731         struct dma_chan *chan;
732         struct pci_dev *dma_dev;
733         struct pch_dma_slave *param;
734         struct eg20t_port *priv =
735                                 container_of(port, struct eg20t_port, port);
736         dma_cap_zero(mask);
737         dma_cap_set(DMA_SLAVE, mask);
738 
739         /* Get DMA's dev information */
740         dma_dev = pci_get_slot(priv->pdev->bus,
741                         PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
742 
743         /* Set Tx DMA */
744         param = &priv->param_tx;
745         param->dma_dev = &dma_dev->dev;
746         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
747 
748         param->tx_reg = port->mapbase + UART_TX;
749         chan = dma_request_channel(mask, filter, param);
750         if (!chan) {
751                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
752                         __func__);
753                 return;
754         }
755         priv->chan_tx = chan;
756 
757         /* Set Rx DMA */
758         param = &priv->param_rx;
759         param->dma_dev = &dma_dev->dev;
760         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
761 
762         param->rx_reg = port->mapbase + UART_RX;
763         chan = dma_request_channel(mask, filter, param);
764         if (!chan) {
765                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
766                         __func__);
767                 dma_release_channel(priv->chan_tx);
768                 priv->chan_tx = NULL;
769                 return;
770         }
771 
772         /* Get Consistent memory for DMA */
773         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
774                                     &priv->rx_buf_dma, GFP_KERNEL);
775         priv->chan_rx = chan;
776 }
777 
778 static void pch_dma_rx_complete(void *arg)
779 {
780         struct eg20t_port *priv = arg;
781         struct uart_port *port = &priv->port;
782         int count;
783 
784         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
785         count = dma_push_rx(priv, priv->trigger_level);
786         if (count)
787                 tty_flip_buffer_push(&port->state->port);
788         async_tx_ack(priv->desc_rx);
789         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
790                                             PCH_UART_HAL_RX_ERR_INT);
791 }
792 
793 static void pch_dma_tx_complete(void *arg)
794 {
795         struct eg20t_port *priv = arg;
796         struct uart_port *port = &priv->port;
797         struct circ_buf *xmit = &port->state->xmit;
798         struct scatterlist *sg = priv->sg_tx_p;
799         int i;
800 
801         for (i = 0; i < priv->nent; i++, sg++) {
802                 xmit->tail += sg_dma_len(sg);
803                 port->icount.tx += sg_dma_len(sg);
804         }
805         xmit->tail &= UART_XMIT_SIZE - 1;
806         async_tx_ack(priv->desc_tx);
807         dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
808         priv->tx_dma_use = 0;
809         priv->nent = 0;
810         kfree(priv->sg_tx_p);
811         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
812 }
813 
814 static int pop_tx(struct eg20t_port *priv, int size)
815 {
816         int count = 0;
817         struct uart_port *port = &priv->port;
818         struct circ_buf *xmit = &port->state->xmit;
819 
820         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
821                 goto pop_tx_end;
822 
823         do {
824                 int cnt_to_end =
825                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
826                 int sz = min(size - count, cnt_to_end);
827                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
828                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
829                 count += sz;
830         } while (!uart_circ_empty(xmit) && count < size);
831 
832 pop_tx_end:
833         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
834                  count, size - count, jiffies);
835 
836         return count;
837 }
838 
839 static int handle_rx_to(struct eg20t_port *priv)
840 {
841         struct pch_uart_buffer *buf;
842         int rx_size;
843         int ret;
844         if (!priv->start_rx) {
845                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
846                                                      PCH_UART_HAL_RX_ERR_INT);
847                 return 0;
848         }
849         buf = &priv->rxbuf;
850         do {
851                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
852                 ret = push_rx(priv, buf->buf, rx_size);
853                 if (ret)
854                         return 0;
855         } while (rx_size == buf->size);
856 
857         return PCH_UART_HANDLED_RX_INT;
858 }
859 
860 static int handle_rx(struct eg20t_port *priv)
861 {
862         return handle_rx_to(priv);
863 }
864 
865 static int dma_handle_rx(struct eg20t_port *priv)
866 {
867         struct uart_port *port = &priv->port;
868         struct dma_async_tx_descriptor *desc;
869         struct scatterlist *sg;
870 
871         priv = container_of(port, struct eg20t_port, port);
872         sg = &priv->sg_rx;
873 
874         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
875 
876         sg_dma_len(sg) = priv->trigger_level;
877 
878         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
879                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
880                      ~PAGE_MASK);
881 
882         sg_dma_address(sg) = priv->rx_buf_dma;
883 
884         desc = dmaengine_prep_slave_sg(priv->chan_rx,
885                         sg, 1, DMA_DEV_TO_MEM,
886                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
887 
888         if (!desc)
889                 return 0;
890 
891         priv->desc_rx = desc;
892         desc->callback = pch_dma_rx_complete;
893         desc->callback_param = priv;
894         desc->tx_submit(desc);
895         dma_async_issue_pending(priv->chan_rx);
896 
897         return PCH_UART_HANDLED_RX_INT;
898 }
899 
900 static unsigned int handle_tx(struct eg20t_port *priv)
901 {
902         struct uart_port *port = &priv->port;
903         struct circ_buf *xmit = &port->state->xmit;
904         int fifo_size;
905         int tx_size;
906         int size;
907         int tx_empty;
908 
909         if (!priv->start_tx) {
910                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
911                         __func__, jiffies);
912                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
913                 priv->tx_empty = 1;
914                 return 0;
915         }
916 
917         fifo_size = max(priv->fifo_size, 1);
918         tx_empty = 1;
919         if (pop_tx_x(priv, xmit->buf)) {
920                 pch_uart_hal_write(priv, xmit->buf, 1);
921                 port->icount.tx++;
922                 tx_empty = 0;
923                 fifo_size--;
924         }
925         size = min(xmit->head - xmit->tail, fifo_size);
926         if (size < 0)
927                 size = fifo_size;
928 
929         tx_size = pop_tx(priv, size);
930         if (tx_size > 0) {
931                 port->icount.tx += tx_size;
932                 tx_empty = 0;
933         }
934 
935         priv->tx_empty = tx_empty;
936 
937         if (tx_empty) {
938                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
939                 uart_write_wakeup(port);
940         }
941 
942         return PCH_UART_HANDLED_TX_INT;
943 }
944 
945 static unsigned int dma_handle_tx(struct eg20t_port *priv)
946 {
947         struct uart_port *port = &priv->port;
948         struct circ_buf *xmit = &port->state->xmit;
949         struct scatterlist *sg;
950         int nent;
951         int fifo_size;
952         int tx_empty;
953         struct dma_async_tx_descriptor *desc;
954         int num;
955         int i;
956         int bytes;
957         int size;
958         int rem;
959 
960         if (!priv->start_tx) {
961                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
962                         __func__, jiffies);
963                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
964                 priv->tx_empty = 1;
965                 return 0;
966         }
967 
968         if (priv->tx_dma_use) {
969                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
970                         __func__, jiffies);
971                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
972                 priv->tx_empty = 1;
973                 return 0;
974         }
975 
976         fifo_size = max(priv->fifo_size, 1);
977         tx_empty = 1;
978         if (pop_tx_x(priv, xmit->buf)) {
979                 pch_uart_hal_write(priv, xmit->buf, 1);
980                 port->icount.tx++;
981                 tx_empty = 0;
982                 fifo_size--;
983         }
984 
985         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
986                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
987                              xmit->tail, UART_XMIT_SIZE));
988         if (!bytes) {
989                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
990                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
991                 uart_write_wakeup(port);
992                 return 0;
993         }
994 
995         if (bytes > fifo_size) {
996                 num = bytes / fifo_size + 1;
997                 size = fifo_size;
998                 rem = bytes % fifo_size;
999         } else {
1000                 num = 1;
1001                 size = bytes;
1002                 rem = bytes;
1003         }
1004 
1005         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
1006                 __func__, num, size, rem);
1007 
1008         priv->tx_dma_use = 1;
1009 
1010         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1011         if (!priv->sg_tx_p) {
1012                 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
1013                 return 0;
1014         }
1015 
1016         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1017         sg = priv->sg_tx_p;
1018 
1019         for (i = 0; i < num; i++, sg++) {
1020                 if (i == (num - 1))
1021                         sg_set_page(sg, virt_to_page(xmit->buf),
1022                                     rem, fifo_size * i);
1023                 else
1024                         sg_set_page(sg, virt_to_page(xmit->buf),
1025                                     size, fifo_size * i);
1026         }
1027 
1028         sg = priv->sg_tx_p;
1029         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1030         if (!nent) {
1031                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1032                 return 0;
1033         }
1034         priv->nent = nent;
1035 
1036         for (i = 0; i < nent; i++, sg++) {
1037                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1038                               fifo_size * i;
1039                 sg_dma_address(sg) = (sg_dma_address(sg) &
1040                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
1041                 if (i == (nent - 1))
1042                         sg_dma_len(sg) = rem;
1043                 else
1044                         sg_dma_len(sg) = size;
1045         }
1046 
1047         desc = dmaengine_prep_slave_sg(priv->chan_tx,
1048                                         priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1049                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1050         if (!desc) {
1051                 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1052                         __func__);
1053                 return 0;
1054         }
1055         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1056         priv->desc_tx = desc;
1057         desc->callback = pch_dma_tx_complete;
1058         desc->callback_param = priv;
1059 
1060         desc->tx_submit(desc);
1061 
1062         dma_async_issue_pending(priv->chan_tx);
1063 
1064         return PCH_UART_HANDLED_TX_INT;
1065 }
1066 
1067 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1068 {
1069         struct uart_port *port = &priv->port;
1070         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1071         char   *error_msg[5] = {};
1072         int    i = 0;
1073 
1074         if (lsr & PCH_UART_LSR_ERR)
1075                 error_msg[i++] = "Error data in FIFO\n";
1076 
1077         if (lsr & UART_LSR_FE) {
1078                 port->icount.frame++;
1079                 error_msg[i++] = "  Framing Error\n";
1080         }
1081 
1082         if (lsr & UART_LSR_PE) {
1083                 port->icount.parity++;
1084                 error_msg[i++] = "  Parity Error\n";
1085         }
1086 
1087         if (lsr & UART_LSR_OE) {
1088                 port->icount.overrun++;
1089                 error_msg[i++] = "  Overrun Error\n";
1090         }
1091 
1092         if (tty == NULL) {
1093                 for (i = 0; error_msg[i] != NULL; i++)
1094                         dev_err(&priv->pdev->dev, error_msg[i]);
1095         } else {
1096                 tty_kref_put(tty);
1097         }
1098 }
1099 
1100 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1101 {
1102         struct eg20t_port *priv = dev_id;
1103         unsigned int handled;
1104         u8 lsr;
1105         int ret = 0;
1106         unsigned char iid;
1107         unsigned long flags;
1108         int next = 1;
1109         u8 msr;
1110 
1111         spin_lock_irqsave(&priv->lock, flags);
1112         handled = 0;
1113         while (next) {
1114                 iid = pch_uart_hal_get_iid(priv);
1115                 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1116                         break;
1117                 switch (iid) {
1118                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
1119                         lsr = pch_uart_hal_get_line_status(priv);
1120                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1121                                                 UART_LSR_PE | UART_LSR_OE)) {
1122                                 pch_uart_err_ir(priv, lsr);
1123                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
1124                         } else {
1125                                 ret = PCH_UART_HANDLED_LS_INT;
1126                         }
1127                         break;
1128                 case PCH_UART_IID_RDR:  /* Received Data Ready */
1129                         if (priv->use_dma) {
1130                                 pch_uart_hal_disable_interrupt(priv,
1131                                                 PCH_UART_HAL_RX_INT |
1132                                                 PCH_UART_HAL_RX_ERR_INT);
1133                                 ret = dma_handle_rx(priv);
1134                                 if (!ret)
1135                                         pch_uart_hal_enable_interrupt(priv,
1136                                                 PCH_UART_HAL_RX_INT |
1137                                                 PCH_UART_HAL_RX_ERR_INT);
1138                         } else {
1139                                 ret = handle_rx(priv);
1140                         }
1141                         break;
1142                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1143                                                    (FIFO Timeout) */
1144                         ret = handle_rx_to(priv);
1145                         break;
1146                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1147                                                    Empty */
1148                         if (priv->use_dma)
1149                                 ret = dma_handle_tx(priv);
1150                         else
1151                                 ret = handle_tx(priv);
1152                         break;
1153                 case PCH_UART_IID_MS:   /* Modem Status */
1154                         msr = pch_uart_hal_get_modem(priv);
1155                         next = 0; /* MS ir prioirty is the lowest. So, MS ir
1156                                      means final interrupt */
1157                         if ((msr & UART_MSR_ANY_DELTA) == 0)
1158                                 break;
1159                         ret |= PCH_UART_HANDLED_MS_INT;
1160                         break;
1161                 default:        /* Never junp to this label */
1162                         dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1163                                 iid, jiffies);
1164                         ret = -1;
1165                         next = 0;
1166                         break;
1167                 }
1168                 handled |= (unsigned int)ret;
1169         }
1170 
1171         spin_unlock_irqrestore(&priv->lock, flags);
1172         return IRQ_RETVAL(handled);
1173 }
1174 
1175 /* This function tests whether the transmitter fifo and shifter for the port
1176                                                 described by 'port' is empty. */
1177 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1178 {
1179         struct eg20t_port *priv;
1180 
1181         priv = container_of(port, struct eg20t_port, port);
1182         if (priv->tx_empty)
1183                 return TIOCSER_TEMT;
1184         else
1185                 return 0;
1186 }
1187 
1188 /* Returns the current state of modem control inputs. */
1189 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1190 {
1191         struct eg20t_port *priv;
1192         u8 modem;
1193         unsigned int ret = 0;
1194 
1195         priv = container_of(port, struct eg20t_port, port);
1196         modem = pch_uart_hal_get_modem(priv);
1197 
1198         if (modem & UART_MSR_DCD)
1199                 ret |= TIOCM_CAR;
1200 
1201         if (modem & UART_MSR_RI)
1202                 ret |= TIOCM_RNG;
1203 
1204         if (modem & UART_MSR_DSR)
1205                 ret |= TIOCM_DSR;
1206 
1207         if (modem & UART_MSR_CTS)
1208                 ret |= TIOCM_CTS;
1209 
1210         return ret;
1211 }
1212 
1213 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1214 {
1215         u32 mcr = 0;
1216         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1217 
1218         if (mctrl & TIOCM_DTR)
1219                 mcr |= UART_MCR_DTR;
1220         if (mctrl & TIOCM_RTS)
1221                 mcr |= UART_MCR_RTS;
1222         if (mctrl & TIOCM_LOOP)
1223                 mcr |= UART_MCR_LOOP;
1224 
1225         if (priv->mcr & UART_MCR_AFE)
1226                 mcr |= UART_MCR_AFE;
1227 
1228         if (mctrl)
1229                 iowrite8(mcr, priv->membase + UART_MCR);
1230 }
1231 
1232 static void pch_uart_stop_tx(struct uart_port *port)
1233 {
1234         struct eg20t_port *priv;
1235         priv = container_of(port, struct eg20t_port, port);
1236         priv->start_tx = 0;
1237         priv->tx_dma_use = 0;
1238 }
1239 
1240 static void pch_uart_start_tx(struct uart_port *port)
1241 {
1242         struct eg20t_port *priv;
1243 
1244         priv = container_of(port, struct eg20t_port, port);
1245 
1246         if (priv->use_dma) {
1247                 if (priv->tx_dma_use) {
1248                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1249                                 __func__);
1250                         return;
1251                 }
1252         }
1253 
1254         priv->start_tx = 1;
1255         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1256 }
1257 
1258 static void pch_uart_stop_rx(struct uart_port *port)
1259 {
1260         struct eg20t_port *priv;
1261         priv = container_of(port, struct eg20t_port, port);
1262         priv->start_rx = 0;
1263         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1264                                              PCH_UART_HAL_RX_ERR_INT);
1265 }
1266 
1267 /* Enable the modem status interrupts. */
1268 static void pch_uart_enable_ms(struct uart_port *port)
1269 {
1270         struct eg20t_port *priv;
1271         priv = container_of(port, struct eg20t_port, port);
1272         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1273 }
1274 
1275 /* Control the transmission of a break signal. */
1276 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1277 {
1278         struct eg20t_port *priv;
1279         unsigned long flags;
1280 
1281         priv = container_of(port, struct eg20t_port, port);
1282         spin_lock_irqsave(&priv->lock, flags);
1283         pch_uart_hal_set_break(priv, ctl);
1284         spin_unlock_irqrestore(&priv->lock, flags);
1285 }
1286 
1287 /* Grab any interrupt resources and initialise any low level driver state. */
1288 static int pch_uart_startup(struct uart_port *port)
1289 {
1290         struct eg20t_port *priv;
1291         int ret;
1292         int fifo_size;
1293         int trigger_level;
1294 
1295         priv = container_of(port, struct eg20t_port, port);
1296         priv->tx_empty = 1;
1297 
1298         if (port->uartclk)
1299                 priv->uartclk = port->uartclk;
1300         else
1301                 port->uartclk = priv->uartclk;
1302 
1303         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1304         ret = pch_uart_hal_set_line(priv, default_baud,
1305                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1306                               PCH_UART_HAL_STB1);
1307         if (ret)
1308                 return ret;
1309 
1310         switch (priv->fifo_size) {
1311         case 256:
1312                 fifo_size = PCH_UART_HAL_FIFO256;
1313                 break;
1314         case 64:
1315                 fifo_size = PCH_UART_HAL_FIFO64;
1316                 break;
1317         case 16:
1318                 fifo_size = PCH_UART_HAL_FIFO16;
1319                 break;
1320         case 1:
1321         default:
1322                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1323                 break;
1324         }
1325 
1326         switch (priv->trigger) {
1327         case PCH_UART_HAL_TRIGGER1:
1328                 trigger_level = 1;
1329                 break;
1330         case PCH_UART_HAL_TRIGGER_L:
1331                 trigger_level = priv->fifo_size / 4;
1332                 break;
1333         case PCH_UART_HAL_TRIGGER_M:
1334                 trigger_level = priv->fifo_size / 2;
1335                 break;
1336         case PCH_UART_HAL_TRIGGER_H:
1337         default:
1338                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1339                 break;
1340         }
1341 
1342         priv->trigger_level = trigger_level;
1343         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1344                                     fifo_size, priv->trigger);
1345         if (ret < 0)
1346                 return ret;
1347 
1348         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1349                         priv->irq_name, priv);
1350         if (ret < 0)
1351                 return ret;
1352 
1353         if (priv->use_dma)
1354                 pch_request_dma(port);
1355 
1356         priv->start_rx = 1;
1357         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1358                                             PCH_UART_HAL_RX_ERR_INT);
1359         uart_update_timeout(port, CS8, default_baud);
1360 
1361         return 0;
1362 }
1363 
1364 static void pch_uart_shutdown(struct uart_port *port)
1365 {
1366         struct eg20t_port *priv;
1367         int ret;
1368 
1369         priv = container_of(port, struct eg20t_port, port);
1370         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1371         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1372         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1373                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1374         if (ret)
1375                 dev_err(priv->port.dev,
1376                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1377 
1378         pch_free_dma(port);
1379 
1380         free_irq(priv->port.irq, priv);
1381 }
1382 
1383 /* Change the port parameters, including word length, parity, stop
1384  *bits.  Update read_status_mask and ignore_status_mask to indicate
1385  *the types of events we are interested in receiving.  */
1386 static void pch_uart_set_termios(struct uart_port *port,
1387                                  struct ktermios *termios, struct ktermios *old)
1388 {
1389         int rtn;
1390         unsigned int baud, parity, bits, stb;
1391         struct eg20t_port *priv;
1392         unsigned long flags;
1393 
1394         priv = container_of(port, struct eg20t_port, port);
1395         switch (termios->c_cflag & CSIZE) {
1396         case CS5:
1397                 bits = PCH_UART_HAL_5BIT;
1398                 break;
1399         case CS6:
1400                 bits = PCH_UART_HAL_6BIT;
1401                 break;
1402         case CS7:
1403                 bits = PCH_UART_HAL_7BIT;
1404                 break;
1405         default:                /* CS8 */
1406                 bits = PCH_UART_HAL_8BIT;
1407                 break;
1408         }
1409         if (termios->c_cflag & CSTOPB)
1410                 stb = PCH_UART_HAL_STB2;
1411         else
1412                 stb = PCH_UART_HAL_STB1;
1413 
1414         if (termios->c_cflag & PARENB) {
1415                 if (termios->c_cflag & PARODD)
1416                         parity = PCH_UART_HAL_PARITY_ODD;
1417                 else
1418                         parity = PCH_UART_HAL_PARITY_EVEN;
1419 
1420         } else
1421                 parity = PCH_UART_HAL_PARITY_NONE;
1422 
1423         /* Only UART0 has auto hardware flow function */
1424         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1425                 priv->mcr |= UART_MCR_AFE;
1426         else
1427                 priv->mcr &= ~UART_MCR_AFE;
1428 
1429         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1430 
1431         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1432 
1433         spin_lock_irqsave(&priv->lock, flags);
1434         spin_lock(&port->lock);
1435 
1436         uart_update_timeout(port, termios->c_cflag, baud);
1437         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1438         if (rtn)
1439                 goto out;
1440 
1441         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1442         /* Don't rewrite B0 */
1443         if (tty_termios_baud_rate(termios))
1444                 tty_termios_encode_baud_rate(termios, baud, baud);
1445 
1446 out:
1447         spin_unlock(&port->lock);
1448         spin_unlock_irqrestore(&priv->lock, flags);
1449 }
1450 
1451 static const char *pch_uart_type(struct uart_port *port)
1452 {
1453         return KBUILD_MODNAME;
1454 }
1455 
1456 static void pch_uart_release_port(struct uart_port *port)
1457 {
1458         struct eg20t_port *priv;
1459 
1460         priv = container_of(port, struct eg20t_port, port);
1461         pci_iounmap(priv->pdev, priv->membase);
1462         pci_release_regions(priv->pdev);
1463 }
1464 
1465 static int pch_uart_request_port(struct uart_port *port)
1466 {
1467         struct eg20t_port *priv;
1468         int ret;
1469         void __iomem *membase;
1470 
1471         priv = container_of(port, struct eg20t_port, port);
1472         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1473         if (ret < 0)
1474                 return -EBUSY;
1475 
1476         membase = pci_iomap(priv->pdev, 1, 0);
1477         if (!membase) {
1478                 pci_release_regions(priv->pdev);
1479                 return -EBUSY;
1480         }
1481         priv->membase = port->membase = membase;
1482 
1483         return 0;
1484 }
1485 
1486 static void pch_uart_config_port(struct uart_port *port, int type)
1487 {
1488         struct eg20t_port *priv;
1489 
1490         priv = container_of(port, struct eg20t_port, port);
1491         if (type & UART_CONFIG_TYPE) {
1492                 port->type = priv->port_type;
1493                 pch_uart_request_port(port);
1494         }
1495 }
1496 
1497 static int pch_uart_verify_port(struct uart_port *port,
1498                                 struct serial_struct *serinfo)
1499 {
1500         struct eg20t_port *priv;
1501 
1502         priv = container_of(port, struct eg20t_port, port);
1503         if (serinfo->flags & UPF_LOW_LATENCY) {
1504                 dev_info(priv->port.dev,
1505                         "PCH UART : Use PIO Mode (without DMA)\n");
1506                 priv->use_dma = 0;
1507                 serinfo->flags &= ~UPF_LOW_LATENCY;
1508         } else {
1509 #ifndef CONFIG_PCH_DMA
1510                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1511                         __func__);
1512                 return -EOPNOTSUPP;
1513 #endif
1514                 if (!priv->use_dma) {
1515                         pch_request_dma(port);
1516                         if (priv->chan_rx)
1517                                 priv->use_dma = 1;
1518                 }
1519                 dev_info(priv->port.dev, "PCH UART: %s\n",
1520                                 priv->use_dma ?
1521                                 "Use DMA Mode" : "No DMA");
1522         }
1523 
1524         return 0;
1525 }
1526 
1527 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1528 /*
1529  *      Wait for transmitter & holding register to empty
1530  */
1531 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1532 {
1533         unsigned int status, tmout = 10000;
1534 
1535         /* Wait up to 10ms for the character(s) to be sent. */
1536         for (;;) {
1537                 status = ioread8(up->membase + UART_LSR);
1538 
1539                 if ((status & bits) == bits)
1540                         break;
1541                 if (--tmout == 0)
1542                         break;
1543                 udelay(1);
1544         }
1545 
1546         /* Wait up to 1s for flow control if necessary */
1547         if (up->port.flags & UPF_CONS_FLOW) {
1548                 unsigned int tmout;
1549                 for (tmout = 1000000; tmout; tmout--) {
1550                         unsigned int msr = ioread8(up->membase + UART_MSR);
1551                         if (msr & UART_MSR_CTS)
1552                                 break;
1553                         udelay(1);
1554                         touch_nmi_watchdog();
1555                 }
1556         }
1557 }
1558 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1559 
1560 #ifdef CONFIG_CONSOLE_POLL
1561 /*
1562  * Console polling routines for communicate via uart while
1563  * in an interrupt or debug context.
1564  */
1565 static int pch_uart_get_poll_char(struct uart_port *port)
1566 {
1567         struct eg20t_port *priv =
1568                 container_of(port, struct eg20t_port, port);
1569         u8 lsr = ioread8(priv->membase + UART_LSR);
1570 
1571         if (!(lsr & UART_LSR_DR))
1572                 return NO_POLL_CHAR;
1573 
1574         return ioread8(priv->membase + PCH_UART_RBR);
1575 }
1576 
1577 
1578 static void pch_uart_put_poll_char(struct uart_port *port,
1579                          unsigned char c)
1580 {
1581         unsigned int ier;
1582         struct eg20t_port *priv =
1583                 container_of(port, struct eg20t_port, port);
1584 
1585         /*
1586          * First save the IER then disable the interrupts
1587          */
1588         ier = ioread8(priv->membase + UART_IER);
1589         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1590 
1591         wait_for_xmitr(priv, UART_LSR_THRE);
1592         /*
1593          * Send the character out.
1594          */
1595         iowrite8(c, priv->membase + PCH_UART_THR);
1596 
1597         /*
1598          * Finally, wait for transmitter to become empty
1599          * and restore the IER
1600          */
1601         wait_for_xmitr(priv, BOTH_EMPTY);
1602         iowrite8(ier, priv->membase + UART_IER);
1603 }
1604 #endif /* CONFIG_CONSOLE_POLL */
1605 
1606 static struct uart_ops pch_uart_ops = {
1607         .tx_empty = pch_uart_tx_empty,
1608         .set_mctrl = pch_uart_set_mctrl,
1609         .get_mctrl = pch_uart_get_mctrl,
1610         .stop_tx = pch_uart_stop_tx,
1611         .start_tx = pch_uart_start_tx,
1612         .stop_rx = pch_uart_stop_rx,
1613         .enable_ms = pch_uart_enable_ms,
1614         .break_ctl = pch_uart_break_ctl,
1615         .startup = pch_uart_startup,
1616         .shutdown = pch_uart_shutdown,
1617         .set_termios = pch_uart_set_termios,
1618 /*      .pm             = pch_uart_pm,          Not supported yet */
1619         .type = pch_uart_type,
1620         .release_port = pch_uart_release_port,
1621         .request_port = pch_uart_request_port,
1622         .config_port = pch_uart_config_port,
1623         .verify_port = pch_uart_verify_port,
1624 #ifdef CONFIG_CONSOLE_POLL
1625         .poll_get_char = pch_uart_get_poll_char,
1626         .poll_put_char = pch_uart_put_poll_char,
1627 #endif
1628 };
1629 
1630 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1631 
1632 static void pch_console_putchar(struct uart_port *port, int ch)
1633 {
1634         struct eg20t_port *priv =
1635                 container_of(port, struct eg20t_port, port);
1636 
1637         wait_for_xmitr(priv, UART_LSR_THRE);
1638         iowrite8(ch, priv->membase + PCH_UART_THR);
1639 }
1640 
1641 /*
1642  *      Print a string to the serial port trying not to disturb
1643  *      any possible real use of the port...
1644  *
1645  *      The console_lock must be held when we get here.
1646  */
1647 static void
1648 pch_console_write(struct console *co, const char *s, unsigned int count)
1649 {
1650         struct eg20t_port *priv;
1651         unsigned long flags;
1652         int priv_locked = 1;
1653         int port_locked = 1;
1654         u8 ier;
1655 
1656         priv = pch_uart_ports[co->index];
1657 
1658         touch_nmi_watchdog();
1659 
1660         local_irq_save(flags);
1661         if (priv->port.sysrq) {
1662                 /* call to uart_handle_sysrq_char already took the priv lock */
1663                 priv_locked = 0;
1664                 /* serial8250_handle_port() already took the port lock */
1665                 port_locked = 0;
1666         } else if (oops_in_progress) {
1667                 priv_locked = spin_trylock(&priv->lock);
1668                 port_locked = spin_trylock(&priv->port.lock);
1669         } else {
1670                 spin_lock(&priv->lock);
1671                 spin_lock(&priv->port.lock);
1672         }
1673 
1674         /*
1675          *      First save the IER then disable the interrupts
1676          */
1677         ier = ioread8(priv->membase + UART_IER);
1678 
1679         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1680 
1681         uart_console_write(&priv->port, s, count, pch_console_putchar);
1682 
1683         /*
1684          *      Finally, wait for transmitter to become empty
1685          *      and restore the IER
1686          */
1687         wait_for_xmitr(priv, BOTH_EMPTY);
1688         iowrite8(ier, priv->membase + UART_IER);
1689 
1690         if (port_locked)
1691                 spin_unlock(&priv->port.lock);
1692         if (priv_locked)
1693                 spin_unlock(&priv->lock);
1694         local_irq_restore(flags);
1695 }
1696 
1697 static int __init pch_console_setup(struct console *co, char *options)
1698 {
1699         struct uart_port *port;
1700         int baud = default_baud;
1701         int bits = 8;
1702         int parity = 'n';
1703         int flow = 'n';
1704 
1705         /*
1706          * Check whether an invalid uart number has been specified, and
1707          * if so, search for the first available port that does have
1708          * console support.
1709          */
1710         if (co->index >= PCH_UART_NR)
1711                 co->index = 0;
1712         port = &pch_uart_ports[co->index]->port;
1713 
1714         if (!port || (!port->iobase && !port->membase))
1715                 return -ENODEV;
1716 
1717         port->uartclk = pch_uart_get_uartclk();
1718 
1719         if (options)
1720                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1721 
1722         return uart_set_options(port, co, baud, parity, bits, flow);
1723 }
1724 
1725 static struct uart_driver pch_uart_driver;
1726 
1727 static struct console pch_console = {
1728         .name           = PCH_UART_DRIVER_DEVICE,
1729         .write          = pch_console_write,
1730         .device         = uart_console_device,
1731         .setup          = pch_console_setup,
1732         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
1733         .index          = -1,
1734         .data           = &pch_uart_driver,
1735 };
1736 
1737 #define PCH_CONSOLE     (&pch_console)
1738 #else
1739 #define PCH_CONSOLE     NULL
1740 #endif  /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1741 
1742 static struct uart_driver pch_uart_driver = {
1743         .owner = THIS_MODULE,
1744         .driver_name = KBUILD_MODNAME,
1745         .dev_name = PCH_UART_DRIVER_DEVICE,
1746         .major = 0,
1747         .minor = 0,
1748         .nr = PCH_UART_NR,
1749         .cons = PCH_CONSOLE,
1750 };
1751 
1752 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1753                                              const struct pci_device_id *id)
1754 {
1755         struct eg20t_port *priv;
1756         int ret;
1757         unsigned int iobase;
1758         unsigned int mapbase;
1759         unsigned char *rxbuf;
1760         int fifosize;
1761         int port_type;
1762         struct pch_uart_driver_data *board;
1763 #ifdef CONFIG_DEBUG_FS
1764         char name[32];  /* for debugfs file name */
1765 #endif
1766 
1767         board = &drv_dat[id->driver_data];
1768         port_type = board->port_type;
1769 
1770         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1771         if (priv == NULL)
1772                 goto init_port_alloc_err;
1773 
1774         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1775         if (!rxbuf)
1776                 goto init_port_free_txbuf;
1777 
1778         switch (port_type) {
1779         case PORT_UNKNOWN:
1780                 fifosize = 256; /* EG20T/ML7213: UART0 */
1781                 break;
1782         case PORT_8250:
1783                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1784                 break;
1785         default:
1786                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1787                 goto init_port_hal_free;
1788         }
1789 
1790         pci_enable_msi(pdev);
1791         pci_set_master(pdev);
1792 
1793         spin_lock_init(&priv->lock);
1794 
1795         iobase = pci_resource_start(pdev, 0);
1796         mapbase = pci_resource_start(pdev, 1);
1797         priv->mapbase = mapbase;
1798         priv->iobase = iobase;
1799         priv->pdev = pdev;
1800         priv->tx_empty = 1;
1801         priv->rxbuf.buf = rxbuf;
1802         priv->rxbuf.size = PAGE_SIZE;
1803 
1804         priv->fifo_size = fifosize;
1805         priv->uartclk = pch_uart_get_uartclk();
1806         priv->port_type = PORT_MAX_8250 + port_type + 1;
1807         priv->port.dev = &pdev->dev;
1808         priv->port.iobase = iobase;
1809         priv->port.membase = NULL;
1810         priv->port.mapbase = mapbase;
1811         priv->port.irq = pdev->irq;
1812         priv->port.iotype = UPIO_PORT;
1813         priv->port.ops = &pch_uart_ops;
1814         priv->port.flags = UPF_BOOT_AUTOCONF;
1815         priv->port.fifosize = fifosize;
1816         priv->port.line = board->line_no;
1817         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1818 
1819         snprintf(priv->irq_name, IRQ_NAME_SIZE,
1820                  KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1821                  priv->port.line);
1822 
1823         spin_lock_init(&priv->port.lock);
1824 
1825         pci_set_drvdata(pdev, priv);
1826         priv->trigger_level = 1;
1827         priv->fcr = 0;
1828 
1829 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1830         pch_uart_ports[board->line_no] = priv;
1831 #endif
1832         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1833         if (ret < 0)
1834                 goto init_port_hal_free;
1835 
1836 #ifdef CONFIG_DEBUG_FS
1837         snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1838         priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1839                                 NULL, priv, &port_regs_ops);
1840 #endif
1841 
1842         return priv;
1843 
1844 init_port_hal_free:
1845 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1846         pch_uart_ports[board->line_no] = NULL;
1847 #endif
1848         free_page((unsigned long)rxbuf);
1849 init_port_free_txbuf:
1850         kfree(priv);
1851 init_port_alloc_err:
1852 
1853         return NULL;
1854 }
1855 
1856 static void pch_uart_exit_port(struct eg20t_port *priv)
1857 {
1858 
1859 #ifdef CONFIG_DEBUG_FS
1860         if (priv->debugfs)
1861                 debugfs_remove(priv->debugfs);
1862 #endif
1863         uart_remove_one_port(&pch_uart_driver, &priv->port);
1864         free_page((unsigned long)priv->rxbuf.buf);
1865 }
1866 
1867 static void pch_uart_pci_remove(struct pci_dev *pdev)
1868 {
1869         struct eg20t_port *priv = pci_get_drvdata(pdev);
1870 
1871         pci_disable_msi(pdev);
1872 
1873 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1874         pch_uart_ports[priv->port.line] = NULL;
1875 #endif
1876         pch_uart_exit_port(priv);
1877         pci_disable_device(pdev);
1878         kfree(priv);
1879         return;
1880 }
1881 #ifdef CONFIG_PM
1882 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1883 {
1884         struct eg20t_port *priv = pci_get_drvdata(pdev);
1885 
1886         uart_suspend_port(&pch_uart_driver, &priv->port);
1887 
1888         pci_save_state(pdev);
1889         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1890         return 0;
1891 }
1892 
1893 static int pch_uart_pci_resume(struct pci_dev *pdev)
1894 {
1895         struct eg20t_port *priv = pci_get_drvdata(pdev);
1896         int ret;
1897 
1898         pci_set_power_state(pdev, PCI_D0);
1899         pci_restore_state(pdev);
1900 
1901         ret = pci_enable_device(pdev);
1902         if (ret) {
1903                 dev_err(&pdev->dev,
1904                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1905                 return ret;
1906         }
1907 
1908         uart_resume_port(&pch_uart_driver, &priv->port);
1909 
1910         return 0;
1911 }
1912 #else
1913 #define pch_uart_pci_suspend NULL
1914 #define pch_uart_pci_resume NULL
1915 #endif
1916 
1917 static const struct pci_device_id pch_uart_pci_id[] = {
1918         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1919          .driver_data = pch_et20t_uart0},
1920         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1921          .driver_data = pch_et20t_uart1},
1922         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1923          .driver_data = pch_et20t_uart2},
1924         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1925          .driver_data = pch_et20t_uart3},
1926         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1927          .driver_data = pch_ml7213_uart0},
1928         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1929          .driver_data = pch_ml7213_uart1},
1930         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1931          .driver_data = pch_ml7213_uart2},
1932         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1933          .driver_data = pch_ml7223_uart0},
1934         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1935          .driver_data = pch_ml7223_uart1},
1936         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1937          .driver_data = pch_ml7831_uart0},
1938         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1939          .driver_data = pch_ml7831_uart1},
1940         {0,},
1941 };
1942 
1943 static int pch_uart_pci_probe(struct pci_dev *pdev,
1944                                         const struct pci_device_id *id)
1945 {
1946         int ret;
1947         struct eg20t_port *priv;
1948 
1949         ret = pci_enable_device(pdev);
1950         if (ret < 0)
1951                 goto probe_error;
1952 
1953         priv = pch_uart_init_port(pdev, id);
1954         if (!priv) {
1955                 ret = -EBUSY;
1956                 goto probe_disable_device;
1957         }
1958         pci_set_drvdata(pdev, priv);
1959 
1960         return ret;
1961 
1962 probe_disable_device:
1963         pci_disable_msi(pdev);
1964         pci_disable_device(pdev);
1965 probe_error:
1966         return ret;
1967 }
1968 
1969 static struct pci_driver pch_uart_pci_driver = {
1970         .name = "pch_uart",
1971         .id_table = pch_uart_pci_id,
1972         .probe = pch_uart_pci_probe,
1973         .remove = pch_uart_pci_remove,
1974         .suspend = pch_uart_pci_suspend,
1975         .resume = pch_uart_pci_resume,
1976 };
1977 
1978 static int __init pch_uart_module_init(void)
1979 {
1980         int ret;
1981 
1982         /* register as UART driver */
1983         ret = uart_register_driver(&pch_uart_driver);
1984         if (ret < 0)
1985                 return ret;
1986 
1987         /* register as PCI driver */
1988         ret = pci_register_driver(&pch_uart_pci_driver);
1989         if (ret < 0)
1990                 uart_unregister_driver(&pch_uart_driver);
1991 
1992         return ret;
1993 }
1994 module_init(pch_uart_module_init);
1995 
1996 static void __exit pch_uart_module_exit(void)
1997 {
1998         pci_unregister_driver(&pch_uart_pci_driver);
1999         uart_unregister_driver(&pch_uart_driver);
2000 }
2001 module_exit(pch_uart_module_exit);
2002 
2003 MODULE_LICENSE("GPL v2");
2004 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
2005 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
2006 
2007 module_param(default_baud, uint, S_IRUGO);
2008 MODULE_PARM_DESC(default_baud,
2009                  "Default BAUD for initial driver state and console (default 9600)");
2010 module_param(user_uartclk, uint, S_IRUGO);
2011 MODULE_PARM_DESC(user_uartclk,
2012                  "Override UART default or board specific UART clock");
2013 

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