Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/tty/serial/pch_uart.c

  1 /*
  2  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
  3  *
  4  *This program is free software; you can redistribute it and/or modify
  5  *it under the terms of the GNU General Public License as published by
  6  *the Free Software Foundation; version 2 of the License.
  7  *
  8  *This program is distributed in the hope that it will be useful,
  9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
 10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 11  *GNU General Public License for more details.
 12  *
 13  *You should have received a copy of the GNU General Public License
 14  *along with this program; if not, write to the Free Software
 15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
 16  */
 17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 18 #define SUPPORT_SYSRQ
 19 #endif
 20 #include <linux/kernel.h>
 21 #include <linux/serial_reg.h>
 22 #include <linux/slab.h>
 23 #include <linux/module.h>
 24 #include <linux/pci.h>
 25 #include <linux/console.h>
 26 #include <linux/serial_core.h>
 27 #include <linux/tty.h>
 28 #include <linux/tty_flip.h>
 29 #include <linux/interrupt.h>
 30 #include <linux/io.h>
 31 #include <linux/dmi.h>
 32 #include <linux/nmi.h>
 33 #include <linux/delay.h>
 34 
 35 #include <linux/debugfs.h>
 36 #include <linux/dmaengine.h>
 37 #include <linux/pch_dma.h>
 38 
 39 enum {
 40         PCH_UART_HANDLED_RX_INT_SHIFT,
 41         PCH_UART_HANDLED_TX_INT_SHIFT,
 42         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
 43         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
 44         PCH_UART_HANDLED_MS_INT_SHIFT,
 45         PCH_UART_HANDLED_LS_INT_SHIFT,
 46 };
 47 
 48 enum {
 49         PCH_UART_8LINE,
 50         PCH_UART_2LINE,
 51 };
 52 
 53 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
 54 
 55 /* Set the max number of UART port
 56  * Intel EG20T PCH: 4 port
 57  * LAPIS Semiconductor ML7213 IOH: 3 port
 58  * LAPIS Semiconductor ML7223 IOH: 2 port
 59 */
 60 #define PCH_UART_NR     4
 61 
 62 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
 63 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
 64 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
 65                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
 66 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
 67                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
 68 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
 69 
 70 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
 71 
 72 #define PCH_UART_RBR            0x00
 73 #define PCH_UART_THR            0x00
 74 
 75 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
 76                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
 77 #define PCH_UART_IER_ERBFI      0x00000001
 78 #define PCH_UART_IER_ETBEI      0x00000002
 79 #define PCH_UART_IER_ELSI       0x00000004
 80 #define PCH_UART_IER_EDSSI      0x00000008
 81 
 82 #define PCH_UART_IIR_IP                 0x00000001
 83 #define PCH_UART_IIR_IID                0x00000006
 84 #define PCH_UART_IIR_MSI                0x00000000
 85 #define PCH_UART_IIR_TRI                0x00000002
 86 #define PCH_UART_IIR_RRI                0x00000004
 87 #define PCH_UART_IIR_REI                0x00000006
 88 #define PCH_UART_IIR_TOI                0x00000008
 89 #define PCH_UART_IIR_FIFO256            0x00000020
 90 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
 91 #define PCH_UART_IIR_FE                 0x000000C0
 92 
 93 #define PCH_UART_FCR_FIFOE              0x00000001
 94 #define PCH_UART_FCR_RFR                0x00000002
 95 #define PCH_UART_FCR_TFR                0x00000004
 96 #define PCH_UART_FCR_DMS                0x00000008
 97 #define PCH_UART_FCR_FIFO256            0x00000020
 98 #define PCH_UART_FCR_RFTL               0x000000C0
 99 
100 #define PCH_UART_FCR_RFTL1              0x00000000
101 #define PCH_UART_FCR_RFTL64             0x00000040
102 #define PCH_UART_FCR_RFTL128            0x00000080
103 #define PCH_UART_FCR_RFTL224            0x000000C0
104 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
105 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
106 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
107 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
108 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
109 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
110 #define PCH_UART_FCR_RFTL_SHIFT         6
111 
112 #define PCH_UART_LCR_WLS        0x00000003
113 #define PCH_UART_LCR_STB        0x00000004
114 #define PCH_UART_LCR_PEN        0x00000008
115 #define PCH_UART_LCR_EPS        0x00000010
116 #define PCH_UART_LCR_SP         0x00000020
117 #define PCH_UART_LCR_SB         0x00000040
118 #define PCH_UART_LCR_DLAB       0x00000080
119 #define PCH_UART_LCR_NP         0x00000000
120 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
121 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
122 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
123 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
124                                 PCH_UART_LCR_SP)
125 
126 #define PCH_UART_LCR_5BIT       0x00000000
127 #define PCH_UART_LCR_6BIT       0x00000001
128 #define PCH_UART_LCR_7BIT       0x00000002
129 #define PCH_UART_LCR_8BIT       0x00000003
130 
131 #define PCH_UART_MCR_DTR        0x00000001
132 #define PCH_UART_MCR_RTS        0x00000002
133 #define PCH_UART_MCR_OUT        0x0000000C
134 #define PCH_UART_MCR_LOOP       0x00000010
135 #define PCH_UART_MCR_AFE        0x00000020
136 
137 #define PCH_UART_LSR_DR         0x00000001
138 #define PCH_UART_LSR_ERR        (1<<7)
139 
140 #define PCH_UART_MSR_DCTS       0x00000001
141 #define PCH_UART_MSR_DDSR       0x00000002
142 #define PCH_UART_MSR_TERI       0x00000004
143 #define PCH_UART_MSR_DDCD       0x00000008
144 #define PCH_UART_MSR_CTS        0x00000010
145 #define PCH_UART_MSR_DSR        0x00000020
146 #define PCH_UART_MSR_RI         0x00000040
147 #define PCH_UART_MSR_DCD        0x00000080
148 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
149                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
150 
151 #define PCH_UART_DLL            0x00
152 #define PCH_UART_DLM            0x01
153 
154 #define PCH_UART_BRCSR          0x0E
155 
156 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
157 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
158 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
159 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
160 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
161 
162 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
163 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
164 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
165 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
166 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
167 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
168 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
169 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
170 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
171 #define PCH_UART_HAL_STB1               0
172 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
173 
174 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
175 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
176 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
177                                         PCH_UART_HAL_CLR_RX_FIFO)
178 
179 #define PCH_UART_HAL_DMA_MODE0          0
180 #define PCH_UART_HAL_FIFO_DIS           0
181 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
182 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
183                                         PCH_UART_FCR_FIFO256)
184 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
185 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
186 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
187 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
188 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
189 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
190 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
191 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
192 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
193 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
194 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
195 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
196 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
197 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
198 
199 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
200 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
201 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
202 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
203 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
204 
205 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
206 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
207 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
208 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
209 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
210 
211 #define PCI_VENDOR_ID_ROHM              0x10DB
212 
213 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
214 
215 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
216 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
217 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
218 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
219 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
220 #define MINNOW_UARTCLK   50000000 /*  50.0000 MHz */
221 
222 struct pch_uart_buffer {
223         unsigned char *buf;
224         int size;
225 };
226 
227 struct eg20t_port {
228         struct uart_port port;
229         int port_type;
230         void __iomem *membase;
231         resource_size_t mapbase;
232         unsigned int iobase;
233         struct pci_dev *pdev;
234         int fifo_size;
235         unsigned int uartclk;
236         int start_tx;
237         int start_rx;
238         int tx_empty;
239         int trigger;
240         int trigger_level;
241         struct pch_uart_buffer rxbuf;
242         unsigned int dmsr;
243         unsigned int fcr;
244         unsigned int mcr;
245         unsigned int use_dma;
246         struct dma_async_tx_descriptor  *desc_tx;
247         struct dma_async_tx_descriptor  *desc_rx;
248         struct pch_dma_slave            param_tx;
249         struct pch_dma_slave            param_rx;
250         struct dma_chan                 *chan_tx;
251         struct dma_chan                 *chan_rx;
252         struct scatterlist              *sg_tx_p;
253         int                             nent;
254         struct scatterlist              sg_rx;
255         int                             tx_dma_use;
256         void                            *rx_buf_virt;
257         dma_addr_t                      rx_buf_dma;
258 
259         struct dentry   *debugfs;
260 #define IRQ_NAME_SIZE 17
261         char                            irq_name[IRQ_NAME_SIZE];
262 
263         /* protect the eg20t_port private structure and io access to membase */
264         spinlock_t lock;
265 };
266 
267 /**
268  * struct pch_uart_driver_data - private data structure for UART-DMA
269  * @port_type:                  The number of DMA channel
270  * @line_no:                    UART port line number (0, 1, 2...)
271  */
272 struct pch_uart_driver_data {
273         int port_type;
274         int line_no;
275 };
276 
277 enum pch_uart_num_t {
278         pch_et20t_uart0 = 0,
279         pch_et20t_uart1,
280         pch_et20t_uart2,
281         pch_et20t_uart3,
282         pch_ml7213_uart0,
283         pch_ml7213_uart1,
284         pch_ml7213_uart2,
285         pch_ml7223_uart0,
286         pch_ml7223_uart1,
287         pch_ml7831_uart0,
288         pch_ml7831_uart1,
289 };
290 
291 static struct pch_uart_driver_data drv_dat[] = {
292         [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
293         [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
294         [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
295         [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
296         [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
297         [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
298         [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
299         [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
300         [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
301         [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
302         [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
303 };
304 
305 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
306 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
307 #endif
308 static unsigned int default_baud = 9600;
309 static unsigned int user_uartclk = 0;
310 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
311 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
312 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
313 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
314 
315 #ifdef CONFIG_DEBUG_FS
316 
317 #define PCH_REGS_BUFSIZE        1024
318 
319 
320 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
321                                 size_t count, loff_t *ppos)
322 {
323         struct eg20t_port *priv = file->private_data;
324         char *buf;
325         u32 len = 0;
326         ssize_t ret;
327         unsigned char lcr;
328 
329         buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
330         if (!buf)
331                 return 0;
332 
333         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
334                         "PCH EG20T port[%d] regs:\n", priv->port.line);
335 
336         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
337                         "=================================\n");
338         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
339                         "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
340         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
341                         "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
342         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
343                         "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
344         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
345                         "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
346         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
347                         "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
348         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
349                         "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
350         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
351                         "BRCSR: \t0x%02x\n",
352                         ioread8(priv->membase + PCH_UART_BRCSR));
353 
354         lcr = ioread8(priv->membase + UART_LCR);
355         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
356         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
357                         "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
358         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
359                         "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
360         iowrite8(lcr, priv->membase + UART_LCR);
361 
362         if (len > PCH_REGS_BUFSIZE)
363                 len = PCH_REGS_BUFSIZE;
364 
365         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
366         kfree(buf);
367         return ret;
368 }
369 
370 static const struct file_operations port_regs_ops = {
371         .owner          = THIS_MODULE,
372         .open           = simple_open,
373         .read           = port_show_regs,
374         .llseek         = default_llseek,
375 };
376 #endif  /* CONFIG_DEBUG_FS */
377 
378 static struct dmi_system_id pch_uart_dmi_table[] = {
379         {
380                 .ident = "CM-iTC",
381                 {
382                         DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
383                 },
384                 (void *)CMITC_UARTCLK,
385         },
386         {
387                 .ident = "FRI2",
388                 {
389                         DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
390                 },
391                 (void *)FRI2_64_UARTCLK,
392         },
393         {
394                 .ident = "Fish River Island II",
395                 {
396                         DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
397                 },
398                 (void *)FRI2_48_UARTCLK,
399         },
400         {
401                 .ident = "COMe-mTT",
402                 {
403                         DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
404                 },
405                 (void *)NTC1_UARTCLK,
406         },
407         {
408                 .ident = "nanoETXexpress-TT",
409                 {
410                         DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
411                 },
412                 (void *)NTC1_UARTCLK,
413         },
414         {
415                 .ident = "MinnowBoard",
416                 {
417                         DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
418                 },
419                 (void *)MINNOW_UARTCLK,
420         },
421 };
422 
423 /* Return UART clock, checking for board specific clocks. */
424 static unsigned int pch_uart_get_uartclk(void)
425 {
426         const struct dmi_system_id *d;
427 
428         if (user_uartclk)
429                 return user_uartclk;
430 
431         d = dmi_first_match(pch_uart_dmi_table);
432         if (d)
433                 return (unsigned long)d->driver_data;
434 
435         return DEFAULT_UARTCLK;
436 }
437 
438 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
439                                           unsigned int flag)
440 {
441         u8 ier = ioread8(priv->membase + UART_IER);
442         ier |= flag & PCH_UART_IER_MASK;
443         iowrite8(ier, priv->membase + UART_IER);
444 }
445 
446 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
447                                            unsigned int flag)
448 {
449         u8 ier = ioread8(priv->membase + UART_IER);
450         ier &= ~(flag & PCH_UART_IER_MASK);
451         iowrite8(ier, priv->membase + UART_IER);
452 }
453 
454 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
455                                  unsigned int parity, unsigned int bits,
456                                  unsigned int stb)
457 {
458         unsigned int dll, dlm, lcr;
459         int div;
460 
461         div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
462         if (div < 0 || USHRT_MAX <= div) {
463                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
464                 return -EINVAL;
465         }
466 
467         dll = (unsigned int)div & 0x00FFU;
468         dlm = ((unsigned int)div >> 8) & 0x00FFU;
469 
470         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
471                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
472                 return -EINVAL;
473         }
474 
475         if (bits & ~PCH_UART_LCR_WLS) {
476                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
477                 return -EINVAL;
478         }
479 
480         if (stb & ~PCH_UART_LCR_STB) {
481                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
482                 return -EINVAL;
483         }
484 
485         lcr = parity;
486         lcr |= bits;
487         lcr |= stb;
488 
489         dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
490                  __func__, baud, div, lcr, jiffies);
491         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
492         iowrite8(dll, priv->membase + PCH_UART_DLL);
493         iowrite8(dlm, priv->membase + PCH_UART_DLM);
494         iowrite8(lcr, priv->membase + UART_LCR);
495 
496         return 0;
497 }
498 
499 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
500                                     unsigned int flag)
501 {
502         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
503                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
504                         __func__, flag);
505                 return -EINVAL;
506         }
507 
508         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
509         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
510                  priv->membase + UART_FCR);
511         iowrite8(priv->fcr, priv->membase + UART_FCR);
512 
513         return 0;
514 }
515 
516 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
517                                  unsigned int dmamode,
518                                  unsigned int fifo_size, unsigned int trigger)
519 {
520         u8 fcr;
521 
522         if (dmamode & ~PCH_UART_FCR_DMS) {
523                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
524                         __func__, dmamode);
525                 return -EINVAL;
526         }
527 
528         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
529                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
530                         __func__, fifo_size);
531                 return -EINVAL;
532         }
533 
534         if (trigger & ~PCH_UART_FCR_RFTL) {
535                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
536                         __func__, trigger);
537                 return -EINVAL;
538         }
539 
540         switch (priv->fifo_size) {
541         case 256:
542                 priv->trigger_level =
543                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
544                 break;
545         case 64:
546                 priv->trigger_level =
547                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
548                 break;
549         case 16:
550                 priv->trigger_level =
551                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
552                 break;
553         default:
554                 priv->trigger_level =
555                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
556                 break;
557         }
558         fcr =
559             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
560         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
561         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
562                  priv->membase + UART_FCR);
563         iowrite8(fcr, priv->membase + UART_FCR);
564         priv->fcr = fcr;
565 
566         return 0;
567 }
568 
569 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
570 {
571         unsigned int msr = ioread8(priv->membase + UART_MSR);
572         priv->dmsr = msr & PCH_UART_MSR_DELTA;
573         return (u8)msr;
574 }
575 
576 static void pch_uart_hal_write(struct eg20t_port *priv,
577                               const unsigned char *buf, int tx_size)
578 {
579         int i;
580         unsigned int thr;
581 
582         for (i = 0; i < tx_size;) {
583                 thr = buf[i++];
584                 iowrite8(thr, priv->membase + PCH_UART_THR);
585         }
586 }
587 
588 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
589                              int rx_size)
590 {
591         int i;
592         u8 rbr, lsr;
593         struct uart_port *port = &priv->port;
594 
595         lsr = ioread8(priv->membase + UART_LSR);
596         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
597              i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
598              lsr = ioread8(priv->membase + UART_LSR)) {
599                 rbr = ioread8(priv->membase + PCH_UART_RBR);
600 
601                 if (lsr & UART_LSR_BI) {
602                         port->icount.brk++;
603                         if (uart_handle_break(port))
604                                 continue;
605                 }
606 #ifdef SUPPORT_SYSRQ
607                 if (port->sysrq) {
608                         if (uart_handle_sysrq_char(port, rbr))
609                                 continue;
610                 }
611 #endif
612 
613                 buf[i++] = rbr;
614         }
615         return i;
616 }
617 
618 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
619 {
620         return ioread8(priv->membase + UART_IIR) &\
621                       (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
622 }
623 
624 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
625 {
626         return ioread8(priv->membase + UART_LSR);
627 }
628 
629 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
630 {
631         unsigned int lcr;
632 
633         lcr = ioread8(priv->membase + UART_LCR);
634         if (on)
635                 lcr |= PCH_UART_LCR_SB;
636         else
637                 lcr &= ~PCH_UART_LCR_SB;
638 
639         iowrite8(lcr, priv->membase + UART_LCR);
640 }
641 
642 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
643                    int size)
644 {
645         struct uart_port *port = &priv->port;
646         struct tty_port *tport = &port->state->port;
647 
648         tty_insert_flip_string(tport, buf, size);
649         tty_flip_buffer_push(tport);
650 
651         return 0;
652 }
653 
654 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
655 {
656         int ret = 0;
657         struct uart_port *port = &priv->port;
658 
659         if (port->x_char) {
660                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
661                         __func__, port->x_char, jiffies);
662                 buf[0] = port->x_char;
663                 port->x_char = 0;
664                 ret = 1;
665         }
666 
667         return ret;
668 }
669 
670 static int dma_push_rx(struct eg20t_port *priv, int size)
671 {
672         int room;
673         struct uart_port *port = &priv->port;
674         struct tty_port *tport = &port->state->port;
675 
676         room = tty_buffer_request_room(tport, size);
677 
678         if (room < size)
679                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
680                          size - room);
681         if (!room)
682                 return 0;
683 
684         tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
685 
686         port->icount.rx += room;
687 
688         return room;
689 }
690 
691 static void pch_free_dma(struct uart_port *port)
692 {
693         struct eg20t_port *priv;
694         priv = container_of(port, struct eg20t_port, port);
695 
696         if (priv->chan_tx) {
697                 dma_release_channel(priv->chan_tx);
698                 priv->chan_tx = NULL;
699         }
700         if (priv->chan_rx) {
701                 dma_release_channel(priv->chan_rx);
702                 priv->chan_rx = NULL;
703         }
704 
705         if (priv->rx_buf_dma) {
706                 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
707                                   priv->rx_buf_dma);
708                 priv->rx_buf_virt = NULL;
709                 priv->rx_buf_dma = 0;
710         }
711 
712         return;
713 }
714 
715 static bool filter(struct dma_chan *chan, void *slave)
716 {
717         struct pch_dma_slave *param = slave;
718 
719         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
720                                                   chan->device->dev)) {
721                 chan->private = param;
722                 return true;
723         } else {
724                 return false;
725         }
726 }
727 
728 static void pch_request_dma(struct uart_port *port)
729 {
730         dma_cap_mask_t mask;
731         struct dma_chan *chan;
732         struct pci_dev *dma_dev;
733         struct pch_dma_slave *param;
734         struct eg20t_port *priv =
735                                 container_of(port, struct eg20t_port, port);
736         dma_cap_zero(mask);
737         dma_cap_set(DMA_SLAVE, mask);
738 
739         dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
740                                        PCI_DEVFN(0xa, 0)); /* Get DMA's dev
741                                                                 information */
742         /* Set Tx DMA */
743         param = &priv->param_tx;
744         param->dma_dev = &dma_dev->dev;
745         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
746 
747         param->tx_reg = port->mapbase + UART_TX;
748         chan = dma_request_channel(mask, filter, param);
749         if (!chan) {
750                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
751                         __func__);
752                 return;
753         }
754         priv->chan_tx = chan;
755 
756         /* Set Rx DMA */
757         param = &priv->param_rx;
758         param->dma_dev = &dma_dev->dev;
759         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
760 
761         param->rx_reg = port->mapbase + UART_RX;
762         chan = dma_request_channel(mask, filter, param);
763         if (!chan) {
764                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
765                         __func__);
766                 dma_release_channel(priv->chan_tx);
767                 priv->chan_tx = NULL;
768                 return;
769         }
770 
771         /* Get Consistent memory for DMA */
772         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
773                                     &priv->rx_buf_dma, GFP_KERNEL);
774         priv->chan_rx = chan;
775 }
776 
777 static void pch_dma_rx_complete(void *arg)
778 {
779         struct eg20t_port *priv = arg;
780         struct uart_port *port = &priv->port;
781         int count;
782 
783         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
784         count = dma_push_rx(priv, priv->trigger_level);
785         if (count)
786                 tty_flip_buffer_push(&port->state->port);
787         async_tx_ack(priv->desc_rx);
788         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
789                                             PCH_UART_HAL_RX_ERR_INT);
790 }
791 
792 static void pch_dma_tx_complete(void *arg)
793 {
794         struct eg20t_port *priv = arg;
795         struct uart_port *port = &priv->port;
796         struct circ_buf *xmit = &port->state->xmit;
797         struct scatterlist *sg = priv->sg_tx_p;
798         int i;
799 
800         for (i = 0; i < priv->nent; i++, sg++) {
801                 xmit->tail += sg_dma_len(sg);
802                 port->icount.tx += sg_dma_len(sg);
803         }
804         xmit->tail &= UART_XMIT_SIZE - 1;
805         async_tx_ack(priv->desc_tx);
806         dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
807         priv->tx_dma_use = 0;
808         priv->nent = 0;
809         kfree(priv->sg_tx_p);
810         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
811 }
812 
813 static int pop_tx(struct eg20t_port *priv, int size)
814 {
815         int count = 0;
816         struct uart_port *port = &priv->port;
817         struct circ_buf *xmit = &port->state->xmit;
818 
819         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
820                 goto pop_tx_end;
821 
822         do {
823                 int cnt_to_end =
824                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
825                 int sz = min(size - count, cnt_to_end);
826                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
827                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
828                 count += sz;
829         } while (!uart_circ_empty(xmit) && count < size);
830 
831 pop_tx_end:
832         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
833                  count, size - count, jiffies);
834 
835         return count;
836 }
837 
838 static int handle_rx_to(struct eg20t_port *priv)
839 {
840         struct pch_uart_buffer *buf;
841         int rx_size;
842         int ret;
843         if (!priv->start_rx) {
844                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
845                                                      PCH_UART_HAL_RX_ERR_INT);
846                 return 0;
847         }
848         buf = &priv->rxbuf;
849         do {
850                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
851                 ret = push_rx(priv, buf->buf, rx_size);
852                 if (ret)
853                         return 0;
854         } while (rx_size == buf->size);
855 
856         return PCH_UART_HANDLED_RX_INT;
857 }
858 
859 static int handle_rx(struct eg20t_port *priv)
860 {
861         return handle_rx_to(priv);
862 }
863 
864 static int dma_handle_rx(struct eg20t_port *priv)
865 {
866         struct uart_port *port = &priv->port;
867         struct dma_async_tx_descriptor *desc;
868         struct scatterlist *sg;
869 
870         priv = container_of(port, struct eg20t_port, port);
871         sg = &priv->sg_rx;
872 
873         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
874 
875         sg_dma_len(sg) = priv->trigger_level;
876 
877         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
878                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
879                      ~PAGE_MASK);
880 
881         sg_dma_address(sg) = priv->rx_buf_dma;
882 
883         desc = dmaengine_prep_slave_sg(priv->chan_rx,
884                         sg, 1, DMA_DEV_TO_MEM,
885                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
886 
887         if (!desc)
888                 return 0;
889 
890         priv->desc_rx = desc;
891         desc->callback = pch_dma_rx_complete;
892         desc->callback_param = priv;
893         desc->tx_submit(desc);
894         dma_async_issue_pending(priv->chan_rx);
895 
896         return PCH_UART_HANDLED_RX_INT;
897 }
898 
899 static unsigned int handle_tx(struct eg20t_port *priv)
900 {
901         struct uart_port *port = &priv->port;
902         struct circ_buf *xmit = &port->state->xmit;
903         int fifo_size;
904         int tx_size;
905         int size;
906         int tx_empty;
907 
908         if (!priv->start_tx) {
909                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
910                         __func__, jiffies);
911                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
912                 priv->tx_empty = 1;
913                 return 0;
914         }
915 
916         fifo_size = max(priv->fifo_size, 1);
917         tx_empty = 1;
918         if (pop_tx_x(priv, xmit->buf)) {
919                 pch_uart_hal_write(priv, xmit->buf, 1);
920                 port->icount.tx++;
921                 tx_empty = 0;
922                 fifo_size--;
923         }
924         size = min(xmit->head - xmit->tail, fifo_size);
925         if (size < 0)
926                 size = fifo_size;
927 
928         tx_size = pop_tx(priv, size);
929         if (tx_size > 0) {
930                 port->icount.tx += tx_size;
931                 tx_empty = 0;
932         }
933 
934         priv->tx_empty = tx_empty;
935 
936         if (tx_empty) {
937                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
938                 uart_write_wakeup(port);
939         }
940 
941         return PCH_UART_HANDLED_TX_INT;
942 }
943 
944 static unsigned int dma_handle_tx(struct eg20t_port *priv)
945 {
946         struct uart_port *port = &priv->port;
947         struct circ_buf *xmit = &port->state->xmit;
948         struct scatterlist *sg;
949         int nent;
950         int fifo_size;
951         int tx_empty;
952         struct dma_async_tx_descriptor *desc;
953         int num;
954         int i;
955         int bytes;
956         int size;
957         int rem;
958 
959         if (!priv->start_tx) {
960                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
961                         __func__, jiffies);
962                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
963                 priv->tx_empty = 1;
964                 return 0;
965         }
966 
967         if (priv->tx_dma_use) {
968                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
969                         __func__, jiffies);
970                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
971                 priv->tx_empty = 1;
972                 return 0;
973         }
974 
975         fifo_size = max(priv->fifo_size, 1);
976         tx_empty = 1;
977         if (pop_tx_x(priv, xmit->buf)) {
978                 pch_uart_hal_write(priv, xmit->buf, 1);
979                 port->icount.tx++;
980                 tx_empty = 0;
981                 fifo_size--;
982         }
983 
984         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
985                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
986                              xmit->tail, UART_XMIT_SIZE));
987         if (!bytes) {
988                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
989                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
990                 uart_write_wakeup(port);
991                 return 0;
992         }
993 
994         if (bytes > fifo_size) {
995                 num = bytes / fifo_size + 1;
996                 size = fifo_size;
997                 rem = bytes % fifo_size;
998         } else {
999                 num = 1;
1000                 size = bytes;
1001                 rem = bytes;
1002         }
1003 
1004         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
1005                 __func__, num, size, rem);
1006 
1007         priv->tx_dma_use = 1;
1008 
1009         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1010         if (!priv->sg_tx_p) {
1011                 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
1012                 return 0;
1013         }
1014 
1015         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1016         sg = priv->sg_tx_p;
1017 
1018         for (i = 0; i < num; i++, sg++) {
1019                 if (i == (num - 1))
1020                         sg_set_page(sg, virt_to_page(xmit->buf),
1021                                     rem, fifo_size * i);
1022                 else
1023                         sg_set_page(sg, virt_to_page(xmit->buf),
1024                                     size, fifo_size * i);
1025         }
1026 
1027         sg = priv->sg_tx_p;
1028         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1029         if (!nent) {
1030                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1031                 return 0;
1032         }
1033         priv->nent = nent;
1034 
1035         for (i = 0; i < nent; i++, sg++) {
1036                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1037                               fifo_size * i;
1038                 sg_dma_address(sg) = (sg_dma_address(sg) &
1039                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
1040                 if (i == (nent - 1))
1041                         sg_dma_len(sg) = rem;
1042                 else
1043                         sg_dma_len(sg) = size;
1044         }
1045 
1046         desc = dmaengine_prep_slave_sg(priv->chan_tx,
1047                                         priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1048                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1049         if (!desc) {
1050                 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
1051                         __func__);
1052                 return 0;
1053         }
1054         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1055         priv->desc_tx = desc;
1056         desc->callback = pch_dma_tx_complete;
1057         desc->callback_param = priv;
1058 
1059         desc->tx_submit(desc);
1060 
1061         dma_async_issue_pending(priv->chan_tx);
1062 
1063         return PCH_UART_HANDLED_TX_INT;
1064 }
1065 
1066 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1067 {
1068         struct uart_port *port = &priv->port;
1069         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1070         char   *error_msg[5] = {};
1071         int    i = 0;
1072 
1073         if (lsr & PCH_UART_LSR_ERR)
1074                 error_msg[i++] = "Error data in FIFO\n";
1075 
1076         if (lsr & UART_LSR_FE) {
1077                 port->icount.frame++;
1078                 error_msg[i++] = "  Framing Error\n";
1079         }
1080 
1081         if (lsr & UART_LSR_PE) {
1082                 port->icount.parity++;
1083                 error_msg[i++] = "  Parity Error\n";
1084         }
1085 
1086         if (lsr & UART_LSR_OE) {
1087                 port->icount.overrun++;
1088                 error_msg[i++] = "  Overrun Error\n";
1089         }
1090 
1091         if (tty == NULL) {
1092                 for (i = 0; error_msg[i] != NULL; i++)
1093                         dev_err(&priv->pdev->dev, error_msg[i]);
1094         } else {
1095                 tty_kref_put(tty);
1096         }
1097 }
1098 
1099 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1100 {
1101         struct eg20t_port *priv = dev_id;
1102         unsigned int handled;
1103         u8 lsr;
1104         int ret = 0;
1105         unsigned char iid;
1106         unsigned long flags;
1107         int next = 1;
1108         u8 msr;
1109 
1110         spin_lock_irqsave(&priv->lock, flags);
1111         handled = 0;
1112         while (next) {
1113                 iid = pch_uart_hal_get_iid(priv);
1114                 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1115                         break;
1116                 switch (iid) {
1117                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
1118                         lsr = pch_uart_hal_get_line_status(priv);
1119                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1120                                                 UART_LSR_PE | UART_LSR_OE)) {
1121                                 pch_uart_err_ir(priv, lsr);
1122                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
1123                         } else {
1124                                 ret = PCH_UART_HANDLED_LS_INT;
1125                         }
1126                         break;
1127                 case PCH_UART_IID_RDR:  /* Received Data Ready */
1128                         if (priv->use_dma) {
1129                                 pch_uart_hal_disable_interrupt(priv,
1130                                                 PCH_UART_HAL_RX_INT |
1131                                                 PCH_UART_HAL_RX_ERR_INT);
1132                                 ret = dma_handle_rx(priv);
1133                                 if (!ret)
1134                                         pch_uart_hal_enable_interrupt(priv,
1135                                                 PCH_UART_HAL_RX_INT |
1136                                                 PCH_UART_HAL_RX_ERR_INT);
1137                         } else {
1138                                 ret = handle_rx(priv);
1139                         }
1140                         break;
1141                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1142                                                    (FIFO Timeout) */
1143                         ret = handle_rx_to(priv);
1144                         break;
1145                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1146                                                    Empty */
1147                         if (priv->use_dma)
1148                                 ret = dma_handle_tx(priv);
1149                         else
1150                                 ret = handle_tx(priv);
1151                         break;
1152                 case PCH_UART_IID_MS:   /* Modem Status */
1153                         msr = pch_uart_hal_get_modem(priv);
1154                         next = 0; /* MS ir prioirty is the lowest. So, MS ir
1155                                      means final interrupt */
1156                         if ((msr & UART_MSR_ANY_DELTA) == 0)
1157                                 break;
1158                         ret |= PCH_UART_HANDLED_MS_INT;
1159                         break;
1160                 default:        /* Never junp to this label */
1161                         dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1162                                 iid, jiffies);
1163                         ret = -1;
1164                         next = 0;
1165                         break;
1166                 }
1167                 handled |= (unsigned int)ret;
1168         }
1169 
1170         spin_unlock_irqrestore(&priv->lock, flags);
1171         return IRQ_RETVAL(handled);
1172 }
1173 
1174 /* This function tests whether the transmitter fifo and shifter for the port
1175                                                 described by 'port' is empty. */
1176 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1177 {
1178         struct eg20t_port *priv;
1179 
1180         priv = container_of(port, struct eg20t_port, port);
1181         if (priv->tx_empty)
1182                 return TIOCSER_TEMT;
1183         else
1184                 return 0;
1185 }
1186 
1187 /* Returns the current state of modem control inputs. */
1188 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1189 {
1190         struct eg20t_port *priv;
1191         u8 modem;
1192         unsigned int ret = 0;
1193 
1194         priv = container_of(port, struct eg20t_port, port);
1195         modem = pch_uart_hal_get_modem(priv);
1196 
1197         if (modem & UART_MSR_DCD)
1198                 ret |= TIOCM_CAR;
1199 
1200         if (modem & UART_MSR_RI)
1201                 ret |= TIOCM_RNG;
1202 
1203         if (modem & UART_MSR_DSR)
1204                 ret |= TIOCM_DSR;
1205 
1206         if (modem & UART_MSR_CTS)
1207                 ret |= TIOCM_CTS;
1208 
1209         return ret;
1210 }
1211 
1212 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1213 {
1214         u32 mcr = 0;
1215         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1216 
1217         if (mctrl & TIOCM_DTR)
1218                 mcr |= UART_MCR_DTR;
1219         if (mctrl & TIOCM_RTS)
1220                 mcr |= UART_MCR_RTS;
1221         if (mctrl & TIOCM_LOOP)
1222                 mcr |= UART_MCR_LOOP;
1223 
1224         if (priv->mcr & UART_MCR_AFE)
1225                 mcr |= UART_MCR_AFE;
1226 
1227         if (mctrl)
1228                 iowrite8(mcr, priv->membase + UART_MCR);
1229 }
1230 
1231 static void pch_uart_stop_tx(struct uart_port *port)
1232 {
1233         struct eg20t_port *priv;
1234         priv = container_of(port, struct eg20t_port, port);
1235         priv->start_tx = 0;
1236         priv->tx_dma_use = 0;
1237 }
1238 
1239 static void pch_uart_start_tx(struct uart_port *port)
1240 {
1241         struct eg20t_port *priv;
1242 
1243         priv = container_of(port, struct eg20t_port, port);
1244 
1245         if (priv->use_dma) {
1246                 if (priv->tx_dma_use) {
1247                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1248                                 __func__);
1249                         return;
1250                 }
1251         }
1252 
1253         priv->start_tx = 1;
1254         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1255 }
1256 
1257 static void pch_uart_stop_rx(struct uart_port *port)
1258 {
1259         struct eg20t_port *priv;
1260         priv = container_of(port, struct eg20t_port, port);
1261         priv->start_rx = 0;
1262         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1263                                              PCH_UART_HAL_RX_ERR_INT);
1264 }
1265 
1266 /* Enable the modem status interrupts. */
1267 static void pch_uart_enable_ms(struct uart_port *port)
1268 {
1269         struct eg20t_port *priv;
1270         priv = container_of(port, struct eg20t_port, port);
1271         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1272 }
1273 
1274 /* Control the transmission of a break signal. */
1275 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1276 {
1277         struct eg20t_port *priv;
1278         unsigned long flags;
1279 
1280         priv = container_of(port, struct eg20t_port, port);
1281         spin_lock_irqsave(&priv->lock, flags);
1282         pch_uart_hal_set_break(priv, ctl);
1283         spin_unlock_irqrestore(&priv->lock, flags);
1284 }
1285 
1286 /* Grab any interrupt resources and initialise any low level driver state. */
1287 static int pch_uart_startup(struct uart_port *port)
1288 {
1289         struct eg20t_port *priv;
1290         int ret;
1291         int fifo_size;
1292         int trigger_level;
1293 
1294         priv = container_of(port, struct eg20t_port, port);
1295         priv->tx_empty = 1;
1296 
1297         if (port->uartclk)
1298                 priv->uartclk = port->uartclk;
1299         else
1300                 port->uartclk = priv->uartclk;
1301 
1302         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1303         ret = pch_uart_hal_set_line(priv, default_baud,
1304                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1305                               PCH_UART_HAL_STB1);
1306         if (ret)
1307                 return ret;
1308 
1309         switch (priv->fifo_size) {
1310         case 256:
1311                 fifo_size = PCH_UART_HAL_FIFO256;
1312                 break;
1313         case 64:
1314                 fifo_size = PCH_UART_HAL_FIFO64;
1315                 break;
1316         case 16:
1317                 fifo_size = PCH_UART_HAL_FIFO16;
1318                 break;
1319         case 1:
1320         default:
1321                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1322                 break;
1323         }
1324 
1325         switch (priv->trigger) {
1326         case PCH_UART_HAL_TRIGGER1:
1327                 trigger_level = 1;
1328                 break;
1329         case PCH_UART_HAL_TRIGGER_L:
1330                 trigger_level = priv->fifo_size / 4;
1331                 break;
1332         case PCH_UART_HAL_TRIGGER_M:
1333                 trigger_level = priv->fifo_size / 2;
1334                 break;
1335         case PCH_UART_HAL_TRIGGER_H:
1336         default:
1337                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1338                 break;
1339         }
1340 
1341         priv->trigger_level = trigger_level;
1342         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1343                                     fifo_size, priv->trigger);
1344         if (ret < 0)
1345                 return ret;
1346 
1347         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1348                         priv->irq_name, priv);
1349         if (ret < 0)
1350                 return ret;
1351 
1352         if (priv->use_dma)
1353                 pch_request_dma(port);
1354 
1355         priv->start_rx = 1;
1356         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1357                                             PCH_UART_HAL_RX_ERR_INT);
1358         uart_update_timeout(port, CS8, default_baud);
1359 
1360         return 0;
1361 }
1362 
1363 static void pch_uart_shutdown(struct uart_port *port)
1364 {
1365         struct eg20t_port *priv;
1366         int ret;
1367 
1368         priv = container_of(port, struct eg20t_port, port);
1369         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1370         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1371         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1372                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1373         if (ret)
1374                 dev_err(priv->port.dev,
1375                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1376 
1377         pch_free_dma(port);
1378 
1379         free_irq(priv->port.irq, priv);
1380 }
1381 
1382 /* Change the port parameters, including word length, parity, stop
1383  *bits.  Update read_status_mask and ignore_status_mask to indicate
1384  *the types of events we are interested in receiving.  */
1385 static void pch_uart_set_termios(struct uart_port *port,
1386                                  struct ktermios *termios, struct ktermios *old)
1387 {
1388         int rtn;
1389         unsigned int baud, parity, bits, stb;
1390         struct eg20t_port *priv;
1391         unsigned long flags;
1392 
1393         priv = container_of(port, struct eg20t_port, port);
1394         switch (termios->c_cflag & CSIZE) {
1395         case CS5:
1396                 bits = PCH_UART_HAL_5BIT;
1397                 break;
1398         case CS6:
1399                 bits = PCH_UART_HAL_6BIT;
1400                 break;
1401         case CS7:
1402                 bits = PCH_UART_HAL_7BIT;
1403                 break;
1404         default:                /* CS8 */
1405                 bits = PCH_UART_HAL_8BIT;
1406                 break;
1407         }
1408         if (termios->c_cflag & CSTOPB)
1409                 stb = PCH_UART_HAL_STB2;
1410         else
1411                 stb = PCH_UART_HAL_STB1;
1412 
1413         if (termios->c_cflag & PARENB) {
1414                 if (termios->c_cflag & PARODD)
1415                         parity = PCH_UART_HAL_PARITY_ODD;
1416                 else
1417                         parity = PCH_UART_HAL_PARITY_EVEN;
1418 
1419         } else
1420                 parity = PCH_UART_HAL_PARITY_NONE;
1421 
1422         /* Only UART0 has auto hardware flow function */
1423         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1424                 priv->mcr |= UART_MCR_AFE;
1425         else
1426                 priv->mcr &= ~UART_MCR_AFE;
1427 
1428         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1429 
1430         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1431 
1432         spin_lock_irqsave(&priv->lock, flags);
1433         spin_lock(&port->lock);
1434 
1435         uart_update_timeout(port, termios->c_cflag, baud);
1436         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1437         if (rtn)
1438                 goto out;
1439 
1440         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1441         /* Don't rewrite B0 */
1442         if (tty_termios_baud_rate(termios))
1443                 tty_termios_encode_baud_rate(termios, baud, baud);
1444 
1445 out:
1446         spin_unlock(&port->lock);
1447         spin_unlock_irqrestore(&priv->lock, flags);
1448 }
1449 
1450 static const char *pch_uart_type(struct uart_port *port)
1451 {
1452         return KBUILD_MODNAME;
1453 }
1454 
1455 static void pch_uart_release_port(struct uart_port *port)
1456 {
1457         struct eg20t_port *priv;
1458 
1459         priv = container_of(port, struct eg20t_port, port);
1460         pci_iounmap(priv->pdev, priv->membase);
1461         pci_release_regions(priv->pdev);
1462 }
1463 
1464 static int pch_uart_request_port(struct uart_port *port)
1465 {
1466         struct eg20t_port *priv;
1467         int ret;
1468         void __iomem *membase;
1469 
1470         priv = container_of(port, struct eg20t_port, port);
1471         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1472         if (ret < 0)
1473                 return -EBUSY;
1474 
1475         membase = pci_iomap(priv->pdev, 1, 0);
1476         if (!membase) {
1477                 pci_release_regions(priv->pdev);
1478                 return -EBUSY;
1479         }
1480         priv->membase = port->membase = membase;
1481 
1482         return 0;
1483 }
1484 
1485 static void pch_uart_config_port(struct uart_port *port, int type)
1486 {
1487         struct eg20t_port *priv;
1488 
1489         priv = container_of(port, struct eg20t_port, port);
1490         if (type & UART_CONFIG_TYPE) {
1491                 port->type = priv->port_type;
1492                 pch_uart_request_port(port);
1493         }
1494 }
1495 
1496 static int pch_uart_verify_port(struct uart_port *port,
1497                                 struct serial_struct *serinfo)
1498 {
1499         struct eg20t_port *priv;
1500 
1501         priv = container_of(port, struct eg20t_port, port);
1502         if (serinfo->flags & UPF_LOW_LATENCY) {
1503                 dev_info(priv->port.dev,
1504                         "PCH UART : Use PIO Mode (without DMA)\n");
1505                 priv->use_dma = 0;
1506                 serinfo->flags &= ~UPF_LOW_LATENCY;
1507         } else {
1508 #ifndef CONFIG_PCH_DMA
1509                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1510                         __func__);
1511                 return -EOPNOTSUPP;
1512 #endif
1513                 if (!priv->use_dma) {
1514                         pch_request_dma(port);
1515                         if (priv->chan_rx)
1516                                 priv->use_dma = 1;
1517                 }
1518                 dev_info(priv->port.dev, "PCH UART: %s\n",
1519                                 priv->use_dma ?
1520                                 "Use DMA Mode" : "No DMA");
1521         }
1522 
1523         return 0;
1524 }
1525 
1526 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1527 /*
1528  *      Wait for transmitter & holding register to empty
1529  */
1530 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1531 {
1532         unsigned int status, tmout = 10000;
1533 
1534         /* Wait up to 10ms for the character(s) to be sent. */
1535         for (;;) {
1536                 status = ioread8(up->membase + UART_LSR);
1537 
1538                 if ((status & bits) == bits)
1539                         break;
1540                 if (--tmout == 0)
1541                         break;
1542                 udelay(1);
1543         }
1544 
1545         /* Wait up to 1s for flow control if necessary */
1546         if (up->port.flags & UPF_CONS_FLOW) {
1547                 unsigned int tmout;
1548                 for (tmout = 1000000; tmout; tmout--) {
1549                         unsigned int msr = ioread8(up->membase + UART_MSR);
1550                         if (msr & UART_MSR_CTS)
1551                                 break;
1552                         udelay(1);
1553                         touch_nmi_watchdog();
1554                 }
1555         }
1556 }
1557 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1558 
1559 #ifdef CONFIG_CONSOLE_POLL
1560 /*
1561  * Console polling routines for communicate via uart while
1562  * in an interrupt or debug context.
1563  */
1564 static int pch_uart_get_poll_char(struct uart_port *port)
1565 {
1566         struct eg20t_port *priv =
1567                 container_of(port, struct eg20t_port, port);
1568         u8 lsr = ioread8(priv->membase + UART_LSR);
1569 
1570         if (!(lsr & UART_LSR_DR))
1571                 return NO_POLL_CHAR;
1572 
1573         return ioread8(priv->membase + PCH_UART_RBR);
1574 }
1575 
1576 
1577 static void pch_uart_put_poll_char(struct uart_port *port,
1578                          unsigned char c)
1579 {
1580         unsigned int ier;
1581         struct eg20t_port *priv =
1582                 container_of(port, struct eg20t_port, port);
1583 
1584         /*
1585          * First save the IER then disable the interrupts
1586          */
1587         ier = ioread8(priv->membase + UART_IER);
1588         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1589 
1590         wait_for_xmitr(priv, UART_LSR_THRE);
1591         /*
1592          * Send the character out.
1593          */
1594         iowrite8(c, priv->membase + PCH_UART_THR);
1595 
1596         /*
1597          * Finally, wait for transmitter to become empty
1598          * and restore the IER
1599          */
1600         wait_for_xmitr(priv, BOTH_EMPTY);
1601         iowrite8(ier, priv->membase + UART_IER);
1602 }
1603 #endif /* CONFIG_CONSOLE_POLL */
1604 
1605 static struct uart_ops pch_uart_ops = {
1606         .tx_empty = pch_uart_tx_empty,
1607         .set_mctrl = pch_uart_set_mctrl,
1608         .get_mctrl = pch_uart_get_mctrl,
1609         .stop_tx = pch_uart_stop_tx,
1610         .start_tx = pch_uart_start_tx,
1611         .stop_rx = pch_uart_stop_rx,
1612         .enable_ms = pch_uart_enable_ms,
1613         .break_ctl = pch_uart_break_ctl,
1614         .startup = pch_uart_startup,
1615         .shutdown = pch_uart_shutdown,
1616         .set_termios = pch_uart_set_termios,
1617 /*      .pm             = pch_uart_pm,          Not supported yet */
1618         .type = pch_uart_type,
1619         .release_port = pch_uart_release_port,
1620         .request_port = pch_uart_request_port,
1621         .config_port = pch_uart_config_port,
1622         .verify_port = pch_uart_verify_port,
1623 #ifdef CONFIG_CONSOLE_POLL
1624         .poll_get_char = pch_uart_get_poll_char,
1625         .poll_put_char = pch_uart_put_poll_char,
1626 #endif
1627 };
1628 
1629 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1630 
1631 static void pch_console_putchar(struct uart_port *port, int ch)
1632 {
1633         struct eg20t_port *priv =
1634                 container_of(port, struct eg20t_port, port);
1635 
1636         wait_for_xmitr(priv, UART_LSR_THRE);
1637         iowrite8(ch, priv->membase + PCH_UART_THR);
1638 }
1639 
1640 /*
1641  *      Print a string to the serial port trying not to disturb
1642  *      any possible real use of the port...
1643  *
1644  *      The console_lock must be held when we get here.
1645  */
1646 static void
1647 pch_console_write(struct console *co, const char *s, unsigned int count)
1648 {
1649         struct eg20t_port *priv;
1650         unsigned long flags;
1651         int priv_locked = 1;
1652         int port_locked = 1;
1653         u8 ier;
1654 
1655         priv = pch_uart_ports[co->index];
1656 
1657         touch_nmi_watchdog();
1658 
1659         local_irq_save(flags);
1660         if (priv->port.sysrq) {
1661                 /* call to uart_handle_sysrq_char already took the priv lock */
1662                 priv_locked = 0;
1663                 /* serial8250_handle_port() already took the port lock */
1664                 port_locked = 0;
1665         } else if (oops_in_progress) {
1666                 priv_locked = spin_trylock(&priv->lock);
1667                 port_locked = spin_trylock(&priv->port.lock);
1668         } else {
1669                 spin_lock(&priv->lock);
1670                 spin_lock(&priv->port.lock);
1671         }
1672 
1673         /*
1674          *      First save the IER then disable the interrupts
1675          */
1676         ier = ioread8(priv->membase + UART_IER);
1677 
1678         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1679 
1680         uart_console_write(&priv->port, s, count, pch_console_putchar);
1681 
1682         /*
1683          *      Finally, wait for transmitter to become empty
1684          *      and restore the IER
1685          */
1686         wait_for_xmitr(priv, BOTH_EMPTY);
1687         iowrite8(ier, priv->membase + UART_IER);
1688 
1689         if (port_locked)
1690                 spin_unlock(&priv->port.lock);
1691         if (priv_locked)
1692                 spin_unlock(&priv->lock);
1693         local_irq_restore(flags);
1694 }
1695 
1696 static int __init pch_console_setup(struct console *co, char *options)
1697 {
1698         struct uart_port *port;
1699         int baud = default_baud;
1700         int bits = 8;
1701         int parity = 'n';
1702         int flow = 'n';
1703 
1704         /*
1705          * Check whether an invalid uart number has been specified, and
1706          * if so, search for the first available port that does have
1707          * console support.
1708          */
1709         if (co->index >= PCH_UART_NR)
1710                 co->index = 0;
1711         port = &pch_uart_ports[co->index]->port;
1712 
1713         if (!port || (!port->iobase && !port->membase))
1714                 return -ENODEV;
1715 
1716         port->uartclk = pch_uart_get_uartclk();
1717 
1718         if (options)
1719                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1720 
1721         return uart_set_options(port, co, baud, parity, bits, flow);
1722 }
1723 
1724 static struct uart_driver pch_uart_driver;
1725 
1726 static struct console pch_console = {
1727         .name           = PCH_UART_DRIVER_DEVICE,
1728         .write          = pch_console_write,
1729         .device         = uart_console_device,
1730         .setup          = pch_console_setup,
1731         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
1732         .index          = -1,
1733         .data           = &pch_uart_driver,
1734 };
1735 
1736 #define PCH_CONSOLE     (&pch_console)
1737 #else
1738 #define PCH_CONSOLE     NULL
1739 #endif  /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1740 
1741 static struct uart_driver pch_uart_driver = {
1742         .owner = THIS_MODULE,
1743         .driver_name = KBUILD_MODNAME,
1744         .dev_name = PCH_UART_DRIVER_DEVICE,
1745         .major = 0,
1746         .minor = 0,
1747         .nr = PCH_UART_NR,
1748         .cons = PCH_CONSOLE,
1749 };
1750 
1751 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1752                                              const struct pci_device_id *id)
1753 {
1754         struct eg20t_port *priv;
1755         int ret;
1756         unsigned int iobase;
1757         unsigned int mapbase;
1758         unsigned char *rxbuf;
1759         int fifosize;
1760         int port_type;
1761         struct pch_uart_driver_data *board;
1762 #ifdef CONFIG_DEBUG_FS
1763         char name[32];  /* for debugfs file name */
1764 #endif
1765 
1766         board = &drv_dat[id->driver_data];
1767         port_type = board->port_type;
1768 
1769         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1770         if (priv == NULL)
1771                 goto init_port_alloc_err;
1772 
1773         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1774         if (!rxbuf)
1775                 goto init_port_free_txbuf;
1776 
1777         switch (port_type) {
1778         case PORT_UNKNOWN:
1779                 fifosize = 256; /* EG20T/ML7213: UART0 */
1780                 break;
1781         case PORT_8250:
1782                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1783                 break;
1784         default:
1785                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1786                 goto init_port_hal_free;
1787         }
1788 
1789         pci_enable_msi(pdev);
1790         pci_set_master(pdev);
1791 
1792         spin_lock_init(&priv->lock);
1793 
1794         iobase = pci_resource_start(pdev, 0);
1795         mapbase = pci_resource_start(pdev, 1);
1796         priv->mapbase = mapbase;
1797         priv->iobase = iobase;
1798         priv->pdev = pdev;
1799         priv->tx_empty = 1;
1800         priv->rxbuf.buf = rxbuf;
1801         priv->rxbuf.size = PAGE_SIZE;
1802 
1803         priv->fifo_size = fifosize;
1804         priv->uartclk = pch_uart_get_uartclk();
1805         priv->port_type = PORT_MAX_8250 + port_type + 1;
1806         priv->port.dev = &pdev->dev;
1807         priv->port.iobase = iobase;
1808         priv->port.membase = NULL;
1809         priv->port.mapbase = mapbase;
1810         priv->port.irq = pdev->irq;
1811         priv->port.iotype = UPIO_PORT;
1812         priv->port.ops = &pch_uart_ops;
1813         priv->port.flags = UPF_BOOT_AUTOCONF;
1814         priv->port.fifosize = fifosize;
1815         priv->port.line = board->line_no;
1816         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1817 
1818         snprintf(priv->irq_name, IRQ_NAME_SIZE,
1819                  KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1820                  priv->port.line);
1821 
1822         spin_lock_init(&priv->port.lock);
1823 
1824         pci_set_drvdata(pdev, priv);
1825         priv->trigger_level = 1;
1826         priv->fcr = 0;
1827 
1828 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1829         pch_uart_ports[board->line_no] = priv;
1830 #endif
1831         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1832         if (ret < 0)
1833                 goto init_port_hal_free;
1834 
1835 #ifdef CONFIG_DEBUG_FS
1836         snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1837         priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1838                                 NULL, priv, &port_regs_ops);
1839 #endif
1840 
1841         return priv;
1842 
1843 init_port_hal_free:
1844 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1845         pch_uart_ports[board->line_no] = NULL;
1846 #endif
1847         free_page((unsigned long)rxbuf);
1848 init_port_free_txbuf:
1849         kfree(priv);
1850 init_port_alloc_err:
1851 
1852         return NULL;
1853 }
1854 
1855 static void pch_uart_exit_port(struct eg20t_port *priv)
1856 {
1857 
1858 #ifdef CONFIG_DEBUG_FS
1859         if (priv->debugfs)
1860                 debugfs_remove(priv->debugfs);
1861 #endif
1862         uart_remove_one_port(&pch_uart_driver, &priv->port);
1863         free_page((unsigned long)priv->rxbuf.buf);
1864 }
1865 
1866 static void pch_uart_pci_remove(struct pci_dev *pdev)
1867 {
1868         struct eg20t_port *priv = pci_get_drvdata(pdev);
1869 
1870         pci_disable_msi(pdev);
1871 
1872 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1873         pch_uart_ports[priv->port.line] = NULL;
1874 #endif
1875         pch_uart_exit_port(priv);
1876         pci_disable_device(pdev);
1877         kfree(priv);
1878         return;
1879 }
1880 #ifdef CONFIG_PM
1881 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1882 {
1883         struct eg20t_port *priv = pci_get_drvdata(pdev);
1884 
1885         uart_suspend_port(&pch_uart_driver, &priv->port);
1886 
1887         pci_save_state(pdev);
1888         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1889         return 0;
1890 }
1891 
1892 static int pch_uart_pci_resume(struct pci_dev *pdev)
1893 {
1894         struct eg20t_port *priv = pci_get_drvdata(pdev);
1895         int ret;
1896 
1897         pci_set_power_state(pdev, PCI_D0);
1898         pci_restore_state(pdev);
1899 
1900         ret = pci_enable_device(pdev);
1901         if (ret) {
1902                 dev_err(&pdev->dev,
1903                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1904                 return ret;
1905         }
1906 
1907         uart_resume_port(&pch_uart_driver, &priv->port);
1908 
1909         return 0;
1910 }
1911 #else
1912 #define pch_uart_pci_suspend NULL
1913 #define pch_uart_pci_resume NULL
1914 #endif
1915 
1916 static const struct pci_device_id pch_uart_pci_id[] = {
1917         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1918          .driver_data = pch_et20t_uart0},
1919         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1920          .driver_data = pch_et20t_uart1},
1921         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1922          .driver_data = pch_et20t_uart2},
1923         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1924          .driver_data = pch_et20t_uart3},
1925         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1926          .driver_data = pch_ml7213_uart0},
1927         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1928          .driver_data = pch_ml7213_uart1},
1929         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1930          .driver_data = pch_ml7213_uart2},
1931         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1932          .driver_data = pch_ml7223_uart0},
1933         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1934          .driver_data = pch_ml7223_uart1},
1935         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1936          .driver_data = pch_ml7831_uart0},
1937         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1938          .driver_data = pch_ml7831_uart1},
1939         {0,},
1940 };
1941 
1942 static int pch_uart_pci_probe(struct pci_dev *pdev,
1943                                         const struct pci_device_id *id)
1944 {
1945         int ret;
1946         struct eg20t_port *priv;
1947 
1948         ret = pci_enable_device(pdev);
1949         if (ret < 0)
1950                 goto probe_error;
1951 
1952         priv = pch_uart_init_port(pdev, id);
1953         if (!priv) {
1954                 ret = -EBUSY;
1955                 goto probe_disable_device;
1956         }
1957         pci_set_drvdata(pdev, priv);
1958 
1959         return ret;
1960 
1961 probe_disable_device:
1962         pci_disable_msi(pdev);
1963         pci_disable_device(pdev);
1964 probe_error:
1965         return ret;
1966 }
1967 
1968 static struct pci_driver pch_uart_pci_driver = {
1969         .name = "pch_uart",
1970         .id_table = pch_uart_pci_id,
1971         .probe = pch_uart_pci_probe,
1972         .remove = pch_uart_pci_remove,
1973         .suspend = pch_uart_pci_suspend,
1974         .resume = pch_uart_pci_resume,
1975 };
1976 
1977 static int __init pch_uart_module_init(void)
1978 {
1979         int ret;
1980 
1981         /* register as UART driver */
1982         ret = uart_register_driver(&pch_uart_driver);
1983         if (ret < 0)
1984                 return ret;
1985 
1986         /* register as PCI driver */
1987         ret = pci_register_driver(&pch_uart_pci_driver);
1988         if (ret < 0)
1989                 uart_unregister_driver(&pch_uart_driver);
1990 
1991         return ret;
1992 }
1993 module_init(pch_uart_module_init);
1994 
1995 static void __exit pch_uart_module_exit(void)
1996 {
1997         pci_unregister_driver(&pch_uart_pci_driver);
1998         uart_unregister_driver(&pch_uart_driver);
1999 }
2000 module_exit(pch_uart_module_exit);
2001 
2002 MODULE_LICENSE("GPL v2");
2003 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
2004 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
2005 
2006 module_param(default_baud, uint, S_IRUGO);
2007 MODULE_PARM_DESC(default_baud,
2008                  "Default BAUD for initial driver state and console (default 9600)");
2009 module_param(user_uartclk, uint, S_IRUGO);
2010 MODULE_PARM_DESC(user_uartclk,
2011                  "Override UART default or board specific UART clock");
2012 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us