Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/tty/serial/omap-serial.c

  1 /*
  2  * Driver for OMAP-UART controller.
  3  * Based on drivers/serial/8250.c
  4  *
  5  * Copyright (C) 2010 Texas Instruments.
  6  *
  7  * Authors:
  8  *      Govindraj R     <govindraj.raja@ti.com>
  9  *      Thara Gopinath  <thara@ti.com>
 10  *
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License as published by
 13  * the Free Software Foundation; either version 2 of the License, or
 14  * (at your option) any later version.
 15  *
 16  * Note: This driver is made separate from 8250 driver as we cannot
 17  * over load 8250 driver with omap platform specific configuration for
 18  * features like DMA, it makes easier to implement features like DMA and
 19  * hardware flow control and software flow control configuration with
 20  * this driver as required for the omap-platform.
 21  */
 22 
 23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 24 #define SUPPORT_SYSRQ
 25 #endif
 26 
 27 #include <linux/module.h>
 28 #include <linux/init.h>
 29 #include <linux/console.h>
 30 #include <linux/serial_reg.h>
 31 #include <linux/delay.h>
 32 #include <linux/slab.h>
 33 #include <linux/tty.h>
 34 #include <linux/tty_flip.h>
 35 #include <linux/platform_device.h>
 36 #include <linux/io.h>
 37 #include <linux/clk.h>
 38 #include <linux/serial_core.h>
 39 #include <linux/irq.h>
 40 #include <linux/pm_runtime.h>
 41 #include <linux/of.h>
 42 #include <linux/of_irq.h>
 43 #include <linux/gpio.h>
 44 #include <linux/of_gpio.h>
 45 #include <linux/platform_data/serial-omap.h>
 46 
 47 #include <dt-bindings/gpio/gpio.h>
 48 
 49 #define OMAP_MAX_HSUART_PORTS   10
 50 
 51 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
 52 
 53 #define OMAP_UART_REV_42 0x0402
 54 #define OMAP_UART_REV_46 0x0406
 55 #define OMAP_UART_REV_52 0x0502
 56 #define OMAP_UART_REV_63 0x0603
 57 
 58 #define OMAP_UART_TX_WAKEUP_EN          BIT(7)
 59 
 60 /* Feature flags */
 61 #define OMAP_UART_WER_HAS_TX_WAKEUP     BIT(0)
 62 
 63 #define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
 64 #define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
 65 
 66 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
 67 
 68 /* SCR register bitmasks */
 69 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
 70 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK               (1 << 6)
 71 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
 72 
 73 /* FCR register bitmasks */
 74 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
 75 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
 76 
 77 /* MVR register bitmasks */
 78 #define OMAP_UART_MVR_SCHEME_SHIFT      30
 79 
 80 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
 81 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
 82 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
 83 
 84 #define OMAP_UART_MVR_MAJ_MASK          0x700
 85 #define OMAP_UART_MVR_MAJ_SHIFT         8
 86 #define OMAP_UART_MVR_MIN_MASK          0x3f
 87 
 88 #define OMAP_UART_DMA_CH_FREE   -1
 89 
 90 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
 91 #define OMAP_MODE13X_SPEED      230400
 92 
 93 /* WER = 0x7F
 94  * Enable module level wakeup in WER reg
 95  */
 96 #define OMAP_UART_WER_MOD_WKUP  0x7F
 97 
 98 /* Enable XON/XOFF flow control on output */
 99 #define OMAP_UART_SW_TX         0x08
100 
101 /* Enable XON/XOFF flow control on input */
102 #define OMAP_UART_SW_RX         0x02
103 
104 #define OMAP_UART_SW_CLR        0xF0
105 
106 #define OMAP_UART_TCR_TRIG      0x0F
107 
108 struct uart_omap_dma {
109         u8                      uart_dma_tx;
110         u8                      uart_dma_rx;
111         int                     rx_dma_channel;
112         int                     tx_dma_channel;
113         dma_addr_t              rx_buf_dma_phys;
114         dma_addr_t              tx_buf_dma_phys;
115         unsigned int            uart_base;
116         /*
117          * Buffer for rx dma. It is not required for tx because the buffer
118          * comes from port structure.
119          */
120         unsigned char           *rx_buf;
121         unsigned int            prev_rx_dma_pos;
122         int                     tx_buf_size;
123         int                     tx_dma_used;
124         int                     rx_dma_used;
125         spinlock_t              tx_lock;
126         spinlock_t              rx_lock;
127         /* timer to poll activity on rx dma */
128         struct timer_list       rx_timer;
129         unsigned int            rx_buf_size;
130         unsigned int            rx_poll_rate;
131         unsigned int            rx_timeout;
132 };
133 
134 struct uart_omap_port {
135         struct uart_port        port;
136         struct uart_omap_dma    uart_dma;
137         struct device           *dev;
138         int                     wakeirq;
139 
140         unsigned char           ier;
141         unsigned char           lcr;
142         unsigned char           mcr;
143         unsigned char           fcr;
144         unsigned char           efr;
145         unsigned char           dll;
146         unsigned char           dlh;
147         unsigned char           mdr1;
148         unsigned char           scr;
149         unsigned char           wer;
150 
151         int                     use_dma;
152         /*
153          * Some bits in registers are cleared on a read, so they must
154          * be saved whenever the register is read, but the bits will not
155          * be immediately processed.
156          */
157         unsigned int            lsr_break_flag;
158         unsigned char           msr_saved_flags;
159         char                    name[20];
160         unsigned long           port_activity;
161         int                     context_loss_cnt;
162         u32                     errata;
163         u8                      wakeups_enabled;
164         u32                     features;
165 
166         int                     rts_gpio;
167 
168         struct pm_qos_request   pm_qos_request;
169         u32                     latency;
170         u32                     calc_latency;
171         struct work_struct      qos_work;
172         bool                    is_suspending;
173 };
174 
175 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
176 
177 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
178 
179 /* Forward declaration of functions */
180 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
181 
182 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
183 {
184         offset <<= up->port.regshift;
185         return readw(up->port.membase + offset);
186 }
187 
188 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
189 {
190         offset <<= up->port.regshift;
191         writew(value, up->port.membase + offset);
192 }
193 
194 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
195 {
196         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
197         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
198                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
199         serial_out(up, UART_FCR, 0);
200 }
201 
202 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
203 {
204         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
205 
206         if (!pdata || !pdata->get_context_loss_count)
207                 return -EINVAL;
208 
209         return pdata->get_context_loss_count(up->dev);
210 }
211 
212 static inline void serial_omap_enable_wakeirq(struct uart_omap_port *up,
213                                        bool enable)
214 {
215         if (!up->wakeirq)
216                 return;
217 
218         if (enable)
219                 enable_irq(up->wakeirq);
220         else
221                 disable_irq_nosync(up->wakeirq);
222 }
223 
224 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
225 {
226         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
227 
228         if (enable == up->wakeups_enabled)
229                 return;
230 
231         serial_omap_enable_wakeirq(up, enable);
232         up->wakeups_enabled = enable;
233 
234         if (!pdata || !pdata->enable_wakeup)
235                 return;
236 
237         pdata->enable_wakeup(up->dev, enable);
238 }
239 
240 /*
241  * Calculate the absolute difference between the desired and actual baud
242  * rate for the given mode.
243  */
244 static inline int calculate_baud_abs_diff(struct uart_port *port,
245                                 unsigned int baud, unsigned int mode)
246 {
247         unsigned int n = port->uartclk / (mode * baud);
248         int abs_diff;
249 
250         if (n == 0)
251                 n = 1;
252 
253         abs_diff = baud - (port->uartclk / (mode * n));
254         if (abs_diff < 0)
255                 abs_diff = -abs_diff;
256 
257         return abs_diff;
258 }
259 
260 /*
261  * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
262  * @port: uart port info
263  * @baud: baudrate for which mode needs to be determined
264  *
265  * Returns true if baud rate is MODE16X and false if MODE13X
266  * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
267  * and Error Rates" determines modes not for all common baud rates.
268  * E.g. for 1000000 baud rate mode must be 16x, but according to that
269  * table it's determined as 13x.
270  */
271 static bool
272 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
273 {
274         int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
275         int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
276 
277         return (abs_diff_13 >= abs_diff_16);
278 }
279 
280 /*
281  * serial_omap_get_divisor - calculate divisor value
282  * @port: uart port info
283  * @baud: baudrate for which divisor needs to be calculated.
284  */
285 static unsigned int
286 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
287 {
288         unsigned int mode;
289 
290         if (!serial_omap_baud_is_mode16(port, baud))
291                 mode = 13;
292         else
293                 mode = 16;
294         return port->uartclk/(mode * baud);
295 }
296 
297 static void serial_omap_enable_ms(struct uart_port *port)
298 {
299         struct uart_omap_port *up = to_uart_omap_port(port);
300 
301         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
302 
303         pm_runtime_get_sync(up->dev);
304         up->ier |= UART_IER_MSI;
305         serial_out(up, UART_IER, up->ier);
306         pm_runtime_mark_last_busy(up->dev);
307         pm_runtime_put_autosuspend(up->dev);
308 }
309 
310 static void serial_omap_stop_tx(struct uart_port *port)
311 {
312         struct uart_omap_port *up = to_uart_omap_port(port);
313         int res;
314 
315         pm_runtime_get_sync(up->dev);
316 
317         /* Handle RS-485 */
318         if (port->rs485.flags & SER_RS485_ENABLED) {
319                 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
320                         /* THR interrupt is fired when both TX FIFO and TX
321                          * shift register are empty. This means there's nothing
322                          * left to transmit now, so make sure the THR interrupt
323                          * is fired when TX FIFO is below the trigger level,
324                          * disable THR interrupts and toggle the RS-485 GPIO
325                          * data direction pin if needed.
326                          */
327                         up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
328                         serial_out(up, UART_OMAP_SCR, up->scr);
329                         res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
330                                 1 : 0;
331                         if (gpio_get_value(up->rts_gpio) != res) {
332                                 if (port->rs485.delay_rts_after_send > 0)
333                                         mdelay(
334                                         port->rs485.delay_rts_after_send);
335                                 gpio_set_value(up->rts_gpio, res);
336                         }
337                 } else {
338                         /* We're asked to stop, but there's still stuff in the
339                          * UART FIFO, so make sure the THR interrupt is fired
340                          * when both TX FIFO and TX shift register are empty.
341                          * The next THR interrupt (if no transmission is started
342                          * in the meantime) will indicate the end of a
343                          * transmission. Therefore we _don't_ disable THR
344                          * interrupts in this situation.
345                          */
346                         up->scr |= OMAP_UART_SCR_TX_EMPTY;
347                         serial_out(up, UART_OMAP_SCR, up->scr);
348                         return;
349                 }
350         }
351 
352         if (up->ier & UART_IER_THRI) {
353                 up->ier &= ~UART_IER_THRI;
354                 serial_out(up, UART_IER, up->ier);
355         }
356 
357         if ((port->rs485.flags & SER_RS485_ENABLED) &&
358             !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
359                 /*
360                  * Empty the RX FIFO, we are not interested in anything
361                  * received during the half-duplex transmission.
362                  */
363                 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
364                 /* Re-enable RX interrupts */
365                 up->ier |= UART_IER_RLSI | UART_IER_RDI;
366                 up->port.read_status_mask |= UART_LSR_DR;
367                 serial_out(up, UART_IER, up->ier);
368         }
369 
370         pm_runtime_mark_last_busy(up->dev);
371         pm_runtime_put_autosuspend(up->dev);
372 }
373 
374 static void serial_omap_stop_rx(struct uart_port *port)
375 {
376         struct uart_omap_port *up = to_uart_omap_port(port);
377 
378         pm_runtime_get_sync(up->dev);
379         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
380         up->port.read_status_mask &= ~UART_LSR_DR;
381         serial_out(up, UART_IER, up->ier);
382         pm_runtime_mark_last_busy(up->dev);
383         pm_runtime_put_autosuspend(up->dev);
384 }
385 
386 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
387 {
388         struct circ_buf *xmit = &up->port.state->xmit;
389         int count;
390 
391         if (up->port.x_char) {
392                 serial_out(up, UART_TX, up->port.x_char);
393                 up->port.icount.tx++;
394                 up->port.x_char = 0;
395                 return;
396         }
397         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
398                 serial_omap_stop_tx(&up->port);
399                 return;
400         }
401         count = up->port.fifosize / 4;
402         do {
403                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
404                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
405                 up->port.icount.tx++;
406                 if (uart_circ_empty(xmit))
407                         break;
408         } while (--count > 0);
409 
410         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
411                 uart_write_wakeup(&up->port);
412 
413         if (uart_circ_empty(xmit))
414                 serial_omap_stop_tx(&up->port);
415 }
416 
417 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
418 {
419         if (!(up->ier & UART_IER_THRI)) {
420                 up->ier |= UART_IER_THRI;
421                 serial_out(up, UART_IER, up->ier);
422         }
423 }
424 
425 static void serial_omap_start_tx(struct uart_port *port)
426 {
427         struct uart_omap_port *up = to_uart_omap_port(port);
428         int res;
429 
430         pm_runtime_get_sync(up->dev);
431 
432         /* Handle RS-485 */
433         if (port->rs485.flags & SER_RS485_ENABLED) {
434                 /* Fire THR interrupts when FIFO is below trigger level */
435                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
436                 serial_out(up, UART_OMAP_SCR, up->scr);
437 
438                 /* if rts not already enabled */
439                 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
440                 if (gpio_get_value(up->rts_gpio) != res) {
441                         gpio_set_value(up->rts_gpio, res);
442                         if (port->rs485.delay_rts_before_send > 0)
443                                 mdelay(port->rs485.delay_rts_before_send);
444                 }
445         }
446 
447         if ((port->rs485.flags & SER_RS485_ENABLED) &&
448             !(port->rs485.flags & SER_RS485_RX_DURING_TX))
449                 serial_omap_stop_rx(port);
450 
451         serial_omap_enable_ier_thri(up);
452         pm_runtime_mark_last_busy(up->dev);
453         pm_runtime_put_autosuspend(up->dev);
454 }
455 
456 static void serial_omap_throttle(struct uart_port *port)
457 {
458         struct uart_omap_port *up = to_uart_omap_port(port);
459         unsigned long flags;
460 
461         pm_runtime_get_sync(up->dev);
462         spin_lock_irqsave(&up->port.lock, flags);
463         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
464         serial_out(up, UART_IER, up->ier);
465         spin_unlock_irqrestore(&up->port.lock, flags);
466         pm_runtime_mark_last_busy(up->dev);
467         pm_runtime_put_autosuspend(up->dev);
468 }
469 
470 static void serial_omap_unthrottle(struct uart_port *port)
471 {
472         struct uart_omap_port *up = to_uart_omap_port(port);
473         unsigned long flags;
474 
475         pm_runtime_get_sync(up->dev);
476         spin_lock_irqsave(&up->port.lock, flags);
477         up->ier |= UART_IER_RLSI | UART_IER_RDI;
478         serial_out(up, UART_IER, up->ier);
479         spin_unlock_irqrestore(&up->port.lock, flags);
480         pm_runtime_mark_last_busy(up->dev);
481         pm_runtime_put_autosuspend(up->dev);
482 }
483 
484 static unsigned int check_modem_status(struct uart_omap_port *up)
485 {
486         unsigned int status;
487 
488         status = serial_in(up, UART_MSR);
489         status |= up->msr_saved_flags;
490         up->msr_saved_flags = 0;
491         if ((status & UART_MSR_ANY_DELTA) == 0)
492                 return status;
493 
494         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
495             up->port.state != NULL) {
496                 if (status & UART_MSR_TERI)
497                         up->port.icount.rng++;
498                 if (status & UART_MSR_DDSR)
499                         up->port.icount.dsr++;
500                 if (status & UART_MSR_DDCD)
501                         uart_handle_dcd_change
502                                 (&up->port, status & UART_MSR_DCD);
503                 if (status & UART_MSR_DCTS)
504                         uart_handle_cts_change
505                                 (&up->port, status & UART_MSR_CTS);
506                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
507         }
508 
509         return status;
510 }
511 
512 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
513 {
514         unsigned int flag;
515         unsigned char ch = 0;
516 
517         if (likely(lsr & UART_LSR_DR))
518                 ch = serial_in(up, UART_RX);
519 
520         up->port.icount.rx++;
521         flag = TTY_NORMAL;
522 
523         if (lsr & UART_LSR_BI) {
524                 flag = TTY_BREAK;
525                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
526                 up->port.icount.brk++;
527                 /*
528                  * We do the SysRQ and SAK checking
529                  * here because otherwise the break
530                  * may get masked by ignore_status_mask
531                  * or read_status_mask.
532                  */
533                 if (uart_handle_break(&up->port))
534                         return;
535 
536         }
537 
538         if (lsr & UART_LSR_PE) {
539                 flag = TTY_PARITY;
540                 up->port.icount.parity++;
541         }
542 
543         if (lsr & UART_LSR_FE) {
544                 flag = TTY_FRAME;
545                 up->port.icount.frame++;
546         }
547 
548         if (lsr & UART_LSR_OE)
549                 up->port.icount.overrun++;
550 
551 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
552         if (up->port.line == up->port.cons->index) {
553                 /* Recover the break flag from console xmit */
554                 lsr |= up->lsr_break_flag;
555         }
556 #endif
557         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
558 }
559 
560 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
561 {
562         unsigned char ch = 0;
563         unsigned int flag;
564 
565         if (!(lsr & UART_LSR_DR))
566                 return;
567 
568         ch = serial_in(up, UART_RX);
569         flag = TTY_NORMAL;
570         up->port.icount.rx++;
571 
572         if (uart_handle_sysrq_char(&up->port, ch))
573                 return;
574 
575         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
576 }
577 
578 /**
579  * serial_omap_irq() - This handles the interrupt from one port
580  * @irq: uart port irq number
581  * @dev_id: uart port info
582  */
583 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
584 {
585         struct uart_omap_port *up = dev_id;
586         unsigned int iir, lsr;
587         unsigned int type;
588         irqreturn_t ret = IRQ_NONE;
589         int max_count = 256;
590 
591         spin_lock(&up->port.lock);
592         pm_runtime_get_sync(up->dev);
593 
594         do {
595                 iir = serial_in(up, UART_IIR);
596                 if (iir & UART_IIR_NO_INT)
597                         break;
598 
599                 ret = IRQ_HANDLED;
600                 lsr = serial_in(up, UART_LSR);
601 
602                 /* extract IRQ type from IIR register */
603                 type = iir & 0x3e;
604 
605                 switch (type) {
606                 case UART_IIR_MSI:
607                         check_modem_status(up);
608                         break;
609                 case UART_IIR_THRI:
610                         transmit_chars(up, lsr);
611                         break;
612                 case UART_IIR_RX_TIMEOUT:
613                         /* FALLTHROUGH */
614                 case UART_IIR_RDI:
615                         serial_omap_rdi(up, lsr);
616                         break;
617                 case UART_IIR_RLSI:
618                         serial_omap_rlsi(up, lsr);
619                         break;
620                 case UART_IIR_CTS_RTS_DSR:
621                         /* simply try again */
622                         break;
623                 case UART_IIR_XOFF:
624                         /* FALLTHROUGH */
625                 default:
626                         break;
627                 }
628         } while (!(iir & UART_IIR_NO_INT) && max_count--);
629 
630         spin_unlock(&up->port.lock);
631 
632         tty_flip_buffer_push(&up->port.state->port);
633 
634         pm_runtime_mark_last_busy(up->dev);
635         pm_runtime_put_autosuspend(up->dev);
636         up->port_activity = jiffies;
637 
638         return ret;
639 }
640 
641 static unsigned int serial_omap_tx_empty(struct uart_port *port)
642 {
643         struct uart_omap_port *up = to_uart_omap_port(port);
644         unsigned long flags = 0;
645         unsigned int ret = 0;
646 
647         pm_runtime_get_sync(up->dev);
648         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
649         spin_lock_irqsave(&up->port.lock, flags);
650         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
651         spin_unlock_irqrestore(&up->port.lock, flags);
652         pm_runtime_mark_last_busy(up->dev);
653         pm_runtime_put_autosuspend(up->dev);
654         return ret;
655 }
656 
657 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
658 {
659         struct uart_omap_port *up = to_uart_omap_port(port);
660         unsigned int status;
661         unsigned int ret = 0;
662 
663         pm_runtime_get_sync(up->dev);
664         status = check_modem_status(up);
665         pm_runtime_mark_last_busy(up->dev);
666         pm_runtime_put_autosuspend(up->dev);
667 
668         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
669 
670         if (status & UART_MSR_DCD)
671                 ret |= TIOCM_CAR;
672         if (status & UART_MSR_RI)
673                 ret |= TIOCM_RNG;
674         if (status & UART_MSR_DSR)
675                 ret |= TIOCM_DSR;
676         if (status & UART_MSR_CTS)
677                 ret |= TIOCM_CTS;
678         return ret;
679 }
680 
681 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
682 {
683         struct uart_omap_port *up = to_uart_omap_port(port);
684         unsigned char mcr = 0, old_mcr, lcr;
685 
686         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
687         if (mctrl & TIOCM_RTS)
688                 mcr |= UART_MCR_RTS;
689         if (mctrl & TIOCM_DTR)
690                 mcr |= UART_MCR_DTR;
691         if (mctrl & TIOCM_OUT1)
692                 mcr |= UART_MCR_OUT1;
693         if (mctrl & TIOCM_OUT2)
694                 mcr |= UART_MCR_OUT2;
695         if (mctrl & TIOCM_LOOP)
696                 mcr |= UART_MCR_LOOP;
697 
698         pm_runtime_get_sync(up->dev);
699         old_mcr = serial_in(up, UART_MCR);
700         old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
701                      UART_MCR_DTR | UART_MCR_RTS);
702         up->mcr = old_mcr | mcr;
703         serial_out(up, UART_MCR, up->mcr);
704 
705         /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
706         lcr = serial_in(up, UART_LCR);
707         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
708         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
709                 up->efr |= UART_EFR_RTS;
710         else
711                 up->efr &= UART_EFR_RTS;
712         serial_out(up, UART_EFR, up->efr);
713         serial_out(up, UART_LCR, lcr);
714 
715         pm_runtime_mark_last_busy(up->dev);
716         pm_runtime_put_autosuspend(up->dev);
717 }
718 
719 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
720 {
721         struct uart_omap_port *up = to_uart_omap_port(port);
722         unsigned long flags = 0;
723 
724         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
725         pm_runtime_get_sync(up->dev);
726         spin_lock_irqsave(&up->port.lock, flags);
727         if (break_state == -1)
728                 up->lcr |= UART_LCR_SBC;
729         else
730                 up->lcr &= ~UART_LCR_SBC;
731         serial_out(up, UART_LCR, up->lcr);
732         spin_unlock_irqrestore(&up->port.lock, flags);
733         pm_runtime_mark_last_busy(up->dev);
734         pm_runtime_put_autosuspend(up->dev);
735 }
736 
737 static int serial_omap_startup(struct uart_port *port)
738 {
739         struct uart_omap_port *up = to_uart_omap_port(port);
740         unsigned long flags = 0;
741         int retval;
742 
743         /*
744          * Allocate the IRQ
745          */
746         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
747                                 up->name, up);
748         if (retval)
749                 return retval;
750 
751         /* Optional wake-up IRQ */
752         if (up->wakeirq) {
753                 retval = request_irq(up->wakeirq, serial_omap_irq,
754                                      up->port.irqflags, up->name, up);
755                 if (retval) {
756                         free_irq(up->port.irq, up);
757                         return retval;
758                 }
759                 disable_irq(up->wakeirq);
760         }
761 
762         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
763 
764         pm_runtime_get_sync(up->dev);
765         /*
766          * Clear the FIFO buffers and disable them.
767          * (they will be reenabled in set_termios())
768          */
769         serial_omap_clear_fifos(up);
770 
771         /*
772          * Clear the interrupt registers.
773          */
774         (void) serial_in(up, UART_LSR);
775         if (serial_in(up, UART_LSR) & UART_LSR_DR)
776                 (void) serial_in(up, UART_RX);
777         (void) serial_in(up, UART_IIR);
778         (void) serial_in(up, UART_MSR);
779 
780         /*
781          * Now, initialize the UART
782          */
783         serial_out(up, UART_LCR, UART_LCR_WLEN8);
784         spin_lock_irqsave(&up->port.lock, flags);
785         /*
786          * Most PC uarts need OUT2 raised to enable interrupts.
787          */
788         up->port.mctrl |= TIOCM_OUT2;
789         serial_omap_set_mctrl(&up->port, up->port.mctrl);
790         spin_unlock_irqrestore(&up->port.lock, flags);
791 
792         up->msr_saved_flags = 0;
793         /*
794          * Finally, enable interrupts. Note: Modem status interrupts
795          * are set via set_termios(), which will be occurring imminently
796          * anyway, so we don't enable them here.
797          */
798         up->ier = UART_IER_RLSI | UART_IER_RDI;
799         serial_out(up, UART_IER, up->ier);
800 
801         /* Enable module level wake up */
802         up->wer = OMAP_UART_WER_MOD_WKUP;
803         if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
804                 up->wer |= OMAP_UART_TX_WAKEUP_EN;
805 
806         serial_out(up, UART_OMAP_WER, up->wer);
807 
808         pm_runtime_mark_last_busy(up->dev);
809         pm_runtime_put_autosuspend(up->dev);
810         up->port_activity = jiffies;
811         return 0;
812 }
813 
814 static void serial_omap_shutdown(struct uart_port *port)
815 {
816         struct uart_omap_port *up = to_uart_omap_port(port);
817         unsigned long flags = 0;
818 
819         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
820 
821         pm_runtime_get_sync(up->dev);
822         /*
823          * Disable interrupts from this port
824          */
825         up->ier = 0;
826         serial_out(up, UART_IER, 0);
827 
828         spin_lock_irqsave(&up->port.lock, flags);
829         up->port.mctrl &= ~TIOCM_OUT2;
830         serial_omap_set_mctrl(&up->port, up->port.mctrl);
831         spin_unlock_irqrestore(&up->port.lock, flags);
832 
833         /*
834          * Disable break condition and FIFOs
835          */
836         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
837         serial_omap_clear_fifos(up);
838 
839         /*
840          * Read data port to reset things, and then free the irq
841          */
842         if (serial_in(up, UART_LSR) & UART_LSR_DR)
843                 (void) serial_in(up, UART_RX);
844 
845         pm_runtime_mark_last_busy(up->dev);
846         pm_runtime_put_autosuspend(up->dev);
847         free_irq(up->port.irq, up);
848         if (up->wakeirq)
849                 free_irq(up->wakeirq, up);
850 }
851 
852 static void serial_omap_uart_qos_work(struct work_struct *work)
853 {
854         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
855                                                 qos_work);
856 
857         pm_qos_update_request(&up->pm_qos_request, up->latency);
858 }
859 
860 static void
861 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
862                         struct ktermios *old)
863 {
864         struct uart_omap_port *up = to_uart_omap_port(port);
865         unsigned char cval = 0;
866         unsigned long flags = 0;
867         unsigned int baud, quot;
868 
869         switch (termios->c_cflag & CSIZE) {
870         case CS5:
871                 cval = UART_LCR_WLEN5;
872                 break;
873         case CS6:
874                 cval = UART_LCR_WLEN6;
875                 break;
876         case CS7:
877                 cval = UART_LCR_WLEN7;
878                 break;
879         default:
880         case CS8:
881                 cval = UART_LCR_WLEN8;
882                 break;
883         }
884 
885         if (termios->c_cflag & CSTOPB)
886                 cval |= UART_LCR_STOP;
887         if (termios->c_cflag & PARENB)
888                 cval |= UART_LCR_PARITY;
889         if (!(termios->c_cflag & PARODD))
890                 cval |= UART_LCR_EPAR;
891         if (termios->c_cflag & CMSPAR)
892                 cval |= UART_LCR_SPAR;
893 
894         /*
895          * Ask the core to calculate the divisor for us.
896          */
897 
898         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
899         quot = serial_omap_get_divisor(port, baud);
900 
901         /* calculate wakeup latency constraint */
902         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
903         up->latency = up->calc_latency;
904         schedule_work(&up->qos_work);
905 
906         up->dll = quot & 0xff;
907         up->dlh = quot >> 8;
908         up->mdr1 = UART_OMAP_MDR1_DISABLE;
909 
910         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
911                         UART_FCR_ENABLE_FIFO;
912 
913         /*
914          * Ok, we're now changing the port state. Do it with
915          * interrupts disabled.
916          */
917         pm_runtime_get_sync(up->dev);
918         spin_lock_irqsave(&up->port.lock, flags);
919 
920         /*
921          * Update the per-port timeout.
922          */
923         uart_update_timeout(port, termios->c_cflag, baud);
924 
925         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
926         if (termios->c_iflag & INPCK)
927                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
928         if (termios->c_iflag & (BRKINT | PARMRK))
929                 up->port.read_status_mask |= UART_LSR_BI;
930 
931         /*
932          * Characters to ignore
933          */
934         up->port.ignore_status_mask = 0;
935         if (termios->c_iflag & IGNPAR)
936                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
937         if (termios->c_iflag & IGNBRK) {
938                 up->port.ignore_status_mask |= UART_LSR_BI;
939                 /*
940                  * If we're ignoring parity and break indicators,
941                  * ignore overruns too (for real raw support).
942                  */
943                 if (termios->c_iflag & IGNPAR)
944                         up->port.ignore_status_mask |= UART_LSR_OE;
945         }
946 
947         /*
948          * ignore all characters if CREAD is not set
949          */
950         if ((termios->c_cflag & CREAD) == 0)
951                 up->port.ignore_status_mask |= UART_LSR_DR;
952 
953         /*
954          * Modem status interrupts
955          */
956         up->ier &= ~UART_IER_MSI;
957         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
958                 up->ier |= UART_IER_MSI;
959         serial_out(up, UART_IER, up->ier);
960         serial_out(up, UART_LCR, cval);         /* reset DLAB */
961         up->lcr = cval;
962         up->scr = 0;
963 
964         /* FIFOs and DMA Settings */
965 
966         /* FCR can be changed only when the
967          * baud clock is not running
968          * DLL_REG and DLH_REG set to 0.
969          */
970         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
971         serial_out(up, UART_DLL, 0);
972         serial_out(up, UART_DLM, 0);
973         serial_out(up, UART_LCR, 0);
974 
975         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
976 
977         up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
978         up->efr &= ~UART_EFR_SCD;
979         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
980 
981         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
982         up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
983         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
984         /* FIFO ENABLE, DMA MODE */
985 
986         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
987         /*
988          * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
989          * sets Enables the granularity of 1 for TRIGGER RX
990          * level. Along with setting RX FIFO trigger level
991          * to 1 (as noted below, 16 characters) and TLR[3:0]
992          * to zero this will result RX FIFO threshold level
993          * to 1 character, instead of 16 as noted in comment
994          * below.
995          */
996 
997         /* Set receive FIFO threshold to 16 characters and
998          * transmit FIFO threshold to 32 spaces
999          */
1000         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
1001         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
1002         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
1003                 UART_FCR_ENABLE_FIFO;
1004 
1005         serial_out(up, UART_FCR, up->fcr);
1006         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1007 
1008         serial_out(up, UART_OMAP_SCR, up->scr);
1009 
1010         /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
1011         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1012         serial_out(up, UART_MCR, up->mcr);
1013         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1014         serial_out(up, UART_EFR, up->efr);
1015         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1016 
1017         /* Protocol, Baud Rate, and Interrupt Settings */
1018 
1019         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1020                 serial_omap_mdr1_errataset(up, up->mdr1);
1021         else
1022                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1023 
1024         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1025         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1026 
1027         serial_out(up, UART_LCR, 0);
1028         serial_out(up, UART_IER, 0);
1029         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1030 
1031         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
1032         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
1033 
1034         serial_out(up, UART_LCR, 0);
1035         serial_out(up, UART_IER, up->ier);
1036         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1037 
1038         serial_out(up, UART_EFR, up->efr);
1039         serial_out(up, UART_LCR, cval);
1040 
1041         if (!serial_omap_baud_is_mode16(port, baud))
1042                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1043         else
1044                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1045 
1046         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1047                 serial_omap_mdr1_errataset(up, up->mdr1);
1048         else
1049                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1050 
1051         /* Configure flow control */
1052         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1053 
1054         /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1055         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1056         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1057 
1058         /* Enable access to TCR/TLR */
1059         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1060         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1061         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1062 
1063         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1064 
1065         up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
1066 
1067         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1068                 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
1069                 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1070                 up->efr |= UART_EFR_CTS;
1071         } else {
1072                 /* Disable AUTORTS and AUTOCTS */
1073                 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1074         }
1075 
1076         if (up->port.flags & UPF_SOFT_FLOW) {
1077                 /* clear SW control mode bits */
1078                 up->efr &= OMAP_UART_SW_CLR;
1079 
1080                 /*
1081                  * IXON Flag:
1082                  * Enable XON/XOFF flow control on input.
1083                  * Receiver compares XON1, XOFF1.
1084                  */
1085                 if (termios->c_iflag & IXON)
1086                         up->efr |= OMAP_UART_SW_RX;
1087 
1088                 /*
1089                  * IXOFF Flag:
1090                  * Enable XON/XOFF flow control on output.
1091                  * Transmit XON1, XOFF1
1092                  */
1093                 if (termios->c_iflag & IXOFF) {
1094                         up->port.status |= UPSTAT_AUTOXOFF;
1095                         up->efr |= OMAP_UART_SW_TX;
1096                 }
1097 
1098                 /*
1099                  * IXANY Flag:
1100                  * Enable any character to restart output.
1101                  * Operation resumes after receiving any
1102                  * character after recognition of the XOFF character
1103                  */
1104                 if (termios->c_iflag & IXANY)
1105                         up->mcr |= UART_MCR_XONANY;
1106                 else
1107                         up->mcr &= ~UART_MCR_XONANY;
1108         }
1109         serial_out(up, UART_MCR, up->mcr);
1110         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1111         serial_out(up, UART_EFR, up->efr);
1112         serial_out(up, UART_LCR, up->lcr);
1113 
1114         serial_omap_set_mctrl(&up->port, up->port.mctrl);
1115 
1116         spin_unlock_irqrestore(&up->port.lock, flags);
1117         pm_runtime_mark_last_busy(up->dev);
1118         pm_runtime_put_autosuspend(up->dev);
1119         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1120 }
1121 
1122 static void
1123 serial_omap_pm(struct uart_port *port, unsigned int state,
1124                unsigned int oldstate)
1125 {
1126         struct uart_omap_port *up = to_uart_omap_port(port);
1127         unsigned char efr;
1128 
1129         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1130 
1131         pm_runtime_get_sync(up->dev);
1132         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1133         efr = serial_in(up, UART_EFR);
1134         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1135         serial_out(up, UART_LCR, 0);
1136 
1137         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1138         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1139         serial_out(up, UART_EFR, efr);
1140         serial_out(up, UART_LCR, 0);
1141 
1142         if (!device_may_wakeup(up->dev)) {
1143                 if (!state)
1144                         pm_runtime_forbid(up->dev);
1145                 else
1146                         pm_runtime_allow(up->dev);
1147         }
1148 
1149         pm_runtime_mark_last_busy(up->dev);
1150         pm_runtime_put_autosuspend(up->dev);
1151 }
1152 
1153 static void serial_omap_release_port(struct uart_port *port)
1154 {
1155         dev_dbg(port->dev, "serial_omap_release_port+\n");
1156 }
1157 
1158 static int serial_omap_request_port(struct uart_port *port)
1159 {
1160         dev_dbg(port->dev, "serial_omap_request_port+\n");
1161         return 0;
1162 }
1163 
1164 static void serial_omap_config_port(struct uart_port *port, int flags)
1165 {
1166         struct uart_omap_port *up = to_uart_omap_port(port);
1167 
1168         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1169                                                         up->port.line);
1170         up->port.type = PORT_OMAP;
1171         up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1172 }
1173 
1174 static int
1175 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1176 {
1177         /* we don't want the core code to modify any port params */
1178         dev_dbg(port->dev, "serial_omap_verify_port+\n");
1179         return -EINVAL;
1180 }
1181 
1182 static const char *
1183 serial_omap_type(struct uart_port *port)
1184 {
1185         struct uart_omap_port *up = to_uart_omap_port(port);
1186 
1187         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1188         return up->name;
1189 }
1190 
1191 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1192 
1193 static inline void wait_for_xmitr(struct uart_omap_port *up)
1194 {
1195         unsigned int status, tmout = 10000;
1196 
1197         /* Wait up to 10ms for the character(s) to be sent. */
1198         do {
1199                 status = serial_in(up, UART_LSR);
1200 
1201                 if (status & UART_LSR_BI)
1202                         up->lsr_break_flag = UART_LSR_BI;
1203 
1204                 if (--tmout == 0)
1205                         break;
1206                 udelay(1);
1207         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1208 
1209         /* Wait up to 1s for flow control if necessary */
1210         if (up->port.flags & UPF_CONS_FLOW) {
1211                 tmout = 1000000;
1212                 for (tmout = 1000000; tmout; tmout--) {
1213                         unsigned int msr = serial_in(up, UART_MSR);
1214 
1215                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1216                         if (msr & UART_MSR_CTS)
1217                                 break;
1218 
1219                         udelay(1);
1220                 }
1221         }
1222 }
1223 
1224 #ifdef CONFIG_CONSOLE_POLL
1225 
1226 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1227 {
1228         struct uart_omap_port *up = to_uart_omap_port(port);
1229 
1230         pm_runtime_get_sync(up->dev);
1231         wait_for_xmitr(up);
1232         serial_out(up, UART_TX, ch);
1233         pm_runtime_mark_last_busy(up->dev);
1234         pm_runtime_put_autosuspend(up->dev);
1235 }
1236 
1237 static int serial_omap_poll_get_char(struct uart_port *port)
1238 {
1239         struct uart_omap_port *up = to_uart_omap_port(port);
1240         unsigned int status;
1241 
1242         pm_runtime_get_sync(up->dev);
1243         status = serial_in(up, UART_LSR);
1244         if (!(status & UART_LSR_DR)) {
1245                 status = NO_POLL_CHAR;
1246                 goto out;
1247         }
1248 
1249         status = serial_in(up, UART_RX);
1250 
1251 out:
1252         pm_runtime_mark_last_busy(up->dev);
1253         pm_runtime_put_autosuspend(up->dev);
1254 
1255         return status;
1256 }
1257 
1258 #endif /* CONFIG_CONSOLE_POLL */
1259 
1260 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1261 
1262 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1263 
1264 static struct uart_driver serial_omap_reg;
1265 
1266 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1267 {
1268         struct uart_omap_port *up = to_uart_omap_port(port);
1269 
1270         wait_for_xmitr(up);
1271         serial_out(up, UART_TX, ch);
1272 }
1273 
1274 static void
1275 serial_omap_console_write(struct console *co, const char *s,
1276                 unsigned int count)
1277 {
1278         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1279         unsigned long flags;
1280         unsigned int ier;
1281         int locked = 1;
1282 
1283         pm_runtime_get_sync(up->dev);
1284 
1285         local_irq_save(flags);
1286         if (up->port.sysrq)
1287                 locked = 0;
1288         else if (oops_in_progress)
1289                 locked = spin_trylock(&up->port.lock);
1290         else
1291                 spin_lock(&up->port.lock);
1292 
1293         /*
1294          * First save the IER then disable the interrupts
1295          */
1296         ier = serial_in(up, UART_IER);
1297         serial_out(up, UART_IER, 0);
1298 
1299         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1300 
1301         /*
1302          * Finally, wait for transmitter to become empty
1303          * and restore the IER
1304          */
1305         wait_for_xmitr(up);
1306         serial_out(up, UART_IER, ier);
1307         /*
1308          * The receive handling will happen properly because the
1309          * receive ready bit will still be set; it is not cleared
1310          * on read.  However, modem control will not, we must
1311          * call it if we have saved something in the saved flags
1312          * while processing with interrupts off.
1313          */
1314         if (up->msr_saved_flags)
1315                 check_modem_status(up);
1316 
1317         pm_runtime_mark_last_busy(up->dev);
1318         pm_runtime_put_autosuspend(up->dev);
1319         if (locked)
1320                 spin_unlock(&up->port.lock);
1321         local_irq_restore(flags);
1322 }
1323 
1324 static int __init
1325 serial_omap_console_setup(struct console *co, char *options)
1326 {
1327         struct uart_omap_port *up;
1328         int baud = 115200;
1329         int bits = 8;
1330         int parity = 'n';
1331         int flow = 'n';
1332 
1333         if (serial_omap_console_ports[co->index] == NULL)
1334                 return -ENODEV;
1335         up = serial_omap_console_ports[co->index];
1336 
1337         if (options)
1338                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1339 
1340         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1341 }
1342 
1343 static struct console serial_omap_console = {
1344         .name           = OMAP_SERIAL_NAME,
1345         .write          = serial_omap_console_write,
1346         .device         = uart_console_device,
1347         .setup          = serial_omap_console_setup,
1348         .flags          = CON_PRINTBUFFER,
1349         .index          = -1,
1350         .data           = &serial_omap_reg,
1351 };
1352 
1353 static void serial_omap_add_console_port(struct uart_omap_port *up)
1354 {
1355         serial_omap_console_ports[up->port.line] = up;
1356 }
1357 
1358 #define OMAP_CONSOLE    (&serial_omap_console)
1359 
1360 #else
1361 
1362 #define OMAP_CONSOLE    NULL
1363 
1364 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1365 {}
1366 
1367 #endif
1368 
1369 /* Enable or disable the rs485 support */
1370 static int
1371 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
1372 {
1373         struct uart_omap_port *up = to_uart_omap_port(port);
1374         unsigned int mode;
1375         int val;
1376 
1377         pm_runtime_get_sync(up->dev);
1378 
1379         /* Disable interrupts from this port */
1380         mode = up->ier;
1381         up->ier = 0;
1382         serial_out(up, UART_IER, 0);
1383 
1384         /* store new config */
1385         port->rs485 = *rs485conf;
1386 
1387         /*
1388          * Just as a precaution, only allow rs485
1389          * to be enabled if the gpio pin is valid
1390          */
1391         if (gpio_is_valid(up->rts_gpio)) {
1392                 /* enable / disable rts */
1393                 val = (port->rs485.flags & SER_RS485_ENABLED) ?
1394                         SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1395                 val = (port->rs485.flags & val) ? 1 : 0;
1396                 gpio_set_value(up->rts_gpio, val);
1397         } else
1398                 port->rs485.flags &= ~SER_RS485_ENABLED;
1399 
1400         /* Enable interrupts */
1401         up->ier = mode;
1402         serial_out(up, UART_IER, up->ier);
1403 
1404         /* If RS-485 is disabled, make sure the THR interrupt is fired when
1405          * TX FIFO is below the trigger level.
1406          */
1407         if (!(port->rs485.flags & SER_RS485_ENABLED) &&
1408             (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1409                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1410                 serial_out(up, UART_OMAP_SCR, up->scr);
1411         }
1412 
1413         pm_runtime_mark_last_busy(up->dev);
1414         pm_runtime_put_autosuspend(up->dev);
1415 
1416         return 0;
1417 }
1418 
1419 static struct uart_ops serial_omap_pops = {
1420         .tx_empty       = serial_omap_tx_empty,
1421         .set_mctrl      = serial_omap_set_mctrl,
1422         .get_mctrl      = serial_omap_get_mctrl,
1423         .stop_tx        = serial_omap_stop_tx,
1424         .start_tx       = serial_omap_start_tx,
1425         .throttle       = serial_omap_throttle,
1426         .unthrottle     = serial_omap_unthrottle,
1427         .stop_rx        = serial_omap_stop_rx,
1428         .enable_ms      = serial_omap_enable_ms,
1429         .break_ctl      = serial_omap_break_ctl,
1430         .startup        = serial_omap_startup,
1431         .shutdown       = serial_omap_shutdown,
1432         .set_termios    = serial_omap_set_termios,
1433         .pm             = serial_omap_pm,
1434         .type           = serial_omap_type,
1435         .release_port   = serial_omap_release_port,
1436         .request_port   = serial_omap_request_port,
1437         .config_port    = serial_omap_config_port,
1438         .verify_port    = serial_omap_verify_port,
1439 #ifdef CONFIG_CONSOLE_POLL
1440         .poll_put_char  = serial_omap_poll_put_char,
1441         .poll_get_char  = serial_omap_poll_get_char,
1442 #endif
1443 };
1444 
1445 static struct uart_driver serial_omap_reg = {
1446         .owner          = THIS_MODULE,
1447         .driver_name    = "OMAP-SERIAL",
1448         .dev_name       = OMAP_SERIAL_NAME,
1449         .nr             = OMAP_MAX_HSUART_PORTS,
1450         .cons           = OMAP_CONSOLE,
1451 };
1452 
1453 #ifdef CONFIG_PM_SLEEP
1454 static int serial_omap_prepare(struct device *dev)
1455 {
1456         struct uart_omap_port *up = dev_get_drvdata(dev);
1457 
1458         up->is_suspending = true;
1459 
1460         return 0;
1461 }
1462 
1463 static void serial_omap_complete(struct device *dev)
1464 {
1465         struct uart_omap_port *up = dev_get_drvdata(dev);
1466 
1467         up->is_suspending = false;
1468 }
1469 
1470 static int serial_omap_suspend(struct device *dev)
1471 {
1472         struct uart_omap_port *up = dev_get_drvdata(dev);
1473 
1474         uart_suspend_port(&serial_omap_reg, &up->port);
1475         flush_work(&up->qos_work);
1476 
1477         if (device_may_wakeup(dev))
1478                 serial_omap_enable_wakeup(up, true);
1479         else
1480                 serial_omap_enable_wakeup(up, false);
1481 
1482         return 0;
1483 }
1484 
1485 static int serial_omap_resume(struct device *dev)
1486 {
1487         struct uart_omap_port *up = dev_get_drvdata(dev);
1488 
1489         if (device_may_wakeup(dev))
1490                 serial_omap_enable_wakeup(up, false);
1491 
1492         uart_resume_port(&serial_omap_reg, &up->port);
1493 
1494         return 0;
1495 }
1496 #else
1497 #define serial_omap_prepare NULL
1498 #define serial_omap_complete NULL
1499 #endif /* CONFIG_PM_SLEEP */
1500 
1501 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1502 {
1503         u32 mvr, scheme;
1504         u16 revision, major, minor;
1505 
1506         mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1507 
1508         /* Check revision register scheme */
1509         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1510 
1511         switch (scheme) {
1512         case 0: /* Legacy Scheme: OMAP2/3 */
1513                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1514                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1515                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1516                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1517                 break;
1518         case 1:
1519                 /* New Scheme: OMAP4+ */
1520                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1521                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1522                                         OMAP_UART_MVR_MAJ_SHIFT;
1523                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1524                 break;
1525         default:
1526                 dev_warn(up->dev,
1527                         "Unknown %s revision, defaulting to highest\n",
1528                         up->name);
1529                 /* highest possible revision */
1530                 major = 0xff;
1531                 minor = 0xff;
1532         }
1533 
1534         /* normalize revision for the driver */
1535         revision = UART_BUILD_REVISION(major, minor);
1536 
1537         switch (revision) {
1538         case OMAP_UART_REV_46:
1539                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1540                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1541                 break;
1542         case OMAP_UART_REV_52:
1543                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1544                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1545                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1546                 break;
1547         case OMAP_UART_REV_63:
1548                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1549                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1550                 break;
1551         default:
1552                 break;
1553         }
1554 }
1555 
1556 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1557 {
1558         struct omap_uart_port_info *omap_up_info;
1559 
1560         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1561         if (!omap_up_info)
1562                 return NULL; /* out of memory */
1563 
1564         of_property_read_u32(dev->of_node, "clock-frequency",
1565                                          &omap_up_info->uartclk);
1566         return omap_up_info;
1567 }
1568 
1569 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1570                                    struct device_node *np)
1571 {
1572         struct serial_rs485 *rs485conf = &up->port.rs485;
1573         u32 rs485_delay[2];
1574         enum of_gpio_flags flags;
1575         int ret;
1576 
1577         rs485conf->flags = 0;
1578         up->rts_gpio = -EINVAL;
1579 
1580         if (!np)
1581                 return 0;
1582 
1583         if (of_property_read_bool(np, "rs485-rts-active-high"))
1584                 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1585         else
1586                 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1587 
1588         /* check for tx enable gpio */
1589         up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags);
1590         if (gpio_is_valid(up->rts_gpio)) {
1591                 ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial");
1592                 if (ret < 0)
1593                         return ret;
1594                 ret = gpio_direction_output(up->rts_gpio,
1595                                             flags & SER_RS485_RTS_AFTER_SEND);
1596                 if (ret < 0)
1597                         return ret;
1598         } else if (up->rts_gpio == -EPROBE_DEFER) {
1599                 return -EPROBE_DEFER;
1600         } else {
1601                 up->rts_gpio = -EINVAL;
1602         }
1603 
1604         if (of_property_read_u32_array(np, "rs485-rts-delay",
1605                                     rs485_delay, 2) == 0) {
1606                 rs485conf->delay_rts_before_send = rs485_delay[0];
1607                 rs485conf->delay_rts_after_send = rs485_delay[1];
1608         }
1609 
1610         if (of_property_read_bool(np, "rs485-rx-during-tx"))
1611                 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1612 
1613         if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
1614                 rs485conf->flags |= SER_RS485_ENABLED;
1615 
1616         return 0;
1617 }
1618 
1619 static int serial_omap_probe(struct platform_device *pdev)
1620 {
1621         struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1622         struct uart_omap_port *up;
1623         struct resource *mem;
1624         void __iomem *base;
1625         int uartirq = 0;
1626         int wakeirq = 0;
1627         int ret;
1628 
1629         /* The optional wakeirq may be specified in the board dts file */
1630         if (pdev->dev.of_node) {
1631                 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1632                 if (!uartirq)
1633                         return -EPROBE_DEFER;
1634                 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1635                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1636                 pdev->dev.platform_data = omap_up_info;
1637         } else {
1638                 uartirq = platform_get_irq(pdev, 0);
1639                 if (uartirq < 0)
1640                         return -EPROBE_DEFER;
1641         }
1642 
1643         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1644         if (!up)
1645                 return -ENOMEM;
1646 
1647         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1648         base = devm_ioremap_resource(&pdev->dev, mem);
1649         if (IS_ERR(base))
1650                 return PTR_ERR(base);
1651 
1652         up->dev = &pdev->dev;
1653         up->port.dev = &pdev->dev;
1654         up->port.type = PORT_OMAP;
1655         up->port.iotype = UPIO_MEM;
1656         up->port.irq = uartirq;
1657         up->wakeirq = wakeirq;
1658         if (!up->wakeirq)
1659                 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1660                          up->port.line);
1661 
1662         up->port.regshift = 2;
1663         up->port.fifosize = 64;
1664         up->port.ops = &serial_omap_pops;
1665 
1666         if (pdev->dev.of_node)
1667                 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1668         else
1669                 ret = pdev->id;
1670 
1671         if (ret < 0) {
1672                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1673                         ret);
1674                 goto err_port_line;
1675         }
1676         up->port.line = ret;
1677 
1678         if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1679                 dev_err(&pdev->dev, "uart ID %d >  MAX %d.\n", up->port.line,
1680                         OMAP_MAX_HSUART_PORTS);
1681                 ret = -ENXIO;
1682                 goto err_port_line;
1683         }
1684 
1685         ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1686         if (ret < 0)
1687                 goto err_rs485;
1688 
1689         sprintf(up->name, "OMAP UART%d", up->port.line);
1690         up->port.mapbase = mem->start;
1691         up->port.membase = base;
1692         up->port.flags = omap_up_info->flags;
1693         up->port.uartclk = omap_up_info->uartclk;
1694         up->port.rs485_config = serial_omap_config_rs485;
1695         if (!up->port.uartclk) {
1696                 up->port.uartclk = DEFAULT_CLK_SPEED;
1697                 dev_warn(&pdev->dev,
1698                          "No clock speed specified: using default: %d\n",
1699                          DEFAULT_CLK_SPEED);
1700         }
1701 
1702         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1703         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1704         pm_qos_add_request(&up->pm_qos_request,
1705                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1706         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1707 
1708         platform_set_drvdata(pdev, up);
1709         if (omap_up_info->autosuspend_timeout == 0)
1710                 omap_up_info->autosuspend_timeout = -1;
1711 
1712         device_init_wakeup(up->dev, true);
1713         pm_runtime_use_autosuspend(&pdev->dev);
1714         pm_runtime_set_autosuspend_delay(&pdev->dev,
1715                         omap_up_info->autosuspend_timeout);
1716 
1717         pm_runtime_irq_safe(&pdev->dev);
1718         pm_runtime_enable(&pdev->dev);
1719 
1720         pm_runtime_get_sync(&pdev->dev);
1721 
1722         omap_serial_fill_features_erratas(up);
1723 
1724         ui[up->port.line] = up;
1725         serial_omap_add_console_port(up);
1726 
1727         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1728         if (ret != 0)
1729                 goto err_add_port;
1730 
1731         pm_runtime_mark_last_busy(up->dev);
1732         pm_runtime_put_autosuspend(up->dev);
1733         return 0;
1734 
1735 err_add_port:
1736         pm_runtime_put(&pdev->dev);
1737         pm_runtime_disable(&pdev->dev);
1738 err_rs485:
1739 err_port_line:
1740         return ret;
1741 }
1742 
1743 static int serial_omap_remove(struct platform_device *dev)
1744 {
1745         struct uart_omap_port *up = platform_get_drvdata(dev);
1746 
1747         pm_runtime_put_sync(up->dev);
1748         pm_runtime_disable(up->dev);
1749         uart_remove_one_port(&serial_omap_reg, &up->port);
1750         pm_qos_remove_request(&up->pm_qos_request);
1751         device_init_wakeup(&dev->dev, false);
1752 
1753         return 0;
1754 }
1755 
1756 /*
1757  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1758  * The access to uart register after MDR1 Access
1759  * causes UART to corrupt data.
1760  *
1761  * Need a delay =
1762  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1763  * give 10 times as much
1764  */
1765 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1766 {
1767         u8 timeout = 255;
1768 
1769         serial_out(up, UART_OMAP_MDR1, mdr1);
1770         udelay(2);
1771         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1772                         UART_FCR_CLEAR_RCVR);
1773         /*
1774          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1775          * TX_FIFO_E bit is 1.
1776          */
1777         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1778                                 (UART_LSR_THRE | UART_LSR_DR))) {
1779                 timeout--;
1780                 if (!timeout) {
1781                         /* Should *never* happen. we warn and carry on */
1782                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1783                                                 serial_in(up, UART_LSR));
1784                         break;
1785                 }
1786                 udelay(1);
1787         }
1788 }
1789 
1790 #ifdef CONFIG_PM
1791 static void serial_omap_restore_context(struct uart_omap_port *up)
1792 {
1793         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1794                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1795         else
1796                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1797 
1798         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1799         serial_out(up, UART_EFR, UART_EFR_ECB);
1800         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1801         serial_out(up, UART_IER, 0x0);
1802         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1803         serial_out(up, UART_DLL, up->dll);
1804         serial_out(up, UART_DLM, up->dlh);
1805         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1806         serial_out(up, UART_IER, up->ier);
1807         serial_out(up, UART_FCR, up->fcr);
1808         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1809         serial_out(up, UART_MCR, up->mcr);
1810         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1811         serial_out(up, UART_OMAP_SCR, up->scr);
1812         serial_out(up, UART_EFR, up->efr);
1813         serial_out(up, UART_LCR, up->lcr);
1814         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1815                 serial_omap_mdr1_errataset(up, up->mdr1);
1816         else
1817                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1818         serial_out(up, UART_OMAP_WER, up->wer);
1819 }
1820 
1821 static int serial_omap_runtime_suspend(struct device *dev)
1822 {
1823         struct uart_omap_port *up = dev_get_drvdata(dev);
1824 
1825         if (!up)
1826                 return -EINVAL;
1827 
1828         /*
1829         * When using 'no_console_suspend', the console UART must not be
1830         * suspended. Since driver suspend is managed by runtime suspend,
1831         * preventing runtime suspend (by returning error) will keep device
1832         * active during suspend.
1833         */
1834         if (up->is_suspending && !console_suspend_enabled &&
1835             uart_console(&up->port))
1836                 return -EBUSY;
1837 
1838         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1839 
1840         serial_omap_enable_wakeup(up, true);
1841 
1842         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1843         schedule_work(&up->qos_work);
1844 
1845         return 0;
1846 }
1847 
1848 static int serial_omap_runtime_resume(struct device *dev)
1849 {
1850         struct uart_omap_port *up = dev_get_drvdata(dev);
1851 
1852         int loss_cnt = serial_omap_get_context_loss_count(up);
1853 
1854         serial_omap_enable_wakeup(up, false);
1855 
1856         if (loss_cnt < 0) {
1857                 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1858                         loss_cnt);
1859                 serial_omap_restore_context(up);
1860         } else if (up->context_loss_cnt != loss_cnt) {
1861                 serial_omap_restore_context(up);
1862         }
1863         up->latency = up->calc_latency;
1864         schedule_work(&up->qos_work);
1865 
1866         return 0;
1867 }
1868 #endif
1869 
1870 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1871         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1872         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1873                                 serial_omap_runtime_resume, NULL)
1874         .prepare        = serial_omap_prepare,
1875         .complete       = serial_omap_complete,
1876 };
1877 
1878 #if defined(CONFIG_OF)
1879 static const struct of_device_id omap_serial_of_match[] = {
1880         { .compatible = "ti,omap2-uart" },
1881         { .compatible = "ti,omap3-uart" },
1882         { .compatible = "ti,omap4-uart" },
1883         {},
1884 };
1885 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1886 #endif
1887 
1888 static struct platform_driver serial_omap_driver = {
1889         .probe          = serial_omap_probe,
1890         .remove         = serial_omap_remove,
1891         .driver         = {
1892                 .name   = DRIVER_NAME,
1893                 .pm     = &serial_omap_dev_pm_ops,
1894                 .of_match_table = of_match_ptr(omap_serial_of_match),
1895         },
1896 };
1897 
1898 static int __init serial_omap_init(void)
1899 {
1900         int ret;
1901 
1902         ret = uart_register_driver(&serial_omap_reg);
1903         if (ret != 0)
1904                 return ret;
1905         ret = platform_driver_register(&serial_omap_driver);
1906         if (ret != 0)
1907                 uart_unregister_driver(&serial_omap_reg);
1908         return ret;
1909 }
1910 
1911 static void __exit serial_omap_exit(void)
1912 {
1913         platform_driver_unregister(&serial_omap_driver);
1914         uart_unregister_driver(&serial_omap_reg);
1915 }
1916 
1917 module_init(serial_omap_init);
1918 module_exit(serial_omap_exit);
1919 
1920 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1921 MODULE_LICENSE("GPL");
1922 MODULE_AUTHOR("Texas Instruments Inc");
1923 

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