Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/tty/serial/omap-serial.c

  1 /*
  2  * Driver for OMAP-UART controller.
  3  * Based on drivers/serial/8250.c
  4  *
  5  * Copyright (C) 2010 Texas Instruments.
  6  *
  7  * Authors:
  8  *      Govindraj R     <govindraj.raja@ti.com>
  9  *      Thara Gopinath  <thara@ti.com>
 10  *
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License as published by
 13  * the Free Software Foundation; either version 2 of the License, or
 14  * (at your option) any later version.
 15  *
 16  * Note: This driver is made separate from 8250 driver as we cannot
 17  * over load 8250 driver with omap platform specific configuration for
 18  * features like DMA, it makes easier to implement features like DMA and
 19  * hardware flow control and software flow control configuration with
 20  * this driver as required for the omap-platform.
 21  */
 22 
 23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 24 #define SUPPORT_SYSRQ
 25 #endif
 26 
 27 #include <linux/module.h>
 28 #include <linux/init.h>
 29 #include <linux/console.h>
 30 #include <linux/serial_reg.h>
 31 #include <linux/delay.h>
 32 #include <linux/slab.h>
 33 #include <linux/tty.h>
 34 #include <linux/tty_flip.h>
 35 #include <linux/platform_device.h>
 36 #include <linux/io.h>
 37 #include <linux/clk.h>
 38 #include <linux/serial_core.h>
 39 #include <linux/irq.h>
 40 #include <linux/pm_runtime.h>
 41 #include <linux/of.h>
 42 #include <linux/of_irq.h>
 43 #include <linux/gpio.h>
 44 #include <linux/of_gpio.h>
 45 #include <linux/platform_data/serial-omap.h>
 46 
 47 #include <dt-bindings/gpio/gpio.h>
 48 
 49 #define OMAP_MAX_HSUART_PORTS   6
 50 
 51 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
 52 
 53 #define OMAP_UART_REV_42 0x0402
 54 #define OMAP_UART_REV_46 0x0406
 55 #define OMAP_UART_REV_52 0x0502
 56 #define OMAP_UART_REV_63 0x0603
 57 
 58 #define OMAP_UART_TX_WAKEUP_EN          BIT(7)
 59 
 60 /* Feature flags */
 61 #define OMAP_UART_WER_HAS_TX_WAKEUP     BIT(0)
 62 
 63 #define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
 64 #define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
 65 
 66 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
 67 
 68 /* SCR register bitmasks */
 69 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
 70 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK               (1 << 6)
 71 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
 72 
 73 /* FCR register bitmasks */
 74 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
 75 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
 76 
 77 /* MVR register bitmasks */
 78 #define OMAP_UART_MVR_SCHEME_SHIFT      30
 79 
 80 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
 81 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
 82 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
 83 
 84 #define OMAP_UART_MVR_MAJ_MASK          0x700
 85 #define OMAP_UART_MVR_MAJ_SHIFT         8
 86 #define OMAP_UART_MVR_MIN_MASK          0x3f
 87 
 88 #define OMAP_UART_DMA_CH_FREE   -1
 89 
 90 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
 91 #define OMAP_MODE13X_SPEED      230400
 92 
 93 /* WER = 0x7F
 94  * Enable module level wakeup in WER reg
 95  */
 96 #define OMAP_UART_WER_MOD_WKUP  0X7F
 97 
 98 /* Enable XON/XOFF flow control on output */
 99 #define OMAP_UART_SW_TX         0x08
100 
101 /* Enable XON/XOFF flow control on input */
102 #define OMAP_UART_SW_RX         0x02
103 
104 #define OMAP_UART_SW_CLR        0xF0
105 
106 #define OMAP_UART_TCR_TRIG      0x0F
107 
108 struct uart_omap_dma {
109         u8                      uart_dma_tx;
110         u8                      uart_dma_rx;
111         int                     rx_dma_channel;
112         int                     tx_dma_channel;
113         dma_addr_t              rx_buf_dma_phys;
114         dma_addr_t              tx_buf_dma_phys;
115         unsigned int            uart_base;
116         /*
117          * Buffer for rx dma.It is not required for tx because the buffer
118          * comes from port structure.
119          */
120         unsigned char           *rx_buf;
121         unsigned int            prev_rx_dma_pos;
122         int                     tx_buf_size;
123         int                     tx_dma_used;
124         int                     rx_dma_used;
125         spinlock_t              tx_lock;
126         spinlock_t              rx_lock;
127         /* timer to poll activity on rx dma */
128         struct timer_list       rx_timer;
129         unsigned int            rx_buf_size;
130         unsigned int            rx_poll_rate;
131         unsigned int            rx_timeout;
132 };
133 
134 struct uart_omap_port {
135         struct uart_port        port;
136         struct uart_omap_dma    uart_dma;
137         struct device           *dev;
138         int                     wakeirq;
139 
140         unsigned char           ier;
141         unsigned char           lcr;
142         unsigned char           mcr;
143         unsigned char           fcr;
144         unsigned char           efr;
145         unsigned char           dll;
146         unsigned char           dlh;
147         unsigned char           mdr1;
148         unsigned char           scr;
149         unsigned char           wer;
150 
151         int                     use_dma;
152         /*
153          * Some bits in registers are cleared on a read, so they must
154          * be saved whenever the register is read but the bits will not
155          * be immediately processed.
156          */
157         unsigned int            lsr_break_flag;
158         unsigned char           msr_saved_flags;
159         char                    name[20];
160         unsigned long           port_activity;
161         int                     context_loss_cnt;
162         u32                     errata;
163         u8                      wakeups_enabled;
164         u32                     features;
165 
166         struct serial_rs485     rs485;
167         int                     rts_gpio;
168 
169         struct pm_qos_request   pm_qos_request;
170         u32                     latency;
171         u32                     calc_latency;
172         struct work_struct      qos_work;
173         bool                    is_suspending;
174 };
175 
176 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
177 
178 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
179 
180 /* Forward declaration of functions */
181 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
182 
183 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
184 {
185         offset <<= up->port.regshift;
186         return readw(up->port.membase + offset);
187 }
188 
189 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
190 {
191         offset <<= up->port.regshift;
192         writew(value, up->port.membase + offset);
193 }
194 
195 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
196 {
197         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
198         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
199                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
200         serial_out(up, UART_FCR, 0);
201 }
202 
203 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
204 {
205         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
206 
207         if (!pdata || !pdata->get_context_loss_count)
208                 return -EINVAL;
209 
210         return pdata->get_context_loss_count(up->dev);
211 }
212 
213 static inline void serial_omap_enable_wakeirq(struct uart_omap_port *up,
214                                        bool enable)
215 {
216         if (!up->wakeirq)
217                 return;
218 
219         if (enable)
220                 enable_irq(up->wakeirq);
221         else
222                 disable_irq_nosync(up->wakeirq);
223 }
224 
225 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
226 {
227         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
228 
229         if (enable == up->wakeups_enabled)
230                 return;
231 
232         serial_omap_enable_wakeirq(up, enable);
233         up->wakeups_enabled = enable;
234 
235         if (!pdata || !pdata->enable_wakeup)
236                 return;
237 
238         pdata->enable_wakeup(up->dev, enable);
239 }
240 
241 /*
242  * Calculate the absolute difference between the desired and actual baud
243  * rate for the given mode.
244  */
245 static inline int calculate_baud_abs_diff(struct uart_port *port,
246                                 unsigned int baud, unsigned int mode)
247 {
248         unsigned int n = port->uartclk / (mode * baud);
249         int abs_diff;
250 
251         if (n == 0)
252                 n = 1;
253 
254         abs_diff = baud - (port->uartclk / (mode * n));
255         if (abs_diff < 0)
256                 abs_diff = -abs_diff;
257 
258         return abs_diff;
259 }
260 
261 /*
262  * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
263  * @port: uart port info
264  * @baud: baudrate for which mode needs to be determined
265  *
266  * Returns true if baud rate is MODE16X and false if MODE13X
267  * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
268  * and Error Rates" determines modes not for all common baud rates.
269  * E.g. for 1000000 baud rate mode must be 16x, but according to that
270  * table it's determined as 13x.
271  */
272 static bool
273 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
274 {
275         int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
276         int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
277 
278         return (abs_diff_13 >= abs_diff_16);
279 }
280 
281 /*
282  * serial_omap_get_divisor - calculate divisor value
283  * @port: uart port info
284  * @baud: baudrate for which divisor needs to be calculated.
285  */
286 static unsigned int
287 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
288 {
289         unsigned int mode;
290 
291         if (!serial_omap_baud_is_mode16(port, baud))
292                 mode = 13;
293         else
294                 mode = 16;
295         return port->uartclk/(mode * baud);
296 }
297 
298 static void serial_omap_enable_ms(struct uart_port *port)
299 {
300         struct uart_omap_port *up = to_uart_omap_port(port);
301 
302         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
303 
304         pm_runtime_get_sync(up->dev);
305         up->ier |= UART_IER_MSI;
306         serial_out(up, UART_IER, up->ier);
307         pm_runtime_mark_last_busy(up->dev);
308         pm_runtime_put_autosuspend(up->dev);
309 }
310 
311 static void serial_omap_stop_tx(struct uart_port *port)
312 {
313         struct uart_omap_port *up = to_uart_omap_port(port);
314         int res;
315 
316         pm_runtime_get_sync(up->dev);
317 
318         /* Handle RS-485 */
319         if (up->rs485.flags & SER_RS485_ENABLED) {
320                 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
321                         /* THR interrupt is fired when both TX FIFO and TX
322                          * shift register are empty. This means there's nothing
323                          * left to transmit now, so make sure the THR interrupt
324                          * is fired when TX FIFO is below the trigger level,
325                          * disable THR interrupts and toggle the RS-485 GPIO
326                          * data direction pin if needed.
327                          */
328                         up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
329                         serial_out(up, UART_OMAP_SCR, up->scr);
330                         res = (up->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
331                         if (gpio_get_value(up->rts_gpio) != res) {
332                                 if (up->rs485.delay_rts_after_send > 0)
333                                         mdelay(up->rs485.delay_rts_after_send);
334                                 gpio_set_value(up->rts_gpio, res);
335                         }
336                 } else {
337                         /* We're asked to stop, but there's still stuff in the
338                          * UART FIFO, so make sure the THR interrupt is fired
339                          * when both TX FIFO and TX shift register are empty.
340                          * The next THR interrupt (if no transmission is started
341                          * in the meantime) will indicate the end of a
342                          * transmission. Therefore we _don't_ disable THR
343                          * interrupts in this situation.
344                          */
345                         up->scr |= OMAP_UART_SCR_TX_EMPTY;
346                         serial_out(up, UART_OMAP_SCR, up->scr);
347                         return;
348                 }
349         }
350 
351         if (up->ier & UART_IER_THRI) {
352                 up->ier &= ~UART_IER_THRI;
353                 serial_out(up, UART_IER, up->ier);
354         }
355 
356         if ((up->rs485.flags & SER_RS485_ENABLED) &&
357             !(up->rs485.flags & SER_RS485_RX_DURING_TX)) {
358                 /*
359                  * Empty the RX FIFO, we are not interested in anything
360                  * received during the half-duplex transmission.
361                  */
362                 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
363                 /* Re-enable RX interrupts */
364                 up->ier |= UART_IER_RLSI | UART_IER_RDI;
365                 up->port.read_status_mask |= UART_LSR_DR;
366                 serial_out(up, UART_IER, up->ier);
367         }
368 
369         pm_runtime_mark_last_busy(up->dev);
370         pm_runtime_put_autosuspend(up->dev);
371 }
372 
373 static void serial_omap_stop_rx(struct uart_port *port)
374 {
375         struct uart_omap_port *up = to_uart_omap_port(port);
376 
377         pm_runtime_get_sync(up->dev);
378         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
379         up->port.read_status_mask &= ~UART_LSR_DR;
380         serial_out(up, UART_IER, up->ier);
381         pm_runtime_mark_last_busy(up->dev);
382         pm_runtime_put_autosuspend(up->dev);
383 }
384 
385 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
386 {
387         struct circ_buf *xmit = &up->port.state->xmit;
388         int count;
389 
390         if (up->port.x_char) {
391                 serial_out(up, UART_TX, up->port.x_char);
392                 up->port.icount.tx++;
393                 up->port.x_char = 0;
394                 return;
395         }
396         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
397                 serial_omap_stop_tx(&up->port);
398                 return;
399         }
400         count = up->port.fifosize / 4;
401         do {
402                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
403                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
404                 up->port.icount.tx++;
405                 if (uart_circ_empty(xmit))
406                         break;
407         } while (--count > 0);
408 
409         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
410                 uart_write_wakeup(&up->port);
411 
412         if (uart_circ_empty(xmit))
413                 serial_omap_stop_tx(&up->port);
414 }
415 
416 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
417 {
418         if (!(up->ier & UART_IER_THRI)) {
419                 up->ier |= UART_IER_THRI;
420                 serial_out(up, UART_IER, up->ier);
421         }
422 }
423 
424 static void serial_omap_start_tx(struct uart_port *port)
425 {
426         struct uart_omap_port *up = to_uart_omap_port(port);
427         int res;
428 
429         pm_runtime_get_sync(up->dev);
430 
431         /* Handle RS-485 */
432         if (up->rs485.flags & SER_RS485_ENABLED) {
433                 /* Fire THR interrupts when FIFO is below trigger level */
434                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
435                 serial_out(up, UART_OMAP_SCR, up->scr);
436 
437                 /* if rts not already enabled */
438                 res = (up->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
439                 if (gpio_get_value(up->rts_gpio) != res) {
440                         gpio_set_value(up->rts_gpio, res);
441                         if (up->rs485.delay_rts_before_send > 0)
442                                 mdelay(up->rs485.delay_rts_before_send);
443                 }
444         }
445 
446         if ((up->rs485.flags & SER_RS485_ENABLED) &&
447             !(up->rs485.flags & SER_RS485_RX_DURING_TX))
448                 serial_omap_stop_rx(port);
449 
450         serial_omap_enable_ier_thri(up);
451         pm_runtime_mark_last_busy(up->dev);
452         pm_runtime_put_autosuspend(up->dev);
453 }
454 
455 static void serial_omap_throttle(struct uart_port *port)
456 {
457         struct uart_omap_port *up = to_uart_omap_port(port);
458         unsigned long flags;
459 
460         pm_runtime_get_sync(up->dev);
461         spin_lock_irqsave(&up->port.lock, flags);
462         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
463         serial_out(up, UART_IER, up->ier);
464         spin_unlock_irqrestore(&up->port.lock, flags);
465         pm_runtime_mark_last_busy(up->dev);
466         pm_runtime_put_autosuspend(up->dev);
467 }
468 
469 static void serial_omap_unthrottle(struct uart_port *port)
470 {
471         struct uart_omap_port *up = to_uart_omap_port(port);
472         unsigned long flags;
473 
474         pm_runtime_get_sync(up->dev);
475         spin_lock_irqsave(&up->port.lock, flags);
476         up->ier |= UART_IER_RLSI | UART_IER_RDI;
477         serial_out(up, UART_IER, up->ier);
478         spin_unlock_irqrestore(&up->port.lock, flags);
479         pm_runtime_mark_last_busy(up->dev);
480         pm_runtime_put_autosuspend(up->dev);
481 }
482 
483 static unsigned int check_modem_status(struct uart_omap_port *up)
484 {
485         unsigned int status;
486 
487         status = serial_in(up, UART_MSR);
488         status |= up->msr_saved_flags;
489         up->msr_saved_flags = 0;
490         if ((status & UART_MSR_ANY_DELTA) == 0)
491                 return status;
492 
493         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
494             up->port.state != NULL) {
495                 if (status & UART_MSR_TERI)
496                         up->port.icount.rng++;
497                 if (status & UART_MSR_DDSR)
498                         up->port.icount.dsr++;
499                 if (status & UART_MSR_DDCD)
500                         uart_handle_dcd_change
501                                 (&up->port, status & UART_MSR_DCD);
502                 if (status & UART_MSR_DCTS)
503                         uart_handle_cts_change
504                                 (&up->port, status & UART_MSR_CTS);
505                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
506         }
507 
508         return status;
509 }
510 
511 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
512 {
513         unsigned int flag;
514         unsigned char ch = 0;
515 
516         if (likely(lsr & UART_LSR_DR))
517                 ch = serial_in(up, UART_RX);
518 
519         up->port.icount.rx++;
520         flag = TTY_NORMAL;
521 
522         if (lsr & UART_LSR_BI) {
523                 flag = TTY_BREAK;
524                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
525                 up->port.icount.brk++;
526                 /*
527                  * We do the SysRQ and SAK checking
528                  * here because otherwise the break
529                  * may get masked by ignore_status_mask
530                  * or read_status_mask.
531                  */
532                 if (uart_handle_break(&up->port))
533                         return;
534 
535         }
536 
537         if (lsr & UART_LSR_PE) {
538                 flag = TTY_PARITY;
539                 up->port.icount.parity++;
540         }
541 
542         if (lsr & UART_LSR_FE) {
543                 flag = TTY_FRAME;
544                 up->port.icount.frame++;
545         }
546 
547         if (lsr & UART_LSR_OE)
548                 up->port.icount.overrun++;
549 
550 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
551         if (up->port.line == up->port.cons->index) {
552                 /* Recover the break flag from console xmit */
553                 lsr |= up->lsr_break_flag;
554         }
555 #endif
556         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
557 }
558 
559 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
560 {
561         unsigned char ch = 0;
562         unsigned int flag;
563 
564         if (!(lsr & UART_LSR_DR))
565                 return;
566 
567         ch = serial_in(up, UART_RX);
568         flag = TTY_NORMAL;
569         up->port.icount.rx++;
570 
571         if (uart_handle_sysrq_char(&up->port, ch))
572                 return;
573 
574         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
575 }
576 
577 /**
578  * serial_omap_irq() - This handles the interrupt from one port
579  * @irq: uart port irq number
580  * @dev_id: uart port info
581  */
582 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
583 {
584         struct uart_omap_port *up = dev_id;
585         unsigned int iir, lsr;
586         unsigned int type;
587         irqreturn_t ret = IRQ_NONE;
588         int max_count = 256;
589 
590         spin_lock(&up->port.lock);
591         pm_runtime_get_sync(up->dev);
592 
593         do {
594                 iir = serial_in(up, UART_IIR);
595                 if (iir & UART_IIR_NO_INT)
596                         break;
597 
598                 ret = IRQ_HANDLED;
599                 lsr = serial_in(up, UART_LSR);
600 
601                 /* extract IRQ type from IIR register */
602                 type = iir & 0x3e;
603 
604                 switch (type) {
605                 case UART_IIR_MSI:
606                         check_modem_status(up);
607                         break;
608                 case UART_IIR_THRI:
609                         transmit_chars(up, lsr);
610                         break;
611                 case UART_IIR_RX_TIMEOUT:
612                         /* FALLTHROUGH */
613                 case UART_IIR_RDI:
614                         serial_omap_rdi(up, lsr);
615                         break;
616                 case UART_IIR_RLSI:
617                         serial_omap_rlsi(up, lsr);
618                         break;
619                 case UART_IIR_CTS_RTS_DSR:
620                         /* simply try again */
621                         break;
622                 case UART_IIR_XOFF:
623                         /* FALLTHROUGH */
624                 default:
625                         break;
626                 }
627         } while (!(iir & UART_IIR_NO_INT) && max_count--);
628 
629         spin_unlock(&up->port.lock);
630 
631         tty_flip_buffer_push(&up->port.state->port);
632 
633         pm_runtime_mark_last_busy(up->dev);
634         pm_runtime_put_autosuspend(up->dev);
635         up->port_activity = jiffies;
636 
637         return ret;
638 }
639 
640 static unsigned int serial_omap_tx_empty(struct uart_port *port)
641 {
642         struct uart_omap_port *up = to_uart_omap_port(port);
643         unsigned long flags = 0;
644         unsigned int ret = 0;
645 
646         pm_runtime_get_sync(up->dev);
647         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
648         spin_lock_irqsave(&up->port.lock, flags);
649         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
650         spin_unlock_irqrestore(&up->port.lock, flags);
651         pm_runtime_mark_last_busy(up->dev);
652         pm_runtime_put_autosuspend(up->dev);
653         return ret;
654 }
655 
656 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
657 {
658         struct uart_omap_port *up = to_uart_omap_port(port);
659         unsigned int status;
660         unsigned int ret = 0;
661 
662         pm_runtime_get_sync(up->dev);
663         status = check_modem_status(up);
664         pm_runtime_mark_last_busy(up->dev);
665         pm_runtime_put_autosuspend(up->dev);
666 
667         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
668 
669         if (status & UART_MSR_DCD)
670                 ret |= TIOCM_CAR;
671         if (status & UART_MSR_RI)
672                 ret |= TIOCM_RNG;
673         if (status & UART_MSR_DSR)
674                 ret |= TIOCM_DSR;
675         if (status & UART_MSR_CTS)
676                 ret |= TIOCM_CTS;
677         return ret;
678 }
679 
680 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
681 {
682         struct uart_omap_port *up = to_uart_omap_port(port);
683         unsigned char mcr = 0, old_mcr;
684 
685         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
686         if (mctrl & TIOCM_RTS)
687                 mcr |= UART_MCR_RTS;
688         if (mctrl & TIOCM_DTR)
689                 mcr |= UART_MCR_DTR;
690         if (mctrl & TIOCM_OUT1)
691                 mcr |= UART_MCR_OUT1;
692         if (mctrl & TIOCM_OUT2)
693                 mcr |= UART_MCR_OUT2;
694         if (mctrl & TIOCM_LOOP)
695                 mcr |= UART_MCR_LOOP;
696 
697         pm_runtime_get_sync(up->dev);
698         old_mcr = serial_in(up, UART_MCR);
699         old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
700                      UART_MCR_DTR | UART_MCR_RTS);
701         up->mcr = old_mcr | mcr;
702         serial_out(up, UART_MCR, up->mcr);
703         pm_runtime_mark_last_busy(up->dev);
704         pm_runtime_put_autosuspend(up->dev);
705 }
706 
707 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
708 {
709         struct uart_omap_port *up = to_uart_omap_port(port);
710         unsigned long flags = 0;
711 
712         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
713         pm_runtime_get_sync(up->dev);
714         spin_lock_irqsave(&up->port.lock, flags);
715         if (break_state == -1)
716                 up->lcr |= UART_LCR_SBC;
717         else
718                 up->lcr &= ~UART_LCR_SBC;
719         serial_out(up, UART_LCR, up->lcr);
720         spin_unlock_irqrestore(&up->port.lock, flags);
721         pm_runtime_mark_last_busy(up->dev);
722         pm_runtime_put_autosuspend(up->dev);
723 }
724 
725 static int serial_omap_startup(struct uart_port *port)
726 {
727         struct uart_omap_port *up = to_uart_omap_port(port);
728         unsigned long flags = 0;
729         int retval;
730 
731         /*
732          * Allocate the IRQ
733          */
734         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
735                                 up->name, up);
736         if (retval)
737                 return retval;
738 
739         /* Optional wake-up IRQ */
740         if (up->wakeirq) {
741                 retval = request_irq(up->wakeirq, serial_omap_irq,
742                                      up->port.irqflags, up->name, up);
743                 if (retval) {
744                         free_irq(up->port.irq, up);
745                         return retval;
746                 }
747                 disable_irq(up->wakeirq);
748         }
749 
750         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
751 
752         pm_runtime_get_sync(up->dev);
753         /*
754          * Clear the FIFO buffers and disable them.
755          * (they will be reenabled in set_termios())
756          */
757         serial_omap_clear_fifos(up);
758         /* For Hardware flow control */
759         serial_out(up, UART_MCR, UART_MCR_RTS);
760 
761         /*
762          * Clear the interrupt registers.
763          */
764         (void) serial_in(up, UART_LSR);
765         if (serial_in(up, UART_LSR) & UART_LSR_DR)
766                 (void) serial_in(up, UART_RX);
767         (void) serial_in(up, UART_IIR);
768         (void) serial_in(up, UART_MSR);
769 
770         /*
771          * Now, initialize the UART
772          */
773         serial_out(up, UART_LCR, UART_LCR_WLEN8);
774         spin_lock_irqsave(&up->port.lock, flags);
775         /*
776          * Most PC uarts need OUT2 raised to enable interrupts.
777          */
778         up->port.mctrl |= TIOCM_OUT2;
779         serial_omap_set_mctrl(&up->port, up->port.mctrl);
780         spin_unlock_irqrestore(&up->port.lock, flags);
781 
782         up->msr_saved_flags = 0;
783         /*
784          * Finally, enable interrupts. Note: Modem status interrupts
785          * are set via set_termios(), which will be occurring imminently
786          * anyway, so we don't enable them here.
787          */
788         up->ier = UART_IER_RLSI | UART_IER_RDI;
789         serial_out(up, UART_IER, up->ier);
790 
791         /* Enable module level wake up */
792         up->wer = OMAP_UART_WER_MOD_WKUP;
793         if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
794                 up->wer |= OMAP_UART_TX_WAKEUP_EN;
795 
796         serial_out(up, UART_OMAP_WER, up->wer);
797 
798         pm_runtime_mark_last_busy(up->dev);
799         pm_runtime_put_autosuspend(up->dev);
800         up->port_activity = jiffies;
801         return 0;
802 }
803 
804 static void serial_omap_shutdown(struct uart_port *port)
805 {
806         struct uart_omap_port *up = to_uart_omap_port(port);
807         unsigned long flags = 0;
808 
809         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
810 
811         pm_runtime_get_sync(up->dev);
812         /*
813          * Disable interrupts from this port
814          */
815         up->ier = 0;
816         serial_out(up, UART_IER, 0);
817 
818         spin_lock_irqsave(&up->port.lock, flags);
819         up->port.mctrl &= ~TIOCM_OUT2;
820         serial_omap_set_mctrl(&up->port, up->port.mctrl);
821         spin_unlock_irqrestore(&up->port.lock, flags);
822 
823         /*
824          * Disable break condition and FIFOs
825          */
826         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
827         serial_omap_clear_fifos(up);
828 
829         /*
830          * Read data port to reset things, and then free the irq
831          */
832         if (serial_in(up, UART_LSR) & UART_LSR_DR)
833                 (void) serial_in(up, UART_RX);
834 
835         pm_runtime_mark_last_busy(up->dev);
836         pm_runtime_put_autosuspend(up->dev);
837         free_irq(up->port.irq, up);
838         if (up->wakeirq)
839                 free_irq(up->wakeirq, up);
840 }
841 
842 static void serial_omap_uart_qos_work(struct work_struct *work)
843 {
844         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
845                                                 qos_work);
846 
847         pm_qos_update_request(&up->pm_qos_request, up->latency);
848 }
849 
850 static void
851 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
852                         struct ktermios *old)
853 {
854         struct uart_omap_port *up = to_uart_omap_port(port);
855         unsigned char cval = 0;
856         unsigned long flags = 0;
857         unsigned int baud, quot;
858 
859         switch (termios->c_cflag & CSIZE) {
860         case CS5:
861                 cval = UART_LCR_WLEN5;
862                 break;
863         case CS6:
864                 cval = UART_LCR_WLEN6;
865                 break;
866         case CS7:
867                 cval = UART_LCR_WLEN7;
868                 break;
869         default:
870         case CS8:
871                 cval = UART_LCR_WLEN8;
872                 break;
873         }
874 
875         if (termios->c_cflag & CSTOPB)
876                 cval |= UART_LCR_STOP;
877         if (termios->c_cflag & PARENB)
878                 cval |= UART_LCR_PARITY;
879         if (!(termios->c_cflag & PARODD))
880                 cval |= UART_LCR_EPAR;
881         if (termios->c_cflag & CMSPAR)
882                 cval |= UART_LCR_SPAR;
883 
884         /*
885          * Ask the core to calculate the divisor for us.
886          */
887 
888         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
889         quot = serial_omap_get_divisor(port, baud);
890 
891         /* calculate wakeup latency constraint */
892         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
893         up->latency = up->calc_latency;
894         schedule_work(&up->qos_work);
895 
896         up->dll = quot & 0xff;
897         up->dlh = quot >> 8;
898         up->mdr1 = UART_OMAP_MDR1_DISABLE;
899 
900         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
901                         UART_FCR_ENABLE_FIFO;
902 
903         /*
904          * Ok, we're now changing the port state. Do it with
905          * interrupts disabled.
906          */
907         pm_runtime_get_sync(up->dev);
908         spin_lock_irqsave(&up->port.lock, flags);
909 
910         /*
911          * Update the per-port timeout.
912          */
913         uart_update_timeout(port, termios->c_cflag, baud);
914 
915         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
916         if (termios->c_iflag & INPCK)
917                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
918         if (termios->c_iflag & (BRKINT | PARMRK))
919                 up->port.read_status_mask |= UART_LSR_BI;
920 
921         /*
922          * Characters to ignore
923          */
924         up->port.ignore_status_mask = 0;
925         if (termios->c_iflag & IGNPAR)
926                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
927         if (termios->c_iflag & IGNBRK) {
928                 up->port.ignore_status_mask |= UART_LSR_BI;
929                 /*
930                  * If we're ignoring parity and break indicators,
931                  * ignore overruns too (for real raw support).
932                  */
933                 if (termios->c_iflag & IGNPAR)
934                         up->port.ignore_status_mask |= UART_LSR_OE;
935         }
936 
937         /*
938          * ignore all characters if CREAD is not set
939          */
940         if ((termios->c_cflag & CREAD) == 0)
941                 up->port.ignore_status_mask |= UART_LSR_DR;
942 
943         /*
944          * Modem status interrupts
945          */
946         up->ier &= ~UART_IER_MSI;
947         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
948                 up->ier |= UART_IER_MSI;
949         serial_out(up, UART_IER, up->ier);
950         serial_out(up, UART_LCR, cval);         /* reset DLAB */
951         up->lcr = cval;
952         up->scr = 0;
953 
954         /* FIFOs and DMA Settings */
955 
956         /* FCR can be changed only when the
957          * baud clock is not running
958          * DLL_REG and DLH_REG set to 0.
959          */
960         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
961         serial_out(up, UART_DLL, 0);
962         serial_out(up, UART_DLM, 0);
963         serial_out(up, UART_LCR, 0);
964 
965         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
966 
967         up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
968         up->efr &= ~UART_EFR_SCD;
969         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
970 
971         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
972         up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
973         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
974         /* FIFO ENABLE, DMA MODE */
975 
976         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
977         /*
978          * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
979          * sets Enables the granularity of 1 for TRIGGER RX
980          * level. Along with setting RX FIFO trigger level
981          * to 1 (as noted below, 16 characters) and TLR[3:0]
982          * to zero this will result RX FIFO threshold level
983          * to 1 character, instead of 16 as noted in comment
984          * below.
985          */
986 
987         /* Set receive FIFO threshold to 16 characters and
988          * transmit FIFO threshold to 32 spaces
989          */
990         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
991         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
992         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
993                 UART_FCR_ENABLE_FIFO;
994 
995         serial_out(up, UART_FCR, up->fcr);
996         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
997 
998         serial_out(up, UART_OMAP_SCR, up->scr);
999 
1000         /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
1001         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1002         serial_out(up, UART_MCR, up->mcr);
1003         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1004         serial_out(up, UART_EFR, up->efr);
1005         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1006 
1007         /* Protocol, Baud Rate, and Interrupt Settings */
1008 
1009         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1010                 serial_omap_mdr1_errataset(up, up->mdr1);
1011         else
1012                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1013 
1014         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1015         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1016 
1017         serial_out(up, UART_LCR, 0);
1018         serial_out(up, UART_IER, 0);
1019         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1020 
1021         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
1022         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
1023 
1024         serial_out(up, UART_LCR, 0);
1025         serial_out(up, UART_IER, up->ier);
1026         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1027 
1028         serial_out(up, UART_EFR, up->efr);
1029         serial_out(up, UART_LCR, cval);
1030 
1031         if (!serial_omap_baud_is_mode16(port, baud))
1032                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1033         else
1034                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1035 
1036         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1037                 serial_omap_mdr1_errataset(up, up->mdr1);
1038         else
1039                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1040 
1041         /* Configure flow control */
1042         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1043 
1044         /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1045         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1046         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1047 
1048         /* Enable access to TCR/TLR */
1049         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1050         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1051         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1052 
1053         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1054 
1055         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1056                 /* Enable AUTORTS and AUTOCTS */
1057                 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
1058 
1059                 /* Ensure MCR RTS is asserted */
1060                 up->mcr |= UART_MCR_RTS;
1061         } else {
1062                 /* Disable AUTORTS and AUTOCTS */
1063                 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1064         }
1065 
1066         if (up->port.flags & UPF_SOFT_FLOW) {
1067                 /* clear SW control mode bits */
1068                 up->efr &= OMAP_UART_SW_CLR;
1069 
1070                 /*
1071                  * IXON Flag:
1072                  * Enable XON/XOFF flow control on input.
1073                  * Receiver compares XON1, XOFF1.
1074                  */
1075                 if (termios->c_iflag & IXON)
1076                         up->efr |= OMAP_UART_SW_RX;
1077 
1078                 /*
1079                  * IXOFF Flag:
1080                  * Enable XON/XOFF flow control on output.
1081                  * Transmit XON1, XOFF1
1082                  */
1083                 if (termios->c_iflag & IXOFF)
1084                         up->efr |= OMAP_UART_SW_TX;
1085 
1086                 /*
1087                  * IXANY Flag:
1088                  * Enable any character to restart output.
1089                  * Operation resumes after receiving any
1090                  * character after recognition of the XOFF character
1091                  */
1092                 if (termios->c_iflag & IXANY)
1093                         up->mcr |= UART_MCR_XONANY;
1094                 else
1095                         up->mcr &= ~UART_MCR_XONANY;
1096         }
1097         serial_out(up, UART_MCR, up->mcr);
1098         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1099         serial_out(up, UART_EFR, up->efr);
1100         serial_out(up, UART_LCR, up->lcr);
1101 
1102         serial_omap_set_mctrl(&up->port, up->port.mctrl);
1103 
1104         spin_unlock_irqrestore(&up->port.lock, flags);
1105         pm_runtime_mark_last_busy(up->dev);
1106         pm_runtime_put_autosuspend(up->dev);
1107         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1108 }
1109 
1110 static void
1111 serial_omap_pm(struct uart_port *port, unsigned int state,
1112                unsigned int oldstate)
1113 {
1114         struct uart_omap_port *up = to_uart_omap_port(port);
1115         unsigned char efr;
1116 
1117         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1118 
1119         pm_runtime_get_sync(up->dev);
1120         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1121         efr = serial_in(up, UART_EFR);
1122         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1123         serial_out(up, UART_LCR, 0);
1124 
1125         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1126         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1127         serial_out(up, UART_EFR, efr);
1128         serial_out(up, UART_LCR, 0);
1129 
1130         if (!device_may_wakeup(up->dev)) {
1131                 if (!state)
1132                         pm_runtime_forbid(up->dev);
1133                 else
1134                         pm_runtime_allow(up->dev);
1135         }
1136 
1137         pm_runtime_mark_last_busy(up->dev);
1138         pm_runtime_put_autosuspend(up->dev);
1139 }
1140 
1141 static void serial_omap_release_port(struct uart_port *port)
1142 {
1143         dev_dbg(port->dev, "serial_omap_release_port+\n");
1144 }
1145 
1146 static int serial_omap_request_port(struct uart_port *port)
1147 {
1148         dev_dbg(port->dev, "serial_omap_request_port+\n");
1149         return 0;
1150 }
1151 
1152 static void serial_omap_config_port(struct uart_port *port, int flags)
1153 {
1154         struct uart_omap_port *up = to_uart_omap_port(port);
1155 
1156         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1157                                                         up->port.line);
1158         up->port.type = PORT_OMAP;
1159         up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1160 }
1161 
1162 static int
1163 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1164 {
1165         /* we don't want the core code to modify any port params */
1166         dev_dbg(port->dev, "serial_omap_verify_port+\n");
1167         return -EINVAL;
1168 }
1169 
1170 static const char *
1171 serial_omap_type(struct uart_port *port)
1172 {
1173         struct uart_omap_port *up = to_uart_omap_port(port);
1174 
1175         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1176         return up->name;
1177 }
1178 
1179 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1180 
1181 static inline void wait_for_xmitr(struct uart_omap_port *up)
1182 {
1183         unsigned int status, tmout = 10000;
1184 
1185         /* Wait up to 10ms for the character(s) to be sent. */
1186         do {
1187                 status = serial_in(up, UART_LSR);
1188 
1189                 if (status & UART_LSR_BI)
1190                         up->lsr_break_flag = UART_LSR_BI;
1191 
1192                 if (--tmout == 0)
1193                         break;
1194                 udelay(1);
1195         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1196 
1197         /* Wait up to 1s for flow control if necessary */
1198         if (up->port.flags & UPF_CONS_FLOW) {
1199                 tmout = 1000000;
1200                 for (tmout = 1000000; tmout; tmout--) {
1201                         unsigned int msr = serial_in(up, UART_MSR);
1202 
1203                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1204                         if (msr & UART_MSR_CTS)
1205                                 break;
1206 
1207                         udelay(1);
1208                 }
1209         }
1210 }
1211 
1212 #ifdef CONFIG_CONSOLE_POLL
1213 
1214 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1215 {
1216         struct uart_omap_port *up = to_uart_omap_port(port);
1217 
1218         pm_runtime_get_sync(up->dev);
1219         wait_for_xmitr(up);
1220         serial_out(up, UART_TX, ch);
1221         pm_runtime_mark_last_busy(up->dev);
1222         pm_runtime_put_autosuspend(up->dev);
1223 }
1224 
1225 static int serial_omap_poll_get_char(struct uart_port *port)
1226 {
1227         struct uart_omap_port *up = to_uart_omap_port(port);
1228         unsigned int status;
1229 
1230         pm_runtime_get_sync(up->dev);
1231         status = serial_in(up, UART_LSR);
1232         if (!(status & UART_LSR_DR)) {
1233                 status = NO_POLL_CHAR;
1234                 goto out;
1235         }
1236 
1237         status = serial_in(up, UART_RX);
1238 
1239 out:
1240         pm_runtime_mark_last_busy(up->dev);
1241         pm_runtime_put_autosuspend(up->dev);
1242 
1243         return status;
1244 }
1245 
1246 #endif /* CONFIG_CONSOLE_POLL */
1247 
1248 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1249 
1250 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1251 
1252 static struct uart_driver serial_omap_reg;
1253 
1254 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1255 {
1256         struct uart_omap_port *up = to_uart_omap_port(port);
1257 
1258         wait_for_xmitr(up);
1259         serial_out(up, UART_TX, ch);
1260 }
1261 
1262 static void
1263 serial_omap_console_write(struct console *co, const char *s,
1264                 unsigned int count)
1265 {
1266         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1267         unsigned long flags;
1268         unsigned int ier;
1269         int locked = 1;
1270 
1271         pm_runtime_get_sync(up->dev);
1272 
1273         local_irq_save(flags);
1274         if (up->port.sysrq)
1275                 locked = 0;
1276         else if (oops_in_progress)
1277                 locked = spin_trylock(&up->port.lock);
1278         else
1279                 spin_lock(&up->port.lock);
1280 
1281         /*
1282          * First save the IER then disable the interrupts
1283          */
1284         ier = serial_in(up, UART_IER);
1285         serial_out(up, UART_IER, 0);
1286 
1287         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1288 
1289         /*
1290          * Finally, wait for transmitter to become empty
1291          * and restore the IER
1292          */
1293         wait_for_xmitr(up);
1294         serial_out(up, UART_IER, ier);
1295         /*
1296          * The receive handling will happen properly because the
1297          * receive ready bit will still be set; it is not cleared
1298          * on read.  However, modem control will not, we must
1299          * call it if we have saved something in the saved flags
1300          * while processing with interrupts off.
1301          */
1302         if (up->msr_saved_flags)
1303                 check_modem_status(up);
1304 
1305         pm_runtime_mark_last_busy(up->dev);
1306         pm_runtime_put_autosuspend(up->dev);
1307         if (locked)
1308                 spin_unlock(&up->port.lock);
1309         local_irq_restore(flags);
1310 }
1311 
1312 static int __init
1313 serial_omap_console_setup(struct console *co, char *options)
1314 {
1315         struct uart_omap_port *up;
1316         int baud = 115200;
1317         int bits = 8;
1318         int parity = 'n';
1319         int flow = 'n';
1320 
1321         if (serial_omap_console_ports[co->index] == NULL)
1322                 return -ENODEV;
1323         up = serial_omap_console_ports[co->index];
1324 
1325         if (options)
1326                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1327 
1328         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1329 }
1330 
1331 static struct console serial_omap_console = {
1332         .name           = OMAP_SERIAL_NAME,
1333         .write          = serial_omap_console_write,
1334         .device         = uart_console_device,
1335         .setup          = serial_omap_console_setup,
1336         .flags          = CON_PRINTBUFFER,
1337         .index          = -1,
1338         .data           = &serial_omap_reg,
1339 };
1340 
1341 static void serial_omap_add_console_port(struct uart_omap_port *up)
1342 {
1343         serial_omap_console_ports[up->port.line] = up;
1344 }
1345 
1346 #define OMAP_CONSOLE    (&serial_omap_console)
1347 
1348 #else
1349 
1350 #define OMAP_CONSOLE    NULL
1351 
1352 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1353 {}
1354 
1355 #endif
1356 
1357 /* Enable or disable the rs485 support */
1358 static void
1359 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
1360 {
1361         struct uart_omap_port *up = to_uart_omap_port(port);
1362         unsigned long flags;
1363         unsigned int mode;
1364         int val;
1365 
1366         pm_runtime_get_sync(up->dev);
1367         spin_lock_irqsave(&up->port.lock, flags);
1368 
1369         /* Disable interrupts from this port */
1370         mode = up->ier;
1371         up->ier = 0;
1372         serial_out(up, UART_IER, 0);
1373 
1374         /* store new config */
1375         up->rs485 = *rs485conf;
1376 
1377         /*
1378          * Just as a precaution, only allow rs485
1379          * to be enabled if the gpio pin is valid
1380          */
1381         if (gpio_is_valid(up->rts_gpio)) {
1382                 /* enable / disable rts */
1383                 val = (up->rs485.flags & SER_RS485_ENABLED) ?
1384                         SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1385                 val = (up->rs485.flags & val) ? 1 : 0;
1386                 gpio_set_value(up->rts_gpio, val);
1387         } else
1388                 up->rs485.flags &= ~SER_RS485_ENABLED;
1389 
1390         /* Enable interrupts */
1391         up->ier = mode;
1392         serial_out(up, UART_IER, up->ier);
1393 
1394         /* If RS-485 is disabled, make sure the THR interrupt is fired when
1395          * TX FIFO is below the trigger level.
1396          */
1397         if (!(up->rs485.flags & SER_RS485_ENABLED) &&
1398             (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1399                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1400                 serial_out(up, UART_OMAP_SCR, up->scr);
1401         }
1402 
1403         spin_unlock_irqrestore(&up->port.lock, flags);
1404         pm_runtime_mark_last_busy(up->dev);
1405         pm_runtime_put_autosuspend(up->dev);
1406 }
1407 
1408 static int
1409 serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1410 {
1411         struct serial_rs485 rs485conf;
1412 
1413         switch (cmd) {
1414         case TIOCSRS485:
1415                 if (copy_from_user(&rs485conf, (void __user *) arg,
1416                                         sizeof(rs485conf)))
1417                         return -EFAULT;
1418 
1419                 serial_omap_config_rs485(port, &rs485conf);
1420                 break;
1421 
1422         case TIOCGRS485:
1423                 if (copy_to_user((void __user *) arg,
1424                                         &(to_uart_omap_port(port)->rs485),
1425                                         sizeof(rs485conf)))
1426                         return -EFAULT;
1427                 break;
1428 
1429         default:
1430                 return -ENOIOCTLCMD;
1431         }
1432         return 0;
1433 }
1434 
1435 
1436 static struct uart_ops serial_omap_pops = {
1437         .tx_empty       = serial_omap_tx_empty,
1438         .set_mctrl      = serial_omap_set_mctrl,
1439         .get_mctrl      = serial_omap_get_mctrl,
1440         .stop_tx        = serial_omap_stop_tx,
1441         .start_tx       = serial_omap_start_tx,
1442         .throttle       = serial_omap_throttle,
1443         .unthrottle     = serial_omap_unthrottle,
1444         .stop_rx        = serial_omap_stop_rx,
1445         .enable_ms      = serial_omap_enable_ms,
1446         .break_ctl      = serial_omap_break_ctl,
1447         .startup        = serial_omap_startup,
1448         .shutdown       = serial_omap_shutdown,
1449         .set_termios    = serial_omap_set_termios,
1450         .pm             = serial_omap_pm,
1451         .type           = serial_omap_type,
1452         .release_port   = serial_omap_release_port,
1453         .request_port   = serial_omap_request_port,
1454         .config_port    = serial_omap_config_port,
1455         .verify_port    = serial_omap_verify_port,
1456         .ioctl          = serial_omap_ioctl,
1457 #ifdef CONFIG_CONSOLE_POLL
1458         .poll_put_char  = serial_omap_poll_put_char,
1459         .poll_get_char  = serial_omap_poll_get_char,
1460 #endif
1461 };
1462 
1463 static struct uart_driver serial_omap_reg = {
1464         .owner          = THIS_MODULE,
1465         .driver_name    = "OMAP-SERIAL",
1466         .dev_name       = OMAP_SERIAL_NAME,
1467         .nr             = OMAP_MAX_HSUART_PORTS,
1468         .cons           = OMAP_CONSOLE,
1469 };
1470 
1471 #ifdef CONFIG_PM_SLEEP
1472 static int serial_omap_prepare(struct device *dev)
1473 {
1474         struct uart_omap_port *up = dev_get_drvdata(dev);
1475 
1476         up->is_suspending = true;
1477 
1478         return 0;
1479 }
1480 
1481 static void serial_omap_complete(struct device *dev)
1482 {
1483         struct uart_omap_port *up = dev_get_drvdata(dev);
1484 
1485         up->is_suspending = false;
1486 }
1487 
1488 static int serial_omap_suspend(struct device *dev)
1489 {
1490         struct uart_omap_port *up = dev_get_drvdata(dev);
1491 
1492         uart_suspend_port(&serial_omap_reg, &up->port);
1493         flush_work(&up->qos_work);
1494 
1495         if (device_may_wakeup(dev))
1496                 serial_omap_enable_wakeup(up, true);
1497         else
1498                 serial_omap_enable_wakeup(up, false);
1499 
1500         return 0;
1501 }
1502 
1503 static int serial_omap_resume(struct device *dev)
1504 {
1505         struct uart_omap_port *up = dev_get_drvdata(dev);
1506 
1507         if (device_may_wakeup(dev))
1508                 serial_omap_enable_wakeup(up, false);
1509 
1510         uart_resume_port(&serial_omap_reg, &up->port);
1511 
1512         return 0;
1513 }
1514 #else
1515 #define serial_omap_prepare NULL
1516 #define serial_omap_complete NULL
1517 #endif /* CONFIG_PM_SLEEP */
1518 
1519 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1520 {
1521         u32 mvr, scheme;
1522         u16 revision, major, minor;
1523 
1524         mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1525 
1526         /* Check revision register scheme */
1527         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1528 
1529         switch (scheme) {
1530         case 0: /* Legacy Scheme: OMAP2/3 */
1531                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1532                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1533                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1534                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1535                 break;
1536         case 1:
1537                 /* New Scheme: OMAP4+ */
1538                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1539                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1540                                         OMAP_UART_MVR_MAJ_SHIFT;
1541                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1542                 break;
1543         default:
1544                 dev_warn(up->dev,
1545                         "Unknown %s revision, defaulting to highest\n",
1546                         up->name);
1547                 /* highest possible revision */
1548                 major = 0xff;
1549                 minor = 0xff;
1550         }
1551 
1552         /* normalize revision for the driver */
1553         revision = UART_BUILD_REVISION(major, minor);
1554 
1555         switch (revision) {
1556         case OMAP_UART_REV_46:
1557                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1558                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1559                 break;
1560         case OMAP_UART_REV_52:
1561                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1562                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1563                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1564                 break;
1565         case OMAP_UART_REV_63:
1566                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1567                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1568                 break;
1569         default:
1570                 break;
1571         }
1572 }
1573 
1574 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1575 {
1576         struct omap_uart_port_info *omap_up_info;
1577 
1578         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1579         if (!omap_up_info)
1580                 return NULL; /* out of memory */
1581 
1582         of_property_read_u32(dev->of_node, "clock-frequency",
1583                                          &omap_up_info->uartclk);
1584         return omap_up_info;
1585 }
1586 
1587 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1588                                    struct device_node *np)
1589 {
1590         struct serial_rs485 *rs485conf = &up->rs485;
1591         u32 rs485_delay[2];
1592         enum of_gpio_flags flags;
1593         int ret;
1594 
1595         rs485conf->flags = 0;
1596         up->rts_gpio = -EINVAL;
1597 
1598         if (!np)
1599                 return 0;
1600 
1601         if (of_property_read_bool(np, "rs485-rts-active-high"))
1602                 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1603         else
1604                 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1605 
1606         /* check for tx enable gpio */
1607         up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags);
1608         if (gpio_is_valid(up->rts_gpio)) {
1609                 ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial");
1610                 if (ret < 0)
1611                         return ret;
1612                 ret = gpio_direction_output(up->rts_gpio,
1613                                             flags & SER_RS485_RTS_AFTER_SEND);
1614                 if (ret < 0)
1615                         return ret;
1616         } else if (up->rts_gpio == -EPROBE_DEFER) {
1617                 return -EPROBE_DEFER;
1618         } else {
1619                 up->rts_gpio = -EINVAL;
1620         }
1621 
1622         if (of_property_read_u32_array(np, "rs485-rts-delay",
1623                                     rs485_delay, 2) == 0) {
1624                 rs485conf->delay_rts_before_send = rs485_delay[0];
1625                 rs485conf->delay_rts_after_send = rs485_delay[1];
1626         }
1627 
1628         if (of_property_read_bool(np, "rs485-rx-during-tx"))
1629                 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1630 
1631         if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
1632                 rs485conf->flags |= SER_RS485_ENABLED;
1633 
1634         return 0;
1635 }
1636 
1637 static int serial_omap_probe(struct platform_device *pdev)
1638 {
1639         struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1640         struct uart_omap_port *up;
1641         struct resource *mem;
1642         void __iomem *base;
1643         int uartirq = 0;
1644         int wakeirq = 0;
1645         int ret;
1646 
1647         /* The optional wakeirq may be specified in the board dts file */
1648         if (pdev->dev.of_node) {
1649                 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1650                 if (!uartirq)
1651                         return -EPROBE_DEFER;
1652                 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1653                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1654                 pdev->dev.platform_data = omap_up_info;
1655         } else {
1656                 uartirq = platform_get_irq(pdev, 0);
1657                 if (uartirq < 0)
1658                         return -EPROBE_DEFER;
1659         }
1660 
1661         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1662         if (!up)
1663                 return -ENOMEM;
1664 
1665         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1666         base = devm_ioremap_resource(&pdev->dev, mem);
1667         if (IS_ERR(base))
1668                 return PTR_ERR(base);
1669 
1670         up->dev = &pdev->dev;
1671         up->port.dev = &pdev->dev;
1672         up->port.type = PORT_OMAP;
1673         up->port.iotype = UPIO_MEM;
1674         up->port.irq = uartirq;
1675         up->wakeirq = wakeirq;
1676         if (!up->wakeirq)
1677                 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1678                          up->port.line);
1679 
1680         up->port.regshift = 2;
1681         up->port.fifosize = 64;
1682         up->port.ops = &serial_omap_pops;
1683 
1684         if (pdev->dev.of_node)
1685                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1686         else
1687                 up->port.line = pdev->id;
1688 
1689         if (up->port.line < 0) {
1690                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1691                                                                 up->port.line);
1692                 ret = -ENODEV;
1693                 goto err_port_line;
1694         }
1695 
1696         ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1697         if (ret < 0)
1698                 goto err_rs485;
1699 
1700         sprintf(up->name, "OMAP UART%d", up->port.line);
1701         up->port.mapbase = mem->start;
1702         up->port.membase = base;
1703         up->port.flags = omap_up_info->flags;
1704         up->port.uartclk = omap_up_info->uartclk;
1705         if (!up->port.uartclk) {
1706                 up->port.uartclk = DEFAULT_CLK_SPEED;
1707                 dev_warn(&pdev->dev,
1708                          "No clock speed specified: using default: %d\n",
1709                          DEFAULT_CLK_SPEED);
1710         }
1711 
1712         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1713         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1714         pm_qos_add_request(&up->pm_qos_request,
1715                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1716         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1717 
1718         platform_set_drvdata(pdev, up);
1719         if (omap_up_info->autosuspend_timeout == 0)
1720                 omap_up_info->autosuspend_timeout = -1;
1721 
1722         device_init_wakeup(up->dev, true);
1723         pm_runtime_use_autosuspend(&pdev->dev);
1724         pm_runtime_set_autosuspend_delay(&pdev->dev,
1725                         omap_up_info->autosuspend_timeout);
1726 
1727         pm_runtime_irq_safe(&pdev->dev);
1728         pm_runtime_enable(&pdev->dev);
1729 
1730         pm_runtime_get_sync(&pdev->dev);
1731 
1732         omap_serial_fill_features_erratas(up);
1733 
1734         ui[up->port.line] = up;
1735         serial_omap_add_console_port(up);
1736 
1737         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1738         if (ret != 0)
1739                 goto err_add_port;
1740 
1741         pm_runtime_mark_last_busy(up->dev);
1742         pm_runtime_put_autosuspend(up->dev);
1743         return 0;
1744 
1745 err_add_port:
1746         pm_runtime_put(&pdev->dev);
1747         pm_runtime_disable(&pdev->dev);
1748 err_rs485:
1749 err_port_line:
1750         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1751                                 pdev->id, __func__, ret);
1752         return ret;
1753 }
1754 
1755 static int serial_omap_remove(struct platform_device *dev)
1756 {
1757         struct uart_omap_port *up = platform_get_drvdata(dev);
1758 
1759         pm_runtime_put_sync(up->dev);
1760         pm_runtime_disable(up->dev);
1761         uart_remove_one_port(&serial_omap_reg, &up->port);
1762         pm_qos_remove_request(&up->pm_qos_request);
1763         device_init_wakeup(&dev->dev, false);
1764 
1765         return 0;
1766 }
1767 
1768 /*
1769  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1770  * The access to uart register after MDR1 Access
1771  * causes UART to corrupt data.
1772  *
1773  * Need a delay =
1774  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1775  * give 10 times as much
1776  */
1777 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1778 {
1779         u8 timeout = 255;
1780 
1781         serial_out(up, UART_OMAP_MDR1, mdr1);
1782         udelay(2);
1783         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1784                         UART_FCR_CLEAR_RCVR);
1785         /*
1786          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1787          * TX_FIFO_E bit is 1.
1788          */
1789         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1790                                 (UART_LSR_THRE | UART_LSR_DR))) {
1791                 timeout--;
1792                 if (!timeout) {
1793                         /* Should *never* happen. we warn and carry on */
1794                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1795                                                 serial_in(up, UART_LSR));
1796                         break;
1797                 }
1798                 udelay(1);
1799         }
1800 }
1801 
1802 #ifdef CONFIG_PM_RUNTIME
1803 static void serial_omap_restore_context(struct uart_omap_port *up)
1804 {
1805         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1806                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1807         else
1808                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1809 
1810         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1811         serial_out(up, UART_EFR, UART_EFR_ECB);
1812         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1813         serial_out(up, UART_IER, 0x0);
1814         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1815         serial_out(up, UART_DLL, up->dll);
1816         serial_out(up, UART_DLM, up->dlh);
1817         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1818         serial_out(up, UART_IER, up->ier);
1819         serial_out(up, UART_FCR, up->fcr);
1820         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1821         serial_out(up, UART_MCR, up->mcr);
1822         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1823         serial_out(up, UART_OMAP_SCR, up->scr);
1824         serial_out(up, UART_EFR, up->efr);
1825         serial_out(up, UART_LCR, up->lcr);
1826         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1827                 serial_omap_mdr1_errataset(up, up->mdr1);
1828         else
1829                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1830         serial_out(up, UART_OMAP_WER, up->wer);
1831 }
1832 
1833 static int serial_omap_runtime_suspend(struct device *dev)
1834 {
1835         struct uart_omap_port *up = dev_get_drvdata(dev);
1836 
1837         if (!up)
1838                 return -EINVAL;
1839 
1840         /*
1841         * When using 'no_console_suspend', the console UART must not be
1842         * suspended. Since driver suspend is managed by runtime suspend,
1843         * preventing runtime suspend (by returning error) will keep device
1844         * active during suspend.
1845         */
1846         if (up->is_suspending && !console_suspend_enabled &&
1847             uart_console(&up->port))
1848                 return -EBUSY;
1849 
1850         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1851 
1852         serial_omap_enable_wakeup(up, true);
1853 
1854         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1855         schedule_work(&up->qos_work);
1856 
1857         return 0;
1858 }
1859 
1860 static int serial_omap_runtime_resume(struct device *dev)
1861 {
1862         struct uart_omap_port *up = dev_get_drvdata(dev);
1863 
1864         int loss_cnt = serial_omap_get_context_loss_count(up);
1865 
1866         serial_omap_enable_wakeup(up, false);
1867 
1868         if (loss_cnt < 0) {
1869                 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1870                         loss_cnt);
1871                 serial_omap_restore_context(up);
1872         } else if (up->context_loss_cnt != loss_cnt) {
1873                 serial_omap_restore_context(up);
1874         }
1875         up->latency = up->calc_latency;
1876         schedule_work(&up->qos_work);
1877 
1878         return 0;
1879 }
1880 #endif
1881 
1882 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1883         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1884         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1885                                 serial_omap_runtime_resume, NULL)
1886         .prepare        = serial_omap_prepare,
1887         .complete       = serial_omap_complete,
1888 };
1889 
1890 #if defined(CONFIG_OF)
1891 static const struct of_device_id omap_serial_of_match[] = {
1892         { .compatible = "ti,omap2-uart" },
1893         { .compatible = "ti,omap3-uart" },
1894         { .compatible = "ti,omap4-uart" },
1895         {},
1896 };
1897 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1898 #endif
1899 
1900 static struct platform_driver serial_omap_driver = {
1901         .probe          = serial_omap_probe,
1902         .remove         = serial_omap_remove,
1903         .driver         = {
1904                 .name   = DRIVER_NAME,
1905                 .pm     = &serial_omap_dev_pm_ops,
1906                 .of_match_table = of_match_ptr(omap_serial_of_match),
1907         },
1908 };
1909 
1910 static int __init serial_omap_init(void)
1911 {
1912         int ret;
1913 
1914         ret = uart_register_driver(&serial_omap_reg);
1915         if (ret != 0)
1916                 return ret;
1917         ret = platform_driver_register(&serial_omap_driver);
1918         if (ret != 0)
1919                 uart_unregister_driver(&serial_omap_reg);
1920         return ret;
1921 }
1922 
1923 static void __exit serial_omap_exit(void)
1924 {
1925         platform_driver_unregister(&serial_omap_driver);
1926         uart_unregister_driver(&serial_omap_reg);
1927 }
1928 
1929 module_init(serial_omap_init);
1930 module_exit(serial_omap_exit);
1931 
1932 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1933 MODULE_LICENSE("GPL");
1934 MODULE_AUTHOR("Texas Instruments Inc");
1935 

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