Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/tty/serial/omap-serial.c

  1 /*
  2  * Driver for OMAP-UART controller.
  3  * Based on drivers/serial/8250.c
  4  *
  5  * Copyright (C) 2010 Texas Instruments.
  6  *
  7  * Authors:
  8  *      Govindraj R     <govindraj.raja@ti.com>
  9  *      Thara Gopinath  <thara@ti.com>
 10  *
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License as published by
 13  * the Free Software Foundation; either version 2 of the License, or
 14  * (at your option) any later version.
 15  *
 16  * Note: This driver is made separate from 8250 driver as we cannot
 17  * over load 8250 driver with omap platform specific configuration for
 18  * features like DMA, it makes easier to implement features like DMA and
 19  * hardware flow control and software flow control configuration with
 20  * this driver as required for the omap-platform.
 21  */
 22 
 23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 24 #define SUPPORT_SYSRQ
 25 #endif
 26 
 27 #include <linux/module.h>
 28 #include <linux/init.h>
 29 #include <linux/console.h>
 30 #include <linux/serial_reg.h>
 31 #include <linux/delay.h>
 32 #include <linux/slab.h>
 33 #include <linux/tty.h>
 34 #include <linux/tty_flip.h>
 35 #include <linux/platform_device.h>
 36 #include <linux/io.h>
 37 #include <linux/clk.h>
 38 #include <linux/serial_core.h>
 39 #include <linux/irq.h>
 40 #include <linux/pm_runtime.h>
 41 #include <linux/of.h>
 42 #include <linux/of_irq.h>
 43 #include <linux/gpio.h>
 44 #include <linux/of_gpio.h>
 45 #include <linux/platform_data/serial-omap.h>
 46 
 47 #include <dt-bindings/gpio/gpio.h>
 48 
 49 #define OMAP_MAX_HSUART_PORTS   6
 50 
 51 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
 52 
 53 #define OMAP_UART_REV_42 0x0402
 54 #define OMAP_UART_REV_46 0x0406
 55 #define OMAP_UART_REV_52 0x0502
 56 #define OMAP_UART_REV_63 0x0603
 57 
 58 #define OMAP_UART_TX_WAKEUP_EN          BIT(7)
 59 
 60 /* Feature flags */
 61 #define OMAP_UART_WER_HAS_TX_WAKEUP     BIT(0)
 62 
 63 #define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
 64 #define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
 65 
 66 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
 67 
 68 /* SCR register bitmasks */
 69 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
 70 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK               (1 << 6)
 71 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
 72 
 73 /* FCR register bitmasks */
 74 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
 75 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
 76 
 77 /* MVR register bitmasks */
 78 #define OMAP_UART_MVR_SCHEME_SHIFT      30
 79 
 80 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
 81 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
 82 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
 83 
 84 #define OMAP_UART_MVR_MAJ_MASK          0x700
 85 #define OMAP_UART_MVR_MAJ_SHIFT         8
 86 #define OMAP_UART_MVR_MIN_MASK          0x3f
 87 
 88 #define OMAP_UART_DMA_CH_FREE   -1
 89 
 90 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
 91 #define OMAP_MODE13X_SPEED      230400
 92 
 93 /* WER = 0x7F
 94  * Enable module level wakeup in WER reg
 95  */
 96 #define OMAP_UART_WER_MOD_WKUP  0X7F
 97 
 98 /* Enable XON/XOFF flow control on output */
 99 #define OMAP_UART_SW_TX         0x08
100 
101 /* Enable XON/XOFF flow control on input */
102 #define OMAP_UART_SW_RX         0x02
103 
104 #define OMAP_UART_SW_CLR        0xF0
105 
106 #define OMAP_UART_TCR_TRIG      0x0F
107 
108 struct uart_omap_dma {
109         u8                      uart_dma_tx;
110         u8                      uart_dma_rx;
111         int                     rx_dma_channel;
112         int                     tx_dma_channel;
113         dma_addr_t              rx_buf_dma_phys;
114         dma_addr_t              tx_buf_dma_phys;
115         unsigned int            uart_base;
116         /*
117          * Buffer for rx dma.It is not required for tx because the buffer
118          * comes from port structure.
119          */
120         unsigned char           *rx_buf;
121         unsigned int            prev_rx_dma_pos;
122         int                     tx_buf_size;
123         int                     tx_dma_used;
124         int                     rx_dma_used;
125         spinlock_t              tx_lock;
126         spinlock_t              rx_lock;
127         /* timer to poll activity on rx dma */
128         struct timer_list       rx_timer;
129         unsigned int            rx_buf_size;
130         unsigned int            rx_poll_rate;
131         unsigned int            rx_timeout;
132 };
133 
134 struct uart_omap_port {
135         struct uart_port        port;
136         struct uart_omap_dma    uart_dma;
137         struct device           *dev;
138         int                     wakeirq;
139 
140         unsigned char           ier;
141         unsigned char           lcr;
142         unsigned char           mcr;
143         unsigned char           fcr;
144         unsigned char           efr;
145         unsigned char           dll;
146         unsigned char           dlh;
147         unsigned char           mdr1;
148         unsigned char           scr;
149         unsigned char           wer;
150 
151         int                     use_dma;
152         /*
153          * Some bits in registers are cleared on a read, so they must
154          * be saved whenever the register is read but the bits will not
155          * be immediately processed.
156          */
157         unsigned int            lsr_break_flag;
158         unsigned char           msr_saved_flags;
159         char                    name[20];
160         unsigned long           port_activity;
161         int                     context_loss_cnt;
162         u32                     errata;
163         u8                      wakeups_enabled;
164         u32                     features;
165 
166         int                     DTR_gpio;
167         int                     DTR_inverted;
168         int                     DTR_active;
169 
170         struct serial_rs485     rs485;
171         int                     rts_gpio;
172 
173         struct pm_qos_request   pm_qos_request;
174         u32                     latency;
175         u32                     calc_latency;
176         struct work_struct      qos_work;
177         bool                    is_suspending;
178 };
179 
180 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
181 
182 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
183 
184 /* Forward declaration of functions */
185 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
186 
187 static struct workqueue_struct *serial_omap_uart_wq;
188 
189 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
190 {
191         offset <<= up->port.regshift;
192         return readw(up->port.membase + offset);
193 }
194 
195 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
196 {
197         offset <<= up->port.regshift;
198         writew(value, up->port.membase + offset);
199 }
200 
201 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
202 {
203         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
204         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
205                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
206         serial_out(up, UART_FCR, 0);
207 }
208 
209 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
210 {
211         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
212 
213         if (!pdata || !pdata->get_context_loss_count)
214                 return -EINVAL;
215 
216         return pdata->get_context_loss_count(up->dev);
217 }
218 
219 static inline void serial_omap_enable_wakeirq(struct uart_omap_port *up,
220                                        bool enable)
221 {
222         if (!up->wakeirq)
223                 return;
224 
225         if (enable)
226                 enable_irq(up->wakeirq);
227         else
228                 disable_irq_nosync(up->wakeirq);
229 }
230 
231 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
232 {
233         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
234 
235         if (enable == up->wakeups_enabled)
236                 return;
237 
238         serial_omap_enable_wakeirq(up, enable);
239         up->wakeups_enabled = enable;
240 
241         if (!pdata || !pdata->enable_wakeup)
242                 return;
243 
244         pdata->enable_wakeup(up->dev, enable);
245 }
246 
247 /*
248  * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
249  * @port: uart port info
250  * @baud: baudrate for which mode needs to be determined
251  *
252  * Returns true if baud rate is MODE16X and false if MODE13X
253  * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
254  * and Error Rates" determines modes not for all common baud rates.
255  * E.g. for 1000000 baud rate mode must be 16x, but according to that
256  * table it's determined as 13x.
257  */
258 static bool
259 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
260 {
261         unsigned int n13 = port->uartclk / (13 * baud);
262         unsigned int n16 = port->uartclk / (16 * baud);
263         int baudAbsDiff13 = baud - (port->uartclk / (13 * n13));
264         int baudAbsDiff16 = baud - (port->uartclk / (16 * n16));
265         if (baudAbsDiff13 < 0)
266                 baudAbsDiff13 = -baudAbsDiff13;
267         if (baudAbsDiff16 < 0)
268                 baudAbsDiff16 = -baudAbsDiff16;
269 
270         return (baudAbsDiff13 >= baudAbsDiff16);
271 }
272 
273 /*
274  * serial_omap_get_divisor - calculate divisor value
275  * @port: uart port info
276  * @baud: baudrate for which divisor needs to be calculated.
277  */
278 static unsigned int
279 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
280 {
281         unsigned int mode;
282 
283         if (!serial_omap_baud_is_mode16(port, baud))
284                 mode = 13;
285         else
286                 mode = 16;
287         return port->uartclk/(mode * baud);
288 }
289 
290 static void serial_omap_enable_ms(struct uart_port *port)
291 {
292         struct uart_omap_port *up = to_uart_omap_port(port);
293 
294         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
295 
296         pm_runtime_get_sync(up->dev);
297         up->ier |= UART_IER_MSI;
298         serial_out(up, UART_IER, up->ier);
299         pm_runtime_mark_last_busy(up->dev);
300         pm_runtime_put_autosuspend(up->dev);
301 }
302 
303 static void serial_omap_stop_tx(struct uart_port *port)
304 {
305         struct uart_omap_port *up = to_uart_omap_port(port);
306         int res;
307 
308         pm_runtime_get_sync(up->dev);
309 
310         /* Handle RS-485 */
311         if (up->rs485.flags & SER_RS485_ENABLED) {
312                 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
313                         /* THR interrupt is fired when both TX FIFO and TX
314                          * shift register are empty. This means there's nothing
315                          * left to transmit now, so make sure the THR interrupt
316                          * is fired when TX FIFO is below the trigger level,
317                          * disable THR interrupts and toggle the RS-485 GPIO
318                          * data direction pin if needed.
319                          */
320                         up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
321                         serial_out(up, UART_OMAP_SCR, up->scr);
322                         res = (up->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
323                         if (gpio_get_value(up->rts_gpio) != res) {
324                                 if (up->rs485.delay_rts_after_send > 0)
325                                         mdelay(up->rs485.delay_rts_after_send);
326                                 gpio_set_value(up->rts_gpio, res);
327                         }
328                 } else {
329                         /* We're asked to stop, but there's still stuff in the
330                          * UART FIFO, so make sure the THR interrupt is fired
331                          * when both TX FIFO and TX shift register are empty.
332                          * The next THR interrupt (if no transmission is started
333                          * in the meantime) will indicate the end of a
334                          * transmission. Therefore we _don't_ disable THR
335                          * interrupts in this situation.
336                          */
337                         up->scr |= OMAP_UART_SCR_TX_EMPTY;
338                         serial_out(up, UART_OMAP_SCR, up->scr);
339                         return;
340                 }
341         }
342 
343         if (up->ier & UART_IER_THRI) {
344                 up->ier &= ~UART_IER_THRI;
345                 serial_out(up, UART_IER, up->ier);
346         }
347 
348         if ((up->rs485.flags & SER_RS485_ENABLED) &&
349             !(up->rs485.flags & SER_RS485_RX_DURING_TX)) {
350                 /*
351                  * Empty the RX FIFO, we are not interested in anything
352                  * received during the half-duplex transmission.
353                  */
354                 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
355                 /* Re-enable RX interrupts */
356                 up->ier |= UART_IER_RLSI | UART_IER_RDI;
357                 up->port.read_status_mask |= UART_LSR_DR;
358                 serial_out(up, UART_IER, up->ier);
359         }
360 
361         pm_runtime_mark_last_busy(up->dev);
362         pm_runtime_put_autosuspend(up->dev);
363 }
364 
365 static void serial_omap_stop_rx(struct uart_port *port)
366 {
367         struct uart_omap_port *up = to_uart_omap_port(port);
368 
369         pm_runtime_get_sync(up->dev);
370         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
371         up->port.read_status_mask &= ~UART_LSR_DR;
372         serial_out(up, UART_IER, up->ier);
373         pm_runtime_mark_last_busy(up->dev);
374         pm_runtime_put_autosuspend(up->dev);
375 }
376 
377 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
378 {
379         struct circ_buf *xmit = &up->port.state->xmit;
380         int count;
381 
382         if (up->port.x_char) {
383                 serial_out(up, UART_TX, up->port.x_char);
384                 up->port.icount.tx++;
385                 up->port.x_char = 0;
386                 return;
387         }
388         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
389                 serial_omap_stop_tx(&up->port);
390                 return;
391         }
392         count = up->port.fifosize / 4;
393         do {
394                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
395                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
396                 up->port.icount.tx++;
397                 if (uart_circ_empty(xmit))
398                         break;
399         } while (--count > 0);
400 
401         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
402                 spin_unlock(&up->port.lock);
403                 uart_write_wakeup(&up->port);
404                 spin_lock(&up->port.lock);
405         }
406 
407         if (uart_circ_empty(xmit))
408                 serial_omap_stop_tx(&up->port);
409 }
410 
411 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
412 {
413         if (!(up->ier & UART_IER_THRI)) {
414                 up->ier |= UART_IER_THRI;
415                 serial_out(up, UART_IER, up->ier);
416         }
417 }
418 
419 static void serial_omap_start_tx(struct uart_port *port)
420 {
421         struct uart_omap_port *up = to_uart_omap_port(port);
422         int res;
423 
424         pm_runtime_get_sync(up->dev);
425 
426         /* Handle RS-485 */
427         if (up->rs485.flags & SER_RS485_ENABLED) {
428                 /* Fire THR interrupts when FIFO is below trigger level */
429                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
430                 serial_out(up, UART_OMAP_SCR, up->scr);
431 
432                 /* if rts not already enabled */
433                 res = (up->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
434                 if (gpio_get_value(up->rts_gpio) != res) {
435                         gpio_set_value(up->rts_gpio, res);
436                         if (up->rs485.delay_rts_before_send > 0)
437                                 mdelay(up->rs485.delay_rts_before_send);
438                 }
439         }
440 
441         if ((up->rs485.flags & SER_RS485_ENABLED) &&
442             !(up->rs485.flags & SER_RS485_RX_DURING_TX))
443                 serial_omap_stop_rx(port);
444 
445         serial_omap_enable_ier_thri(up);
446         pm_runtime_mark_last_busy(up->dev);
447         pm_runtime_put_autosuspend(up->dev);
448 }
449 
450 static void serial_omap_throttle(struct uart_port *port)
451 {
452         struct uart_omap_port *up = to_uart_omap_port(port);
453         unsigned long flags;
454 
455         pm_runtime_get_sync(up->dev);
456         spin_lock_irqsave(&up->port.lock, flags);
457         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
458         serial_out(up, UART_IER, up->ier);
459         spin_unlock_irqrestore(&up->port.lock, flags);
460         pm_runtime_mark_last_busy(up->dev);
461         pm_runtime_put_autosuspend(up->dev);
462 }
463 
464 static void serial_omap_unthrottle(struct uart_port *port)
465 {
466         struct uart_omap_port *up = to_uart_omap_port(port);
467         unsigned long flags;
468 
469         pm_runtime_get_sync(up->dev);
470         spin_lock_irqsave(&up->port.lock, flags);
471         up->ier |= UART_IER_RLSI | UART_IER_RDI;
472         serial_out(up, UART_IER, up->ier);
473         spin_unlock_irqrestore(&up->port.lock, flags);
474         pm_runtime_mark_last_busy(up->dev);
475         pm_runtime_put_autosuspend(up->dev);
476 }
477 
478 static unsigned int check_modem_status(struct uart_omap_port *up)
479 {
480         unsigned int status;
481 
482         status = serial_in(up, UART_MSR);
483         status |= up->msr_saved_flags;
484         up->msr_saved_flags = 0;
485         if ((status & UART_MSR_ANY_DELTA) == 0)
486                 return status;
487 
488         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
489             up->port.state != NULL) {
490                 if (status & UART_MSR_TERI)
491                         up->port.icount.rng++;
492                 if (status & UART_MSR_DDSR)
493                         up->port.icount.dsr++;
494                 if (status & UART_MSR_DDCD)
495                         uart_handle_dcd_change
496                                 (&up->port, status & UART_MSR_DCD);
497                 if (status & UART_MSR_DCTS)
498                         uart_handle_cts_change
499                                 (&up->port, status & UART_MSR_CTS);
500                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
501         }
502 
503         return status;
504 }
505 
506 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
507 {
508         unsigned int flag;
509         unsigned char ch = 0;
510 
511         if (likely(lsr & UART_LSR_DR))
512                 ch = serial_in(up, UART_RX);
513 
514         up->port.icount.rx++;
515         flag = TTY_NORMAL;
516 
517         if (lsr & UART_LSR_BI) {
518                 flag = TTY_BREAK;
519                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
520                 up->port.icount.brk++;
521                 /*
522                  * We do the SysRQ and SAK checking
523                  * here because otherwise the break
524                  * may get masked by ignore_status_mask
525                  * or read_status_mask.
526                  */
527                 if (uart_handle_break(&up->port))
528                         return;
529 
530         }
531 
532         if (lsr & UART_LSR_PE) {
533                 flag = TTY_PARITY;
534                 up->port.icount.parity++;
535         }
536 
537         if (lsr & UART_LSR_FE) {
538                 flag = TTY_FRAME;
539                 up->port.icount.frame++;
540         }
541 
542         if (lsr & UART_LSR_OE)
543                 up->port.icount.overrun++;
544 
545 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
546         if (up->port.line == up->port.cons->index) {
547                 /* Recover the break flag from console xmit */
548                 lsr |= up->lsr_break_flag;
549         }
550 #endif
551         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
552 }
553 
554 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
555 {
556         unsigned char ch = 0;
557         unsigned int flag;
558 
559         if (!(lsr & UART_LSR_DR))
560                 return;
561 
562         ch = serial_in(up, UART_RX);
563         flag = TTY_NORMAL;
564         up->port.icount.rx++;
565 
566         if (uart_handle_sysrq_char(&up->port, ch))
567                 return;
568 
569         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
570 }
571 
572 /**
573  * serial_omap_irq() - This handles the interrupt from one port
574  * @irq: uart port irq number
575  * @dev_id: uart port info
576  */
577 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
578 {
579         struct uart_omap_port *up = dev_id;
580         unsigned int iir, lsr;
581         unsigned int type;
582         irqreturn_t ret = IRQ_NONE;
583         int max_count = 256;
584 
585         spin_lock(&up->port.lock);
586         pm_runtime_get_sync(up->dev);
587 
588         do {
589                 iir = serial_in(up, UART_IIR);
590                 if (iir & UART_IIR_NO_INT)
591                         break;
592 
593                 ret = IRQ_HANDLED;
594                 lsr = serial_in(up, UART_LSR);
595 
596                 /* extract IRQ type from IIR register */
597                 type = iir & 0x3e;
598 
599                 switch (type) {
600                 case UART_IIR_MSI:
601                         check_modem_status(up);
602                         break;
603                 case UART_IIR_THRI:
604                         transmit_chars(up, lsr);
605                         break;
606                 case UART_IIR_RX_TIMEOUT:
607                         /* FALLTHROUGH */
608                 case UART_IIR_RDI:
609                         serial_omap_rdi(up, lsr);
610                         break;
611                 case UART_IIR_RLSI:
612                         serial_omap_rlsi(up, lsr);
613                         break;
614                 case UART_IIR_CTS_RTS_DSR:
615                         /* simply try again */
616                         break;
617                 case UART_IIR_XOFF:
618                         /* FALLTHROUGH */
619                 default:
620                         break;
621                 }
622         } while (!(iir & UART_IIR_NO_INT) && max_count--);
623 
624         spin_unlock(&up->port.lock);
625 
626         tty_flip_buffer_push(&up->port.state->port);
627 
628         pm_runtime_mark_last_busy(up->dev);
629         pm_runtime_put_autosuspend(up->dev);
630         up->port_activity = jiffies;
631 
632         return ret;
633 }
634 
635 static unsigned int serial_omap_tx_empty(struct uart_port *port)
636 {
637         struct uart_omap_port *up = to_uart_omap_port(port);
638         unsigned long flags = 0;
639         unsigned int ret = 0;
640 
641         pm_runtime_get_sync(up->dev);
642         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
643         spin_lock_irqsave(&up->port.lock, flags);
644         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
645         spin_unlock_irqrestore(&up->port.lock, flags);
646         pm_runtime_mark_last_busy(up->dev);
647         pm_runtime_put_autosuspend(up->dev);
648         return ret;
649 }
650 
651 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
652 {
653         struct uart_omap_port *up = to_uart_omap_port(port);
654         unsigned int status;
655         unsigned int ret = 0;
656 
657         pm_runtime_get_sync(up->dev);
658         status = check_modem_status(up);
659         pm_runtime_mark_last_busy(up->dev);
660         pm_runtime_put_autosuspend(up->dev);
661 
662         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
663 
664         if (status & UART_MSR_DCD)
665                 ret |= TIOCM_CAR;
666         if (status & UART_MSR_RI)
667                 ret |= TIOCM_RNG;
668         if (status & UART_MSR_DSR)
669                 ret |= TIOCM_DSR;
670         if (status & UART_MSR_CTS)
671                 ret |= TIOCM_CTS;
672         return ret;
673 }
674 
675 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
676 {
677         struct uart_omap_port *up = to_uart_omap_port(port);
678         unsigned char mcr = 0, old_mcr;
679 
680         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
681         if (mctrl & TIOCM_RTS)
682                 mcr |= UART_MCR_RTS;
683         if (mctrl & TIOCM_DTR)
684                 mcr |= UART_MCR_DTR;
685         if (mctrl & TIOCM_OUT1)
686                 mcr |= UART_MCR_OUT1;
687         if (mctrl & TIOCM_OUT2)
688                 mcr |= UART_MCR_OUT2;
689         if (mctrl & TIOCM_LOOP)
690                 mcr |= UART_MCR_LOOP;
691 
692         pm_runtime_get_sync(up->dev);
693         old_mcr = serial_in(up, UART_MCR);
694         old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
695                      UART_MCR_DTR | UART_MCR_RTS);
696         up->mcr = old_mcr | mcr;
697         serial_out(up, UART_MCR, up->mcr);
698         pm_runtime_mark_last_busy(up->dev);
699         pm_runtime_put_autosuspend(up->dev);
700 
701         if (gpio_is_valid(up->DTR_gpio) &&
702             !!(mctrl & TIOCM_DTR) != up->DTR_active) {
703                 up->DTR_active = !up->DTR_active;
704                 if (gpio_cansleep(up->DTR_gpio))
705                         schedule_work(&up->qos_work);
706                 else
707                         gpio_set_value(up->DTR_gpio,
708                                        up->DTR_active != up->DTR_inverted);
709         }
710 }
711 
712 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
713 {
714         struct uart_omap_port *up = to_uart_omap_port(port);
715         unsigned long flags = 0;
716 
717         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
718         pm_runtime_get_sync(up->dev);
719         spin_lock_irqsave(&up->port.lock, flags);
720         if (break_state == -1)
721                 up->lcr |= UART_LCR_SBC;
722         else
723                 up->lcr &= ~UART_LCR_SBC;
724         serial_out(up, UART_LCR, up->lcr);
725         spin_unlock_irqrestore(&up->port.lock, flags);
726         pm_runtime_mark_last_busy(up->dev);
727         pm_runtime_put_autosuspend(up->dev);
728 }
729 
730 static int serial_omap_startup(struct uart_port *port)
731 {
732         struct uart_omap_port *up = to_uart_omap_port(port);
733         unsigned long flags = 0;
734         int retval;
735 
736         /*
737          * Allocate the IRQ
738          */
739         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
740                                 up->name, up);
741         if (retval)
742                 return retval;
743 
744         /* Optional wake-up IRQ */
745         if (up->wakeirq) {
746                 retval = request_irq(up->wakeirq, serial_omap_irq,
747                                      up->port.irqflags, up->name, up);
748                 if (retval) {
749                         free_irq(up->port.irq, up);
750                         return retval;
751                 }
752                 disable_irq(up->wakeirq);
753         }
754 
755         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
756 
757         pm_runtime_get_sync(up->dev);
758         /*
759          * Clear the FIFO buffers and disable them.
760          * (they will be reenabled in set_termios())
761          */
762         serial_omap_clear_fifos(up);
763         /* For Hardware flow control */
764         serial_out(up, UART_MCR, UART_MCR_RTS);
765 
766         /*
767          * Clear the interrupt registers.
768          */
769         (void) serial_in(up, UART_LSR);
770         if (serial_in(up, UART_LSR) & UART_LSR_DR)
771                 (void) serial_in(up, UART_RX);
772         (void) serial_in(up, UART_IIR);
773         (void) serial_in(up, UART_MSR);
774 
775         /*
776          * Now, initialize the UART
777          */
778         serial_out(up, UART_LCR, UART_LCR_WLEN8);
779         spin_lock_irqsave(&up->port.lock, flags);
780         /*
781          * Most PC uarts need OUT2 raised to enable interrupts.
782          */
783         up->port.mctrl |= TIOCM_OUT2;
784         serial_omap_set_mctrl(&up->port, up->port.mctrl);
785         spin_unlock_irqrestore(&up->port.lock, flags);
786 
787         up->msr_saved_flags = 0;
788         /*
789          * Finally, enable interrupts. Note: Modem status interrupts
790          * are set via set_termios(), which will be occurring imminently
791          * anyway, so we don't enable them here.
792          */
793         up->ier = UART_IER_RLSI | UART_IER_RDI;
794         serial_out(up, UART_IER, up->ier);
795 
796         /* Enable module level wake up */
797         up->wer = OMAP_UART_WER_MOD_WKUP;
798         if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
799                 up->wer |= OMAP_UART_TX_WAKEUP_EN;
800 
801         serial_out(up, UART_OMAP_WER, up->wer);
802 
803         pm_runtime_mark_last_busy(up->dev);
804         pm_runtime_put_autosuspend(up->dev);
805         up->port_activity = jiffies;
806         return 0;
807 }
808 
809 static void serial_omap_shutdown(struct uart_port *port)
810 {
811         struct uart_omap_port *up = to_uart_omap_port(port);
812         unsigned long flags = 0;
813 
814         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
815 
816         pm_runtime_get_sync(up->dev);
817         /*
818          * Disable interrupts from this port
819          */
820         up->ier = 0;
821         serial_out(up, UART_IER, 0);
822 
823         spin_lock_irqsave(&up->port.lock, flags);
824         up->port.mctrl &= ~TIOCM_OUT2;
825         serial_omap_set_mctrl(&up->port, up->port.mctrl);
826         spin_unlock_irqrestore(&up->port.lock, flags);
827 
828         /*
829          * Disable break condition and FIFOs
830          */
831         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
832         serial_omap_clear_fifos(up);
833 
834         /*
835          * Read data port to reset things, and then free the irq
836          */
837         if (serial_in(up, UART_LSR) & UART_LSR_DR)
838                 (void) serial_in(up, UART_RX);
839 
840         pm_runtime_mark_last_busy(up->dev);
841         pm_runtime_put_autosuspend(up->dev);
842         free_irq(up->port.irq, up);
843         if (up->wakeirq)
844                 free_irq(up->wakeirq, up);
845 }
846 
847 static void serial_omap_uart_qos_work(struct work_struct *work)
848 {
849         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
850                                                 qos_work);
851 
852         pm_qos_update_request(&up->pm_qos_request, up->latency);
853         if (gpio_is_valid(up->DTR_gpio))
854                 gpio_set_value_cansleep(up->DTR_gpio,
855                                         up->DTR_active != up->DTR_inverted);
856 }
857 
858 static void
859 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
860                         struct ktermios *old)
861 {
862         struct uart_omap_port *up = to_uart_omap_port(port);
863         unsigned char cval = 0;
864         unsigned long flags = 0;
865         unsigned int baud, quot;
866 
867         switch (termios->c_cflag & CSIZE) {
868         case CS5:
869                 cval = UART_LCR_WLEN5;
870                 break;
871         case CS6:
872                 cval = UART_LCR_WLEN6;
873                 break;
874         case CS7:
875                 cval = UART_LCR_WLEN7;
876                 break;
877         default:
878         case CS8:
879                 cval = UART_LCR_WLEN8;
880                 break;
881         }
882 
883         if (termios->c_cflag & CSTOPB)
884                 cval |= UART_LCR_STOP;
885         if (termios->c_cflag & PARENB)
886                 cval |= UART_LCR_PARITY;
887         if (!(termios->c_cflag & PARODD))
888                 cval |= UART_LCR_EPAR;
889         if (termios->c_cflag & CMSPAR)
890                 cval |= UART_LCR_SPAR;
891 
892         /*
893          * Ask the core to calculate the divisor for us.
894          */
895 
896         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
897         quot = serial_omap_get_divisor(port, baud);
898 
899         /* calculate wakeup latency constraint */
900         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
901         up->latency = up->calc_latency;
902         schedule_work(&up->qos_work);
903 
904         up->dll = quot & 0xff;
905         up->dlh = quot >> 8;
906         up->mdr1 = UART_OMAP_MDR1_DISABLE;
907 
908         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
909                         UART_FCR_ENABLE_FIFO;
910 
911         /*
912          * Ok, we're now changing the port state. Do it with
913          * interrupts disabled.
914          */
915         pm_runtime_get_sync(up->dev);
916         spin_lock_irqsave(&up->port.lock, flags);
917 
918         /*
919          * Update the per-port timeout.
920          */
921         uart_update_timeout(port, termios->c_cflag, baud);
922 
923         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
924         if (termios->c_iflag & INPCK)
925                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
926         if (termios->c_iflag & (BRKINT | PARMRK))
927                 up->port.read_status_mask |= UART_LSR_BI;
928 
929         /*
930          * Characters to ignore
931          */
932         up->port.ignore_status_mask = 0;
933         if (termios->c_iflag & IGNPAR)
934                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
935         if (termios->c_iflag & IGNBRK) {
936                 up->port.ignore_status_mask |= UART_LSR_BI;
937                 /*
938                  * If we're ignoring parity and break indicators,
939                  * ignore overruns too (for real raw support).
940                  */
941                 if (termios->c_iflag & IGNPAR)
942                         up->port.ignore_status_mask |= UART_LSR_OE;
943         }
944 
945         /*
946          * ignore all characters if CREAD is not set
947          */
948         if ((termios->c_cflag & CREAD) == 0)
949                 up->port.ignore_status_mask |= UART_LSR_DR;
950 
951         /*
952          * Modem status interrupts
953          */
954         up->ier &= ~UART_IER_MSI;
955         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
956                 up->ier |= UART_IER_MSI;
957         serial_out(up, UART_IER, up->ier);
958         serial_out(up, UART_LCR, cval);         /* reset DLAB */
959         up->lcr = cval;
960         up->scr = 0;
961 
962         /* FIFOs and DMA Settings */
963 
964         /* FCR can be changed only when the
965          * baud clock is not running
966          * DLL_REG and DLH_REG set to 0.
967          */
968         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
969         serial_out(up, UART_DLL, 0);
970         serial_out(up, UART_DLM, 0);
971         serial_out(up, UART_LCR, 0);
972 
973         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
974 
975         up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
976         up->efr &= ~UART_EFR_SCD;
977         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
978 
979         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
980         up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
981         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
982         /* FIFO ENABLE, DMA MODE */
983 
984         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
985         /*
986          * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
987          * sets Enables the granularity of 1 for TRIGGER RX
988          * level. Along with setting RX FIFO trigger level
989          * to 1 (as noted below, 16 characters) and TLR[3:0]
990          * to zero this will result RX FIFO threshold level
991          * to 1 character, instead of 16 as noted in comment
992          * below.
993          */
994 
995         /* Set receive FIFO threshold to 16 characters and
996          * transmit FIFO threshold to 32 spaces
997          */
998         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
999         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
1000         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
1001                 UART_FCR_ENABLE_FIFO;
1002 
1003         serial_out(up, UART_FCR, up->fcr);
1004         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1005 
1006         serial_out(up, UART_OMAP_SCR, up->scr);
1007 
1008         /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
1009         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1010         serial_out(up, UART_MCR, up->mcr);
1011         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1012         serial_out(up, UART_EFR, up->efr);
1013         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1014 
1015         /* Protocol, Baud Rate, and Interrupt Settings */
1016 
1017         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1018                 serial_omap_mdr1_errataset(up, up->mdr1);
1019         else
1020                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1021 
1022         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1023         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1024 
1025         serial_out(up, UART_LCR, 0);
1026         serial_out(up, UART_IER, 0);
1027         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1028 
1029         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
1030         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
1031 
1032         serial_out(up, UART_LCR, 0);
1033         serial_out(up, UART_IER, up->ier);
1034         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1035 
1036         serial_out(up, UART_EFR, up->efr);
1037         serial_out(up, UART_LCR, cval);
1038 
1039         if (!serial_omap_baud_is_mode16(port, baud))
1040                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1041         else
1042                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1043 
1044         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1045                 serial_omap_mdr1_errataset(up, up->mdr1);
1046         else
1047                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1048 
1049         /* Configure flow control */
1050         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1051 
1052         /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1053         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1054         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1055 
1056         /* Enable access to TCR/TLR */
1057         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1058         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1059         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1060 
1061         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1062 
1063         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1064                 /* Enable AUTORTS and AUTOCTS */
1065                 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
1066 
1067                 /* Ensure MCR RTS is asserted */
1068                 up->mcr |= UART_MCR_RTS;
1069         } else {
1070                 /* Disable AUTORTS and AUTOCTS */
1071                 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1072         }
1073 
1074         if (up->port.flags & UPF_SOFT_FLOW) {
1075                 /* clear SW control mode bits */
1076                 up->efr &= OMAP_UART_SW_CLR;
1077 
1078                 /*
1079                  * IXON Flag:
1080                  * Enable XON/XOFF flow control on input.
1081                  * Receiver compares XON1, XOFF1.
1082                  */
1083                 if (termios->c_iflag & IXON)
1084                         up->efr |= OMAP_UART_SW_RX;
1085 
1086                 /*
1087                  * IXOFF Flag:
1088                  * Enable XON/XOFF flow control on output.
1089                  * Transmit XON1, XOFF1
1090                  */
1091                 if (termios->c_iflag & IXOFF)
1092                         up->efr |= OMAP_UART_SW_TX;
1093 
1094                 /*
1095                  * IXANY Flag:
1096                  * Enable any character to restart output.
1097                  * Operation resumes after receiving any
1098                  * character after recognition of the XOFF character
1099                  */
1100                 if (termios->c_iflag & IXANY)
1101                         up->mcr |= UART_MCR_XONANY;
1102                 else
1103                         up->mcr &= ~UART_MCR_XONANY;
1104         }
1105         serial_out(up, UART_MCR, up->mcr);
1106         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1107         serial_out(up, UART_EFR, up->efr);
1108         serial_out(up, UART_LCR, up->lcr);
1109 
1110         serial_omap_set_mctrl(&up->port, up->port.mctrl);
1111 
1112         spin_unlock_irqrestore(&up->port.lock, flags);
1113         pm_runtime_mark_last_busy(up->dev);
1114         pm_runtime_put_autosuspend(up->dev);
1115         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1116 }
1117 
1118 static void
1119 serial_omap_pm(struct uart_port *port, unsigned int state,
1120                unsigned int oldstate)
1121 {
1122         struct uart_omap_port *up = to_uart_omap_port(port);
1123         unsigned char efr;
1124 
1125         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1126 
1127         pm_runtime_get_sync(up->dev);
1128         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1129         efr = serial_in(up, UART_EFR);
1130         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1131         serial_out(up, UART_LCR, 0);
1132 
1133         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1134         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1135         serial_out(up, UART_EFR, efr);
1136         serial_out(up, UART_LCR, 0);
1137 
1138         if (!device_may_wakeup(up->dev)) {
1139                 if (!state)
1140                         pm_runtime_forbid(up->dev);
1141                 else
1142                         pm_runtime_allow(up->dev);
1143         }
1144 
1145         pm_runtime_mark_last_busy(up->dev);
1146         pm_runtime_put_autosuspend(up->dev);
1147 }
1148 
1149 static void serial_omap_release_port(struct uart_port *port)
1150 {
1151         dev_dbg(port->dev, "serial_omap_release_port+\n");
1152 }
1153 
1154 static int serial_omap_request_port(struct uart_port *port)
1155 {
1156         dev_dbg(port->dev, "serial_omap_request_port+\n");
1157         return 0;
1158 }
1159 
1160 static void serial_omap_config_port(struct uart_port *port, int flags)
1161 {
1162         struct uart_omap_port *up = to_uart_omap_port(port);
1163 
1164         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1165                                                         up->port.line);
1166         up->port.type = PORT_OMAP;
1167         up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1168 }
1169 
1170 static int
1171 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1172 {
1173         /* we don't want the core code to modify any port params */
1174         dev_dbg(port->dev, "serial_omap_verify_port+\n");
1175         return -EINVAL;
1176 }
1177 
1178 static const char *
1179 serial_omap_type(struct uart_port *port)
1180 {
1181         struct uart_omap_port *up = to_uart_omap_port(port);
1182 
1183         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1184         return up->name;
1185 }
1186 
1187 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1188 
1189 static inline void wait_for_xmitr(struct uart_omap_port *up)
1190 {
1191         unsigned int status, tmout = 10000;
1192 
1193         /* Wait up to 10ms for the character(s) to be sent. */
1194         do {
1195                 status = serial_in(up, UART_LSR);
1196 
1197                 if (status & UART_LSR_BI)
1198                         up->lsr_break_flag = UART_LSR_BI;
1199 
1200                 if (--tmout == 0)
1201                         break;
1202                 udelay(1);
1203         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1204 
1205         /* Wait up to 1s for flow control if necessary */
1206         if (up->port.flags & UPF_CONS_FLOW) {
1207                 tmout = 1000000;
1208                 for (tmout = 1000000; tmout; tmout--) {
1209                         unsigned int msr = serial_in(up, UART_MSR);
1210 
1211                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1212                         if (msr & UART_MSR_CTS)
1213                                 break;
1214 
1215                         udelay(1);
1216                 }
1217         }
1218 }
1219 
1220 #ifdef CONFIG_CONSOLE_POLL
1221 
1222 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1223 {
1224         struct uart_omap_port *up = to_uart_omap_port(port);
1225 
1226         pm_runtime_get_sync(up->dev);
1227         wait_for_xmitr(up);
1228         serial_out(up, UART_TX, ch);
1229         pm_runtime_mark_last_busy(up->dev);
1230         pm_runtime_put_autosuspend(up->dev);
1231 }
1232 
1233 static int serial_omap_poll_get_char(struct uart_port *port)
1234 {
1235         struct uart_omap_port *up = to_uart_omap_port(port);
1236         unsigned int status;
1237 
1238         pm_runtime_get_sync(up->dev);
1239         status = serial_in(up, UART_LSR);
1240         if (!(status & UART_LSR_DR)) {
1241                 status = NO_POLL_CHAR;
1242                 goto out;
1243         }
1244 
1245         status = serial_in(up, UART_RX);
1246 
1247 out:
1248         pm_runtime_mark_last_busy(up->dev);
1249         pm_runtime_put_autosuspend(up->dev);
1250 
1251         return status;
1252 }
1253 
1254 #endif /* CONFIG_CONSOLE_POLL */
1255 
1256 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1257 
1258 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1259 
1260 static struct uart_driver serial_omap_reg;
1261 
1262 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1263 {
1264         struct uart_omap_port *up = to_uart_omap_port(port);
1265 
1266         wait_for_xmitr(up);
1267         serial_out(up, UART_TX, ch);
1268 }
1269 
1270 static void
1271 serial_omap_console_write(struct console *co, const char *s,
1272                 unsigned int count)
1273 {
1274         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1275         unsigned long flags;
1276         unsigned int ier;
1277         int locked = 1;
1278 
1279         pm_runtime_get_sync(up->dev);
1280 
1281         local_irq_save(flags);
1282         if (up->port.sysrq)
1283                 locked = 0;
1284         else if (oops_in_progress)
1285                 locked = spin_trylock(&up->port.lock);
1286         else
1287                 spin_lock(&up->port.lock);
1288 
1289         /*
1290          * First save the IER then disable the interrupts
1291          */
1292         ier = serial_in(up, UART_IER);
1293         serial_out(up, UART_IER, 0);
1294 
1295         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1296 
1297         /*
1298          * Finally, wait for transmitter to become empty
1299          * and restore the IER
1300          */
1301         wait_for_xmitr(up);
1302         serial_out(up, UART_IER, ier);
1303         /*
1304          * The receive handling will happen properly because the
1305          * receive ready bit will still be set; it is not cleared
1306          * on read.  However, modem control will not, we must
1307          * call it if we have saved something in the saved flags
1308          * while processing with interrupts off.
1309          */
1310         if (up->msr_saved_flags)
1311                 check_modem_status(up);
1312 
1313         pm_runtime_mark_last_busy(up->dev);
1314         pm_runtime_put_autosuspend(up->dev);
1315         if (locked)
1316                 spin_unlock(&up->port.lock);
1317         local_irq_restore(flags);
1318 }
1319 
1320 static int __init
1321 serial_omap_console_setup(struct console *co, char *options)
1322 {
1323         struct uart_omap_port *up;
1324         int baud = 115200;
1325         int bits = 8;
1326         int parity = 'n';
1327         int flow = 'n';
1328 
1329         if (serial_omap_console_ports[co->index] == NULL)
1330                 return -ENODEV;
1331         up = serial_omap_console_ports[co->index];
1332 
1333         if (options)
1334                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1335 
1336         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1337 }
1338 
1339 static struct console serial_omap_console = {
1340         .name           = OMAP_SERIAL_NAME,
1341         .write          = serial_omap_console_write,
1342         .device         = uart_console_device,
1343         .setup          = serial_omap_console_setup,
1344         .flags          = CON_PRINTBUFFER,
1345         .index          = -1,
1346         .data           = &serial_omap_reg,
1347 };
1348 
1349 static void serial_omap_add_console_port(struct uart_omap_port *up)
1350 {
1351         serial_omap_console_ports[up->port.line] = up;
1352 }
1353 
1354 #define OMAP_CONSOLE    (&serial_omap_console)
1355 
1356 #else
1357 
1358 #define OMAP_CONSOLE    NULL
1359 
1360 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1361 {}
1362 
1363 #endif
1364 
1365 /* Enable or disable the rs485 support */
1366 static void
1367 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
1368 {
1369         struct uart_omap_port *up = to_uart_omap_port(port);
1370         unsigned long flags;
1371         unsigned int mode;
1372         int val;
1373 
1374         pm_runtime_get_sync(up->dev);
1375         spin_lock_irqsave(&up->port.lock, flags);
1376 
1377         /* Disable interrupts from this port */
1378         mode = up->ier;
1379         up->ier = 0;
1380         serial_out(up, UART_IER, 0);
1381 
1382         /* store new config */
1383         up->rs485 = *rs485conf;
1384 
1385         /*
1386          * Just as a precaution, only allow rs485
1387          * to be enabled if the gpio pin is valid
1388          */
1389         if (gpio_is_valid(up->rts_gpio)) {
1390                 /* enable / disable rts */
1391                 val = (up->rs485.flags & SER_RS485_ENABLED) ?
1392                         SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1393                 val = (up->rs485.flags & val) ? 1 : 0;
1394                 gpio_set_value(up->rts_gpio, val);
1395         } else
1396                 up->rs485.flags &= ~SER_RS485_ENABLED;
1397 
1398         /* Enable interrupts */
1399         up->ier = mode;
1400         serial_out(up, UART_IER, up->ier);
1401 
1402         /* If RS-485 is disabled, make sure the THR interrupt is fired when
1403          * TX FIFO is below the trigger level.
1404          */
1405         if (!(up->rs485.flags & SER_RS485_ENABLED) &&
1406             (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1407                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1408                 serial_out(up, UART_OMAP_SCR, up->scr);
1409         }
1410 
1411         spin_unlock_irqrestore(&up->port.lock, flags);
1412         pm_runtime_mark_last_busy(up->dev);
1413         pm_runtime_put_autosuspend(up->dev);
1414 }
1415 
1416 static int
1417 serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1418 {
1419         struct serial_rs485 rs485conf;
1420 
1421         switch (cmd) {
1422         case TIOCSRS485:
1423                 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
1424                                         sizeof(rs485conf)))
1425                         return -EFAULT;
1426 
1427                 serial_omap_config_rs485(port, &rs485conf);
1428                 break;
1429 
1430         case TIOCGRS485:
1431                 if (copy_to_user((struct serial_rs485 *) arg,
1432                                         &(to_uart_omap_port(port)->rs485),
1433                                         sizeof(rs485conf)))
1434                         return -EFAULT;
1435                 break;
1436 
1437         default:
1438                 return -ENOIOCTLCMD;
1439         }
1440         return 0;
1441 }
1442 
1443 
1444 static struct uart_ops serial_omap_pops = {
1445         .tx_empty       = serial_omap_tx_empty,
1446         .set_mctrl      = serial_omap_set_mctrl,
1447         .get_mctrl      = serial_omap_get_mctrl,
1448         .stop_tx        = serial_omap_stop_tx,
1449         .start_tx       = serial_omap_start_tx,
1450         .throttle       = serial_omap_throttle,
1451         .unthrottle     = serial_omap_unthrottle,
1452         .stop_rx        = serial_omap_stop_rx,
1453         .enable_ms      = serial_omap_enable_ms,
1454         .break_ctl      = serial_omap_break_ctl,
1455         .startup        = serial_omap_startup,
1456         .shutdown       = serial_omap_shutdown,
1457         .set_termios    = serial_omap_set_termios,
1458         .pm             = serial_omap_pm,
1459         .type           = serial_omap_type,
1460         .release_port   = serial_omap_release_port,
1461         .request_port   = serial_omap_request_port,
1462         .config_port    = serial_omap_config_port,
1463         .verify_port    = serial_omap_verify_port,
1464         .ioctl          = serial_omap_ioctl,
1465 #ifdef CONFIG_CONSOLE_POLL
1466         .poll_put_char  = serial_omap_poll_put_char,
1467         .poll_get_char  = serial_omap_poll_get_char,
1468 #endif
1469 };
1470 
1471 static struct uart_driver serial_omap_reg = {
1472         .owner          = THIS_MODULE,
1473         .driver_name    = "OMAP-SERIAL",
1474         .dev_name       = OMAP_SERIAL_NAME,
1475         .nr             = OMAP_MAX_HSUART_PORTS,
1476         .cons           = OMAP_CONSOLE,
1477 };
1478 
1479 #ifdef CONFIG_PM_SLEEP
1480 static int serial_omap_prepare(struct device *dev)
1481 {
1482         struct uart_omap_port *up = dev_get_drvdata(dev);
1483 
1484         up->is_suspending = true;
1485 
1486         return 0;
1487 }
1488 
1489 static void serial_omap_complete(struct device *dev)
1490 {
1491         struct uart_omap_port *up = dev_get_drvdata(dev);
1492 
1493         up->is_suspending = false;
1494 }
1495 
1496 static int serial_omap_suspend(struct device *dev)
1497 {
1498         struct uart_omap_port *up = dev_get_drvdata(dev);
1499 
1500         uart_suspend_port(&serial_omap_reg, &up->port);
1501         flush_work(&up->qos_work);
1502 
1503         if (device_may_wakeup(dev))
1504                 serial_omap_enable_wakeup(up, true);
1505         else
1506                 serial_omap_enable_wakeup(up, false);
1507 
1508         return 0;
1509 }
1510 
1511 static int serial_omap_resume(struct device *dev)
1512 {
1513         struct uart_omap_port *up = dev_get_drvdata(dev);
1514 
1515         if (device_may_wakeup(dev))
1516                 serial_omap_enable_wakeup(up, false);
1517 
1518         uart_resume_port(&serial_omap_reg, &up->port);
1519 
1520         return 0;
1521 }
1522 #else
1523 #define serial_omap_prepare NULL
1524 #define serial_omap_complete NULL
1525 #endif /* CONFIG_PM_SLEEP */
1526 
1527 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1528 {
1529         u32 mvr, scheme;
1530         u16 revision, major, minor;
1531 
1532         mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1533 
1534         /* Check revision register scheme */
1535         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1536 
1537         switch (scheme) {
1538         case 0: /* Legacy Scheme: OMAP2/3 */
1539                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1540                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1541                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1542                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1543                 break;
1544         case 1:
1545                 /* New Scheme: OMAP4+ */
1546                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1547                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1548                                         OMAP_UART_MVR_MAJ_SHIFT;
1549                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1550                 break;
1551         default:
1552                 dev_warn(up->dev,
1553                         "Unknown %s revision, defaulting to highest\n",
1554                         up->name);
1555                 /* highest possible revision */
1556                 major = 0xff;
1557                 minor = 0xff;
1558         }
1559 
1560         /* normalize revision for the driver */
1561         revision = UART_BUILD_REVISION(major, minor);
1562 
1563         switch (revision) {
1564         case OMAP_UART_REV_46:
1565                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1566                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1567                 break;
1568         case OMAP_UART_REV_52:
1569                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1570                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1571                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1572                 break;
1573         case OMAP_UART_REV_63:
1574                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1575                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1576                 break;
1577         default:
1578                 break;
1579         }
1580 }
1581 
1582 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1583 {
1584         struct omap_uart_port_info *omap_up_info;
1585 
1586         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1587         if (!omap_up_info)
1588                 return NULL; /* out of memory */
1589 
1590         of_property_read_u32(dev->of_node, "clock-frequency",
1591                                          &omap_up_info->uartclk);
1592         return omap_up_info;
1593 }
1594 
1595 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1596                                    struct device_node *np)
1597 {
1598         struct serial_rs485 *rs485conf = &up->rs485;
1599         u32 rs485_delay[2];
1600         enum of_gpio_flags flags;
1601         int ret;
1602 
1603         rs485conf->flags = 0;
1604         up->rts_gpio = -EINVAL;
1605 
1606         if (!np)
1607                 return 0;
1608 
1609         if (of_property_read_bool(np, "rs485-rts-active-high"))
1610                 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1611         else
1612                 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1613 
1614         /* check for tx enable gpio */
1615         up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags);
1616         if (gpio_is_valid(up->rts_gpio)) {
1617                 ret = gpio_request(up->rts_gpio, "omap-serial");
1618                 if (ret < 0)
1619                         return ret;
1620                 ret = gpio_direction_output(up->rts_gpio,
1621                                             flags & SER_RS485_RTS_AFTER_SEND);
1622                 if (ret < 0)
1623                         return ret;
1624         } else if (up->rts_gpio == -EPROBE_DEFER) {
1625                 return -EPROBE_DEFER;
1626         } else {
1627                 up->rts_gpio = -EINVAL;
1628         }
1629 
1630         if (of_property_read_u32_array(np, "rs485-rts-delay",
1631                                     rs485_delay, 2) == 0) {
1632                 rs485conf->delay_rts_before_send = rs485_delay[0];
1633                 rs485conf->delay_rts_after_send = rs485_delay[1];
1634         }
1635 
1636         if (of_property_read_bool(np, "rs485-rx-during-tx"))
1637                 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1638 
1639         if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
1640                 rs485conf->flags |= SER_RS485_ENABLED;
1641 
1642         return 0;
1643 }
1644 
1645 static int serial_omap_probe(struct platform_device *pdev)
1646 {
1647         struct uart_omap_port   *up;
1648         struct resource         *mem, *irq;
1649         struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1650         int ret, uartirq = 0, wakeirq = 0;
1651 
1652         /* The optional wakeirq may be specified in the board dts file */
1653         if (pdev->dev.of_node) {
1654                 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1655                 if (!uartirq)
1656                         return -EPROBE_DEFER;
1657                 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1658                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1659                 pdev->dev.platform_data = omap_up_info;
1660         } else {
1661                 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1662                 if (!irq) {
1663                         dev_err(&pdev->dev, "no irq resource?\n");
1664                         return -ENODEV;
1665                 }
1666                 uartirq = irq->start;
1667         }
1668 
1669         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1670         if (!mem) {
1671                 dev_err(&pdev->dev, "no mem resource?\n");
1672                 return -ENODEV;
1673         }
1674 
1675         if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1676                                 pdev->dev.driver->name)) {
1677                 dev_err(&pdev->dev, "memory region already claimed\n");
1678                 return -EBUSY;
1679         }
1680 
1681         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1682             omap_up_info->DTR_present) {
1683                 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1684                 if (ret < 0)
1685                         return ret;
1686                 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1687                                             omap_up_info->DTR_inverted);
1688                 if (ret < 0)
1689                         return ret;
1690         }
1691 
1692         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1693         if (!up)
1694                 return -ENOMEM;
1695 
1696         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1697             omap_up_info->DTR_present) {
1698                 up->DTR_gpio = omap_up_info->DTR_gpio;
1699                 up->DTR_inverted = omap_up_info->DTR_inverted;
1700         } else
1701                 up->DTR_gpio = -EINVAL;
1702         up->DTR_active = 0;
1703 
1704         up->dev = &pdev->dev;
1705         up->port.dev = &pdev->dev;
1706         up->port.type = PORT_OMAP;
1707         up->port.iotype = UPIO_MEM;
1708         up->port.irq = uartirq;
1709         up->wakeirq = wakeirq;
1710         if (!up->wakeirq)
1711                 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1712                          up->port.line);
1713 
1714         up->port.regshift = 2;
1715         up->port.fifosize = 64;
1716         up->port.ops = &serial_omap_pops;
1717 
1718         if (pdev->dev.of_node)
1719                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1720         else
1721                 up->port.line = pdev->id;
1722 
1723         if (up->port.line < 0) {
1724                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1725                                                                 up->port.line);
1726                 ret = -ENODEV;
1727                 goto err_port_line;
1728         }
1729 
1730         ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1731         if (ret < 0)
1732                 goto err_rs485;
1733 
1734         sprintf(up->name, "OMAP UART%d", up->port.line);
1735         up->port.mapbase = mem->start;
1736         up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1737                                                 resource_size(mem));
1738         if (!up->port.membase) {
1739                 dev_err(&pdev->dev, "can't ioremap UART\n");
1740                 ret = -ENOMEM;
1741                 goto err_ioremap;
1742         }
1743 
1744         up->port.flags = omap_up_info->flags;
1745         up->port.uartclk = omap_up_info->uartclk;
1746         if (!up->port.uartclk) {
1747                 up->port.uartclk = DEFAULT_CLK_SPEED;
1748                 dev_warn(&pdev->dev,
1749                          "No clock speed specified: using default: %d\n",
1750                          DEFAULT_CLK_SPEED);
1751         }
1752 
1753         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1754         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1755         pm_qos_add_request(&up->pm_qos_request,
1756                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1757         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1758         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1759 
1760         platform_set_drvdata(pdev, up);
1761         if (omap_up_info->autosuspend_timeout == 0)
1762                 omap_up_info->autosuspend_timeout = -1;
1763         device_init_wakeup(up->dev, true);
1764         pm_runtime_use_autosuspend(&pdev->dev);
1765         pm_runtime_set_autosuspend_delay(&pdev->dev,
1766                         omap_up_info->autosuspend_timeout);
1767 
1768         pm_runtime_irq_safe(&pdev->dev);
1769         pm_runtime_enable(&pdev->dev);
1770 
1771         pm_runtime_get_sync(&pdev->dev);
1772 
1773         omap_serial_fill_features_erratas(up);
1774 
1775         ui[up->port.line] = up;
1776         serial_omap_add_console_port(up);
1777 
1778         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1779         if (ret != 0)
1780                 goto err_add_port;
1781 
1782         pm_runtime_mark_last_busy(up->dev);
1783         pm_runtime_put_autosuspend(up->dev);
1784         return 0;
1785 
1786 err_add_port:
1787         pm_runtime_put(&pdev->dev);
1788         pm_runtime_disable(&pdev->dev);
1789 err_ioremap:
1790 err_rs485:
1791 err_port_line:
1792         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1793                                 pdev->id, __func__, ret);
1794         return ret;
1795 }
1796 
1797 static int serial_omap_remove(struct platform_device *dev)
1798 {
1799         struct uart_omap_port *up = platform_get_drvdata(dev);
1800 
1801         pm_runtime_put_sync(up->dev);
1802         pm_runtime_disable(up->dev);
1803         uart_remove_one_port(&serial_omap_reg, &up->port);
1804         pm_qos_remove_request(&up->pm_qos_request);
1805         device_init_wakeup(&dev->dev, false);
1806 
1807         return 0;
1808 }
1809 
1810 /*
1811  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1812  * The access to uart register after MDR1 Access
1813  * causes UART to corrupt data.
1814  *
1815  * Need a delay =
1816  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1817  * give 10 times as much
1818  */
1819 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1820 {
1821         u8 timeout = 255;
1822 
1823         serial_out(up, UART_OMAP_MDR1, mdr1);
1824         udelay(2);
1825         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1826                         UART_FCR_CLEAR_RCVR);
1827         /*
1828          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1829          * TX_FIFO_E bit is 1.
1830          */
1831         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1832                                 (UART_LSR_THRE | UART_LSR_DR))) {
1833                 timeout--;
1834                 if (!timeout) {
1835                         /* Should *never* happen. we warn and carry on */
1836                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1837                                                 serial_in(up, UART_LSR));
1838                         break;
1839                 }
1840                 udelay(1);
1841         }
1842 }
1843 
1844 #ifdef CONFIG_PM_RUNTIME
1845 static void serial_omap_restore_context(struct uart_omap_port *up)
1846 {
1847         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1848                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1849         else
1850                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1851 
1852         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1853         serial_out(up, UART_EFR, UART_EFR_ECB);
1854         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1855         serial_out(up, UART_IER, 0x0);
1856         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1857         serial_out(up, UART_DLL, up->dll);
1858         serial_out(up, UART_DLM, up->dlh);
1859         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1860         serial_out(up, UART_IER, up->ier);
1861         serial_out(up, UART_FCR, up->fcr);
1862         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1863         serial_out(up, UART_MCR, up->mcr);
1864         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1865         serial_out(up, UART_OMAP_SCR, up->scr);
1866         serial_out(up, UART_EFR, up->efr);
1867         serial_out(up, UART_LCR, up->lcr);
1868         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1869                 serial_omap_mdr1_errataset(up, up->mdr1);
1870         else
1871                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1872         serial_out(up, UART_OMAP_WER, up->wer);
1873 }
1874 
1875 static int serial_omap_runtime_suspend(struct device *dev)
1876 {
1877         struct uart_omap_port *up = dev_get_drvdata(dev);
1878 
1879         if (!up)
1880                 return -EINVAL;
1881 
1882         /*
1883         * When using 'no_console_suspend', the console UART must not be
1884         * suspended. Since driver suspend is managed by runtime suspend,
1885         * preventing runtime suspend (by returning error) will keep device
1886         * active during suspend.
1887         */
1888         if (up->is_suspending && !console_suspend_enabled &&
1889             uart_console(&up->port))
1890                 return -EBUSY;
1891 
1892         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1893 
1894         serial_omap_enable_wakeup(up, true);
1895 
1896         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1897         schedule_work(&up->qos_work);
1898 
1899         return 0;
1900 }
1901 
1902 static int serial_omap_runtime_resume(struct device *dev)
1903 {
1904         struct uart_omap_port *up = dev_get_drvdata(dev);
1905 
1906         int loss_cnt = serial_omap_get_context_loss_count(up);
1907 
1908         serial_omap_enable_wakeup(up, false);
1909 
1910         if (loss_cnt < 0) {
1911                 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1912                         loss_cnt);
1913                 serial_omap_restore_context(up);
1914         } else if (up->context_loss_cnt != loss_cnt) {
1915                 serial_omap_restore_context(up);
1916         }
1917         up->latency = up->calc_latency;
1918         schedule_work(&up->qos_work);
1919 
1920         return 0;
1921 }
1922 #endif
1923 
1924 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1925         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1926         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1927                                 serial_omap_runtime_resume, NULL)
1928         .prepare        = serial_omap_prepare,
1929         .complete       = serial_omap_complete,
1930 };
1931 
1932 #if defined(CONFIG_OF)
1933 static const struct of_device_id omap_serial_of_match[] = {
1934         { .compatible = "ti,omap2-uart" },
1935         { .compatible = "ti,omap3-uart" },
1936         { .compatible = "ti,omap4-uart" },
1937         {},
1938 };
1939 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1940 #endif
1941 
1942 static struct platform_driver serial_omap_driver = {
1943         .probe          = serial_omap_probe,
1944         .remove         = serial_omap_remove,
1945         .driver         = {
1946                 .name   = DRIVER_NAME,
1947                 .pm     = &serial_omap_dev_pm_ops,
1948                 .of_match_table = of_match_ptr(omap_serial_of_match),
1949         },
1950 };
1951 
1952 static int __init serial_omap_init(void)
1953 {
1954         int ret;
1955 
1956         ret = uart_register_driver(&serial_omap_reg);
1957         if (ret != 0)
1958                 return ret;
1959         ret = platform_driver_register(&serial_omap_driver);
1960         if (ret != 0)
1961                 uart_unregister_driver(&serial_omap_reg);
1962         return ret;
1963 }
1964 
1965 static void __exit serial_omap_exit(void)
1966 {
1967         platform_driver_unregister(&serial_omap_driver);
1968         uart_unregister_driver(&serial_omap_reg);
1969 }
1970 
1971 module_init(serial_omap_init);
1972 module_exit(serial_omap_exit);
1973 
1974 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1975 MODULE_LICENSE("GPL");
1976 MODULE_AUTHOR("Texas Instruments Inc");
1977 

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