Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/tty/serial/mxs-auart.c

  1 /*
  2  * Freescale STMP37XX/STMP378X Application UART driver
  3  *
  4  * Author: dmitry pervushin <dimka@embeddedalley.com>
  5  *
  6  * Copyright 2008-2010 Freescale Semiconductor, Inc.
  7  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  8  *
  9  * The code contained herein is licensed under the GNU General Public
 10  * License. You may obtain a copy of the GNU General Public License
 11  * Version 2 or later at the following locations:
 12  *
 13  * http://www.opensource.org/licenses/gpl-license.html
 14  * http://www.gnu.org/copyleft/gpl.html
 15  */
 16 
 17 #include <linux/kernel.h>
 18 #include <linux/errno.h>
 19 #include <linux/init.h>
 20 #include <linux/console.h>
 21 #include <linux/interrupt.h>
 22 #include <linux/module.h>
 23 #include <linux/slab.h>
 24 #include <linux/wait.h>
 25 #include <linux/tty.h>
 26 #include <linux/tty_driver.h>
 27 #include <linux/tty_flip.h>
 28 #include <linux/serial.h>
 29 #include <linux/serial_core.h>
 30 #include <linux/platform_device.h>
 31 #include <linux/device.h>
 32 #include <linux/clk.h>
 33 #include <linux/delay.h>
 34 #include <linux/io.h>
 35 #include <linux/of_device.h>
 36 #include <linux/dma-mapping.h>
 37 #include <linux/dmaengine.h>
 38 
 39 #include <asm/cacheflush.h>
 40 
 41 #define MXS_AUART_PORTS 5
 42 #define MXS_AUART_FIFO_SIZE             16
 43 
 44 #define AUART_CTRL0                     0x00000000
 45 #define AUART_CTRL0_SET                 0x00000004
 46 #define AUART_CTRL0_CLR                 0x00000008
 47 #define AUART_CTRL0_TOG                 0x0000000c
 48 #define AUART_CTRL1                     0x00000010
 49 #define AUART_CTRL1_SET                 0x00000014
 50 #define AUART_CTRL1_CLR                 0x00000018
 51 #define AUART_CTRL1_TOG                 0x0000001c
 52 #define AUART_CTRL2                     0x00000020
 53 #define AUART_CTRL2_SET                 0x00000024
 54 #define AUART_CTRL2_CLR                 0x00000028
 55 #define AUART_CTRL2_TOG                 0x0000002c
 56 #define AUART_LINECTRL                  0x00000030
 57 #define AUART_LINECTRL_SET              0x00000034
 58 #define AUART_LINECTRL_CLR              0x00000038
 59 #define AUART_LINECTRL_TOG              0x0000003c
 60 #define AUART_LINECTRL2                 0x00000040
 61 #define AUART_LINECTRL2_SET             0x00000044
 62 #define AUART_LINECTRL2_CLR             0x00000048
 63 #define AUART_LINECTRL2_TOG             0x0000004c
 64 #define AUART_INTR                      0x00000050
 65 #define AUART_INTR_SET                  0x00000054
 66 #define AUART_INTR_CLR                  0x00000058
 67 #define AUART_INTR_TOG                  0x0000005c
 68 #define AUART_DATA                      0x00000060
 69 #define AUART_STAT                      0x00000070
 70 #define AUART_DEBUG                     0x00000080
 71 #define AUART_VERSION                   0x00000090
 72 #define AUART_AUTOBAUD                  0x000000a0
 73 
 74 #define AUART_CTRL0_SFTRST                      (1 << 31)
 75 #define AUART_CTRL0_CLKGATE                     (1 << 30)
 76 #define AUART_CTRL0_RXTO_ENABLE                 (1 << 27)
 77 #define AUART_CTRL0_RXTIMEOUT(v)                (((v) & 0x7ff) << 16)
 78 #define AUART_CTRL0_XFER_COUNT(v)               ((v) & 0xffff)
 79 
 80 #define AUART_CTRL1_XFER_COUNT(v)               ((v) & 0xffff)
 81 
 82 #define AUART_CTRL2_DMAONERR                    (1 << 26)
 83 #define AUART_CTRL2_TXDMAE                      (1 << 25)
 84 #define AUART_CTRL2_RXDMAE                      (1 << 24)
 85 
 86 #define AUART_CTRL2_CTSEN                       (1 << 15)
 87 #define AUART_CTRL2_RTSEN                       (1 << 14)
 88 #define AUART_CTRL2_RTS                         (1 << 11)
 89 #define AUART_CTRL2_RXE                         (1 << 9)
 90 #define AUART_CTRL2_TXE                         (1 << 8)
 91 #define AUART_CTRL2_UARTEN                      (1 << 0)
 92 
 93 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT        16
 94 #define AUART_LINECTRL_BAUD_DIVINT_MASK         0xffff0000
 95 #define AUART_LINECTRL_BAUD_DIVINT(v)           (((v) & 0xffff) << 16)
 96 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT       8
 97 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK        0x00003f00
 98 #define AUART_LINECTRL_BAUD_DIVFRAC(v)          (((v) & 0x3f) << 8)
 99 #define AUART_LINECTRL_WLEN_MASK                0x00000060
100 #define AUART_LINECTRL_WLEN(v)                  (((v) & 0x3) << 5)
101 #define AUART_LINECTRL_FEN                      (1 << 4)
102 #define AUART_LINECTRL_STP2                     (1 << 3)
103 #define AUART_LINECTRL_EPS                      (1 << 2)
104 #define AUART_LINECTRL_PEN                      (1 << 1)
105 #define AUART_LINECTRL_BRK                      (1 << 0)
106 
107 #define AUART_INTR_RTIEN                        (1 << 22)
108 #define AUART_INTR_TXIEN                        (1 << 21)
109 #define AUART_INTR_RXIEN                        (1 << 20)
110 #define AUART_INTR_CTSMIEN                      (1 << 17)
111 #define AUART_INTR_RTIS                         (1 << 6)
112 #define AUART_INTR_TXIS                         (1 << 5)
113 #define AUART_INTR_RXIS                         (1 << 4)
114 #define AUART_INTR_CTSMIS                       (1 << 1)
115 
116 #define AUART_STAT_BUSY                         (1 << 29)
117 #define AUART_STAT_CTS                          (1 << 28)
118 #define AUART_STAT_TXFE                         (1 << 27)
119 #define AUART_STAT_TXFF                         (1 << 25)
120 #define AUART_STAT_RXFE                         (1 << 24)
121 #define AUART_STAT_OERR                         (1 << 19)
122 #define AUART_STAT_BERR                         (1 << 18)
123 #define AUART_STAT_PERR                         (1 << 17)
124 #define AUART_STAT_FERR                         (1 << 16)
125 #define AUART_STAT_RXCOUNT_MASK                 0xffff
126 
127 static struct uart_driver auart_driver;
128 
129 enum mxs_auart_type {
130         IMX23_AUART,
131         IMX28_AUART,
132 };
133 
134 struct mxs_auart_port {
135         struct uart_port port;
136 
137 #define MXS_AUART_DMA_ENABLED   0x2
138 #define MXS_AUART_DMA_TX_SYNC   2  /* bit 2 */
139 #define MXS_AUART_DMA_RX_READY  3  /* bit 3 */
140 #define MXS_AUART_RTSCTS        4  /* bit 4 */
141         unsigned long flags;
142         unsigned int ctrl;
143         enum mxs_auart_type devtype;
144 
145         unsigned int irq;
146 
147         struct clk *clk;
148         struct device *dev;
149 
150         /* for DMA */
151         struct scatterlist tx_sgl;
152         struct dma_chan *tx_dma_chan;
153         void *tx_dma_buf;
154 
155         struct scatterlist rx_sgl;
156         struct dma_chan *rx_dma_chan;
157         void *rx_dma_buf;
158 };
159 
160 static struct platform_device_id mxs_auart_devtype[] = {
161         { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART },
162         { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART },
163         { /* sentinel */ }
164 };
165 MODULE_DEVICE_TABLE(platform, mxs_auart_devtype);
166 
167 static struct of_device_id mxs_auart_dt_ids[] = {
168         {
169                 .compatible = "fsl,imx28-auart",
170                 .data = &mxs_auart_devtype[IMX28_AUART]
171         }, {
172                 .compatible = "fsl,imx23-auart",
173                 .data = &mxs_auart_devtype[IMX23_AUART]
174         }, { /* sentinel */ }
175 };
176 MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
177 
178 static inline int is_imx28_auart(struct mxs_auart_port *s)
179 {
180         return s->devtype == IMX28_AUART;
181 }
182 
183 static inline bool auart_dma_enabled(struct mxs_auart_port *s)
184 {
185         return s->flags & MXS_AUART_DMA_ENABLED;
186 }
187 
188 static void mxs_auart_stop_tx(struct uart_port *u);
189 
190 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
191 
192 static void mxs_auart_tx_chars(struct mxs_auart_port *s);
193 
194 static void dma_tx_callback(void *param)
195 {
196         struct mxs_auart_port *s = param;
197         struct circ_buf *xmit = &s->port.state->xmit;
198 
199         dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
200 
201         /* clear the bit used to serialize the DMA tx. */
202         clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
203         smp_mb__after_atomic();
204 
205         /* wake up the possible processes. */
206         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
207                 uart_write_wakeup(&s->port);
208 
209         mxs_auart_tx_chars(s);
210 }
211 
212 static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
213 {
214         struct dma_async_tx_descriptor *desc;
215         struct scatterlist *sgl = &s->tx_sgl;
216         struct dma_chan *channel = s->tx_dma_chan;
217         u32 pio;
218 
219         /* [1] : send PIO. Note, the first pio word is CTRL1. */
220         pio = AUART_CTRL1_XFER_COUNT(size);
221         desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
222                                         1, DMA_TRANS_NONE, 0);
223         if (!desc) {
224                 dev_err(s->dev, "step 1 error\n");
225                 return -EINVAL;
226         }
227 
228         /* [2] : set DMA buffer. */
229         sg_init_one(sgl, s->tx_dma_buf, size);
230         dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
231         desc = dmaengine_prep_slave_sg(channel, sgl,
232                         1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
233         if (!desc) {
234                 dev_err(s->dev, "step 2 error\n");
235                 return -EINVAL;
236         }
237 
238         /* [3] : submit the DMA */
239         desc->callback = dma_tx_callback;
240         desc->callback_param = s;
241         dmaengine_submit(desc);
242         dma_async_issue_pending(channel);
243         return 0;
244 }
245 
246 static void mxs_auart_tx_chars(struct mxs_auart_port *s)
247 {
248         struct circ_buf *xmit = &s->port.state->xmit;
249 
250         if (auart_dma_enabled(s)) {
251                 u32 i = 0;
252                 int size;
253                 void *buffer = s->tx_dma_buf;
254 
255                 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
256                         return;
257 
258                 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
259                         size = min_t(u32, UART_XMIT_SIZE - i,
260                                      CIRC_CNT_TO_END(xmit->head,
261                                                      xmit->tail,
262                                                      UART_XMIT_SIZE));
263                         memcpy(buffer + i, xmit->buf + xmit->tail, size);
264                         xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
265 
266                         i += size;
267                         if (i >= UART_XMIT_SIZE)
268                                 break;
269                 }
270 
271                 if (uart_tx_stopped(&s->port))
272                         mxs_auart_stop_tx(&s->port);
273 
274                 if (i) {
275                         mxs_auart_dma_tx(s, i);
276                 } else {
277                         clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
278                         smp_mb__after_atomic();
279                 }
280                 return;
281         }
282 
283 
284         while (!(readl(s->port.membase + AUART_STAT) &
285                  AUART_STAT_TXFF)) {
286                 if (s->port.x_char) {
287                         s->port.icount.tx++;
288                         writel(s->port.x_char,
289                                      s->port.membase + AUART_DATA);
290                         s->port.x_char = 0;
291                         continue;
292                 }
293                 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
294                         s->port.icount.tx++;
295                         writel(xmit->buf[xmit->tail],
296                                      s->port.membase + AUART_DATA);
297                         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
298                 } else
299                         break;
300         }
301         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
302                 uart_write_wakeup(&s->port);
303 
304         if (uart_circ_empty(&(s->port.state->xmit)))
305                 writel(AUART_INTR_TXIEN,
306                              s->port.membase + AUART_INTR_CLR);
307         else
308                 writel(AUART_INTR_TXIEN,
309                              s->port.membase + AUART_INTR_SET);
310 
311         if (uart_tx_stopped(&s->port))
312                 mxs_auart_stop_tx(&s->port);
313 }
314 
315 static void mxs_auart_rx_char(struct mxs_auart_port *s)
316 {
317         int flag;
318         u32 stat;
319         u8 c;
320 
321         c = readl(s->port.membase + AUART_DATA);
322         stat = readl(s->port.membase + AUART_STAT);
323 
324         flag = TTY_NORMAL;
325         s->port.icount.rx++;
326 
327         if (stat & AUART_STAT_BERR) {
328                 s->port.icount.brk++;
329                 if (uart_handle_break(&s->port))
330                         goto out;
331         } else if (stat & AUART_STAT_PERR) {
332                 s->port.icount.parity++;
333         } else if (stat & AUART_STAT_FERR) {
334                 s->port.icount.frame++;
335         }
336 
337         /*
338          * Mask off conditions which should be ingored.
339          */
340         stat &= s->port.read_status_mask;
341 
342         if (stat & AUART_STAT_BERR) {
343                 flag = TTY_BREAK;
344         } else if (stat & AUART_STAT_PERR)
345                 flag = TTY_PARITY;
346         else if (stat & AUART_STAT_FERR)
347                 flag = TTY_FRAME;
348 
349         if (stat & AUART_STAT_OERR)
350                 s->port.icount.overrun++;
351 
352         if (uart_handle_sysrq_char(&s->port, c))
353                 goto out;
354 
355         uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
356 out:
357         writel(stat, s->port.membase + AUART_STAT);
358 }
359 
360 static void mxs_auart_rx_chars(struct mxs_auart_port *s)
361 {
362         u32 stat = 0;
363 
364         for (;;) {
365                 stat = readl(s->port.membase + AUART_STAT);
366                 if (stat & AUART_STAT_RXFE)
367                         break;
368                 mxs_auart_rx_char(s);
369         }
370 
371         writel(stat, s->port.membase + AUART_STAT);
372         tty_flip_buffer_push(&s->port.state->port);
373 }
374 
375 static int mxs_auart_request_port(struct uart_port *u)
376 {
377         return 0;
378 }
379 
380 static int mxs_auart_verify_port(struct uart_port *u,
381                                     struct serial_struct *ser)
382 {
383         if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
384                 return -EINVAL;
385         return 0;
386 }
387 
388 static void mxs_auart_config_port(struct uart_port *u, int flags)
389 {
390 }
391 
392 static const char *mxs_auart_type(struct uart_port *u)
393 {
394         struct mxs_auart_port *s = to_auart_port(u);
395 
396         return dev_name(s->dev);
397 }
398 
399 static void mxs_auart_release_port(struct uart_port *u)
400 {
401 }
402 
403 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
404 {
405         struct mxs_auart_port *s = to_auart_port(u);
406 
407         u32 ctrl = readl(u->membase + AUART_CTRL2);
408 
409         ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
410         if (mctrl & TIOCM_RTS) {
411                 if (tty_port_cts_enabled(&u->state->port))
412                         ctrl |= AUART_CTRL2_RTSEN;
413                 else
414                         ctrl |= AUART_CTRL2_RTS;
415         }
416 
417         s->ctrl = mctrl;
418         writel(ctrl, u->membase + AUART_CTRL2);
419 }
420 
421 static u32 mxs_auart_get_mctrl(struct uart_port *u)
422 {
423         struct mxs_auart_port *s = to_auart_port(u);
424         u32 stat = readl(u->membase + AUART_STAT);
425         int ctrl2 = readl(u->membase + AUART_CTRL2);
426         u32 mctrl = s->ctrl;
427 
428         mctrl &= ~TIOCM_CTS;
429         if (stat & AUART_STAT_CTS)
430                 mctrl |= TIOCM_CTS;
431 
432         if (ctrl2 & AUART_CTRL2_RTS)
433                 mctrl |= TIOCM_RTS;
434 
435         return mctrl;
436 }
437 
438 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
439 static void dma_rx_callback(void *arg)
440 {
441         struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
442         struct tty_port *port = &s->port.state->port;
443         int count;
444         u32 stat;
445 
446         dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
447 
448         stat = readl(s->port.membase + AUART_STAT);
449         stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
450                         AUART_STAT_PERR | AUART_STAT_FERR);
451 
452         count = stat & AUART_STAT_RXCOUNT_MASK;
453         tty_insert_flip_string(port, s->rx_dma_buf, count);
454 
455         writel(stat, s->port.membase + AUART_STAT);
456         tty_flip_buffer_push(port);
457 
458         /* start the next DMA for RX. */
459         mxs_auart_dma_prep_rx(s);
460 }
461 
462 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
463 {
464         struct dma_async_tx_descriptor *desc;
465         struct scatterlist *sgl = &s->rx_sgl;
466         struct dma_chan *channel = s->rx_dma_chan;
467         u32 pio[1];
468 
469         /* [1] : send PIO */
470         pio[0] = AUART_CTRL0_RXTO_ENABLE
471                 | AUART_CTRL0_RXTIMEOUT(0x80)
472                 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
473         desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
474                                         1, DMA_TRANS_NONE, 0);
475         if (!desc) {
476                 dev_err(s->dev, "step 1 error\n");
477                 return -EINVAL;
478         }
479 
480         /* [2] : send DMA request */
481         sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
482         dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
483         desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
484                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
485         if (!desc) {
486                 dev_err(s->dev, "step 2 error\n");
487                 return -1;
488         }
489 
490         /* [3] : submit the DMA, but do not issue it. */
491         desc->callback = dma_rx_callback;
492         desc->callback_param = s;
493         dmaengine_submit(desc);
494         dma_async_issue_pending(channel);
495         return 0;
496 }
497 
498 static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
499 {
500         if (s->tx_dma_chan) {
501                 dma_release_channel(s->tx_dma_chan);
502                 s->tx_dma_chan = NULL;
503         }
504         if (s->rx_dma_chan) {
505                 dma_release_channel(s->rx_dma_chan);
506                 s->rx_dma_chan = NULL;
507         }
508 
509         kfree(s->tx_dma_buf);
510         kfree(s->rx_dma_buf);
511         s->tx_dma_buf = NULL;
512         s->rx_dma_buf = NULL;
513 }
514 
515 static void mxs_auart_dma_exit(struct mxs_auart_port *s)
516 {
517 
518         writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
519                 s->port.membase + AUART_CTRL2_CLR);
520 
521         mxs_auart_dma_exit_channel(s);
522         s->flags &= ~MXS_AUART_DMA_ENABLED;
523         clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
524         clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
525 }
526 
527 static int mxs_auart_dma_init(struct mxs_auart_port *s)
528 {
529         if (auart_dma_enabled(s))
530                 return 0;
531 
532         /* init for RX */
533         s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
534         if (!s->rx_dma_chan)
535                 goto err_out;
536         s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
537         if (!s->rx_dma_buf)
538                 goto err_out;
539 
540         /* init for TX */
541         s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
542         if (!s->tx_dma_chan)
543                 goto err_out;
544         s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
545         if (!s->tx_dma_buf)
546                 goto err_out;
547 
548         /* set the flags */
549         s->flags |= MXS_AUART_DMA_ENABLED;
550         dev_dbg(s->dev, "enabled the DMA support.");
551 
552         /* The DMA buffer is now the FIFO the TTY subsystem can use */
553         s->port.fifosize = UART_XMIT_SIZE;
554 
555         return 0;
556 
557 err_out:
558         mxs_auart_dma_exit_channel(s);
559         return -EINVAL;
560 
561 }
562 
563 static void mxs_auart_settermios(struct uart_port *u,
564                                  struct ktermios *termios,
565                                  struct ktermios *old)
566 {
567         struct mxs_auart_port *s = to_auart_port(u);
568         u32 bm, ctrl, ctrl2, div;
569         unsigned int cflag, baud;
570 
571         cflag = termios->c_cflag;
572 
573         ctrl = AUART_LINECTRL_FEN;
574         ctrl2 = readl(u->membase + AUART_CTRL2);
575 
576         /* byte size */
577         switch (cflag & CSIZE) {
578         case CS5:
579                 bm = 0;
580                 break;
581         case CS6:
582                 bm = 1;
583                 break;
584         case CS7:
585                 bm = 2;
586                 break;
587         case CS8:
588                 bm = 3;
589                 break;
590         default:
591                 return;
592         }
593 
594         ctrl |= AUART_LINECTRL_WLEN(bm);
595 
596         /* parity */
597         if (cflag & PARENB) {
598                 ctrl |= AUART_LINECTRL_PEN;
599                 if ((cflag & PARODD) == 0)
600                         ctrl |= AUART_LINECTRL_EPS;
601         }
602 
603         u->read_status_mask = 0;
604 
605         if (termios->c_iflag & INPCK)
606                 u->read_status_mask |= AUART_STAT_PERR;
607         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
608                 u->read_status_mask |= AUART_STAT_BERR;
609 
610         /*
611          * Characters to ignore
612          */
613         u->ignore_status_mask = 0;
614         if (termios->c_iflag & IGNPAR)
615                 u->ignore_status_mask |= AUART_STAT_PERR;
616         if (termios->c_iflag & IGNBRK) {
617                 u->ignore_status_mask |= AUART_STAT_BERR;
618                 /*
619                  * If we're ignoring parity and break indicators,
620                  * ignore overruns too (for real raw support).
621                  */
622                 if (termios->c_iflag & IGNPAR)
623                         u->ignore_status_mask |= AUART_STAT_OERR;
624         }
625 
626         /*
627          * ignore all characters if CREAD is not set
628          */
629         if (cflag & CREAD)
630                 ctrl2 |= AUART_CTRL2_RXE;
631         else
632                 ctrl2 &= ~AUART_CTRL2_RXE;
633 
634         /* figure out the stop bits requested */
635         if (cflag & CSTOPB)
636                 ctrl |= AUART_LINECTRL_STP2;
637 
638         /* figure out the hardware flow control settings */
639         if (cflag & CRTSCTS) {
640                 /*
641                  * The DMA has a bug(see errata:2836) in mx23.
642                  * So we can not implement the DMA for auart in mx23,
643                  * we can only implement the DMA support for auart
644                  * in mx28.
645                  */
646                 if (is_imx28_auart(s)
647                                 && test_bit(MXS_AUART_RTSCTS, &s->flags)) {
648                         if (!mxs_auart_dma_init(s))
649                                 /* enable DMA tranfer */
650                                 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
651                                        | AUART_CTRL2_DMAONERR;
652                 }
653                 ctrl2 |= AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN;
654         } else {
655                 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
656         }
657 
658         /* set baud rate */
659         baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
660         div = u->uartclk * 32 / baud;
661         ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
662         ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
663 
664         writel(ctrl, u->membase + AUART_LINECTRL);
665         writel(ctrl2, u->membase + AUART_CTRL2);
666 
667         uart_update_timeout(u, termios->c_cflag, baud);
668 
669         /* prepare for the DMA RX. */
670         if (auart_dma_enabled(s) &&
671                 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
672                 if (!mxs_auart_dma_prep_rx(s)) {
673                         /* Disable the normal RX interrupt. */
674                         writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
675                                         u->membase + AUART_INTR_CLR);
676                 } else {
677                         mxs_auart_dma_exit(s);
678                         dev_err(s->dev, "We can not start up the DMA.\n");
679                 }
680         }
681 }
682 
683 static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
684 {
685         u32 istat;
686         struct mxs_auart_port *s = context;
687         u32 stat = readl(s->port.membase + AUART_STAT);
688 
689         istat = readl(s->port.membase + AUART_INTR);
690 
691         /* ack irq */
692         writel(istat & (AUART_INTR_RTIS
693                 | AUART_INTR_TXIS
694                 | AUART_INTR_RXIS
695                 | AUART_INTR_CTSMIS),
696                         s->port.membase + AUART_INTR_CLR);
697 
698         if (istat & AUART_INTR_CTSMIS) {
699                 uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
700                 writel(AUART_INTR_CTSMIS,
701                                 s->port.membase + AUART_INTR_CLR);
702                 istat &= ~AUART_INTR_CTSMIS;
703         }
704 
705         if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
706                 if (!auart_dma_enabled(s))
707                         mxs_auart_rx_chars(s);
708                 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
709         }
710 
711         if (istat & AUART_INTR_TXIS) {
712                 mxs_auart_tx_chars(s);
713                 istat &= ~AUART_INTR_TXIS;
714         }
715 
716         return IRQ_HANDLED;
717 }
718 
719 static void mxs_auart_reset(struct uart_port *u)
720 {
721         int i;
722         unsigned int reg;
723 
724         writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
725 
726         for (i = 0; i < 10000; i++) {
727                 reg = readl(u->membase + AUART_CTRL0);
728                 if (!(reg & AUART_CTRL0_SFTRST))
729                         break;
730                 udelay(3);
731         }
732         writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
733 }
734 
735 static int mxs_auart_startup(struct uart_port *u)
736 {
737         int ret;
738         struct mxs_auart_port *s = to_auart_port(u);
739 
740         ret = clk_prepare_enable(s->clk);
741         if (ret)
742                 return ret;
743 
744         writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
745 
746         writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
747 
748         writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
749                         u->membase + AUART_INTR);
750 
751         /* Reset FIFO size (it could have changed if DMA was enabled) */
752         u->fifosize = MXS_AUART_FIFO_SIZE;
753 
754         /*
755          * Enable fifo so all four bytes of a DMA word are written to
756          * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
757          */
758         writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
759 
760         return 0;
761 }
762 
763 static void mxs_auart_shutdown(struct uart_port *u)
764 {
765         struct mxs_auart_port *s = to_auart_port(u);
766 
767         if (auart_dma_enabled(s))
768                 mxs_auart_dma_exit(s);
769 
770         writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
771 
772         writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
773                         u->membase + AUART_INTR_CLR);
774 
775         writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
776 
777         clk_disable_unprepare(s->clk);
778 }
779 
780 static unsigned int mxs_auart_tx_empty(struct uart_port *u)
781 {
782         if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
783                 return TIOCSER_TEMT;
784         else
785                 return 0;
786 }
787 
788 static void mxs_auart_start_tx(struct uart_port *u)
789 {
790         struct mxs_auart_port *s = to_auart_port(u);
791 
792         /* enable transmitter */
793         writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
794 
795         mxs_auart_tx_chars(s);
796 }
797 
798 static void mxs_auart_stop_tx(struct uart_port *u)
799 {
800         writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
801 }
802 
803 static void mxs_auart_stop_rx(struct uart_port *u)
804 {
805         writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
806 }
807 
808 static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
809 {
810         if (ctl)
811                 writel(AUART_LINECTRL_BRK,
812                              u->membase + AUART_LINECTRL_SET);
813         else
814                 writel(AUART_LINECTRL_BRK,
815                              u->membase + AUART_LINECTRL_CLR);
816 }
817 
818 static struct uart_ops mxs_auart_ops = {
819         .tx_empty       = mxs_auart_tx_empty,
820         .start_tx       = mxs_auart_start_tx,
821         .stop_tx        = mxs_auart_stop_tx,
822         .stop_rx        = mxs_auart_stop_rx,
823         .break_ctl      = mxs_auart_break_ctl,
824         .set_mctrl      = mxs_auart_set_mctrl,
825         .get_mctrl      = mxs_auart_get_mctrl,
826         .startup        = mxs_auart_startup,
827         .shutdown       = mxs_auart_shutdown,
828         .set_termios    = mxs_auart_settermios,
829         .type           = mxs_auart_type,
830         .release_port   = mxs_auart_release_port,
831         .request_port   = mxs_auart_request_port,
832         .config_port    = mxs_auart_config_port,
833         .verify_port    = mxs_auart_verify_port,
834 };
835 
836 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
837 
838 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
839 static void mxs_auart_console_putchar(struct uart_port *port, int ch)
840 {
841         unsigned int to = 1000;
842 
843         while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
844                 if (!to--)
845                         break;
846                 udelay(1);
847         }
848 
849         writel(ch, port->membase + AUART_DATA);
850 }
851 
852 static void
853 auart_console_write(struct console *co, const char *str, unsigned int count)
854 {
855         struct mxs_auart_port *s;
856         struct uart_port *port;
857         unsigned int old_ctrl0, old_ctrl2;
858         unsigned int to = 20000;
859 
860         if (co->index >= MXS_AUART_PORTS || co->index < 0)
861                 return;
862 
863         s = auart_port[co->index];
864         port = &s->port;
865 
866         clk_enable(s->clk);
867 
868         /* First save the CR then disable the interrupts */
869         old_ctrl2 = readl(port->membase + AUART_CTRL2);
870         old_ctrl0 = readl(port->membase + AUART_CTRL0);
871 
872         writel(AUART_CTRL0_CLKGATE,
873                      port->membase + AUART_CTRL0_CLR);
874         writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
875                      port->membase + AUART_CTRL2_SET);
876 
877         uart_console_write(port, str, count, mxs_auart_console_putchar);
878 
879         /* Finally, wait for transmitter to become empty ... */
880         while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
881                 udelay(1);
882                 if (!to--)
883                         break;
884         }
885 
886         /*
887          * ... and restore the TCR if we waited long enough for the transmitter
888          * to be idle. This might keep the transmitter enabled although it is
889          * unused, but that is better than to disable it while it is still
890          * transmitting.
891          */
892         if (!(readl(port->membase + AUART_STAT) & AUART_STAT_BUSY)) {
893                 writel(old_ctrl0, port->membase + AUART_CTRL0);
894                 writel(old_ctrl2, port->membase + AUART_CTRL2);
895         }
896 
897         clk_disable(s->clk);
898 }
899 
900 static void __init
901 auart_console_get_options(struct uart_port *port, int *baud,
902                           int *parity, int *bits)
903 {
904         unsigned int lcr_h, quot;
905 
906         if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
907                 return;
908 
909         lcr_h = readl(port->membase + AUART_LINECTRL);
910 
911         *parity = 'n';
912         if (lcr_h & AUART_LINECTRL_PEN) {
913                 if (lcr_h & AUART_LINECTRL_EPS)
914                         *parity = 'e';
915                 else
916                         *parity = 'o';
917         }
918 
919         if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
920                 *bits = 7;
921         else
922                 *bits = 8;
923 
924         quot = ((readl(port->membase + AUART_LINECTRL)
925                         & AUART_LINECTRL_BAUD_DIVINT_MASK))
926                             >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
927         quot |= ((readl(port->membase + AUART_LINECTRL)
928                         & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
929                                 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
930         if (quot == 0)
931                 quot = 1;
932 
933         *baud = (port->uartclk << 2) / quot;
934 }
935 
936 static int __init
937 auart_console_setup(struct console *co, char *options)
938 {
939         struct mxs_auart_port *s;
940         int baud = 9600;
941         int bits = 8;
942         int parity = 'n';
943         int flow = 'n';
944         int ret;
945 
946         /*
947          * Check whether an invalid uart number has been specified, and
948          * if so, search for the first available port that does have
949          * console support.
950          */
951         if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
952                 co->index = 0;
953         s = auart_port[co->index];
954         if (!s)
955                 return -ENODEV;
956 
957         ret = clk_prepare_enable(s->clk);
958         if (ret)
959                 return ret;
960 
961         if (options)
962                 uart_parse_options(options, &baud, &parity, &bits, &flow);
963         else
964                 auart_console_get_options(&s->port, &baud, &parity, &bits);
965 
966         ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
967 
968         clk_disable_unprepare(s->clk);
969 
970         return ret;
971 }
972 
973 static struct console auart_console = {
974         .name           = "ttyAPP",
975         .write          = auart_console_write,
976         .device         = uart_console_device,
977         .setup          = auart_console_setup,
978         .flags          = CON_PRINTBUFFER,
979         .index          = -1,
980         .data           = &auart_driver,
981 };
982 #endif
983 
984 static struct uart_driver auart_driver = {
985         .owner          = THIS_MODULE,
986         .driver_name    = "ttyAPP",
987         .dev_name       = "ttyAPP",
988         .major          = 0,
989         .minor          = 0,
990         .nr             = MXS_AUART_PORTS,
991 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
992         .cons =         &auart_console,
993 #endif
994 };
995 
996 /*
997  * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
998  * could successfully get all information from dt or a negative errno.
999  */
1000 static int serial_mxs_probe_dt(struct mxs_auart_port *s,
1001                 struct platform_device *pdev)
1002 {
1003         struct device_node *np = pdev->dev.of_node;
1004         int ret;
1005 
1006         if (!np)
1007                 /* no device tree device */
1008                 return 1;
1009 
1010         ret = of_alias_get_id(np, "serial");
1011         if (ret < 0) {
1012                 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1013                 return ret;
1014         }
1015         s->port.line = ret;
1016 
1017         if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1018                 set_bit(MXS_AUART_RTSCTS, &s->flags);
1019 
1020         return 0;
1021 }
1022 
1023 static int mxs_auart_probe(struct platform_device *pdev)
1024 {
1025         const struct of_device_id *of_id =
1026                         of_match_device(mxs_auart_dt_ids, &pdev->dev);
1027         struct mxs_auart_port *s;
1028         u32 version;
1029         int ret = 0;
1030         struct resource *r;
1031 
1032         s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
1033         if (!s) {
1034                 ret = -ENOMEM;
1035                 goto out;
1036         }
1037 
1038         ret = serial_mxs_probe_dt(s, pdev);
1039         if (ret > 0)
1040                 s->port.line = pdev->id < 0 ? 0 : pdev->id;
1041         else if (ret < 0)
1042                 goto out_free;
1043 
1044         if (of_id) {
1045                 pdev->id_entry = of_id->data;
1046                 s->devtype = pdev->id_entry->driver_data;
1047         }
1048 
1049         s->clk = clk_get(&pdev->dev, NULL);
1050         if (IS_ERR(s->clk)) {
1051                 ret = PTR_ERR(s->clk);
1052                 goto out_free;
1053         }
1054 
1055         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1056         if (!r) {
1057                 ret = -ENXIO;
1058                 goto out_free_clk;
1059         }
1060 
1061         s->port.mapbase = r->start;
1062         s->port.membase = ioremap(r->start, resource_size(r));
1063         s->port.ops = &mxs_auart_ops;
1064         s->port.iotype = UPIO_MEM;
1065         s->port.fifosize = MXS_AUART_FIFO_SIZE;
1066         s->port.uartclk = clk_get_rate(s->clk);
1067         s->port.type = PORT_IMX;
1068         s->port.dev = s->dev = &pdev->dev;
1069 
1070         s->ctrl = 0;
1071 
1072         s->irq = platform_get_irq(pdev, 0);
1073         s->port.irq = s->irq;
1074         ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
1075         if (ret)
1076                 goto out_free_clk;
1077 
1078         platform_set_drvdata(pdev, s);
1079 
1080         auart_port[s->port.line] = s;
1081 
1082         mxs_auart_reset(&s->port);
1083 
1084         ret = uart_add_one_port(&auart_driver, &s->port);
1085         if (ret)
1086                 goto out_free_irq;
1087 
1088         version = readl(s->port.membase + AUART_VERSION);
1089         dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1090                (version >> 24) & 0xff,
1091                (version >> 16) & 0xff, version & 0xffff);
1092 
1093         return 0;
1094 
1095 out_free_irq:
1096         auart_port[pdev->id] = NULL;
1097         free_irq(s->irq, s);
1098 out_free_clk:
1099         clk_put(s->clk);
1100 out_free:
1101         kfree(s);
1102 out:
1103         return ret;
1104 }
1105 
1106 static int mxs_auart_remove(struct platform_device *pdev)
1107 {
1108         struct mxs_auart_port *s = platform_get_drvdata(pdev);
1109 
1110         uart_remove_one_port(&auart_driver, &s->port);
1111 
1112         auart_port[pdev->id] = NULL;
1113 
1114         clk_put(s->clk);
1115         free_irq(s->irq, s);
1116         kfree(s);
1117 
1118         return 0;
1119 }
1120 
1121 static struct platform_driver mxs_auart_driver = {
1122         .probe = mxs_auart_probe,
1123         .remove = mxs_auart_remove,
1124         .driver = {
1125                 .name = "mxs-auart",
1126                 .owner = THIS_MODULE,
1127                 .of_match_table = mxs_auart_dt_ids,
1128         },
1129 };
1130 
1131 static int __init mxs_auart_init(void)
1132 {
1133         int r;
1134 
1135         r = uart_register_driver(&auart_driver);
1136         if (r)
1137                 goto out;
1138 
1139         r = platform_driver_register(&mxs_auart_driver);
1140         if (r)
1141                 goto out_err;
1142 
1143         return 0;
1144 out_err:
1145         uart_unregister_driver(&auart_driver);
1146 out:
1147         return r;
1148 }
1149 
1150 static void __exit mxs_auart_exit(void)
1151 {
1152         platform_driver_unregister(&mxs_auart_driver);
1153         uart_unregister_driver(&auart_driver);
1154 }
1155 
1156 module_init(mxs_auart_init);
1157 module_exit(mxs_auart_exit);
1158 MODULE_LICENSE("GPL");
1159 MODULE_DESCRIPTION("Freescale MXS application uart driver");
1160 MODULE_ALIAS("platform:mxs-auart");
1161 

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