Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/tty/serial/msm_serial.c

  1 /*
  2  * Driver for msm7k serial device and console
  3  *
  4  * Copyright (C) 2007 Google, Inc.
  5  * Author: Robert Love <rlove@google.com>
  6  * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
  7  *
  8  * This software is licensed under the terms of the GNU General Public
  9  * License version 2, as published by the Free Software Foundation, and
 10  * may be copied, distributed, and modified under those terms.
 11  *
 12  * This program is distributed in the hope that it will be useful,
 13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 15  * GNU General Public License for more details.
 16  */
 17 
 18 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 19 # define SUPPORT_SYSRQ
 20 #endif
 21 
 22 #include <linux/atomic.h>
 23 #include <linux/hrtimer.h>
 24 #include <linux/module.h>
 25 #include <linux/io.h>
 26 #include <linux/ioport.h>
 27 #include <linux/irq.h>
 28 #include <linux/init.h>
 29 #include <linux/console.h>
 30 #include <linux/tty.h>
 31 #include <linux/tty_flip.h>
 32 #include <linux/serial_core.h>
 33 #include <linux/serial.h>
 34 #include <linux/clk.h>
 35 #include <linux/platform_device.h>
 36 #include <linux/delay.h>
 37 #include <linux/of.h>
 38 #include <linux/of_device.h>
 39 
 40 #include "msm_serial.h"
 41 
 42 enum {
 43         UARTDM_1P1 = 1,
 44         UARTDM_1P2,
 45         UARTDM_1P3,
 46         UARTDM_1P4,
 47 };
 48 
 49 struct msm_port {
 50         struct uart_port        uart;
 51         char                    name[16];
 52         struct clk              *clk;
 53         struct clk              *pclk;
 54         unsigned int            imr;
 55         int                     is_uartdm;
 56         unsigned int            old_snap_state;
 57 };
 58 
 59 static inline void wait_for_xmitr(struct uart_port *port)
 60 {
 61         while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
 62                 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
 63                         break;
 64                 udelay(1);
 65         }
 66         msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
 67 }
 68 
 69 static void msm_stop_tx(struct uart_port *port)
 70 {
 71         struct msm_port *msm_port = UART_TO_MSM(port);
 72 
 73         msm_port->imr &= ~UART_IMR_TXLEV;
 74         msm_write(port, msm_port->imr, UART_IMR);
 75 }
 76 
 77 static void msm_start_tx(struct uart_port *port)
 78 {
 79         struct msm_port *msm_port = UART_TO_MSM(port);
 80 
 81         msm_port->imr |= UART_IMR_TXLEV;
 82         msm_write(port, msm_port->imr, UART_IMR);
 83 }
 84 
 85 static void msm_stop_rx(struct uart_port *port)
 86 {
 87         struct msm_port *msm_port = UART_TO_MSM(port);
 88 
 89         msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
 90         msm_write(port, msm_port->imr, UART_IMR);
 91 }
 92 
 93 static void msm_enable_ms(struct uart_port *port)
 94 {
 95         struct msm_port *msm_port = UART_TO_MSM(port);
 96 
 97         msm_port->imr |= UART_IMR_DELTA_CTS;
 98         msm_write(port, msm_port->imr, UART_IMR);
 99 }
100 
101 static void handle_rx_dm(struct uart_port *port, unsigned int misr)
102 {
103         struct tty_port *tport = &port->state->port;
104         unsigned int sr;
105         int count = 0;
106         struct msm_port *msm_port = UART_TO_MSM(port);
107 
108         if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
109                 port->icount.overrun++;
110                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
111                 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
112         }
113 
114         if (misr & UART_IMR_RXSTALE) {
115                 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
116                         msm_port->old_snap_state;
117                 msm_port->old_snap_state = 0;
118         } else {
119                 count = 4 * (msm_read(port, UART_RFWR));
120                 msm_port->old_snap_state += count;
121         }
122 
123         /* TODO: Precise error reporting */
124 
125         port->icount.rx += count;
126 
127         while (count > 0) {
128                 unsigned char buf[4];
129 
130                 sr = msm_read(port, UART_SR);
131                 if ((sr & UART_SR_RX_READY) == 0) {
132                         msm_port->old_snap_state -= count;
133                         break;
134                 }
135                 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
136                 if (sr & UART_SR_RX_BREAK) {
137                         port->icount.brk++;
138                         if (uart_handle_break(port))
139                                 continue;
140                 } else if (sr & UART_SR_PAR_FRAME_ERR)
141                         port->icount.frame++;
142 
143                 /* TODO: handle sysrq */
144                 tty_insert_flip_string(tport, buf, min(count, 4));
145                 count -= 4;
146         }
147 
148         spin_unlock(&port->lock);
149         tty_flip_buffer_push(tport);
150         spin_lock(&port->lock);
151 
152         if (misr & (UART_IMR_RXSTALE))
153                 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
154         msm_write(port, 0xFFFFFF, UARTDM_DMRX);
155         msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
156 }
157 
158 static void handle_rx(struct uart_port *port)
159 {
160         struct tty_port *tport = &port->state->port;
161         unsigned int sr;
162 
163         /*
164          * Handle overrun. My understanding of the hardware is that overrun
165          * is not tied to the RX buffer, so we handle the case out of band.
166          */
167         if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
168                 port->icount.overrun++;
169                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
170                 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
171         }
172 
173         /* and now the main RX loop */
174         while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
175                 unsigned int c;
176                 char flag = TTY_NORMAL;
177 
178                 c = msm_read(port, UART_RF);
179 
180                 if (sr & UART_SR_RX_BREAK) {
181                         port->icount.brk++;
182                         if (uart_handle_break(port))
183                                 continue;
184                 } else if (sr & UART_SR_PAR_FRAME_ERR) {
185                         port->icount.frame++;
186                 } else {
187                         port->icount.rx++;
188                 }
189 
190                 /* Mask conditions we're ignorning. */
191                 sr &= port->read_status_mask;
192 
193                 if (sr & UART_SR_RX_BREAK) {
194                         flag = TTY_BREAK;
195                 } else if (sr & UART_SR_PAR_FRAME_ERR) {
196                         flag = TTY_FRAME;
197                 }
198 
199                 if (!uart_handle_sysrq_char(port, c))
200                         tty_insert_flip_char(tport, c, flag);
201         }
202 
203         spin_unlock(&port->lock);
204         tty_flip_buffer_push(tport);
205         spin_lock(&port->lock);
206 }
207 
208 static void reset_dm_count(struct uart_port *port, int count)
209 {
210         wait_for_xmitr(port);
211         msm_write(port, count, UARTDM_NCF_TX);
212         msm_read(port, UARTDM_NCF_TX);
213 }
214 
215 static void handle_tx(struct uart_port *port)
216 {
217         struct circ_buf *xmit = &port->state->xmit;
218         struct msm_port *msm_port = UART_TO_MSM(port);
219         unsigned int tx_count, num_chars;
220         unsigned int tf_pointer = 0;
221         void __iomem *tf;
222 
223         if (msm_port->is_uartdm)
224                 tf = port->membase + UARTDM_TF;
225         else
226                 tf = port->membase + UART_TF;
227 
228         tx_count = uart_circ_chars_pending(xmit);
229         tx_count = min3(tx_count, (unsigned int)UART_XMIT_SIZE - xmit->tail,
230                         port->fifosize);
231 
232         if (port->x_char) {
233                 if (msm_port->is_uartdm)
234                         reset_dm_count(port, tx_count + 1);
235 
236                 iowrite8_rep(tf, &port->x_char, 1);
237                 port->icount.tx++;
238                 port->x_char = 0;
239         } else if (tx_count && msm_port->is_uartdm) {
240                 reset_dm_count(port, tx_count);
241         }
242 
243         while (tf_pointer < tx_count) {
244                 int i;
245                 char buf[4] = { 0 };
246 
247                 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
248                         break;
249 
250                 if (msm_port->is_uartdm)
251                         num_chars = min(tx_count - tf_pointer,
252                                         (unsigned int)sizeof(buf));
253                 else
254                         num_chars = 1;
255 
256                 for (i = 0; i < num_chars; i++) {
257                         buf[i] = xmit->buf[xmit->tail + i];
258                         port->icount.tx++;
259                 }
260 
261                 iowrite32_rep(tf, buf, 1);
262                 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
263                 tf_pointer += num_chars;
264         }
265 
266         /* disable tx interrupts if nothing more to send */
267         if (uart_circ_empty(xmit))
268                 msm_stop_tx(port);
269 
270         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
271                 uart_write_wakeup(port);
272 }
273 
274 static void handle_delta_cts(struct uart_port *port)
275 {
276         msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
277         port->icount.cts++;
278         wake_up_interruptible(&port->state->port.delta_msr_wait);
279 }
280 
281 static irqreturn_t msm_irq(int irq, void *dev_id)
282 {
283         struct uart_port *port = dev_id;
284         struct msm_port *msm_port = UART_TO_MSM(port);
285         unsigned int misr;
286 
287         spin_lock(&port->lock);
288         misr = msm_read(port, UART_MISR);
289         msm_write(port, 0, UART_IMR); /* disable interrupt */
290 
291         if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
292                 if (msm_port->is_uartdm)
293                         handle_rx_dm(port, misr);
294                 else
295                         handle_rx(port);
296         }
297         if (misr & UART_IMR_TXLEV)
298                 handle_tx(port);
299         if (misr & UART_IMR_DELTA_CTS)
300                 handle_delta_cts(port);
301 
302         msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
303         spin_unlock(&port->lock);
304 
305         return IRQ_HANDLED;
306 }
307 
308 static unsigned int msm_tx_empty(struct uart_port *port)
309 {
310         return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
311 }
312 
313 static unsigned int msm_get_mctrl(struct uart_port *port)
314 {
315         return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
316 }
317 
318 
319 static void msm_reset(struct uart_port *port)
320 {
321         struct msm_port *msm_port = UART_TO_MSM(port);
322 
323         /* reset everything */
324         msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
325         msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
326         msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
327         msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
328         msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
329         msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
330 
331         /* Disable DM modes */
332         if (msm_port->is_uartdm)
333                 msm_write(port, 0, UARTDM_DMEN);
334 }
335 
336 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
337 {
338         unsigned int mr;
339         mr = msm_read(port, UART_MR1);
340 
341         if (!(mctrl & TIOCM_RTS)) {
342                 mr &= ~UART_MR1_RX_RDY_CTL;
343                 msm_write(port, mr, UART_MR1);
344                 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
345         } else {
346                 mr |= UART_MR1_RX_RDY_CTL;
347                 msm_write(port, mr, UART_MR1);
348         }
349 }
350 
351 static void msm_break_ctl(struct uart_port *port, int break_ctl)
352 {
353         if (break_ctl)
354                 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
355         else
356                 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
357 }
358 
359 struct msm_baud_map {
360         u16     divisor;
361         u8      code;
362         u8      rxstale;
363 };
364 
365 static const struct msm_baud_map *
366 msm_find_best_baud(struct uart_port *port, unsigned int baud)
367 {
368         unsigned int i, divisor;
369         const struct msm_baud_map *entry;
370         static const struct msm_baud_map table[] = {
371                 { 1536, 0x00,  1 },
372                 {  768, 0x11,  1 },
373                 {  384, 0x22,  1 },
374                 {  192, 0x33,  1 },
375                 {   96, 0x44,  1 },
376                 {   48, 0x55,  1 },
377                 {   32, 0x66,  1 },
378                 {   24, 0x77,  1 },
379                 {   16, 0x88,  1 },
380                 {   12, 0x99,  6 },
381                 {    8, 0xaa,  6 },
382                 {    6, 0xbb,  6 },
383                 {    4, 0xcc,  6 },
384                 {    3, 0xdd,  8 },
385                 {    2, 0xee, 16 },
386                 {    1, 0xff, 31 },
387         };
388 
389         divisor = uart_get_divisor(port, baud);
390 
391         for (i = 0, entry = table; i < ARRAY_SIZE(table); i++, entry++)
392                 if (entry->divisor <= divisor)
393                         break;
394 
395         return entry; /* Default to smallest divider */
396 }
397 
398 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
399 {
400         unsigned int rxstale, watermark;
401         struct msm_port *msm_port = UART_TO_MSM(port);
402         const struct msm_baud_map *entry;
403 
404         entry = msm_find_best_baud(port, baud);
405 
406         if (msm_port->is_uartdm)
407                 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
408 
409         msm_write(port, entry->code, UART_CSR);
410 
411         /* RX stale watermark */
412         rxstale = entry->rxstale;
413         watermark = UART_IPR_STALE_LSB & rxstale;
414         watermark |= UART_IPR_RXSTALE_LAST;
415         watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
416         msm_write(port, watermark, UART_IPR);
417 
418         /* set RX watermark */
419         watermark = (port->fifosize * 3) / 4;
420         msm_write(port, watermark, UART_RFWR);
421 
422         /* set TX watermark */
423         msm_write(port, 10, UART_TFWR);
424 
425         if (msm_port->is_uartdm) {
426                 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
427                 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
428                 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
429         }
430 
431         return baud;
432 }
433 
434 
435 static void msm_init_clock(struct uart_port *port)
436 {
437         struct msm_port *msm_port = UART_TO_MSM(port);
438 
439         clk_prepare_enable(msm_port->clk);
440         clk_prepare_enable(msm_port->pclk);
441         msm_serial_set_mnd_regs(port);
442 }
443 
444 static int msm_startup(struct uart_port *port)
445 {
446         struct msm_port *msm_port = UART_TO_MSM(port);
447         unsigned int data, rfr_level;
448         int ret;
449 
450         snprintf(msm_port->name, sizeof(msm_port->name),
451                  "msm_serial%d", port->line);
452 
453         ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
454                           msm_port->name, port);
455         if (unlikely(ret))
456                 return ret;
457 
458         msm_init_clock(port);
459 
460         if (likely(port->fifosize > 12))
461                 rfr_level = port->fifosize - 12;
462         else
463                 rfr_level = port->fifosize;
464 
465         /* set automatic RFR level */
466         data = msm_read(port, UART_MR1);
467         data &= ~UART_MR1_AUTO_RFR_LEVEL1;
468         data &= ~UART_MR1_AUTO_RFR_LEVEL0;
469         data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
470         data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
471         msm_write(port, data, UART_MR1);
472 
473         /* make sure that RXSTALE count is non-zero */
474         data = msm_read(port, UART_IPR);
475         if (unlikely(!data)) {
476                 data |= UART_IPR_RXSTALE_LAST;
477                 data |= UART_IPR_STALE_LSB;
478                 msm_write(port, data, UART_IPR);
479         }
480 
481         data = 0;
482         if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) {
483                 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
484                 msm_reset(port);
485                 data = UART_CR_TX_ENABLE;
486         }
487 
488         data |= UART_CR_RX_ENABLE;
489         msm_write(port, data, UART_CR); /* enable TX & RX */
490 
491         /* Make sure IPR is not 0 to start with*/
492         if (msm_port->is_uartdm)
493                 msm_write(port, UART_IPR_STALE_LSB, UART_IPR);
494 
495         /* turn on RX and CTS interrupts */
496         msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
497                         UART_IMR_CURRENT_CTS;
498 
499         if (msm_port->is_uartdm) {
500                 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
501                 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
502                 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
503         }
504 
505         msm_write(port, msm_port->imr, UART_IMR);
506         return 0;
507 }
508 
509 static void msm_shutdown(struct uart_port *port)
510 {
511         struct msm_port *msm_port = UART_TO_MSM(port);
512 
513         msm_port->imr = 0;
514         msm_write(port, 0, UART_IMR); /* disable interrupts */
515 
516         clk_disable_unprepare(msm_port->clk);
517 
518         free_irq(port->irq, port);
519 }
520 
521 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
522                             struct ktermios *old)
523 {
524         unsigned long flags;
525         unsigned int baud, mr;
526 
527         spin_lock_irqsave(&port->lock, flags);
528 
529         /* calculate and set baud rate */
530         baud = uart_get_baud_rate(port, termios, old, 300, 115200);
531         baud = msm_set_baud_rate(port, baud);
532         if (tty_termios_baud_rate(termios))
533                 tty_termios_encode_baud_rate(termios, baud, baud);
534 
535         /* calculate parity */
536         mr = msm_read(port, UART_MR2);
537         mr &= ~UART_MR2_PARITY_MODE;
538         if (termios->c_cflag & PARENB) {
539                 if (termios->c_cflag & PARODD)
540                         mr |= UART_MR2_PARITY_MODE_ODD;
541                 else if (termios->c_cflag & CMSPAR)
542                         mr |= UART_MR2_PARITY_MODE_SPACE;
543                 else
544                         mr |= UART_MR2_PARITY_MODE_EVEN;
545         }
546 
547         /* calculate bits per char */
548         mr &= ~UART_MR2_BITS_PER_CHAR;
549         switch (termios->c_cflag & CSIZE) {
550         case CS5:
551                 mr |= UART_MR2_BITS_PER_CHAR_5;
552                 break;
553         case CS6:
554                 mr |= UART_MR2_BITS_PER_CHAR_6;
555                 break;
556         case CS7:
557                 mr |= UART_MR2_BITS_PER_CHAR_7;
558                 break;
559         case CS8:
560         default:
561                 mr |= UART_MR2_BITS_PER_CHAR_8;
562                 break;
563         }
564 
565         /* calculate stop bits */
566         mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
567         if (termios->c_cflag & CSTOPB)
568                 mr |= UART_MR2_STOP_BIT_LEN_TWO;
569         else
570                 mr |= UART_MR2_STOP_BIT_LEN_ONE;
571 
572         /* set parity, bits per char, and stop bit */
573         msm_write(port, mr, UART_MR2);
574 
575         /* calculate and set hardware flow control */
576         mr = msm_read(port, UART_MR1);
577         mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
578         if (termios->c_cflag & CRTSCTS) {
579                 mr |= UART_MR1_CTS_CTL;
580                 mr |= UART_MR1_RX_RDY_CTL;
581         }
582         msm_write(port, mr, UART_MR1);
583 
584         /* Configure status bits to ignore based on termio flags. */
585         port->read_status_mask = 0;
586         if (termios->c_iflag & INPCK)
587                 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
588         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
589                 port->read_status_mask |= UART_SR_RX_BREAK;
590 
591         uart_update_timeout(port, termios->c_cflag, baud);
592 
593         spin_unlock_irqrestore(&port->lock, flags);
594 }
595 
596 static const char *msm_type(struct uart_port *port)
597 {
598         return "MSM";
599 }
600 
601 static void msm_release_port(struct uart_port *port)
602 {
603         struct platform_device *pdev = to_platform_device(port->dev);
604         struct resource *uart_resource;
605         resource_size_t size;
606 
607         uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
608         if (unlikely(!uart_resource))
609                 return;
610         size = resource_size(uart_resource);
611 
612         release_mem_region(port->mapbase, size);
613         iounmap(port->membase);
614         port->membase = NULL;
615 }
616 
617 static int msm_request_port(struct uart_port *port)
618 {
619         struct platform_device *pdev = to_platform_device(port->dev);
620         struct resource *uart_resource;
621         resource_size_t size;
622         int ret;
623 
624         uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
625         if (unlikely(!uart_resource))
626                 return -ENXIO;
627 
628         size = resource_size(uart_resource);
629 
630         if (!request_mem_region(port->mapbase, size, "msm_serial"))
631                 return -EBUSY;
632 
633         port->membase = ioremap(port->mapbase, size);
634         if (!port->membase) {
635                 ret = -EBUSY;
636                 goto fail_release_port;
637         }
638 
639         return 0;
640 
641 fail_release_port:
642         release_mem_region(port->mapbase, size);
643         return ret;
644 }
645 
646 static void msm_config_port(struct uart_port *port, int flags)
647 {
648         int ret;
649         if (flags & UART_CONFIG_TYPE) {
650                 port->type = PORT_MSM;
651                 ret = msm_request_port(port);
652                 if (ret)
653                         return;
654         }
655 }
656 
657 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
658 {
659         if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
660                 return -EINVAL;
661         if (unlikely(port->irq != ser->irq))
662                 return -EINVAL;
663         return 0;
664 }
665 
666 static void msm_power(struct uart_port *port, unsigned int state,
667                       unsigned int oldstate)
668 {
669         struct msm_port *msm_port = UART_TO_MSM(port);
670 
671         switch (state) {
672         case 0:
673                 clk_prepare_enable(msm_port->clk);
674                 clk_prepare_enable(msm_port->pclk);
675                 break;
676         case 3:
677                 clk_disable_unprepare(msm_port->clk);
678                 clk_disable_unprepare(msm_port->pclk);
679                 break;
680         default:
681                 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
682         }
683 }
684 
685 #ifdef CONFIG_CONSOLE_POLL
686 static int msm_poll_init(struct uart_port *port)
687 {
688         struct msm_port *msm_port = UART_TO_MSM(port);
689 
690         /* Enable single character mode on RX FIFO */
691         if (msm_port->is_uartdm >= UARTDM_1P4)
692                 msm_write(port, UARTDM_DMEN_RX_SC_ENABLE, UARTDM_DMEN);
693 
694         return 0;
695 }
696 
697 static int msm_poll_get_char_single(struct uart_port *port)
698 {
699         struct msm_port *msm_port = UART_TO_MSM(port);
700         unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
701 
702         if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
703                 return NO_POLL_CHAR;
704         else
705                 return msm_read(port, rf_reg) & 0xff;
706 }
707 
708 static int msm_poll_get_char_dm_1p3(struct uart_port *port)
709 {
710         int c;
711         static u32 slop;
712         static int count;
713         unsigned char *sp = (unsigned char *)&slop;
714 
715         /* Check if a previous read had more than one char */
716         if (count) {
717                 c = sp[sizeof(slop) - count];
718                 count--;
719         /* Or if FIFO is empty */
720         } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
721                 /*
722                  * If RX packing buffer has less than a word, force stale to
723                  * push contents into RX FIFO
724                  */
725                 count = msm_read(port, UARTDM_RXFS);
726                 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
727                 if (count) {
728                         msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
729                         slop = msm_read(port, UARTDM_RF);
730                         c = sp[0];
731                         count--;
732                 } else {
733                         c = NO_POLL_CHAR;
734                 }
735         /* FIFO has a word */
736         } else {
737                 slop = msm_read(port, UARTDM_RF);
738                 c = sp[0];
739                 count = sizeof(slop) - 1;
740         }
741 
742         return c;
743 }
744 
745 static int msm_poll_get_char(struct uart_port *port)
746 {
747         u32 imr;
748         int c;
749         struct msm_port *msm_port = UART_TO_MSM(port);
750 
751         /* Disable all interrupts */
752         imr = msm_read(port, UART_IMR);
753         msm_write(port, 0, UART_IMR);
754 
755         if (msm_port->is_uartdm == UARTDM_1P3)
756                 c = msm_poll_get_char_dm_1p3(port);
757         else
758                 c = msm_poll_get_char_single(port);
759 
760         /* Enable interrupts */
761         msm_write(port, imr, UART_IMR);
762 
763         return c;
764 }
765 
766 static void msm_poll_put_char(struct uart_port *port, unsigned char c)
767 {
768         u32 imr;
769         struct msm_port *msm_port = UART_TO_MSM(port);
770 
771         /* Disable all interrupts */
772         imr = msm_read(port, UART_IMR);
773         msm_write(port, 0, UART_IMR);
774 
775         if (msm_port->is_uartdm)
776                 reset_dm_count(port, 1);
777 
778         /* Wait until FIFO is empty */
779         while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
780                 cpu_relax();
781 
782         /* Write a character */
783         msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
784 
785         /* Wait until FIFO is empty */
786         while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
787                 cpu_relax();
788 
789         /* Enable interrupts */
790         msm_write(port, imr, UART_IMR);
791 
792         return;
793 }
794 #endif
795 
796 static struct uart_ops msm_uart_pops = {
797         .tx_empty = msm_tx_empty,
798         .set_mctrl = msm_set_mctrl,
799         .get_mctrl = msm_get_mctrl,
800         .stop_tx = msm_stop_tx,
801         .start_tx = msm_start_tx,
802         .stop_rx = msm_stop_rx,
803         .enable_ms = msm_enable_ms,
804         .break_ctl = msm_break_ctl,
805         .startup = msm_startup,
806         .shutdown = msm_shutdown,
807         .set_termios = msm_set_termios,
808         .type = msm_type,
809         .release_port = msm_release_port,
810         .request_port = msm_request_port,
811         .config_port = msm_config_port,
812         .verify_port = msm_verify_port,
813         .pm = msm_power,
814 #ifdef CONFIG_CONSOLE_POLL
815         .poll_init = msm_poll_init,
816         .poll_get_char  = msm_poll_get_char,
817         .poll_put_char  = msm_poll_put_char,
818 #endif
819 };
820 
821 static struct msm_port msm_uart_ports[] = {
822         {
823                 .uart = {
824                         .iotype = UPIO_MEM,
825                         .ops = &msm_uart_pops,
826                         .flags = UPF_BOOT_AUTOCONF,
827                         .fifosize = 64,
828                         .line = 0,
829                 },
830         },
831         {
832                 .uart = {
833                         .iotype = UPIO_MEM,
834                         .ops = &msm_uart_pops,
835                         .flags = UPF_BOOT_AUTOCONF,
836                         .fifosize = 64,
837                         .line = 1,
838                 },
839         },
840         {
841                 .uart = {
842                         .iotype = UPIO_MEM,
843                         .ops = &msm_uart_pops,
844                         .flags = UPF_BOOT_AUTOCONF,
845                         .fifosize = 64,
846                         .line = 2,
847                 },
848         },
849 };
850 
851 #define UART_NR ARRAY_SIZE(msm_uart_ports)
852 
853 static inline struct uart_port *get_port_from_line(unsigned int line)
854 {
855         return &msm_uart_ports[line].uart;
856 }
857 
858 #ifdef CONFIG_SERIAL_MSM_CONSOLE
859 static void msm_console_write(struct console *co, const char *s,
860                               unsigned int count)
861 {
862         int i;
863         struct uart_port *port;
864         struct msm_port *msm_port;
865         int num_newlines = 0;
866         bool replaced = false;
867         void __iomem *tf;
868 
869         BUG_ON(co->index < 0 || co->index >= UART_NR);
870 
871         port = get_port_from_line(co->index);
872         msm_port = UART_TO_MSM(port);
873 
874         if (msm_port->is_uartdm)
875                 tf = port->membase + UARTDM_TF;
876         else
877                 tf = port->membase + UART_TF;
878 
879         /* Account for newlines that will get a carriage return added */
880         for (i = 0; i < count; i++)
881                 if (s[i] == '\n')
882                         num_newlines++;
883         count += num_newlines;
884 
885         spin_lock(&port->lock);
886         if (msm_port->is_uartdm)
887                 reset_dm_count(port, count);
888 
889         i = 0;
890         while (i < count) {
891                 int j;
892                 unsigned int num_chars;
893                 char buf[4] = { 0 };
894 
895                 if (msm_port->is_uartdm)
896                         num_chars = min(count - i, (unsigned int)sizeof(buf));
897                 else
898                         num_chars = 1;
899 
900                 for (j = 0; j < num_chars; j++) {
901                         char c = *s;
902 
903                         if (c == '\n' && !replaced) {
904                                 buf[j] = '\r';
905                                 j++;
906                                 replaced = true;
907                         }
908                         if (j < num_chars) {
909                                 buf[j] = c;
910                                 s++;
911                                 replaced = false;
912                         }
913                 }
914 
915                 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
916                         cpu_relax();
917 
918                 iowrite32_rep(tf, buf, 1);
919                 i += num_chars;
920         }
921         spin_unlock(&port->lock);
922 }
923 
924 static int __init msm_console_setup(struct console *co, char *options)
925 {
926         struct uart_port *port;
927         struct msm_port *msm_port;
928         int baud = 0, flow, bits, parity;
929 
930         if (unlikely(co->index >= UART_NR || co->index < 0))
931                 return -ENXIO;
932 
933         port = get_port_from_line(co->index);
934         msm_port = UART_TO_MSM(port);
935 
936         if (unlikely(!port->membase))
937                 return -ENXIO;
938 
939         msm_init_clock(port);
940 
941         if (options)
942                 uart_parse_options(options, &baud, &parity, &bits, &flow);
943 
944         bits = 8;
945         parity = 'n';
946         flow = 'n';
947         msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
948                   UART_MR2);    /* 8N1 */
949 
950         if (baud < 300 || baud > 115200)
951                 baud = 115200;
952         msm_set_baud_rate(port, baud);
953 
954         msm_reset(port);
955 
956         if (msm_port->is_uartdm) {
957                 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
958                 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
959         }
960 
961         printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
962 
963         return uart_set_options(port, co, baud, parity, bits, flow);
964 }
965 
966 static struct uart_driver msm_uart_driver;
967 
968 static struct console msm_console = {
969         .name = "ttyMSM",
970         .write = msm_console_write,
971         .device = uart_console_device,
972         .setup = msm_console_setup,
973         .flags = CON_PRINTBUFFER,
974         .index = -1,
975         .data = &msm_uart_driver,
976 };
977 
978 #define MSM_CONSOLE     (&msm_console)
979 
980 #else
981 #define MSM_CONSOLE     NULL
982 #endif
983 
984 static struct uart_driver msm_uart_driver = {
985         .owner = THIS_MODULE,
986         .driver_name = "msm_serial",
987         .dev_name = "ttyMSM",
988         .nr = UART_NR,
989         .cons = MSM_CONSOLE,
990 };
991 
992 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
993 
994 static const struct of_device_id msm_uartdm_table[] = {
995         { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
996         { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
997         { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
998         { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
999         { }
1000 };
1001 
1002 static int msm_serial_probe(struct platform_device *pdev)
1003 {
1004         struct msm_port *msm_port;
1005         struct resource *resource;
1006         struct uart_port *port;
1007         const struct of_device_id *id;
1008         int irq;
1009 
1010         if (pdev->id == -1)
1011                 pdev->id = atomic_inc_return(&msm_uart_next_id) - 1;
1012 
1013         if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
1014                 return -ENXIO;
1015 
1016         printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id);
1017 
1018         port = get_port_from_line(pdev->id);
1019         port->dev = &pdev->dev;
1020         msm_port = UART_TO_MSM(port);
1021 
1022         id = of_match_device(msm_uartdm_table, &pdev->dev);
1023         if (id)
1024                 msm_port->is_uartdm = (unsigned long)id->data;
1025         else
1026                 msm_port->is_uartdm = 0;
1027 
1028         msm_port->clk = devm_clk_get(&pdev->dev, "core");
1029         if (IS_ERR(msm_port->clk))
1030                 return PTR_ERR(msm_port->clk);
1031 
1032         if (msm_port->is_uartdm) {
1033                 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1034                 if (IS_ERR(msm_port->pclk))
1035                         return PTR_ERR(msm_port->pclk);
1036 
1037                 clk_set_rate(msm_port->clk, 1843200);
1038         }
1039 
1040         port->uartclk = clk_get_rate(msm_port->clk);
1041         printk(KERN_INFO "uartclk = %d\n", port->uartclk);
1042 
1043 
1044         resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1045         if (unlikely(!resource))
1046                 return -ENXIO;
1047         port->mapbase = resource->start;
1048 
1049         irq = platform_get_irq(pdev, 0);
1050         if (unlikely(irq < 0))
1051                 return -ENXIO;
1052         port->irq = irq;
1053 
1054         platform_set_drvdata(pdev, port);
1055 
1056         return uart_add_one_port(&msm_uart_driver, port);
1057 }
1058 
1059 static int msm_serial_remove(struct platform_device *pdev)
1060 {
1061         struct uart_port *port = platform_get_drvdata(pdev);
1062 
1063         uart_remove_one_port(&msm_uart_driver, port);
1064 
1065         return 0;
1066 }
1067 
1068 static const struct of_device_id msm_match_table[] = {
1069         { .compatible = "qcom,msm-uart" },
1070         { .compatible = "qcom,msm-uartdm" },
1071         {}
1072 };
1073 
1074 static struct platform_driver msm_platform_driver = {
1075         .remove = msm_serial_remove,
1076         .probe = msm_serial_probe,
1077         .driver = {
1078                 .name = "msm_serial",
1079                 .owner = THIS_MODULE,
1080                 .of_match_table = msm_match_table,
1081         },
1082 };
1083 
1084 static int __init msm_serial_init(void)
1085 {
1086         int ret;
1087 
1088         ret = uart_register_driver(&msm_uart_driver);
1089         if (unlikely(ret))
1090                 return ret;
1091 
1092         ret = platform_driver_register(&msm_platform_driver);
1093         if (unlikely(ret))
1094                 uart_unregister_driver(&msm_uart_driver);
1095 
1096         printk(KERN_INFO "msm_serial: driver initialized\n");
1097 
1098         return ret;
1099 }
1100 
1101 static void __exit msm_serial_exit(void)
1102 {
1103 #ifdef CONFIG_SERIAL_MSM_CONSOLE
1104         unregister_console(&msm_console);
1105 #endif
1106         platform_driver_unregister(&msm_platform_driver);
1107         uart_unregister_driver(&msm_uart_driver);
1108 }
1109 
1110 module_init(msm_serial_init);
1111 module_exit(msm_serial_exit);
1112 
1113 MODULE_AUTHOR("Robert Love <rlove@google.com>");
1114 MODULE_DESCRIPTION("Driver for msm7x serial device");
1115 MODULE_LICENSE("GPL");
1116 

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