Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/tty/serial/mfd.c

  1 /*
  2  * mfd.c: driver for High Speed UART device of Intel Medfield platform
  3  *
  4  * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
  5  *
  6  * (C) Copyright 2010 Intel Corporation
  7  *
  8  * This program is free software; you can redistribute it and/or
  9  * modify it under the terms of the GNU General Public License
 10  * as published by the Free Software Foundation; version 2
 11  * of the License.
 12  */
 13 
 14 /* Notes:
 15  * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
 16  *    2/3 chan to port 1, 4/5 chan to port 3. Even number chans
 17  *    are used for RX, odd chans for TX
 18  *
 19  * 2. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
 20  *    asserted, only when the HW is reset the DDCD and DDSR will
 21  *    be triggered
 22  */
 23 
 24 #if defined(CONFIG_SERIAL_MFD_HSU_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 25 #define SUPPORT_SYSRQ
 26 #endif
 27 
 28 #include <linux/module.h>
 29 #include <linux/init.h>
 30 #include <linux/console.h>
 31 #include <linux/sysrq.h>
 32 #include <linux/slab.h>
 33 #include <linux/serial_reg.h>
 34 #include <linux/circ_buf.h>
 35 #include <linux/delay.h>
 36 #include <linux/interrupt.h>
 37 #include <linux/tty.h>
 38 #include <linux/tty_flip.h>
 39 #include <linux/serial_core.h>
 40 #include <linux/serial_mfd.h>
 41 #include <linux/dma-mapping.h>
 42 #include <linux/pci.h>
 43 #include <linux/nmi.h>
 44 #include <linux/io.h>
 45 #include <linux/debugfs.h>
 46 #include <linux/pm_runtime.h>
 47 
 48 #define HSU_DMA_BUF_SIZE        2048
 49 
 50 #define chan_readl(chan, offset)        readl(chan->reg + offset)
 51 #define chan_writel(chan, offset, val)  writel(val, chan->reg + offset)
 52 
 53 #define mfd_readl(obj, offset)          readl(obj->reg + offset)
 54 #define mfd_writel(obj, offset, val)    writel(val, obj->reg + offset)
 55 
 56 static int hsu_dma_enable;
 57 module_param(hsu_dma_enable, int, 0);
 58 MODULE_PARM_DESC(hsu_dma_enable,
 59                  "It is a bitmap to set working mode, if bit[x] is 1, then port[x] will work in DMA mode, otherwise in PIO mode.");
 60 
 61 struct hsu_dma_buffer {
 62         u8              *buf;
 63         dma_addr_t      dma_addr;
 64         u32             dma_size;
 65         u32             ofs;
 66 };
 67 
 68 struct hsu_dma_chan {
 69         u32     id;
 70         enum dma_data_direction dirt;
 71         struct uart_hsu_port    *uport;
 72         void __iomem            *reg;
 73 };
 74 
 75 struct uart_hsu_port {
 76         struct uart_port        port;
 77         unsigned char           ier;
 78         unsigned char           lcr;
 79         unsigned char           mcr;
 80         unsigned int            lsr_break_flag;
 81         char                    name[12];
 82         int                     index;
 83         struct device           *dev;
 84 
 85         struct hsu_dma_chan     *txc;
 86         struct hsu_dma_chan     *rxc;
 87         struct hsu_dma_buffer   txbuf;
 88         struct hsu_dma_buffer   rxbuf;
 89         int                     use_dma;        /* flag for DMA/PIO */
 90         int                     running;
 91         int                     dma_tx_on;
 92 };
 93 
 94 /* Top level data structure of HSU */
 95 struct hsu_port {
 96         void __iomem    *reg;
 97         unsigned long   paddr;
 98         unsigned long   iolen;
 99         u32             irq;
100 
101         struct uart_hsu_port    port[3];
102         struct hsu_dma_chan     chans[10];
103 
104         struct dentry *debugfs;
105 };
106 
107 static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
108 {
109         unsigned int val;
110 
111         if (offset > UART_MSR) {
112                 offset <<= 2;
113                 val = readl(up->port.membase + offset);
114         } else
115                 val = (unsigned int)readb(up->port.membase + offset);
116 
117         return val;
118 }
119 
120 static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
121 {
122         if (offset > UART_MSR) {
123                 offset <<= 2;
124                 writel(value, up->port.membase + offset);
125         } else {
126                 unsigned char val = value & 0xff;
127                 writeb(val, up->port.membase + offset);
128         }
129 }
130 
131 #ifdef CONFIG_DEBUG_FS
132 
133 #define HSU_REGS_BUFSIZE        1024
134 
135 
136 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
137                                 size_t count, loff_t *ppos)
138 {
139         struct uart_hsu_port *up = file->private_data;
140         char *buf;
141         u32 len = 0;
142         ssize_t ret;
143 
144         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
145         if (!buf)
146                 return 0;
147 
148         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
149                         "MFD HSU port[%d] regs:\n", up->index);
150 
151         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
152                         "=================================\n");
153         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
154                         "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
155         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
156                         "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
157         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
158                         "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
159         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
160                         "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
161         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
162                         "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
163         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
164                         "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
165         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
166                         "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
167         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
168                         "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
169         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
170                         "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
171         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
172                         "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
173 
174         if (len > HSU_REGS_BUFSIZE)
175                 len = HSU_REGS_BUFSIZE;
176 
177         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
178         kfree(buf);
179         return ret;
180 }
181 
182 static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
183                                 size_t count, loff_t *ppos)
184 {
185         struct hsu_dma_chan *chan = file->private_data;
186         char *buf;
187         u32 len = 0;
188         ssize_t ret;
189 
190         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
191         if (!buf)
192                 return 0;
193 
194         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
195                         "MFD HSU DMA channel [%d] regs:\n", chan->id);
196 
197         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
198                         "=================================\n");
199         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
200                         "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
201         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
202                         "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
203         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
204                         "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
205         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
206                         "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
207         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
208                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
209         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
210                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
211         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
212                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
213         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
214                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
215         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
216                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
217         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
218                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
219         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
220                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
221         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
222                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
223 
224         if (len > HSU_REGS_BUFSIZE)
225                 len = HSU_REGS_BUFSIZE;
226 
227         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
228         kfree(buf);
229         return ret;
230 }
231 
232 static const struct file_operations port_regs_ops = {
233         .owner          = THIS_MODULE,
234         .open           = simple_open,
235         .read           = port_show_regs,
236         .llseek         = default_llseek,
237 };
238 
239 static const struct file_operations dma_regs_ops = {
240         .owner          = THIS_MODULE,
241         .open           = simple_open,
242         .read           = dma_show_regs,
243         .llseek         = default_llseek,
244 };
245 
246 static int hsu_debugfs_init(struct hsu_port *hsu)
247 {
248         int i;
249         char name[32];
250 
251         hsu->debugfs = debugfs_create_dir("hsu", NULL);
252         if (!hsu->debugfs)
253                 return -ENOMEM;
254 
255         for (i = 0; i < 3; i++) {
256                 snprintf(name, sizeof(name), "port_%d_regs", i);
257                 debugfs_create_file(name, S_IFREG | S_IRUGO,
258                         hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
259         }
260 
261         for (i = 0; i < 6; i++) {
262                 snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
263                 debugfs_create_file(name, S_IFREG | S_IRUGO,
264                         hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
265         }
266 
267         return 0;
268 }
269 
270 static void hsu_debugfs_remove(struct hsu_port *hsu)
271 {
272         if (hsu->debugfs)
273                 debugfs_remove_recursive(hsu->debugfs);
274 }
275 
276 #else
277 static inline int hsu_debugfs_init(struct hsu_port *hsu)
278 {
279         return 0;
280 }
281 
282 static inline void hsu_debugfs_remove(struct hsu_port *hsu)
283 {
284 }
285 #endif /* CONFIG_DEBUG_FS */
286 
287 static void serial_hsu_enable_ms(struct uart_port *port)
288 {
289         struct uart_hsu_port *up =
290                 container_of(port, struct uart_hsu_port, port);
291 
292         up->ier |= UART_IER_MSI;
293         serial_out(up, UART_IER, up->ier);
294 }
295 
296 static void hsu_dma_tx(struct uart_hsu_port *up)
297 {
298         struct circ_buf *xmit = &up->port.state->xmit;
299         struct hsu_dma_buffer *dbuf = &up->txbuf;
300         int count;
301 
302         /* test_and_set_bit may be better, but anyway it's in lock protected mode */
303         if (up->dma_tx_on)
304                 return;
305 
306         /* Update the circ buf info */
307         xmit->tail += dbuf->ofs;
308         xmit->tail &= UART_XMIT_SIZE - 1;
309 
310         up->port.icount.tx += dbuf->ofs;
311         dbuf->ofs = 0;
312 
313         /* Disable the channel */
314         chan_writel(up->txc, HSU_CH_CR, 0x0);
315 
316         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
317                 dma_sync_single_for_device(up->port.dev,
318                                            dbuf->dma_addr,
319                                            dbuf->dma_size,
320                                            DMA_TO_DEVICE);
321 
322                 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
323                 dbuf->ofs = count;
324 
325                 /* Reprogram the channel */
326                 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
327                 chan_writel(up->txc, HSU_CH_D0TSR, count);
328 
329                 /* Reenable the channel */
330                 chan_writel(up->txc, HSU_CH_DCR, 0x1
331                                                  | (0x1 << 8)
332                                                  | (0x1 << 16)
333                                                  | (0x1 << 24));
334                 up->dma_tx_on = 1;
335                 chan_writel(up->txc, HSU_CH_CR, 0x1);
336         }
337 
338         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
339                 uart_write_wakeup(&up->port);
340 }
341 
342 /* The buffer is already cache coherent */
343 static void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc,
344                                         struct hsu_dma_buffer *dbuf)
345 {
346         dbuf->ofs = 0;
347 
348         chan_writel(rxc, HSU_CH_BSR, 32);
349         chan_writel(rxc, HSU_CH_MOTSR, 4);
350 
351         chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
352         chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
353         chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
354                                          | (0x1 << 16)
355                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
356                                          );
357         chan_writel(rxc, HSU_CH_CR, 0x3);
358 }
359 
360 /* Protected by spin_lock_irqsave(port->lock) */
361 static void serial_hsu_start_tx(struct uart_port *port)
362 {
363         struct uart_hsu_port *up =
364                 container_of(port, struct uart_hsu_port, port);
365 
366         if (up->use_dma) {
367                 hsu_dma_tx(up);
368         } else if (!(up->ier & UART_IER_THRI)) {
369                 up->ier |= UART_IER_THRI;
370                 serial_out(up, UART_IER, up->ier);
371         }
372 }
373 
374 static void serial_hsu_stop_tx(struct uart_port *port)
375 {
376         struct uart_hsu_port *up =
377                 container_of(port, struct uart_hsu_port, port);
378         struct hsu_dma_chan *txc = up->txc;
379 
380         if (up->use_dma)
381                 chan_writel(txc, HSU_CH_CR, 0x0);
382         else if (up->ier & UART_IER_THRI) {
383                 up->ier &= ~UART_IER_THRI;
384                 serial_out(up, UART_IER, up->ier);
385         }
386 }
387 
388 /* This is always called in spinlock protected mode, so
389  * modify timeout timer is safe here */
390 static void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts,
391                         unsigned long *flags)
392 {
393         struct hsu_dma_buffer *dbuf = &up->rxbuf;
394         struct hsu_dma_chan *chan = up->rxc;
395         struct uart_port *port = &up->port;
396         struct tty_port *tport = &port->state->port;
397         int count;
398 
399         /*
400          * First need to know how many is already transferred,
401          * then check if its a timeout DMA irq, and return
402          * the trail bytes out, push them up and reenable the
403          * channel
404          */
405 
406         /* Timeout IRQ, need wait some time, see Errata 2 */
407         if (int_sts & 0xf00)
408                 udelay(2);
409 
410         /* Stop the channel */
411         chan_writel(chan, HSU_CH_CR, 0x0);
412 
413         count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
414         if (!count) {
415                 /* Restart the channel before we leave */
416                 chan_writel(chan, HSU_CH_CR, 0x3);
417                 return;
418         }
419 
420         dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
421                         dbuf->dma_size, DMA_FROM_DEVICE);
422 
423         /*
424          * Head will only wrap around when we recycle
425          * the DMA buffer, and when that happens, we
426          * explicitly set tail to 0. So head will
427          * always be greater than tail.
428          */
429         tty_insert_flip_string(tport, dbuf->buf, count);
430         port->icount.rx += count;
431 
432         dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
433                         dbuf->dma_size, DMA_FROM_DEVICE);
434 
435         /* Reprogram the channel */
436         chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
437         chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
438         chan_writel(chan, HSU_CH_DCR, 0x1
439                                          | (0x1 << 8)
440                                          | (0x1 << 16)
441                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
442                                          );
443         spin_unlock_irqrestore(&up->port.lock, *flags);
444         tty_flip_buffer_push(tport);
445         spin_lock_irqsave(&up->port.lock, *flags);
446 
447         chan_writel(chan, HSU_CH_CR, 0x3);
448 
449 }
450 
451 static void serial_hsu_stop_rx(struct uart_port *port)
452 {
453         struct uart_hsu_port *up =
454                 container_of(port, struct uart_hsu_port, port);
455         struct hsu_dma_chan *chan = up->rxc;
456 
457         if (up->use_dma)
458                 chan_writel(chan, HSU_CH_CR, 0x2);
459         else {
460                 up->ier &= ~UART_IER_RLSI;
461                 up->port.read_status_mask &= ~UART_LSR_DR;
462                 serial_out(up, UART_IER, up->ier);
463         }
464 }
465 
466 static inline void receive_chars(struct uart_hsu_port *up, int *status,
467                 unsigned long *flags)
468 {
469         unsigned int ch, flag;
470         unsigned int max_count = 256;
471 
472         do {
473                 ch = serial_in(up, UART_RX);
474                 flag = TTY_NORMAL;
475                 up->port.icount.rx++;
476 
477                 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
478                                        UART_LSR_FE | UART_LSR_OE))) {
479 
480                         dev_warn(up->dev, "We really rush into ERR/BI case"
481                                 "status = 0x%02x", *status);
482                         /* For statistics only */
483                         if (*status & UART_LSR_BI) {
484                                 *status &= ~(UART_LSR_FE | UART_LSR_PE);
485                                 up->port.icount.brk++;
486                                 /*
487                                  * We do the SysRQ and SAK checking
488                                  * here because otherwise the break
489                                  * may get masked by ignore_status_mask
490                                  * or read_status_mask.
491                                  */
492                                 if (uart_handle_break(&up->port))
493                                         goto ignore_char;
494                         } else if (*status & UART_LSR_PE)
495                                 up->port.icount.parity++;
496                         else if (*status & UART_LSR_FE)
497                                 up->port.icount.frame++;
498                         if (*status & UART_LSR_OE)
499                                 up->port.icount.overrun++;
500 
501                         /* Mask off conditions which should be ignored. */
502                         *status &= up->port.read_status_mask;
503 
504 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
505                         if (up->port.cons &&
506                                 up->port.cons->index == up->port.line) {
507                                 /* Recover the break flag from console xmit */
508                                 *status |= up->lsr_break_flag;
509                                 up->lsr_break_flag = 0;
510                         }
511 #endif
512                         if (*status & UART_LSR_BI) {
513                                 flag = TTY_BREAK;
514                         } else if (*status & UART_LSR_PE)
515                                 flag = TTY_PARITY;
516                         else if (*status & UART_LSR_FE)
517                                 flag = TTY_FRAME;
518                 }
519 
520                 if (uart_handle_sysrq_char(&up->port, ch))
521                         goto ignore_char;
522 
523                 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
524         ignore_char:
525                 *status = serial_in(up, UART_LSR);
526         } while ((*status & UART_LSR_DR) && max_count--);
527 
528         spin_unlock_irqrestore(&up->port.lock, *flags);
529         tty_flip_buffer_push(&up->port.state->port);
530         spin_lock_irqsave(&up->port.lock, *flags);
531 }
532 
533 static void transmit_chars(struct uart_hsu_port *up)
534 {
535         struct circ_buf *xmit = &up->port.state->xmit;
536         int count;
537 
538         if (up->port.x_char) {
539                 serial_out(up, UART_TX, up->port.x_char);
540                 up->port.icount.tx++;
541                 up->port.x_char = 0;
542                 return;
543         }
544         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
545                 serial_hsu_stop_tx(&up->port);
546                 return;
547         }
548 
549         /* The IRQ is for TX FIFO half-empty */
550         count = up->port.fifosize / 2;
551 
552         do {
553                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
554                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
555 
556                 up->port.icount.tx++;
557                 if (uart_circ_empty(xmit))
558                         break;
559         } while (--count > 0);
560 
561         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
562                 uart_write_wakeup(&up->port);
563 
564         if (uart_circ_empty(xmit))
565                 serial_hsu_stop_tx(&up->port);
566 }
567 
568 static inline void check_modem_status(struct uart_hsu_port *up)
569 {
570         int status;
571 
572         status = serial_in(up, UART_MSR);
573 
574         if ((status & UART_MSR_ANY_DELTA) == 0)
575                 return;
576 
577         if (status & UART_MSR_TERI)
578                 up->port.icount.rng++;
579         if (status & UART_MSR_DDSR)
580                 up->port.icount.dsr++;
581         /* We may only get DDCD when HW init and reset */
582         if (status & UART_MSR_DDCD)
583                 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
584         /* Will start/stop_tx accordingly */
585         if (status & UART_MSR_DCTS)
586                 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
587 
588         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
589 }
590 
591 /*
592  * This handles the interrupt from one port.
593  */
594 static irqreturn_t port_irq(int irq, void *dev_id)
595 {
596         struct uart_hsu_port *up = dev_id;
597         unsigned int iir, lsr;
598         unsigned long flags;
599 
600         if (unlikely(!up->running))
601                 return IRQ_NONE;
602 
603         spin_lock_irqsave(&up->port.lock, flags);
604         if (up->use_dma) {
605                 lsr = serial_in(up, UART_LSR);
606                 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
607                                        UART_LSR_FE | UART_LSR_OE)))
608                         dev_warn(up->dev,
609                                 "Got lsr irq while using DMA, lsr = 0x%2x\n",
610                                 lsr);
611                 check_modem_status(up);
612                 spin_unlock_irqrestore(&up->port.lock, flags);
613                 return IRQ_HANDLED;
614         }
615 
616         iir = serial_in(up, UART_IIR);
617         if (iir & UART_IIR_NO_INT) {
618                 spin_unlock_irqrestore(&up->port.lock, flags);
619                 return IRQ_NONE;
620         }
621 
622         lsr = serial_in(up, UART_LSR);
623         if (lsr & UART_LSR_DR)
624                 receive_chars(up, &lsr, &flags);
625         check_modem_status(up);
626 
627         /* lsr will be renewed during the receive_chars */
628         if (lsr & UART_LSR_THRE)
629                 transmit_chars(up);
630 
631         spin_unlock_irqrestore(&up->port.lock, flags);
632         return IRQ_HANDLED;
633 }
634 
635 static inline void dma_chan_irq(struct hsu_dma_chan *chan)
636 {
637         struct uart_hsu_port *up = chan->uport;
638         unsigned long flags;
639         u32 int_sts;
640 
641         spin_lock_irqsave(&up->port.lock, flags);
642 
643         if (!up->use_dma || !up->running)
644                 goto exit;
645 
646         /*
647          * No matter what situation, need read clear the IRQ status
648          * There is a bug, see Errata 5, HSD 2900918
649          */
650         int_sts = chan_readl(chan, HSU_CH_SR);
651 
652         /* Rx channel */
653         if (chan->dirt == DMA_FROM_DEVICE)
654                 hsu_dma_rx(up, int_sts, &flags);
655 
656         /* Tx channel */
657         if (chan->dirt == DMA_TO_DEVICE) {
658                 chan_writel(chan, HSU_CH_CR, 0x0);
659                 up->dma_tx_on = 0;
660                 hsu_dma_tx(up);
661         }
662 
663 exit:
664         spin_unlock_irqrestore(&up->port.lock, flags);
665         return;
666 }
667 
668 static irqreturn_t dma_irq(int irq, void *dev_id)
669 {
670         struct hsu_port *hsu = dev_id;
671         u32 int_sts, i;
672 
673         int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
674 
675         /* Currently we only have 6 channels may be used */
676         for (i = 0; i < 6; i++) {
677                 if (int_sts & 0x1)
678                         dma_chan_irq(&hsu->chans[i]);
679                 int_sts >>= 1;
680         }
681 
682         return IRQ_HANDLED;
683 }
684 
685 static unsigned int serial_hsu_tx_empty(struct uart_port *port)
686 {
687         struct uart_hsu_port *up =
688                 container_of(port, struct uart_hsu_port, port);
689         unsigned long flags;
690         unsigned int ret;
691 
692         spin_lock_irqsave(&up->port.lock, flags);
693         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
694         spin_unlock_irqrestore(&up->port.lock, flags);
695 
696         return ret;
697 }
698 
699 static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
700 {
701         struct uart_hsu_port *up =
702                 container_of(port, struct uart_hsu_port, port);
703         unsigned char status;
704         unsigned int ret;
705 
706         status = serial_in(up, UART_MSR);
707 
708         ret = 0;
709         if (status & UART_MSR_DCD)
710                 ret |= TIOCM_CAR;
711         if (status & UART_MSR_RI)
712                 ret |= TIOCM_RNG;
713         if (status & UART_MSR_DSR)
714                 ret |= TIOCM_DSR;
715         if (status & UART_MSR_CTS)
716                 ret |= TIOCM_CTS;
717         return ret;
718 }
719 
720 static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
721 {
722         struct uart_hsu_port *up =
723                 container_of(port, struct uart_hsu_port, port);
724         unsigned char mcr = 0;
725 
726         if (mctrl & TIOCM_RTS)
727                 mcr |= UART_MCR_RTS;
728         if (mctrl & TIOCM_DTR)
729                 mcr |= UART_MCR_DTR;
730         if (mctrl & TIOCM_OUT1)
731                 mcr |= UART_MCR_OUT1;
732         if (mctrl & TIOCM_OUT2)
733                 mcr |= UART_MCR_OUT2;
734         if (mctrl & TIOCM_LOOP)
735                 mcr |= UART_MCR_LOOP;
736 
737         mcr |= up->mcr;
738 
739         serial_out(up, UART_MCR, mcr);
740 }
741 
742 static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
743 {
744         struct uart_hsu_port *up =
745                 container_of(port, struct uart_hsu_port, port);
746         unsigned long flags;
747 
748         spin_lock_irqsave(&up->port.lock, flags);
749         if (break_state == -1)
750                 up->lcr |= UART_LCR_SBC;
751         else
752                 up->lcr &= ~UART_LCR_SBC;
753         serial_out(up, UART_LCR, up->lcr);
754         spin_unlock_irqrestore(&up->port.lock, flags);
755 }
756 
757 /*
758  * What special to do:
759  * 1. chose the 64B fifo mode
760  * 2. start dma or pio depends on configuration
761  * 3. we only allocate dma memory when needed
762  */
763 static int serial_hsu_startup(struct uart_port *port)
764 {
765         struct uart_hsu_port *up =
766                 container_of(port, struct uart_hsu_port, port);
767         unsigned long flags;
768 
769         pm_runtime_get_sync(up->dev);
770 
771         /*
772          * Clear the FIFO buffers and disable them.
773          * (they will be reenabled in set_termios())
774          */
775         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
776         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
777                         UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
778         serial_out(up, UART_FCR, 0);
779 
780         /* Clear the interrupt registers. */
781         (void) serial_in(up, UART_LSR);
782         (void) serial_in(up, UART_RX);
783         (void) serial_in(up, UART_IIR);
784         (void) serial_in(up, UART_MSR);
785 
786         /* Now, initialize the UART, default is 8n1 */
787         serial_out(up, UART_LCR, UART_LCR_WLEN8);
788 
789         spin_lock_irqsave(&up->port.lock, flags);
790 
791         up->port.mctrl |= TIOCM_OUT2;
792         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
793 
794         /*
795          * Finally, enable interrupts.  Note: Modem status interrupts
796          * are set via set_termios(), which will be occurring imminently
797          * anyway, so we don't enable them here.
798          */
799         if (!up->use_dma)
800                 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
801         else
802                 up->ier = 0;
803         serial_out(up, UART_IER, up->ier);
804 
805         spin_unlock_irqrestore(&up->port.lock, flags);
806 
807         /* DMA init */
808         if (up->use_dma) {
809                 struct hsu_dma_buffer *dbuf;
810                 struct circ_buf *xmit = &port->state->xmit;
811 
812                 up->dma_tx_on = 0;
813 
814                 /* First allocate the RX buffer */
815                 dbuf = &up->rxbuf;
816                 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
817                 if (!dbuf->buf) {
818                         up->use_dma = 0;
819                         goto exit;
820                 }
821                 dbuf->dma_addr = dma_map_single(port->dev,
822                                                 dbuf->buf,
823                                                 HSU_DMA_BUF_SIZE,
824                                                 DMA_FROM_DEVICE);
825                 dbuf->dma_size = HSU_DMA_BUF_SIZE;
826 
827                 /* Start the RX channel right now */
828                 hsu_dma_start_rx_chan(up->rxc, dbuf);
829 
830                 /* Next init the TX DMA */
831                 dbuf = &up->txbuf;
832                 dbuf->buf = xmit->buf;
833                 dbuf->dma_addr = dma_map_single(port->dev,
834                                                dbuf->buf,
835                                                UART_XMIT_SIZE,
836                                                DMA_TO_DEVICE);
837                 dbuf->dma_size = UART_XMIT_SIZE;
838 
839                 /* This should not be changed all around */
840                 chan_writel(up->txc, HSU_CH_BSR, 32);
841                 chan_writel(up->txc, HSU_CH_MOTSR, 4);
842                 dbuf->ofs = 0;
843         }
844 
845 exit:
846          /* And clear the interrupt registers again for luck. */
847         (void) serial_in(up, UART_LSR);
848         (void) serial_in(up, UART_RX);
849         (void) serial_in(up, UART_IIR);
850         (void) serial_in(up, UART_MSR);
851 
852         up->running = 1;
853         return 0;
854 }
855 
856 static void serial_hsu_shutdown(struct uart_port *port)
857 {
858         struct uart_hsu_port *up =
859                 container_of(port, struct uart_hsu_port, port);
860         unsigned long flags;
861 
862         /* Disable interrupts from this port */
863         up->ier = 0;
864         serial_out(up, UART_IER, 0);
865         up->running = 0;
866 
867         spin_lock_irqsave(&up->port.lock, flags);
868         up->port.mctrl &= ~TIOCM_OUT2;
869         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
870         spin_unlock_irqrestore(&up->port.lock, flags);
871 
872         /* Disable break condition and FIFOs */
873         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
874         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
875                                   UART_FCR_CLEAR_RCVR |
876                                   UART_FCR_CLEAR_XMIT);
877         serial_out(up, UART_FCR, 0);
878 
879         pm_runtime_put(up->dev);
880 }
881 
882 static void
883 serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
884                        struct ktermios *old)
885 {
886         struct uart_hsu_port *up =
887                         container_of(port, struct uart_hsu_port, port);
888         unsigned char cval, fcr = 0;
889         unsigned long flags;
890         unsigned int baud, quot;
891         u32 ps, mul;
892 
893         switch (termios->c_cflag & CSIZE) {
894         case CS5:
895                 cval = UART_LCR_WLEN5;
896                 break;
897         case CS6:
898                 cval = UART_LCR_WLEN6;
899                 break;
900         case CS7:
901                 cval = UART_LCR_WLEN7;
902                 break;
903         default:
904         case CS8:
905                 cval = UART_LCR_WLEN8;
906                 break;
907         }
908 
909         /* CMSPAR isn't supported by this driver */
910         termios->c_cflag &= ~CMSPAR;
911 
912         if (termios->c_cflag & CSTOPB)
913                 cval |= UART_LCR_STOP;
914         if (termios->c_cflag & PARENB)
915                 cval |= UART_LCR_PARITY;
916         if (!(termios->c_cflag & PARODD))
917                 cval |= UART_LCR_EPAR;
918 
919         /*
920          * The base clk is 50Mhz, and the baud rate come from:
921          *      baud = 50M * MUL / (DIV * PS * DLAB)
922          *
923          * For those basic low baud rate we can get the direct
924          * scalar from 2746800, like 115200 = 2746800/24. For those
925          * higher baud rate, we handle them case by case, mainly by
926          * adjusting the MUL/PS registers, and DIV register is kept
927          * as default value 0x3d09 to make things simple
928          */
929         baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
930 
931         quot = 1;
932         ps = 0x10;
933         mul = 0x3600;
934         switch (baud) {
935         case 3500000:
936                 mul = 0x3345;
937                 ps = 0xC;
938                 break;
939         case 1843200:
940                 mul = 0x2400;
941                 break;
942         case 3000000:
943         case 2500000:
944         case 2000000:
945         case 1500000:
946         case 1000000:
947         case 500000:
948                 /* mul/ps/quot = 0x9C4/0x10/0x1 will make a 500000 bps */
949                 mul = baud / 500000 * 0x9C4;
950                 break;
951         default:
952                 /* Use uart_get_divisor to get quot for other baud rates */
953                 quot = 0;
954         }
955 
956         if (!quot)
957                 quot = uart_get_divisor(port, baud);
958 
959         if ((up->port.uartclk / quot) < (2400 * 16))
960                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
961         else if ((up->port.uartclk / quot) < (230400 * 16))
962                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
963         else
964                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
965 
966         fcr |= UART_FCR_HSU_64B_FIFO;
967 
968         /*
969          * Ok, we're now changing the port state.  Do it with
970          * interrupts disabled.
971          */
972         spin_lock_irqsave(&up->port.lock, flags);
973 
974         /* Update the per-port timeout */
975         uart_update_timeout(port, termios->c_cflag, baud);
976 
977         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
978         if (termios->c_iflag & INPCK)
979                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
980         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
981                 up->port.read_status_mask |= UART_LSR_BI;
982 
983         /* Characters to ignore */
984         up->port.ignore_status_mask = 0;
985         if (termios->c_iflag & IGNPAR)
986                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
987         if (termios->c_iflag & IGNBRK) {
988                 up->port.ignore_status_mask |= UART_LSR_BI;
989                 /*
990                  * If we're ignoring parity and break indicators,
991                  * ignore overruns too (for real raw support).
992                  */
993                 if (termios->c_iflag & IGNPAR)
994                         up->port.ignore_status_mask |= UART_LSR_OE;
995         }
996 
997         /* Ignore all characters if CREAD is not set */
998         if ((termios->c_cflag & CREAD) == 0)
999                 up->port.ignore_status_mask |= UART_LSR_DR;
1000 
1001         /*
1002          * CTS flow control flag and modem status interrupts, disable
1003          * MSI by default
1004          */
1005         up->ier &= ~UART_IER_MSI;
1006         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1007                 up->ier |= UART_IER_MSI;
1008 
1009         serial_out(up, UART_IER, up->ier);
1010 
1011         if (termios->c_cflag & CRTSCTS)
1012                 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1013         else
1014                 up->mcr &= ~UART_MCR_AFE;
1015 
1016         serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1017         serial_out(up, UART_DLL, quot & 0xff);          /* LS of divisor */
1018         serial_out(up, UART_DLM, quot >> 8);            /* MS of divisor */
1019         serial_out(up, UART_LCR, cval);                 /* reset DLAB */
1020         serial_out(up, UART_MUL, mul);                  /* set MUL */
1021         serial_out(up, UART_PS, ps);                    /* set PS */
1022         up->lcr = cval;                                 /* Save LCR */
1023         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1024         serial_out(up, UART_FCR, fcr);
1025         spin_unlock_irqrestore(&up->port.lock, flags);
1026 }
1027 
1028 static void
1029 serial_hsu_pm(struct uart_port *port, unsigned int state,
1030               unsigned int oldstate)
1031 {
1032 }
1033 
1034 static void serial_hsu_release_port(struct uart_port *port)
1035 {
1036 }
1037 
1038 static int serial_hsu_request_port(struct uart_port *port)
1039 {
1040         return 0;
1041 }
1042 
1043 static void serial_hsu_config_port(struct uart_port *port, int flags)
1044 {
1045         struct uart_hsu_port *up =
1046                 container_of(port, struct uart_hsu_port, port);
1047         up->port.type = PORT_MFD;
1048 }
1049 
1050 static int
1051 serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
1052 {
1053         /* We don't want the core code to modify any port params */
1054         return -EINVAL;
1055 }
1056 
1057 static const char *
1058 serial_hsu_type(struct uart_port *port)
1059 {
1060         struct uart_hsu_port *up =
1061                 container_of(port, struct uart_hsu_port, port);
1062         return up->name;
1063 }
1064 
1065 /* Mainly for uart console use */
1066 static struct uart_hsu_port *serial_hsu_ports[3];
1067 static struct uart_driver serial_hsu_reg;
1068 
1069 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1070 
1071 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1072 
1073 /* Wait for transmitter & holding register to empty */
1074 static inline void wait_for_xmitr(struct uart_hsu_port *up)
1075 {
1076         unsigned int status, tmout = 1000;
1077 
1078         /* Wait up to 1ms for the character to be sent. */
1079         do {
1080                 status = serial_in(up, UART_LSR);
1081 
1082                 if (status & UART_LSR_BI)
1083                         up->lsr_break_flag = UART_LSR_BI;
1084 
1085                 if (--tmout == 0)
1086                         break;
1087                 udelay(1);
1088         } while (!(status & BOTH_EMPTY));
1089 
1090         /* Wait up to 1s for flow control if necessary */
1091         if (up->port.flags & UPF_CONS_FLOW) {
1092                 tmout = 1000000;
1093                 while (--tmout &&
1094                        ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1095                         udelay(1);
1096         }
1097 }
1098 
1099 static void serial_hsu_console_putchar(struct uart_port *port, int ch)
1100 {
1101         struct uart_hsu_port *up =
1102                 container_of(port, struct uart_hsu_port, port);
1103 
1104         wait_for_xmitr(up);
1105         serial_out(up, UART_TX, ch);
1106 }
1107 
1108 /*
1109  * Print a string to the serial port trying not to disturb
1110  * any possible real use of the port...
1111  *
1112  *      The console_lock must be held when we get here.
1113  */
1114 static void
1115 serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
1116 {
1117         struct uart_hsu_port *up = serial_hsu_ports[co->index];
1118         unsigned long flags;
1119         unsigned int ier;
1120         int locked = 1;
1121 
1122         touch_nmi_watchdog();
1123 
1124         local_irq_save(flags);
1125         if (up->port.sysrq)
1126                 locked = 0;
1127         else if (oops_in_progress) {
1128                 locked = spin_trylock(&up->port.lock);
1129         } else
1130                 spin_lock(&up->port.lock);
1131 
1132         /* First save the IER then disable the interrupts */
1133         ier = serial_in(up, UART_IER);
1134         serial_out(up, UART_IER, 0);
1135 
1136         uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1137 
1138         /*
1139          * Finally, wait for transmitter to become empty
1140          * and restore the IER
1141          */
1142         wait_for_xmitr(up);
1143         serial_out(up, UART_IER, ier);
1144 
1145         if (locked)
1146                 spin_unlock(&up->port.lock);
1147         local_irq_restore(flags);
1148 }
1149 
1150 static struct console serial_hsu_console;
1151 
1152 static int __init
1153 serial_hsu_console_setup(struct console *co, char *options)
1154 {
1155         struct uart_hsu_port *up;
1156         int baud = 115200;
1157         int bits = 8;
1158         int parity = 'n';
1159         int flow = 'n';
1160 
1161         if (co->index == -1 || co->index >= serial_hsu_reg.nr)
1162                 co->index = 0;
1163         up = serial_hsu_ports[co->index];
1164         if (!up)
1165                 return -ENODEV;
1166 
1167         if (options)
1168                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1169 
1170         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1171 }
1172 
1173 static struct console serial_hsu_console = {
1174         .name           = "ttyMFD",
1175         .write          = serial_hsu_console_write,
1176         .device         = uart_console_device,
1177         .setup          = serial_hsu_console_setup,
1178         .flags          = CON_PRINTBUFFER,
1179         .index          = -1,
1180         .data           = &serial_hsu_reg,
1181 };
1182 
1183 #define SERIAL_HSU_CONSOLE      (&serial_hsu_console)
1184 #else
1185 #define SERIAL_HSU_CONSOLE      NULL
1186 #endif
1187 
1188 static struct uart_ops serial_hsu_pops = {
1189         .tx_empty       = serial_hsu_tx_empty,
1190         .set_mctrl      = serial_hsu_set_mctrl,
1191         .get_mctrl      = serial_hsu_get_mctrl,
1192         .stop_tx        = serial_hsu_stop_tx,
1193         .start_tx       = serial_hsu_start_tx,
1194         .stop_rx        = serial_hsu_stop_rx,
1195         .enable_ms      = serial_hsu_enable_ms,
1196         .break_ctl      = serial_hsu_break_ctl,
1197         .startup        = serial_hsu_startup,
1198         .shutdown       = serial_hsu_shutdown,
1199         .set_termios    = serial_hsu_set_termios,
1200         .pm             = serial_hsu_pm,
1201         .type           = serial_hsu_type,
1202         .release_port   = serial_hsu_release_port,
1203         .request_port   = serial_hsu_request_port,
1204         .config_port    = serial_hsu_config_port,
1205         .verify_port    = serial_hsu_verify_port,
1206 };
1207 
1208 static struct uart_driver serial_hsu_reg = {
1209         .owner          = THIS_MODULE,
1210         .driver_name    = "MFD serial",
1211         .dev_name       = "ttyMFD",
1212         .major          = TTY_MAJOR,
1213         .minor          = 128,
1214         .nr             = 3,
1215         .cons           = SERIAL_HSU_CONSOLE,
1216 };
1217 
1218 #ifdef CONFIG_PM
1219 static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
1220 {
1221         void *priv = pci_get_drvdata(pdev);
1222         struct uart_hsu_port *up;
1223 
1224         /* Make sure this is not the internal dma controller */
1225         if (priv && (pdev->device != 0x081E)) {
1226                 up = priv;
1227                 uart_suspend_port(&serial_hsu_reg, &up->port);
1228         }
1229 
1230         pci_save_state(pdev);
1231         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1232         return 0;
1233 }
1234 
1235 static int serial_hsu_resume(struct pci_dev *pdev)
1236 {
1237         void *priv = pci_get_drvdata(pdev);
1238         struct uart_hsu_port *up;
1239         int ret;
1240 
1241         pci_set_power_state(pdev, PCI_D0);
1242         pci_restore_state(pdev);
1243 
1244         ret = pci_enable_device(pdev);
1245         if (ret)
1246                 dev_warn(&pdev->dev,
1247                         "HSU: can't re-enable device, try to continue\n");
1248 
1249         if (priv && (pdev->device != 0x081E)) {
1250                 up = priv;
1251                 uart_resume_port(&serial_hsu_reg, &up->port);
1252         }
1253         return 0;
1254 }
1255 #else
1256 #define serial_hsu_suspend      NULL
1257 #define serial_hsu_resume       NULL
1258 #endif
1259 
1260 #ifdef CONFIG_PM_RUNTIME
1261 static int serial_hsu_runtime_idle(struct device *dev)
1262 {
1263         pm_schedule_suspend(dev, 500);
1264         return -EBUSY;
1265 }
1266 
1267 static int serial_hsu_runtime_suspend(struct device *dev)
1268 {
1269         return 0;
1270 }
1271 
1272 static int serial_hsu_runtime_resume(struct device *dev)
1273 {
1274         return 0;
1275 }
1276 #else
1277 #define serial_hsu_runtime_idle         NULL
1278 #define serial_hsu_runtime_suspend      NULL
1279 #define serial_hsu_runtime_resume       NULL
1280 #endif
1281 
1282 static const struct dev_pm_ops serial_hsu_pm_ops = {
1283         .runtime_suspend = serial_hsu_runtime_suspend,
1284         .runtime_resume = serial_hsu_runtime_resume,
1285         .runtime_idle = serial_hsu_runtime_idle,
1286 };
1287 
1288 /* temp global pointer before we settle down on using one or four PCI dev */
1289 static struct hsu_port *phsu;
1290 
1291 static int serial_hsu_probe(struct pci_dev *pdev,
1292                                 const struct pci_device_id *ent)
1293 {
1294         struct uart_hsu_port *uport;
1295         int index, ret;
1296 
1297         printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1298                 pdev->vendor, pdev->device);
1299 
1300         switch (pdev->device) {
1301         case 0x081B:
1302                 index = 0;
1303                 break;
1304         case 0x081C:
1305                 index = 1;
1306                 break;
1307         case 0x081D:
1308                 index = 2;
1309                 break;
1310         case 0x081E:
1311                 /* internal DMA controller */
1312                 index = 3;
1313                 break;
1314         default:
1315                 dev_err(&pdev->dev, "HSU: out of index!");
1316                 return -ENODEV;
1317         }
1318 
1319         ret = pci_enable_device(pdev);
1320         if (ret)
1321                 return ret;
1322 
1323         if (index == 3) {
1324                 /* DMA controller */
1325                 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
1326                 if (ret) {
1327                         dev_err(&pdev->dev, "can not get IRQ\n");
1328                         goto err_disable;
1329                 }
1330                 pci_set_drvdata(pdev, phsu);
1331         } else {
1332                 /* UART port 0~2 */
1333                 uport = &phsu->port[index];
1334                 uport->port.irq = pdev->irq;
1335                 uport->port.dev = &pdev->dev;
1336                 uport->dev = &pdev->dev;
1337 
1338                 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
1339                 if (ret) {
1340                         dev_err(&pdev->dev, "can not get IRQ\n");
1341                         goto err_disable;
1342                 }
1343                 uart_add_one_port(&serial_hsu_reg, &uport->port);
1344 
1345                 pci_set_drvdata(pdev, uport);
1346         }
1347 
1348         pm_runtime_put_noidle(&pdev->dev);
1349         pm_runtime_allow(&pdev->dev);
1350 
1351         return 0;
1352 
1353 err_disable:
1354         pci_disable_device(pdev);
1355         return ret;
1356 }
1357 
1358 static void hsu_global_init(void)
1359 {
1360         struct hsu_port *hsu;
1361         struct uart_hsu_port *uport;
1362         struct hsu_dma_chan *dchan;
1363         int i, ret;
1364 
1365         hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
1366         if (!hsu)
1367                 return;
1368 
1369         /* Get basic io resource and map it */
1370         hsu->paddr = 0xffa28000;
1371         hsu->iolen = 0x1000;
1372 
1373         if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
1374                 pr_warning("HSU: error in request mem region\n");
1375 
1376         hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
1377         if (!hsu->reg) {
1378                 pr_err("HSU: error in ioremap\n");
1379                 ret = -ENOMEM;
1380                 goto err_free_region;
1381         }
1382 
1383         /* Initialise the 3 UART ports */
1384         uport = hsu->port;
1385         for (i = 0; i < 3; i++) {
1386                 uport->port.type = PORT_MFD;
1387                 uport->port.iotype = UPIO_MEM;
1388                 uport->port.mapbase = (resource_size_t)hsu->paddr
1389                                         + HSU_PORT_REG_OFFSET
1390                                         + i * HSU_PORT_REG_LENGTH;
1391                 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
1392                                         + i * HSU_PORT_REG_LENGTH;
1393 
1394                 sprintf(uport->name, "hsu_port%d", i);
1395                 uport->port.fifosize = 64;
1396                 uport->port.ops = &serial_hsu_pops;
1397                 uport->port.line = i;
1398                 uport->port.flags = UPF_IOREMAP;
1399                 /* set the scalable maxim support rate to 2746800 bps */
1400                 uport->port.uartclk = 115200 * 24 * 16;
1401 
1402                 uport->running = 0;
1403                 uport->txc = &hsu->chans[i * 2];
1404                 uport->rxc = &hsu->chans[i * 2 + 1];
1405 
1406                 serial_hsu_ports[i] = uport;
1407                 uport->index = i;
1408 
1409                 if (hsu_dma_enable & (1<<i))
1410                         uport->use_dma = 1;
1411                 else
1412                         uport->use_dma = 0;
1413 
1414                 uport++;
1415         }
1416 
1417         /* Initialise 6 dma channels */
1418         dchan = hsu->chans;
1419         for (i = 0; i < 6; i++) {
1420                 dchan->id = i;
1421                 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1422                 dchan->uport = &hsu->port[i/2];
1423                 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
1424                                 i * HSU_DMA_CHANS_REG_LENGTH;
1425 
1426                 dchan++;
1427         }
1428 
1429         phsu = hsu;
1430         hsu_debugfs_init(hsu);
1431         return;
1432 
1433 err_free_region:
1434         release_mem_region(hsu->paddr, hsu->iolen);
1435         kfree(hsu);
1436         return;
1437 }
1438 
1439 static void serial_hsu_remove(struct pci_dev *pdev)
1440 {
1441         void *priv = pci_get_drvdata(pdev);
1442         struct uart_hsu_port *up;
1443 
1444         if (!priv)
1445                 return;
1446 
1447         pm_runtime_forbid(&pdev->dev);
1448         pm_runtime_get_noresume(&pdev->dev);
1449 
1450         /* For port 0/1/2, priv is the address of uart_hsu_port */
1451         if (pdev->device != 0x081E) {
1452                 up = priv;
1453                 uart_remove_one_port(&serial_hsu_reg, &up->port);
1454         }
1455 
1456         free_irq(pdev->irq, priv);
1457         pci_disable_device(pdev);
1458 }
1459 
1460 /* First 3 are UART ports, and the 4th is the DMA */
1461 static const struct pci_device_id pci_ids[] = {
1462         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
1463         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
1464         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
1465         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
1466         {},
1467 };
1468 
1469 static struct pci_driver hsu_pci_driver = {
1470         .name =         "HSU serial",
1471         .id_table =     pci_ids,
1472         .probe =        serial_hsu_probe,
1473         .remove =       serial_hsu_remove,
1474         .suspend =      serial_hsu_suspend,
1475         .resume =       serial_hsu_resume,
1476         .driver = {
1477                 .pm = &serial_hsu_pm_ops,
1478         },
1479 };
1480 
1481 static int __init hsu_pci_init(void)
1482 {
1483         int ret;
1484 
1485         hsu_global_init();
1486 
1487         ret = uart_register_driver(&serial_hsu_reg);
1488         if (ret)
1489                 return ret;
1490 
1491         return pci_register_driver(&hsu_pci_driver);
1492 }
1493 
1494 static void __exit hsu_pci_exit(void)
1495 {
1496         pci_unregister_driver(&hsu_pci_driver);
1497         uart_unregister_driver(&serial_hsu_reg);
1498 
1499         hsu_debugfs_remove(phsu);
1500 
1501         kfree(phsu);
1502 }
1503 
1504 module_init(hsu_pci_init);
1505 module_exit(hsu_pci_exit);
1506 
1507 MODULE_LICENSE("GPL v2");
1508 MODULE_DEVICE_TABLE(pci, pci_ids);
1509 

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