Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/tty/serial/lpc32xx_hs.c

  1 /*
  2  * High Speed Serial Ports on NXP LPC32xx SoC
  3  *
  4  * Authors: Kevin Wells <kevin.wells@nxp.com>
  5  *          Roland Stigge <stigge@antcom.de>
  6  *
  7  * Copyright (C) 2010 NXP Semiconductors
  8  * Copyright (C) 2012 Roland Stigge
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License as published by
 12  * the Free Software Foundation; either version 2 of the License, or
 13  * (at your option) any later version.
 14  *
 15  * This program is distributed in the hope that it will be useful,
 16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 18  * GNU General Public License for more details.
 19  */
 20 
 21 #include <linux/module.h>
 22 #include <linux/ioport.h>
 23 #include <linux/init.h>
 24 #include <linux/console.h>
 25 #include <linux/sysrq.h>
 26 #include <linux/tty.h>
 27 #include <linux/tty_flip.h>
 28 #include <linux/serial_core.h>
 29 #include <linux/serial.h>
 30 #include <linux/platform_device.h>
 31 #include <linux/delay.h>
 32 #include <linux/nmi.h>
 33 #include <linux/io.h>
 34 #include <linux/irq.h>
 35 #include <linux/gpio.h>
 36 #include <linux/of.h>
 37 #include <mach/platform.h>
 38 #include <mach/hardware.h>
 39 
 40 /*
 41  * High Speed UART register offsets
 42  */
 43 #define LPC32XX_HSUART_FIFO(x)                  ((x) + 0x00)
 44 #define LPC32XX_HSUART_LEVEL(x)                 ((x) + 0x04)
 45 #define LPC32XX_HSUART_IIR(x)                   ((x) + 0x08)
 46 #define LPC32XX_HSUART_CTRL(x)                  ((x) + 0x0C)
 47 #define LPC32XX_HSUART_RATE(x)                  ((x) + 0x10)
 48 
 49 #define LPC32XX_HSU_BREAK_DATA                  (1 << 10)
 50 #define LPC32XX_HSU_ERROR_DATA                  (1 << 9)
 51 #define LPC32XX_HSU_RX_EMPTY                    (1 << 8)
 52 
 53 #define LPC32XX_HSU_TX_LEV(n)                   (((n) >> 8) & 0xFF)
 54 #define LPC32XX_HSU_RX_LEV(n)                   ((n) & 0xFF)
 55 
 56 #define LPC32XX_HSU_TX_INT_SET                  (1 << 6)
 57 #define LPC32XX_HSU_RX_OE_INT                   (1 << 5)
 58 #define LPC32XX_HSU_BRK_INT                     (1 << 4)
 59 #define LPC32XX_HSU_FE_INT                      (1 << 3)
 60 #define LPC32XX_HSU_RX_TIMEOUT_INT              (1 << 2)
 61 #define LPC32XX_HSU_RX_TRIG_INT                 (1 << 1)
 62 #define LPC32XX_HSU_TX_INT                      (1 << 0)
 63 
 64 #define LPC32XX_HSU_HRTS_INV                    (1 << 21)
 65 #define LPC32XX_HSU_HRTS_TRIG_8B                (0x0 << 19)
 66 #define LPC32XX_HSU_HRTS_TRIG_16B               (0x1 << 19)
 67 #define LPC32XX_HSU_HRTS_TRIG_32B               (0x2 << 19)
 68 #define LPC32XX_HSU_HRTS_TRIG_48B               (0x3 << 19)
 69 #define LPC32XX_HSU_HRTS_EN                     (1 << 18)
 70 #define LPC32XX_HSU_TMO_DISABLED                (0x0 << 16)
 71 #define LPC32XX_HSU_TMO_INACT_4B                (0x1 << 16)
 72 #define LPC32XX_HSU_TMO_INACT_8B                (0x2 << 16)
 73 #define LPC32XX_HSU_TMO_INACT_16B               (0x3 << 16)
 74 #define LPC32XX_HSU_HCTS_INV                    (1 << 15)
 75 #define LPC32XX_HSU_HCTS_EN                     (1 << 14)
 76 #define LPC32XX_HSU_OFFSET(n)                   ((n) << 9)
 77 #define LPC32XX_HSU_BREAK                       (1 << 8)
 78 #define LPC32XX_HSU_ERR_INT_EN                  (1 << 7)
 79 #define LPC32XX_HSU_RX_INT_EN                   (1 << 6)
 80 #define LPC32XX_HSU_TX_INT_EN                   (1 << 5)
 81 #define LPC32XX_HSU_RX_TL1B                     (0x0 << 2)
 82 #define LPC32XX_HSU_RX_TL4B                     (0x1 << 2)
 83 #define LPC32XX_HSU_RX_TL8B                     (0x2 << 2)
 84 #define LPC32XX_HSU_RX_TL16B                    (0x3 << 2)
 85 #define LPC32XX_HSU_RX_TL32B                    (0x4 << 2)
 86 #define LPC32XX_HSU_RX_TL48B                    (0x5 << 2)
 87 #define LPC32XX_HSU_TX_TLEMPTY                  (0x0 << 0)
 88 #define LPC32XX_HSU_TX_TL0B                     (0x0 << 0)
 89 #define LPC32XX_HSU_TX_TL4B                     (0x1 << 0)
 90 #define LPC32XX_HSU_TX_TL8B                     (0x2 << 0)
 91 #define LPC32XX_HSU_TX_TL16B                    (0x3 << 0)
 92 
 93 #define MODNAME "lpc32xx_hsuart"
 94 
 95 struct lpc32xx_hsuart_port {
 96         struct uart_port port;
 97 };
 98 
 99 #define FIFO_READ_LIMIT 128
100 #define MAX_PORTS 3
101 #define LPC32XX_TTY_NAME "ttyTX"
102 static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
103 
104 #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
105 static void wait_for_xmit_empty(struct uart_port *port)
106 {
107         unsigned int timeout = 10000;
108 
109         do {
110                 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
111                                                         port->membase))) == 0)
112                         break;
113                 if (--timeout == 0)
114                         break;
115                 udelay(1);
116         } while (1);
117 }
118 
119 static void wait_for_xmit_ready(struct uart_port *port)
120 {
121         unsigned int timeout = 10000;
122 
123         while (1) {
124                 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
125                                                         port->membase))) < 32)
126                         break;
127                 if (--timeout == 0)
128                         break;
129                 udelay(1);
130         }
131 }
132 
133 static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
134 {
135         wait_for_xmit_ready(port);
136         writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
137 }
138 
139 static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
140                                          unsigned int count)
141 {
142         struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
143         unsigned long flags;
144         int locked = 1;
145 
146         touch_nmi_watchdog();
147         local_irq_save(flags);
148         if (up->port.sysrq)
149                 locked = 0;
150         else if (oops_in_progress)
151                 locked = spin_trylock(&up->port.lock);
152         else
153                 spin_lock(&up->port.lock);
154 
155         uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
156         wait_for_xmit_empty(&up->port);
157 
158         if (locked)
159                 spin_unlock(&up->port.lock);
160         local_irq_restore(flags);
161 }
162 
163 static int __init lpc32xx_hsuart_console_setup(struct console *co,
164                                                char *options)
165 {
166         struct uart_port *port;
167         int baud = 115200;
168         int bits = 8;
169         int parity = 'n';
170         int flow = 'n';
171 
172         if (co->index >= MAX_PORTS)
173                 co->index = 0;
174 
175         port = &lpc32xx_hs_ports[co->index].port;
176         if (!port->membase)
177                 return -ENODEV;
178 
179         if (options)
180                 uart_parse_options(options, &baud, &parity, &bits, &flow);
181 
182         return uart_set_options(port, co, baud, parity, bits, flow);
183 }
184 
185 static struct uart_driver lpc32xx_hsuart_reg;
186 static struct console lpc32xx_hsuart_console = {
187         .name           = LPC32XX_TTY_NAME,
188         .write          = lpc32xx_hsuart_console_write,
189         .device         = uart_console_device,
190         .setup          = lpc32xx_hsuart_console_setup,
191         .flags          = CON_PRINTBUFFER,
192         .index          = -1,
193         .data           = &lpc32xx_hsuart_reg,
194 };
195 
196 static int __init lpc32xx_hsuart_console_init(void)
197 {
198         register_console(&lpc32xx_hsuart_console);
199         return 0;
200 }
201 console_initcall(lpc32xx_hsuart_console_init);
202 
203 #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
204 #else
205 #define LPC32XX_HSUART_CONSOLE NULL
206 #endif
207 
208 static struct uart_driver lpc32xx_hs_reg = {
209         .owner          = THIS_MODULE,
210         .driver_name    = MODNAME,
211         .dev_name       = LPC32XX_TTY_NAME,
212         .nr             = MAX_PORTS,
213         .cons           = LPC32XX_HSUART_CONSOLE,
214 };
215 static int uarts_registered;
216 
217 static unsigned int __serial_get_clock_div(unsigned long uartclk,
218                                            unsigned long rate)
219 {
220         u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
221         u32 rate_diff;
222 
223         /* Find the closest divider to get the desired clock rate */
224         div = uartclk / rate;
225         goodrate = hsu_rate = (div / 14) - 1;
226         if (hsu_rate != 0)
227                 hsu_rate--;
228 
229         /* Tweak divider */
230         l_hsu_rate = hsu_rate + 3;
231         rate_diff = 0xFFFFFFFF;
232 
233         while (hsu_rate < l_hsu_rate) {
234                 comprate = uartclk / ((hsu_rate + 1) * 14);
235                 if (abs(comprate - rate) < rate_diff) {
236                         goodrate = hsu_rate;
237                         rate_diff = abs(comprate - rate);
238                 }
239 
240                 hsu_rate++;
241         }
242         if (hsu_rate > 0xFF)
243                 hsu_rate = 0xFF;
244 
245         return goodrate;
246 }
247 
248 static void __serial_uart_flush(struct uart_port *port)
249 {
250         u32 tmp;
251         int cnt = 0;
252 
253         while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
254                (cnt++ < FIFO_READ_LIMIT))
255                 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
256 }
257 
258 static void __serial_lpc32xx_rx(struct uart_port *port)
259 {
260         struct tty_port *tport = &port->state->port;
261         unsigned int tmp, flag;
262 
263         /* Read data from FIFO and push into terminal */
264         tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
265         while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
266                 flag = TTY_NORMAL;
267                 port->icount.rx++;
268 
269                 if (tmp & LPC32XX_HSU_ERROR_DATA) {
270                         /* Framing error */
271                         writel(LPC32XX_HSU_FE_INT,
272                                LPC32XX_HSUART_IIR(port->membase));
273                         port->icount.frame++;
274                         flag = TTY_FRAME;
275                         tty_insert_flip_char(tport, 0, TTY_FRAME);
276                 }
277 
278                 tty_insert_flip_char(tport, (tmp & 0xFF), flag);
279 
280                 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
281         }
282 
283         spin_unlock(&port->lock);
284         tty_flip_buffer_push(tport);
285         spin_lock(&port->lock);
286 }
287 
288 static void __serial_lpc32xx_tx(struct uart_port *port)
289 {
290         struct circ_buf *xmit = &port->state->xmit;
291         unsigned int tmp;
292 
293         if (port->x_char) {
294                 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase));
295                 port->icount.tx++;
296                 port->x_char = 0;
297                 return;
298         }
299 
300         if (uart_circ_empty(xmit) || uart_tx_stopped(port))
301                 goto exit_tx;
302 
303         /* Transfer data */
304         while (LPC32XX_HSU_TX_LEV(readl(
305                 LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
306                 writel((u32) xmit->buf[xmit->tail],
307                        LPC32XX_HSUART_FIFO(port->membase));
308                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
309                 port->icount.tx++;
310                 if (uart_circ_empty(xmit))
311                         break;
312         }
313 
314         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
315                 uart_write_wakeup(port);
316 
317 exit_tx:
318         if (uart_circ_empty(xmit)) {
319                 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
320                 tmp &= ~LPC32XX_HSU_TX_INT_EN;
321                 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
322         }
323 }
324 
325 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
326 {
327         struct uart_port *port = dev_id;
328         struct tty_port *tport = &port->state->port;
329         u32 status;
330 
331         spin_lock(&port->lock);
332 
333         /* Read UART status and clear latched interrupts */
334         status = readl(LPC32XX_HSUART_IIR(port->membase));
335 
336         if (status & LPC32XX_HSU_BRK_INT) {
337                 /* Break received */
338                 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
339                 port->icount.brk++;
340                 uart_handle_break(port);
341         }
342 
343         /* Framing error */
344         if (status & LPC32XX_HSU_FE_INT)
345                 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
346 
347         if (status & LPC32XX_HSU_RX_OE_INT) {
348                 /* Receive FIFO overrun */
349                 writel(LPC32XX_HSU_RX_OE_INT,
350                        LPC32XX_HSUART_IIR(port->membase));
351                 port->icount.overrun++;
352                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
353                 tty_schedule_flip(tport);
354         }
355 
356         /* Data received? */
357         if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT))
358                 __serial_lpc32xx_rx(port);
359 
360         /* Transmit data request? */
361         if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
362                 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
363                 __serial_lpc32xx_tx(port);
364         }
365 
366         spin_unlock(&port->lock);
367 
368         return IRQ_HANDLED;
369 }
370 
371 /* port->lock is not held.  */
372 static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
373 {
374         unsigned int ret = 0;
375 
376         if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
377                 ret = TIOCSER_TEMT;
378 
379         return ret;
380 }
381 
382 /* port->lock held by caller.  */
383 static void serial_lpc32xx_set_mctrl(struct uart_port *port,
384                                      unsigned int mctrl)
385 {
386         /* No signals are supported on HS UARTs */
387 }
388 
389 /* port->lock is held by caller and interrupts are disabled.  */
390 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
391 {
392         /* No signals are supported on HS UARTs */
393         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
394 }
395 
396 /* port->lock held by caller.  */
397 static void serial_lpc32xx_stop_tx(struct uart_port *port)
398 {
399         u32 tmp;
400 
401         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
402         tmp &= ~LPC32XX_HSU_TX_INT_EN;
403         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
404 }
405 
406 /* port->lock held by caller.  */
407 static void serial_lpc32xx_start_tx(struct uart_port *port)
408 {
409         u32 tmp;
410 
411         __serial_lpc32xx_tx(port);
412         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
413         tmp |= LPC32XX_HSU_TX_INT_EN;
414         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
415 }
416 
417 /* port->lock held by caller.  */
418 static void serial_lpc32xx_stop_rx(struct uart_port *port)
419 {
420         u32 tmp;
421 
422         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
423         tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
424         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
425 
426         writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
427                 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
428 }
429 
430 /* port->lock held by caller.  */
431 static void serial_lpc32xx_enable_ms(struct uart_port *port)
432 {
433         /* Modem status is not supported */
434 }
435 
436 /* port->lock is not held.  */
437 static void serial_lpc32xx_break_ctl(struct uart_port *port,
438                                      int break_state)
439 {
440         unsigned long flags;
441         u32 tmp;
442 
443         spin_lock_irqsave(&port->lock, flags);
444         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
445         if (break_state != 0)
446                 tmp |= LPC32XX_HSU_BREAK;
447         else
448                 tmp &= ~LPC32XX_HSU_BREAK;
449         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
450         spin_unlock_irqrestore(&port->lock, flags);
451 }
452 
453 /* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
454 static void lpc32xx_loopback_set(resource_size_t mapbase, int state)
455 {
456         int bit;
457         u32 tmp;
458 
459         switch (mapbase) {
460         case LPC32XX_HS_UART1_BASE:
461                 bit = 0;
462                 break;
463         case LPC32XX_HS_UART2_BASE:
464                 bit = 1;
465                 break;
466         case LPC32XX_HS_UART7_BASE:
467                 bit = 6;
468                 break;
469         default:
470                 WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
471                 return;
472         }
473 
474         tmp = readl(LPC32XX_UARTCTL_CLOOP);
475         if (state)
476                 tmp |= (1 << bit);
477         else
478                 tmp &= ~(1 << bit);
479         writel(tmp, LPC32XX_UARTCTL_CLOOP);
480 }
481 
482 /* port->lock is not held.  */
483 static int serial_lpc32xx_startup(struct uart_port *port)
484 {
485         int retval;
486         unsigned long flags;
487         u32 tmp;
488 
489         spin_lock_irqsave(&port->lock, flags);
490 
491         __serial_uart_flush(port);
492 
493         writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
494                 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
495                LPC32XX_HSUART_IIR(port->membase));
496 
497         writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
498 
499         /*
500          * Set receiver timeout, HSU offset of 20, no break, no interrupts,
501          * and default FIFO trigger levels
502          */
503         tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
504                 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
505         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
506 
507         lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
508 
509         spin_unlock_irqrestore(&port->lock, flags);
510 
511         retval = request_irq(port->irq, serial_lpc32xx_interrupt,
512                              0, MODNAME, port);
513         if (!retval)
514                 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
515                        LPC32XX_HSUART_CTRL(port->membase));
516 
517         return retval;
518 }
519 
520 /* port->lock is not held.  */
521 static void serial_lpc32xx_shutdown(struct uart_port *port)
522 {
523         u32 tmp;
524         unsigned long flags;
525 
526         spin_lock_irqsave(&port->lock, flags);
527 
528         tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
529                 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
530         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
531 
532         lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
533 
534         spin_unlock_irqrestore(&port->lock, flags);
535 
536         free_irq(port->irq, port);
537 }
538 
539 /* port->lock is not held.  */
540 static void serial_lpc32xx_set_termios(struct uart_port *port,
541                                        struct ktermios *termios,
542                                        struct ktermios *old)
543 {
544         unsigned long flags;
545         unsigned int baud, quot;
546         u32 tmp;
547 
548         /* Always 8-bit, no parity, 1 stop bit */
549         termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
550         termios->c_cflag |= CS8;
551 
552         termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
553 
554         baud = uart_get_baud_rate(port, termios, old, 0,
555                                   port->uartclk / 14);
556 
557         quot = __serial_get_clock_div(port->uartclk, baud);
558 
559         spin_lock_irqsave(&port->lock, flags);
560 
561         /* Ignore characters? */
562         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
563         if ((termios->c_cflag & CREAD) == 0)
564                 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
565         else
566                 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
567         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
568 
569         writel(quot, LPC32XX_HSUART_RATE(port->membase));
570 
571         uart_update_timeout(port, termios->c_cflag, baud);
572 
573         spin_unlock_irqrestore(&port->lock, flags);
574 
575         /* Don't rewrite B0 */
576         if (tty_termios_baud_rate(termios))
577                 tty_termios_encode_baud_rate(termios, baud, baud);
578 }
579 
580 static const char *serial_lpc32xx_type(struct uart_port *port)
581 {
582         return MODNAME;
583 }
584 
585 static void serial_lpc32xx_release_port(struct uart_port *port)
586 {
587         if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
588                 if (port->flags & UPF_IOREMAP) {
589                         iounmap(port->membase);
590                         port->membase = NULL;
591                 }
592 
593                 release_mem_region(port->mapbase, SZ_4K);
594         }
595 }
596 
597 static int serial_lpc32xx_request_port(struct uart_port *port)
598 {
599         int ret = -ENODEV;
600 
601         if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
602                 ret = 0;
603 
604                 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
605                         ret = -EBUSY;
606                 else if (port->flags & UPF_IOREMAP) {
607                         port->membase = ioremap(port->mapbase, SZ_4K);
608                         if (!port->membase) {
609                                 release_mem_region(port->mapbase, SZ_4K);
610                                 ret = -ENOMEM;
611                         }
612                 }
613         }
614 
615         return ret;
616 }
617 
618 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
619 {
620         int ret;
621 
622         ret = serial_lpc32xx_request_port(port);
623         if (ret < 0)
624                 return;
625         port->type = PORT_UART00;
626         port->fifosize = 64;
627 
628         __serial_uart_flush(port);
629 
630         writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
631                 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
632                LPC32XX_HSUART_IIR(port->membase));
633 
634         writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
635 
636         /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
637            and default FIFO trigger levels */
638         writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
639                LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
640                LPC32XX_HSUART_CTRL(port->membase));
641 }
642 
643 static int serial_lpc32xx_verify_port(struct uart_port *port,
644                                       struct serial_struct *ser)
645 {
646         int ret = 0;
647 
648         if (ser->type != PORT_UART00)
649                 ret = -EINVAL;
650 
651         return ret;
652 }
653 
654 static struct uart_ops serial_lpc32xx_pops = {
655         .tx_empty       = serial_lpc32xx_tx_empty,
656         .set_mctrl      = serial_lpc32xx_set_mctrl,
657         .get_mctrl      = serial_lpc32xx_get_mctrl,
658         .stop_tx        = serial_lpc32xx_stop_tx,
659         .start_tx       = serial_lpc32xx_start_tx,
660         .stop_rx        = serial_lpc32xx_stop_rx,
661         .enable_ms      = serial_lpc32xx_enable_ms,
662         .break_ctl      = serial_lpc32xx_break_ctl,
663         .startup        = serial_lpc32xx_startup,
664         .shutdown       = serial_lpc32xx_shutdown,
665         .set_termios    = serial_lpc32xx_set_termios,
666         .type           = serial_lpc32xx_type,
667         .release_port   = serial_lpc32xx_release_port,
668         .request_port   = serial_lpc32xx_request_port,
669         .config_port    = serial_lpc32xx_config_port,
670         .verify_port    = serial_lpc32xx_verify_port,
671 };
672 
673 /*
674  * Register a set of serial devices attached to a platform device
675  */
676 static int serial_hs_lpc32xx_probe(struct platform_device *pdev)
677 {
678         struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
679         int ret = 0;
680         struct resource *res;
681 
682         if (uarts_registered >= MAX_PORTS) {
683                 dev_err(&pdev->dev,
684                         "Error: Number of possible ports exceeded (%d)!\n",
685                         uarts_registered + 1);
686                 return -ENXIO;
687         }
688 
689         memset(p, 0, sizeof(*p));
690 
691         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
692         if (!res) {
693                 dev_err(&pdev->dev,
694                         "Error getting mem resource for HS UART port %d\n",
695                         uarts_registered);
696                 return -ENXIO;
697         }
698         p->port.mapbase = res->start;
699         p->port.membase = NULL;
700 
701         p->port.irq = platform_get_irq(pdev, 0);
702         if (p->port.irq < 0) {
703                 dev_err(&pdev->dev, "Error getting irq for HS UART port %d\n",
704                         uarts_registered);
705                 return p->port.irq;
706         }
707 
708         p->port.iotype = UPIO_MEM32;
709         p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
710         p->port.regshift = 2;
711         p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
712         p->port.dev = &pdev->dev;
713         p->port.ops = &serial_lpc32xx_pops;
714         p->port.line = uarts_registered++;
715         spin_lock_init(&p->port.lock);
716 
717         /* send port to loopback mode by default */
718         lpc32xx_loopback_set(p->port.mapbase, 1);
719 
720         ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
721 
722         platform_set_drvdata(pdev, p);
723 
724         return ret;
725 }
726 
727 /*
728  * Remove serial ports registered against a platform device.
729  */
730 static int serial_hs_lpc32xx_remove(struct platform_device *pdev)
731 {
732         struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
733 
734         uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
735 
736         return 0;
737 }
738 
739 
740 #ifdef CONFIG_PM
741 static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
742                                      pm_message_t state)
743 {
744         struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
745 
746         uart_suspend_port(&lpc32xx_hs_reg, &p->port);
747 
748         return 0;
749 }
750 
751 static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
752 {
753         struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
754 
755         uart_resume_port(&lpc32xx_hs_reg, &p->port);
756 
757         return 0;
758 }
759 #else
760 #define serial_hs_lpc32xx_suspend       NULL
761 #define serial_hs_lpc32xx_resume        NULL
762 #endif
763 
764 static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
765         { .compatible = "nxp,lpc3220-hsuart" },
766         { /* sentinel */ }
767 };
768 
769 MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
770 
771 static struct platform_driver serial_hs_lpc32xx_driver = {
772         .probe          = serial_hs_lpc32xx_probe,
773         .remove         = serial_hs_lpc32xx_remove,
774         .suspend        = serial_hs_lpc32xx_suspend,
775         .resume         = serial_hs_lpc32xx_resume,
776         .driver         = {
777                 .name   = MODNAME,
778                 .owner  = THIS_MODULE,
779                 .of_match_table = serial_hs_lpc32xx_dt_ids,
780         },
781 };
782 
783 static int __init lpc32xx_hsuart_init(void)
784 {
785         int ret;
786 
787         ret = uart_register_driver(&lpc32xx_hs_reg);
788         if (ret)
789                 return ret;
790 
791         ret = platform_driver_register(&serial_hs_lpc32xx_driver);
792         if (ret)
793                 uart_unregister_driver(&lpc32xx_hs_reg);
794 
795         return ret;
796 }
797 
798 static void __exit lpc32xx_hsuart_exit(void)
799 {
800         platform_driver_unregister(&serial_hs_lpc32xx_driver);
801         uart_unregister_driver(&lpc32xx_hs_reg);
802 }
803 
804 module_init(lpc32xx_hsuart_init);
805 module_exit(lpc32xx_hsuart_exit);
806 
807 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
808 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
809 MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
810 MODULE_LICENSE("GPL");
811 

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