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Linux/drivers/tty/serial/imx.c

  1 /*
  2  * Driver for Motorola/Freescale IMX serial ports
  3  *
  4  * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  5  *
  6  * Author: Sascha Hauer <sascha@saschahauer.de>
  7  * Copyright (C) 2004 Pengutronix
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License as published by
 11  * the Free Software Foundation; either version 2 of the License, or
 12  * (at your option) any later version.
 13  *
 14  * This program is distributed in the hope that it will be useful,
 15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17  * GNU General Public License for more details.
 18  */
 19 
 20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 21 #define SUPPORT_SYSRQ
 22 #endif
 23 
 24 #include <linux/module.h>
 25 #include <linux/ioport.h>
 26 #include <linux/init.h>
 27 #include <linux/console.h>
 28 #include <linux/sysrq.h>
 29 #include <linux/platform_device.h>
 30 #include <linux/tty.h>
 31 #include <linux/tty_flip.h>
 32 #include <linux/serial_core.h>
 33 #include <linux/serial.h>
 34 #include <linux/clk.h>
 35 #include <linux/delay.h>
 36 #include <linux/rational.h>
 37 #include <linux/slab.h>
 38 #include <linux/of.h>
 39 #include <linux/of_device.h>
 40 #include <linux/io.h>
 41 #include <linux/dma-mapping.h>
 42 
 43 #include <asm/irq.h>
 44 #include <linux/platform_data/serial-imx.h>
 45 #include <linux/platform_data/dma-imx.h>
 46 
 47 #include "serial_mctrl_gpio.h"
 48 
 49 /* Register definitions */
 50 #define URXD0 0x0  /* Receiver Register */
 51 #define URTX0 0x40 /* Transmitter Register */
 52 #define UCR1  0x80 /* Control Register 1 */
 53 #define UCR2  0x84 /* Control Register 2 */
 54 #define UCR3  0x88 /* Control Register 3 */
 55 #define UCR4  0x8c /* Control Register 4 */
 56 #define UFCR  0x90 /* FIFO Control Register */
 57 #define USR1  0x94 /* Status Register 1 */
 58 #define USR2  0x98 /* Status Register 2 */
 59 #define UESC  0x9c /* Escape Character Register */
 60 #define UTIM  0xa0 /* Escape Timer Register */
 61 #define UBIR  0xa4 /* BRM Incremental Register */
 62 #define UBMR  0xa8 /* BRM Modulator Register */
 63 #define UBRC  0xac /* Baud Rate Count Register */
 64 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
 65 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
 66 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
 67 
 68 /* UART Control Register Bit Fields.*/
 69 #define URXD_DUMMY_READ (1<<16)
 70 #define URXD_CHARRDY    (1<<15)
 71 #define URXD_ERR        (1<<14)
 72 #define URXD_OVRRUN     (1<<13)
 73 #define URXD_FRMERR     (1<<12)
 74 #define URXD_BRK        (1<<11)
 75 #define URXD_PRERR      (1<<10)
 76 #define URXD_RX_DATA    (0xFF<<0)
 77 #define UCR1_ADEN       (1<<15) /* Auto detect interrupt */
 78 #define UCR1_ADBR       (1<<14) /* Auto detect baud rate */
 79 #define UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
 80 #define UCR1_IDEN       (1<<12) /* Idle condition interrupt */
 81 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
 82 #define UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
 83 #define UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
 84 #define UCR1_IREN       (1<<7)  /* Infrared interface enable */
 85 #define UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
 86 #define UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
 87 #define UCR1_SNDBRK     (1<<4)  /* Send break */
 88 #define UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
 89 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
 90 #define UCR1_ATDMAEN    (1<<2)  /* Aging DMA Timer Enable */
 91 #define UCR1_DOZE       (1<<1)  /* Doze */
 92 #define UCR1_UARTEN     (1<<0)  /* UART enabled */
 93 #define UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
 94 #define UCR2_IRTS       (1<<14) /* Ignore RTS pin */
 95 #define UCR2_CTSC       (1<<13) /* CTS pin control */
 96 #define UCR2_CTS        (1<<12) /* Clear to send */
 97 #define UCR2_ESCEN      (1<<11) /* Escape enable */
 98 #define UCR2_PREN       (1<<8)  /* Parity enable */
 99 #define UCR2_PROE       (1<<7)  /* Parity odd/even */
100 #define UCR2_STPB       (1<<6)  /* Stop */
101 #define UCR2_WS         (1<<5)  /* Word size */
102 #define UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
103 #define UCR2_ATEN       (1<<3)  /* Aging Timer Enable */
104 #define UCR2_TXEN       (1<<2)  /* Transmitter enabled */
105 #define UCR2_RXEN       (1<<1)  /* Receiver enabled */
106 #define UCR2_SRST       (1<<0)  /* SW reset */
107 #define UCR3_DTREN      (1<<13) /* DTR interrupt enable */
108 #define UCR3_PARERREN   (1<<12) /* Parity enable */
109 #define UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
110 #define UCR3_DSR        (1<<10) /* Data set ready */
111 #define UCR3_DCD        (1<<9)  /* Data carrier detect */
112 #define UCR3_RI         (1<<8)  /* Ring indicator */
113 #define UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
114 #define UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
115 #define UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
116 #define UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
117 #define UCR3_DTRDEN     (1<<3)  /* Data Terminal Ready Delta Enable. */
118 #define IMX21_UCR3_RXDMUXSEL    (1<<2)  /* RXD Muxed Input Select */
119 #define UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
120 #define UCR3_BPEN       (1<<0)  /* Preset registers enable */
121 #define UCR4_CTSTL_SHF  10      /* CTS trigger level shift */
122 #define UCR4_CTSTL_MASK 0x3F    /* CTS trigger is 6 bits wide */
123 #define UCR4_INVR       (1<<9)  /* Inverted infrared reception */
124 #define UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
125 #define UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
126 #define UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
127 #define UCR4_IDDMAEN    (1<<6)  /* DMA IDLE Condition Detected */
128 #define UCR4_IRSC       (1<<5)  /* IR special case */
129 #define UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
130 #define UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
131 #define UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
132 #define UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
133 #define UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
134 #define UFCR_DCEDTE     (1<<6)  /* DCE/DTE mode select */
135 #define UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
136 #define UFCR_RFDIV_REG(x)       (((x) < 7 ? 6 - (x) : 6) << 7)
137 #define UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
138 #define USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
139 #define USR1_RTSS       (1<<14) /* RTS pin status */
140 #define USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
141 #define USR1_RTSD       (1<<12) /* RTS delta */
142 #define USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
143 #define USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
144 #define USR1_RRDY       (1<<9)   /* Receiver ready interrupt/dma flag */
145 #define USR1_AGTIM      (1<<8)   /* Ageing timer interrupt flag */
146 #define USR1_DTRD       (1<<7)   /* DTR Delta */
147 #define USR1_RXDS        (1<<6)  /* Receiver idle interrupt flag */
148 #define USR1_AIRINT      (1<<5)  /* Async IR wake interrupt flag */
149 #define USR1_AWAKE       (1<<4)  /* Aysnc wake interrupt flag */
150 #define USR2_ADET        (1<<15) /* Auto baud rate detect complete */
151 #define USR2_TXFE        (1<<14) /* Transmit buffer FIFO empty */
152 #define USR2_DTRF        (1<<13) /* DTR edge interrupt flag */
153 #define USR2_IDLE        (1<<12) /* Idle condition */
154 #define USR2_RIDELT      (1<<10) /* Ring Interrupt Delta */
155 #define USR2_RIIN        (1<<9)  /* Ring Indicator Input */
156 #define USR2_IRINT       (1<<8)  /* Serial infrared interrupt flag */
157 #define USR2_WAKE        (1<<7)  /* Wake */
158 #define USR2_DCDIN       (1<<5)  /* Data Carrier Detect Input */
159 #define USR2_RTSF        (1<<4)  /* RTS edge interrupt flag */
160 #define USR2_TXDC        (1<<3)  /* Transmitter complete */
161 #define USR2_BRCD        (1<<2)  /* Break condition */
162 #define USR2_ORE        (1<<1)   /* Overrun error */
163 #define USR2_RDR        (1<<0)   /* Recv data ready */
164 #define UTS_FRCPERR     (1<<13) /* Force parity error */
165 #define UTS_LOOP        (1<<12)  /* Loop tx and rx */
166 #define UTS_TXEMPTY      (1<<6)  /* TxFIFO empty */
167 #define UTS_RXEMPTY      (1<<5)  /* RxFIFO empty */
168 #define UTS_TXFULL       (1<<4)  /* TxFIFO full */
169 #define UTS_RXFULL       (1<<3)  /* RxFIFO full */
170 #define UTS_SOFTRST      (1<<0)  /* Software reset */
171 
172 /* We've been assigned a range on the "Low-density serial ports" major */
173 #define SERIAL_IMX_MAJOR        207
174 #define MINOR_START             16
175 #define DEV_NAME                "ttymxc"
176 
177 /*
178  * This determines how often we check the modem status signals
179  * for any change.  They generally aren't connected to an IRQ
180  * so we have to poll them.  We also check immediately before
181  * filling the TX fifo incase CTS has been dropped.
182  */
183 #define MCTRL_TIMEOUT   (250*HZ/1000)
184 
185 #define DRIVER_NAME "IMX-uart"
186 
187 #define UART_NR 8
188 
189 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
190 enum imx_uart_type {
191         IMX1_UART,
192         IMX21_UART,
193         IMX6Q_UART,
194 };
195 
196 /* device type dependent stuff */
197 struct imx_uart_data {
198         unsigned uts_reg;
199         enum imx_uart_type devtype;
200 };
201 
202 struct imx_port {
203         struct uart_port        port;
204         struct timer_list       timer;
205         unsigned int            old_status;
206         unsigned int            have_rtscts:1;
207         unsigned int            dte_mode:1;
208         unsigned int            irda_inv_rx:1;
209         unsigned int            irda_inv_tx:1;
210         unsigned short          trcv_delay; /* transceiver delay */
211         struct clk              *clk_ipg;
212         struct clk              *clk_per;
213         const struct imx_uart_data *devdata;
214 
215         struct mctrl_gpios *gpios;
216 
217         /* DMA fields */
218         unsigned int            dma_is_inited:1;
219         unsigned int            dma_is_enabled:1;
220         unsigned int            dma_is_rxing:1;
221         unsigned int            dma_is_txing:1;
222         struct dma_chan         *dma_chan_rx, *dma_chan_tx;
223         struct scatterlist      rx_sgl, tx_sgl[2];
224         void                    *rx_buf;
225         unsigned int            tx_bytes;
226         unsigned int            dma_tx_nents;
227         wait_queue_head_t       dma_wait;
228         unsigned int            saved_reg[10];
229         bool                    context_saved;
230 };
231 
232 struct imx_port_ucrs {
233         unsigned int    ucr1;
234         unsigned int    ucr2;
235         unsigned int    ucr3;
236 };
237 
238 static struct imx_uart_data imx_uart_devdata[] = {
239         [IMX1_UART] = {
240                 .uts_reg = IMX1_UTS,
241                 .devtype = IMX1_UART,
242         },
243         [IMX21_UART] = {
244                 .uts_reg = IMX21_UTS,
245                 .devtype = IMX21_UART,
246         },
247         [IMX6Q_UART] = {
248                 .uts_reg = IMX21_UTS,
249                 .devtype = IMX6Q_UART,
250         },
251 };
252 
253 static const struct platform_device_id imx_uart_devtype[] = {
254         {
255                 .name = "imx1-uart",
256                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
257         }, {
258                 .name = "imx21-uart",
259                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
260         }, {
261                 .name = "imx6q-uart",
262                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
263         }, {
264                 /* sentinel */
265         }
266 };
267 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
268 
269 static const struct of_device_id imx_uart_dt_ids[] = {
270         { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
271         { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
272         { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
273         { /* sentinel */ }
274 };
275 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
276 
277 static inline unsigned uts_reg(struct imx_port *sport)
278 {
279         return sport->devdata->uts_reg;
280 }
281 
282 static inline int is_imx1_uart(struct imx_port *sport)
283 {
284         return sport->devdata->devtype == IMX1_UART;
285 }
286 
287 static inline int is_imx21_uart(struct imx_port *sport)
288 {
289         return sport->devdata->devtype == IMX21_UART;
290 }
291 
292 static inline int is_imx6q_uart(struct imx_port *sport)
293 {
294         return sport->devdata->devtype == IMX6Q_UART;
295 }
296 /*
297  * Save and restore functions for UCR1, UCR2 and UCR3 registers
298  */
299 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
300 static void imx_port_ucrs_save(struct uart_port *port,
301                                struct imx_port_ucrs *ucr)
302 {
303         /* save control registers */
304         ucr->ucr1 = readl(port->membase + UCR1);
305         ucr->ucr2 = readl(port->membase + UCR2);
306         ucr->ucr3 = readl(port->membase + UCR3);
307 }
308 
309 static void imx_port_ucrs_restore(struct uart_port *port,
310                                   struct imx_port_ucrs *ucr)
311 {
312         /* restore control registers */
313         writel(ucr->ucr1, port->membase + UCR1);
314         writel(ucr->ucr2, port->membase + UCR2);
315         writel(ucr->ucr3, port->membase + UCR3);
316 }
317 #endif
318 
319 static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2)
320 {
321         *ucr2 &= ~UCR2_CTSC;
322         *ucr2 |= UCR2_CTS;
323 
324         mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
325 }
326 
327 static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2)
328 {
329         *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
330 
331         mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
332 }
333 
334 static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2)
335 {
336         *ucr2 |= UCR2_CTSC;
337 }
338 
339 /*
340  * interrupts disabled on entry
341  */
342 static void imx_stop_tx(struct uart_port *port)
343 {
344         struct imx_port *sport = (struct imx_port *)port;
345         unsigned long temp;
346 
347         /*
348          * We are maybe in the SMP context, so if the DMA TX thread is running
349          * on other cpu, we have to wait for it to finish.
350          */
351         if (sport->dma_is_enabled && sport->dma_is_txing)
352                 return;
353 
354         temp = readl(port->membase + UCR1);
355         writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
356 
357         /* in rs485 mode disable transmitter if shifter is empty */
358         if (port->rs485.flags & SER_RS485_ENABLED &&
359             readl(port->membase + USR2) & USR2_TXDC) {
360                 temp = readl(port->membase + UCR2);
361                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
362                         imx_port_rts_inactive(sport, &temp);
363                 else
364                         imx_port_rts_active(sport, &temp);
365                 temp |= UCR2_RXEN;
366                 writel(temp, port->membase + UCR2);
367 
368                 temp = readl(port->membase + UCR4);
369                 temp &= ~UCR4_TCEN;
370                 writel(temp, port->membase + UCR4);
371         }
372 }
373 
374 /*
375  * interrupts disabled on entry
376  */
377 static void imx_stop_rx(struct uart_port *port)
378 {
379         struct imx_port *sport = (struct imx_port *)port;
380         unsigned long temp;
381 
382         if (sport->dma_is_enabled && sport->dma_is_rxing) {
383                 if (sport->port.suspended) {
384                         dmaengine_terminate_all(sport->dma_chan_rx);
385                         sport->dma_is_rxing = 0;
386                 } else {
387                         return;
388                 }
389         }
390 
391         temp = readl(sport->port.membase + UCR2);
392         writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
393 
394         /* disable the `Receiver Ready Interrrupt` */
395         temp = readl(sport->port.membase + UCR1);
396         writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
397 }
398 
399 /*
400  * Set the modem control timer to fire immediately.
401  */
402 static void imx_enable_ms(struct uart_port *port)
403 {
404         struct imx_port *sport = (struct imx_port *)port;
405 
406         mod_timer(&sport->timer, jiffies);
407 
408         mctrl_gpio_enable_ms(sport->gpios);
409 }
410 
411 static void imx_dma_tx(struct imx_port *sport);
412 static inline void imx_transmit_buffer(struct imx_port *sport)
413 {
414         struct circ_buf *xmit = &sport->port.state->xmit;
415         unsigned long temp;
416 
417         if (sport->port.x_char) {
418                 /* Send next char */
419                 writel(sport->port.x_char, sport->port.membase + URTX0);
420                 sport->port.icount.tx++;
421                 sport->port.x_char = 0;
422                 return;
423         }
424 
425         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
426                 imx_stop_tx(&sport->port);
427                 return;
428         }
429 
430         if (sport->dma_is_enabled) {
431                 /*
432                  * We've just sent a X-char Ensure the TX DMA is enabled
433                  * and the TX IRQ is disabled.
434                  **/
435                 temp = readl(sport->port.membase + UCR1);
436                 temp &= ~UCR1_TXMPTYEN;
437                 if (sport->dma_is_txing) {
438                         temp |= UCR1_TDMAEN;
439                         writel(temp, sport->port.membase + UCR1);
440                 } else {
441                         writel(temp, sport->port.membase + UCR1);
442                         imx_dma_tx(sport);
443                 }
444         }
445 
446         while (!uart_circ_empty(xmit) &&
447                !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
448                 /* send xmit->buf[xmit->tail]
449                  * out the port here */
450                 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
451                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
452                 sport->port.icount.tx++;
453         }
454 
455         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
456                 uart_write_wakeup(&sport->port);
457 
458         if (uart_circ_empty(xmit))
459                 imx_stop_tx(&sport->port);
460 }
461 
462 static void dma_tx_callback(void *data)
463 {
464         struct imx_port *sport = data;
465         struct scatterlist *sgl = &sport->tx_sgl[0];
466         struct circ_buf *xmit = &sport->port.state->xmit;
467         unsigned long flags;
468         unsigned long temp;
469 
470         spin_lock_irqsave(&sport->port.lock, flags);
471 
472         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
473 
474         temp = readl(sport->port.membase + UCR1);
475         temp &= ~UCR1_TDMAEN;
476         writel(temp, sport->port.membase + UCR1);
477 
478         /* update the stat */
479         xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
480         sport->port.icount.tx += sport->tx_bytes;
481 
482         dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
483 
484         sport->dma_is_txing = 0;
485 
486         spin_unlock_irqrestore(&sport->port.lock, flags);
487 
488         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
489                 uart_write_wakeup(&sport->port);
490 
491         if (waitqueue_active(&sport->dma_wait)) {
492                 wake_up(&sport->dma_wait);
493                 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
494                 return;
495         }
496 
497         spin_lock_irqsave(&sport->port.lock, flags);
498         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
499                 imx_dma_tx(sport);
500         spin_unlock_irqrestore(&sport->port.lock, flags);
501 }
502 
503 static void imx_dma_tx(struct imx_port *sport)
504 {
505         struct circ_buf *xmit = &sport->port.state->xmit;
506         struct scatterlist *sgl = sport->tx_sgl;
507         struct dma_async_tx_descriptor *desc;
508         struct dma_chan *chan = sport->dma_chan_tx;
509         struct device *dev = sport->port.dev;
510         unsigned long temp;
511         int ret;
512 
513         if (sport->dma_is_txing)
514                 return;
515 
516         sport->tx_bytes = uart_circ_chars_pending(xmit);
517 
518         if (xmit->tail < xmit->head) {
519                 sport->dma_tx_nents = 1;
520                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
521         } else {
522                 sport->dma_tx_nents = 2;
523                 sg_init_table(sgl, 2);
524                 sg_set_buf(sgl, xmit->buf + xmit->tail,
525                                 UART_XMIT_SIZE - xmit->tail);
526                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
527         }
528 
529         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
530         if (ret == 0) {
531                 dev_err(dev, "DMA mapping error for TX.\n");
532                 return;
533         }
534         desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
535                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
536         if (!desc) {
537                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
538                              DMA_TO_DEVICE);
539                 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
540                 return;
541         }
542         desc->callback = dma_tx_callback;
543         desc->callback_param = sport;
544 
545         dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
546                         uart_circ_chars_pending(xmit));
547 
548         temp = readl(sport->port.membase + UCR1);
549         temp |= UCR1_TDMAEN;
550         writel(temp, sport->port.membase + UCR1);
551 
552         /* fire it */
553         sport->dma_is_txing = 1;
554         dmaengine_submit(desc);
555         dma_async_issue_pending(chan);
556         return;
557 }
558 
559 /*
560  * interrupts disabled on entry
561  */
562 static void imx_start_tx(struct uart_port *port)
563 {
564         struct imx_port *sport = (struct imx_port *)port;
565         unsigned long temp;
566 
567         if (port->rs485.flags & SER_RS485_ENABLED) {
568                 temp = readl(port->membase + UCR2);
569                 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
570                         imx_port_rts_inactive(sport, &temp);
571                 else
572                         imx_port_rts_active(sport, &temp);
573                 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
574                         temp &= ~UCR2_RXEN;
575                 writel(temp, port->membase + UCR2);
576 
577                 /* enable transmitter and shifter empty irq */
578                 temp = readl(port->membase + UCR4);
579                 temp |= UCR4_TCEN;
580                 writel(temp, port->membase + UCR4);
581         }
582 
583         if (!sport->dma_is_enabled) {
584                 temp = readl(sport->port.membase + UCR1);
585                 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
586         }
587 
588         if (sport->dma_is_enabled) {
589                 if (sport->port.x_char) {
590                         /* We have X-char to send, so enable TX IRQ and
591                          * disable TX DMA to let TX interrupt to send X-char */
592                         temp = readl(sport->port.membase + UCR1);
593                         temp &= ~UCR1_TDMAEN;
594                         temp |= UCR1_TXMPTYEN;
595                         writel(temp, sport->port.membase + UCR1);
596                         return;
597                 }
598 
599                 if (!uart_circ_empty(&port->state->xmit) &&
600                     !uart_tx_stopped(port))
601                         imx_dma_tx(sport);
602                 return;
603         }
604 }
605 
606 static irqreturn_t imx_rtsint(int irq, void *dev_id)
607 {
608         struct imx_port *sport = dev_id;
609         unsigned int val;
610         unsigned long flags;
611 
612         spin_lock_irqsave(&sport->port.lock, flags);
613 
614         writel(USR1_RTSD, sport->port.membase + USR1);
615         val = readl(sport->port.membase + USR1) & USR1_RTSS;
616         uart_handle_cts_change(&sport->port, !!val);
617         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
618 
619         spin_unlock_irqrestore(&sport->port.lock, flags);
620         return IRQ_HANDLED;
621 }
622 
623 static irqreturn_t imx_txint(int irq, void *dev_id)
624 {
625         struct imx_port *sport = dev_id;
626         unsigned long flags;
627 
628         spin_lock_irqsave(&sport->port.lock, flags);
629         imx_transmit_buffer(sport);
630         spin_unlock_irqrestore(&sport->port.lock, flags);
631         return IRQ_HANDLED;
632 }
633 
634 static irqreturn_t imx_rxint(int irq, void *dev_id)
635 {
636         struct imx_port *sport = dev_id;
637         unsigned int rx, flg, ignored = 0;
638         struct tty_port *port = &sport->port.state->port;
639         unsigned long flags, temp;
640 
641         spin_lock_irqsave(&sport->port.lock, flags);
642 
643         while (readl(sport->port.membase + USR2) & USR2_RDR) {
644                 flg = TTY_NORMAL;
645                 sport->port.icount.rx++;
646 
647                 rx = readl(sport->port.membase + URXD0);
648 
649                 temp = readl(sport->port.membase + USR2);
650                 if (temp & USR2_BRCD) {
651                         writel(USR2_BRCD, sport->port.membase + USR2);
652                         if (uart_handle_break(&sport->port))
653                                 continue;
654                 }
655 
656                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
657                         continue;
658 
659                 if (unlikely(rx & URXD_ERR)) {
660                         if (rx & URXD_BRK)
661                                 sport->port.icount.brk++;
662                         else if (rx & URXD_PRERR)
663                                 sport->port.icount.parity++;
664                         else if (rx & URXD_FRMERR)
665                                 sport->port.icount.frame++;
666                         if (rx & URXD_OVRRUN)
667                                 sport->port.icount.overrun++;
668 
669                         if (rx & sport->port.ignore_status_mask) {
670                                 if (++ignored > 100)
671                                         goto out;
672                                 continue;
673                         }
674 
675                         rx &= (sport->port.read_status_mask | 0xFF);
676 
677                         if (rx & URXD_BRK)
678                                 flg = TTY_BREAK;
679                         else if (rx & URXD_PRERR)
680                                 flg = TTY_PARITY;
681                         else if (rx & URXD_FRMERR)
682                                 flg = TTY_FRAME;
683                         if (rx & URXD_OVRRUN)
684                                 flg = TTY_OVERRUN;
685 
686 #ifdef SUPPORT_SYSRQ
687                         sport->port.sysrq = 0;
688 #endif
689                 }
690 
691                 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
692                         goto out;
693 
694                 if (tty_insert_flip_char(port, rx, flg) == 0)
695                         sport->port.icount.buf_overrun++;
696         }
697 
698 out:
699         spin_unlock_irqrestore(&sport->port.lock, flags);
700         tty_flip_buffer_push(port);
701         return IRQ_HANDLED;
702 }
703 
704 static int start_rx_dma(struct imx_port *sport);
705 /*
706  * If the RXFIFO is filled with some data, and then we
707  * arise a DMA operation to receive them.
708  */
709 static void imx_dma_rxint(struct imx_port *sport)
710 {
711         unsigned long temp;
712         unsigned long flags;
713 
714         spin_lock_irqsave(&sport->port.lock, flags);
715 
716         temp = readl(sport->port.membase + USR2);
717         if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
718                 sport->dma_is_rxing = 1;
719 
720                 /* disable the receiver ready and aging timer interrupts */
721                 temp = readl(sport->port.membase + UCR1);
722                 temp &= ~(UCR1_RRDYEN);
723                 writel(temp, sport->port.membase + UCR1);
724 
725                 temp = readl(sport->port.membase + UCR2);
726                 temp &= ~(UCR2_ATEN);
727                 writel(temp, sport->port.membase + UCR2);
728 
729                 /* tell the DMA to receive the data. */
730                 start_rx_dma(sport);
731         }
732 
733         spin_unlock_irqrestore(&sport->port.lock, flags);
734 }
735 
736 /*
737  * We have a modem side uart, so the meanings of RTS and CTS are inverted.
738  */
739 static unsigned int imx_get_hwmctrl(struct imx_port *sport)
740 {
741         unsigned int tmp = TIOCM_DSR;
742         unsigned usr1 = readl(sport->port.membase + USR1);
743 
744         if (usr1 & USR1_RTSS)
745                 tmp |= TIOCM_CTS;
746 
747         /* in DCE mode DCDIN is always 0 */
748         if (!(usr1 & USR2_DCDIN))
749                 tmp |= TIOCM_CAR;
750 
751         if (sport->dte_mode)
752                 if (!(readl(sport->port.membase + USR2) & USR2_RIIN))
753                         tmp |= TIOCM_RI;
754 
755         return tmp;
756 }
757 
758 /*
759  * Handle any change of modem status signal since we were last called.
760  */
761 static void imx_mctrl_check(struct imx_port *sport)
762 {
763         unsigned int status, changed;
764 
765         status = imx_get_hwmctrl(sport);
766         changed = status ^ sport->old_status;
767 
768         if (changed == 0)
769                 return;
770 
771         sport->old_status = status;
772 
773         if (changed & TIOCM_RI && status & TIOCM_RI)
774                 sport->port.icount.rng++;
775         if (changed & TIOCM_DSR)
776                 sport->port.icount.dsr++;
777         if (changed & TIOCM_CAR)
778                 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
779         if (changed & TIOCM_CTS)
780                 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
781 
782         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
783 }
784 
785 static irqreturn_t imx_int(int irq, void *dev_id)
786 {
787         struct imx_port *sport = dev_id;
788         unsigned int sts;
789         unsigned int sts2;
790         irqreturn_t ret = IRQ_NONE;
791 
792         sts = readl(sport->port.membase + USR1);
793         sts2 = readl(sport->port.membase + USR2);
794 
795         if (sts & (USR1_RRDY | USR1_AGTIM)) {
796                 if (sport->dma_is_enabled)
797                         imx_dma_rxint(sport);
798                 else
799                         imx_rxint(irq, dev_id);
800                 ret = IRQ_HANDLED;
801         }
802 
803         if ((sts & USR1_TRDY &&
804              readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
805             (sts2 & USR2_TXDC &&
806              readl(sport->port.membase + UCR4) & UCR4_TCEN)) {
807                 imx_txint(irq, dev_id);
808                 ret = IRQ_HANDLED;
809         }
810 
811         if (sts & USR1_DTRD) {
812                 unsigned long flags;
813 
814                 if (sts & USR1_DTRD)
815                         writel(USR1_DTRD, sport->port.membase + USR1);
816 
817                 spin_lock_irqsave(&sport->port.lock, flags);
818                 imx_mctrl_check(sport);
819                 spin_unlock_irqrestore(&sport->port.lock, flags);
820 
821                 ret = IRQ_HANDLED;
822         }
823 
824         if (sts & USR1_RTSD) {
825                 imx_rtsint(irq, dev_id);
826                 ret = IRQ_HANDLED;
827         }
828 
829         if (sts & USR1_AWAKE) {
830                 writel(USR1_AWAKE, sport->port.membase + USR1);
831                 ret = IRQ_HANDLED;
832         }
833 
834         if (sts2 & USR2_ORE) {
835                 sport->port.icount.overrun++;
836                 writel(USR2_ORE, sport->port.membase + USR2);
837                 ret = IRQ_HANDLED;
838         }
839 
840         return ret;
841 }
842 
843 /*
844  * Return TIOCSER_TEMT when transmitter is not busy.
845  */
846 static unsigned int imx_tx_empty(struct uart_port *port)
847 {
848         struct imx_port *sport = (struct imx_port *)port;
849         unsigned int ret;
850 
851         ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ?  TIOCSER_TEMT : 0;
852 
853         /* If the TX DMA is working, return 0. */
854         if (sport->dma_is_enabled && sport->dma_is_txing)
855                 ret = 0;
856 
857         return ret;
858 }
859 
860 static unsigned int imx_get_mctrl(struct uart_port *port)
861 {
862         struct imx_port *sport = (struct imx_port *)port;
863         unsigned int ret = imx_get_hwmctrl(sport);
864 
865         mctrl_gpio_get(sport->gpios, &ret);
866 
867         return ret;
868 }
869 
870 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
871 {
872         struct imx_port *sport = (struct imx_port *)port;
873         unsigned long temp;
874 
875         if (!(port->rs485.flags & SER_RS485_ENABLED)) {
876                 temp = readl(sport->port.membase + UCR2);
877                 temp &= ~(UCR2_CTS | UCR2_CTSC);
878                 if (mctrl & TIOCM_RTS)
879                         temp |= UCR2_CTS | UCR2_CTSC;
880                 writel(temp, sport->port.membase + UCR2);
881         }
882 
883         temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR;
884         if (!(mctrl & TIOCM_DTR))
885                 temp |= UCR3_DSR;
886         writel(temp, sport->port.membase + UCR3);
887 
888         temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
889         if (mctrl & TIOCM_LOOP)
890                 temp |= UTS_LOOP;
891         writel(temp, sport->port.membase + uts_reg(sport));
892 
893         mctrl_gpio_set(sport->gpios, mctrl);
894 }
895 
896 /*
897  * Interrupts always disabled.
898  */
899 static void imx_break_ctl(struct uart_port *port, int break_state)
900 {
901         struct imx_port *sport = (struct imx_port *)port;
902         unsigned long flags, temp;
903 
904         spin_lock_irqsave(&sport->port.lock, flags);
905 
906         temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
907 
908         if (break_state != 0)
909                 temp |= UCR1_SNDBRK;
910 
911         writel(temp, sport->port.membase + UCR1);
912 
913         spin_unlock_irqrestore(&sport->port.lock, flags);
914 }
915 
916 /*
917  * This is our per-port timeout handler, for checking the
918  * modem status signals.
919  */
920 static void imx_timeout(unsigned long data)
921 {
922         struct imx_port *sport = (struct imx_port *)data;
923         unsigned long flags;
924 
925         if (sport->port.state) {
926                 spin_lock_irqsave(&sport->port.lock, flags);
927                 imx_mctrl_check(sport);
928                 spin_unlock_irqrestore(&sport->port.lock, flags);
929 
930                 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
931         }
932 }
933 
934 #define RX_BUF_SIZE     (PAGE_SIZE)
935 static void imx_rx_dma_done(struct imx_port *sport)
936 {
937         unsigned long temp;
938         unsigned long flags;
939 
940         spin_lock_irqsave(&sport->port.lock, flags);
941 
942         /* re-enable interrupts to get notified when new symbols are incoming */
943         temp = readl(sport->port.membase + UCR1);
944         temp |= UCR1_RRDYEN;
945         writel(temp, sport->port.membase + UCR1);
946 
947         temp = readl(sport->port.membase + UCR2);
948         temp |= UCR2_ATEN;
949         writel(temp, sport->port.membase + UCR2);
950 
951         sport->dma_is_rxing = 0;
952 
953         /* Is the shutdown waiting for us? */
954         if (waitqueue_active(&sport->dma_wait))
955                 wake_up(&sport->dma_wait);
956 
957         spin_unlock_irqrestore(&sport->port.lock, flags);
958 }
959 
960 /*
961  * There are two kinds of RX DMA interrupts(such as in the MX6Q):
962  *   [1] the RX DMA buffer is full.
963  *   [2] the aging timer expires
964  *
965  * Condition [2] is triggered when a character has been sitting in the FIFO
966  * for at least 8 byte durations.
967  */
968 static void dma_rx_callback(void *data)
969 {
970         struct imx_port *sport = data;
971         struct dma_chan *chan = sport->dma_chan_rx;
972         struct scatterlist *sgl = &sport->rx_sgl;
973         struct tty_port *port = &sport->port.state->port;
974         struct dma_tx_state state;
975         enum dma_status status;
976         unsigned int count;
977 
978         /* unmap it first */
979         dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
980 
981         status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
982         count = RX_BUF_SIZE - state.residue;
983 
984         dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
985 
986         if (count) {
987                 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
988                         int bytes = tty_insert_flip_string(port, sport->rx_buf,
989                                         count);
990 
991                         if (bytes != count)
992                                 sport->port.icount.buf_overrun++;
993                 }
994                 tty_flip_buffer_push(port);
995                 sport->port.icount.rx += count;
996         }
997 
998         /*
999          * Restart RX DMA directly if more data is available in order to skip
1000          * the roundtrip through the IRQ handler. If there is some data already
1001          * in the FIFO, DMA needs to be restarted soon anyways.
1002          *
1003          * Otherwise stop the DMA and reactivate FIFO IRQs to restart DMA once
1004          * data starts to arrive again.
1005          */
1006         if (readl(sport->port.membase + USR2) & USR2_RDR)
1007                 start_rx_dma(sport);
1008         else
1009                 imx_rx_dma_done(sport);
1010 }
1011 
1012 static int start_rx_dma(struct imx_port *sport)
1013 {
1014         struct scatterlist *sgl = &sport->rx_sgl;
1015         struct dma_chan *chan = sport->dma_chan_rx;
1016         struct device *dev = sport->port.dev;
1017         struct dma_async_tx_descriptor *desc;
1018         int ret;
1019 
1020         sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1021         ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1022         if (ret == 0) {
1023                 dev_err(dev, "DMA mapping error for RX.\n");
1024                 return -EINVAL;
1025         }
1026         desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
1027                                         DMA_PREP_INTERRUPT);
1028         if (!desc) {
1029                 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1030                 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1031                 return -EINVAL;
1032         }
1033         desc->callback = dma_rx_callback;
1034         desc->callback_param = sport;
1035 
1036         dev_dbg(dev, "RX: prepare for the DMA.\n");
1037         dmaengine_submit(desc);
1038         dma_async_issue_pending(chan);
1039         return 0;
1040 }
1041 
1042 #define TXTL_DEFAULT 2 /* reset default */
1043 #define RXTL_DEFAULT 1 /* reset default */
1044 #define TXTL_DMA 8 /* DMA burst setting */
1045 #define RXTL_DMA 9 /* DMA burst setting */
1046 
1047 static void imx_setup_ufcr(struct imx_port *sport,
1048                           unsigned char txwl, unsigned char rxwl)
1049 {
1050         unsigned int val;
1051 
1052         /* set receiver / transmitter trigger level */
1053         val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1054         val |= txwl << UFCR_TXTL_SHF | rxwl;
1055         writel(val, sport->port.membase + UFCR);
1056 }
1057 
1058 static void imx_uart_dma_exit(struct imx_port *sport)
1059 {
1060         if (sport->dma_chan_rx) {
1061                 dma_release_channel(sport->dma_chan_rx);
1062                 sport->dma_chan_rx = NULL;
1063 
1064                 kfree(sport->rx_buf);
1065                 sport->rx_buf = NULL;
1066         }
1067 
1068         if (sport->dma_chan_tx) {
1069                 dma_release_channel(sport->dma_chan_tx);
1070                 sport->dma_chan_tx = NULL;
1071         }
1072 
1073         sport->dma_is_inited = 0;
1074 }
1075 
1076 static int imx_uart_dma_init(struct imx_port *sport)
1077 {
1078         struct dma_slave_config slave_config = {};
1079         struct device *dev = sport->port.dev;
1080         int ret;
1081 
1082         /* Prepare for RX : */
1083         sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1084         if (!sport->dma_chan_rx) {
1085                 dev_dbg(dev, "cannot get the DMA channel.\n");
1086                 ret = -EINVAL;
1087                 goto err;
1088         }
1089 
1090         slave_config.direction = DMA_DEV_TO_MEM;
1091         slave_config.src_addr = sport->port.mapbase + URXD0;
1092         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1093         /* one byte less than the watermark level to enable the aging timer */
1094         slave_config.src_maxburst = RXTL_DMA - 1;
1095         ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1096         if (ret) {
1097                 dev_err(dev, "error in RX dma configuration.\n");
1098                 goto err;
1099         }
1100 
1101         sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1102         if (!sport->rx_buf) {
1103                 ret = -ENOMEM;
1104                 goto err;
1105         }
1106 
1107         /* Prepare for TX : */
1108         sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1109         if (!sport->dma_chan_tx) {
1110                 dev_err(dev, "cannot get the TX DMA channel!\n");
1111                 ret = -EINVAL;
1112                 goto err;
1113         }
1114 
1115         slave_config.direction = DMA_MEM_TO_DEV;
1116         slave_config.dst_addr = sport->port.mapbase + URTX0;
1117         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1118         slave_config.dst_maxburst = TXTL_DMA;
1119         ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1120         if (ret) {
1121                 dev_err(dev, "error in TX dma configuration.");
1122                 goto err;
1123         }
1124 
1125         sport->dma_is_inited = 1;
1126 
1127         return 0;
1128 err:
1129         imx_uart_dma_exit(sport);
1130         return ret;
1131 }
1132 
1133 static void imx_enable_dma(struct imx_port *sport)
1134 {
1135         unsigned long temp;
1136 
1137         init_waitqueue_head(&sport->dma_wait);
1138 
1139         /* set UCR1 */
1140         temp = readl(sport->port.membase + UCR1);
1141         temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN;
1142         writel(temp, sport->port.membase + UCR1);
1143 
1144         temp = readl(sport->port.membase + UCR2);
1145         temp |= UCR2_ATEN;
1146         writel(temp, sport->port.membase + UCR2);
1147 
1148         imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1149 
1150         sport->dma_is_enabled = 1;
1151 }
1152 
1153 static void imx_disable_dma(struct imx_port *sport)
1154 {
1155         unsigned long temp;
1156 
1157         /* clear UCR1 */
1158         temp = readl(sport->port.membase + UCR1);
1159         temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1160         writel(temp, sport->port.membase + UCR1);
1161 
1162         /* clear UCR2 */
1163         temp = readl(sport->port.membase + UCR2);
1164         temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN);
1165         writel(temp, sport->port.membase + UCR2);
1166 
1167         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1168 
1169         sport->dma_is_enabled = 0;
1170 }
1171 
1172 /* half the RX buffer size */
1173 #define CTSTL 16
1174 
1175 static int imx_startup(struct uart_port *port)
1176 {
1177         struct imx_port *sport = (struct imx_port *)port;
1178         int retval, i;
1179         unsigned long flags, temp;
1180 
1181         retval = clk_prepare_enable(sport->clk_per);
1182         if (retval)
1183                 return retval;
1184         retval = clk_prepare_enable(sport->clk_ipg);
1185         if (retval) {
1186                 clk_disable_unprepare(sport->clk_per);
1187                 return retval;
1188         }
1189 
1190         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1191 
1192         /* disable the DREN bit (Data Ready interrupt enable) before
1193          * requesting IRQs
1194          */
1195         temp = readl(sport->port.membase + UCR4);
1196 
1197         /* set the trigger level for CTS */
1198         temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1199         temp |= CTSTL << UCR4_CTSTL_SHF;
1200 
1201         writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1202 
1203         /* Can we enable the DMA support? */
1204         if (is_imx6q_uart(sport) && !uart_console(port) &&
1205             !sport->dma_is_inited)
1206                 imx_uart_dma_init(sport);
1207 
1208         spin_lock_irqsave(&sport->port.lock, flags);
1209         /* Reset fifo's and state machines */
1210         i = 100;
1211 
1212         temp = readl(sport->port.membase + UCR2);
1213         temp &= ~UCR2_SRST;
1214         writel(temp, sport->port.membase + UCR2);
1215 
1216         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1217                 udelay(1);
1218 
1219         /*
1220          * Finally, clear and enable interrupts
1221          */
1222         writel(USR1_RTSD | USR1_DTRD, sport->port.membase + USR1);
1223         writel(USR2_ORE, sport->port.membase + USR2);
1224 
1225         if (sport->dma_is_inited && !sport->dma_is_enabled)
1226                 imx_enable_dma(sport);
1227 
1228         temp = readl(sport->port.membase + UCR1);
1229         temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1230 
1231         writel(temp, sport->port.membase + UCR1);
1232 
1233         temp = readl(sport->port.membase + UCR4);
1234         temp |= UCR4_OREN;
1235         writel(temp, sport->port.membase + UCR4);
1236 
1237         temp = readl(sport->port.membase + UCR2);
1238         temp |= (UCR2_RXEN | UCR2_TXEN);
1239         if (!sport->have_rtscts)
1240                 temp |= UCR2_IRTS;
1241         /*
1242          * make sure the edge sensitive RTS-irq is disabled,
1243          * we're using RTSD instead.
1244          */
1245         if (!is_imx1_uart(sport))
1246                 temp &= ~UCR2_RTSEN;
1247         writel(temp, sport->port.membase + UCR2);
1248 
1249         if (!is_imx1_uart(sport)) {
1250                 temp = readl(sport->port.membase + UCR3);
1251 
1252                 /*
1253                  * The effect of RI and DCD differs depending on the UFCR_DCEDTE
1254                  * bit. In DCE mode they control the outputs, in DTE mode they
1255                  * enable the respective irqs. At least the DCD irq cannot be
1256                  * cleared on i.MX25 at least, so it's not usable and must be
1257                  * disabled. I don't have test hardware to check if RI has the
1258                  * same problem but I consider this likely so it's disabled for
1259                  * now, too.
1260                  */
1261                 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP |
1262                         UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1263 
1264                 if (sport->dte_mode)
1265                         temp &= ~(UCR3_RI | UCR3_DCD);
1266 
1267                 writel(temp, sport->port.membase + UCR3);
1268         }
1269 
1270         /*
1271          * Enable modem status interrupts
1272          */
1273         imx_enable_ms(&sport->port);
1274         spin_unlock_irqrestore(&sport->port.lock, flags);
1275 
1276         return 0;
1277 }
1278 
1279 static void imx_shutdown(struct uart_port *port)
1280 {
1281         struct imx_port *sport = (struct imx_port *)port;
1282         unsigned long temp;
1283         unsigned long flags;
1284 
1285         if (sport->dma_is_enabled) {
1286                 int ret;
1287 
1288                 /* We have to wait for the DMA to finish. */
1289                 ret = wait_event_interruptible(sport->dma_wait,
1290                         !sport->dma_is_rxing && !sport->dma_is_txing);
1291                 if (ret != 0) {
1292                         sport->dma_is_rxing = 0;
1293                         sport->dma_is_txing = 0;
1294                         dmaengine_terminate_all(sport->dma_chan_tx);
1295                         dmaengine_terminate_all(sport->dma_chan_rx);
1296                 }
1297                 spin_lock_irqsave(&sport->port.lock, flags);
1298                 imx_stop_tx(port);
1299                 imx_stop_rx(port);
1300                 imx_disable_dma(sport);
1301                 spin_unlock_irqrestore(&sport->port.lock, flags);
1302                 imx_uart_dma_exit(sport);
1303         }
1304 
1305         mctrl_gpio_disable_ms(sport->gpios);
1306 
1307         spin_lock_irqsave(&sport->port.lock, flags);
1308         temp = readl(sport->port.membase + UCR2);
1309         temp &= ~(UCR2_TXEN);
1310         writel(temp, sport->port.membase + UCR2);
1311         spin_unlock_irqrestore(&sport->port.lock, flags);
1312 
1313         /*
1314          * Stop our timer.
1315          */
1316         del_timer_sync(&sport->timer);
1317 
1318         /*
1319          * Disable all interrupts, port and break condition.
1320          */
1321 
1322         spin_lock_irqsave(&sport->port.lock, flags);
1323         temp = readl(sport->port.membase + UCR1);
1324         temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1325 
1326         writel(temp, sport->port.membase + UCR1);
1327         spin_unlock_irqrestore(&sport->port.lock, flags);
1328 
1329         clk_disable_unprepare(sport->clk_per);
1330         clk_disable_unprepare(sport->clk_ipg);
1331 }
1332 
1333 static void imx_flush_buffer(struct uart_port *port)
1334 {
1335         struct imx_port *sport = (struct imx_port *)port;
1336         struct scatterlist *sgl = &sport->tx_sgl[0];
1337         unsigned long temp;
1338         int i = 100, ubir, ubmr, uts;
1339 
1340         if (!sport->dma_chan_tx)
1341                 return;
1342 
1343         sport->tx_bytes = 0;
1344         dmaengine_terminate_all(sport->dma_chan_tx);
1345         if (sport->dma_is_txing) {
1346                 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1347                              DMA_TO_DEVICE);
1348                 temp = readl(sport->port.membase + UCR1);
1349                 temp &= ~UCR1_TDMAEN;
1350                 writel(temp, sport->port.membase + UCR1);
1351                 sport->dma_is_txing = false;
1352         }
1353 
1354         /*
1355          * According to the Reference Manual description of the UART SRST bit:
1356          * "Reset the transmit and receive state machines,
1357          * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1358          * and UTS[6-3]". As we don't need to restore the old values from
1359          * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1360          */
1361         ubir = readl(sport->port.membase + UBIR);
1362         ubmr = readl(sport->port.membase + UBMR);
1363         uts = readl(sport->port.membase + IMX21_UTS);
1364 
1365         temp = readl(sport->port.membase + UCR2);
1366         temp &= ~UCR2_SRST;
1367         writel(temp, sport->port.membase + UCR2);
1368 
1369         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1370                 udelay(1);
1371 
1372         /* Restore the registers */
1373         writel(ubir, sport->port.membase + UBIR);
1374         writel(ubmr, sport->port.membase + UBMR);
1375         writel(uts, sport->port.membase + IMX21_UTS);
1376 }
1377 
1378 static void
1379 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1380                    struct ktermios *old)
1381 {
1382         struct imx_port *sport = (struct imx_port *)port;
1383         unsigned long flags;
1384         unsigned long ucr2, old_ucr1, old_ucr2;
1385         unsigned int baud, quot;
1386         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1387         unsigned long div, ufcr;
1388         unsigned long num, denom;
1389         uint64_t tdiv64;
1390 
1391         /*
1392          * We only support CS7 and CS8.
1393          */
1394         while ((termios->c_cflag & CSIZE) != CS7 &&
1395                (termios->c_cflag & CSIZE) != CS8) {
1396                 termios->c_cflag &= ~CSIZE;
1397                 termios->c_cflag |= old_csize;
1398                 old_csize = CS8;
1399         }
1400 
1401         if ((termios->c_cflag & CSIZE) == CS8)
1402                 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1403         else
1404                 ucr2 = UCR2_SRST | UCR2_IRTS;
1405 
1406         if (termios->c_cflag & CRTSCTS) {
1407                 if (sport->have_rtscts) {
1408                         ucr2 &= ~UCR2_IRTS;
1409 
1410                         if (port->rs485.flags & SER_RS485_ENABLED) {
1411                                 /*
1412                                  * RTS is mandatory for rs485 operation, so keep
1413                                  * it under manual control and keep transmitter
1414                                  * disabled.
1415                                  */
1416                                 if (port->rs485.flags &
1417                                     SER_RS485_RTS_AFTER_SEND)
1418                                         imx_port_rts_inactive(sport, &ucr2);
1419                                 else
1420                                         imx_port_rts_active(sport, &ucr2);
1421                         } else {
1422                                 imx_port_rts_auto(sport, &ucr2);
1423                         }
1424                 } else {
1425                         termios->c_cflag &= ~CRTSCTS;
1426                 }
1427         } else if (port->rs485.flags & SER_RS485_ENABLED) {
1428                 /* disable transmitter */
1429                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1430                         imx_port_rts_inactive(sport, &ucr2);
1431                 else
1432                         imx_port_rts_active(sport, &ucr2);
1433         }
1434 
1435 
1436         if (termios->c_cflag & CSTOPB)
1437                 ucr2 |= UCR2_STPB;
1438         if (termios->c_cflag & PARENB) {
1439                 ucr2 |= UCR2_PREN;
1440                 if (termios->c_cflag & PARODD)
1441                         ucr2 |= UCR2_PROE;
1442         }
1443 
1444         del_timer_sync(&sport->timer);
1445 
1446         /*
1447          * Ask the core to calculate the divisor for us.
1448          */
1449         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1450         quot = uart_get_divisor(port, baud);
1451 
1452         spin_lock_irqsave(&sport->port.lock, flags);
1453 
1454         sport->port.read_status_mask = 0;
1455         if (termios->c_iflag & INPCK)
1456                 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1457         if (termios->c_iflag & (BRKINT | PARMRK))
1458                 sport->port.read_status_mask |= URXD_BRK;
1459 
1460         /*
1461          * Characters to ignore
1462          */
1463         sport->port.ignore_status_mask = 0;
1464         if (termios->c_iflag & IGNPAR)
1465                 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1466         if (termios->c_iflag & IGNBRK) {
1467                 sport->port.ignore_status_mask |= URXD_BRK;
1468                 /*
1469                  * If we're ignoring parity and break indicators,
1470                  * ignore overruns too (for real raw support).
1471                  */
1472                 if (termios->c_iflag & IGNPAR)
1473                         sport->port.ignore_status_mask |= URXD_OVRRUN;
1474         }
1475 
1476         if ((termios->c_cflag & CREAD) == 0)
1477                 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1478 
1479         /*
1480          * Update the per-port timeout.
1481          */
1482         uart_update_timeout(port, termios->c_cflag, baud);
1483 
1484         /*
1485          * disable interrupts and drain transmitter
1486          */
1487         old_ucr1 = readl(sport->port.membase + UCR1);
1488         writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1489                         sport->port.membase + UCR1);
1490 
1491         while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1492                 barrier();
1493 
1494         /* then, disable everything */
1495         old_ucr2 = readl(sport->port.membase + UCR2);
1496         writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN),
1497                         sport->port.membase + UCR2);
1498         old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1499 
1500         /* custom-baudrate handling */
1501         div = sport->port.uartclk / (baud * 16);
1502         if (baud == 38400 && quot != div)
1503                 baud = sport->port.uartclk / (quot * 16);
1504 
1505         div = sport->port.uartclk / (baud * 16);
1506         if (div > 7)
1507                 div = 7;
1508         if (!div)
1509                 div = 1;
1510 
1511         rational_best_approximation(16 * div * baud, sport->port.uartclk,
1512                 1 << 16, 1 << 16, &num, &denom);
1513 
1514         tdiv64 = sport->port.uartclk;
1515         tdiv64 *= num;
1516         do_div(tdiv64, denom * 16 * div);
1517         tty_termios_encode_baud_rate(termios,
1518                                 (speed_t)tdiv64, (speed_t)tdiv64);
1519 
1520         num -= 1;
1521         denom -= 1;
1522 
1523         ufcr = readl(sport->port.membase + UFCR);
1524         ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1525         if (sport->dte_mode)
1526                 ufcr |= UFCR_DCEDTE;
1527         writel(ufcr, sport->port.membase + UFCR);
1528 
1529         writel(num, sport->port.membase + UBIR);
1530         writel(denom, sport->port.membase + UBMR);
1531 
1532         if (!is_imx1_uart(sport))
1533                 writel(sport->port.uartclk / div / 1000,
1534                                 sport->port.membase + IMX21_ONEMS);
1535 
1536         writel(old_ucr1, sport->port.membase + UCR1);
1537 
1538         /* set the parity, stop bits and data size */
1539         writel(ucr2 | old_ucr2, sport->port.membase + UCR2);
1540 
1541         if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1542                 imx_enable_ms(&sport->port);
1543 
1544         spin_unlock_irqrestore(&sport->port.lock, flags);
1545 }
1546 
1547 static const char *imx_type(struct uart_port *port)
1548 {
1549         struct imx_port *sport = (struct imx_port *)port;
1550 
1551         return sport->port.type == PORT_IMX ? "IMX" : NULL;
1552 }
1553 
1554 /*
1555  * Configure/autoconfigure the port.
1556  */
1557 static void imx_config_port(struct uart_port *port, int flags)
1558 {
1559         struct imx_port *sport = (struct imx_port *)port;
1560 
1561         if (flags & UART_CONFIG_TYPE)
1562                 sport->port.type = PORT_IMX;
1563 }
1564 
1565 /*
1566  * Verify the new serial_struct (for TIOCSSERIAL).
1567  * The only change we allow are to the flags and type, and
1568  * even then only between PORT_IMX and PORT_UNKNOWN
1569  */
1570 static int
1571 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1572 {
1573         struct imx_port *sport = (struct imx_port *)port;
1574         int ret = 0;
1575 
1576         if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1577                 ret = -EINVAL;
1578         if (sport->port.irq != ser->irq)
1579                 ret = -EINVAL;
1580         if (ser->io_type != UPIO_MEM)
1581                 ret = -EINVAL;
1582         if (sport->port.uartclk / 16 != ser->baud_base)
1583                 ret = -EINVAL;
1584         if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1585                 ret = -EINVAL;
1586         if (sport->port.iobase != ser->port)
1587                 ret = -EINVAL;
1588         if (ser->hub6 != 0)
1589                 ret = -EINVAL;
1590         return ret;
1591 }
1592 
1593 #if defined(CONFIG_CONSOLE_POLL)
1594 
1595 static int imx_poll_init(struct uart_port *port)
1596 {
1597         struct imx_port *sport = (struct imx_port *)port;
1598         unsigned long flags;
1599         unsigned long temp;
1600         int retval;
1601 
1602         retval = clk_prepare_enable(sport->clk_ipg);
1603         if (retval)
1604                 return retval;
1605         retval = clk_prepare_enable(sport->clk_per);
1606         if (retval)
1607                 clk_disable_unprepare(sport->clk_ipg);
1608 
1609         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1610 
1611         spin_lock_irqsave(&sport->port.lock, flags);
1612 
1613         temp = readl(sport->port.membase + UCR1);
1614         if (is_imx1_uart(sport))
1615                 temp |= IMX1_UCR1_UARTCLKEN;
1616         temp |= UCR1_UARTEN | UCR1_RRDYEN;
1617         temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1618         writel(temp, sport->port.membase + UCR1);
1619 
1620         temp = readl(sport->port.membase + UCR2);
1621         temp |= UCR2_RXEN;
1622         writel(temp, sport->port.membase + UCR2);
1623 
1624         spin_unlock_irqrestore(&sport->port.lock, flags);
1625 
1626         return 0;
1627 }
1628 
1629 static int imx_poll_get_char(struct uart_port *port)
1630 {
1631         if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1632                 return NO_POLL_CHAR;
1633 
1634         return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1635 }
1636 
1637 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1638 {
1639         unsigned int status;
1640 
1641         /* drain */
1642         do {
1643                 status = readl_relaxed(port->membase + USR1);
1644         } while (~status & USR1_TRDY);
1645 
1646         /* write */
1647         writel_relaxed(c, port->membase + URTX0);
1648 
1649         /* flush */
1650         do {
1651                 status = readl_relaxed(port->membase + USR2);
1652         } while (~status & USR2_TXDC);
1653 }
1654 #endif
1655 
1656 static int imx_rs485_config(struct uart_port *port,
1657                             struct serial_rs485 *rs485conf)
1658 {
1659         struct imx_port *sport = (struct imx_port *)port;
1660         unsigned long temp;
1661 
1662         /* unimplemented */
1663         rs485conf->delay_rts_before_send = 0;
1664         rs485conf->delay_rts_after_send = 0;
1665 
1666         /* RTS is required to control the transmitter */
1667         if (!sport->have_rtscts)
1668                 rs485conf->flags &= ~SER_RS485_ENABLED;
1669 
1670         if (rs485conf->flags & SER_RS485_ENABLED) {
1671                 /* disable transmitter */
1672                 temp = readl(sport->port.membase + UCR2);
1673                 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1674                         imx_port_rts_inactive(sport, &temp);
1675                 else
1676                         imx_port_rts_active(sport, &temp);
1677                 writel(temp, sport->port.membase + UCR2);
1678         }
1679 
1680         /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1681         if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1682             rs485conf->flags & SER_RS485_RX_DURING_TX) {
1683                 temp = readl(sport->port.membase + UCR2);
1684                 temp |= UCR2_RXEN;
1685                 writel(temp, sport->port.membase + UCR2);
1686         }
1687 
1688         port->rs485 = *rs485conf;
1689 
1690         return 0;
1691 }
1692 
1693 static struct uart_ops imx_pops = {
1694         .tx_empty       = imx_tx_empty,
1695         .set_mctrl      = imx_set_mctrl,
1696         .get_mctrl      = imx_get_mctrl,
1697         .stop_tx        = imx_stop_tx,
1698         .start_tx       = imx_start_tx,
1699         .stop_rx        = imx_stop_rx,
1700         .enable_ms      = imx_enable_ms,
1701         .break_ctl      = imx_break_ctl,
1702         .startup        = imx_startup,
1703         .shutdown       = imx_shutdown,
1704         .flush_buffer   = imx_flush_buffer,
1705         .set_termios    = imx_set_termios,
1706         .type           = imx_type,
1707         .config_port    = imx_config_port,
1708         .verify_port    = imx_verify_port,
1709 #if defined(CONFIG_CONSOLE_POLL)
1710         .poll_init      = imx_poll_init,
1711         .poll_get_char  = imx_poll_get_char,
1712         .poll_put_char  = imx_poll_put_char,
1713 #endif
1714 };
1715 
1716 static struct imx_port *imx_ports[UART_NR];
1717 
1718 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1719 static void imx_console_putchar(struct uart_port *port, int ch)
1720 {
1721         struct imx_port *sport = (struct imx_port *)port;
1722 
1723         while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1724                 barrier();
1725 
1726         writel(ch, sport->port.membase + URTX0);
1727 }
1728 
1729 /*
1730  * Interrupts are disabled on entering
1731  */
1732 static void
1733 imx_console_write(struct console *co, const char *s, unsigned int count)
1734 {
1735         struct imx_port *sport = imx_ports[co->index];
1736         struct imx_port_ucrs old_ucr;
1737         unsigned int ucr1;
1738         unsigned long flags = 0;
1739         int locked = 1;
1740         int retval;
1741 
1742         retval = clk_enable(sport->clk_per);
1743         if (retval)
1744                 return;
1745         retval = clk_enable(sport->clk_ipg);
1746         if (retval) {
1747                 clk_disable(sport->clk_per);
1748                 return;
1749         }
1750 
1751         if (sport->port.sysrq)
1752                 locked = 0;
1753         else if (oops_in_progress)
1754                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1755         else
1756                 spin_lock_irqsave(&sport->port.lock, flags);
1757 
1758         /*
1759          *      First, save UCR1/2/3 and then disable interrupts
1760          */
1761         imx_port_ucrs_save(&sport->port, &old_ucr);
1762         ucr1 = old_ucr.ucr1;
1763 
1764         if (is_imx1_uart(sport))
1765                 ucr1 |= IMX1_UCR1_UARTCLKEN;
1766         ucr1 |= UCR1_UARTEN;
1767         ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1768 
1769         writel(ucr1, sport->port.membase + UCR1);
1770 
1771         writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1772 
1773         uart_console_write(&sport->port, s, count, imx_console_putchar);
1774 
1775         /*
1776          *      Finally, wait for transmitter to become empty
1777          *      and restore UCR1/2/3
1778          */
1779         while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1780 
1781         imx_port_ucrs_restore(&sport->port, &old_ucr);
1782 
1783         if (locked)
1784                 spin_unlock_irqrestore(&sport->port.lock, flags);
1785 
1786         clk_disable(sport->clk_ipg);
1787         clk_disable(sport->clk_per);
1788 }
1789 
1790 /*
1791  * If the port was already initialised (eg, by a boot loader),
1792  * try to determine the current setup.
1793  */
1794 static void __init
1795 imx_console_get_options(struct imx_port *sport, int *baud,
1796                            int *parity, int *bits)
1797 {
1798 
1799         if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1800                 /* ok, the port was enabled */
1801                 unsigned int ucr2, ubir, ubmr, uartclk;
1802                 unsigned int baud_raw;
1803                 unsigned int ucfr_rfdiv;
1804 
1805                 ucr2 = readl(sport->port.membase + UCR2);
1806 
1807                 *parity = 'n';
1808                 if (ucr2 & UCR2_PREN) {
1809                         if (ucr2 & UCR2_PROE)
1810                                 *parity = 'o';
1811                         else
1812                                 *parity = 'e';
1813                 }
1814 
1815                 if (ucr2 & UCR2_WS)
1816                         *bits = 8;
1817                 else
1818                         *bits = 7;
1819 
1820                 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1821                 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1822 
1823                 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1824                 if (ucfr_rfdiv == 6)
1825                         ucfr_rfdiv = 7;
1826                 else
1827                         ucfr_rfdiv = 6 - ucfr_rfdiv;
1828 
1829                 uartclk = clk_get_rate(sport->clk_per);
1830                 uartclk /= ucfr_rfdiv;
1831 
1832                 {       /*
1833                          * The next code provides exact computation of
1834                          *   baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1835                          * without need of float support or long long division,
1836                          * which would be required to prevent 32bit arithmetic overflow
1837                          */
1838                         unsigned int mul = ubir + 1;
1839                         unsigned int div = 16 * (ubmr + 1);
1840                         unsigned int rem = uartclk % div;
1841 
1842                         baud_raw = (uartclk / div) * mul;
1843                         baud_raw += (rem * mul + div / 2) / div;
1844                         *baud = (baud_raw + 50) / 100 * 100;
1845                 }
1846 
1847                 if (*baud != baud_raw)
1848                         pr_info("Console IMX rounded baud rate from %d to %d\n",
1849                                 baud_raw, *baud);
1850         }
1851 }
1852 
1853 static int __init
1854 imx_console_setup(struct console *co, char *options)
1855 {
1856         struct imx_port *sport;
1857         int baud = 9600;
1858         int bits = 8;
1859         int parity = 'n';
1860         int flow = 'n';
1861         int retval;
1862 
1863         /*
1864          * Check whether an invalid uart number has been specified, and
1865          * if so, search for the first available port that does have
1866          * console support.
1867          */
1868         if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1869                 co->index = 0;
1870         sport = imx_ports[co->index];
1871         if (sport == NULL)
1872                 return -ENODEV;
1873 
1874         /* For setting the registers, we only need to enable the ipg clock. */
1875         retval = clk_prepare_enable(sport->clk_ipg);
1876         if (retval)
1877                 goto error_console;
1878 
1879         if (options)
1880                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1881         else
1882                 imx_console_get_options(sport, &baud, &parity, &bits);
1883 
1884         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1885 
1886         retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1887 
1888         clk_disable(sport->clk_ipg);
1889         if (retval) {
1890                 clk_unprepare(sport->clk_ipg);
1891                 goto error_console;
1892         }
1893 
1894         retval = clk_prepare(sport->clk_per);
1895         if (retval)
1896                 clk_disable_unprepare(sport->clk_ipg);
1897 
1898 error_console:
1899         return retval;
1900 }
1901 
1902 static struct uart_driver imx_reg;
1903 static struct console imx_console = {
1904         .name           = DEV_NAME,
1905         .write          = imx_console_write,
1906         .device         = uart_console_device,
1907         .setup          = imx_console_setup,
1908         .flags          = CON_PRINTBUFFER,
1909         .index          = -1,
1910         .data           = &imx_reg,
1911 };
1912 
1913 #define IMX_CONSOLE     &imx_console
1914 
1915 #ifdef CONFIG_OF
1916 static void imx_console_early_putchar(struct uart_port *port, int ch)
1917 {
1918         while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
1919                 cpu_relax();
1920 
1921         writel_relaxed(ch, port->membase + URTX0);
1922 }
1923 
1924 static void imx_console_early_write(struct console *con, const char *s,
1925                                     unsigned count)
1926 {
1927         struct earlycon_device *dev = con->data;
1928 
1929         uart_console_write(&dev->port, s, count, imx_console_early_putchar);
1930 }
1931 
1932 static int __init
1933 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
1934 {
1935         if (!dev->port.membase)
1936                 return -ENODEV;
1937 
1938         dev->con->write = imx_console_early_write;
1939 
1940         return 0;
1941 }
1942 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
1943 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
1944 #endif
1945 
1946 #else
1947 #define IMX_CONSOLE     NULL
1948 #endif
1949 
1950 static struct uart_driver imx_reg = {
1951         .owner          = THIS_MODULE,
1952         .driver_name    = DRIVER_NAME,
1953         .dev_name       = DEV_NAME,
1954         .major          = SERIAL_IMX_MAJOR,
1955         .minor          = MINOR_START,
1956         .nr             = ARRAY_SIZE(imx_ports),
1957         .cons           = IMX_CONSOLE,
1958 };
1959 
1960 #ifdef CONFIG_OF
1961 /*
1962  * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1963  * could successfully get all information from dt or a negative errno.
1964  */
1965 static int serial_imx_probe_dt(struct imx_port *sport,
1966                 struct platform_device *pdev)
1967 {
1968         struct device_node *np = pdev->dev.of_node;
1969         int ret;
1970 
1971         sport->devdata = of_device_get_match_data(&pdev->dev);
1972         if (!sport->devdata)
1973                 /* no device tree device */
1974                 return 1;
1975 
1976         ret = of_alias_get_id(np, "serial");
1977         if (ret < 0) {
1978                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1979                 return ret;
1980         }
1981         sport->port.line = ret;
1982 
1983         if (of_get_property(np, "uart-has-rtscts", NULL) ||
1984             of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
1985                 sport->have_rtscts = 1;
1986 
1987         if (of_get_property(np, "fsl,dte-mode", NULL))
1988                 sport->dte_mode = 1;
1989 
1990         return 0;
1991 }
1992 #else
1993 static inline int serial_imx_probe_dt(struct imx_port *sport,
1994                 struct platform_device *pdev)
1995 {
1996         return 1;
1997 }
1998 #endif
1999 
2000 static void serial_imx_probe_pdata(struct imx_port *sport,
2001                 struct platform_device *pdev)
2002 {
2003         struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
2004 
2005         sport->port.line = pdev->id;
2006         sport->devdata = (struct imx_uart_data  *) pdev->id_entry->driver_data;
2007 
2008         if (!pdata)
2009                 return;
2010 
2011         if (pdata->flags & IMXUART_HAVE_RTSCTS)
2012                 sport->have_rtscts = 1;
2013 }
2014 
2015 static int serial_imx_probe(struct platform_device *pdev)
2016 {
2017         struct imx_port *sport;
2018         void __iomem *base;
2019         int ret = 0, reg;
2020         struct resource *res;
2021         int txirq, rxirq, rtsirq;
2022 
2023         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2024         if (!sport)
2025                 return -ENOMEM;
2026 
2027         ret = serial_imx_probe_dt(sport, pdev);
2028         if (ret > 0)
2029                 serial_imx_probe_pdata(sport, pdev);
2030         else if (ret < 0)
2031                 return ret;
2032 
2033         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2034         base = devm_ioremap_resource(&pdev->dev, res);
2035         if (IS_ERR(base))
2036                 return PTR_ERR(base);
2037 
2038         rxirq = platform_get_irq(pdev, 0);
2039         txirq = platform_get_irq(pdev, 1);
2040         rtsirq = platform_get_irq(pdev, 2);
2041 
2042         sport->port.dev = &pdev->dev;
2043         sport->port.mapbase = res->start;
2044         sport->port.membase = base;
2045         sport->port.type = PORT_IMX,
2046         sport->port.iotype = UPIO_MEM;
2047         sport->port.irq = rxirq;
2048         sport->port.fifosize = 32;
2049         sport->port.ops = &imx_pops;
2050         sport->port.rs485_config = imx_rs485_config;
2051         sport->port.rs485.flags =
2052                 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
2053         sport->port.flags = UPF_BOOT_AUTOCONF;
2054         init_timer(&sport->timer);
2055         sport->timer.function = imx_timeout;
2056         sport->timer.data     = (unsigned long)sport;
2057 
2058         sport->gpios = mctrl_gpio_init(&sport->port, 0);
2059         if (IS_ERR(sport->gpios))
2060                 return PTR_ERR(sport->gpios);
2061 
2062         sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2063         if (IS_ERR(sport->clk_ipg)) {
2064                 ret = PTR_ERR(sport->clk_ipg);
2065                 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2066                 return ret;
2067         }
2068 
2069         sport->clk_per = devm_clk_get(&pdev->dev, "per");
2070         if (IS_ERR(sport->clk_per)) {
2071                 ret = PTR_ERR(sport->clk_per);
2072                 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2073                 return ret;
2074         }
2075 
2076         sport->port.uartclk = clk_get_rate(sport->clk_per);
2077 
2078         /* For register access, we only need to enable the ipg clock. */
2079         ret = clk_prepare_enable(sport->clk_ipg);
2080         if (ret)
2081                 return ret;
2082 
2083         /* Disable interrupts before requesting them */
2084         reg = readl_relaxed(sport->port.membase + UCR1);
2085         reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2086                  UCR1_TXMPTYEN | UCR1_RTSDEN);
2087         writel_relaxed(reg, sport->port.membase + UCR1);
2088 
2089         clk_disable_unprepare(sport->clk_ipg);
2090 
2091         /*
2092          * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2093          * chips only have one interrupt.
2094          */
2095         if (txirq > 0) {
2096                 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
2097                                        dev_name(&pdev->dev), sport);
2098                 if (ret)
2099                         return ret;
2100 
2101                 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
2102                                        dev_name(&pdev->dev), sport);
2103                 if (ret)
2104                         return ret;
2105         } else {
2106                 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
2107                                        dev_name(&pdev->dev), sport);
2108                 if (ret)
2109                         return ret;
2110         }
2111 
2112         imx_ports[sport->port.line] = sport;
2113 
2114         platform_set_drvdata(pdev, sport);
2115 
2116         return uart_add_one_port(&imx_reg, &sport->port);
2117 }
2118 
2119 static int serial_imx_remove(struct platform_device *pdev)
2120 {
2121         struct imx_port *sport = platform_get_drvdata(pdev);
2122 
2123         return uart_remove_one_port(&imx_reg, &sport->port);
2124 }
2125 
2126 static void serial_imx_restore_context(struct imx_port *sport)
2127 {
2128         if (!sport->context_saved)
2129                 return;
2130 
2131         writel(sport->saved_reg[4], sport->port.membase + UFCR);
2132         writel(sport->saved_reg[5], sport->port.membase + UESC);
2133         writel(sport->saved_reg[6], sport->port.membase + UTIM);
2134         writel(sport->saved_reg[7], sport->port.membase + UBIR);
2135         writel(sport->saved_reg[8], sport->port.membase + UBMR);
2136         writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
2137         writel(sport->saved_reg[0], sport->port.membase + UCR1);
2138         writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
2139         writel(sport->saved_reg[2], sport->port.membase + UCR3);
2140         writel(sport->saved_reg[3], sport->port.membase + UCR4);
2141         sport->context_saved = false;
2142 }
2143 
2144 static void serial_imx_save_context(struct imx_port *sport)
2145 {
2146         /* Save necessary regs */
2147         sport->saved_reg[0] = readl(sport->port.membase + UCR1);
2148         sport->saved_reg[1] = readl(sport->port.membase + UCR2);
2149         sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2150         sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2151         sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2152         sport->saved_reg[5] = readl(sport->port.membase + UESC);
2153         sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2154         sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2155         sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2156         sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2157         sport->context_saved = true;
2158 }
2159 
2160 static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2161 {
2162         unsigned int val;
2163 
2164         val = readl(sport->port.membase + UCR3);
2165         if (on)
2166                 val |= UCR3_AWAKEN;
2167         else
2168                 val &= ~UCR3_AWAKEN;
2169         writel(val, sport->port.membase + UCR3);
2170 
2171         val = readl(sport->port.membase + UCR1);
2172         if (on)
2173                 val |= UCR1_RTSDEN;
2174         else
2175                 val &= ~UCR1_RTSDEN;
2176         writel(val, sport->port.membase + UCR1);
2177 }
2178 
2179 static int imx_serial_port_suspend_noirq(struct device *dev)
2180 {
2181         struct platform_device *pdev = to_platform_device(dev);
2182         struct imx_port *sport = platform_get_drvdata(pdev);
2183         int ret;
2184 
2185         ret = clk_enable(sport->clk_ipg);
2186         if (ret)
2187                 return ret;
2188 
2189         serial_imx_save_context(sport);
2190 
2191         clk_disable(sport->clk_ipg);
2192 
2193         return 0;
2194 }
2195 
2196 static int imx_serial_port_resume_noirq(struct device *dev)
2197 {
2198         struct platform_device *pdev = to_platform_device(dev);
2199         struct imx_port *sport = platform_get_drvdata(pdev);
2200         int ret;
2201 
2202         ret = clk_enable(sport->clk_ipg);
2203         if (ret)
2204                 return ret;
2205 
2206         serial_imx_restore_context(sport);
2207 
2208         clk_disable(sport->clk_ipg);
2209 
2210         return 0;
2211 }
2212 
2213 static int imx_serial_port_suspend(struct device *dev)
2214 {
2215         struct platform_device *pdev = to_platform_device(dev);
2216         struct imx_port *sport = platform_get_drvdata(pdev);
2217 
2218         /* enable wakeup from i.MX UART */
2219         serial_imx_enable_wakeup(sport, true);
2220 
2221         uart_suspend_port(&imx_reg, &sport->port);
2222 
2223         /* Needed to enable clock in suspend_noirq */
2224         return clk_prepare(sport->clk_ipg);
2225 }
2226 
2227 static int imx_serial_port_resume(struct device *dev)
2228 {
2229         struct platform_device *pdev = to_platform_device(dev);
2230         struct imx_port *sport = platform_get_drvdata(pdev);
2231 
2232         /* disable wakeup from i.MX UART */
2233         serial_imx_enable_wakeup(sport, false);
2234 
2235         uart_resume_port(&imx_reg, &sport->port);
2236 
2237         clk_unprepare(sport->clk_ipg);
2238 
2239         return 0;
2240 }
2241 
2242 static const struct dev_pm_ops imx_serial_port_pm_ops = {
2243         .suspend_noirq = imx_serial_port_suspend_noirq,
2244         .resume_noirq = imx_serial_port_resume_noirq,
2245         .suspend = imx_serial_port_suspend,
2246         .resume = imx_serial_port_resume,
2247 };
2248 
2249 static struct platform_driver serial_imx_driver = {
2250         .probe          = serial_imx_probe,
2251         .remove         = serial_imx_remove,
2252 
2253         .id_table       = imx_uart_devtype,
2254         .driver         = {
2255                 .name   = "imx-uart",
2256                 .of_match_table = imx_uart_dt_ids,
2257                 .pm     = &imx_serial_port_pm_ops,
2258         },
2259 };
2260 
2261 static int __init imx_serial_init(void)
2262 {
2263         int ret = uart_register_driver(&imx_reg);
2264 
2265         if (ret)
2266                 return ret;
2267 
2268         ret = platform_driver_register(&serial_imx_driver);
2269         if (ret != 0)
2270                 uart_unregister_driver(&imx_reg);
2271 
2272         return ret;
2273 }
2274 
2275 static void __exit imx_serial_exit(void)
2276 {
2277         platform_driver_unregister(&serial_imx_driver);
2278         uart_unregister_driver(&imx_reg);
2279 }
2280 
2281 module_init(imx_serial_init);
2282 module_exit(imx_serial_exit);
2283 
2284 MODULE_AUTHOR("Sascha Hauer");
2285 MODULE_DESCRIPTION("IMX generic serial port driver");
2286 MODULE_LICENSE("GPL");
2287 MODULE_ALIAS("platform:imx-uart");
2288 

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