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Linux/drivers/tty/serial/8250/8250_pci.c

  1 /*
  2  *  Probe module for 8250/16550-type PCI serial ports.
  3  *
  4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  5  *
  6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License.
 11  */
 12 #undef DEBUG
 13 #include <linux/module.h>
 14 #include <linux/pci.h>
 15 #include <linux/string.h>
 16 #include <linux/kernel.h>
 17 #include <linux/slab.h>
 18 #include <linux/delay.h>
 19 #include <linux/tty.h>
 20 #include <linux/serial_reg.h>
 21 #include <linux/serial_core.h>
 22 #include <linux/8250_pci.h>
 23 #include <linux/bitops.h>
 24 #include <linux/rational.h>
 25 
 26 #include <asm/byteorder.h>
 27 #include <asm/io.h>
 28 
 29 #include <linux/dmaengine.h>
 30 #include <linux/platform_data/dma-dw.h>
 31 #include <linux/platform_data/dma-hsu.h>
 32 
 33 #include "8250.h"
 34 
 35 /*
 36  * init function returns:
 37  *  > 0 - number of ports
 38  *  = 0 - use board->num_ports
 39  *  < 0 - error
 40  */
 41 struct pci_serial_quirk {
 42         u32     vendor;
 43         u32     device;
 44         u32     subvendor;
 45         u32     subdevice;
 46         int     (*probe)(struct pci_dev *dev);
 47         int     (*init)(struct pci_dev *dev);
 48         int     (*setup)(struct serial_private *,
 49                          const struct pciserial_board *,
 50                          struct uart_8250_port *, int);
 51         void    (*exit)(struct pci_dev *dev);
 52 };
 53 
 54 #define PCI_NUM_BAR_RESOURCES   6
 55 
 56 struct serial_private {
 57         struct pci_dev          *dev;
 58         unsigned int            nr;
 59         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
 60         struct pci_serial_quirk *quirk;
 61         int                     line[0];
 62 };
 63 
 64 static int pci_default_setup(struct serial_private*,
 65           const struct pciserial_board*, struct uart_8250_port *, int);
 66 
 67 static void moan_device(const char *str, struct pci_dev *dev)
 68 {
 69         dev_err(&dev->dev,
 70                "%s: %s\n"
 71                "Please send the output of lspci -vv, this\n"
 72                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
 73                "manufacturer and name of serial board or\n"
 74                "modem board to <linux-serial@vger.kernel.org>.\n",
 75                pci_name(dev), str, dev->vendor, dev->device,
 76                dev->subsystem_vendor, dev->subsystem_device);
 77 }
 78 
 79 static int
 80 setup_port(struct serial_private *priv, struct uart_8250_port *port,
 81            int bar, int offset, int regshift)
 82 {
 83         struct pci_dev *dev = priv->dev;
 84 
 85         if (bar >= PCI_NUM_BAR_RESOURCES)
 86                 return -EINVAL;
 87 
 88         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
 89                 if (!priv->remapped_bar[bar])
 90                         priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
 91                 if (!priv->remapped_bar[bar])
 92                         return -ENOMEM;
 93 
 94                 port->port.iotype = UPIO_MEM;
 95                 port->port.iobase = 0;
 96                 port->port.mapbase = pci_resource_start(dev, bar) + offset;
 97                 port->port.membase = priv->remapped_bar[bar] + offset;
 98                 port->port.regshift = regshift;
 99         } else {
100                 port->port.iotype = UPIO_PORT;
101                 port->port.iobase = pci_resource_start(dev, bar) + offset;
102                 port->port.mapbase = 0;
103                 port->port.membase = NULL;
104                 port->port.regshift = 0;
105         }
106         return 0;
107 }
108 
109 /*
110  * ADDI-DATA GmbH communication cards <info@addi-data.com>
111  */
112 static int addidata_apci7800_setup(struct serial_private *priv,
113                                 const struct pciserial_board *board,
114                                 struct uart_8250_port *port, int idx)
115 {
116         unsigned int bar = 0, offset = board->first_offset;
117         bar = FL_GET_BASE(board->flags);
118 
119         if (idx < 2) {
120                 offset += idx * board->uart_offset;
121         } else if ((idx >= 2) && (idx < 4)) {
122                 bar += 1;
123                 offset += ((idx - 2) * board->uart_offset);
124         } else if ((idx >= 4) && (idx < 6)) {
125                 bar += 2;
126                 offset += ((idx - 4) * board->uart_offset);
127         } else if (idx >= 6) {
128                 bar += 3;
129                 offset += ((idx - 6) * board->uart_offset);
130         }
131 
132         return setup_port(priv, port, bar, offset, board->reg_shift);
133 }
134 
135 /*
136  * AFAVLAB uses a different mixture of BARs and offsets
137  * Not that ugly ;) -- HW
138  */
139 static int
140 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
141               struct uart_8250_port *port, int idx)
142 {
143         unsigned int bar, offset = board->first_offset;
144 
145         bar = FL_GET_BASE(board->flags);
146         if (idx < 4)
147                 bar += idx;
148         else {
149                 bar = 4;
150                 offset += (idx - 4) * board->uart_offset;
151         }
152 
153         return setup_port(priv, port, bar, offset, board->reg_shift);
154 }
155 
156 /*
157  * HP's Remote Management Console.  The Diva chip came in several
158  * different versions.  N-class, L2000 and A500 have two Diva chips, each
159  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
160  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
161  * one Diva chip, but it has been expanded to 5 UARTs.
162  */
163 static int pci_hp_diva_init(struct pci_dev *dev)
164 {
165         int rc = 0;
166 
167         switch (dev->subsystem_device) {
168         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
169         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
170         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
171         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
172                 rc = 3;
173                 break;
174         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
175                 rc = 2;
176                 break;
177         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
178                 rc = 4;
179                 break;
180         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
181         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
182                 rc = 1;
183                 break;
184         }
185 
186         return rc;
187 }
188 
189 /*
190  * HP's Diva chip puts the 4th/5th serial port further out, and
191  * some serial ports are supposed to be hidden on certain models.
192  */
193 static int
194 pci_hp_diva_setup(struct serial_private *priv,
195                 const struct pciserial_board *board,
196                 struct uart_8250_port *port, int idx)
197 {
198         unsigned int offset = board->first_offset;
199         unsigned int bar = FL_GET_BASE(board->flags);
200 
201         switch (priv->dev->subsystem_device) {
202         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
203                 if (idx == 3)
204                         idx++;
205                 break;
206         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
207                 if (idx > 0)
208                         idx++;
209                 if (idx > 2)
210                         idx++;
211                 break;
212         }
213         if (idx > 2)
214                 offset = 0x18;
215 
216         offset += idx * board->uart_offset;
217 
218         return setup_port(priv, port, bar, offset, board->reg_shift);
219 }
220 
221 /*
222  * Added for EKF Intel i960 serial boards
223  */
224 static int pci_inteli960ni_init(struct pci_dev *dev)
225 {
226         u32 oldval;
227 
228         if (!(dev->subsystem_device & 0x1000))
229                 return -ENODEV;
230 
231         /* is firmware started? */
232         pci_read_config_dword(dev, 0x44, &oldval);
233         if (oldval == 0x00001000L) { /* RESET value */
234                 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
235                 return -ENODEV;
236         }
237         return 0;
238 }
239 
240 /*
241  * Some PCI serial cards using the PLX 9050 PCI interface chip require
242  * that the card interrupt be explicitly enabled or disabled.  This
243  * seems to be mainly needed on card using the PLX which also use I/O
244  * mapped memory.
245  */
246 static int pci_plx9050_init(struct pci_dev *dev)
247 {
248         u8 irq_config;
249         void __iomem *p;
250 
251         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
252                 moan_device("no memory in bar 0", dev);
253                 return 0;
254         }
255 
256         irq_config = 0x41;
257         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
258             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
259                 irq_config = 0x43;
260 
261         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
262             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
263                 /*
264                  * As the megawolf cards have the int pins active
265                  * high, and have 2 UART chips, both ints must be
266                  * enabled on the 9050. Also, the UARTS are set in
267                  * 16450 mode by default, so we have to enable the
268                  * 16C950 'enhanced' mode so that we can use the
269                  * deep FIFOs
270                  */
271                 irq_config = 0x5b;
272         /*
273          * enable/disable interrupts
274          */
275         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
276         if (p == NULL)
277                 return -ENOMEM;
278         writel(irq_config, p + 0x4c);
279 
280         /*
281          * Read the register back to ensure that it took effect.
282          */
283         readl(p + 0x4c);
284         iounmap(p);
285 
286         return 0;
287 }
288 
289 static void pci_plx9050_exit(struct pci_dev *dev)
290 {
291         u8 __iomem *p;
292 
293         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
294                 return;
295 
296         /*
297          * disable interrupts
298          */
299         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
300         if (p != NULL) {
301                 writel(0, p + 0x4c);
302 
303                 /*
304                  * Read the register back to ensure that it took effect.
305                  */
306                 readl(p + 0x4c);
307                 iounmap(p);
308         }
309 }
310 
311 #define NI8420_INT_ENABLE_REG   0x38
312 #define NI8420_INT_ENABLE_BIT   0x2000
313 
314 static void pci_ni8420_exit(struct pci_dev *dev)
315 {
316         void __iomem *p;
317         unsigned int bar = 0;
318 
319         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
320                 moan_device("no memory in bar", dev);
321                 return;
322         }
323 
324         p = pci_ioremap_bar(dev, bar);
325         if (p == NULL)
326                 return;
327 
328         /* Disable the CPU Interrupt */
329         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
330                p + NI8420_INT_ENABLE_REG);
331         iounmap(p);
332 }
333 
334 
335 /* MITE registers */
336 #define MITE_IOWBSR1    0xc4
337 #define MITE_IOWCR1     0xf4
338 #define MITE_LCIMR1     0x08
339 #define MITE_LCIMR2     0x10
340 
341 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
342 
343 static void pci_ni8430_exit(struct pci_dev *dev)
344 {
345         void __iomem *p;
346         unsigned int bar = 0;
347 
348         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
349                 moan_device("no memory in bar", dev);
350                 return;
351         }
352 
353         p = pci_ioremap_bar(dev, bar);
354         if (p == NULL)
355                 return;
356 
357         /* Disable the CPU Interrupt */
358         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
359         iounmap(p);
360 }
361 
362 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
363 static int
364 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
365                 struct uart_8250_port *port, int idx)
366 {
367         unsigned int bar, offset = board->first_offset;
368 
369         bar = 0;
370 
371         if (idx < 4) {
372                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
373                 offset += idx * board->uart_offset;
374         } else if (idx < 8) {
375                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
376                 offset += idx * board->uart_offset + 0xC00;
377         } else /* we have only 8 ports on PMC-OCTALPRO */
378                 return 1;
379 
380         return setup_port(priv, port, bar, offset, board->reg_shift);
381 }
382 
383 /*
384 * This does initialization for PMC OCTALPRO cards:
385 * maps the device memory, resets the UARTs (needed, bc
386 * if the module is removed and inserted again, the card
387 * is in the sleep mode) and enables global interrupt.
388 */
389 
390 /* global control register offset for SBS PMC-OctalPro */
391 #define OCT_REG_CR_OFF          0x500
392 
393 static int sbs_init(struct pci_dev *dev)
394 {
395         u8 __iomem *p;
396 
397         p = pci_ioremap_bar(dev, 0);
398 
399         if (p == NULL)
400                 return -ENOMEM;
401         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
402         writeb(0x10, p + OCT_REG_CR_OFF);
403         udelay(50);
404         writeb(0x0, p + OCT_REG_CR_OFF);
405 
406         /* Set bit-2 (INTENABLE) of Control Register */
407         writeb(0x4, p + OCT_REG_CR_OFF);
408         iounmap(p);
409 
410         return 0;
411 }
412 
413 /*
414  * Disables the global interrupt of PMC-OctalPro
415  */
416 
417 static void sbs_exit(struct pci_dev *dev)
418 {
419         u8 __iomem *p;
420 
421         p = pci_ioremap_bar(dev, 0);
422         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
423         if (p != NULL)
424                 writeb(0, p + OCT_REG_CR_OFF);
425         iounmap(p);
426 }
427 
428 /*
429  * SIIG serial cards have an PCI interface chip which also controls
430  * the UART clocking frequency. Each UART can be clocked independently
431  * (except cards equipped with 4 UARTs) and initial clocking settings
432  * are stored in the EEPROM chip. It can cause problems because this
433  * version of serial driver doesn't support differently clocked UART's
434  * on single PCI card. To prevent this, initialization functions set
435  * high frequency clocking for all UART's on given card. It is safe (I
436  * hope) because it doesn't touch EEPROM settings to prevent conflicts
437  * with other OSes (like M$ DOS).
438  *
439  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
440  *
441  * There is two family of SIIG serial cards with different PCI
442  * interface chip and different configuration methods:
443  *     - 10x cards have control registers in IO and/or memory space;
444  *     - 20x cards have control registers in standard PCI configuration space.
445  *
446  * Note: all 10x cards have PCI device ids 0x10..
447  *       all 20x cards have PCI device ids 0x20..
448  *
449  * There are also Quartet Serial cards which use Oxford Semiconductor
450  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
451  *
452  * Note: some SIIG cards are probed by the parport_serial object.
453  */
454 
455 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
456 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
457 
458 static int pci_siig10x_init(struct pci_dev *dev)
459 {
460         u16 data;
461         void __iomem *p;
462 
463         switch (dev->device & 0xfff8) {
464         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
465                 data = 0xffdf;
466                 break;
467         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
468                 data = 0xf7ff;
469                 break;
470         default:                        /* 1S1P, 4S */
471                 data = 0xfffb;
472                 break;
473         }
474 
475         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
476         if (p == NULL)
477                 return -ENOMEM;
478 
479         writew(readw(p + 0x28) & data, p + 0x28);
480         readw(p + 0x28);
481         iounmap(p);
482         return 0;
483 }
484 
485 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
486 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
487 
488 static int pci_siig20x_init(struct pci_dev *dev)
489 {
490         u8 data;
491 
492         /* Change clock frequency for the first UART. */
493         pci_read_config_byte(dev, 0x6f, &data);
494         pci_write_config_byte(dev, 0x6f, data & 0xef);
495 
496         /* If this card has 2 UART, we have to do the same with second UART. */
497         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
498             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
499                 pci_read_config_byte(dev, 0x73, &data);
500                 pci_write_config_byte(dev, 0x73, data & 0xef);
501         }
502         return 0;
503 }
504 
505 static int pci_siig_init(struct pci_dev *dev)
506 {
507         unsigned int type = dev->device & 0xff00;
508 
509         if (type == 0x1000)
510                 return pci_siig10x_init(dev);
511         else if (type == 0x2000)
512                 return pci_siig20x_init(dev);
513 
514         moan_device("Unknown SIIG card", dev);
515         return -ENODEV;
516 }
517 
518 static int pci_siig_setup(struct serial_private *priv,
519                           const struct pciserial_board *board,
520                           struct uart_8250_port *port, int idx)
521 {
522         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
523 
524         if (idx > 3) {
525                 bar = 4;
526                 offset = (idx - 4) * 8;
527         }
528 
529         return setup_port(priv, port, bar, offset, 0);
530 }
531 
532 /*
533  * Timedia has an explosion of boards, and to avoid the PCI table from
534  * growing *huge*, we use this function to collapse some 70 entries
535  * in the PCI table into one, for sanity's and compactness's sake.
536  */
537 static const unsigned short timedia_single_port[] = {
538         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
539 };
540 
541 static const unsigned short timedia_dual_port[] = {
542         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
543         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
544         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
545         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
546         0xD079, 0
547 };
548 
549 static const unsigned short timedia_quad_port[] = {
550         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
551         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
552         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
553         0xB157, 0
554 };
555 
556 static const unsigned short timedia_eight_port[] = {
557         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
558         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
559 };
560 
561 static const struct timedia_struct {
562         int num;
563         const unsigned short *ids;
564 } timedia_data[] = {
565         { 1, timedia_single_port },
566         { 2, timedia_dual_port },
567         { 4, timedia_quad_port },
568         { 8, timedia_eight_port }
569 };
570 
571 /*
572  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
573  * listing them individually, this driver merely grabs them all with
574  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
575  * and should be left free to be claimed by parport_serial instead.
576  */
577 static int pci_timedia_probe(struct pci_dev *dev)
578 {
579         /*
580          * Check the third digit of the subdevice ID
581          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
582          */
583         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
584                 dev_info(&dev->dev,
585                         "ignoring Timedia subdevice %04x for parport_serial\n",
586                         dev->subsystem_device);
587                 return -ENODEV;
588         }
589 
590         return 0;
591 }
592 
593 static int pci_timedia_init(struct pci_dev *dev)
594 {
595         const unsigned short *ids;
596         int i, j;
597 
598         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
599                 ids = timedia_data[i].ids;
600                 for (j = 0; ids[j]; j++)
601                         if (dev->subsystem_device == ids[j])
602                                 return timedia_data[i].num;
603         }
604         return 0;
605 }
606 
607 /*
608  * Timedia/SUNIX uses a mixture of BARs and offsets
609  * Ugh, this is ugly as all hell --- TYT
610  */
611 static int
612 pci_timedia_setup(struct serial_private *priv,
613                   const struct pciserial_board *board,
614                   struct uart_8250_port *port, int idx)
615 {
616         unsigned int bar = 0, offset = board->first_offset;
617 
618         switch (idx) {
619         case 0:
620                 bar = 0;
621                 break;
622         case 1:
623                 offset = board->uart_offset;
624                 bar = 0;
625                 break;
626         case 2:
627                 bar = 1;
628                 break;
629         case 3:
630                 offset = board->uart_offset;
631                 /* FALLTHROUGH */
632         case 4: /* BAR 2 */
633         case 5: /* BAR 3 */
634         case 6: /* BAR 4 */
635         case 7: /* BAR 5 */
636                 bar = idx - 2;
637         }
638 
639         return setup_port(priv, port, bar, offset, board->reg_shift);
640 }
641 
642 /*
643  * Some Titan cards are also a little weird
644  */
645 static int
646 titan_400l_800l_setup(struct serial_private *priv,
647                       const struct pciserial_board *board,
648                       struct uart_8250_port *port, int idx)
649 {
650         unsigned int bar, offset = board->first_offset;
651 
652         switch (idx) {
653         case 0:
654                 bar = 1;
655                 break;
656         case 1:
657                 bar = 2;
658                 break;
659         default:
660                 bar = 4;
661                 offset = (idx - 2) * board->uart_offset;
662         }
663 
664         return setup_port(priv, port, bar, offset, board->reg_shift);
665 }
666 
667 static int pci_xircom_init(struct pci_dev *dev)
668 {
669         msleep(100);
670         return 0;
671 }
672 
673 static int pci_ni8420_init(struct pci_dev *dev)
674 {
675         void __iomem *p;
676         unsigned int bar = 0;
677 
678         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
679                 moan_device("no memory in bar", dev);
680                 return 0;
681         }
682 
683         p = pci_ioremap_bar(dev, bar);
684         if (p == NULL)
685                 return -ENOMEM;
686 
687         /* Enable CPU Interrupt */
688         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
689                p + NI8420_INT_ENABLE_REG);
690 
691         iounmap(p);
692         return 0;
693 }
694 
695 #define MITE_IOWBSR1_WSIZE      0xa
696 #define MITE_IOWBSR1_WIN_OFFSET 0x800
697 #define MITE_IOWBSR1_WENAB      (1 << 7)
698 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
699 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
700 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
701 
702 static int pci_ni8430_init(struct pci_dev *dev)
703 {
704         void __iomem *p;
705         struct pci_bus_region region;
706         u32 device_window;
707         unsigned int bar = 0;
708 
709         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
710                 moan_device("no memory in bar", dev);
711                 return 0;
712         }
713 
714         p = pci_ioremap_bar(dev, bar);
715         if (p == NULL)
716                 return -ENOMEM;
717 
718         /*
719          * Set device window address and size in BAR0, while acknowledging that
720          * the resource structure may contain a translated address that differs
721          * from the address the device responds to.
722          */
723         pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
724         device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
725                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
726         writel(device_window, p + MITE_IOWBSR1);
727 
728         /* Set window access to go to RAMSEL IO address space */
729         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
730                p + MITE_IOWCR1);
731 
732         /* Enable IO Bus Interrupt 0 */
733         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
734 
735         /* Enable CPU Interrupt */
736         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
737 
738         iounmap(p);
739         return 0;
740 }
741 
742 /* UART Port Control Register */
743 #define NI8430_PORTCON  0x0f
744 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
745 
746 static int
747 pci_ni8430_setup(struct serial_private *priv,
748                  const struct pciserial_board *board,
749                  struct uart_8250_port *port, int idx)
750 {
751         struct pci_dev *dev = priv->dev;
752         void __iomem *p;
753         unsigned int bar, offset = board->first_offset;
754 
755         if (idx >= board->num_ports)
756                 return 1;
757 
758         bar = FL_GET_BASE(board->flags);
759         offset += idx * board->uart_offset;
760 
761         p = pci_ioremap_bar(dev, bar);
762         if (!p)
763                 return -ENOMEM;
764 
765         /* enable the transceiver */
766         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
767                p + offset + NI8430_PORTCON);
768 
769         iounmap(p);
770 
771         return setup_port(priv, port, bar, offset, board->reg_shift);
772 }
773 
774 static int pci_netmos_9900_setup(struct serial_private *priv,
775                                 const struct pciserial_board *board,
776                                 struct uart_8250_port *port, int idx)
777 {
778         unsigned int bar;
779 
780         if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
781             (priv->dev->subsystem_device & 0xff00) == 0x3000) {
782                 /* netmos apparently orders BARs by datasheet layout, so serial
783                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
784                  */
785                 bar = 3 * idx;
786 
787                 return setup_port(priv, port, bar, 0, board->reg_shift);
788         } else {
789                 return pci_default_setup(priv, board, port, idx);
790         }
791 }
792 
793 /* the 99xx series comes with a range of device IDs and a variety
794  * of capabilities:
795  *
796  * 9900 has varying capabilities and can cascade to sub-controllers
797  *   (cascading should be purely internal)
798  * 9904 is hardwired with 4 serial ports
799  * 9912 and 9922 are hardwired with 2 serial ports
800  */
801 static int pci_netmos_9900_numports(struct pci_dev *dev)
802 {
803         unsigned int c = dev->class;
804         unsigned int pi;
805         unsigned short sub_serports;
806 
807         pi = (c & 0xff);
808 
809         if (pi == 2) {
810                 return 1;
811         } else if ((pi == 0) &&
812                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
813                 /* two possibilities: 0x30ps encodes number of parallel and
814                  * serial ports, or 0x1000 indicates *something*. This is not
815                  * immediately obvious, since the 2s1p+4s configuration seems
816                  * to offer all functionality on functions 0..2, while still
817                  * advertising the same function 3 as the 4s+2s1p config.
818                  */
819                 sub_serports = dev->subsystem_device & 0xf;
820                 if (sub_serports > 0) {
821                         return sub_serports;
822                 } else {
823                         dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
824                         return 0;
825                 }
826         }
827 
828         moan_device("unknown NetMos/Mostech program interface", dev);
829         return 0;
830 }
831 
832 static int pci_netmos_init(struct pci_dev *dev)
833 {
834         /* subdevice 0x00PS means <P> parallel, <S> serial */
835         unsigned int num_serial = dev->subsystem_device & 0xf;
836 
837         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
838                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
839                 return 0;
840 
841         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
842                         dev->subsystem_device == 0x0299)
843                 return 0;
844 
845         switch (dev->device) { /* FALLTHROUGH on all */
846                 case PCI_DEVICE_ID_NETMOS_9904:
847                 case PCI_DEVICE_ID_NETMOS_9912:
848                 case PCI_DEVICE_ID_NETMOS_9922:
849                 case PCI_DEVICE_ID_NETMOS_9900:
850                         num_serial = pci_netmos_9900_numports(dev);
851                         break;
852 
853                 default:
854                         if (num_serial == 0 ) {
855                                 moan_device("unknown NetMos/Mostech device", dev);
856                         }
857         }
858 
859         if (num_serial == 0)
860                 return -ENODEV;
861 
862         return num_serial;
863 }
864 
865 /*
866  * These chips are available with optionally one parallel port and up to
867  * two serial ports. Unfortunately they all have the same product id.
868  *
869  * Basic configuration is done over a region of 32 I/O ports. The base
870  * ioport is called INTA or INTC, depending on docs/other drivers.
871  *
872  * The region of the 32 I/O ports is configured in POSIO0R...
873  */
874 
875 /* registers */
876 #define ITE_887x_MISCR          0x9c
877 #define ITE_887x_INTCBAR        0x78
878 #define ITE_887x_UARTBAR        0x7c
879 #define ITE_887x_PS0BAR         0x10
880 #define ITE_887x_POSIO0         0x60
881 
882 /* I/O space size */
883 #define ITE_887x_IOSIZE         32
884 /* I/O space size (bits 26-24; 8 bytes = 011b) */
885 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
886 /* I/O space size (bits 26-24; 32 bytes = 101b) */
887 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
888 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
889 #define ITE_887x_POSIO_SPEED            (3 << 29)
890 /* enable IO_Space bit */
891 #define ITE_887x_POSIO_ENABLE           (1 << 31)
892 
893 static int pci_ite887x_init(struct pci_dev *dev)
894 {
895         /* inta_addr are the configuration addresses of the ITE */
896         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
897                                                         0x200, 0x280, 0 };
898         int ret, i, type;
899         struct resource *iobase = NULL;
900         u32 miscr, uartbar, ioport;
901 
902         /* search for the base-ioport */
903         i = 0;
904         while (inta_addr[i] && iobase == NULL) {
905                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
906                                                                 "ite887x");
907                 if (iobase != NULL) {
908                         /* write POSIO0R - speed | size | ioport */
909                         pci_write_config_dword(dev, ITE_887x_POSIO0,
910                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
911                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
912                         /* write INTCBAR - ioport */
913                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
914                                                                 inta_addr[i]);
915                         ret = inb(inta_addr[i]);
916                         if (ret != 0xff) {
917                                 /* ioport connected */
918                                 break;
919                         }
920                         release_region(iobase->start, ITE_887x_IOSIZE);
921                         iobase = NULL;
922                 }
923                 i++;
924         }
925 
926         if (!inta_addr[i]) {
927                 dev_err(&dev->dev, "ite887x: could not find iobase\n");
928                 return -ENODEV;
929         }
930 
931         /* start of undocumented type checking (see parport_pc.c) */
932         type = inb(iobase->start + 0x18) & 0x0f;
933 
934         switch (type) {
935         case 0x2:       /* ITE8871 (1P) */
936         case 0xa:       /* ITE8875 (1P) */
937                 ret = 0;
938                 break;
939         case 0xe:       /* ITE8872 (2S1P) */
940                 ret = 2;
941                 break;
942         case 0x6:       /* ITE8873 (1S) */
943                 ret = 1;
944                 break;
945         case 0x8:       /* ITE8874 (2S) */
946                 ret = 2;
947                 break;
948         default:
949                 moan_device("Unknown ITE887x", dev);
950                 ret = -ENODEV;
951         }
952 
953         /* configure all serial ports */
954         for (i = 0; i < ret; i++) {
955                 /* read the I/O port from the device */
956                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
957                                                                 &ioport);
958                 ioport &= 0x0000FF00;   /* the actual base address */
959                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
960                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
961                         ITE_887x_POSIO_IOSIZE_8 | ioport);
962 
963                 /* write the ioport to the UARTBAR */
964                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
965                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
966                 uartbar |= (ioport << (16 * i));        /* set the ioport */
967                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
968 
969                 /* get current config */
970                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
971                 /* disable interrupts (UARTx_Routing[3:0]) */
972                 miscr &= ~(0xf << (12 - 4 * i));
973                 /* activate the UART (UARTx_En) */
974                 miscr |= 1 << (23 - i);
975                 /* write new config with activated UART */
976                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
977         }
978 
979         if (ret <= 0) {
980                 /* the device has no UARTs if we get here */
981                 release_region(iobase->start, ITE_887x_IOSIZE);
982         }
983 
984         return ret;
985 }
986 
987 static void pci_ite887x_exit(struct pci_dev *dev)
988 {
989         u32 ioport;
990         /* the ioport is bit 0-15 in POSIO0R */
991         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
992         ioport &= 0xffff;
993         release_region(ioport, ITE_887x_IOSIZE);
994 }
995 
996 /*
997  * EndRun Technologies.
998  * Determine the number of ports available on the device.
999  */
1000 #define PCI_VENDOR_ID_ENDRUN                    0x7401
1001 #define PCI_DEVICE_ID_ENDRUN_1588       0xe100
1002 
1003 static int pci_endrun_init(struct pci_dev *dev)
1004 {
1005         u8 __iomem *p;
1006         unsigned long deviceID;
1007         unsigned int  number_uarts = 0;
1008 
1009         /* EndRun device is all 0xexxx */
1010         if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1011                 (dev->device & 0xf000) != 0xe000)
1012                 return 0;
1013 
1014         p = pci_iomap(dev, 0, 5);
1015         if (p == NULL)
1016                 return -ENOMEM;
1017 
1018         deviceID = ioread32(p);
1019         /* EndRun device */
1020         if (deviceID == 0x07000200) {
1021                 number_uarts = ioread8(p + 4);
1022                 dev_dbg(&dev->dev,
1023                         "%d ports detected on EndRun PCI Express device\n",
1024                         number_uarts);
1025         }
1026         pci_iounmap(dev, p);
1027         return number_uarts;
1028 }
1029 
1030 /*
1031  * Oxford Semiconductor Inc.
1032  * Check that device is part of the Tornado range of devices, then determine
1033  * the number of ports available on the device.
1034  */
1035 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1036 {
1037         u8 __iomem *p;
1038         unsigned long deviceID;
1039         unsigned int  number_uarts = 0;
1040 
1041         /* OxSemi Tornado devices are all 0xCxxx */
1042         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1043             (dev->device & 0xF000) != 0xC000)
1044                 return 0;
1045 
1046         p = pci_iomap(dev, 0, 5);
1047         if (p == NULL)
1048                 return -ENOMEM;
1049 
1050         deviceID = ioread32(p);
1051         /* Tornado device */
1052         if (deviceID == 0x07000200) {
1053                 number_uarts = ioread8(p + 4);
1054                 dev_dbg(&dev->dev,
1055                         "%d ports detected on Oxford PCI Express device\n",
1056                         number_uarts);
1057         }
1058         pci_iounmap(dev, p);
1059         return number_uarts;
1060 }
1061 
1062 static int pci_asix_setup(struct serial_private *priv,
1063                   const struct pciserial_board *board,
1064                   struct uart_8250_port *port, int idx)
1065 {
1066         port->bugs |= UART_BUG_PARITY;
1067         return pci_default_setup(priv, board, port, idx);
1068 }
1069 
1070 /* Quatech devices have their own extra interface features */
1071 
1072 struct quatech_feature {
1073         u16 devid;
1074         bool amcc;
1075 };
1076 
1077 #define QPCR_TEST_FOR1          0x3F
1078 #define QPCR_TEST_GET1          0x00
1079 #define QPCR_TEST_FOR2          0x40
1080 #define QPCR_TEST_GET2          0x40
1081 #define QPCR_TEST_FOR3          0x80
1082 #define QPCR_TEST_GET3          0x40
1083 #define QPCR_TEST_FOR4          0xC0
1084 #define QPCR_TEST_GET4          0x80
1085 
1086 #define QOPR_CLOCK_X1           0x0000
1087 #define QOPR_CLOCK_X2           0x0001
1088 #define QOPR_CLOCK_X4           0x0002
1089 #define QOPR_CLOCK_X8           0x0003
1090 #define QOPR_CLOCK_RATE_MASK    0x0003
1091 
1092 
1093 static struct quatech_feature quatech_cards[] = {
1094         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1095         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1096         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1097         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1098         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1099         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1100         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1101         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1102         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1103         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1104         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1105         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1106         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1107         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1108         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1109         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1110         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1111         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1112         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1113         { 0, }
1114 };
1115 
1116 static int pci_quatech_amcc(u16 devid)
1117 {
1118         struct quatech_feature *qf = &quatech_cards[0];
1119         while (qf->devid) {
1120                 if (qf->devid == devid)
1121                         return qf->amcc;
1122                 qf++;
1123         }
1124         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1125         return 0;
1126 };
1127 
1128 static int pci_quatech_rqopr(struct uart_8250_port *port)
1129 {
1130         unsigned long base = port->port.iobase;
1131         u8 LCR, val;
1132 
1133         LCR = inb(base + UART_LCR);
1134         outb(0xBF, base + UART_LCR);
1135         val = inb(base + UART_SCR);
1136         outb(LCR, base + UART_LCR);
1137         return val;
1138 }
1139 
1140 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1141 {
1142         unsigned long base = port->port.iobase;
1143         u8 LCR, val;
1144 
1145         LCR = inb(base + UART_LCR);
1146         outb(0xBF, base + UART_LCR);
1147         val = inb(base + UART_SCR);
1148         outb(qopr, base + UART_SCR);
1149         outb(LCR, base + UART_LCR);
1150 }
1151 
1152 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1153 {
1154         unsigned long base = port->port.iobase;
1155         u8 LCR, val, qmcr;
1156 
1157         LCR = inb(base + UART_LCR);
1158         outb(0xBF, base + UART_LCR);
1159         val = inb(base + UART_SCR);
1160         outb(val | 0x10, base + UART_SCR);
1161         qmcr = inb(base + UART_MCR);
1162         outb(val, base + UART_SCR);
1163         outb(LCR, base + UART_LCR);
1164 
1165         return qmcr;
1166 }
1167 
1168 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1169 {
1170         unsigned long base = port->port.iobase;
1171         u8 LCR, val;
1172 
1173         LCR = inb(base + UART_LCR);
1174         outb(0xBF, base + UART_LCR);
1175         val = inb(base + UART_SCR);
1176         outb(val | 0x10, base + UART_SCR);
1177         outb(qmcr, base + UART_MCR);
1178         outb(val, base + UART_SCR);
1179         outb(LCR, base + UART_LCR);
1180 }
1181 
1182 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1183 {
1184         unsigned long base = port->port.iobase;
1185         u8 LCR, val;
1186 
1187         LCR = inb(base + UART_LCR);
1188         outb(0xBF, base + UART_LCR);
1189         val = inb(base + UART_SCR);
1190         if (val & 0x20) {
1191                 outb(0x80, UART_LCR);
1192                 if (!(inb(UART_SCR) & 0x20)) {
1193                         outb(LCR, base + UART_LCR);
1194                         return 1;
1195                 }
1196         }
1197         return 0;
1198 }
1199 
1200 static int pci_quatech_test(struct uart_8250_port *port)
1201 {
1202         u8 reg;
1203         u8 qopr = pci_quatech_rqopr(port);
1204         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1205         reg = pci_quatech_rqopr(port) & 0xC0;
1206         if (reg != QPCR_TEST_GET1)
1207                 return -EINVAL;
1208         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1209         reg = pci_quatech_rqopr(port) & 0xC0;
1210         if (reg != QPCR_TEST_GET2)
1211                 return -EINVAL;
1212         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1213         reg = pci_quatech_rqopr(port) & 0xC0;
1214         if (reg != QPCR_TEST_GET3)
1215                 return -EINVAL;
1216         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1217         reg = pci_quatech_rqopr(port) & 0xC0;
1218         if (reg != QPCR_TEST_GET4)
1219                 return -EINVAL;
1220 
1221         pci_quatech_wqopr(port, qopr);
1222         return 0;
1223 }
1224 
1225 static int pci_quatech_clock(struct uart_8250_port *port)
1226 {
1227         u8 qopr, reg, set;
1228         unsigned long clock;
1229 
1230         if (pci_quatech_test(port) < 0)
1231                 return 1843200;
1232 
1233         qopr = pci_quatech_rqopr(port);
1234 
1235         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1236         reg = pci_quatech_rqopr(port);
1237         if (reg & QOPR_CLOCK_X8) {
1238                 clock = 1843200;
1239                 goto out;
1240         }
1241         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1242         reg = pci_quatech_rqopr(port);
1243         if (!(reg & QOPR_CLOCK_X8)) {
1244                 clock = 1843200;
1245                 goto out;
1246         }
1247         reg &= QOPR_CLOCK_X8;
1248         if (reg == QOPR_CLOCK_X2) {
1249                 clock =  3685400;
1250                 set = QOPR_CLOCK_X2;
1251         } else if (reg == QOPR_CLOCK_X4) {
1252                 clock = 7372800;
1253                 set = QOPR_CLOCK_X4;
1254         } else if (reg == QOPR_CLOCK_X8) {
1255                 clock = 14745600;
1256                 set = QOPR_CLOCK_X8;
1257         } else {
1258                 clock = 1843200;
1259                 set = QOPR_CLOCK_X1;
1260         }
1261         qopr &= ~QOPR_CLOCK_RATE_MASK;
1262         qopr |= set;
1263 
1264 out:
1265         pci_quatech_wqopr(port, qopr);
1266         return clock;
1267 }
1268 
1269 static int pci_quatech_rs422(struct uart_8250_port *port)
1270 {
1271         u8 qmcr;
1272         int rs422 = 0;
1273 
1274         if (!pci_quatech_has_qmcr(port))
1275                 return 0;
1276         qmcr = pci_quatech_rqmcr(port);
1277         pci_quatech_wqmcr(port, 0xFF);
1278         if (pci_quatech_rqmcr(port))
1279                 rs422 = 1;
1280         pci_quatech_wqmcr(port, qmcr);
1281         return rs422;
1282 }
1283 
1284 static int pci_quatech_init(struct pci_dev *dev)
1285 {
1286         if (pci_quatech_amcc(dev->device)) {
1287                 unsigned long base = pci_resource_start(dev, 0);
1288                 if (base) {
1289                         u32 tmp;
1290                         outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1291                         tmp = inl(base + 0x3c);
1292                         outl(tmp | 0x01000000, base + 0x3c);
1293                         outl(tmp &= ~0x01000000, base + 0x3c);
1294                 }
1295         }
1296         return 0;
1297 }
1298 
1299 static int pci_quatech_setup(struct serial_private *priv,
1300                   const struct pciserial_board *board,
1301                   struct uart_8250_port *port, int idx)
1302 {
1303         /* Needed by pci_quatech calls below */
1304         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1305         /* Set up the clocking */
1306         port->port.uartclk = pci_quatech_clock(port);
1307         /* For now just warn about RS422 */
1308         if (pci_quatech_rs422(port))
1309                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1310         return pci_default_setup(priv, board, port, idx);
1311 }
1312 
1313 static void pci_quatech_exit(struct pci_dev *dev)
1314 {
1315 }
1316 
1317 static int pci_default_setup(struct serial_private *priv,
1318                   const struct pciserial_board *board,
1319                   struct uart_8250_port *port, int idx)
1320 {
1321         unsigned int bar, offset = board->first_offset, maxnr;
1322 
1323         bar = FL_GET_BASE(board->flags);
1324         if (board->flags & FL_BASE_BARS)
1325                 bar += idx;
1326         else
1327                 offset += idx * board->uart_offset;
1328 
1329         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1330                 (board->reg_shift + 3);
1331 
1332         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1333                 return 1;
1334 
1335         return setup_port(priv, port, bar, offset, board->reg_shift);
1336 }
1337 
1338 static int pci_pericom_setup(struct serial_private *priv,
1339                   const struct pciserial_board *board,
1340                   struct uart_8250_port *port, int idx)
1341 {
1342         unsigned int bar, offset = board->first_offset, maxnr;
1343 
1344         bar = FL_GET_BASE(board->flags);
1345         if (board->flags & FL_BASE_BARS)
1346                 bar += idx;
1347         else
1348                 offset += idx * board->uart_offset;
1349 
1350         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1351                 (board->reg_shift + 3);
1352 
1353         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1354                 return 1;
1355 
1356         port->port.uartclk = 14745600;
1357 
1358         return setup_port(priv, port, bar, offset, board->reg_shift);
1359 }
1360 
1361 static int
1362 ce4100_serial_setup(struct serial_private *priv,
1363                   const struct pciserial_board *board,
1364                   struct uart_8250_port *port, int idx)
1365 {
1366         int ret;
1367 
1368         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1369         port->port.iotype = UPIO_MEM32;
1370         port->port.type = PORT_XSCALE;
1371         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1372         port->port.regshift = 2;
1373 
1374         return ret;
1375 }
1376 
1377 #define PCI_DEVICE_ID_INTEL_BYT_UART1   0x0f0a
1378 #define PCI_DEVICE_ID_INTEL_BYT_UART2   0x0f0c
1379 
1380 #define PCI_DEVICE_ID_INTEL_BSW_UART1   0x228a
1381 #define PCI_DEVICE_ID_INTEL_BSW_UART2   0x228c
1382 
1383 #define BYT_PRV_CLK                     0x800
1384 #define BYT_PRV_CLK_EN                  (1 << 0)
1385 #define BYT_PRV_CLK_M_VAL_SHIFT         1
1386 #define BYT_PRV_CLK_N_VAL_SHIFT         16
1387 #define BYT_PRV_CLK_UPDATE              (1 << 31)
1388 
1389 #define BYT_TX_OVF_INT                  0x820
1390 #define BYT_TX_OVF_INT_MASK             (1 << 1)
1391 
1392 static void
1393 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1394                 struct ktermios *old)
1395 {
1396         unsigned int baud = tty_termios_baud_rate(termios);
1397         unsigned long fref = 100000000, fuart = baud * 16;
1398         unsigned long w = BIT(15) - 1;
1399         unsigned long m, n;
1400         u32 reg;
1401 
1402         /* Get Fuart closer to Fref */
1403         fuart *= rounddown_pow_of_two(fref / fuart);
1404 
1405         /*
1406          * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1407          * dividers must be adjusted.
1408          *
1409          * uartclk = (m / n) * 100 MHz, where m <= n
1410          */
1411         rational_best_approximation(fuart, fref, w, w, &m, &n);
1412         p->uartclk = fuart;
1413 
1414         /* Reset the clock */
1415         reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1416         writel(reg, p->membase + BYT_PRV_CLK);
1417         reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1418         writel(reg, p->membase + BYT_PRV_CLK);
1419 
1420         serial8250_do_set_termios(p, termios, old);
1421 }
1422 
1423 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1424 {
1425         struct dw_dma_slave *dws = param;
1426 
1427         if (dws->dma_dev != chan->device->dev)
1428                 return false;
1429 
1430         chan->private = dws;
1431         return true;
1432 }
1433 
1434 static int
1435 byt_serial_setup(struct serial_private *priv,
1436                  const struct pciserial_board *board,
1437                  struct uart_8250_port *port, int idx)
1438 {
1439         struct pci_dev *pdev = priv->dev;
1440         struct device *dev = port->port.dev;
1441         struct uart_8250_dma *dma;
1442         struct dw_dma_slave *tx_param, *rx_param;
1443         struct pci_dev *dma_dev;
1444         int ret;
1445 
1446         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1447         if (!dma)
1448                 return -ENOMEM;
1449 
1450         tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1451         if (!tx_param)
1452                 return -ENOMEM;
1453 
1454         rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1455         if (!rx_param)
1456                 return -ENOMEM;
1457 
1458         switch (pdev->device) {
1459         case PCI_DEVICE_ID_INTEL_BYT_UART1:
1460         case PCI_DEVICE_ID_INTEL_BSW_UART1:
1461                 rx_param->src_id = 3;
1462                 tx_param->dst_id = 2;
1463                 break;
1464         case PCI_DEVICE_ID_INTEL_BYT_UART2:
1465         case PCI_DEVICE_ID_INTEL_BSW_UART2:
1466                 rx_param->src_id = 5;
1467                 tx_param->dst_id = 4;
1468                 break;
1469         default:
1470                 return -EINVAL;
1471         }
1472 
1473         rx_param->src_master = 1;
1474         rx_param->dst_master = 0;
1475 
1476         dma->rxconf.src_maxburst = 16;
1477 
1478         tx_param->src_master = 1;
1479         tx_param->dst_master = 0;
1480 
1481         dma->txconf.dst_maxburst = 16;
1482 
1483         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1484         rx_param->dma_dev = &dma_dev->dev;
1485         tx_param->dma_dev = &dma_dev->dev;
1486 
1487         dma->fn = byt_dma_filter;
1488         dma->rx_param = rx_param;
1489         dma->tx_param = tx_param;
1490 
1491         ret = pci_default_setup(priv, board, port, idx);
1492         port->port.iotype = UPIO_MEM;
1493         port->port.type = PORT_16550A;
1494         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1495         port->port.set_termios = byt_set_termios;
1496         port->port.fifosize = 64;
1497         port->tx_loadsz = 64;
1498         port->dma = dma;
1499         port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1500 
1501         /* Disable Tx counter interrupts */
1502         writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1503 
1504         return ret;
1505 }
1506 
1507 #define INTEL_MID_UART_PS               0x30
1508 #define INTEL_MID_UART_MUL              0x34
1509 #define INTEL_MID_UART_DIV              0x38
1510 
1511 static void intel_mid_set_termios(struct uart_port *p,
1512                                   struct ktermios *termios,
1513                                   struct ktermios *old,
1514                                   unsigned long fref)
1515 {
1516         unsigned int baud = tty_termios_baud_rate(termios);
1517         unsigned short ps = 16;
1518         unsigned long fuart = baud * ps;
1519         unsigned long w = BIT(24) - 1;
1520         unsigned long mul, div;
1521 
1522         if (fref < fuart) {
1523                 /* Find prescaler value that satisfies Fuart < Fref */
1524                 if (fref > baud)
1525                         ps = fref / baud;       /* baud rate too high */
1526                 else
1527                         ps = 1;                 /* PLL case */
1528                 fuart = baud * ps;
1529         } else {
1530                 /* Get Fuart closer to Fref */
1531                 fuart *= rounddown_pow_of_two(fref / fuart);
1532         }
1533 
1534         rational_best_approximation(fuart, fref, w, w, &mul, &div);
1535         p->uartclk = fuart * 16 / ps;           /* core uses ps = 16 always */
1536 
1537         writel(ps, p->membase + INTEL_MID_UART_PS);             /* set PS */
1538         writel(mul, p->membase + INTEL_MID_UART_MUL);           /* set MUL */
1539         writel(div, p->membase + INTEL_MID_UART_DIV);
1540 
1541         serial8250_do_set_termios(p, termios, old);
1542 }
1543 
1544 static void intel_mid_set_termios_38_4M(struct uart_port *p,
1545                                         struct ktermios *termios,
1546                                         struct ktermios *old)
1547 {
1548         intel_mid_set_termios(p, termios, old, 38400000);
1549 }
1550 
1551 static void intel_mid_set_termios_50M(struct uart_port *p,
1552                                       struct ktermios *termios,
1553                                       struct ktermios *old)
1554 {
1555         /*
1556          * The uart clk is 50Mhz, and the baud rate come from:
1557          *      baud = 50M * MUL / (DIV * PS * DLAB)
1558          */
1559         intel_mid_set_termios(p, termios, old, 50000000);
1560 }
1561 
1562 static bool intel_mid_dma_filter(struct dma_chan *chan, void *param)
1563 {
1564         struct hsu_dma_slave *s = param;
1565 
1566         if (s->dma_dev != chan->device->dev || s->chan_id != chan->chan_id)
1567                 return false;
1568 
1569         chan->private = s;
1570         return true;
1571 }
1572 
1573 static int intel_mid_serial_setup(struct serial_private *priv,
1574                                   const struct pciserial_board *board,
1575                                   struct uart_8250_port *port, int idx,
1576                                   int index, struct pci_dev *dma_dev)
1577 {
1578         struct device *dev = port->port.dev;
1579         struct uart_8250_dma *dma;
1580         struct hsu_dma_slave *tx_param, *rx_param;
1581 
1582         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1583         if (!dma)
1584                 return -ENOMEM;
1585 
1586         tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1587         if (!tx_param)
1588                 return -ENOMEM;
1589 
1590         rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1591         if (!rx_param)
1592                 return -ENOMEM;
1593 
1594         rx_param->chan_id = index * 2 + 1;
1595         tx_param->chan_id = index * 2;
1596 
1597         dma->rxconf.src_maxburst = 64;
1598         dma->txconf.dst_maxburst = 64;
1599 
1600         rx_param->dma_dev = &dma_dev->dev;
1601         tx_param->dma_dev = &dma_dev->dev;
1602 
1603         dma->fn = intel_mid_dma_filter;
1604         dma->rx_param = rx_param;
1605         dma->tx_param = tx_param;
1606 
1607         port->port.type = PORT_16750;
1608         port->port.flags |= UPF_FIXED_PORT | UPF_FIXED_TYPE;
1609         port->dma = dma;
1610 
1611         return pci_default_setup(priv, board, port, idx);
1612 }
1613 
1614 #define PCI_DEVICE_ID_INTEL_PNW_UART1   0x081b
1615 #define PCI_DEVICE_ID_INTEL_PNW_UART2   0x081c
1616 #define PCI_DEVICE_ID_INTEL_PNW_UART3   0x081d
1617 
1618 static int pnw_serial_setup(struct serial_private *priv,
1619                             const struct pciserial_board *board,
1620                             struct uart_8250_port *port, int idx)
1621 {
1622         struct pci_dev *pdev = priv->dev;
1623         struct pci_dev *dma_dev;
1624         int index;
1625 
1626         switch (pdev->device) {
1627         case PCI_DEVICE_ID_INTEL_PNW_UART1:
1628                 index = 0;
1629                 break;
1630         case PCI_DEVICE_ID_INTEL_PNW_UART2:
1631                 index = 1;
1632                 break;
1633         case PCI_DEVICE_ID_INTEL_PNW_UART3:
1634                 index = 2;
1635                 break;
1636         default:
1637                 return -EINVAL;
1638         }
1639 
1640         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 3));
1641 
1642         port->port.set_termios = intel_mid_set_termios_50M;
1643 
1644         return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
1645 }
1646 
1647 #define PCI_DEVICE_ID_INTEL_TNG_UART    0x1191
1648 
1649 static int tng_serial_setup(struct serial_private *priv,
1650                             const struct pciserial_board *board,
1651                             struct uart_8250_port *port, int idx)
1652 {
1653         struct pci_dev *pdev = priv->dev;
1654         struct pci_dev *dma_dev;
1655         int index = PCI_FUNC(pdev->devfn);
1656 
1657         /* Currently no support for HSU port0 */
1658         if (index-- == 0)
1659                 return -ENODEV;
1660 
1661         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0));
1662 
1663         port->port.set_termios = intel_mid_set_termios_38_4M;
1664 
1665         return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
1666 }
1667 
1668 static int
1669 pci_omegapci_setup(struct serial_private *priv,
1670                       const struct pciserial_board *board,
1671                       struct uart_8250_port *port, int idx)
1672 {
1673         return setup_port(priv, port, 2, idx * 8, 0);
1674 }
1675 
1676 static int
1677 pci_brcm_trumanage_setup(struct serial_private *priv,
1678                          const struct pciserial_board *board,
1679                          struct uart_8250_port *port, int idx)
1680 {
1681         int ret = pci_default_setup(priv, board, port, idx);
1682 
1683         port->port.type = PORT_BRCM_TRUMANAGE;
1684         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1685         return ret;
1686 }
1687 
1688 static int pci_fintek_setup(struct serial_private *priv,
1689                             const struct pciserial_board *board,
1690                             struct uart_8250_port *port, int idx)
1691 {
1692         struct pci_dev *pdev = priv->dev;
1693         u8 config_base;
1694         u16 iobase;
1695 
1696         config_base = 0x40 + 0x08 * idx;
1697 
1698         /* Get the io address from configuration space */
1699         pci_read_config_word(pdev, config_base + 4, &iobase);
1700 
1701         dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1702 
1703         port->port.iotype = UPIO_PORT;
1704         port->port.iobase = iobase;
1705 
1706         return 0;
1707 }
1708 
1709 static int pci_fintek_init(struct pci_dev *dev)
1710 {
1711         unsigned long iobase;
1712         u32 max_port, i;
1713         u32 bar_data[3];
1714         u8 config_base;
1715 
1716         switch (dev->device) {
1717         case 0x1104: /* 4 ports */
1718         case 0x1108: /* 8 ports */
1719                 max_port = dev->device & 0xff;
1720                 break;
1721         case 0x1112: /* 12 ports */
1722                 max_port = 12;
1723                 break;
1724         default:
1725                 return -EINVAL;
1726         }
1727 
1728         /* Get the io address dispatch from the BIOS */
1729         pci_read_config_dword(dev, 0x24, &bar_data[0]);
1730         pci_read_config_dword(dev, 0x20, &bar_data[1]);
1731         pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1732 
1733         for (i = 0; i < max_port; ++i) {
1734                 /* UART0 configuration offset start from 0x40 */
1735                 config_base = 0x40 + 0x08 * i;
1736 
1737                 /* Calculate Real IO Port */
1738                 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1739 
1740                 /* Enable UART I/O port */
1741                 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1742 
1743                 /* Select 128-byte FIFO and 8x FIFO threshold */
1744                 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1745 
1746                 /* LSB UART */
1747                 pci_write_config_byte(dev, config_base + 0x04,
1748                                 (u8)(iobase & 0xff));
1749 
1750                 /* MSB UART */
1751                 pci_write_config_byte(dev, config_base + 0x05,
1752                                 (u8)((iobase & 0xff00) >> 8));
1753 
1754                 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1755         }
1756 
1757         return max_port;
1758 }
1759 
1760 static int skip_tx_en_setup(struct serial_private *priv,
1761                         const struct pciserial_board *board,
1762                         struct uart_8250_port *port, int idx)
1763 {
1764         port->port.flags |= UPF_NO_TXEN_TEST;
1765         dev_dbg(&priv->dev->dev,
1766                 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1767                 priv->dev->vendor, priv->dev->device,
1768                 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1769 
1770         return pci_default_setup(priv, board, port, idx);
1771 }
1772 
1773 static void kt_handle_break(struct uart_port *p)
1774 {
1775         struct uart_8250_port *up = up_to_u8250p(p);
1776         /*
1777          * On receipt of a BI, serial device in Intel ME (Intel
1778          * management engine) needs to have its fifos cleared for sane
1779          * SOL (Serial Over Lan) output.
1780          */
1781         serial8250_clear_and_reinit_fifos(up);
1782 }
1783 
1784 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1785 {
1786         struct uart_8250_port *up = up_to_u8250p(p);
1787         unsigned int val;
1788 
1789         /*
1790          * When the Intel ME (management engine) gets reset its serial
1791          * port registers could return 0 momentarily.  Functions like
1792          * serial8250_console_write, read and save the IER, perform
1793          * some operation and then restore it.  In order to avoid
1794          * setting IER register inadvertently to 0, if the value read
1795          * is 0, double check with ier value in uart_8250_port and use
1796          * that instead.  up->ier should be the same value as what is
1797          * currently configured.
1798          */
1799         val = inb(p->iobase + offset);
1800         if (offset == UART_IER) {
1801                 if (val == 0)
1802                         val = up->ier;
1803         }
1804         return val;
1805 }
1806 
1807 static int kt_serial_setup(struct serial_private *priv,
1808                            const struct pciserial_board *board,
1809                            struct uart_8250_port *port, int idx)
1810 {
1811         port->port.flags |= UPF_BUG_THRE;
1812         port->port.serial_in = kt_serial_in;
1813         port->port.handle_break = kt_handle_break;
1814         return skip_tx_en_setup(priv, board, port, idx);
1815 }
1816 
1817 static int pci_eg20t_init(struct pci_dev *dev)
1818 {
1819 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1820         return -ENODEV;
1821 #else
1822         return 0;
1823 #endif
1824 }
1825 
1826 static int
1827 pci_xr17c154_setup(struct serial_private *priv,
1828                   const struct pciserial_board *board,
1829                   struct uart_8250_port *port, int idx)
1830 {
1831         port->port.flags |= UPF_EXAR_EFR;
1832         return pci_default_setup(priv, board, port, idx);
1833 }
1834 
1835 static int
1836 pci_xr17v35x_setup(struct serial_private *priv,
1837                   const struct pciserial_board *board,
1838                   struct uart_8250_port *port, int idx)
1839 {
1840         u8 __iomem *p;
1841 
1842         p = pci_ioremap_bar(priv->dev, 0);
1843         if (p == NULL)
1844                 return -ENOMEM;
1845 
1846         port->port.flags |= UPF_EXAR_EFR;
1847 
1848         /*
1849          * Setup Multipurpose Input/Output pins.
1850          */
1851         if (idx == 0) {
1852                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1853                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1854                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1855                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1856                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1857                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1858                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1859                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1860                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1861                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1862                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1863                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1864         }
1865         writeb(0x00, p + UART_EXAR_8XMODE);
1866         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1867         writeb(128, p + UART_EXAR_TXTRG);
1868         writeb(128, p + UART_EXAR_RXTRG);
1869         iounmap(p);
1870 
1871         return pci_default_setup(priv, board, port, idx);
1872 }
1873 
1874 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1875 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1876 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1877 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1878 
1879 static int
1880 pci_fastcom335_setup(struct serial_private *priv,
1881                   const struct pciserial_board *board,
1882                   struct uart_8250_port *port, int idx)
1883 {
1884         u8 __iomem *p;
1885 
1886         p = pci_ioremap_bar(priv->dev, 0);
1887         if (p == NULL)
1888                 return -ENOMEM;
1889 
1890         port->port.flags |= UPF_EXAR_EFR;
1891 
1892         /*
1893          * Setup Multipurpose Input/Output pins.
1894          */
1895         if (idx == 0) {
1896                 switch (priv->dev->device) {
1897                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1898                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1899                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1900                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1901                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1902                         break;
1903                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1904                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1905                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1906                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1907                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1908                         break;
1909                 }
1910                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1911                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1912                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1913         }
1914         writeb(0x00, p + UART_EXAR_8XMODE);
1915         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1916         writeb(32, p + UART_EXAR_TXTRG);
1917         writeb(32, p + UART_EXAR_RXTRG);
1918         iounmap(p);
1919 
1920         return pci_default_setup(priv, board, port, idx);
1921 }
1922 
1923 static int
1924 pci_wch_ch353_setup(struct serial_private *priv,
1925                     const struct pciserial_board *board,
1926                     struct uart_8250_port *port, int idx)
1927 {
1928         port->port.flags |= UPF_FIXED_TYPE;
1929         port->port.type = PORT_16550A;
1930         return pci_default_setup(priv, board, port, idx);
1931 }
1932 
1933 static int
1934 pci_wch_ch38x_setup(struct serial_private *priv,
1935                     const struct pciserial_board *board,
1936                     struct uart_8250_port *port, int idx)
1937 {
1938         port->port.flags |= UPF_FIXED_TYPE;
1939         port->port.type = PORT_16850;
1940         return pci_default_setup(priv, board, port, idx);
1941 }
1942 
1943 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1944 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1945 #define PCI_DEVICE_ID_OCTPRO            0x0001
1946 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1947 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1948 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1949 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1950 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1951 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1952 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1953 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1954 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1955 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1956 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1957 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1958 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1959 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1960 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1961 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1962 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1963 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1964 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1965 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1966 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1967 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1968 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1969 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
1970 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1971 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1972 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1973 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1974 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1975 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1976 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1977 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1978 #define PCI_VENDOR_ID_WCH               0x4348
1979 #define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
1980 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1981 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1982 #define PCI_DEVICE_ID_WCH_CH353_1S1P    0x5053
1983 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1984 #define PCI_VENDOR_ID_AGESTAR           0x5372
1985 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1986 #define PCI_VENDOR_ID_ASIX              0x9710
1987 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1988 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1989 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1990 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1991 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1992 #define PCI_DEVICE_ID_INTEL_QRK_UART    0x0936
1993 
1994 #define PCI_VENDOR_ID_SUNIX             0x1fd4
1995 #define PCI_DEVICE_ID_SUNIX_1999        0x1999
1996 
1997 #define PCIE_VENDOR_ID_WCH              0x1c00
1998 #define PCIE_DEVICE_ID_WCH_CH382_2S1P   0x3250
1999 #define PCIE_DEVICE_ID_WCH_CH384_4S     0x3470
2000 
2001 #define PCI_DEVICE_ID_EXAR_XR17V8358    0x8358
2002 
2003 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
2004 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
2005 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
2006 
2007 /*
2008  * Master list of serial port init/setup/exit quirks.
2009  * This does not describe the general nature of the port.
2010  * (ie, baud base, number and location of ports, etc)
2011  *
2012  * This list is ordered alphabetically by vendor then device.
2013  * Specific entries must come before more generic entries.
2014  */
2015 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
2016         /*
2017         * ADDI-DATA GmbH communication cards <info@addi-data.com>
2018         */
2019         {
2020                 .vendor         = PCI_VENDOR_ID_AMCC,
2021                 .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2022                 .subvendor      = PCI_ANY_ID,
2023                 .subdevice      = PCI_ANY_ID,
2024                 .setup          = addidata_apci7800_setup,
2025         },
2026         /*
2027          * AFAVLAB cards - these may be called via parport_serial
2028          *  It is not clear whether this applies to all products.
2029          */
2030         {
2031                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
2032                 .device         = PCI_ANY_ID,
2033                 .subvendor      = PCI_ANY_ID,
2034                 .subdevice      = PCI_ANY_ID,
2035                 .setup          = afavlab_setup,
2036         },
2037         /*
2038          * HP Diva
2039          */
2040         {
2041                 .vendor         = PCI_VENDOR_ID_HP,
2042                 .device         = PCI_DEVICE_ID_HP_DIVA,
2043                 .subvendor      = PCI_ANY_ID,
2044                 .subdevice      = PCI_ANY_ID,
2045                 .init           = pci_hp_diva_init,
2046                 .setup          = pci_hp_diva_setup,
2047         },
2048         /*
2049          * Intel
2050          */
2051         {
2052                 .vendor         = PCI_VENDOR_ID_INTEL,
2053                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
2054                 .subvendor      = 0xe4bf,
2055                 .subdevice      = PCI_ANY_ID,
2056                 .init           = pci_inteli960ni_init,
2057                 .setup          = pci_default_setup,
2058         },
2059         {
2060                 .vendor         = PCI_VENDOR_ID_INTEL,
2061                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
2062                 .subvendor      = PCI_ANY_ID,
2063                 .subdevice      = PCI_ANY_ID,
2064                 .setup          = skip_tx_en_setup,
2065         },
2066         {
2067                 .vendor         = PCI_VENDOR_ID_INTEL,
2068                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
2069                 .subvendor      = PCI_ANY_ID,
2070                 .subdevice      = PCI_ANY_ID,
2071                 .setup          = skip_tx_en_setup,
2072         },
2073         {
2074                 .vendor         = PCI_VENDOR_ID_INTEL,
2075                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
2076                 .subvendor      = PCI_ANY_ID,
2077                 .subdevice      = PCI_ANY_ID,
2078                 .setup          = skip_tx_en_setup,
2079         },
2080         {
2081                 .vendor         = PCI_VENDOR_ID_INTEL,
2082                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
2083                 .subvendor      = PCI_ANY_ID,
2084                 .subdevice      = PCI_ANY_ID,
2085                 .setup          = ce4100_serial_setup,
2086         },
2087         {
2088                 .vendor         = PCI_VENDOR_ID_INTEL,
2089                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2090                 .subvendor      = PCI_ANY_ID,
2091                 .subdevice      = PCI_ANY_ID,
2092                 .setup          = kt_serial_setup,
2093         },
2094         {
2095                 .vendor         = PCI_VENDOR_ID_INTEL,
2096                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART1,
2097                 .subvendor      = PCI_ANY_ID,
2098                 .subdevice      = PCI_ANY_ID,
2099                 .setup          = byt_serial_setup,
2100         },
2101         {
2102                 .vendor         = PCI_VENDOR_ID_INTEL,
2103                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART2,
2104                 .subvendor      = PCI_ANY_ID,
2105                 .subdevice      = PCI_ANY_ID,
2106                 .setup          = byt_serial_setup,
2107         },
2108         {
2109                 .vendor         = PCI_VENDOR_ID_INTEL,
2110                 .device         = PCI_DEVICE_ID_INTEL_PNW_UART1,
2111                 .subvendor      = PCI_ANY_ID,
2112                 .subdevice      = PCI_ANY_ID,
2113                 .setup          = pnw_serial_setup,
2114         },
2115         {
2116                 .vendor         = PCI_VENDOR_ID_INTEL,
2117                 .device         = PCI_DEVICE_ID_INTEL_PNW_UART2,
2118                 .subvendor      = PCI_ANY_ID,
2119                 .subdevice      = PCI_ANY_ID,
2120                 .setup          = pnw_serial_setup,
2121         },
2122         {
2123                 .vendor         = PCI_VENDOR_ID_INTEL,
2124                 .device         = PCI_DEVICE_ID_INTEL_PNW_UART3,
2125                 .subvendor      = PCI_ANY_ID,
2126                 .subdevice      = PCI_ANY_ID,
2127                 .setup          = pnw_serial_setup,
2128         },
2129         {
2130                 .vendor         = PCI_VENDOR_ID_INTEL,
2131                 .device         = PCI_DEVICE_ID_INTEL_TNG_UART,
2132                 .subvendor      = PCI_ANY_ID,
2133                 .subdevice      = PCI_ANY_ID,
2134                 .setup          = tng_serial_setup,
2135         },
2136         {
2137                 .vendor         = PCI_VENDOR_ID_INTEL,
2138                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART1,
2139                 .subvendor      = PCI_ANY_ID,
2140                 .subdevice      = PCI_ANY_ID,
2141                 .setup          = byt_serial_setup,
2142         },
2143         {
2144                 .vendor         = PCI_VENDOR_ID_INTEL,
2145                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART2,
2146                 .subvendor      = PCI_ANY_ID,
2147                 .subdevice      = PCI_ANY_ID,
2148                 .setup          = byt_serial_setup,
2149         },
2150         /*
2151          * ITE
2152          */
2153         {
2154                 .vendor         = PCI_VENDOR_ID_ITE,
2155                 .device         = PCI_DEVICE_ID_ITE_8872,
2156                 .subvendor      = PCI_ANY_ID,
2157                 .subdevice      = PCI_ANY_ID,
2158                 .init           = pci_ite887x_init,
2159                 .setup          = pci_default_setup,
2160                 .exit           = pci_ite887x_exit,
2161         },
2162         /*
2163          * National Instruments
2164          */
2165         {
2166                 .vendor         = PCI_VENDOR_ID_NI,
2167                 .device         = PCI_DEVICE_ID_NI_PCI23216,
2168                 .subvendor      = PCI_ANY_ID,
2169                 .subdevice      = PCI_ANY_ID,
2170                 .init           = pci_ni8420_init,
2171                 .setup          = pci_default_setup,
2172                 .exit           = pci_ni8420_exit,
2173         },
2174         {
2175                 .vendor         = PCI_VENDOR_ID_NI,
2176                 .device         = PCI_DEVICE_ID_NI_PCI2328,
2177                 .subvendor      = PCI_ANY_ID,
2178                 .subdevice      = PCI_ANY_ID,
2179                 .init           = pci_ni8420_init,
2180                 .setup          = pci_default_setup,
2181                 .exit           = pci_ni8420_exit,
2182         },
2183         {
2184                 .vendor         = PCI_VENDOR_ID_NI,
2185                 .device         = PCI_DEVICE_ID_NI_PCI2324,
2186                 .subvendor      = PCI_ANY_ID,
2187                 .subdevice      = PCI_ANY_ID,
2188                 .init           = pci_ni8420_init,
2189                 .setup          = pci_default_setup,
2190                 .exit           = pci_ni8420_exit,
2191         },
2192         {
2193                 .vendor         = PCI_VENDOR_ID_NI,
2194                 .device         = PCI_DEVICE_ID_NI_PCI2322,
2195                 .subvendor      = PCI_ANY_ID,
2196                 .subdevice      = PCI_ANY_ID,
2197                 .init           = pci_ni8420_init,
2198                 .setup          = pci_default_setup,
2199                 .exit           = pci_ni8420_exit,
2200         },
2201         {
2202                 .vendor         = PCI_VENDOR_ID_NI,
2203                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
2204                 .subvendor      = PCI_ANY_ID,
2205                 .subdevice      = PCI_ANY_ID,
2206                 .init           = pci_ni8420_init,
2207                 .setup          = pci_default_setup,
2208                 .exit           = pci_ni8420_exit,
2209         },
2210         {
2211                 .vendor         = PCI_VENDOR_ID_NI,
2212                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
2213                 .subvendor      = PCI_ANY_ID,
2214                 .subdevice      = PCI_ANY_ID,
2215                 .init           = pci_ni8420_init,
2216                 .setup          = pci_default_setup,
2217                 .exit           = pci_ni8420_exit,
2218         },
2219         {
2220                 .vendor         = PCI_VENDOR_ID_NI,
2221                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
2222                 .subvendor      = PCI_ANY_ID,
2223                 .subdevice      = PCI_ANY_ID,
2224                 .init           = pci_ni8420_init,
2225                 .setup          = pci_default_setup,
2226                 .exit           = pci_ni8420_exit,
2227         },
2228         {
2229                 .vendor         = PCI_VENDOR_ID_NI,
2230                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
2231                 .subvendor      = PCI_ANY_ID,
2232                 .subdevice      = PCI_ANY_ID,
2233                 .init           = pci_ni8420_init,
2234                 .setup          = pci_default_setup,
2235                 .exit           = pci_ni8420_exit,
2236         },
2237         {
2238                 .vendor         = PCI_VENDOR_ID_NI,
2239                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
2240                 .subvendor      = PCI_ANY_ID,
2241                 .subdevice      = PCI_ANY_ID,
2242                 .init           = pci_ni8420_init,
2243                 .setup          = pci_default_setup,
2244                 .exit           = pci_ni8420_exit,
2245         },
2246         {
2247                 .vendor         = PCI_VENDOR_ID_NI,
2248                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
2249                 .subvendor      = PCI_ANY_ID,
2250                 .subdevice      = PCI_ANY_ID,
2251                 .init           = pci_ni8420_init,
2252                 .setup          = pci_default_setup,
2253                 .exit           = pci_ni8420_exit,
2254         },
2255         {
2256                 .vendor         = PCI_VENDOR_ID_NI,
2257                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
2258                 .subvendor      = PCI_ANY_ID,
2259                 .subdevice      = PCI_ANY_ID,
2260                 .init           = pci_ni8420_init,
2261                 .setup          = pci_default_setup,
2262                 .exit           = pci_ni8420_exit,
2263         },
2264         {
2265                 .vendor         = PCI_VENDOR_ID_NI,
2266                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
2267                 .subvendor      = PCI_ANY_ID,
2268                 .subdevice      = PCI_ANY_ID,
2269                 .init           = pci_ni8420_init,
2270                 .setup          = pci_default_setup,
2271                 .exit           = pci_ni8420_exit,
2272         },
2273         {
2274                 .vendor         = PCI_VENDOR_ID_NI,
2275                 .device         = PCI_ANY_ID,
2276                 .subvendor      = PCI_ANY_ID,
2277                 .subdevice      = PCI_ANY_ID,
2278                 .init           = pci_ni8430_init,
2279                 .setup          = pci_ni8430_setup,
2280                 .exit           = pci_ni8430_exit,
2281         },
2282         /* Quatech */
2283         {
2284                 .vendor         = PCI_VENDOR_ID_QUATECH,
2285                 .device         = PCI_ANY_ID,
2286                 .subvendor      = PCI_ANY_ID,
2287                 .subdevice      = PCI_ANY_ID,
2288                 .init           = pci_quatech_init,
2289                 .setup          = pci_quatech_setup,
2290                 .exit           = pci_quatech_exit,
2291         },
2292         /*
2293          * Panacom
2294          */
2295         {
2296                 .vendor         = PCI_VENDOR_ID_PANACOM,
2297                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2298                 .subvendor      = PCI_ANY_ID,
2299                 .subdevice      = PCI_ANY_ID,
2300                 .init           = pci_plx9050_init,
2301                 .setup          = pci_default_setup,
2302                 .exit           = pci_plx9050_exit,
2303         },
2304         {
2305                 .vendor         = PCI_VENDOR_ID_PANACOM,
2306                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2307                 .subvendor      = PCI_ANY_ID,
2308                 .subdevice      = PCI_ANY_ID,
2309                 .init           = pci_plx9050_init,
2310                 .setup          = pci_default_setup,
2311                 .exit           = pci_plx9050_exit,
2312         },
2313         /*
2314          * Pericom
2315          */
2316         {
2317                 .vendor         = 0x12d8,
2318                 .device         = 0x7952,
2319                 .subvendor      = PCI_ANY_ID,
2320                 .subdevice      = PCI_ANY_ID,
2321                 .setup          = pci_pericom_setup,
2322         },
2323         {
2324                 .vendor         = 0x12d8,
2325                 .device         = 0x7954,
2326                 .subvendor      = PCI_ANY_ID,
2327                 .subdevice      = PCI_ANY_ID,
2328                 .setup          = pci_pericom_setup,
2329         },
2330         {
2331                 .vendor         = 0x12d8,
2332                 .device         = 0x7958,
2333                 .subvendor      = PCI_ANY_ID,
2334                 .subdevice      = PCI_ANY_ID,
2335                 .setup          = pci_pericom_setup,
2336         },
2337 
2338         /*
2339          * PLX
2340          */
2341         {
2342                 .vendor         = PCI_VENDOR_ID_PLX,
2343                 .device         = PCI_DEVICE_ID_PLX_9050,
2344                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2345                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2346                 .init           = pci_plx9050_init,
2347                 .setup          = pci_default_setup,
2348                 .exit           = pci_plx9050_exit,
2349         },
2350         {
2351                 .vendor         = PCI_VENDOR_ID_PLX,
2352                 .device         = PCI_DEVICE_ID_PLX_9050,
2353                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2354                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2355                 .init           = pci_plx9050_init,
2356                 .setup          = pci_default_setup,
2357                 .exit           = pci_plx9050_exit,
2358         },
2359         {
2360                 .vendor         = PCI_VENDOR_ID_PLX,
2361                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2362                 .subvendor      = PCI_VENDOR_ID_PLX,
2363                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2364                 .init           = pci_plx9050_init,
2365                 .setup          = pci_default_setup,
2366                 .exit           = pci_plx9050_exit,
2367         },
2368         /*
2369          * SBS Technologies, Inc., PMC-OCTALPRO 232
2370          */
2371         {
2372                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2373                 .device         = PCI_DEVICE_ID_OCTPRO,
2374                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2375                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2376                 .init           = sbs_init,
2377                 .setup          = sbs_setup,
2378                 .exit           = sbs_exit,
2379         },
2380         /*
2381          * SBS Technologies, Inc., PMC-OCTALPRO 422
2382          */
2383         {
2384                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2385                 .device         = PCI_DEVICE_ID_OCTPRO,
2386                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2387                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2388                 .init           = sbs_init,
2389                 .setup          = sbs_setup,
2390                 .exit           = sbs_exit,
2391         },
2392         /*
2393          * SBS Technologies, Inc., P-Octal 232
2394          */
2395         {
2396                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2397                 .device         = PCI_DEVICE_ID_OCTPRO,
2398                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2399                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2400                 .init           = sbs_init,
2401                 .setup          = sbs_setup,
2402                 .exit           = sbs_exit,
2403         },
2404         /*
2405          * SBS Technologies, Inc., P-Octal 422
2406          */
2407         {
2408                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2409                 .device         = PCI_DEVICE_ID_OCTPRO,
2410                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2411                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2412                 .init           = sbs_init,
2413                 .setup          = sbs_setup,
2414                 .exit           = sbs_exit,
2415         },
2416         /*
2417          * SIIG cards - these may be called via parport_serial
2418          */
2419         {
2420                 .vendor         = PCI_VENDOR_ID_SIIG,
2421                 .device         = PCI_ANY_ID,
2422                 .subvendor      = PCI_ANY_ID,
2423                 .subdevice      = PCI_ANY_ID,
2424                 .init           = pci_siig_init,
2425                 .setup          = pci_siig_setup,
2426         },
2427         /*
2428          * Titan cards
2429          */
2430         {
2431                 .vendor         = PCI_VENDOR_ID_TITAN,
2432                 .device         = PCI_DEVICE_ID_TITAN_400L,
2433                 .subvendor      = PCI_ANY_ID,
2434                 .subdevice      = PCI_ANY_ID,
2435                 .setup          = titan_400l_800l_setup,
2436         },
2437         {
2438                 .vendor         = PCI_VENDOR_ID_TITAN,
2439                 .device         = PCI_DEVICE_ID_TITAN_800L,
2440                 .subvendor      = PCI_ANY_ID,
2441                 .subdevice      = PCI_ANY_ID,
2442                 .setup          = titan_400l_800l_setup,
2443         },
2444         /*
2445          * Timedia cards
2446          */
2447         {
2448                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2449                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2450                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2451                 .subdevice      = PCI_ANY_ID,
2452                 .probe          = pci_timedia_probe,
2453                 .init           = pci_timedia_init,
2454                 .setup          = pci_timedia_setup,
2455         },
2456         {
2457                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2458                 .device         = PCI_ANY_ID,
2459                 .subvendor      = PCI_ANY_ID,
2460                 .subdevice      = PCI_ANY_ID,
2461                 .setup          = pci_timedia_setup,
2462         },
2463         /*
2464          * SUNIX (Timedia) cards
2465          * Do not "probe" for these cards as there is at least one combination
2466          * card that should be handled by parport_pc that doesn't match the
2467          * rule in pci_timedia_probe.
2468          * It is part number is MIO5079A but its subdevice ID is 0x0102.
2469          * There are some boards with part number SER5037AL that report
2470          * subdevice ID 0x0002.
2471          */
2472         {
2473                 .vendor         = PCI_VENDOR_ID_SUNIX,
2474                 .device         = PCI_DEVICE_ID_SUNIX_1999,
2475                 .subvendor      = PCI_VENDOR_ID_SUNIX,
2476                 .subdevice      = PCI_ANY_ID,
2477                 .init           = pci_timedia_init,
2478                 .setup          = pci_timedia_setup,
2479         },
2480         /*
2481          * Exar cards
2482          */
2483         {
2484                 .vendor = PCI_VENDOR_ID_EXAR,
2485                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2486                 .subvendor      = PCI_ANY_ID,
2487                 .subdevice      = PCI_ANY_ID,
2488                 .setup          = pci_xr17c154_setup,
2489         },
2490         {
2491                 .vendor = PCI_VENDOR_ID_EXAR,
2492                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2493                 .subvendor      = PCI_ANY_ID,
2494                 .subdevice      = PCI_ANY_ID,
2495                 .setup          = pci_xr17c154_setup,
2496         },
2497         {
2498                 .vendor = PCI_VENDOR_ID_EXAR,
2499                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2500                 .subvendor      = PCI_ANY_ID,
2501                 .subdevice      = PCI_ANY_ID,
2502                 .setup          = pci_xr17c154_setup,
2503         },
2504         {
2505                 .vendor = PCI_VENDOR_ID_EXAR,
2506                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2507                 .subvendor      = PCI_ANY_ID,
2508                 .subdevice      = PCI_ANY_ID,
2509                 .setup          = pci_xr17v35x_setup,
2510         },
2511         {
2512                 .vendor = PCI_VENDOR_ID_EXAR,
2513                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2514                 .subvendor      = PCI_ANY_ID,
2515                 .subdevice      = PCI_ANY_ID,
2516                 .setup          = pci_xr17v35x_setup,
2517         },
2518         {
2519                 .vendor = PCI_VENDOR_ID_EXAR,
2520                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2521                 .subvendor      = PCI_ANY_ID,
2522                 .subdevice      = PCI_ANY_ID,
2523                 .setup          = pci_xr17v35x_setup,
2524         },
2525         {
2526                 .vendor = PCI_VENDOR_ID_EXAR,
2527                 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2528                 .subvendor      = PCI_ANY_ID,
2529                 .subdevice      = PCI_ANY_ID,
2530                 .setup          = pci_xr17v35x_setup,
2531         },
2532         /*
2533          * Xircom cards
2534          */
2535         {
2536                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2537                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2538                 .subvendor      = PCI_ANY_ID,
2539                 .subdevice      = PCI_ANY_ID,
2540                 .init           = pci_xircom_init,
2541                 .setup          = pci_default_setup,
2542         },
2543         /*
2544          * Netmos cards - these may be called via parport_serial
2545          */
2546         {
2547                 .vendor         = PCI_VENDOR_ID_NETMOS,
2548                 .device         = PCI_ANY_ID,
2549                 .subvendor      = PCI_ANY_ID,
2550                 .subdevice      = PCI_ANY_ID,
2551                 .init           = pci_netmos_init,
2552                 .setup          = pci_netmos_9900_setup,
2553         },
2554         /*
2555          * EndRun Technologies
2556         */
2557         {
2558                 .vendor         = PCI_VENDOR_ID_ENDRUN,
2559                 .device         = PCI_ANY_ID,
2560                 .subvendor      = PCI_ANY_ID,
2561                 .subdevice      = PCI_ANY_ID,
2562                 .init           = pci_endrun_init,
2563                 .setup          = pci_default_setup,
2564         },
2565         /*
2566          * For Oxford Semiconductor Tornado based devices
2567          */
2568         {
2569                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2570                 .device         = PCI_ANY_ID,
2571                 .subvendor      = PCI_ANY_ID,
2572                 .subdevice      = PCI_ANY_ID,
2573                 .init           = pci_oxsemi_tornado_init,
2574                 .setup          = pci_default_setup,
2575         },
2576         {
2577                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2578                 .device         = PCI_ANY_ID,
2579                 .subvendor      = PCI_ANY_ID,
2580                 .subdevice      = PCI_ANY_ID,
2581                 .init           = pci_oxsemi_tornado_init,
2582                 .setup          = pci_default_setup,
2583         },
2584         {
2585                 .vendor         = PCI_VENDOR_ID_DIGI,
2586                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2587                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2588                 .subdevice              = PCI_ANY_ID,
2589                 .init                   = pci_oxsemi_tornado_init,
2590                 .setup          = pci_default_setup,
2591         },
2592         {
2593                 .vendor         = PCI_VENDOR_ID_INTEL,
2594                 .device         = 0x8811,
2595                 .subvendor      = PCI_ANY_ID,
2596                 .subdevice      = PCI_ANY_ID,
2597                 .init           = pci_eg20t_init,
2598                 .setup          = pci_default_setup,
2599         },
2600         {
2601                 .vendor         = PCI_VENDOR_ID_INTEL,
2602                 .device         = 0x8812,
2603                 .subvendor      = PCI_ANY_ID,
2604                 .subdevice      = PCI_ANY_ID,
2605                 .init           = pci_eg20t_init,
2606                 .setup          = pci_default_setup,
2607         },
2608         {
2609                 .vendor         = PCI_VENDOR_ID_INTEL,
2610                 .device         = 0x8813,
2611                 .subvendor      = PCI_ANY_ID,
2612                 .subdevice      = PCI_ANY_ID,
2613                 .init           = pci_eg20t_init,
2614                 .setup          = pci_default_setup,
2615         },
2616         {
2617                 .vendor         = PCI_VENDOR_ID_INTEL,
2618                 .device         = 0x8814,
2619                 .subvendor      = PCI_ANY_ID,
2620                 .subdevice      = PCI_ANY_ID,
2621                 .init           = pci_eg20t_init,
2622                 .setup          = pci_default_setup,
2623         },
2624         {
2625                 .vendor         = 0x10DB,
2626                 .device         = 0x8027,
2627                 .subvendor      = PCI_ANY_ID,
2628                 .subdevice      = PCI_ANY_ID,
2629                 .init           = pci_eg20t_init,
2630                 .setup          = pci_default_setup,
2631         },
2632         {
2633                 .vendor         = 0x10DB,
2634                 .device         = 0x8028,
2635                 .subvendor      = PCI_ANY_ID,
2636                 .subdevice      = PCI_ANY_ID,
2637                 .init           = pci_eg20t_init,
2638                 .setup          = pci_default_setup,
2639         },
2640         {
2641                 .vendor         = 0x10DB,
2642                 .device         = 0x8029,
2643                 .subvendor      = PCI_ANY_ID,
2644                 .subdevice      = PCI_ANY_ID,
2645                 .init           = pci_eg20t_init,
2646                 .setup          = pci_default_setup,
2647         },
2648         {
2649                 .vendor         = 0x10DB,
2650                 .device         = 0x800C,
2651                 .subvendor      = PCI_ANY_ID,
2652                 .subdevice      = PCI_ANY_ID,
2653                 .init           = pci_eg20t_init,
2654                 .setup          = pci_default_setup,
2655         },
2656         {
2657                 .vendor         = 0x10DB,
2658                 .device         = 0x800D,
2659                 .subvendor      = PCI_ANY_ID,
2660                 .subdevice      = PCI_ANY_ID,
2661                 .init           = pci_eg20t_init,
2662                 .setup          = pci_default_setup,
2663         },
2664         /*
2665          * Cronyx Omega PCI (PLX-chip based)
2666          */
2667         {
2668                 .vendor         = PCI_VENDOR_ID_PLX,
2669                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2670                 .subvendor      = PCI_ANY_ID,
2671                 .subdevice      = PCI_ANY_ID,
2672                 .setup          = pci_omegapci_setup,
2673         },
2674         /* WCH CH353 1S1P card (16550 clone) */
2675         {
2676                 .vendor         = PCI_VENDOR_ID_WCH,
2677                 .device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2678                 .subvendor      = PCI_ANY_ID,
2679                 .subdevice      = PCI_ANY_ID,
2680                 .setup          = pci_wch_ch353_setup,
2681         },
2682         /* WCH CH353 2S1P card (16550 clone) */
2683         {
2684                 .vendor         = PCI_VENDOR_ID_WCH,
2685                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2686                 .subvendor      = PCI_ANY_ID,
2687                 .subdevice      = PCI_ANY_ID,
2688                 .setup          = pci_wch_ch353_setup,
2689         },
2690         /* WCH CH353 4S card (16550 clone) */
2691         {
2692                 .vendor         = PCI_VENDOR_ID_WCH,
2693                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2694                 .subvendor      = PCI_ANY_ID,
2695                 .subdevice      = PCI_ANY_ID,
2696                 .setup          = pci_wch_ch353_setup,
2697         },
2698         /* WCH CH353 2S1PF card (16550 clone) */
2699         {
2700                 .vendor         = PCI_VENDOR_ID_WCH,
2701                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2702                 .subvendor      = PCI_ANY_ID,
2703                 .subdevice      = PCI_ANY_ID,
2704                 .setup          = pci_wch_ch353_setup,
2705         },
2706         /* WCH CH352 2S card (16550 clone) */
2707         {
2708                 .vendor         = PCI_VENDOR_ID_WCH,
2709                 .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2710                 .subvendor      = PCI_ANY_ID,
2711                 .subdevice      = PCI_ANY_ID,
2712                 .setup          = pci_wch_ch353_setup,
2713         },
2714         /* WCH CH382 2S1P card (16850 clone) */
2715         {
2716                 .vendor         = PCIE_VENDOR_ID_WCH,
2717                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2718                 .subvendor      = PCI_ANY_ID,
2719                 .subdevice      = PCI_ANY_ID,
2720                 .setup          = pci_wch_ch38x_setup,
2721         },
2722         /* WCH CH384 4S card (16850 clone) */
2723         {
2724                 .vendor         = PCIE_VENDOR_ID_WCH,
2725                 .device         = PCIE_DEVICE_ID_WCH_CH384_4S,
2726                 .subvendor      = PCI_ANY_ID,
2727                 .subdevice      = PCI_ANY_ID,
2728                 .setup          = pci_wch_ch38x_setup,
2729         },
2730         /*
2731          * ASIX devices with FIFO bug
2732          */
2733         {
2734                 .vendor         = PCI_VENDOR_ID_ASIX,
2735                 .device         = PCI_ANY_ID,
2736                 .subvendor      = PCI_ANY_ID,
2737                 .subdevice      = PCI_ANY_ID,
2738                 .setup          = pci_asix_setup,
2739         },
2740         /*
2741          * Commtech, Inc. Fastcom adapters
2742          *
2743          */
2744         {
2745                 .vendor = PCI_VENDOR_ID_COMMTECH,
2746                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2747                 .subvendor      = PCI_ANY_ID,
2748                 .subdevice      = PCI_ANY_ID,
2749                 .setup          = pci_fastcom335_setup,
2750         },
2751         {
2752                 .vendor = PCI_VENDOR_ID_COMMTECH,
2753                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2754                 .subvendor      = PCI_ANY_ID,
2755                 .subdevice      = PCI_ANY_ID,
2756                 .setup          = pci_fastcom335_setup,
2757         },
2758         {
2759                 .vendor = PCI_VENDOR_ID_COMMTECH,
2760                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2761                 .subvendor      = PCI_ANY_ID,
2762                 .subdevice      = PCI_ANY_ID,
2763                 .setup          = pci_fastcom335_setup,
2764         },
2765         {
2766                 .vendor = PCI_VENDOR_ID_COMMTECH,
2767                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2768                 .subvendor      = PCI_ANY_ID,
2769                 .subdevice      = PCI_ANY_ID,
2770                 .setup          = pci_fastcom335_setup,
2771         },
2772         {
2773                 .vendor = PCI_VENDOR_ID_COMMTECH,
2774                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2775                 .subvendor      = PCI_ANY_ID,
2776                 .subdevice      = PCI_ANY_ID,
2777                 .setup          = pci_xr17v35x_setup,
2778         },
2779         {
2780                 .vendor = PCI_VENDOR_ID_COMMTECH,
2781                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2782                 .subvendor      = PCI_ANY_ID,
2783                 .subdevice      = PCI_ANY_ID,
2784                 .setup          = pci_xr17v35x_setup,
2785         },
2786         {
2787                 .vendor = PCI_VENDOR_ID_COMMTECH,
2788                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2789                 .subvendor      = PCI_ANY_ID,
2790                 .subdevice      = PCI_ANY_ID,
2791                 .setup          = pci_xr17v35x_setup,
2792         },
2793         /*
2794          * Broadcom TruManage (NetXtreme)
2795          */
2796         {
2797                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2798                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2799                 .subvendor      = PCI_ANY_ID,
2800                 .subdevice      = PCI_ANY_ID,
2801                 .setup          = pci_brcm_trumanage_setup,
2802         },
2803         {
2804                 .vendor         = 0x1c29,
2805                 .device         = 0x1104,
2806                 .subvendor      = PCI_ANY_ID,
2807                 .subdevice      = PCI_ANY_ID,
2808                 .setup          = pci_fintek_setup,
2809                 .init           = pci_fintek_init,
2810         },
2811         {
2812                 .vendor         = 0x1c29,
2813                 .device         = 0x1108,
2814                 .subvendor      = PCI_ANY_ID,
2815                 .subdevice      = PCI_ANY_ID,
2816                 .setup          = pci_fintek_setup,
2817                 .init           = pci_fintek_init,
2818         },
2819         {
2820                 .vendor         = 0x1c29,
2821                 .device         = 0x1112,
2822                 .subvendor      = PCI_ANY_ID,
2823                 .subdevice      = PCI_ANY_ID,
2824                 .setup          = pci_fintek_setup,
2825                 .init           = pci_fintek_init,
2826         },
2827 
2828         /*
2829          * Default "match everything" terminator entry
2830          */
2831         {
2832                 .vendor         = PCI_ANY_ID,
2833                 .device         = PCI_ANY_ID,
2834                 .subvendor      = PCI_ANY_ID,
2835                 .subdevice      = PCI_ANY_ID,
2836                 .setup          = pci_default_setup,
2837         }
2838 };
2839 
2840 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2841 {
2842         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2843 }
2844 
2845 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2846 {
2847         struct pci_serial_quirk *quirk;
2848 
2849         for (quirk = pci_serial_quirks; ; quirk++)
2850                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2851                     quirk_id_matches(quirk->device, dev->device) &&
2852                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2853                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2854                         break;
2855         return quirk;
2856 }
2857 
2858 static inline int get_pci_irq(struct pci_dev *dev,
2859                                 const struct pciserial_board *board)
2860 {
2861         if (board->flags & FL_NOIRQ)
2862                 return 0;
2863         else
2864                 return dev->irq;
2865 }
2866 
2867 /*
2868  * This is the configuration table for all of the PCI serial boards
2869  * which we support.  It is directly indexed by the pci_board_num_t enum
2870  * value, which is encoded in the pci_device_id PCI probe table's
2871  * driver_data member.
2872  *
2873  * The makeup of these names are:
2874  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2875  *
2876  *  bn          = PCI BAR number
2877  *  bt          = Index using PCI BARs
2878  *  n           = number of serial ports
2879  *  baud        = baud rate
2880  *  offsetinhex = offset for each sequential port (in hex)
2881  *
2882  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2883  *
2884  * Please note: in theory if n = 1, _bt infix should make no difference.
2885  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2886  */
2887 enum pci_board_num_t {
2888         pbn_default = 0,
2889 
2890         pbn_b0_1_115200,
2891         pbn_b0_2_115200,
2892         pbn_b0_4_115200,
2893         pbn_b0_5_115200,
2894         pbn_b0_8_115200,
2895 
2896         pbn_b0_1_921600,
2897         pbn_b0_2_921600,
2898         pbn_b0_4_921600,
2899 
2900         pbn_b0_2_1130000,
2901 
2902         pbn_b0_4_1152000,
2903 
2904         pbn_b0_2_1152000_200,
2905         pbn_b0_4_1152000_200,
2906         pbn_b0_8_1152000_200,
2907 
2908         pbn_b0_2_1843200,
2909         pbn_b0_4_1843200,
2910 
2911         pbn_b0_2_1843200_200,
2912         pbn_b0_4_1843200_200,
2913         pbn_b0_8_1843200_200,
2914 
2915         pbn_b0_1_4000000,
2916 
2917         pbn_b0_bt_1_115200,
2918         pbn_b0_bt_2_115200,
2919         pbn_b0_bt_4_115200,
2920         pbn_b0_bt_8_115200,
2921 
2922         pbn_b0_bt_1_460800,
2923         pbn_b0_bt_2_460800,
2924         pbn_b0_bt_4_460800,
2925 
2926         pbn_b0_bt_1_921600,
2927         pbn_b0_bt_2_921600,
2928         pbn_b0_bt_4_921600,
2929         pbn_b0_bt_8_921600,
2930 
2931         pbn_b1_1_115200,
2932         pbn_b1_2_115200,
2933         pbn_b1_4_115200,
2934         pbn_b1_8_115200,
2935         pbn_b1_16_115200,
2936 
2937         pbn_b1_1_921600,
2938         pbn_b1_2_921600,
2939         pbn_b1_4_921600,
2940         pbn_b1_8_921600,
2941 
2942         pbn_b1_2_1250000,
2943 
2944         pbn_b1_bt_1_115200,
2945         pbn_b1_bt_2_115200,
2946         pbn_b1_bt_4_115200,
2947 
2948         pbn_b1_bt_2_921600,
2949 
2950         pbn_b1_1_1382400,
2951         pbn_b1_2_1382400,
2952         pbn_b1_4_1382400,
2953         pbn_b1_8_1382400,
2954 
2955         pbn_b2_1_115200,
2956         pbn_b2_2_115200,
2957         pbn_b2_4_115200,
2958         pbn_b2_8_115200,
2959 
2960         pbn_b2_1_460800,
2961         pbn_b2_4_460800,
2962         pbn_b2_8_460800,
2963         pbn_b2_16_460800,
2964 
2965         pbn_b2_1_921600,
2966         pbn_b2_4_921600,
2967         pbn_b2_8_921600,
2968 
2969         pbn_b2_8_1152000,
2970 
2971         pbn_b2_bt_1_115200,
2972         pbn_b2_bt_2_115200,
2973         pbn_b2_bt_4_115200,
2974 
2975         pbn_b2_bt_2_921600,
2976         pbn_b2_bt_4_921600,
2977 
2978         pbn_b3_2_115200,
2979         pbn_b3_4_115200,
2980         pbn_b3_8_115200,
2981 
2982         pbn_b4_bt_2_921600,
2983         pbn_b4_bt_4_921600,
2984         pbn_b4_bt_8_921600,
2985 
2986         /*
2987          * Board-specific versions.
2988          */
2989         pbn_panacom,
2990         pbn_panacom2,
2991         pbn_panacom4,
2992         pbn_plx_romulus,
2993         pbn_endrun_2_4000000,
2994         pbn_oxsemi,
2995         pbn_oxsemi_1_4000000,
2996         pbn_oxsemi_2_4000000,
2997         pbn_oxsemi_4_4000000,
2998         pbn_oxsemi_8_4000000,
2999         pbn_intel_i960,
3000         pbn_sgi_ioc3,
3001         pbn_computone_4,
3002         pbn_computone_6,
3003         pbn_computone_8,
3004         pbn_sbsxrsio,
3005         pbn_exar_XR17C152,
3006         pbn_exar_XR17C154,
3007         pbn_exar_XR17C158,
3008         pbn_exar_XR17V352,
3009         pbn_exar_XR17V354,
3010         pbn_exar_XR17V358,
3011         pbn_exar_XR17V8358,
3012         pbn_exar_ibm_saturn,
3013         pbn_pasemi_1682M,
3014         pbn_ni8430_2,
3015         pbn_ni8430_4,
3016         pbn_ni8430_8,
3017         pbn_ni8430_16,
3018         pbn_ADDIDATA_PCIe_1_3906250,
3019         pbn_ADDIDATA_PCIe_2_3906250,
3020         pbn_ADDIDATA_PCIe_4_3906250,
3021         pbn_ADDIDATA_PCIe_8_3906250,
3022         pbn_ce4100_1_115200,
3023         pbn_byt,
3024         pbn_pnw,
3025         pbn_tng,
3026         pbn_qrk,
3027         pbn_omegapci,
3028         pbn_NETMOS9900_2s_115200,
3029         pbn_brcm_trumanage,
3030         pbn_fintek_4,
3031         pbn_fintek_8,
3032         pbn_fintek_12,
3033         pbn_wch384_4,
3034 };
3035 
3036 /*
3037  * uart_offset - the space between channels
3038  * reg_shift   - describes how the UART registers are mapped
3039  *               to PCI memory by the card.
3040  * For example IER register on SBS, Inc. PMC-OctPro is located at
3041  * offset 0x10 from the UART base, while UART_IER is defined as 1
3042  * in include/linux/serial_reg.h,
3043  * see first lines of serial_in() and serial_out() in 8250.c
3044 */
3045 
3046 static struct pciserial_board pci_boards[] = {
3047         [pbn_default] = {
3048                 .flags          = FL_BASE0,
3049                 .num_ports      = 1,
3050                 .base_baud      = 115200,
3051                 .uart_offset    = 8,
3052         },
3053         [pbn_b0_1_115200] = {
3054                 .flags          = FL_BASE0,
3055                 .num_ports      = 1,
3056                 .base_baud      = 115200,
3057                 .uart_offset    = 8,
3058         },
3059         [pbn_b0_2_115200] = {
3060                 .flags          = FL_BASE0,
3061                 .num_ports      = 2,
3062                 .base_baud      = 115200,
3063                 .uart_offset    = 8,
3064         },
3065         [pbn_b0_4_115200] = {
3066                 .flags          = FL_BASE0,
3067                 .num_ports      = 4,
3068                 .base_baud      = 115200,
3069                 .uart_offset    = 8,
3070         },
3071         [pbn_b0_5_115200] = {
3072                 .flags          = FL_BASE0,
3073                 .num_ports      = 5,
3074                 .base_baud      = 115200,
3075                 .uart_offset    = 8,
3076         },
3077         [pbn_b0_8_115200] = {
3078                 .flags          = FL_BASE0,
3079                 .num_ports      = 8,
3080                 .base_baud      = 115200,
3081                 .uart_offset    = 8,
3082         },
3083         [pbn_b0_1_921600] = {
3084                 .flags          = FL_BASE0,
3085                 .num_ports      = 1,
3086                 .base_baud      = 921600,
3087                 .uart_offset    = 8,
3088         },
3089         [pbn_b0_2_921600] = {
3090                 .flags          = FL_BASE0,
3091                 .num_ports      = 2,
3092                 .base_baud      = 921600,
3093                 .uart_offset    = 8,
3094         },
3095         [pbn_b0_4_921600] = {
3096                 .flags          = FL_BASE0,
3097                 .num_ports      = 4,
3098                 .base_baud      = 921600,
3099                 .uart_offset    = 8,
3100         },
3101 
3102         [pbn_b0_2_1130000] = {
3103                 .flags          = FL_BASE0,
3104                 .num_ports      = 2,
3105                 .base_baud      = 1130000,
3106                 .uart_offset    = 8,
3107         },
3108 
3109         [pbn_b0_4_1152000] = {
3110                 .flags          = FL_BASE0,
3111                 .num_ports      = 4,
3112                 .base_baud      = 1152000,
3113                 .uart_offset    = 8,
3114         },
3115 
3116         [pbn_b0_2_1152000_200] = {
3117                 .flags          = FL_BASE0,
3118                 .num_ports      = 2,
3119                 .base_baud      = 1152000,
3120                 .uart_offset    = 0x200,
3121         },
3122 
3123         [pbn_b0_4_1152000_200] = {
3124                 .flags          = FL_BASE0,
3125                 .num_ports      = 4,
3126                 .base_baud      = 1152000,
3127                 .uart_offset    = 0x200,
3128         },
3129 
3130         [pbn_b0_8_1152000_200] = {
3131                 .flags          = FL_BASE0,
3132                 .num_ports      = 8,
3133                 .base_baud      = 1152000,
3134                 .uart_offset    = 0x200,
3135         },
3136 
3137         [pbn_b0_2_1843200] = {
3138                 .flags          = FL_BASE0,
3139                 .num_ports      = 2,
3140                 .base_baud      = 1843200,
3141                 .uart_offset    = 8,
3142         },
3143         [pbn_b0_4_1843200] = {
3144                 .flags          = FL_BASE0,
3145                 .num_ports      = 4,
3146                 .base_baud      = 1843200,
3147                 .uart_offset    = 8,
3148         },
3149 
3150         [pbn_b0_2_1843200_200] = {
3151                 .flags          = FL_BASE0,
3152                 .num_ports      = 2,
3153                 .base_baud      = 1843200,
3154                 .uart_offset    = 0x200,
3155         },
3156         [pbn_b0_4_1843200_200] = {
3157                 .flags          = FL_BASE0,
3158                 .num_ports      = 4,
3159                 .base_baud      = 1843200,
3160                 .uart_offset    = 0x200,
3161         },
3162         [pbn_b0_8_1843200_200] = {
3163                 .flags          = FL_BASE0,
3164                 .num_ports      = 8,
3165                 .base_baud      = 1843200,
3166                 .uart_offset    = 0x200,
3167         },
3168         [pbn_b0_1_4000000] = {
3169                 .flags          = FL_BASE0,
3170                 .num_ports      = 1,
3171                 .base_baud      = 4000000,
3172                 .uart_offset    = 8,
3173         },
3174 
3175         [pbn_b0_bt_1_115200] = {
3176                 .flags          = FL_BASE0|FL_BASE_BARS,
3177                 .num_ports      = 1,
3178                 .base_baud      = 115200,
3179                 .uart_offset    = 8,
3180         },
3181         [pbn_b0_bt_2_115200] = {
3182                 .flags          = FL_BASE0|FL_BASE_BARS,
3183                 .num_ports      = 2,
3184                 .base_baud      = 115200,
3185                 .uart_offset    = 8,
3186         },
3187         [pbn_b0_bt_4_115200] = {
3188                 .flags          = FL_BASE0|FL_BASE_BARS,
3189                 .num_ports      = 4,
3190                 .base_baud      = 115200,
3191                 .uart_offset    = 8,
3192         },
3193         [pbn_b0_bt_8_115200] = {
3194                 .flags          = FL_BASE0|FL_BASE_BARS,
3195                 .num_ports      = 8,
3196                 .base_baud      = 115200,
3197                 .uart_offset    = 8,
3198         },
3199 
3200         [pbn_b0_bt_1_460800] = {
3201                 .flags          = FL_BASE0|FL_BASE_BARS,
3202                 .num_ports      = 1,
3203                 .base_baud      = 460800,
3204                 .uart_offset    = 8,
3205         },
3206         [pbn_b0_bt_2_460800] = {
3207                 .flags          = FL_BASE0|FL_BASE_BARS,
3208                 .num_ports      = 2,
3209                 .base_baud      = 460800,
3210                 .uart_offset    = 8,
3211         },
3212         [pbn_b0_bt_4_460800] = {
3213                 .flags          = FL_BASE0|FL_BASE_BARS,
3214                 .num_ports      = 4,
3215                 .base_baud      = 460800,
3216                 .uart_offset    = 8,
3217         },
3218 
3219         [pbn_b0_bt_1_921600] = {
3220                 .flags          = FL_BASE0|FL_BASE_BARS,
3221                 .num_ports      = 1,
3222                 .base_baud      = 921600,
3223                 .uart_offset    = 8,
3224         },
3225         [pbn_b0_bt_2_921600] = {
3226                 .flags          = FL_BASE0|FL_BASE_BARS,
3227                 .num_ports      = 2,
3228                 .base_baud      = 921600,
3229                 .uart_offset    = 8,
3230         },
3231         [pbn_b0_bt_4_921600] = {
3232                 .flags          = FL_BASE0|FL_BASE_BARS,
3233                 .num_ports      = 4,
3234                 .base_baud      = 921600,
3235                 .uart_offset    = 8,
3236         },
3237         [pbn_b0_bt_8_921600] = {
3238                 .flags          = FL_BASE0|FL_BASE_BARS,
3239                 .num_ports      = 8,
3240                 .base_baud      = 921600,
3241                 .uart_offset    = 8,
3242         },
3243 
3244         [pbn_b1_1_115200] = {
3245                 .flags          = FL_BASE1,
3246                 .num_ports      = 1,
3247                 .base_baud      = 115200,
3248                 .uart_offset    = 8,
3249         },
3250         [pbn_b1_2_115200] = {
3251                 .flags          = FL_BASE1,
3252                 .num_ports      = 2,
3253                 .base_baud      = 115200,
3254                 .uart_offset    = 8,
3255         },
3256         [pbn_b1_4_115200] = {
3257                 .flags          = FL_BASE1,
3258                 .num_ports      = 4,
3259                 .base_baud      = 115200,
3260                 .uart_offset    = 8,
3261         },
3262         [pbn_b1_8_115200] = {
3263                 .flags          = FL_BASE1,
3264                 .num_ports      = 8,
3265                 .base_baud      = 115200,
3266                 .uart_offset    = 8,
3267         },
3268         [pbn_b1_16_115200] = {
3269                 .flags          = FL_BASE1,
3270                 .num_ports      = 16,
3271                 .base_baud      = 115200,
3272                 .uart_offset    = 8,
3273         },
3274 
3275         [pbn_b1_1_921600] = {
3276                 .flags          = FL_BASE1,
3277                 .num_ports      = 1,
3278                 .base_baud      = 921600,
3279                 .uart_offset    = 8,
3280         },
3281         [pbn_b1_2_921600] = {
3282                 .flags          = FL_BASE1,
3283                 .num_ports      = 2,
3284                 .base_baud      = 921600,
3285                 .uart_offset    = 8,
3286         },
3287         [pbn_b1_4_921600] = {
3288                 .flags          = FL_BASE1,
3289                 .num_ports      = 4,
3290                 .base_baud      = 921600,
3291                 .uart_offset    = 8,
3292         },
3293         [pbn_b1_8_921600] = {
3294                 .flags          = FL_BASE1,
3295                 .num_ports      = 8,
3296                 .base_baud      = 921600,
3297                 .uart_offset    = 8,
3298         },
3299         [pbn_b1_2_1250000] = {
3300                 .flags          = FL_BASE1,
3301                 .num_ports      = 2,
3302                 .base_baud      = 1250000,
3303                 .uart_offset    = 8,
3304         },
3305 
3306         [pbn_b1_bt_1_115200] = {
3307                 .flags          = FL_BASE1|FL_BASE_BARS,
3308                 .num_ports      = 1,
3309                 .base_baud      = 115200,
3310                 .uart_offset    = 8,
3311         },
3312         [pbn_b1_bt_2_115200] = {
3313                 .flags          = FL_BASE1|FL_BASE_BARS,
3314                 .num_ports      = 2,
3315                 .base_baud      = 115200,
3316                 .uart_offset    = 8,
3317         },
3318         [pbn_b1_bt_4_115200] = {
3319                 .flags          = FL_BASE1|FL_BASE_BARS,
3320                 .num_ports      = 4,
3321                 .base_baud      = 115200,
3322                 .uart_offset    = 8,
3323         },
3324 
3325         [pbn_b1_bt_2_921600] = {
3326                 .flags          = FL_BASE1|FL_BASE_BARS,
3327                 .num_ports      = 2,
3328                 .base_baud      = 921600,
3329                 .uart_offset    = 8,
3330         },
3331 
3332         [pbn_b1_1_1382400] = {
3333                 .flags          = FL_BASE1,
3334                 .num_ports      = 1,
3335                 .base_baud      = 1382400,
3336                 .uart_offset    = 8,
3337         },
3338         [pbn_b1_2_1382400] = {
3339                 .flags          = FL_BASE1,
3340                 .num_ports      = 2,
3341                 .base_baud      = 1382400,
3342                 .uart_offset    = 8,
3343         },
3344         [pbn_b1_4_1382400] = {
3345                 .flags          = FL_BASE1,
3346                 .num_ports      = 4,
3347                 .base_baud      = 1382400,
3348                 .uart_offset    = 8,
3349         },
3350         [pbn_b1_8_1382400] = {
3351                 .flags          = FL_BASE1,
3352                 .num_ports      = 8,
3353                 .base_baud      = 1382400,
3354                 .uart_offset    = 8,
3355         },
3356 
3357         [pbn_b2_1_115200] = {
3358                 .flags          = FL_BASE2,
3359                 .num_ports      = 1,
3360                 .base_baud      = 115200,
3361                 .uart_offset    = 8,
3362         },
3363         [pbn_b2_2_115200] = {
3364                 .flags          = FL_BASE2,
3365                 .num_ports      = 2,
3366                 .base_baud      = 115200,
3367                 .uart_offset    = 8,
3368         },
3369         [pbn_b2_4_115200] = {
3370                 .flags          = FL_BASE2,
3371                 .num_ports      = 4,
3372                 .base_baud      = 115200,
3373                 .uart_offset    = 8,
3374         },
3375         [pbn_b2_8_115200] = {
3376                 .flags          = FL_BASE2,
3377                 .num_ports      = 8,
3378                 .base_baud      = 115200,
3379                 .uart_offset    = 8,
3380         },
3381 
3382         [pbn_b2_1_460800] = {
3383                 .flags          = FL_BASE2,
3384                 .num_ports      = 1,
3385                 .base_baud      = 460800,
3386                 .uart_offset    = 8,
3387         },
3388         [pbn_b2_4_460800] = {
3389                 .flags          = FL_BASE2,
3390                 .num_ports      = 4,
3391                 .base_baud      = 460800,
3392                 .uart_offset    = 8,
3393         },
3394         [pbn_b2_8_460800] = {
3395                 .flags          = FL_BASE2,
3396                 .num_ports      = 8,
3397                 .base_baud      = 460800,
3398                 .uart_offset    = 8,
3399         },
3400         [pbn_b2_16_460800] = {
3401                 .flags          = FL_BASE2,
3402                 .num_ports      = 16,
3403                 .base_baud      = 460800,
3404                 .uart_offset    = 8,
3405          },
3406 
3407         [pbn_b2_1_921600] = {
3408                 .flags          = FL_BASE2,
3409                 .num_ports      = 1,
3410                 .base_baud      = 921600,
3411                 .uart_offset    = 8,
3412         },
3413         [pbn_b2_4_921600] = {
3414                 .flags          = FL_BASE2,
3415                 .num_ports      = 4,
3416                 .base_baud      = 921600,
3417                 .uart_offset    = 8,
3418         },
3419         [pbn_b2_8_921600] = {
3420                 .flags          = FL_BASE2,
3421                 .num_ports      = 8,
3422                 .base_baud      = 921600,
3423                 .uart_offset    = 8,
3424         },
3425 
3426         [pbn_b2_8_1152000] = {
3427                 .flags          = FL_BASE2,
3428                 .num_ports      = 8,
3429                 .base_baud      = 1152000,
3430                 .uart_offset    = 8,
3431         },
3432 
3433         [pbn_b2_bt_1_115200] = {
3434                 .flags          = FL_BASE2|FL_BASE_BARS,
3435                 .num_ports      = 1,
3436                 .base_baud      = 115200,
3437                 .uart_offset    = 8,
3438         },
3439         [pbn_b2_bt_2_115200] = {
3440                 .flags          = FL_BASE2|FL_BASE_BARS,
3441                 .num_ports      = 2,
3442                 .base_baud      = 115200,
3443                 .uart_offset    = 8,
3444         },
3445         [pbn_b2_bt_4_115200] = {
3446                 .flags          = FL_BASE2|FL_BASE_BARS,
3447                 .num_ports      = 4,
3448                 .base_baud      = 115200,
3449                 .uart_offset    = 8,
3450         },
3451 
3452         [pbn_b2_bt_2_921600] = {
3453                 .flags          = FL_BASE2|FL_BASE_BARS,
3454                 .num_ports      = 2,
3455                 .base_baud      = 921600,
3456                 .uart_offset    = 8,
3457         },
3458         [pbn_b2_bt_4_921600] = {
3459                 .flags          = FL_BASE2|FL_BASE_BARS,
3460                 .num_ports      = 4,
3461                 .base_baud      = 921600,
3462                 .uart_offset    = 8,
3463         },
3464 
3465         [pbn_b3_2_115200] = {
3466                 .flags          = FL_BASE3,
3467                 .num_ports      = 2,
3468                 .base_baud      = 115200,
3469                 .uart_offset    = 8,
3470         },
3471         [pbn_b3_4_115200] = {
3472                 .flags          = FL_BASE3,
3473                 .num_ports      = 4,
3474                 .base_baud      = 115200,
3475                 .uart_offset    = 8,
3476         },
3477         [pbn_b3_8_115200] = {
3478                 .flags          = FL_BASE3,
3479                 .num_ports      = 8,
3480                 .base_baud      = 115200,
3481                 .uart_offset    = 8,
3482         },
3483 
3484         [pbn_b4_bt_2_921600] = {
3485                 .flags          = FL_BASE4,
3486                 .num_ports      = 2,
3487                 .base_baud      = 921600,
3488                 .uart_offset    = 8,
3489         },
3490         [pbn_b4_bt_4_921600] = {
3491                 .flags          = FL_BASE4,
3492                 .num_ports      = 4,
3493                 .base_baud      = 921600,
3494                 .uart_offset    = 8,
3495         },
3496         [pbn_b4_bt_8_921600] = {
3497                 .flags          = FL_BASE4,
3498                 .num_ports      = 8,
3499                 .base_baud      = 921600,
3500                 .uart_offset    = 8,
3501         },
3502 
3503         /*
3504          * Entries following this are board-specific.
3505          */
3506 
3507         /*
3508          * Panacom - IOMEM
3509          */
3510         [pbn_panacom] = {
3511                 .flags          = FL_BASE2,
3512                 .num_ports      = 2,
3513                 .base_baud      = 921600,
3514                 .uart_offset    = 0x400,
3515                 .reg_shift      = 7,
3516         },
3517         [pbn_panacom2] = {
3518                 .flags          = FL_BASE2|FL_BASE_BARS,
3519                 .num_ports      = 2,
3520                 .base_baud      = 921600,
3521                 .uart_offset    = 0x400,
3522                 .reg_shift      = 7,
3523         },
3524         [pbn_panacom4] = {
3525                 .flags          = FL_BASE2|FL_BASE_BARS,
3526                 .num_ports      = 4,
3527                 .base_baud      = 921600,
3528                 .uart_offset    = 0x400,
3529                 .reg_shift      = 7,
3530         },
3531 
3532         /* I think this entry is broken - the first_offset looks wrong --rmk */
3533         [pbn_plx_romulus] = {
3534                 .flags          = FL_BASE2,
3535                 .num_ports      = 4,
3536                 .base_baud      = 921600,
3537                 .uart_offset    = 8 << 2,
3538                 .reg_shift      = 2,
3539                 .first_offset   = 0x03,
3540         },
3541 
3542         /*
3543          * EndRun Technologies
3544         * Uses the size of PCI Base region 0 to
3545         * signal now many ports are available
3546         * 2 port 952 Uart support
3547         */
3548         [pbn_endrun_2_4000000] = {
3549                 .flags          = FL_BASE0,
3550                 .num_ports      = 2,
3551                 .base_baud      = 4000000,
3552                 .uart_offset    = 0x200,
3553                 .first_offset   = 0x1000,
3554         },
3555 
3556         /*
3557          * This board uses the size of PCI Base region 0 to
3558          * signal now many ports are available
3559          */
3560         [pbn_oxsemi] = {
3561                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3562                 .num_ports      = 32,
3563                 .base_baud      = 115200,
3564                 .uart_offset    = 8,
3565         },
3566         [pbn_oxsemi_1_4000000] = {
3567                 .flags          = FL_BASE0,
3568                 .num_ports      = 1,
3569                 .base_baud      = 4000000,
3570                 .uart_offset    = 0x200,
3571                 .first_offset   = 0x1000,
3572         },
3573         [pbn_oxsemi_2_4000000] = {
3574                 .flags          = FL_BASE0,
3575                 .num_ports      = 2,
3576                 .base_baud      = 4000000,
3577                 .uart_offset    = 0x200,
3578                 .first_offset   = 0x1000,
3579         },
3580         [pbn_oxsemi_4_4000000] = {
3581                 .flags          = FL_BASE0,
3582                 .num_ports      = 4,
3583                 .base_baud      = 4000000,
3584                 .uart_offset    = 0x200,
3585                 .first_offset   = 0x1000,
3586         },
3587         [pbn_oxsemi_8_4000000] = {
3588                 .flags          = FL_BASE0,
3589                 .num_ports      = 8,
3590                 .base_baud      = 4000000,
3591                 .uart_offset    = 0x200,
3592                 .first_offset   = 0x1000,
3593         },
3594 
3595 
3596         /*
3597          * EKF addition for i960 Boards form EKF with serial port.
3598          * Max 256 ports.
3599          */
3600         [pbn_intel_i960] = {
3601                 .flags          = FL_BASE0,
3602                 .num_ports      = 32,
3603                 .base_baud      = 921600,
3604                 .uart_offset    = 8 << 2,
3605                 .reg_shift      = 2,
3606                 .first_offset   = 0x10000,
3607         },
3608         [pbn_sgi_ioc3] = {
3609                 .flags          = FL_BASE0|FL_NOIRQ,
3610                 .num_ports      = 1,
3611                 .base_baud      = 458333,
3612                 .uart_offset    = 8,
3613                 .reg_shift      = 0,
3614                 .first_offset   = 0x20178,
3615         },
3616 
3617         /*
3618          * Computone - uses IOMEM.
3619          */
3620         [pbn_computone_4] = {
3621                 .flags          = FL_BASE0,
3622                 .num_ports      = 4,
3623                 .base_baud      = 921600,
3624                 .uart_offset    = 0x40,
3625                 .reg_shift      = 2,
3626                 .first_offset   = 0x200,
3627         },
3628         [pbn_computone_6] = {
3629                 .flags          = FL_BASE0,
3630                 .num_ports      = 6,
3631                 .base_baud      = 921600,
3632                 .uart_offset    = 0x40,
3633                 .reg_shift      = 2,
3634                 .first_offset   = 0x200,
3635         },
3636         [pbn_computone_8] = {
3637                 .flags          = FL_BASE0,
3638                 .num_ports      = 8,
3639                 .base_baud      = 921600,
3640                 .uart_offset    = 0x40,
3641                 .reg_shift      = 2,
3642                 .first_offset   = 0x200,
3643         },
3644         [pbn_sbsxrsio] = {
3645                 .flags          = FL_BASE0,
3646                 .num_ports      = 8,
3647                 .base_baud      = 460800,
3648                 .uart_offset    = 256,
3649                 .reg_shift      = 4,
3650         },
3651         /*
3652          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3653          *  Only basic 16550A support.
3654          *  XR17C15[24] are not tested, but they should work.
3655          */
3656         [pbn_exar_XR17C152] = {
3657                 .flags          = FL_BASE0,
3658                 .num_ports      = 2,
3659                 .base_baud      = 921600,
3660                 .uart_offset    = 0x200,
3661         },
3662         [pbn_exar_XR17C154] = {
3663                 .flags          = FL_BASE0,
3664                 .num_ports      = 4,
3665                 .base_baud      = 921600,
3666                 .uart_offset    = 0x200,
3667         },
3668         [pbn_exar_XR17C158] = {
3669                 .flags          = FL_BASE0,
3670                 .num_ports      = 8,
3671                 .base_baud      = 921600,
3672                 .uart_offset    = 0x200,
3673         },
3674         [pbn_exar_XR17V352] = {
3675                 .flags          = FL_BASE0,
3676                 .num_ports      = 2,
3677                 .base_baud      = 7812500,
3678                 .uart_offset    = 0x400,
3679                 .reg_shift      = 0,
3680                 .first_offset   = 0,
3681         },
3682         [pbn_exar_XR17V354] = {
3683                 .flags          = FL_BASE0,
3684                 .num_ports      = 4,
3685                 .base_baud      = 7812500,
3686                 .uart_offset    = 0x400,
3687                 .reg_shift      = 0,
3688                 .first_offset   = 0,
3689         },
3690         [pbn_exar_XR17V358] = {
3691                 .flags          = FL_BASE0,
3692                 .num_ports      = 8,
3693                 .base_baud      = 7812500,
3694                 .uart_offset    = 0x400,
3695                 .reg_shift      = 0,
3696                 .first_offset   = 0,
3697         },
3698         [pbn_exar_XR17V8358] = {
3699                 .flags          = FL_BASE0,
3700                 .num_ports      = 16,
3701                 .base_baud      = 7812500,
3702                 .uart_offset    = 0x400,
3703                 .reg_shift      = 0,
3704                 .first_offset   = 0,
3705         },
3706         [pbn_exar_ibm_saturn] = {
3707                 .flags          = FL_BASE0,
3708                 .num_ports      = 1,
3709                 .base_baud      = 921600,
3710                 .uart_offset    = 0x200,
3711         },
3712 
3713         /*
3714          * PA Semi PWRficient PA6T-1682M on-chip UART
3715          */
3716         [pbn_pasemi_1682M] = {
3717                 .flags          = FL_BASE0,
3718                 .num_ports      = 1,
3719                 .base_baud      = 8333333,
3720         },
3721         /*
3722          * National Instruments 843x
3723          */
3724         [pbn_ni8430_16] = {
3725                 .flags          = FL_BASE0,
3726                 .num_ports      = 16,
3727                 .base_baud      = 3686400,
3728                 .uart_offset    = 0x10,
3729                 .first_offset   = 0x800,
3730         },
3731         [pbn_ni8430_8] = {
3732                 .flags          = FL_BASE0,
3733                 .num_ports      = 8,
3734                 .base_baud      = 3686400,
3735                 .uart_offset    = 0x10,
3736                 .first_offset   = 0x800,
3737         },
3738         [pbn_ni8430_4] = {
3739                 .flags          = FL_BASE0,
3740                 .num_ports      = 4,
3741                 .base_baud      = 3686400,
3742                 .uart_offset    = 0x10,
3743                 .first_offset   = 0x800,
3744         },
3745         [pbn_ni8430_2] = {
3746                 .flags          = FL_BASE0,
3747                 .num_ports      = 2,
3748                 .base_baud      = 3686400,
3749                 .uart_offset    = 0x10,
3750                 .first_offset   = 0x800,
3751         },
3752         /*
3753          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3754          */
3755         [pbn_ADDIDATA_PCIe_1_3906250] = {
3756                 .flags          = FL_BASE0,
3757                 .num_ports      = 1,
3758                 .base_baud      = 3906250,
3759                 .uart_offset    = 0x200,
3760                 .first_offset   = 0x1000,
3761         },
3762         [pbn_ADDIDATA_PCIe_2_3906250] = {
3763                 .flags          = FL_BASE0,
3764                 .num_ports      = 2,
3765                 .base_baud      = 3906250,
3766                 .uart_offset    = 0x200,
3767                 .first_offset   = 0x1000,
3768         },
3769         [pbn_ADDIDATA_PCIe_4_3906250] = {
3770                 .flags          = FL_BASE0,
3771                 .num_ports      = 4,
3772                 .base_baud      = 3906250,
3773                 .uart_offset    = 0x200,
3774                 .first_offset   = 0x1000,
3775         },
3776         [pbn_ADDIDATA_PCIe_8_3906250] = {
3777                 .flags          = FL_BASE0,
3778                 .num_ports      = 8,
3779                 .base_baud      = 3906250,
3780                 .uart_offset    = 0x200,
3781                 .first_offset   = 0x1000,
3782         },
3783         [pbn_ce4100_1_115200] = {
3784                 .flags          = FL_BASE_BARS,
3785                 .num_ports      = 2,
3786                 .base_baud      = 921600,
3787                 .reg_shift      = 2,
3788         },
3789         /*
3790          * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3791          * but is overridden by byt_set_termios.
3792          */
3793         [pbn_byt] = {
3794                 .flags          = FL_BASE0,
3795                 .num_ports      = 1,
3796                 .base_baud      = 2764800,
3797                 .uart_offset    = 0x80,
3798                 .reg_shift      = 2,
3799         },
3800         [pbn_pnw] = {
3801                 .flags          = FL_BASE0,
3802                 .num_ports      = 1,
3803                 .base_baud      = 115200,
3804         },
3805         [pbn_tng] = {
3806                 .flags          = FL_BASE0,
3807                 .num_ports      = 1,
3808                 .base_baud      = 1843200,
3809         },
3810         [pbn_qrk] = {
3811                 .flags          = FL_BASE0,
3812                 .num_ports      = 1,
3813                 .base_baud      = 2764800,
3814                 .reg_shift      = 2,
3815         },
3816         [pbn_omegapci] = {
3817                 .flags          = FL_BASE0,
3818                 .num_ports      = 8,
3819                 .base_baud      = 115200,
3820                 .uart_offset    = 0x200,
3821         },
3822         [pbn_NETMOS9900_2s_115200] = {
3823                 .flags          = FL_BASE0,
3824                 .num_ports      = 2,
3825                 .base_baud      = 115200,
3826         },
3827         [pbn_brcm_trumanage] = {
3828                 .flags          = FL_BASE0,
3829                 .num_ports      = 1,
3830                 .reg_shift      = 2,
3831                 .base_baud      = 115200,
3832         },
3833         [pbn_fintek_4] = {
3834                 .num_ports      = 4,
3835                 .uart_offset    = 8,
3836                 .base_baud      = 115200,
3837                 .first_offset   = 0x40,
3838         },
3839         [pbn_fintek_8] = {
3840                 .num_ports      = 8,
3841                 .uart_offset    = 8,
3842                 .base_baud      = 115200,
3843                 .first_offset   = 0x40,
3844         },
3845         [pbn_fintek_12] = {
3846                 .num_ports      = 12,
3847                 .uart_offset    = 8,
3848                 .base_baud      = 115200,
3849                 .first_offset   = 0x40,
3850         },
3851 
3852         [pbn_wch384_4] = {
3853                 .flags          = FL_BASE0,
3854                 .num_ports      = 4,
3855                 .base_baud      = 115200,
3856                 .uart_offset    = 8,
3857                 .first_offset   = 0xC0,
3858         },
3859 };
3860 
3861 static const struct pci_device_id blacklist[] = {
3862         /* softmodems */
3863         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3864         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3865         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3866 
3867         /* multi-io cards handled by parport_serial */
3868         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3869         { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3870         { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3871         { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3872 };
3873 
3874 /*
3875  * Given a complete unknown PCI device, try to use some heuristics to
3876  * guess what the configuration might be, based on the pitiful PCI
3877  * serial specs.  Returns 0 on success, 1 on failure.
3878  */
3879 static int
3880 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3881 {
3882         const struct pci_device_id *bldev;
3883         int num_iomem, num_port, first_port = -1, i;
3884 
3885         /*
3886          * If it is not a communications device or the programming
3887          * interface is greater than 6, give up.
3888          *
3889          * (Should we try to make guesses for multiport serial devices
3890          * later?)
3891          */
3892         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3893              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3894             (dev->class & 0xff) > 6)
3895                 return -ENODEV;
3896 
3897         /*
3898          * Do not access blacklisted devices that are known not to
3899          * feature serial ports or are handled by other modules.
3900          */
3901         for (bldev = blacklist;
3902              bldev < blacklist + ARRAY_SIZE(blacklist);
3903              bldev++) {
3904                 if (dev->vendor == bldev->vendor &&
3905                     dev->device == bldev->device)
3906                         return -ENODEV;
3907         }
3908 
3909         num_iomem = num_port = 0;
3910         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3911                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3912                         num_port++;
3913                         if (first_port == -1)
3914                                 first_port = i;
3915                 }
3916                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3917                         num_iomem++;
3918         }
3919 
3920         /*
3921          * If there is 1 or 0 iomem regions, and exactly one port,
3922          * use it.  We guess the number of ports based on the IO
3923          * region size.
3924          */
3925         if (num_iomem <= 1 && num_port == 1) {
3926                 board->flags = first_port;
3927                 board->num_ports = pci_resource_len(dev, first_port) / 8;
3928                 return 0;
3929         }
3930 
3931         /*
3932          * Now guess if we've got a board which indexes by BARs.
3933          * Each IO BAR should be 8 bytes, and they should follow
3934          * consecutively.
3935          */
3936         first_port = -1;
3937         num_port = 0;
3938         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3939                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3940                     pci_resource_len(dev, i) == 8 &&
3941                     (first_port == -1 || (first_port + num_port) == i)) {
3942                         num_port++;
3943                         if (first_port == -1)
3944                                 first_port = i;
3945                 }
3946         }
3947 
3948         if (num_port > 1) {
3949                 board->flags = first_port | FL_BASE_BARS;
3950                 board->num_ports = num_port;
3951                 return 0;
3952         }
3953 
3954         return -ENODEV;
3955 }
3956 
3957 static inline int
3958 serial_pci_matches(const struct pciserial_board *board,
3959                    const struct pciserial_board *guessed)
3960 {
3961         return
3962             board->num_ports == guessed->num_ports &&
3963             board->base_baud == guessed->base_baud &&
3964             board->uart_offset == guessed->uart_offset &&
3965             board->reg_shift == guessed->reg_shift &&
3966             board->first_offset == guessed->first_offset;
3967 }
3968 
3969 struct serial_private *
3970 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3971 {
3972         struct uart_8250_port uart;
3973         struct serial_private *priv;
3974         struct pci_serial_quirk *quirk;
3975         int rc, nr_ports, i;
3976 
3977         nr_ports = board->num_ports;
3978 
3979         /*
3980          * Find an init and setup quirks.
3981          */
3982         quirk = find_quirk(dev);
3983 
3984         /*
3985          * Run the new-style initialization function.
3986          * The initialization function returns:
3987          *  <0  - error
3988          *   0  - use board->num_ports
3989          *  >0  - number of ports
3990          */
3991         if (quirk->init) {
3992                 rc = quirk->init(dev);
3993                 if (rc < 0) {
3994                         priv = ERR_PTR(rc);
3995                         goto err_out;
3996                 }
3997                 if (rc)
3998                         nr_ports = rc;
3999         }
4000 
4001         priv = kzalloc(sizeof(struct serial_private) +
4002                        sizeof(unsigned int) * nr_ports,
4003                        GFP_KERNEL);
4004         if (!priv) {
4005                 priv = ERR_PTR(-ENOMEM);
4006                 goto err_deinit;
4007         }
4008 
4009         priv->dev = dev;
4010         priv->quirk = quirk;
4011 
4012         memset(&uart, 0, sizeof(uart));
4013         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4014         uart.port.uartclk = board->base_baud * 16;
4015         uart.port.irq = get_pci_irq(dev, board);
4016         uart.port.dev = &dev->dev;
4017 
4018         for (i = 0; i < nr_ports; i++) {
4019                 if (quirk->setup(priv, board, &uart, i))
4020                         break;
4021 
4022                 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4023                         uart.port.iobase, uart.port.irq, uart.port.iotype);
4024 
4025                 priv->line[i] = serial8250_register_8250_port(&uart);
4026                 if (priv->line[i] < 0) {
4027                         dev_err(&dev->dev,
4028                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4029                                 uart.port.iobase, uart.port.irq,
4030                                 uart.port.iotype, priv->line[i]);
4031                         break;
4032                 }
4033         }
4034         priv->nr = i;
4035         return priv;
4036 
4037 err_deinit:
4038         if (quirk->exit)
4039                 quirk->exit(dev);
4040 err_out:
4041         return priv;
4042 }
4043 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4044 
4045 void pciserial_remove_ports(struct serial_private *priv)
4046 {
4047         struct pci_serial_quirk *quirk;
4048         int i;
4049 
4050         for (i = 0; i < priv->nr; i++)
4051                 serial8250_unregister_port(priv->line[i]);
4052 
4053         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4054                 if (priv->remapped_bar[i])
4055                         iounmap(priv->remapped_bar[i]);
4056                 priv->remapped_bar[i] = NULL;
4057         }
4058 
4059         /*
4060          * Find the exit quirks.
4061          */
4062         quirk = find_quirk(priv->dev);
4063         if (quirk->exit)
4064                 quirk->exit(priv->dev);
4065 
4066         kfree(priv);
4067 }
4068 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4069 
4070 void pciserial_suspend_ports(struct serial_private *priv)
4071 {
4072         int i;
4073 
4074         for (i = 0; i < priv->nr; i++)
4075                 if (priv->line[i] >= 0)
4076                         serial8250_suspend_port(priv->line[i]);
4077 
4078         /*
4079          * Ensure that every init quirk is properly torn down
4080          */
4081         if (priv->quirk->exit)
4082                 priv->quirk->exit(priv->dev);
4083 }
4084 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4085 
4086 void pciserial_resume_ports(struct serial_private *priv)
4087 {
4088         int i;
4089 
4090         /*
4091          * Ensure that the board is correctly configured.
4092          */
4093         if (priv->quirk->init)
4094                 priv->quirk->init(priv->dev);
4095 
4096         for (i = 0; i < priv->nr; i++)
4097                 if (priv->line[i] >= 0)
4098                         serial8250_resume_port(priv->line[i]);
4099 }
4100 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4101 
4102 /*
4103  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
4104  * to the arrangement of serial ports on a PCI card.
4105  */
4106 static int
4107 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4108 {
4109         struct pci_serial_quirk *quirk;
4110         struct serial_private *priv;
4111         const struct pciserial_board *board;
4112         struct pciserial_board tmp;
4113         int rc;
4114 
4115         quirk = find_quirk(dev);
4116         if (quirk->probe) {
4117                 rc = quirk->probe(dev);
4118                 if (rc)
4119                         return rc;
4120         }
4121 
4122         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4123                 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4124                         ent->driver_data);
4125                 return -EINVAL;
4126         }
4127 
4128         board = &pci_boards[ent->driver_data];
4129 
4130         rc = pci_enable_device(dev);
4131         pci_save_state(dev);
4132         if (rc)
4133                 return rc;
4134 
4135         if (ent->driver_data == pbn_default) {
4136                 /*
4137                  * Use a copy of the pci_board entry for this;
4138                  * avoid changing entries in the table.
4139                  */
4140                 memcpy(&tmp, board, sizeof(struct pciserial_board));
4141                 board = &tmp;
4142 
4143                 /*
4144                  * We matched one of our class entries.  Try to
4145                  * determine the parameters of this board.
4146                  */
4147                 rc = serial_pci_guess_board(dev, &tmp);
4148                 if (rc)
4149                         goto disable;
4150         } else {
4151                 /*
4152                  * We matched an explicit entry.  If we are able to
4153                  * detect this boards settings with our heuristic,
4154                  * then we no longer need this entry.
4155                  */
4156                 memcpy(&tmp, &pci_boards[pbn_default],
4157                        sizeof(struct pciserial_board));
4158                 rc = serial_pci_guess_board(dev, &tmp);
4159                 if (rc == 0 && serial_pci_matches(board, &tmp))
4160                         moan_device("Redundant entry in serial pci_table.",
4161                                     dev);
4162         }
4163 
4164         priv = pciserial_init_ports(dev, board);
4165         if (!IS_ERR(priv)) {
4166                 pci_set_drvdata(dev, priv);
4167                 return 0;
4168         }
4169 
4170         rc = PTR_ERR(priv);
4171 
4172  disable:
4173         pci_disable_device(dev);
4174         return rc;
4175 }
4176 
4177 static void pciserial_remove_one(struct pci_dev *dev)
4178 {
4179         struct serial_private *priv = pci_get_drvdata(dev);
4180 
4181         pciserial_remove_ports(priv);
4182 
4183         pci_disable_device(dev);
4184 }
4185 
4186 #ifdef CONFIG_PM_SLEEP
4187 static int pciserial_suspend_one(struct device *dev)
4188 {
4189         struct pci_dev *pdev = to_pci_dev(dev);
4190         struct serial_private *priv = pci_get_drvdata(pdev);
4191 
4192         if (priv)
4193                 pciserial_suspend_ports(priv);
4194 
4195         return 0;
4196 }
4197 
4198 static int pciserial_resume_one(struct device *dev)
4199 {
4200         struct pci_dev *pdev = to_pci_dev(dev);
4201         struct serial_private *priv = pci_get_drvdata(pdev);
4202         int err;
4203 
4204         if (priv) {
4205                 /*
4206                  * The device may have been disabled.  Re-enable it.
4207                  */
4208                 err = pci_enable_device(pdev);
4209                 /* FIXME: We cannot simply error out here */
4210                 if (err)
4211                         dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4212                 pciserial_resume_ports(priv);
4213         }
4214         return 0;
4215 }
4216 #endif
4217 
4218 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4219                          pciserial_resume_one);
4220 
4221 static struct pci_device_id serial_pci_tbl[] = {
4222         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4223         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4224                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4225                 pbn_b2_8_921600 },
4226         /* Advantech also use 0x3618 and 0xf618 */
4227         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4228                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4229                 pbn_b0_4_921600 },
4230         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4231                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4232                 pbn_b0_4_921600 },
4233         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4234                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4235                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4236                 pbn_b1_8_1382400 },
4237         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4238                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4239                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4240                 pbn_b1_4_1382400 },
4241         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4242                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4243                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4244                 pbn_b1_2_1382400 },
4245         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4246                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4247                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4248                 pbn_b1_8_1382400 },
4249         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4250                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4251                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4252                 pbn_b1_4_1382400 },
4253         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4254                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4255                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4256                 pbn_b1_2_1382400 },
4257         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4258                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4259                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4260                 pbn_b1_8_921600 },
4261         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4262                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4263                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4264                 pbn_b1_8_921600 },
4265         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4266                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4267                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4268                 pbn_b1_4_921600 },
4269         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4270                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4271                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4272                 pbn_b1_4_921600 },
4273         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4274                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4275                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4276                 pbn_b1_2_921600 },
4277         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4278                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4279                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4280                 pbn_b1_8_921600 },
4281         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4282                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4283                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4284                 pbn_b1_8_921600 },
4285         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4286                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4287                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4288                 pbn_b1_4_921600 },
4289         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4290                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4291                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4292                 pbn_b1_2_1250000 },
4293         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4294                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4295                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4296                 pbn_b0_2_1843200 },
4297         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4298                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4299                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4300                 pbn_b0_4_1843200 },
4301         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4302                 PCI_VENDOR_ID_AFAVLAB,
4303                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4304                 pbn_b0_4_1152000 },
4305         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4306                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4307                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4308                 pbn_b0_2_1843200_200 },
4309         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4310                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4311                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4312                 pbn_b0_4_1843200_200 },
4313         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4314                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4315                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4316                 pbn_b0_8_1843200_200 },
4317         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4318                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4319                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4320                 pbn_b0_2_1843200_200 },
4321         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4322                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4323                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4324                 pbn_b0_4_1843200_200 },
4325         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4326                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4327                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4328                 pbn_b0_8_1843200_200 },
4329         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4330                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4331                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4332                 pbn_b0_2_1843200_200 },
4333         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4334                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4335                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4336                 pbn_b0_4_1843200_200 },
4337         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4338                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4339                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4340                 pbn_b0_8_1843200_200 },
4341         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4342                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4343                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4344                 pbn_b0_2_1843200_200 },
4345         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4346                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4347                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4348                 pbn_b0_4_1843200_200 },
4349         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4350                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4351                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4352                 pbn_b0_8_1843200_200 },
4353         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4354                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4355                 0, 0, pbn_exar_ibm_saturn },
4356 
4357         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4358                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4359                 pbn_b2_bt_1_115200 },
4360         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4361                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4362                 pbn_b2_bt_2_115200 },
4363         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4364                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4365                 pbn_b2_bt_4_115200 },
4366         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4367                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4368                 pbn_b2_bt_2_115200 },
4369         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4370                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4371                 pbn_b2_bt_4_115200 },
4372         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4373                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4374                 pbn_b2_8_115200 },
4375         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4376                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4377                 pbn_b2_8_460800 },
4378         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4379                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4380                 pbn_b2_8_115200 },
4381 
4382         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4383                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4384                 pbn_b2_bt_2_115200 },
4385         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4386                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4387                 pbn_b2_bt_2_921600 },
4388         /*
4389          * VScom SPCOM800, from sl@s.pl
4390          */
4391         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4392                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4393                 pbn_b2_8_921600 },
4394         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4395                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4396                 pbn_b2_4_921600 },
4397         /* Unknown card - subdevice 0x1584 */
4398         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4399                 PCI_VENDOR_ID_PLX,
4400                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4401                 pbn_b2_4_115200 },
4402         /* Unknown card - subdevice 0x1588 */
4403         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4404                 PCI_VENDOR_ID_PLX,
4405                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4406                 pbn_b2_8_115200 },
4407         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4408                 PCI_SUBVENDOR_ID_KEYSPAN,
4409                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4410                 pbn_panacom },
4411         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4412                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4413                 pbn_panacom4 },
4414         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4415                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4416                 pbn_panacom2 },
4417         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4418                 PCI_VENDOR_ID_ESDGMBH,
4419                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4420                 pbn_b2_4_115200 },
4421         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4422                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4423                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4424                 pbn_b2_4_460800 },
4425         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4426                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4427                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4428                 pbn_b2_8_460800 },
4429         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4430                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4431                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4432                 pbn_b2_16_460800 },
4433         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4434                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4435                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4436                 pbn_b2_16_460800 },
4437         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4438                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4439                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4440                 pbn_b2_4_460800 },
4441         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4442                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4443                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4444                 pbn_b2_8_460800 },
4445         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4446                 PCI_SUBVENDOR_ID_EXSYS,
4447                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4448                 pbn_b2_4_115200 },
4449         /*
4450          * Megawolf Romulus PCI Serial Card, from Mike Hudson
4451          * (Exoray@isys.ca)
4452          */
4453         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4454                 0x10b5, 0x106a, 0, 0,
4455                 pbn_plx_romulus },
4456         /*
4457         * EndRun Technologies. PCI express device range.
4458         *    EndRun PTP/1588 has 2 Native UARTs.
4459         */
4460         {       PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4461                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4462                 pbn_endrun_2_4000000 },
4463         /*
4464          * Quatech cards. These actually have configurable clocks but for
4465          * now we just use the default.
4466          *
4467          * 100 series are RS232, 200 series RS422,
4468          */
4469         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4470                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471                 pbn_b1_4_115200 },
4472         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4473                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474                 pbn_b1_2_115200 },
4475         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4476                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477                 pbn_b2_2_115200 },
4478         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4479                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480                 pbn_b1_2_115200 },
4481         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4482                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4483                 pbn_b2_2_115200 },
4484         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4485                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4486                 pbn_b1_4_115200 },
4487         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4488                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4489                 pbn_b1_8_115200 },
4490         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4491                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4492                 pbn_b1_8_115200 },
4493         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4494                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4495                 pbn_b1_4_115200 },
4496         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4497                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4498                 pbn_b1_2_115200 },
4499         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4500                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4501                 pbn_b1_4_115200 },
4502         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4503                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4504                 pbn_b1_2_115200 },
4505         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4506                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507                 pbn_b2_4_115200 },
4508         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4509                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510                 pbn_b2_2_115200 },
4511         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4512                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513                 pbn_b2_1_115200 },
4514         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4515                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516                 pbn_b2_4_115200 },
4517         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4518                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4519                 pbn_b2_2_115200 },
4520         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4521                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4522                 pbn_b2_1_115200 },
4523         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4524                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525                 pbn_b0_8_115200 },
4526 
4527         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4528                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4529                 0, 0,
4530                 pbn_b0_4_921600 },
4531         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4532                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4533                 0, 0,
4534                 pbn_b0_4_1152000 },
4535         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
4536                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4537                 pbn_b0_bt_2_921600 },
4538 
4539                 /*
4540                  * The below card is a little controversial since it is the
4541                  * subject of a PCI vendor/device ID clash.  (See
4542                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4543                  * For now just used the hex ID 0x950a.
4544                  */
4545         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4546                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4547                 0, 0, pbn_b0_2_115200 },
4548         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4549                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4550                 0, 0, pbn_b0_2_115200 },
4551         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4552                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4553                 pbn_b0_2_1130000 },
4554         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4555                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4556                 pbn_b0_1_921600 },
4557         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4558                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4559                 pbn_b0_4_115200 },
4560         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4561                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4562                 pbn_b0_bt_2_921600 },
4563         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4564                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4565                 pbn_b2_8_1152000 },
4566 
4567         /*
4568          * Oxford Semiconductor Inc. Tornado PCI express device range.
4569          */
4570         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4571                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4572                 pbn_b0_1_4000000 },
4573         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4574                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4575                 pbn_b0_1_4000000 },
4576         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4577                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4578                 pbn_oxsemi_1_4000000 },
4579         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4580                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581                 pbn_oxsemi_1_4000000 },
4582         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4583                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584                 pbn_b0_1_4000000 },
4585         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4586                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587                 pbn_b0_1_4000000 },
4588         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4589                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590                 pbn_oxsemi_1_4000000 },
4591         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4592                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593                 pbn_oxsemi_1_4000000 },
4594         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4595                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596                 pbn_b0_1_4000000 },
4597         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4598                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599                 pbn_b0_1_4000000 },
4600         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4601                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602                 pbn_b0_1_4000000 },
4603         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4604                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605                 pbn_b0_1_4000000 },
4606         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4607                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608                 pbn_oxsemi_2_4000000 },
4609         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4610                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611                 pbn_oxsemi_2_4000000 },
4612         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4613                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614                 pbn_oxsemi_4_4000000 },
4615         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4616                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617                 pbn_oxsemi_4_4000000 },
4618         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4619                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620                 pbn_oxsemi_8_4000000 },
4621         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4622                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623                 pbn_oxsemi_8_4000000 },
4624         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4625                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626                 pbn_oxsemi_1_4000000 },
4627         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4628                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629                 pbn_oxsemi_1_4000000 },
4630         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4631                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632                 pbn_oxsemi_1_4000000 },
4633         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4634                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635                 pbn_oxsemi_1_4000000 },
4636         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4637                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638                 pbn_oxsemi_1_4000000 },
4639         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4640                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641                 pbn_oxsemi_1_4000000 },
4642         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4643                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644                 pbn_oxsemi_1_4000000 },
4645         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4646                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647                 pbn_oxsemi_1_4000000 },
4648         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4649                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650                 pbn_oxsemi_1_4000000 },
4651         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4652                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653                 pbn_oxsemi_1_4000000 },
4654         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4655                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656                 pbn_oxsemi_1_4000000 },
4657         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4658                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4659                 pbn_oxsemi_1_4000000 },
4660         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4661                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662                 pbn_oxsemi_1_4000000 },
4663         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4664                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4665                 pbn_oxsemi_1_4000000 },
4666         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4667                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4668                 pbn_oxsemi_1_4000000 },
4669         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4670                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4671                 pbn_oxsemi_1_4000000 },
4672         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4673                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4674                 pbn_oxsemi_1_4000000 },
4675         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4676                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4677                 pbn_oxsemi_1_4000000 },
4678         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4679                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4680                 pbn_oxsemi_1_4000000 },
4681         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4682                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4683                 pbn_oxsemi_1_4000000 },
4684         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4685                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4686                 pbn_oxsemi_1_4000000 },
4687         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4688                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4689                 pbn_oxsemi_1_4000000 },
4690         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4691                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4692                 pbn_oxsemi_1_4000000 },
4693         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4694                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695                 pbn_oxsemi_1_4000000 },
4696         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4697                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4698                 pbn_oxsemi_1_4000000 },
4699         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4700                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4701                 pbn_oxsemi_1_4000000 },
4702         /*
4703          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4704          */
4705         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4706                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4707                 pbn_oxsemi_1_4000000 },
4708         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4709                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4710                 pbn_oxsemi_2_4000000 },
4711         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4712                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4713                 pbn_oxsemi_4_4000000 },
4714         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4715                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4716                 pbn_oxsemi_8_4000000 },
4717 
4718         /*
4719          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4720          */
4721         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4722                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4723                 pbn_oxsemi_2_4000000 },
4724 
4725         /*
4726          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4727          * from skokodyn@yahoo.com
4728          */
4729         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4730                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4731                 pbn_sbsxrsio },
4732         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4733                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4734                 pbn_sbsxrsio },
4735         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4736                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4737                 pbn_sbsxrsio },
4738         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4739                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4740                 pbn_sbsxrsio },
4741 
4742         /*
4743          * Digitan DS560-558, from jimd@esoft.com
4744          */
4745         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4746                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4747                 pbn_b1_1_115200 },
4748 
4749         /*
4750          * Titan Electronic cards
4751          *  The 400L and 800L have a custom setup quirk.
4752          */
4753         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4754                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4755                 pbn_b0_1_921600 },
4756         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4757                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4758                 pbn_b0_2_921600 },
4759         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4760                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4761                 pbn_b0_4_921600 },
4762         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4763                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4764                 pbn_b0_4_921600 },
4765         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4766                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4767                 pbn_b1_1_921600 },
4768         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4769                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4770                 pbn_b1_bt_2_921600 },
4771         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4772                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773                 pbn_b0_bt_4_921600 },
4774         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4775                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4776                 pbn_b0_bt_8_921600 },
4777         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4778                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779                 pbn_b4_bt_2_921600 },
4780         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4781                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4782                 pbn_b4_bt_4_921600 },
4783         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4784                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4785                 pbn_b4_bt_8_921600 },
4786         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4787                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4788                 pbn_b0_4_921600 },
4789         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4790                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4791                 pbn_b0_4_921600 },
4792         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4793                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4794                 pbn_b0_4_921600 },
4795         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4796                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4797                 pbn_oxsemi_1_4000000 },
4798         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4799                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4800                 pbn_oxsemi_2_4000000 },
4801         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4802                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4803                 pbn_oxsemi_4_4000000 },
4804         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4805                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4806                 pbn_oxsemi_8_4000000 },
4807         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4808                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4809                 pbn_oxsemi_2_4000000 },
4810         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4811                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4812                 pbn_oxsemi_2_4000000 },
4813         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4814                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4815                 pbn_b0_bt_2_921600 },
4816         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4817                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4818                 pbn_b0_4_921600 },
4819         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4820                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4821                 pbn_b0_4_921600 },
4822         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4823                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4824                 pbn_b0_4_921600 },
4825         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4826                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4827                 pbn_b0_4_921600 },
4828 
4829         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4830                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4831                 pbn_b2_1_460800 },
4832         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4833                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4834                 pbn_b2_1_460800 },
4835         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4836                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4837                 pbn_b2_1_460800 },
4838         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4839                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4840                 pbn_b2_bt_2_921600 },
4841         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4842                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4843                 pbn_b2_bt_2_921600 },
4844         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4845                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4846                 pbn_b2_bt_2_921600 },
4847         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4848                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4849                 pbn_b2_bt_4_921600 },
4850         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4851                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4852                 pbn_b2_bt_4_921600 },
4853         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4854                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4855                 pbn_b2_bt_4_921600 },
4856         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4857                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4858                 pbn_b0_1_921600 },
4859         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4860                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4861                 pbn_b0_1_921600 },
4862         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4863                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4864                 pbn_b0_1_921600 },
4865         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4866                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4867                 pbn_b0_bt_2_921600 },
4868         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4869                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4870                 pbn_b0_bt_2_921600 },
4871         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4872                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4873                 pbn_b0_bt_2_921600 },
4874         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4875                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4876                 pbn_b0_bt_4_921600 },
4877         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4878                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4879                 pbn_b0_bt_4_921600 },
4880         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4881                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4882                 pbn_b0_bt_4_921600 },
4883         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4884                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4885                 pbn_b0_bt_8_921600 },
4886         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4887                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4888                 pbn_b0_bt_8_921600 },
4889         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4890                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891                 pbn_b0_bt_8_921600 },
4892 
4893         /*
4894          * Computone devices submitted by Doug McNash dmcnash@computone.com
4895          */
4896         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4897                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4898                 0, 0, pbn_computone_4 },
4899         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4900                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4901                 0, 0, pbn_computone_8 },
4902         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4903                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4904                 0, 0, pbn_computone_6 },
4905 
4906         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4907                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908                 pbn_oxsemi },
4909         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4910                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4911                 pbn_b0_bt_1_921600 },
4912 
4913         /*
4914          * SUNIX (TIMEDIA)
4915          */
4916         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4917                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4918                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4919                 pbn_b0_bt_1_921600 },
4920 
4921         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4922                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4923                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4924                 pbn_b0_bt_1_921600 },
4925 
4926         /*
4927          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4928          */
4929         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4930                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4931                 pbn_b0_bt_8_115200 },
4932         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4933                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4934                 pbn_b0_bt_8_115200 },
4935 
4936         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4937                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4938                 pbn_b0_bt_2_115200 },
4939         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4940                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4941                 pbn_b0_bt_2_115200 },
4942         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4943                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944                 pbn_b0_bt_2_115200 },
4945         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4946                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4947                 pbn_b0_bt_2_115200 },
4948         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4949                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4950                 pbn_b0_bt_2_115200 },
4951         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4952                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4953                 pbn_b0_bt_4_460800 },
4954         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4955                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4956                 pbn_b0_bt_4_460800 },
4957         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4958                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4959                 pbn_b0_bt_2_460800 },
4960         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4961                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4962                 pbn_b0_bt_2_460800 },
4963         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4964                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4965                 pbn_b0_bt_2_460800 },
4966         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4967                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4968                 pbn_b0_bt_1_115200 },
4969         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4970                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4971                 pbn_b0_bt_1_460800 },
4972 
4973         /*
4974          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4975          * Cards are identified by their subsystem vendor IDs, which
4976          * (in hex) match the model number.
4977          *
4978          * Note that JC140x are RS422/485 cards which require ox950
4979          * ACR = 0x10, and as such are not currently fully supported.
4980          */
4981         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4982                 0x1204, 0x0004, 0, 0,
4983                 pbn_b0_4_921600 },
4984         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4985                 0x1208, 0x0004, 0, 0,
4986                 pbn_b0_4_921600 },
4987 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4988                 0x1402, 0x0002, 0, 0,
4989                 pbn_b0_2_921600 }, */
4990 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4991                 0x1404, 0x0004, 0, 0,
4992                 pbn_b0_4_921600 }, */
4993         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4994                 0x1208, 0x0004, 0, 0,
4995                 pbn_b0_4_921600 },
4996 
4997         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4998                 0x1204, 0x0004, 0, 0,
4999                 pbn_b0_4_921600 },
5000         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5001                 0x1208, 0x0004, 0, 0,
5002                 pbn_b0_4_921600 },
5003         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5004                 0x1208, 0x0004, 0, 0,
5005                 pbn_b0_4_921600 },
5006         /*
5007          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5008          */
5009         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5010                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5011                 pbn_b1_1_1382400 },
5012 
5013         /*
5014          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5015          */
5016         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5017                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5018                 pbn_b1_1_1382400 },
5019 
5020         /*
5021          * RAStel 2 port modem, gerg@moreton.com.au
5022          */
5023         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5024                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5025                 pbn_b2_bt_2_115200 },
5026 
5027         /*
5028          * EKF addition for i960 Boards form EKF with serial port
5029          */
5030         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5031                 0xE4BF, PCI_ANY_ID, 0, 0,
5032                 pbn_intel_i960 },
5033 
5034         /*
5035          * Xircom Cardbus/Ethernet combos
5036          */
5037         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5038                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5039                 pbn_b0_1_115200 },
5040         /*
5041          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5042          */
5043         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5044                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5045                 pbn_b0_1_115200 },
5046 
5047         /*
5048          * Untested PCI modems, sent in from various folks...
5049          */
5050 
5051         /*
5052          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5053          */
5054         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
5055                 0x1048, 0x1500, 0, 0,
5056                 pbn_b1_1_115200 },
5057 
5058         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5059                 0xFF00, 0, 0, 0,
5060                 pbn_sgi_ioc3 },
5061 
5062         /*
5063          * HP Diva card
5064          */
5065         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5066                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5067                 pbn_b1_1_115200 },
5068         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5069                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5070                 pbn_b0_5_115200 },
5071         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5072                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5073                 pbn_b2_1_115200 },
5074 
5075         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5076                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5077                 pbn_b3_2_115200 },
5078         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5079                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5080                 pbn_b3_4_115200 },
5081         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5082                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5083                 pbn_b3_8_115200 },
5084 
5085         /*
5086          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5087          */
5088         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5089                 PCI_ANY_ID, PCI_ANY_ID,
5090                 0,
5091                 0, pbn_exar_XR17C152 },
5092         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5093                 PCI_ANY_ID, PCI_ANY_ID,
5094                 0,
5095                 0, pbn_exar_XR17C154 },
5096         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5097                 PCI_ANY_ID, PCI_ANY_ID,
5098                 0,
5099                 0, pbn_exar_XR17C158 },
5100         /*
5101          * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5102          */
5103         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5104                 PCI_ANY_ID, PCI_ANY_ID,
5105                 0,
5106                 0, pbn_exar_XR17V352 },
5107         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5108                 PCI_ANY_ID, PCI_ANY_ID,
5109                 0,
5110                 0, pbn_exar_XR17V354 },
5111         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5112                 PCI_ANY_ID, PCI_ANY_ID,
5113                 0,
5114                 0, pbn_exar_XR17V358 },
5115         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5116                 PCI_ANY_ID, PCI_ANY_ID,
5117                 0,
5118                 0, pbn_exar_XR17V8358 },
5119         /*
5120          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5121          */
5122         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5123                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5124                 pbn_b0_1_115200 },
5125         /*
5126          * ITE
5127          */
5128         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5129                 PCI_ANY_ID, PCI_ANY_ID,
5130                 0, 0,
5131                 pbn_b1_bt_1_115200 },
5132 
5133         /*
5134          * IntaShield IS-200
5135          */
5136         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5137                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
5138                 pbn_b2_2_115200 },
5139         /*
5140          * IntaShield IS-400
5141          */
5142         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5143                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
5144                 pbn_b2_4_115200 },
5145         /*
5146          * Perle PCI-RAS cards
5147          */
5148         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5149                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5150                 0, 0, pbn_b2_4_921600 },
5151         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5152                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5153                 0, 0, pbn_b2_8_921600 },
5154 
5155         /*
5156          * Mainpine series cards: Fairly standard layout but fools
5157          * parts of the autodetect in some cases and uses otherwise
5158          * unmatched communications subclasses in the PCI Express case
5159          */
5160 
5161         {       /* RockForceDUO */
5162                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5163                 PCI_VENDOR_ID_MAINPINE, 0x0200,
5164                 0, 0, pbn_b0_2_115200 },
5165         {       /* RockForceQUATRO */
5166                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5167                 PCI_VENDOR_ID_MAINPINE, 0x0300,
5168                 0, 0, pbn_b0_4_115200 },
5169         {       /* RockForceDUO+ */
5170                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5171                 PCI_VENDOR_ID_MAINPINE, 0x0400,
5172                 0, 0, pbn_b0_2_115200 },
5173         {       /* RockForceQUATRO+ */
5174                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5175                 PCI_VENDOR_ID_MAINPINE, 0x0500,
5176                 0, 0, pbn_b0_4_115200 },
5177         {       /* RockForce+ */
5178                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5179                 PCI_VENDOR_ID_MAINPINE, 0x0600,
5180                 0, 0, pbn_b0_2_115200 },
5181         {       /* RockForce+ */
5182                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5183                 PCI_VENDOR_ID_MAINPINE, 0x0700,
5184                 0, 0, pbn_b0_4_115200 },
5185         {       /* RockForceOCTO+ */
5186                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5187                 PCI_VENDOR_ID_MAINPINE, 0x0800,
5188                 0, 0, pbn_b0_8_115200 },
5189         {       /* RockForceDUO+ */
5190                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5191                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5192                 0, 0, pbn_b0_2_115200 },
5193         {       /* RockForceQUARTRO+ */
5194                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5195                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5196                 0, 0, pbn_b0_4_115200 },
5197         {       /* RockForceOCTO+ */
5198                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5199                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5200                 0, 0, pbn_b0_8_115200 },
5201         {       /* RockForceD1 */
5202                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5203                 PCI_VENDOR_ID_MAINPINE, 0x2000,
5204                 0, 0, pbn_b0_1_115200 },
5205         {       /* RockForceF1 */
5206                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5207                 PCI_VENDOR_ID_MAINPINE, 0x2100,
5208                 0, 0, pbn_b0_1_115200 },
5209         {       /* RockForceD2 */
5210                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5211                 PCI_VENDOR_ID_MAINPINE, 0x2200,
5212                 0, 0, pbn_b0_2_115200 },
5213         {       /* RockForceF2 */
5214                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5215                 PCI_VENDOR_ID_MAINPINE, 0x2300,
5216                 0, 0, pbn_b0_2_115200 },
5217         {       /* RockForceD4 */
5218                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5219                 PCI_VENDOR_ID_MAINPINE, 0x2400,
5220                 0, 0, pbn_b0_4_115200 },
5221         {       /* RockForceF4 */
5222                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5223                 PCI_VENDOR_ID_MAINPINE, 0x2500,
5224                 0, 0, pbn_b0_4_115200 },
5225         {       /* RockForceD8 */
5226                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5227                 PCI_VENDOR_ID_MAINPINE, 0x2600,
5228                 0, 0, pbn_b0_8_115200 },
5229         {       /* RockForceF8 */
5230                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5231                 PCI_VENDOR_ID_MAINPINE, 0x2700,
5232                 0, 0, pbn_b0_8_115200 },
5233         {       /* IQ Express D1 */
5234                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5235                 PCI_VENDOR_ID_MAINPINE, 0x3000,
5236                 0, 0, pbn_b0_1_115200 },
5237         {       /* IQ Express F1 */
5238                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5239                 PCI_VENDOR_ID_MAINPINE, 0x3100,
5240                 0, 0, pbn_b0_1_115200 },
5241         {       /* IQ Express D2 */
5242                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5243                 PCI_VENDOR_ID_MAINPINE, 0x3200,
5244                 0, 0, pbn_b0_2_115200 },
5245         {       /* IQ Express F2 */
5246                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5247                 PCI_VENDOR_ID_MAINPINE, 0x3300,
5248                 0, 0, pbn_b0_2_115200 },
5249         {       /* IQ Express D4 */
5250                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5251                 PCI_VENDOR_ID_MAINPINE, 0x3400,
5252                 0, 0, pbn_b0_4_115200 },
5253         {       /* IQ Express F4 */
5254                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5255                 PCI_VENDOR_ID_MAINPINE, 0x3500,
5256                 0, 0, pbn_b0_4_115200 },
5257         {       /* IQ Express D8 */
5258                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5259                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5260                 0, 0, pbn_b0_8_115200 },
5261         {       /* IQ Express F8 */
5262                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5263                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5264                 0, 0, pbn_b0_8_115200 },
5265 
5266 
5267         /*
5268          * PA Semi PA6T-1682M on-chip UART
5269          */
5270         {       PCI_VENDOR_ID_PASEMI, 0xa004,
5271                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5272                 pbn_pasemi_1682M },
5273 
5274         /*
5275          * National Instruments
5276          */
5277         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5278                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5279                 pbn_b1_16_115200 },
5280         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5281                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5282                 pbn_b1_8_115200 },
5283         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5284                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5285                 pbn_b1_bt_4_115200 },
5286         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5287                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5288                 pbn_b1_bt_2_115200 },
5289         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5290                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5291                 pbn_b1_bt_4_115200 },
5292         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5293                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5294                 pbn_b1_bt_2_115200 },
5295         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5296                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5297                 pbn_b1_16_115200 },
5298         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5299                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5300                 pbn_b1_8_115200 },
5301         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5302                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5303                 pbn_b1_bt_4_115200 },
5304         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5305                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5306                 pbn_b1_bt_2_115200 },
5307         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5308                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5309                 pbn_b1_bt_4_115200 },
5310         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5311                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5312                 pbn_b1_bt_2_115200 },
5313         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5314                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5315                 pbn_ni8430_2 },
5316         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5317                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5318                 pbn_ni8430_2 },
5319         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5320                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5321                 pbn_ni8430_4 },
5322         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5323                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5324                 pbn_ni8430_4 },
5325         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5326                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5327                 pbn_ni8430_8 },
5328         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5329                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5330                 pbn_ni8430_8 },
5331         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5332                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5333                 pbn_ni8430_16 },
5334         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5335                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5336                 pbn_ni8430_16 },
5337         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5338                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5339                 pbn_ni8430_2 },
5340         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5341                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5342                 pbn_ni8430_2 },
5343         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5344                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5345                 pbn_ni8430_4 },
5346         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5347                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5348                 pbn_ni8430_4 },
5349 
5350         /*
5351         * ADDI-DATA GmbH communication cards <info@addi-data.com>
5352         */
5353         {       PCI_VENDOR_ID_ADDIDATA,
5354                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5355                 PCI_ANY_ID,
5356                 PCI_ANY_ID,
5357                 0,
5358                 0,
5359                 pbn_b0_4_115200 },
5360 
5361         {       PCI_VENDOR_ID_ADDIDATA,
5362                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5363                 PCI_ANY_ID,
5364                 PCI_ANY_ID,
5365                 0,
5366                 0,
5367                 pbn_b0_2_115200 },
5368 
5369         {       PCI_VENDOR_ID_ADDIDATA,
5370                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5371                 PCI_ANY_ID,
5372                 PCI_ANY_ID,
5373                 0,
5374                 0,
5375                 pbn_b0_1_115200 },
5376 
5377         {       PCI_VENDOR_ID_AMCC,
5378                 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5379                 PCI_ANY_ID,
5380                 PCI_ANY_ID,
5381                 0,
5382                 0,
5383                 pbn_b1_8_115200 },
5384 
5385         {       PCI_VENDOR_ID_ADDIDATA,
5386                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5387                 PCI_ANY_ID,
5388                 PCI_ANY_ID,
5389                 0,
5390                 0,
5391                 pbn_b0_4_115200 },
5392 
5393         {       PCI_VENDOR_ID_ADDIDATA,
5394                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5395                 PCI_ANY_ID,
5396                 PCI_ANY_ID,
5397                 0,
5398                 0,
5399                 pbn_b0_2_115200 },
5400 
5401         {       PCI_VENDOR_ID_ADDIDATA,
5402                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5403                 PCI_ANY_ID,
5404                 PCI_ANY_ID,
5405                 0,
5406                 0,
5407                 pbn_b0_1_115200 },
5408 
5409         {       PCI_VENDOR_ID_ADDIDATA,
5410                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5411                 PCI_ANY_ID,
5412                 PCI_ANY_ID,
5413                 0,
5414                 0,
5415                 pbn_b0_4_115200 },
5416 
5417         {       PCI_VENDOR_ID_ADDIDATA,
5418                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5419                 PCI_ANY_ID,
5420                 PCI_ANY_ID,
5421                 0,
5422                 0,
5423                 pbn_b0_2_115200 },
5424 
5425         {       PCI_VENDOR_ID_ADDIDATA,
5426                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5427                 PCI_ANY_ID,
5428                 PCI_ANY_ID,
5429                 0,
5430                 0,
5431                 pbn_b0_1_115200 },
5432 
5433         {       PCI_VENDOR_ID_ADDIDATA,
5434                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5435                 PCI_ANY_ID,
5436                 PCI_ANY_ID,
5437                 0,
5438                 0,
5439                 pbn_b0_8_115200 },
5440 
5441         {       PCI_VENDOR_ID_ADDIDATA,
5442                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5443                 PCI_ANY_ID,
5444                 PCI_ANY_ID,
5445                 0,
5446                 0,
5447                 pbn_ADDIDATA_PCIe_4_3906250 },
5448 
5449         {       PCI_VENDOR_ID_ADDIDATA,
5450                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5451                 PCI_ANY_ID,
5452                 PCI_ANY_ID,
5453                 0,
5454                 0,
5455                 pbn_ADDIDATA_PCIe_2_3906250 },
5456 
5457         {       PCI_VENDOR_ID_ADDIDATA,
5458                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5459                 PCI_ANY_ID,
5460                 PCI_ANY_ID,
5461                 0,
5462                 0,
5463                 pbn_ADDIDATA_PCIe_1_3906250 },
5464 
5465         {       PCI_VENDOR_ID_ADDIDATA,
5466                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5467                 PCI_ANY_ID,
5468                 PCI_ANY_ID,
5469                 0,
5470                 0,
5471                 pbn_ADDIDATA_PCIe_8_3906250 },
5472 
5473         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5474                 PCI_VENDOR_ID_IBM, 0x0299,
5475                 0, 0, pbn_b0_bt_2_115200 },
5476 
5477         /*
5478          * other NetMos 9835 devices are most likely handled by the
5479          * parport_serial driver, check drivers/parport/parport_serial.c
5480          * before adding them here.
5481          */
5482 
5483         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5484                 0xA000, 0x1000,
5485                 0, 0, pbn_b0_1_115200 },
5486 
5487         /* the 9901 is a rebranded 9912 */
5488         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5489                 0xA000, 0x1000,
5490                 0, 0, pbn_b0_1_115200 },
5491 
5492         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5493                 0xA000, 0x1000,
5494                 0, 0, pbn_b0_1_115200 },
5495 
5496         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5497                 0xA000, 0x1000,
5498                 0, 0, pbn_b0_1_115200 },
5499 
5500         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5501                 0xA000, 0x1000,
5502                 0, 0, pbn_b0_1_115200 },
5503 
5504         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5505                 0xA000, 0x3002,
5506                 0, 0, pbn_NETMOS9900_2s_115200 },
5507 
5508         /*
5509          * Best Connectivity and Rosewill PCI Multi I/O cards
5510          */
5511 
5512         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5513                 0xA000, 0x1000,
5514                 0, 0, pbn_b0_1_115200 },
5515 
5516         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5517                 0xA000, 0x3002,
5518                 0, 0, pbn_b0_bt_2_115200 },
5519 
5520         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5521                 0xA000, 0x3004,
5522                 0, 0, pbn_b0_bt_4_115200 },
5523         /* Intel CE4100 */
5524         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5525                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5526                 pbn_ce4100_1_115200 },
5527         /* Intel BayTrail */
5528         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5529                 PCI_ANY_ID,  PCI_ANY_ID,
5530                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5531                 pbn_byt },
5532         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5533                 PCI_ANY_ID,  PCI_ANY_ID,
5534                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5535                 pbn_byt },
5536         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5537                 PCI_ANY_ID,  PCI_ANY_ID,
5538                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5539                 pbn_byt },
5540         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5541                 PCI_ANY_ID,  PCI_ANY_ID,
5542                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5543                 pbn_byt },
5544 
5545         /*
5546          * Intel Penwell
5547          */
5548         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART1,
5549                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5550                 pbn_pnw},
5551         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART2,
5552                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5553                 pbn_pnw},
5554         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART3,
5555                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5556                 pbn_pnw},
5557 
5558         /*
5559          * Intel Tangier
5560          */
5561         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TNG_UART,
5562                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5563                 pbn_tng},
5564 
5565         /*
5566          * Intel Quark x1000
5567          */
5568         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5569                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5570                 pbn_qrk },
5571         /*
5572          * Cronyx Omega PCI
5573          */
5574         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5575                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5576                 pbn_omegapci },
5577 
5578         /*
5579          * Broadcom TruManage
5580          */
5581         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5582                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5583                 pbn_brcm_trumanage },
5584 
5585         /*
5586          * AgeStar as-prs2-009
5587          */
5588         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5589                 PCI_ANY_ID, PCI_ANY_ID,
5590                 0, 0, pbn_b0_bt_2_115200 },
5591 
5592         /*
5593          * WCH CH353 series devices: The 2S1P is handled by parport_serial
5594          * so not listed here.
5595          */
5596         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5597                 PCI_ANY_ID, PCI_ANY_ID,
5598                 0, 0, pbn_b0_bt_4_115200 },
5599 
5600         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5601                 PCI_ANY_ID, PCI_ANY_ID,
5602                 0, 0, pbn_b0_bt_2_115200 },
5603 
5604         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5605                 PCI_ANY_ID, PCI_ANY_ID,
5606                 0, 0, pbn_wch384_4 },
5607 
5608         /*
5609          * Commtech, Inc. Fastcom adapters
5610          */
5611         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5612                 PCI_ANY_ID, PCI_ANY_ID,
5613                 0,
5614                 0, pbn_b0_2_1152000_200 },
5615         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5616                 PCI_ANY_ID, PCI_ANY_ID,
5617                 0,
5618                 0, pbn_b0_4_1152000_200 },
5619         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5620                 PCI_ANY_ID, PCI_ANY_ID,
5621                 0,
5622                 0, pbn_b0_4_1152000_200 },
5623         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5624                 PCI_ANY_ID, PCI_ANY_ID,
5625                 0,
5626                 0, pbn_b0_8_1152000_200 },
5627         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5628                 PCI_ANY_ID, PCI_ANY_ID,
5629                 0,
5630                 0, pbn_exar_XR17V352 },
5631         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5632                 PCI_ANY_ID, PCI_ANY_ID,
5633                 0,
5634                 0, pbn_exar_XR17V354 },
5635         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5636                 PCI_ANY_ID, PCI_ANY_ID,
5637                 0,
5638                 0, pbn_exar_XR17V358 },
5639 
5640         /* Fintek PCI serial cards */
5641         { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5642         { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5643         { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5644 
5645         /*
5646          * These entries match devices with class COMMUNICATION_SERIAL,
5647          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5648          */
5649         {       PCI_ANY_ID, PCI_ANY_ID,
5650                 PCI_ANY_ID, PCI_ANY_ID,
5651                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5652                 0xffff00, pbn_default },
5653         {       PCI_ANY_ID, PCI_ANY_ID,
5654                 PCI_ANY_ID, PCI_ANY_ID,
5655                 PCI_CLASS_COMMUNICATION_MODEM << 8,
5656                 0xffff00, pbn_default },
5657         {       PCI_ANY_ID, PCI_ANY_ID,
5658                 PCI_ANY_ID, PCI_ANY_ID,
5659                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5660                 0xffff00, pbn_default },
5661         { 0, }
5662 };
5663 
5664 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5665                                                 pci_channel_state_t state)
5666 {
5667         struct serial_private *priv = pci_get_drvdata(dev);
5668 
5669         if (state == pci_channel_io_perm_failure)
5670                 return PCI_ERS_RESULT_DISCONNECT;
5671 
5672         if (priv)
5673                 pciserial_suspend_ports(priv);
5674 
5675         pci_disable_device(dev);
5676 
5677         return PCI_ERS_RESULT_NEED_RESET;
5678 }
5679 
5680 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5681 {
5682         int rc;
5683 
5684         rc = pci_enable_device(dev);
5685 
5686         if (rc)
5687                 return PCI_ERS_RESULT_DISCONNECT;
5688 
5689         pci_restore_state(dev);
5690         pci_save_state(dev);
5691 
5692         return PCI_ERS_RESULT_RECOVERED;
5693 }
5694 
5695 static void serial8250_io_resume(struct pci_dev *dev)
5696 {
5697         struct serial_private *priv = pci_get_drvdata(dev);
5698 
5699         if (priv)
5700                 pciserial_resume_ports(priv);
5701 }
5702 
5703 static const struct pci_error_handlers serial8250_err_handler = {
5704         .error_detected = serial8250_io_error_detected,
5705         .slot_reset = serial8250_io_slot_reset,
5706         .resume = serial8250_io_resume,
5707 };
5708 
5709 static struct pci_driver serial_pci_driver = {
5710         .name           = "serial",
5711         .probe          = pciserial_init_one,
5712         .remove         = pciserial_remove_one,
5713         .driver         = {
5714                 .pm     = &pciserial_pm_ops,
5715         },
5716         .id_table       = serial_pci_tbl,
5717         .err_handler    = &serial8250_err_handler,
5718 };
5719 
5720 module_pci_driver(serial_pci_driver);
5721 
5722 MODULE_LICENSE("GPL");
5723 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5724 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
5725 

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