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Linux/drivers/tty/serial/8250/8250_pci.c

  1 /*
  2  *  Probe module for 8250/16550-type PCI serial ports.
  3  *
  4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  5  *
  6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License.
 11  */
 12 #undef DEBUG
 13 #include <linux/module.h>
 14 #include <linux/pci.h>
 15 #include <linux/string.h>
 16 #include <linux/kernel.h>
 17 #include <linux/slab.h>
 18 #include <linux/delay.h>
 19 #include <linux/tty.h>
 20 #include <linux/serial_reg.h>
 21 #include <linux/serial_core.h>
 22 #include <linux/8250_pci.h>
 23 #include <linux/bitops.h>
 24 #include <linux/rational.h>
 25 
 26 #include <asm/byteorder.h>
 27 #include <asm/io.h>
 28 
 29 #include <linux/dmaengine.h>
 30 #include <linux/platform_data/dma-dw.h>
 31 
 32 #include "8250.h"
 33 
 34 /*
 35  * init function returns:
 36  *  > 0 - number of ports
 37  *  = 0 - use board->num_ports
 38  *  < 0 - error
 39  */
 40 struct pci_serial_quirk {
 41         u32     vendor;
 42         u32     device;
 43         u32     subvendor;
 44         u32     subdevice;
 45         int     (*probe)(struct pci_dev *dev);
 46         int     (*init)(struct pci_dev *dev);
 47         int     (*setup)(struct serial_private *,
 48                          const struct pciserial_board *,
 49                          struct uart_8250_port *, int);
 50         void    (*exit)(struct pci_dev *dev);
 51 };
 52 
 53 #define PCI_NUM_BAR_RESOURCES   6
 54 
 55 struct serial_private {
 56         struct pci_dev          *dev;
 57         unsigned int            nr;
 58         struct pci_serial_quirk *quirk;
 59         int                     line[0];
 60 };
 61 
 62 static int pci_default_setup(struct serial_private*,
 63           const struct pciserial_board*, struct uart_8250_port *, int);
 64 
 65 static void moan_device(const char *str, struct pci_dev *dev)
 66 {
 67         dev_err(&dev->dev,
 68                "%s: %s\n"
 69                "Please send the output of lspci -vv, this\n"
 70                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
 71                "manufacturer and name of serial board or\n"
 72                "modem board to <linux-serial@vger.kernel.org>.\n",
 73                pci_name(dev), str, dev->vendor, dev->device,
 74                dev->subsystem_vendor, dev->subsystem_device);
 75 }
 76 
 77 static int
 78 setup_port(struct serial_private *priv, struct uart_8250_port *port,
 79            int bar, int offset, int regshift)
 80 {
 81         struct pci_dev *dev = priv->dev;
 82 
 83         if (bar >= PCI_NUM_BAR_RESOURCES)
 84                 return -EINVAL;
 85 
 86         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
 87                 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
 88                         return -ENOMEM;
 89 
 90                 port->port.iotype = UPIO_MEM;
 91                 port->port.iobase = 0;
 92                 port->port.mapbase = pci_resource_start(dev, bar) + offset;
 93                 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
 94                 port->port.regshift = regshift;
 95         } else {
 96                 port->port.iotype = UPIO_PORT;
 97                 port->port.iobase = pci_resource_start(dev, bar) + offset;
 98                 port->port.mapbase = 0;
 99                 port->port.membase = NULL;
100                 port->port.regshift = 0;
101         }
102         return 0;
103 }
104 
105 /*
106  * ADDI-DATA GmbH communication cards <info@addi-data.com>
107  */
108 static int addidata_apci7800_setup(struct serial_private *priv,
109                                 const struct pciserial_board *board,
110                                 struct uart_8250_port *port, int idx)
111 {
112         unsigned int bar = 0, offset = board->first_offset;
113         bar = FL_GET_BASE(board->flags);
114 
115         if (idx < 2) {
116                 offset += idx * board->uart_offset;
117         } else if ((idx >= 2) && (idx < 4)) {
118                 bar += 1;
119                 offset += ((idx - 2) * board->uart_offset);
120         } else if ((idx >= 4) && (idx < 6)) {
121                 bar += 2;
122                 offset += ((idx - 4) * board->uart_offset);
123         } else if (idx >= 6) {
124                 bar += 3;
125                 offset += ((idx - 6) * board->uart_offset);
126         }
127 
128         return setup_port(priv, port, bar, offset, board->reg_shift);
129 }
130 
131 /*
132  * AFAVLAB uses a different mixture of BARs and offsets
133  * Not that ugly ;) -- HW
134  */
135 static int
136 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
137               struct uart_8250_port *port, int idx)
138 {
139         unsigned int bar, offset = board->first_offset;
140 
141         bar = FL_GET_BASE(board->flags);
142         if (idx < 4)
143                 bar += idx;
144         else {
145                 bar = 4;
146                 offset += (idx - 4) * board->uart_offset;
147         }
148 
149         return setup_port(priv, port, bar, offset, board->reg_shift);
150 }
151 
152 /*
153  * HP's Remote Management Console.  The Diva chip came in several
154  * different versions.  N-class, L2000 and A500 have two Diva chips, each
155  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
156  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
157  * one Diva chip, but it has been expanded to 5 UARTs.
158  */
159 static int pci_hp_diva_init(struct pci_dev *dev)
160 {
161         int rc = 0;
162 
163         switch (dev->subsystem_device) {
164         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
165         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
166         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
167         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
168                 rc = 3;
169                 break;
170         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
171                 rc = 2;
172                 break;
173         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
174                 rc = 4;
175                 break;
176         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
177         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
178                 rc = 1;
179                 break;
180         }
181 
182         return rc;
183 }
184 
185 /*
186  * HP's Diva chip puts the 4th/5th serial port further out, and
187  * some serial ports are supposed to be hidden on certain models.
188  */
189 static int
190 pci_hp_diva_setup(struct serial_private *priv,
191                 const struct pciserial_board *board,
192                 struct uart_8250_port *port, int idx)
193 {
194         unsigned int offset = board->first_offset;
195         unsigned int bar = FL_GET_BASE(board->flags);
196 
197         switch (priv->dev->subsystem_device) {
198         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
199                 if (idx == 3)
200                         idx++;
201                 break;
202         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
203                 if (idx > 0)
204                         idx++;
205                 if (idx > 2)
206                         idx++;
207                 break;
208         }
209         if (idx > 2)
210                 offset = 0x18;
211 
212         offset += idx * board->uart_offset;
213 
214         return setup_port(priv, port, bar, offset, board->reg_shift);
215 }
216 
217 /*
218  * Added for EKF Intel i960 serial boards
219  */
220 static int pci_inteli960ni_init(struct pci_dev *dev)
221 {
222         u32 oldval;
223 
224         if (!(dev->subsystem_device & 0x1000))
225                 return -ENODEV;
226 
227         /* is firmware started? */
228         pci_read_config_dword(dev, 0x44, &oldval);
229         if (oldval == 0x00001000L) { /* RESET value */
230                 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
231                 return -ENODEV;
232         }
233         return 0;
234 }
235 
236 /*
237  * Some PCI serial cards using the PLX 9050 PCI interface chip require
238  * that the card interrupt be explicitly enabled or disabled.  This
239  * seems to be mainly needed on card using the PLX which also use I/O
240  * mapped memory.
241  */
242 static int pci_plx9050_init(struct pci_dev *dev)
243 {
244         u8 irq_config;
245         void __iomem *p;
246 
247         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
248                 moan_device("no memory in bar 0", dev);
249                 return 0;
250         }
251 
252         irq_config = 0x41;
253         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
254             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
255                 irq_config = 0x43;
256 
257         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
258             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
259                 /*
260                  * As the megawolf cards have the int pins active
261                  * high, and have 2 UART chips, both ints must be
262                  * enabled on the 9050. Also, the UARTS are set in
263                  * 16450 mode by default, so we have to enable the
264                  * 16C950 'enhanced' mode so that we can use the
265                  * deep FIFOs
266                  */
267                 irq_config = 0x5b;
268         /*
269          * enable/disable interrupts
270          */
271         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
272         if (p == NULL)
273                 return -ENOMEM;
274         writel(irq_config, p + 0x4c);
275 
276         /*
277          * Read the register back to ensure that it took effect.
278          */
279         readl(p + 0x4c);
280         iounmap(p);
281 
282         return 0;
283 }
284 
285 static void pci_plx9050_exit(struct pci_dev *dev)
286 {
287         u8 __iomem *p;
288 
289         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
290                 return;
291 
292         /*
293          * disable interrupts
294          */
295         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
296         if (p != NULL) {
297                 writel(0, p + 0x4c);
298 
299                 /*
300                  * Read the register back to ensure that it took effect.
301                  */
302                 readl(p + 0x4c);
303                 iounmap(p);
304         }
305 }
306 
307 #define NI8420_INT_ENABLE_REG   0x38
308 #define NI8420_INT_ENABLE_BIT   0x2000
309 
310 static void pci_ni8420_exit(struct pci_dev *dev)
311 {
312         void __iomem *p;
313         unsigned int bar = 0;
314 
315         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
316                 moan_device("no memory in bar", dev);
317                 return;
318         }
319 
320         p = pci_ioremap_bar(dev, bar);
321         if (p == NULL)
322                 return;
323 
324         /* Disable the CPU Interrupt */
325         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
326                p + NI8420_INT_ENABLE_REG);
327         iounmap(p);
328 }
329 
330 
331 /* MITE registers */
332 #define MITE_IOWBSR1    0xc4
333 #define MITE_IOWCR1     0xf4
334 #define MITE_LCIMR1     0x08
335 #define MITE_LCIMR2     0x10
336 
337 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
338 
339 static void pci_ni8430_exit(struct pci_dev *dev)
340 {
341         void __iomem *p;
342         unsigned int bar = 0;
343 
344         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
345                 moan_device("no memory in bar", dev);
346                 return;
347         }
348 
349         p = pci_ioremap_bar(dev, bar);
350         if (p == NULL)
351                 return;
352 
353         /* Disable the CPU Interrupt */
354         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
355         iounmap(p);
356 }
357 
358 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
359 static int
360 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
361                 struct uart_8250_port *port, int idx)
362 {
363         unsigned int bar, offset = board->first_offset;
364 
365         bar = 0;
366 
367         if (idx < 4) {
368                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
369                 offset += idx * board->uart_offset;
370         } else if (idx < 8) {
371                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
372                 offset += idx * board->uart_offset + 0xC00;
373         } else /* we have only 8 ports on PMC-OCTALPRO */
374                 return 1;
375 
376         return setup_port(priv, port, bar, offset, board->reg_shift);
377 }
378 
379 /*
380 * This does initialization for PMC OCTALPRO cards:
381 * maps the device memory, resets the UARTs (needed, bc
382 * if the module is removed and inserted again, the card
383 * is in the sleep mode) and enables global interrupt.
384 */
385 
386 /* global control register offset for SBS PMC-OctalPro */
387 #define OCT_REG_CR_OFF          0x500
388 
389 static int sbs_init(struct pci_dev *dev)
390 {
391         u8 __iomem *p;
392 
393         p = pci_ioremap_bar(dev, 0);
394 
395         if (p == NULL)
396                 return -ENOMEM;
397         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
398         writeb(0x10, p + OCT_REG_CR_OFF);
399         udelay(50);
400         writeb(0x0, p + OCT_REG_CR_OFF);
401 
402         /* Set bit-2 (INTENABLE) of Control Register */
403         writeb(0x4, p + OCT_REG_CR_OFF);
404         iounmap(p);
405 
406         return 0;
407 }
408 
409 /*
410  * Disables the global interrupt of PMC-OctalPro
411  */
412 
413 static void sbs_exit(struct pci_dev *dev)
414 {
415         u8 __iomem *p;
416 
417         p = pci_ioremap_bar(dev, 0);
418         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
419         if (p != NULL)
420                 writeb(0, p + OCT_REG_CR_OFF);
421         iounmap(p);
422 }
423 
424 /*
425  * SIIG serial cards have an PCI interface chip which also controls
426  * the UART clocking frequency. Each UART can be clocked independently
427  * (except cards equipped with 4 UARTs) and initial clocking settings
428  * are stored in the EEPROM chip. It can cause problems because this
429  * version of serial driver doesn't support differently clocked UART's
430  * on single PCI card. To prevent this, initialization functions set
431  * high frequency clocking for all UART's on given card. It is safe (I
432  * hope) because it doesn't touch EEPROM settings to prevent conflicts
433  * with other OSes (like M$ DOS).
434  *
435  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
436  *
437  * There is two family of SIIG serial cards with different PCI
438  * interface chip and different configuration methods:
439  *     - 10x cards have control registers in IO and/or memory space;
440  *     - 20x cards have control registers in standard PCI configuration space.
441  *
442  * Note: all 10x cards have PCI device ids 0x10..
443  *       all 20x cards have PCI device ids 0x20..
444  *
445  * There are also Quartet Serial cards which use Oxford Semiconductor
446  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
447  *
448  * Note: some SIIG cards are probed by the parport_serial object.
449  */
450 
451 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
452 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
453 
454 static int pci_siig10x_init(struct pci_dev *dev)
455 {
456         u16 data;
457         void __iomem *p;
458 
459         switch (dev->device & 0xfff8) {
460         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
461                 data = 0xffdf;
462                 break;
463         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
464                 data = 0xf7ff;
465                 break;
466         default:                        /* 1S1P, 4S */
467                 data = 0xfffb;
468                 break;
469         }
470 
471         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
472         if (p == NULL)
473                 return -ENOMEM;
474 
475         writew(readw(p + 0x28) & data, p + 0x28);
476         readw(p + 0x28);
477         iounmap(p);
478         return 0;
479 }
480 
481 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
482 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
483 
484 static int pci_siig20x_init(struct pci_dev *dev)
485 {
486         u8 data;
487 
488         /* Change clock frequency for the first UART. */
489         pci_read_config_byte(dev, 0x6f, &data);
490         pci_write_config_byte(dev, 0x6f, data & 0xef);
491 
492         /* If this card has 2 UART, we have to do the same with second UART. */
493         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
494             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
495                 pci_read_config_byte(dev, 0x73, &data);
496                 pci_write_config_byte(dev, 0x73, data & 0xef);
497         }
498         return 0;
499 }
500 
501 static int pci_siig_init(struct pci_dev *dev)
502 {
503         unsigned int type = dev->device & 0xff00;
504 
505         if (type == 0x1000)
506                 return pci_siig10x_init(dev);
507         else if (type == 0x2000)
508                 return pci_siig20x_init(dev);
509 
510         moan_device("Unknown SIIG card", dev);
511         return -ENODEV;
512 }
513 
514 static int pci_siig_setup(struct serial_private *priv,
515                           const struct pciserial_board *board,
516                           struct uart_8250_port *port, int idx)
517 {
518         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
519 
520         if (idx > 3) {
521                 bar = 4;
522                 offset = (idx - 4) * 8;
523         }
524 
525         return setup_port(priv, port, bar, offset, 0);
526 }
527 
528 /*
529  * Timedia has an explosion of boards, and to avoid the PCI table from
530  * growing *huge*, we use this function to collapse some 70 entries
531  * in the PCI table into one, for sanity's and compactness's sake.
532  */
533 static const unsigned short timedia_single_port[] = {
534         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
535 };
536 
537 static const unsigned short timedia_dual_port[] = {
538         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
539         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
540         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
541         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
542         0xD079, 0
543 };
544 
545 static const unsigned short timedia_quad_port[] = {
546         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
547         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
548         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
549         0xB157, 0
550 };
551 
552 static const unsigned short timedia_eight_port[] = {
553         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
554         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
555 };
556 
557 static const struct timedia_struct {
558         int num;
559         const unsigned short *ids;
560 } timedia_data[] = {
561         { 1, timedia_single_port },
562         { 2, timedia_dual_port },
563         { 4, timedia_quad_port },
564         { 8, timedia_eight_port }
565 };
566 
567 /*
568  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
569  * listing them individually, this driver merely grabs them all with
570  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
571  * and should be left free to be claimed by parport_serial instead.
572  */
573 static int pci_timedia_probe(struct pci_dev *dev)
574 {
575         /*
576          * Check the third digit of the subdevice ID
577          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
578          */
579         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
580                 dev_info(&dev->dev,
581                         "ignoring Timedia subdevice %04x for parport_serial\n",
582                         dev->subsystem_device);
583                 return -ENODEV;
584         }
585 
586         return 0;
587 }
588 
589 static int pci_timedia_init(struct pci_dev *dev)
590 {
591         const unsigned short *ids;
592         int i, j;
593 
594         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
595                 ids = timedia_data[i].ids;
596                 for (j = 0; ids[j]; j++)
597                         if (dev->subsystem_device == ids[j])
598                                 return timedia_data[i].num;
599         }
600         return 0;
601 }
602 
603 /*
604  * Timedia/SUNIX uses a mixture of BARs and offsets
605  * Ugh, this is ugly as all hell --- TYT
606  */
607 static int
608 pci_timedia_setup(struct serial_private *priv,
609                   const struct pciserial_board *board,
610                   struct uart_8250_port *port, int idx)
611 {
612         unsigned int bar = 0, offset = board->first_offset;
613 
614         switch (idx) {
615         case 0:
616                 bar = 0;
617                 break;
618         case 1:
619                 offset = board->uart_offset;
620                 bar = 0;
621                 break;
622         case 2:
623                 bar = 1;
624                 break;
625         case 3:
626                 offset = board->uart_offset;
627                 /* FALLTHROUGH */
628         case 4: /* BAR 2 */
629         case 5: /* BAR 3 */
630         case 6: /* BAR 4 */
631         case 7: /* BAR 5 */
632                 bar = idx - 2;
633         }
634 
635         return setup_port(priv, port, bar, offset, board->reg_shift);
636 }
637 
638 /*
639  * Some Titan cards are also a little weird
640  */
641 static int
642 titan_400l_800l_setup(struct serial_private *priv,
643                       const struct pciserial_board *board,
644                       struct uart_8250_port *port, int idx)
645 {
646         unsigned int bar, offset = board->first_offset;
647 
648         switch (idx) {
649         case 0:
650                 bar = 1;
651                 break;
652         case 1:
653                 bar = 2;
654                 break;
655         default:
656                 bar = 4;
657                 offset = (idx - 2) * board->uart_offset;
658         }
659 
660         return setup_port(priv, port, bar, offset, board->reg_shift);
661 }
662 
663 static int pci_xircom_init(struct pci_dev *dev)
664 {
665         msleep(100);
666         return 0;
667 }
668 
669 static int pci_ni8420_init(struct pci_dev *dev)
670 {
671         void __iomem *p;
672         unsigned int bar = 0;
673 
674         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
675                 moan_device("no memory in bar", dev);
676                 return 0;
677         }
678 
679         p = pci_ioremap_bar(dev, bar);
680         if (p == NULL)
681                 return -ENOMEM;
682 
683         /* Enable CPU Interrupt */
684         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
685                p + NI8420_INT_ENABLE_REG);
686 
687         iounmap(p);
688         return 0;
689 }
690 
691 #define MITE_IOWBSR1_WSIZE      0xa
692 #define MITE_IOWBSR1_WIN_OFFSET 0x800
693 #define MITE_IOWBSR1_WENAB      (1 << 7)
694 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
695 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
696 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
697 
698 static int pci_ni8430_init(struct pci_dev *dev)
699 {
700         void __iomem *p;
701         struct pci_bus_region region;
702         u32 device_window;
703         unsigned int bar = 0;
704 
705         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
706                 moan_device("no memory in bar", dev);
707                 return 0;
708         }
709 
710         p = pci_ioremap_bar(dev, bar);
711         if (p == NULL)
712                 return -ENOMEM;
713 
714         /*
715          * Set device window address and size in BAR0, while acknowledging that
716          * the resource structure may contain a translated address that differs
717          * from the address the device responds to.
718          */
719         pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
720         device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
721                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
722         writel(device_window, p + MITE_IOWBSR1);
723 
724         /* Set window access to go to RAMSEL IO address space */
725         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
726                p + MITE_IOWCR1);
727 
728         /* Enable IO Bus Interrupt 0 */
729         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
730 
731         /* Enable CPU Interrupt */
732         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
733 
734         iounmap(p);
735         return 0;
736 }
737 
738 /* UART Port Control Register */
739 #define NI8430_PORTCON  0x0f
740 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
741 
742 static int
743 pci_ni8430_setup(struct serial_private *priv,
744                  const struct pciserial_board *board,
745                  struct uart_8250_port *port, int idx)
746 {
747         struct pci_dev *dev = priv->dev;
748         void __iomem *p;
749         unsigned int bar, offset = board->first_offset;
750 
751         if (idx >= board->num_ports)
752                 return 1;
753 
754         bar = FL_GET_BASE(board->flags);
755         offset += idx * board->uart_offset;
756 
757         p = pci_ioremap_bar(dev, bar);
758         if (!p)
759                 return -ENOMEM;
760 
761         /* enable the transceiver */
762         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
763                p + offset + NI8430_PORTCON);
764 
765         iounmap(p);
766 
767         return setup_port(priv, port, bar, offset, board->reg_shift);
768 }
769 
770 static int pci_netmos_9900_setup(struct serial_private *priv,
771                                 const struct pciserial_board *board,
772                                 struct uart_8250_port *port, int idx)
773 {
774         unsigned int bar;
775 
776         if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
777             (priv->dev->subsystem_device & 0xff00) == 0x3000) {
778                 /* netmos apparently orders BARs by datasheet layout, so serial
779                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
780                  */
781                 bar = 3 * idx;
782 
783                 return setup_port(priv, port, bar, 0, board->reg_shift);
784         } else {
785                 return pci_default_setup(priv, board, port, idx);
786         }
787 }
788 
789 /* the 99xx series comes with a range of device IDs and a variety
790  * of capabilities:
791  *
792  * 9900 has varying capabilities and can cascade to sub-controllers
793  *   (cascading should be purely internal)
794  * 9904 is hardwired with 4 serial ports
795  * 9912 and 9922 are hardwired with 2 serial ports
796  */
797 static int pci_netmos_9900_numports(struct pci_dev *dev)
798 {
799         unsigned int c = dev->class;
800         unsigned int pi;
801         unsigned short sub_serports;
802 
803         pi = c & 0xff;
804 
805         if (pi == 2)
806                 return 1;
807 
808         if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
809                 /* two possibilities: 0x30ps encodes number of parallel and
810                  * serial ports, or 0x1000 indicates *something*. This is not
811                  * immediately obvious, since the 2s1p+4s configuration seems
812                  * to offer all functionality on functions 0..2, while still
813                  * advertising the same function 3 as the 4s+2s1p config.
814                  */
815                 sub_serports = dev->subsystem_device & 0xf;
816                 if (sub_serports > 0)
817                         return sub_serports;
818 
819                 dev_err(&dev->dev,
820                         "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
821                 return 0;
822         }
823 
824         moan_device("unknown NetMos/Mostech program interface", dev);
825         return 0;
826 }
827 
828 static int pci_netmos_init(struct pci_dev *dev)
829 {
830         /* subdevice 0x00PS means <P> parallel, <S> serial */
831         unsigned int num_serial = dev->subsystem_device & 0xf;
832 
833         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
834                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
835                 return 0;
836 
837         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
838                         dev->subsystem_device == 0x0299)
839                 return 0;
840 
841         switch (dev->device) { /* FALLTHROUGH on all */
842         case PCI_DEVICE_ID_NETMOS_9904:
843         case PCI_DEVICE_ID_NETMOS_9912:
844         case PCI_DEVICE_ID_NETMOS_9922:
845         case PCI_DEVICE_ID_NETMOS_9900:
846                 num_serial = pci_netmos_9900_numports(dev);
847                 break;
848 
849         default:
850                 break;
851         }
852 
853         if (num_serial == 0) {
854                 moan_device("unknown NetMos/Mostech device", dev);
855                 return -ENODEV;
856         }
857 
858         return num_serial;
859 }
860 
861 /*
862  * These chips are available with optionally one parallel port and up to
863  * two serial ports. Unfortunately they all have the same product id.
864  *
865  * Basic configuration is done over a region of 32 I/O ports. The base
866  * ioport is called INTA or INTC, depending on docs/other drivers.
867  *
868  * The region of the 32 I/O ports is configured in POSIO0R...
869  */
870 
871 /* registers */
872 #define ITE_887x_MISCR          0x9c
873 #define ITE_887x_INTCBAR        0x78
874 #define ITE_887x_UARTBAR        0x7c
875 #define ITE_887x_PS0BAR         0x10
876 #define ITE_887x_POSIO0         0x60
877 
878 /* I/O space size */
879 #define ITE_887x_IOSIZE         32
880 /* I/O space size (bits 26-24; 8 bytes = 011b) */
881 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
882 /* I/O space size (bits 26-24; 32 bytes = 101b) */
883 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
884 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
885 #define ITE_887x_POSIO_SPEED            (3 << 29)
886 /* enable IO_Space bit */
887 #define ITE_887x_POSIO_ENABLE           (1 << 31)
888 
889 static int pci_ite887x_init(struct pci_dev *dev)
890 {
891         /* inta_addr are the configuration addresses of the ITE */
892         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
893                                                         0x200, 0x280, 0 };
894         int ret, i, type;
895         struct resource *iobase = NULL;
896         u32 miscr, uartbar, ioport;
897 
898         /* search for the base-ioport */
899         i = 0;
900         while (inta_addr[i] && iobase == NULL) {
901                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
902                                                                 "ite887x");
903                 if (iobase != NULL) {
904                         /* write POSIO0R - speed | size | ioport */
905                         pci_write_config_dword(dev, ITE_887x_POSIO0,
906                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
907                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
908                         /* write INTCBAR - ioport */
909                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
910                                                                 inta_addr[i]);
911                         ret = inb(inta_addr[i]);
912                         if (ret != 0xff) {
913                                 /* ioport connected */
914                                 break;
915                         }
916                         release_region(iobase->start, ITE_887x_IOSIZE);
917                         iobase = NULL;
918                 }
919                 i++;
920         }
921 
922         if (!inta_addr[i]) {
923                 dev_err(&dev->dev, "ite887x: could not find iobase\n");
924                 return -ENODEV;
925         }
926 
927         /* start of undocumented type checking (see parport_pc.c) */
928         type = inb(iobase->start + 0x18) & 0x0f;
929 
930         switch (type) {
931         case 0x2:       /* ITE8871 (1P) */
932         case 0xa:       /* ITE8875 (1P) */
933                 ret = 0;
934                 break;
935         case 0xe:       /* ITE8872 (2S1P) */
936                 ret = 2;
937                 break;
938         case 0x6:       /* ITE8873 (1S) */
939                 ret = 1;
940                 break;
941         case 0x8:       /* ITE8874 (2S) */
942                 ret = 2;
943                 break;
944         default:
945                 moan_device("Unknown ITE887x", dev);
946                 ret = -ENODEV;
947         }
948 
949         /* configure all serial ports */
950         for (i = 0; i < ret; i++) {
951                 /* read the I/O port from the device */
952                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
953                                                                 &ioport);
954                 ioport &= 0x0000FF00;   /* the actual base address */
955                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
956                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
957                         ITE_887x_POSIO_IOSIZE_8 | ioport);
958 
959                 /* write the ioport to the UARTBAR */
960                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
961                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
962                 uartbar |= (ioport << (16 * i));        /* set the ioport */
963                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
964 
965                 /* get current config */
966                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
967                 /* disable interrupts (UARTx_Routing[3:0]) */
968                 miscr &= ~(0xf << (12 - 4 * i));
969                 /* activate the UART (UARTx_En) */
970                 miscr |= 1 << (23 - i);
971                 /* write new config with activated UART */
972                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
973         }
974 
975         if (ret <= 0) {
976                 /* the device has no UARTs if we get here */
977                 release_region(iobase->start, ITE_887x_IOSIZE);
978         }
979 
980         return ret;
981 }
982 
983 static void pci_ite887x_exit(struct pci_dev *dev)
984 {
985         u32 ioport;
986         /* the ioport is bit 0-15 in POSIO0R */
987         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
988         ioport &= 0xffff;
989         release_region(ioport, ITE_887x_IOSIZE);
990 }
991 
992 /*
993  * EndRun Technologies.
994  * Determine the number of ports available on the device.
995  */
996 #define PCI_VENDOR_ID_ENDRUN                    0x7401
997 #define PCI_DEVICE_ID_ENDRUN_1588       0xe100
998 
999 static int pci_endrun_init(struct pci_dev *dev)
1000 {
1001         u8 __iomem *p;
1002         unsigned long deviceID;
1003         unsigned int  number_uarts = 0;
1004 
1005         /* EndRun device is all 0xexxx */
1006         if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1007                 (dev->device & 0xf000) != 0xe000)
1008                 return 0;
1009 
1010         p = pci_iomap(dev, 0, 5);
1011         if (p == NULL)
1012                 return -ENOMEM;
1013 
1014         deviceID = ioread32(p);
1015         /* EndRun device */
1016         if (deviceID == 0x07000200) {
1017                 number_uarts = ioread8(p + 4);
1018                 dev_dbg(&dev->dev,
1019                         "%d ports detected on EndRun PCI Express device\n",
1020                         number_uarts);
1021         }
1022         pci_iounmap(dev, p);
1023         return number_uarts;
1024 }
1025 
1026 /*
1027  * Oxford Semiconductor Inc.
1028  * Check that device is part of the Tornado range of devices, then determine
1029  * the number of ports available on the device.
1030  */
1031 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1032 {
1033         u8 __iomem *p;
1034         unsigned long deviceID;
1035         unsigned int  number_uarts = 0;
1036 
1037         /* OxSemi Tornado devices are all 0xCxxx */
1038         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1039             (dev->device & 0xF000) != 0xC000)
1040                 return 0;
1041 
1042         p = pci_iomap(dev, 0, 5);
1043         if (p == NULL)
1044                 return -ENOMEM;
1045 
1046         deviceID = ioread32(p);
1047         /* Tornado device */
1048         if (deviceID == 0x07000200) {
1049                 number_uarts = ioread8(p + 4);
1050                 dev_dbg(&dev->dev,
1051                         "%d ports detected on Oxford PCI Express device\n",
1052                         number_uarts);
1053         }
1054         pci_iounmap(dev, p);
1055         return number_uarts;
1056 }
1057 
1058 static int pci_asix_setup(struct serial_private *priv,
1059                   const struct pciserial_board *board,
1060                   struct uart_8250_port *port, int idx)
1061 {
1062         port->bugs |= UART_BUG_PARITY;
1063         return pci_default_setup(priv, board, port, idx);
1064 }
1065 
1066 /* Quatech devices have their own extra interface features */
1067 
1068 struct quatech_feature {
1069         u16 devid;
1070         bool amcc;
1071 };
1072 
1073 #define QPCR_TEST_FOR1          0x3F
1074 #define QPCR_TEST_GET1          0x00
1075 #define QPCR_TEST_FOR2          0x40
1076 #define QPCR_TEST_GET2          0x40
1077 #define QPCR_TEST_FOR3          0x80
1078 #define QPCR_TEST_GET3          0x40
1079 #define QPCR_TEST_FOR4          0xC0
1080 #define QPCR_TEST_GET4          0x80
1081 
1082 #define QOPR_CLOCK_X1           0x0000
1083 #define QOPR_CLOCK_X2           0x0001
1084 #define QOPR_CLOCK_X4           0x0002
1085 #define QOPR_CLOCK_X8           0x0003
1086 #define QOPR_CLOCK_RATE_MASK    0x0003
1087 
1088 
1089 static struct quatech_feature quatech_cards[] = {
1090         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1091         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1092         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1093         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1094         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1095         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1096         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1097         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1098         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1099         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1100         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1101         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1102         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1103         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1104         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1105         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1106         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1107         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1108         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1109         { 0, }
1110 };
1111 
1112 static int pci_quatech_amcc(u16 devid)
1113 {
1114         struct quatech_feature *qf = &quatech_cards[0];
1115         while (qf->devid) {
1116                 if (qf->devid == devid)
1117                         return qf->amcc;
1118                 qf++;
1119         }
1120         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1121         return 0;
1122 };
1123 
1124 static int pci_quatech_rqopr(struct uart_8250_port *port)
1125 {
1126         unsigned long base = port->port.iobase;
1127         u8 LCR, val;
1128 
1129         LCR = inb(base + UART_LCR);
1130         outb(0xBF, base + UART_LCR);
1131         val = inb(base + UART_SCR);
1132         outb(LCR, base + UART_LCR);
1133         return val;
1134 }
1135 
1136 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1137 {
1138         unsigned long base = port->port.iobase;
1139         u8 LCR;
1140 
1141         LCR = inb(base + UART_LCR);
1142         outb(0xBF, base + UART_LCR);
1143         inb(base + UART_SCR);
1144         outb(qopr, base + UART_SCR);
1145         outb(LCR, base + UART_LCR);
1146 }
1147 
1148 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1149 {
1150         unsigned long base = port->port.iobase;
1151         u8 LCR, val, qmcr;
1152 
1153         LCR = inb(base + UART_LCR);
1154         outb(0xBF, base + UART_LCR);
1155         val = inb(base + UART_SCR);
1156         outb(val | 0x10, base + UART_SCR);
1157         qmcr = inb(base + UART_MCR);
1158         outb(val, base + UART_SCR);
1159         outb(LCR, base + UART_LCR);
1160 
1161         return qmcr;
1162 }
1163 
1164 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1165 {
1166         unsigned long base = port->port.iobase;
1167         u8 LCR, val;
1168 
1169         LCR = inb(base + UART_LCR);
1170         outb(0xBF, base + UART_LCR);
1171         val = inb(base + UART_SCR);
1172         outb(val | 0x10, base + UART_SCR);
1173         outb(qmcr, base + UART_MCR);
1174         outb(val, base + UART_SCR);
1175         outb(LCR, base + UART_LCR);
1176 }
1177 
1178 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1179 {
1180         unsigned long base = port->port.iobase;
1181         u8 LCR, val;
1182 
1183         LCR = inb(base + UART_LCR);
1184         outb(0xBF, base + UART_LCR);
1185         val = inb(base + UART_SCR);
1186         if (val & 0x20) {
1187                 outb(0x80, UART_LCR);
1188                 if (!(inb(UART_SCR) & 0x20)) {
1189                         outb(LCR, base + UART_LCR);
1190                         return 1;
1191                 }
1192         }
1193         return 0;
1194 }
1195 
1196 static int pci_quatech_test(struct uart_8250_port *port)
1197 {
1198         u8 reg, qopr;
1199 
1200         qopr = pci_quatech_rqopr(port);
1201         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1202         reg = pci_quatech_rqopr(port) & 0xC0;
1203         if (reg != QPCR_TEST_GET1)
1204                 return -EINVAL;
1205         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1206         reg = pci_quatech_rqopr(port) & 0xC0;
1207         if (reg != QPCR_TEST_GET2)
1208                 return -EINVAL;
1209         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1210         reg = pci_quatech_rqopr(port) & 0xC0;
1211         if (reg != QPCR_TEST_GET3)
1212                 return -EINVAL;
1213         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1214         reg = pci_quatech_rqopr(port) & 0xC0;
1215         if (reg != QPCR_TEST_GET4)
1216                 return -EINVAL;
1217 
1218         pci_quatech_wqopr(port, qopr);
1219         return 0;
1220 }
1221 
1222 static int pci_quatech_clock(struct uart_8250_port *port)
1223 {
1224         u8 qopr, reg, set;
1225         unsigned long clock;
1226 
1227         if (pci_quatech_test(port) < 0)
1228                 return 1843200;
1229 
1230         qopr = pci_quatech_rqopr(port);
1231 
1232         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1233         reg = pci_quatech_rqopr(port);
1234         if (reg & QOPR_CLOCK_X8) {
1235                 clock = 1843200;
1236                 goto out;
1237         }
1238         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1239         reg = pci_quatech_rqopr(port);
1240         if (!(reg & QOPR_CLOCK_X8)) {
1241                 clock = 1843200;
1242                 goto out;
1243         }
1244         reg &= QOPR_CLOCK_X8;
1245         if (reg == QOPR_CLOCK_X2) {
1246                 clock =  3685400;
1247                 set = QOPR_CLOCK_X2;
1248         } else if (reg == QOPR_CLOCK_X4) {
1249                 clock = 7372800;
1250                 set = QOPR_CLOCK_X4;
1251         } else if (reg == QOPR_CLOCK_X8) {
1252                 clock = 14745600;
1253                 set = QOPR_CLOCK_X8;
1254         } else {
1255                 clock = 1843200;
1256                 set = QOPR_CLOCK_X1;
1257         }
1258         qopr &= ~QOPR_CLOCK_RATE_MASK;
1259         qopr |= set;
1260 
1261 out:
1262         pci_quatech_wqopr(port, qopr);
1263         return clock;
1264 }
1265 
1266 static int pci_quatech_rs422(struct uart_8250_port *port)
1267 {
1268         u8 qmcr;
1269         int rs422 = 0;
1270 
1271         if (!pci_quatech_has_qmcr(port))
1272                 return 0;
1273         qmcr = pci_quatech_rqmcr(port);
1274         pci_quatech_wqmcr(port, 0xFF);
1275         if (pci_quatech_rqmcr(port))
1276                 rs422 = 1;
1277         pci_quatech_wqmcr(port, qmcr);
1278         return rs422;
1279 }
1280 
1281 static int pci_quatech_init(struct pci_dev *dev)
1282 {
1283         if (pci_quatech_amcc(dev->device)) {
1284                 unsigned long base = pci_resource_start(dev, 0);
1285                 if (base) {
1286                         u32 tmp;
1287 
1288                         outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1289                         tmp = inl(base + 0x3c);
1290                         outl(tmp | 0x01000000, base + 0x3c);
1291                         outl(tmp &= ~0x01000000, base + 0x3c);
1292                 }
1293         }
1294         return 0;
1295 }
1296 
1297 static int pci_quatech_setup(struct serial_private *priv,
1298                   const struct pciserial_board *board,
1299                   struct uart_8250_port *port, int idx)
1300 {
1301         /* Needed by pci_quatech calls below */
1302         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1303         /* Set up the clocking */
1304         port->port.uartclk = pci_quatech_clock(port);
1305         /* For now just warn about RS422 */
1306         if (pci_quatech_rs422(port))
1307                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1308         return pci_default_setup(priv, board, port, idx);
1309 }
1310 
1311 static void pci_quatech_exit(struct pci_dev *dev)
1312 {
1313 }
1314 
1315 static int pci_default_setup(struct serial_private *priv,
1316                   const struct pciserial_board *board,
1317                   struct uart_8250_port *port, int idx)
1318 {
1319         unsigned int bar, offset = board->first_offset, maxnr;
1320 
1321         bar = FL_GET_BASE(board->flags);
1322         if (board->flags & FL_BASE_BARS)
1323                 bar += idx;
1324         else
1325                 offset += idx * board->uart_offset;
1326 
1327         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1328                 (board->reg_shift + 3);
1329 
1330         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1331                 return 1;
1332 
1333         return setup_port(priv, port, bar, offset, board->reg_shift);
1334 }
1335 
1336 static int
1337 ce4100_serial_setup(struct serial_private *priv,
1338                   const struct pciserial_board *board,
1339                   struct uart_8250_port *port, int idx)
1340 {
1341         int ret;
1342 
1343         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1344         port->port.iotype = UPIO_MEM32;
1345         port->port.type = PORT_XSCALE;
1346         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1347         port->port.regshift = 2;
1348 
1349         return ret;
1350 }
1351 
1352 #define PCI_DEVICE_ID_INTEL_BYT_UART1   0x0f0a
1353 #define PCI_DEVICE_ID_INTEL_BYT_UART2   0x0f0c
1354 
1355 #define PCI_DEVICE_ID_INTEL_BSW_UART1   0x228a
1356 #define PCI_DEVICE_ID_INTEL_BSW_UART2   0x228c
1357 
1358 #define PCI_DEVICE_ID_INTEL_BDW_UART1   0x9ce3
1359 #define PCI_DEVICE_ID_INTEL_BDW_UART2   0x9ce4
1360 
1361 #define BYT_PRV_CLK                     0x800
1362 #define BYT_PRV_CLK_EN                  (1 << 0)
1363 #define BYT_PRV_CLK_M_VAL_SHIFT         1
1364 #define BYT_PRV_CLK_N_VAL_SHIFT         16
1365 #define BYT_PRV_CLK_UPDATE              (1 << 31)
1366 
1367 #define BYT_TX_OVF_INT                  0x820
1368 #define BYT_TX_OVF_INT_MASK             (1 << 1)
1369 
1370 static void
1371 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1372                 struct ktermios *old)
1373 {
1374         unsigned int baud = tty_termios_baud_rate(termios);
1375         unsigned long fref = 100000000, fuart = baud * 16;
1376         unsigned long w = BIT(15) - 1;
1377         unsigned long m, n;
1378         u32 reg;
1379 
1380         /* Gracefully handle the B0 case: fall back to B9600 */
1381         fuart = fuart ? fuart : 9600 * 16;
1382 
1383         /* Get Fuart closer to Fref */
1384         fuart *= rounddown_pow_of_two(fref / fuart);
1385 
1386         /*
1387          * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1388          * dividers must be adjusted.
1389          *
1390          * uartclk = (m / n) * 100 MHz, where m <= n
1391          */
1392         rational_best_approximation(fuart, fref, w, w, &m, &n);
1393         p->uartclk = fuart;
1394 
1395         /* Reset the clock */
1396         reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1397         writel(reg, p->membase + BYT_PRV_CLK);
1398         reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1399         writel(reg, p->membase + BYT_PRV_CLK);
1400 
1401         p->status &= ~UPSTAT_AUTOCTS;
1402         if (termios->c_cflag & CRTSCTS)
1403                 p->status |= UPSTAT_AUTOCTS;
1404 
1405         serial8250_do_set_termios(p, termios, old);
1406 }
1407 
1408 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1409 {
1410         struct dw_dma_slave *dws = param;
1411 
1412         if (dws->dma_dev != chan->device->dev)
1413                 return false;
1414 
1415         chan->private = dws;
1416         return true;
1417 }
1418 
1419 static unsigned int
1420 byt_get_mctrl(struct uart_port *port)
1421 {
1422         unsigned int ret = serial8250_do_get_mctrl(port);
1423 
1424         /* Force DCD and DSR signals to permanently be reported as active. */
1425         ret |= TIOCM_CAR | TIOCM_DSR;
1426 
1427         return ret;
1428 }
1429 
1430 static int
1431 byt_serial_setup(struct serial_private *priv,
1432                  const struct pciserial_board *board,
1433                  struct uart_8250_port *port, int idx)
1434 {
1435         struct pci_dev *pdev = priv->dev;
1436         struct device *dev = port->port.dev;
1437         struct uart_8250_dma *dma;
1438         struct dw_dma_slave *tx_param, *rx_param;
1439         struct pci_dev *dma_dev;
1440         int ret;
1441 
1442         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1443         if (!dma)
1444                 return -ENOMEM;
1445 
1446         tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1447         if (!tx_param)
1448                 return -ENOMEM;
1449 
1450         rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1451         if (!rx_param)
1452                 return -ENOMEM;
1453 
1454         switch (pdev->device) {
1455         case PCI_DEVICE_ID_INTEL_BYT_UART1:
1456         case PCI_DEVICE_ID_INTEL_BSW_UART1:
1457         case PCI_DEVICE_ID_INTEL_BDW_UART1:
1458                 rx_param->src_id = 3;
1459                 tx_param->dst_id = 2;
1460                 break;
1461         case PCI_DEVICE_ID_INTEL_BYT_UART2:
1462         case PCI_DEVICE_ID_INTEL_BSW_UART2:
1463         case PCI_DEVICE_ID_INTEL_BDW_UART2:
1464                 rx_param->src_id = 5;
1465                 tx_param->dst_id = 4;
1466                 break;
1467         default:
1468                 return -EINVAL;
1469         }
1470 
1471         rx_param->m_master = 0;
1472         rx_param->p_master = 1;
1473 
1474         dma->rxconf.src_maxburst = 16;
1475 
1476         tx_param->m_master = 0;
1477         tx_param->p_master = 1;
1478 
1479         dma->txconf.dst_maxburst = 16;
1480 
1481         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1482         rx_param->dma_dev = &dma_dev->dev;
1483         tx_param->dma_dev = &dma_dev->dev;
1484 
1485         dma->fn = byt_dma_filter;
1486         dma->rx_param = rx_param;
1487         dma->tx_param = tx_param;
1488 
1489         ret = pci_default_setup(priv, board, port, idx);
1490         port->port.iotype = UPIO_MEM;
1491         port->port.type = PORT_16550A;
1492         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1493         port->port.set_termios = byt_set_termios;
1494         port->port.get_mctrl = byt_get_mctrl;
1495         port->port.fifosize = 64;
1496         port->tx_loadsz = 64;
1497         port->dma = dma;
1498         port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1499 
1500         /* Disable Tx counter interrupts */
1501         writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1502 
1503         return ret;
1504 }
1505 
1506 static int
1507 pci_omegapci_setup(struct serial_private *priv,
1508                       const struct pciserial_board *board,
1509                       struct uart_8250_port *port, int idx)
1510 {
1511         return setup_port(priv, port, 2, idx * 8, 0);
1512 }
1513 
1514 static int
1515 pci_brcm_trumanage_setup(struct serial_private *priv,
1516                          const struct pciserial_board *board,
1517                          struct uart_8250_port *port, int idx)
1518 {
1519         int ret = pci_default_setup(priv, board, port, idx);
1520 
1521         port->port.type = PORT_BRCM_TRUMANAGE;
1522         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1523         return ret;
1524 }
1525 
1526 /* RTS will control by MCR if this bit is 0 */
1527 #define FINTEK_RTS_CONTROL_BY_HW        BIT(4)
1528 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1529 #define FINTEK_RTS_INVERT               BIT(5)
1530 
1531 /* We should do proper H/W transceiver setting before change to RS485 mode */
1532 static int pci_fintek_rs485_config(struct uart_port *port,
1533                                struct serial_rs485 *rs485)
1534 {
1535         struct pci_dev *pci_dev = to_pci_dev(port->dev);
1536         u8 setting;
1537         u8 *index = (u8 *) port->private_data;
1538 
1539         pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1540 
1541         if (!rs485)
1542                 rs485 = &port->rs485;
1543         else if (rs485->flags & SER_RS485_ENABLED)
1544                 memset(rs485->padding, 0, sizeof(rs485->padding));
1545         else
1546                 memset(rs485, 0, sizeof(*rs485));
1547 
1548         /* F81504/508/512 not support RTS delay before or after send */
1549         rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1550 
1551         if (rs485->flags & SER_RS485_ENABLED) {
1552                 /* Enable RTS H/W control mode */
1553                 setting |= FINTEK_RTS_CONTROL_BY_HW;
1554 
1555                 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1556                         /* RTS driving high on TX */
1557                         setting &= ~FINTEK_RTS_INVERT;
1558                 } else {
1559                         /* RTS driving low on TX */
1560                         setting |= FINTEK_RTS_INVERT;
1561                 }
1562 
1563                 rs485->delay_rts_after_send = 0;
1564                 rs485->delay_rts_before_send = 0;
1565         } else {
1566                 /* Disable RTS H/W control mode */
1567                 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1568         }
1569 
1570         pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1571 
1572         if (rs485 != &port->rs485)
1573                 port->rs485 = *rs485;
1574 
1575         return 0;
1576 }
1577 
1578 static int pci_fintek_setup(struct serial_private *priv,
1579                             const struct pciserial_board *board,
1580                             struct uart_8250_port *port, int idx)
1581 {
1582         struct pci_dev *pdev = priv->dev;
1583         u8 *data;
1584         u8 config_base;
1585         u16 iobase;
1586 
1587         config_base = 0x40 + 0x08 * idx;
1588 
1589         /* Get the io address from configuration space */
1590         pci_read_config_word(pdev, config_base + 4, &iobase);
1591 
1592         dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1593 
1594         port->port.iotype = UPIO_PORT;
1595         port->port.iobase = iobase;
1596         port->port.rs485_config = pci_fintek_rs485_config;
1597 
1598         data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1599         if (!data)
1600                 return -ENOMEM;
1601 
1602         /* preserve index in PCI configuration space */
1603         *data = idx;
1604         port->port.private_data = data;
1605 
1606         return 0;
1607 }
1608 
1609 static int pci_fintek_init(struct pci_dev *dev)
1610 {
1611         unsigned long iobase;
1612         u32 max_port, i;
1613         u32 bar_data[3];
1614         u8 config_base;
1615         struct serial_private *priv = pci_get_drvdata(dev);
1616         struct uart_8250_port *port;
1617 
1618         switch (dev->device) {
1619         case 0x1104: /* 4 ports */
1620         case 0x1108: /* 8 ports */
1621                 max_port = dev->device & 0xff;
1622                 break;
1623         case 0x1112: /* 12 ports */
1624                 max_port = 12;
1625                 break;
1626         default:
1627                 return -EINVAL;
1628         }
1629 
1630         /* Get the io address dispatch from the BIOS */
1631         pci_read_config_dword(dev, 0x24, &bar_data[0]);
1632         pci_read_config_dword(dev, 0x20, &bar_data[1]);
1633         pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1634 
1635         for (i = 0; i < max_port; ++i) {
1636                 /* UART0 configuration offset start from 0x40 */
1637                 config_base = 0x40 + 0x08 * i;
1638 
1639                 /* Calculate Real IO Port */
1640                 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1641 
1642                 /* Enable UART I/O port */
1643                 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1644 
1645                 /* Select 128-byte FIFO and 8x FIFO threshold */
1646                 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1647 
1648                 /* LSB UART */
1649                 pci_write_config_byte(dev, config_base + 0x04,
1650                                 (u8)(iobase & 0xff));
1651 
1652                 /* MSB UART */
1653                 pci_write_config_byte(dev, config_base + 0x05,
1654                                 (u8)((iobase & 0xff00) >> 8));
1655 
1656                 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1657 
1658                 if (priv) {
1659                         /* re-apply RS232/485 mode when
1660                          * pciserial_resume_ports()
1661                          */
1662                         port = serial8250_get_port(priv->line[i]);
1663                         pci_fintek_rs485_config(&port->port, NULL);
1664                 } else {
1665                         /* First init without port data
1666                          * force init to RS232 Mode
1667                          */
1668                         pci_write_config_byte(dev, config_base + 0x07, 0x01);
1669                 }
1670         }
1671 
1672         return max_port;
1673 }
1674 
1675 static int skip_tx_en_setup(struct serial_private *priv,
1676                         const struct pciserial_board *board,
1677                         struct uart_8250_port *port, int idx)
1678 {
1679         port->port.flags |= UPF_NO_TXEN_TEST;
1680         dev_dbg(&priv->dev->dev,
1681                 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1682                 priv->dev->vendor, priv->dev->device,
1683                 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1684 
1685         return pci_default_setup(priv, board, port, idx);
1686 }
1687 
1688 static void kt_handle_break(struct uart_port *p)
1689 {
1690         struct uart_8250_port *up = up_to_u8250p(p);
1691         /*
1692          * On receipt of a BI, serial device in Intel ME (Intel
1693          * management engine) needs to have its fifos cleared for sane
1694          * SOL (Serial Over Lan) output.
1695          */
1696         serial8250_clear_and_reinit_fifos(up);
1697 }
1698 
1699 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1700 {
1701         struct uart_8250_port *up = up_to_u8250p(p);
1702         unsigned int val;
1703 
1704         /*
1705          * When the Intel ME (management engine) gets reset its serial
1706          * port registers could return 0 momentarily.  Functions like
1707          * serial8250_console_write, read and save the IER, perform
1708          * some operation and then restore it.  In order to avoid
1709          * setting IER register inadvertently to 0, if the value read
1710          * is 0, double check with ier value in uart_8250_port and use
1711          * that instead.  up->ier should be the same value as what is
1712          * currently configured.
1713          */
1714         val = inb(p->iobase + offset);
1715         if (offset == UART_IER) {
1716                 if (val == 0)
1717                         val = up->ier;
1718         }
1719         return val;
1720 }
1721 
1722 static int kt_serial_setup(struct serial_private *priv,
1723                            const struct pciserial_board *board,
1724                            struct uart_8250_port *port, int idx)
1725 {
1726         port->port.flags |= UPF_BUG_THRE;
1727         port->port.serial_in = kt_serial_in;
1728         port->port.handle_break = kt_handle_break;
1729         return skip_tx_en_setup(priv, board, port, idx);
1730 }
1731 
1732 static int pci_eg20t_init(struct pci_dev *dev)
1733 {
1734 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1735         return -ENODEV;
1736 #else
1737         return 0;
1738 #endif
1739 }
1740 
1741 #define PCI_DEVICE_ID_EXAR_XR17V4358    0x4358
1742 #define PCI_DEVICE_ID_EXAR_XR17V8358    0x8358
1743 
1744 static int
1745 pci_xr17c154_setup(struct serial_private *priv,
1746                   const struct pciserial_board *board,
1747                   struct uart_8250_port *port, int idx)
1748 {
1749         port->port.flags |= UPF_EXAR_EFR;
1750         return pci_default_setup(priv, board, port, idx);
1751 }
1752 
1753 static inline int
1754 xr17v35x_has_slave(struct serial_private *priv)
1755 {
1756         const int dev_id = priv->dev->device;
1757 
1758         return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1759                 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1760 }
1761 
1762 static int
1763 pci_xr17v35x_setup(struct serial_private *priv,
1764                   const struct pciserial_board *board,
1765                   struct uart_8250_port *port, int idx)
1766 {
1767         u8 __iomem *p;
1768 
1769         p = pci_ioremap_bar(priv->dev, 0);
1770         if (p == NULL)
1771                 return -ENOMEM;
1772 
1773         port->port.flags |= UPF_EXAR_EFR;
1774 
1775         /*
1776          * Setup the uart clock for the devices on expansion slot to
1777          * half the clock speed of the main chip (which is 125MHz)
1778          */
1779         if (xr17v35x_has_slave(priv) && idx >= 8)
1780                 port->port.uartclk = (7812500 * 16 / 2);
1781 
1782         /*
1783          * Setup Multipurpose Input/Output pins.
1784          */
1785         if (idx == 0) {
1786                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1787                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1788                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1789                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1790                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1791                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1792                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1793                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1794                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1795                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1796                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1797                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1798         }
1799         writeb(0x00, p + UART_EXAR_8XMODE);
1800         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1801         writeb(128, p + UART_EXAR_TXTRG);
1802         writeb(128, p + UART_EXAR_RXTRG);
1803         iounmap(p);
1804 
1805         return pci_default_setup(priv, board, port, idx);
1806 }
1807 
1808 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1809 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1810 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1811 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1812 
1813 static int
1814 pci_fastcom335_setup(struct serial_private *priv,
1815                   const struct pciserial_board *board,
1816                   struct uart_8250_port *port, int idx)
1817 {
1818         u8 __iomem *p;
1819 
1820         p = pci_ioremap_bar(priv->dev, 0);
1821         if (p == NULL)
1822                 return -ENOMEM;
1823 
1824         port->port.flags |= UPF_EXAR_EFR;
1825 
1826         /*
1827          * Setup Multipurpose Input/Output pins.
1828          */
1829         if (idx == 0) {
1830                 switch (priv->dev->device) {
1831                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1832                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1833                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1834                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1835                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1836                         break;
1837                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1838                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1839                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1840                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1841                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1842                         break;
1843                 }
1844                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1845                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1846                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1847         }
1848         writeb(0x00, p + UART_EXAR_8XMODE);
1849         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1850         writeb(32, p + UART_EXAR_TXTRG);
1851         writeb(32, p + UART_EXAR_RXTRG);
1852         iounmap(p);
1853 
1854         return pci_default_setup(priv, board, port, idx);
1855 }
1856 
1857 static int
1858 pci_wch_ch353_setup(struct serial_private *priv,
1859                     const struct pciserial_board *board,
1860                     struct uart_8250_port *port, int idx)
1861 {
1862         port->port.flags |= UPF_FIXED_TYPE;
1863         port->port.type = PORT_16550A;
1864         return pci_default_setup(priv, board, port, idx);
1865 }
1866 
1867 static int
1868 pci_wch_ch355_setup(struct serial_private *priv,
1869                 const struct pciserial_board *board,
1870                 struct uart_8250_port *port, int idx)
1871 {
1872         port->port.flags |= UPF_FIXED_TYPE;
1873         port->port.type = PORT_16550A;
1874         return pci_default_setup(priv, board, port, idx);
1875 }
1876 
1877 static int
1878 pci_wch_ch38x_setup(struct serial_private *priv,
1879                     const struct pciserial_board *board,
1880                     struct uart_8250_port *port, int idx)
1881 {
1882         port->port.flags |= UPF_FIXED_TYPE;
1883         port->port.type = PORT_16850;
1884         return pci_default_setup(priv, board, port, idx);
1885 }
1886 
1887 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1888 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1889 #define PCI_DEVICE_ID_OCTPRO            0x0001
1890 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1891 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1892 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1893 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1894 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1895 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1896 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1897 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1898 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1899 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1900 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1901 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1902 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1903 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1904 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1905 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1906 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1907 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1908 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1909 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1910 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1911 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1912 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1913 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
1914 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1915 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1916 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1917 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1918 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1919 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1920 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1921 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1922 #define PCI_VENDOR_ID_WCH               0x4348
1923 #define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
1924 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1925 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1926 #define PCI_DEVICE_ID_WCH_CH353_1S1P    0x5053
1927 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1928 #define PCI_DEVICE_ID_WCH_CH355_4S      0x7173
1929 #define PCI_VENDOR_ID_AGESTAR           0x5372
1930 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1931 #define PCI_VENDOR_ID_ASIX              0x9710
1932 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1933 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1934 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1935 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1936 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1937 #define PCI_DEVICE_ID_INTEL_QRK_UART    0x0936
1938 
1939 #define PCI_VENDOR_ID_SUNIX             0x1fd4
1940 #define PCI_DEVICE_ID_SUNIX_1999        0x1999
1941 
1942 #define PCIE_VENDOR_ID_WCH              0x1c00
1943 #define PCIE_DEVICE_ID_WCH_CH382_2S1P   0x3250
1944 #define PCIE_DEVICE_ID_WCH_CH384_4S     0x3470
1945 #define PCIE_DEVICE_ID_WCH_CH382_2S     0x3253
1946 
1947 #define PCI_VENDOR_ID_PERICOM                   0x12D8
1948 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951        0x7951
1949 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952        0x7952
1950 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954        0x7954
1951 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958        0x7958
1952 
1953 #define PCI_VENDOR_ID_ACCESIO                   0x494f
1954 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB     0x1051
1955 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S      0x1053
1956 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB     0x105C
1957 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S      0x105E
1958 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB   0x1091
1959 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2    0x1093
1960 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB   0x1099
1961 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4    0x109B
1962 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB    0x10D1
1963 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM     0x10D3
1964 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB    0x10DA
1965 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM     0x10DC
1966 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1    0x1108
1967 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2    0x1110
1968 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2    0x1111
1969 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4    0x1118
1970 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4    0x1119
1971 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S       0x1152
1972 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S       0x115A
1973 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2     0x1190
1974 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2    0x1191
1975 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4     0x1198
1976 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4    0x1199
1977 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM      0x11D0
1978 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4     0x105A
1979 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4     0x105B
1980 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8     0x106A
1981 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8     0x106B
1982 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4     0x1098
1983 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8     0x10A9
1984 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM      0x10D9
1985 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM      0x10E9
1986 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM      0x11D8
1987 
1988 
1989 
1990 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1991 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1992 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1993 
1994 /*
1995  * Master list of serial port init/setup/exit quirks.
1996  * This does not describe the general nature of the port.
1997  * (ie, baud base, number and location of ports, etc)
1998  *
1999  * This list is ordered alphabetically by vendor then device.
2000  * Specific entries must come before more generic entries.
2001  */
2002 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
2003         /*
2004         * ADDI-DATA GmbH communication cards <info@addi-data.com>
2005         */
2006         {
2007                 .vendor         = PCI_VENDOR_ID_AMCC,
2008                 .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2009                 .subvendor      = PCI_ANY_ID,
2010                 .subdevice      = PCI_ANY_ID,
2011                 .setup          = addidata_apci7800_setup,
2012         },
2013         /*
2014          * AFAVLAB cards - these may be called via parport_serial
2015          *  It is not clear whether this applies to all products.
2016          */
2017         {
2018                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
2019                 .device         = PCI_ANY_ID,
2020                 .subvendor      = PCI_ANY_ID,
2021                 .subdevice      = PCI_ANY_ID,
2022                 .setup          = afavlab_setup,
2023         },
2024         /*
2025          * HP Diva
2026          */
2027         {
2028                 .vendor         = PCI_VENDOR_ID_HP,
2029                 .device         = PCI_DEVICE_ID_HP_DIVA,
2030                 .subvendor      = PCI_ANY_ID,
2031                 .subdevice      = PCI_ANY_ID,
2032                 .init           = pci_hp_diva_init,
2033                 .setup          = pci_hp_diva_setup,
2034         },
2035         /*
2036          * Intel
2037          */
2038         {
2039                 .vendor         = PCI_VENDOR_ID_INTEL,
2040                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
2041                 .subvendor      = 0xe4bf,
2042                 .subdevice      = PCI_ANY_ID,
2043                 .init           = pci_inteli960ni_init,
2044                 .setup          = pci_default_setup,
2045         },
2046         {
2047                 .vendor         = PCI_VENDOR_ID_INTEL,
2048                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
2049                 .subvendor      = PCI_ANY_ID,
2050                 .subdevice      = PCI_ANY_ID,
2051                 .setup          = skip_tx_en_setup,
2052         },
2053         {
2054                 .vendor         = PCI_VENDOR_ID_INTEL,
2055                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
2056                 .subvendor      = PCI_ANY_ID,
2057                 .subdevice      = PCI_ANY_ID,
2058                 .setup          = skip_tx_en_setup,
2059         },
2060         {
2061                 .vendor         = PCI_VENDOR_ID_INTEL,
2062                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
2063                 .subvendor      = PCI_ANY_ID,
2064                 .subdevice      = PCI_ANY_ID,
2065                 .setup          = skip_tx_en_setup,
2066         },
2067         {
2068                 .vendor         = PCI_VENDOR_ID_INTEL,
2069                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
2070                 .subvendor      = PCI_ANY_ID,
2071                 .subdevice      = PCI_ANY_ID,
2072                 .setup          = ce4100_serial_setup,
2073         },
2074         {
2075                 .vendor         = PCI_VENDOR_ID_INTEL,
2076                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2077                 .subvendor      = PCI_ANY_ID,
2078                 .subdevice      = PCI_ANY_ID,
2079                 .setup          = kt_serial_setup,
2080         },
2081         {
2082                 .vendor         = PCI_VENDOR_ID_INTEL,
2083                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART1,
2084                 .subvendor      = PCI_ANY_ID,
2085                 .subdevice      = PCI_ANY_ID,
2086                 .setup          = byt_serial_setup,
2087         },
2088         {
2089                 .vendor         = PCI_VENDOR_ID_INTEL,
2090                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART2,
2091                 .subvendor      = PCI_ANY_ID,
2092                 .subdevice      = PCI_ANY_ID,
2093                 .setup          = byt_serial_setup,
2094         },
2095         {
2096                 .vendor         = PCI_VENDOR_ID_INTEL,
2097                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART1,
2098                 .subvendor      = PCI_ANY_ID,
2099                 .subdevice      = PCI_ANY_ID,
2100                 .setup          = byt_serial_setup,
2101         },
2102         {
2103                 .vendor         = PCI_VENDOR_ID_INTEL,
2104                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART2,
2105                 .subvendor      = PCI_ANY_ID,
2106                 .subdevice      = PCI_ANY_ID,
2107                 .setup          = byt_serial_setup,
2108         },
2109         {
2110                 .vendor         = PCI_VENDOR_ID_INTEL,
2111                 .device         = PCI_DEVICE_ID_INTEL_BDW_UART1,
2112                 .subvendor      = PCI_ANY_ID,
2113                 .subdevice      = PCI_ANY_ID,
2114                 .setup          = byt_serial_setup,
2115         },
2116         {
2117                 .vendor         = PCI_VENDOR_ID_INTEL,
2118                 .device         = PCI_DEVICE_ID_INTEL_BDW_UART2,
2119                 .subvendor      = PCI_ANY_ID,
2120                 .subdevice      = PCI_ANY_ID,
2121                 .setup          = byt_serial_setup,
2122         },
2123         /*
2124          * ITE
2125          */
2126         {
2127                 .vendor         = PCI_VENDOR_ID_ITE,
2128                 .device         = PCI_DEVICE_ID_ITE_8872,
2129                 .subvendor      = PCI_ANY_ID,
2130                 .subdevice      = PCI_ANY_ID,
2131                 .init           = pci_ite887x_init,
2132                 .setup          = pci_default_setup,
2133                 .exit           = pci_ite887x_exit,
2134         },
2135         /*
2136          * National Instruments
2137          */
2138         {
2139                 .vendor         = PCI_VENDOR_ID_NI,
2140                 .device         = PCI_DEVICE_ID_NI_PCI23216,
2141                 .subvendor      = PCI_ANY_ID,
2142                 .subdevice      = PCI_ANY_ID,
2143                 .init           = pci_ni8420_init,
2144                 .setup          = pci_default_setup,
2145                 .exit           = pci_ni8420_exit,
2146         },
2147         {
2148                 .vendor         = PCI_VENDOR_ID_NI,
2149                 .device         = PCI_DEVICE_ID_NI_PCI2328,
2150                 .subvendor      = PCI_ANY_ID,
2151                 .subdevice      = PCI_ANY_ID,
2152                 .init           = pci_ni8420_init,
2153                 .setup          = pci_default_setup,
2154                 .exit           = pci_ni8420_exit,
2155         },
2156         {
2157                 .vendor         = PCI_VENDOR_ID_NI,
2158                 .device         = PCI_DEVICE_ID_NI_PCI2324,
2159                 .subvendor      = PCI_ANY_ID,
2160                 .subdevice      = PCI_ANY_ID,
2161                 .init           = pci_ni8420_init,
2162                 .setup          = pci_default_setup,
2163                 .exit           = pci_ni8420_exit,
2164         },
2165         {
2166                 .vendor         = PCI_VENDOR_ID_NI,
2167                 .device         = PCI_DEVICE_ID_NI_PCI2322,
2168                 .subvendor      = PCI_ANY_ID,
2169                 .subdevice      = PCI_ANY_ID,
2170                 .init           = pci_ni8420_init,
2171                 .setup          = pci_default_setup,
2172                 .exit           = pci_ni8420_exit,
2173         },
2174         {
2175                 .vendor         = PCI_VENDOR_ID_NI,
2176                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
2177                 .subvendor      = PCI_ANY_ID,
2178                 .subdevice      = PCI_ANY_ID,
2179                 .init           = pci_ni8420_init,
2180                 .setup          = pci_default_setup,
2181                 .exit           = pci_ni8420_exit,
2182         },
2183         {
2184                 .vendor         = PCI_VENDOR_ID_NI,
2185                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
2186                 .subvendor      = PCI_ANY_ID,
2187                 .subdevice      = PCI_ANY_ID,
2188                 .init           = pci_ni8420_init,
2189                 .setup          = pci_default_setup,
2190                 .exit           = pci_ni8420_exit,
2191         },
2192         {
2193                 .vendor         = PCI_VENDOR_ID_NI,
2194                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
2195                 .subvendor      = PCI_ANY_ID,
2196                 .subdevice      = PCI_ANY_ID,
2197                 .init           = pci_ni8420_init,
2198                 .setup          = pci_default_setup,
2199                 .exit           = pci_ni8420_exit,
2200         },
2201         {
2202                 .vendor         = PCI_VENDOR_ID_NI,
2203                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
2204                 .subvendor      = PCI_ANY_ID,
2205                 .subdevice      = PCI_ANY_ID,
2206                 .init           = pci_ni8420_init,
2207                 .setup          = pci_default_setup,
2208                 .exit           = pci_ni8420_exit,
2209         },
2210         {
2211                 .vendor         = PCI_VENDOR_ID_NI,
2212                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
2213                 .subvendor      = PCI_ANY_ID,
2214                 .subdevice      = PCI_ANY_ID,
2215                 .init           = pci_ni8420_init,
2216                 .setup          = pci_default_setup,
2217                 .exit           = pci_ni8420_exit,
2218         },
2219         {
2220                 .vendor         = PCI_VENDOR_ID_NI,
2221                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
2222                 .subvendor      = PCI_ANY_ID,
2223                 .subdevice      = PCI_ANY_ID,
2224                 .init           = pci_ni8420_init,
2225                 .setup          = pci_default_setup,
2226                 .exit           = pci_ni8420_exit,
2227         },
2228         {
2229                 .vendor         = PCI_VENDOR_ID_NI,
2230                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
2231                 .subvendor      = PCI_ANY_ID,
2232                 .subdevice      = PCI_ANY_ID,
2233                 .init           = pci_ni8420_init,
2234                 .setup          = pci_default_setup,
2235                 .exit           = pci_ni8420_exit,
2236         },
2237         {
2238                 .vendor         = PCI_VENDOR_ID_NI,
2239                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
2240                 .subvendor      = PCI_ANY_ID,
2241                 .subdevice      = PCI_ANY_ID,
2242                 .init           = pci_ni8420_init,
2243                 .setup          = pci_default_setup,
2244                 .exit           = pci_ni8420_exit,
2245         },
2246         {
2247                 .vendor         = PCI_VENDOR_ID_NI,
2248                 .device         = PCI_ANY_ID,
2249                 .subvendor      = PCI_ANY_ID,
2250                 .subdevice      = PCI_ANY_ID,
2251                 .init           = pci_ni8430_init,
2252                 .setup          = pci_ni8430_setup,
2253                 .exit           = pci_ni8430_exit,
2254         },
2255         /* Quatech */
2256         {
2257                 .vendor         = PCI_VENDOR_ID_QUATECH,
2258                 .device         = PCI_ANY_ID,
2259                 .subvendor      = PCI_ANY_ID,
2260                 .subdevice      = PCI_ANY_ID,
2261                 .init           = pci_quatech_init,
2262                 .setup          = pci_quatech_setup,
2263                 .exit           = pci_quatech_exit,
2264         },
2265         /*
2266          * Panacom
2267          */
2268         {
2269                 .vendor         = PCI_VENDOR_ID_PANACOM,
2270                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2271                 .subvendor      = PCI_ANY_ID,
2272                 .subdevice      = PCI_ANY_ID,
2273                 .init           = pci_plx9050_init,
2274                 .setup          = pci_default_setup,
2275                 .exit           = pci_plx9050_exit,
2276         },
2277         {
2278                 .vendor         = PCI_VENDOR_ID_PANACOM,
2279                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2280                 .subvendor      = PCI_ANY_ID,
2281                 .subdevice      = PCI_ANY_ID,
2282                 .init           = pci_plx9050_init,
2283                 .setup          = pci_default_setup,
2284                 .exit           = pci_plx9050_exit,
2285         },
2286         /*
2287          * PLX
2288          */
2289         {
2290                 .vendor         = PCI_VENDOR_ID_PLX,
2291                 .device         = PCI_DEVICE_ID_PLX_9050,
2292                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2293                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2294                 .init           = pci_plx9050_init,
2295                 .setup          = pci_default_setup,
2296                 .exit           = pci_plx9050_exit,
2297         },
2298         {
2299                 .vendor         = PCI_VENDOR_ID_PLX,
2300                 .device         = PCI_DEVICE_ID_PLX_9050,
2301                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2302                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2303                 .init           = pci_plx9050_init,
2304                 .setup          = pci_default_setup,
2305                 .exit           = pci_plx9050_exit,
2306         },
2307         {
2308                 .vendor         = PCI_VENDOR_ID_PLX,
2309                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2310                 .subvendor      = PCI_VENDOR_ID_PLX,
2311                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2312                 .init           = pci_plx9050_init,
2313                 .setup          = pci_default_setup,
2314                 .exit           = pci_plx9050_exit,
2315         },
2316         /*
2317          * SBS Technologies, Inc., PMC-OCTALPRO 232
2318          */
2319         {
2320                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2321                 .device         = PCI_DEVICE_ID_OCTPRO,
2322                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2323                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2324                 .init           = sbs_init,
2325                 .setup          = sbs_setup,
2326                 .exit           = sbs_exit,
2327         },
2328         /*
2329          * SBS Technologies, Inc., PMC-OCTALPRO 422
2330          */
2331         {
2332                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2333                 .device         = PCI_DEVICE_ID_OCTPRO,
2334                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2335                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2336                 .init           = sbs_init,
2337                 .setup          = sbs_setup,
2338                 .exit           = sbs_exit,
2339         },
2340         /*
2341          * SBS Technologies, Inc., P-Octal 232
2342          */
2343         {
2344                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2345                 .device         = PCI_DEVICE_ID_OCTPRO,
2346                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2347                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2348                 .init           = sbs_init,
2349                 .setup          = sbs_setup,
2350                 .exit           = sbs_exit,
2351         },
2352         /*
2353          * SBS Technologies, Inc., P-Octal 422
2354          */
2355         {
2356                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2357                 .device         = PCI_DEVICE_ID_OCTPRO,
2358                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2359                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2360                 .init           = sbs_init,
2361                 .setup          = sbs_setup,
2362                 .exit           = sbs_exit,
2363         },
2364         /*
2365          * SIIG cards - these may be called via parport_serial
2366          */
2367         {
2368                 .vendor         = PCI_VENDOR_ID_SIIG,
2369                 .device         = PCI_ANY_ID,
2370                 .subvendor      = PCI_ANY_ID,
2371                 .subdevice      = PCI_ANY_ID,
2372                 .init           = pci_siig_init,
2373                 .setup          = pci_siig_setup,
2374         },
2375         /*
2376          * Titan cards
2377          */
2378         {
2379                 .vendor         = PCI_VENDOR_ID_TITAN,
2380                 .device         = PCI_DEVICE_ID_TITAN_400L,
2381                 .subvendor      = PCI_ANY_ID,
2382                 .subdevice      = PCI_ANY_ID,
2383                 .setup          = titan_400l_800l_setup,
2384         },
2385         {
2386                 .vendor         = PCI_VENDOR_ID_TITAN,
2387                 .device         = PCI_DEVICE_ID_TITAN_800L,
2388                 .subvendor      = PCI_ANY_ID,
2389                 .subdevice      = PCI_ANY_ID,
2390                 .setup          = titan_400l_800l_setup,
2391         },
2392         /*
2393          * Timedia cards
2394          */
2395         {
2396                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2397                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2398                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2399                 .subdevice      = PCI_ANY_ID,
2400                 .probe          = pci_timedia_probe,
2401                 .init           = pci_timedia_init,
2402                 .setup          = pci_timedia_setup,
2403         },
2404         {
2405                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2406                 .device         = PCI_ANY_ID,
2407                 .subvendor      = PCI_ANY_ID,
2408                 .subdevice      = PCI_ANY_ID,
2409                 .setup          = pci_timedia_setup,
2410         },
2411         /*
2412          * SUNIX (Timedia) cards
2413          * Do not "probe" for these cards as there is at least one combination
2414          * card that should be handled by parport_pc that doesn't match the
2415          * rule in pci_timedia_probe.
2416          * It is part number is MIO5079A but its subdevice ID is 0x0102.
2417          * There are some boards with part number SER5037AL that report
2418          * subdevice ID 0x0002.
2419          */
2420         {
2421                 .vendor         = PCI_VENDOR_ID_SUNIX,
2422                 .device         = PCI_DEVICE_ID_SUNIX_1999,
2423                 .subvendor      = PCI_VENDOR_ID_SUNIX,
2424                 .subdevice      = PCI_ANY_ID,
2425                 .init           = pci_timedia_init,
2426                 .setup          = pci_timedia_setup,
2427         },
2428         /*
2429          * Exar cards
2430          */
2431         {
2432                 .vendor = PCI_VENDOR_ID_EXAR,
2433                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2434                 .subvendor      = PCI_ANY_ID,
2435                 .subdevice      = PCI_ANY_ID,
2436                 .setup          = pci_xr17c154_setup,
2437         },
2438         {
2439                 .vendor = PCI_VENDOR_ID_EXAR,
2440                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2441                 .subvendor      = PCI_ANY_ID,
2442                 .subdevice      = PCI_ANY_ID,
2443                 .setup          = pci_xr17c154_setup,
2444         },
2445         {
2446                 .vendor = PCI_VENDOR_ID_EXAR,
2447                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2448                 .subvendor      = PCI_ANY_ID,
2449                 .subdevice      = PCI_ANY_ID,
2450                 .setup          = pci_xr17c154_setup,
2451         },
2452         {
2453                 .vendor = PCI_VENDOR_ID_EXAR,
2454                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2455                 .subvendor      = PCI_ANY_ID,
2456                 .subdevice      = PCI_ANY_ID,
2457                 .setup          = pci_xr17v35x_setup,
2458         },
2459         {
2460                 .vendor = PCI_VENDOR_ID_EXAR,
2461                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2462                 .subvendor      = PCI_ANY_ID,
2463                 .subdevice      = PCI_ANY_ID,
2464                 .setup          = pci_xr17v35x_setup,
2465         },
2466         {
2467                 .vendor = PCI_VENDOR_ID_EXAR,
2468                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2469                 .subvendor      = PCI_ANY_ID,
2470                 .subdevice      = PCI_ANY_ID,
2471                 .setup          = pci_xr17v35x_setup,
2472         },
2473         {
2474                 .vendor = PCI_VENDOR_ID_EXAR,
2475                 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2476                 .subvendor      = PCI_ANY_ID,
2477                 .subdevice      = PCI_ANY_ID,
2478                 .setup          = pci_xr17v35x_setup,
2479         },
2480         {
2481                 .vendor = PCI_VENDOR_ID_EXAR,
2482                 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2483                 .subvendor      = PCI_ANY_ID,
2484                 .subdevice      = PCI_ANY_ID,
2485                 .setup          = pci_xr17v35x_setup,
2486         },
2487         /*
2488          * Xircom cards
2489          */
2490         {
2491                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2492                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2493                 .subvendor      = PCI_ANY_ID,
2494                 .subdevice      = PCI_ANY_ID,
2495                 .init           = pci_xircom_init,
2496                 .setup          = pci_default_setup,
2497         },
2498         /*
2499          * Netmos cards - these may be called via parport_serial
2500          */
2501         {
2502                 .vendor         = PCI_VENDOR_ID_NETMOS,
2503                 .device         = PCI_ANY_ID,
2504                 .subvendor      = PCI_ANY_ID,
2505                 .subdevice      = PCI_ANY_ID,
2506                 .init           = pci_netmos_init,
2507                 .setup          = pci_netmos_9900_setup,
2508         },
2509         /*
2510          * EndRun Technologies
2511         */
2512         {
2513                 .vendor         = PCI_VENDOR_ID_ENDRUN,
2514                 .device         = PCI_ANY_ID,
2515                 .subvendor      = PCI_ANY_ID,
2516                 .subdevice      = PCI_ANY_ID,
2517                 .init           = pci_endrun_init,
2518                 .setup          = pci_default_setup,
2519         },
2520         /*
2521          * For Oxford Semiconductor Tornado based devices
2522          */
2523         {
2524                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2525                 .device         = PCI_ANY_ID,
2526                 .subvendor      = PCI_ANY_ID,
2527                 .subdevice      = PCI_ANY_ID,
2528                 .init           = pci_oxsemi_tornado_init,
2529                 .setup          = pci_default_setup,
2530         },
2531         {
2532                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2533                 .device         = PCI_ANY_ID,
2534                 .subvendor      = PCI_ANY_ID,
2535                 .subdevice      = PCI_ANY_ID,
2536                 .init           = pci_oxsemi_tornado_init,
2537                 .setup          = pci_default_setup,
2538         },
2539         {
2540                 .vendor         = PCI_VENDOR_ID_DIGI,
2541                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2542                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2543                 .subdevice              = PCI_ANY_ID,
2544                 .init                   = pci_oxsemi_tornado_init,
2545                 .setup          = pci_default_setup,
2546         },
2547         {
2548                 .vendor         = PCI_VENDOR_ID_INTEL,
2549                 .device         = 0x8811,
2550                 .subvendor      = PCI_ANY_ID,
2551                 .subdevice      = PCI_ANY_ID,
2552                 .init           = pci_eg20t_init,
2553                 .setup          = pci_default_setup,
2554         },
2555         {
2556                 .vendor         = PCI_VENDOR_ID_INTEL,
2557                 .device         = 0x8812,
2558                 .subvendor      = PCI_ANY_ID,
2559                 .subdevice      = PCI_ANY_ID,
2560                 .init           = pci_eg20t_init,
2561                 .setup          = pci_default_setup,
2562         },
2563         {
2564                 .vendor         = PCI_VENDOR_ID_INTEL,
2565                 .device         = 0x8813,
2566                 .subvendor      = PCI_ANY_ID,
2567                 .subdevice      = PCI_ANY_ID,
2568                 .init           = pci_eg20t_init,
2569                 .setup          = pci_default_setup,
2570         },
2571         {
2572                 .vendor         = PCI_VENDOR_ID_INTEL,
2573                 .device         = 0x8814,
2574                 .subvendor      = PCI_ANY_ID,
2575                 .subdevice      = PCI_ANY_ID,
2576                 .init           = pci_eg20t_init,
2577                 .setup          = pci_default_setup,
2578         },
2579         {
2580                 .vendor         = 0x10DB,
2581                 .device         = 0x8027,
2582                 .subvendor      = PCI_ANY_ID,
2583                 .subdevice      = PCI_ANY_ID,
2584                 .init           = pci_eg20t_init,
2585                 .setup          = pci_default_setup,
2586         },
2587         {
2588                 .vendor         = 0x10DB,
2589                 .device         = 0x8028,
2590                 .subvendor      = PCI_ANY_ID,
2591                 .subdevice      = PCI_ANY_ID,
2592                 .init           = pci_eg20t_init,
2593                 .setup          = pci_default_setup,
2594         },
2595         {
2596                 .vendor         = 0x10DB,
2597                 .device         = 0x8029,
2598                 .subvendor      = PCI_ANY_ID,
2599                 .subdevice      = PCI_ANY_ID,
2600                 .init           = pci_eg20t_init,
2601                 .setup          = pci_default_setup,
2602         },
2603         {
2604                 .vendor         = 0x10DB,
2605                 .device         = 0x800C,
2606                 .subvendor      = PCI_ANY_ID,
2607                 .subdevice      = PCI_ANY_ID,
2608                 .init           = pci_eg20t_init,
2609                 .setup          = pci_default_setup,
2610         },
2611         {
2612                 .vendor         = 0x10DB,
2613                 .device         = 0x800D,
2614                 .subvendor      = PCI_ANY_ID,
2615                 .subdevice      = PCI_ANY_ID,
2616                 .init           = pci_eg20t_init,
2617                 .setup          = pci_default_setup,
2618         },
2619         /*
2620          * Cronyx Omega PCI (PLX-chip based)
2621          */
2622         {
2623                 .vendor         = PCI_VENDOR_ID_PLX,
2624                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2625                 .subvendor      = PCI_ANY_ID,
2626                 .subdevice      = PCI_ANY_ID,
2627                 .setup          = pci_omegapci_setup,
2628         },
2629         /* WCH CH353 1S1P card (16550 clone) */
2630         {
2631                 .vendor         = PCI_VENDOR_ID_WCH,
2632                 .device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2633                 .subvendor      = PCI_ANY_ID,
2634                 .subdevice      = PCI_ANY_ID,
2635                 .setup          = pci_wch_ch353_setup,
2636         },
2637         /* WCH CH353 2S1P card (16550 clone) */
2638         {
2639                 .vendor         = PCI_VENDOR_ID_WCH,
2640                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2641                 .subvendor      = PCI_ANY_ID,
2642                 .subdevice      = PCI_ANY_ID,
2643                 .setup          = pci_wch_ch353_setup,
2644         },
2645         /* WCH CH353 4S card (16550 clone) */
2646         {
2647                 .vendor         = PCI_VENDOR_ID_WCH,
2648                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2649                 .subvendor      = PCI_ANY_ID,
2650                 .subdevice      = PCI_ANY_ID,
2651                 .setup          = pci_wch_ch353_setup,
2652         },
2653         /* WCH CH353 2S1PF card (16550 clone) */
2654         {
2655                 .vendor         = PCI_VENDOR_ID_WCH,
2656                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2657                 .subvendor      = PCI_ANY_ID,
2658                 .subdevice      = PCI_ANY_ID,
2659                 .setup          = pci_wch_ch353_setup,
2660         },
2661         /* WCH CH352 2S card (16550 clone) */
2662         {
2663                 .vendor         = PCI_VENDOR_ID_WCH,
2664                 .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2665                 .subvendor      = PCI_ANY_ID,
2666                 .subdevice      = PCI_ANY_ID,
2667                 .setup          = pci_wch_ch353_setup,
2668         },
2669         /* WCH CH355 4S card (16550 clone) */
2670         {
2671                 .vendor         = PCI_VENDOR_ID_WCH,
2672                 .device         = PCI_DEVICE_ID_WCH_CH355_4S,
2673                 .subvendor      = PCI_ANY_ID,
2674                 .subdevice      = PCI_ANY_ID,
2675                 .setup          = pci_wch_ch355_setup,
2676         },
2677         /* WCH CH382 2S card (16850 clone) */
2678         {
2679                 .vendor         = PCIE_VENDOR_ID_WCH,
2680                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S,
2681                 .subvendor      = PCI_ANY_ID,
2682                 .subdevice      = PCI_ANY_ID,
2683                 .setup          = pci_wch_ch38x_setup,
2684         },
2685         /* WCH CH382 2S1P card (16850 clone) */
2686         {
2687                 .vendor         = PCIE_VENDOR_ID_WCH,
2688                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2689                 .subvendor      = PCI_ANY_ID,
2690                 .subdevice      = PCI_ANY_ID,
2691                 .setup          = pci_wch_ch38x_setup,
2692         },
2693         /* WCH CH384 4S card (16850 clone) */
2694         {
2695                 .vendor         = PCIE_VENDOR_ID_WCH,
2696                 .device         = PCIE_DEVICE_ID_WCH_CH384_4S,
2697                 .subvendor      = PCI_ANY_ID,
2698                 .subdevice      = PCI_ANY_ID,
2699                 .setup          = pci_wch_ch38x_setup,
2700         },
2701         /*
2702          * ASIX devices with FIFO bug
2703          */
2704         {
2705                 .vendor         = PCI_VENDOR_ID_ASIX,
2706                 .device         = PCI_ANY_ID,
2707                 .subvendor      = PCI_ANY_ID,
2708                 .subdevice      = PCI_ANY_ID,
2709                 .setup          = pci_asix_setup,
2710         },
2711         /*
2712          * Commtech, Inc. Fastcom adapters
2713          *
2714          */
2715         {
2716                 .vendor = PCI_VENDOR_ID_COMMTECH,
2717                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2718                 .subvendor      = PCI_ANY_ID,
2719                 .subdevice      = PCI_ANY_ID,
2720                 .setup          = pci_fastcom335_setup,
2721         },
2722         {
2723                 .vendor = PCI_VENDOR_ID_COMMTECH,
2724                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2725                 .subvendor      = PCI_ANY_ID,
2726                 .subdevice      = PCI_ANY_ID,
2727                 .setup          = pci_fastcom335_setup,
2728         },
2729         {
2730                 .vendor = PCI_VENDOR_ID_COMMTECH,
2731                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2732                 .subvendor      = PCI_ANY_ID,
2733                 .subdevice      = PCI_ANY_ID,
2734                 .setup          = pci_fastcom335_setup,
2735         },
2736         {
2737                 .vendor = PCI_VENDOR_ID_COMMTECH,
2738                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2739                 .subvendor      = PCI_ANY_ID,
2740                 .subdevice      = PCI_ANY_ID,
2741                 .setup          = pci_fastcom335_setup,
2742         },
2743         {
2744                 .vendor = PCI_VENDOR_ID_COMMTECH,
2745                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2746                 .subvendor      = PCI_ANY_ID,
2747                 .subdevice      = PCI_ANY_ID,
2748                 .setup          = pci_xr17v35x_setup,
2749         },
2750         {
2751                 .vendor = PCI_VENDOR_ID_COMMTECH,
2752                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2753                 .subvendor      = PCI_ANY_ID,
2754                 .subdevice      = PCI_ANY_ID,
2755                 .setup          = pci_xr17v35x_setup,
2756         },
2757         {
2758                 .vendor = PCI_VENDOR_ID_COMMTECH,
2759                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2760                 .subvendor      = PCI_ANY_ID,
2761                 .subdevice      = PCI_ANY_ID,
2762                 .setup          = pci_xr17v35x_setup,
2763         },
2764         /*
2765          * Broadcom TruManage (NetXtreme)
2766          */
2767         {
2768                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2769                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2770                 .subvendor      = PCI_ANY_ID,
2771                 .subdevice      = PCI_ANY_ID,
2772                 .setup          = pci_brcm_trumanage_setup,
2773         },
2774         {
2775                 .vendor         = 0x1c29,
2776                 .device         = 0x1104,
2777                 .subvendor      = PCI_ANY_ID,
2778                 .subdevice      = PCI_ANY_ID,
2779                 .setup          = pci_fintek_setup,
2780                 .init           = pci_fintek_init,
2781         },
2782         {
2783                 .vendor         = 0x1c29,
2784                 .device         = 0x1108,
2785                 .subvendor      = PCI_ANY_ID,
2786                 .subdevice      = PCI_ANY_ID,
2787                 .setup          = pci_fintek_setup,
2788                 .init           = pci_fintek_init,
2789         },
2790         {
2791                 .vendor         = 0x1c29,
2792                 .device         = 0x1112,
2793                 .subvendor      = PCI_ANY_ID,
2794                 .subdevice      = PCI_ANY_ID,
2795                 .setup          = pci_fintek_setup,
2796                 .init           = pci_fintek_init,
2797         },
2798 
2799         /*
2800          * Default "match everything" terminator entry
2801          */
2802         {
2803                 .vendor         = PCI_ANY_ID,
2804                 .device         = PCI_ANY_ID,
2805                 .subvendor      = PCI_ANY_ID,
2806                 .subdevice      = PCI_ANY_ID,
2807                 .setup          = pci_default_setup,
2808         }
2809 };
2810 
2811 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2812 {
2813         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2814 }
2815 
2816 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2817 {
2818         struct pci_serial_quirk *quirk;
2819 
2820         for (quirk = pci_serial_quirks; ; quirk++)
2821                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2822                     quirk_id_matches(quirk->device, dev->device) &&
2823                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2824                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2825                         break;
2826         return quirk;
2827 }
2828 
2829 static inline int get_pci_irq(struct pci_dev *dev,
2830                                 const struct pciserial_board *board)
2831 {
2832         if (board->flags & FL_NOIRQ)
2833                 return 0;
2834         else
2835                 return dev->irq;
2836 }
2837 
2838 /*
2839  * This is the configuration table for all of the PCI serial boards
2840  * which we support.  It is directly indexed by the pci_board_num_t enum
2841  * value, which is encoded in the pci_device_id PCI probe table's
2842  * driver_data member.
2843  *
2844  * The makeup of these names are:
2845  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2846  *
2847  *  bn          = PCI BAR number
2848  *  bt          = Index using PCI BARs
2849  *  n           = number of serial ports
2850  *  baud        = baud rate
2851  *  offsetinhex = offset for each sequential port (in hex)
2852  *
2853  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2854  *
2855  * Please note: in theory if n = 1, _bt infix should make no difference.
2856  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2857  */
2858 enum pci_board_num_t {
2859         pbn_default = 0,
2860 
2861         pbn_b0_1_115200,
2862         pbn_b0_2_115200,
2863         pbn_b0_4_115200,
2864         pbn_b0_5_115200,
2865         pbn_b0_8_115200,
2866 
2867         pbn_b0_1_921600,
2868         pbn_b0_2_921600,
2869         pbn_b0_4_921600,
2870 
2871         pbn_b0_2_1130000,
2872 
2873         pbn_b0_4_1152000,
2874 
2875         pbn_b0_2_1152000_200,
2876         pbn_b0_4_1152000_200,
2877         pbn_b0_8_1152000_200,
2878 
2879         pbn_b0_2_1843200,
2880         pbn_b0_4_1843200,
2881 
2882         pbn_b0_2_1843200_200,
2883         pbn_b0_4_1843200_200,
2884         pbn_b0_8_1843200_200,
2885 
2886         pbn_b0_1_4000000,
2887 
2888         pbn_b0_bt_1_115200,
2889         pbn_b0_bt_2_115200,
2890         pbn_b0_bt_4_115200,
2891         pbn_b0_bt_8_115200,
2892 
2893         pbn_b0_bt_1_460800,
2894         pbn_b0_bt_2_460800,
2895         pbn_b0_bt_4_460800,
2896 
2897         pbn_b0_bt_1_921600,
2898         pbn_b0_bt_2_921600,
2899         pbn_b0_bt_4_921600,
2900         pbn_b0_bt_8_921600,
2901 
2902         pbn_b1_1_115200,
2903         pbn_b1_2_115200,
2904         pbn_b1_4_115200,
2905         pbn_b1_8_115200,
2906         pbn_b1_16_115200,
2907 
2908         pbn_b1_1_921600,
2909         pbn_b1_2_921600,
2910         pbn_b1_4_921600,
2911         pbn_b1_8_921600,
2912 
2913         pbn_b1_2_1250000,
2914 
2915         pbn_b1_bt_1_115200,
2916         pbn_b1_bt_2_115200,
2917         pbn_b1_bt_4_115200,
2918 
2919         pbn_b1_bt_2_921600,
2920 
2921         pbn_b1_1_1382400,
2922         pbn_b1_2_1382400,
2923         pbn_b1_4_1382400,
2924         pbn_b1_8_1382400,
2925 
2926         pbn_b2_1_115200,
2927         pbn_b2_2_115200,
2928         pbn_b2_4_115200,
2929         pbn_b2_8_115200,
2930 
2931         pbn_b2_1_460800,
2932         pbn_b2_4_460800,
2933         pbn_b2_8_460800,
2934         pbn_b2_16_460800,
2935 
2936         pbn_b2_1_921600,
2937         pbn_b2_4_921600,
2938         pbn_b2_8_921600,
2939 
2940         pbn_b2_8_1152000,
2941 
2942         pbn_b2_bt_1_115200,
2943         pbn_b2_bt_2_115200,
2944         pbn_b2_bt_4_115200,
2945 
2946         pbn_b2_bt_2_921600,
2947         pbn_b2_bt_4_921600,
2948 
2949         pbn_b3_2_115200,
2950         pbn_b3_4_115200,
2951         pbn_b3_8_115200,
2952 
2953         pbn_b4_bt_2_921600,
2954         pbn_b4_bt_4_921600,
2955         pbn_b4_bt_8_921600,
2956 
2957         /*
2958          * Board-specific versions.
2959          */
2960         pbn_panacom,
2961         pbn_panacom2,
2962         pbn_panacom4,
2963         pbn_plx_romulus,
2964         pbn_endrun_2_4000000,
2965         pbn_oxsemi,
2966         pbn_oxsemi_1_4000000,
2967         pbn_oxsemi_2_4000000,
2968         pbn_oxsemi_4_4000000,
2969         pbn_oxsemi_8_4000000,
2970         pbn_intel_i960,
2971         pbn_sgi_ioc3,
2972         pbn_computone_4,
2973         pbn_computone_6,
2974         pbn_computone_8,
2975         pbn_sbsxrsio,
2976         pbn_exar_XR17C152,
2977         pbn_exar_XR17C154,
2978         pbn_exar_XR17C158,
2979         pbn_exar_XR17V352,
2980         pbn_exar_XR17V354,
2981         pbn_exar_XR17V358,
2982         pbn_exar_XR17V4358,
2983         pbn_exar_XR17V8358,
2984         pbn_exar_ibm_saturn,
2985         pbn_pasemi_1682M,
2986         pbn_ni8430_2,
2987         pbn_ni8430_4,
2988         pbn_ni8430_8,
2989         pbn_ni8430_16,
2990         pbn_ADDIDATA_PCIe_1_3906250,
2991         pbn_ADDIDATA_PCIe_2_3906250,
2992         pbn_ADDIDATA_PCIe_4_3906250,
2993         pbn_ADDIDATA_PCIe_8_3906250,
2994         pbn_ce4100_1_115200,
2995         pbn_byt,
2996         pbn_qrk,
2997         pbn_omegapci,
2998         pbn_NETMOS9900_2s_115200,
2999         pbn_brcm_trumanage,
3000         pbn_fintek_4,
3001         pbn_fintek_8,
3002         pbn_fintek_12,
3003         pbn_wch382_2,
3004         pbn_wch384_4,
3005         pbn_pericom_PI7C9X7951,
3006         pbn_pericom_PI7C9X7952,
3007         pbn_pericom_PI7C9X7954,
3008         pbn_pericom_PI7C9X7958,
3009 };
3010 
3011 /*
3012  * uart_offset - the space between channels
3013  * reg_shift   - describes how the UART registers are mapped
3014  *               to PCI memory by the card.
3015  * For example IER register on SBS, Inc. PMC-OctPro is located at
3016  * offset 0x10 from the UART base, while UART_IER is defined as 1
3017  * in include/linux/serial_reg.h,
3018  * see first lines of serial_in() and serial_out() in 8250.c
3019 */
3020 
3021 static struct pciserial_board pci_boards[] = {
3022         [pbn_default] = {
3023                 .flags          = FL_BASE0,
3024                 .num_ports      = 1,
3025                 .base_baud      = 115200,
3026                 .uart_offset    = 8,
3027         },
3028         [pbn_b0_1_115200] = {
3029                 .flags          = FL_BASE0,
3030                 .num_ports      = 1,
3031                 .base_baud      = 115200,
3032                 .uart_offset    = 8,
3033         },
3034         [pbn_b0_2_115200] = {
3035                 .flags          = FL_BASE0,
3036                 .num_ports      = 2,
3037                 .base_baud      = 115200,
3038                 .uart_offset    = 8,
3039         },
3040         [pbn_b0_4_115200] = {
3041                 .flags          = FL_BASE0,
3042                 .num_ports      = 4,
3043                 .base_baud      = 115200,
3044                 .uart_offset    = 8,
3045         },
3046         [pbn_b0_5_115200] = {
3047                 .flags          = FL_BASE0,
3048                 .num_ports      = 5,
3049                 .base_baud      = 115200,
3050                 .uart_offset    = 8,
3051         },
3052         [pbn_b0_8_115200] = {
3053                 .flags          = FL_BASE0,
3054                 .num_ports      = 8,
3055                 .base_baud      = 115200,
3056                 .uart_offset    = 8,
3057         },
3058         [pbn_b0_1_921600] = {
3059                 .flags          = FL_BASE0,
3060                 .num_ports      = 1,
3061                 .base_baud      = 921600,
3062                 .uart_offset    = 8,
3063         },
3064         [pbn_b0_2_921600] = {
3065                 .flags          = FL_BASE0,
3066                 .num_ports      = 2,
3067                 .base_baud      = 921600,
3068                 .uart_offset    = 8,
3069         },
3070         [pbn_b0_4_921600] = {
3071                 .flags          = FL_BASE0,
3072                 .num_ports      = 4,
3073                 .base_baud      = 921600,
3074                 .uart_offset    = 8,
3075         },
3076 
3077         [pbn_b0_2_1130000] = {
3078                 .flags          = FL_BASE0,
3079                 .num_ports      = 2,
3080                 .base_baud      = 1130000,
3081                 .uart_offset    = 8,
3082         },
3083 
3084         [pbn_b0_4_1152000] = {
3085                 .flags          = FL_BASE0,
3086                 .num_ports      = 4,
3087                 .base_baud      = 1152000,
3088                 .uart_offset    = 8,
3089         },
3090 
3091         [pbn_b0_2_1152000_200] = {
3092                 .flags          = FL_BASE0,
3093                 .num_ports      = 2,
3094                 .base_baud      = 1152000,
3095                 .uart_offset    = 0x200,
3096         },
3097 
3098         [pbn_b0_4_1152000_200] = {
3099                 .flags          = FL_BASE0,
3100                 .num_ports      = 4,
3101                 .base_baud      = 1152000,
3102                 .uart_offset    = 0x200,
3103         },
3104 
3105         [pbn_b0_8_1152000_200] = {
3106                 .flags          = FL_BASE0,
3107                 .num_ports      = 8,
3108                 .base_baud      = 1152000,
3109                 .uart_offset    = 0x200,
3110         },
3111 
3112         [pbn_b0_2_1843200] = {
3113                 .flags          = FL_BASE0,
3114                 .num_ports      = 2,
3115                 .base_baud      = 1843200,
3116                 .uart_offset    = 8,
3117         },
3118         [pbn_b0_4_1843200] = {
3119                 .flags          = FL_BASE0,
3120                 .num_ports      = 4,
3121                 .base_baud      = 1843200,
3122                 .uart_offset    = 8,
3123         },
3124 
3125         [pbn_b0_2_1843200_200] = {
3126                 .flags          = FL_BASE0,
3127                 .num_ports      = 2,
3128                 .base_baud      = 1843200,
3129                 .uart_offset    = 0x200,
3130         },
3131         [pbn_b0_4_1843200_200] = {
3132                 .flags          = FL_BASE0,
3133                 .num_ports      = 4,
3134                 .base_baud      = 1843200,
3135                 .uart_offset    = 0x200,
3136         },
3137         [pbn_b0_8_1843200_200] = {
3138                 .flags          = FL_BASE0,
3139                 .num_ports      = 8,
3140                 .base_baud      = 1843200,
3141                 .uart_offset    = 0x200,
3142         },
3143         [pbn_b0_1_4000000] = {
3144                 .flags          = FL_BASE0,
3145                 .num_ports      = 1,
3146                 .base_baud      = 4000000,
3147                 .uart_offset    = 8,
3148         },
3149 
3150         [pbn_b0_bt_1_115200] = {
3151                 .flags          = FL_BASE0|FL_BASE_BARS,
3152                 .num_ports      = 1,
3153                 .base_baud      = 115200,
3154                 .uart_offset    = 8,
3155         },
3156         [pbn_b0_bt_2_115200] = {
3157                 .flags          = FL_BASE0|FL_BASE_BARS,
3158                 .num_ports      = 2,
3159                 .base_baud      = 115200,
3160                 .uart_offset    = 8,
3161         },
3162         [pbn_b0_bt_4_115200] = {
3163                 .flags          = FL_BASE0|FL_BASE_BARS,
3164                 .num_ports      = 4,
3165                 .base_baud      = 115200,
3166                 .uart_offset    = 8,
3167         },
3168         [pbn_b0_bt_8_115200] = {
3169                 .flags          = FL_BASE0|FL_BASE_BARS,
3170                 .num_ports      = 8,
3171                 .base_baud      = 115200,
3172                 .uart_offset    = 8,
3173         },
3174 
3175         [pbn_b0_bt_1_460800] = {
3176                 .flags          = FL_BASE0|FL_BASE_BARS,
3177                 .num_ports      = 1,
3178                 .base_baud      = 460800,
3179                 .uart_offset    = 8,
3180         },
3181         [pbn_b0_bt_2_460800] = {
3182                 .flags          = FL_BASE0|FL_BASE_BARS,
3183                 .num_ports      = 2,
3184                 .base_baud      = 460800,
3185                 .uart_offset    = 8,
3186         },
3187         [pbn_b0_bt_4_460800] = {
3188                 .flags          = FL_BASE0|FL_BASE_BARS,
3189                 .num_ports      = 4,
3190                 .base_baud      = 460800,
3191                 .uart_offset    = 8,
3192         },
3193 
3194         [pbn_b0_bt_1_921600] = {
3195                 .flags          = FL_BASE0|FL_BASE_BARS,
3196                 .num_ports      = 1,
3197                 .base_baud      = 921600,
3198                 .uart_offset    = 8,
3199         },
3200         [pbn_b0_bt_2_921600] = {
3201                 .flags          = FL_BASE0|FL_BASE_BARS,
3202                 .num_ports      = 2,
3203                 .base_baud      = 921600,
3204                 .uart_offset    = 8,
3205         },
3206         [pbn_b0_bt_4_921600] = {
3207                 .flags          = FL_BASE0|FL_BASE_BARS,
3208                 .num_ports      = 4,
3209                 .base_baud      = 921600,
3210                 .uart_offset    = 8,
3211         },
3212         [pbn_b0_bt_8_921600] = {
3213                 .flags          = FL_BASE0|FL_BASE_BARS,
3214                 .num_ports      = 8,
3215                 .base_baud      = 921600,
3216                 .uart_offset    = 8,
3217         },
3218 
3219         [pbn_b1_1_115200] = {
3220                 .flags          = FL_BASE1,
3221                 .num_ports      = 1,
3222                 .base_baud      = 115200,
3223                 .uart_offset    = 8,
3224         },
3225         [pbn_b1_2_115200] = {
3226                 .flags          = FL_BASE1,
3227                 .num_ports      = 2,
3228                 .base_baud      = 115200,
3229                 .uart_offset    = 8,
3230         },
3231         [pbn_b1_4_115200] = {
3232                 .flags          = FL_BASE1,
3233                 .num_ports      = 4,
3234                 .base_baud      = 115200,
3235                 .uart_offset    = 8,
3236         },
3237         [pbn_b1_8_115200] = {
3238                 .flags          = FL_BASE1,
3239                 .num_ports      = 8,
3240                 .base_baud      = 115200,
3241                 .uart_offset    = 8,
3242         },
3243         [pbn_b1_16_115200] = {
3244                 .flags          = FL_BASE1,
3245                 .num_ports      = 16,
3246                 .base_baud      = 115200,
3247                 .uart_offset    = 8,
3248         },
3249 
3250         [pbn_b1_1_921600] = {
3251                 .flags          = FL_BASE1,
3252                 .num_ports      = 1,
3253                 .base_baud      = 921600,
3254                 .uart_offset    = 8,
3255         },
3256         [pbn_b1_2_921600] = {
3257                 .flags          = FL_BASE1,
3258                 .num_ports      = 2,
3259                 .base_baud      = 921600,
3260                 .uart_offset    = 8,
3261         },
3262         [pbn_b1_4_921600] = {
3263                 .flags          = FL_BASE1,
3264                 .num_ports      = 4,
3265                 .base_baud      = 921600,
3266                 .uart_offset    = 8,
3267         },
3268         [pbn_b1_8_921600] = {
3269                 .flags          = FL_BASE1,
3270                 .num_ports      = 8,
3271                 .base_baud      = 921600,
3272                 .uart_offset    = 8,
3273         },
3274         [pbn_b1_2_1250000] = {
3275                 .flags          = FL_BASE1,
3276                 .num_ports      = 2,
3277                 .base_baud      = 1250000,
3278                 .uart_offset    = 8,
3279         },
3280 
3281         [pbn_b1_bt_1_115200] = {
3282                 .flags          = FL_BASE1|FL_BASE_BARS,
3283                 .num_ports      = 1,
3284                 .base_baud      = 115200,
3285                 .uart_offset    = 8,
3286         },
3287         [pbn_b1_bt_2_115200] = {
3288                 .flags          = FL_BASE1|FL_BASE_BARS,
3289                 .num_ports      = 2,
3290                 .base_baud      = 115200,
3291                 .uart_offset    = 8,
3292         },
3293         [pbn_b1_bt_4_115200] = {
3294                 .flags          = FL_BASE1|FL_BASE_BARS,
3295                 .num_ports      = 4,
3296                 .base_baud      = 115200,
3297                 .uart_offset    = 8,
3298         },
3299 
3300         [pbn_b1_bt_2_921600] = {
3301                 .flags          = FL_BASE1|FL_BASE_BARS,
3302                 .num_ports      = 2,
3303                 .base_baud      = 921600,
3304                 .uart_offset    = 8,
3305         },
3306 
3307         [pbn_b1_1_1382400] = {
3308                 .flags          = FL_BASE1,
3309                 .num_ports      = 1,
3310                 .base_baud      = 1382400,
3311                 .uart_offset    = 8,
3312         },
3313         [pbn_b1_2_1382400] = {
3314                 .flags          = FL_BASE1,
3315                 .num_ports      = 2,
3316                 .base_baud      = 1382400,
3317                 .uart_offset    = 8,
3318         },
3319         [pbn_b1_4_1382400] = {
3320                 .flags          = FL_BASE1,
3321                 .num_ports      = 4,
3322                 .base_baud      = 1382400,
3323                 .uart_offset    = 8,
3324         },
3325         [pbn_b1_8_1382400] = {
3326                 .flags          = FL_BASE1,
3327                 .num_ports      = 8,
3328                 .base_baud      = 1382400,
3329                 .uart_offset    = 8,
3330         },
3331 
3332         [pbn_b2_1_115200] = {
3333                 .flags          = FL_BASE2,
3334                 .num_ports      = 1,
3335                 .base_baud      = 115200,
3336                 .uart_offset    = 8,
3337         },
3338         [pbn_b2_2_115200] = {
3339                 .flags          = FL_BASE2,
3340                 .num_ports      = 2,
3341                 .base_baud      = 115200,
3342                 .uart_offset    = 8,
3343         },
3344         [pbn_b2_4_115200] = {
3345                 .flags          = FL_BASE2,
3346                 .num_ports      = 4,
3347                 .base_baud      = 115200,
3348                 .uart_offset    = 8,
3349         },
3350         [pbn_b2_8_115200] = {
3351                 .flags          = FL_BASE2,
3352                 .num_ports      = 8,
3353                 .base_baud      = 115200,
3354                 .uart_offset    = 8,
3355         },
3356 
3357         [pbn_b2_1_460800] = {
3358                 .flags          = FL_BASE2,
3359                 .num_ports      = 1,
3360                 .base_baud      = 460800,
3361                 .uart_offset    = 8,
3362         },
3363         [pbn_b2_4_460800] = {
3364                 .flags          = FL_BASE2,
3365                 .num_ports      = 4,
3366                 .base_baud      = 460800,
3367                 .uart_offset    = 8,
3368         },
3369         [pbn_b2_8_460800] = {
3370                 .flags          = FL_BASE2,
3371                 .num_ports      = 8,
3372                 .base_baud      = 460800,
3373                 .uart_offset    = 8,
3374         },
3375         [pbn_b2_16_460800] = {
3376                 .flags          = FL_BASE2,
3377                 .num_ports      = 16,
3378                 .base_baud      = 460800,
3379                 .uart_offset    = 8,
3380          },
3381 
3382         [pbn_b2_1_921600] = {
3383                 .flags          = FL_BASE2,
3384                 .num_ports      = 1,
3385                 .base_baud      = 921600,
3386                 .uart_offset    = 8,
3387         },
3388         [pbn_b2_4_921600] = {
3389                 .flags          = FL_BASE2,
3390                 .num_ports      = 4,
3391                 .base_baud      = 921600,
3392                 .uart_offset    = 8,
3393         },
3394         [pbn_b2_8_921600] = {
3395                 .flags          = FL_BASE2,
3396                 .num_ports      = 8,
3397                 .base_baud      = 921600,
3398                 .uart_offset    = 8,
3399         },
3400 
3401         [pbn_b2_8_1152000] = {
3402                 .flags          = FL_BASE2,
3403                 .num_ports      = 8,
3404                 .base_baud      = 1152000,
3405                 .uart_offset    = 8,
3406         },
3407 
3408         [pbn_b2_bt_1_115200] = {
3409                 .flags          = FL_BASE2|FL_BASE_BARS,
3410                 .num_ports      = 1,
3411                 .base_baud      = 115200,
3412                 .uart_offset    = 8,
3413         },
3414         [pbn_b2_bt_2_115200] = {
3415                 .flags          = FL_BASE2|FL_BASE_BARS,
3416                 .num_ports      = 2,
3417                 .base_baud      = 115200,
3418                 .uart_offset    = 8,
3419         },
3420         [pbn_b2_bt_4_115200] = {
3421                 .flags          = FL_BASE2|FL_BASE_BARS,
3422                 .num_ports      = 4,
3423                 .base_baud      = 115200,
3424                 .uart_offset    = 8,
3425         },
3426 
3427         [pbn_b2_bt_2_921600] = {
3428                 .flags          = FL_BASE2|FL_BASE_BARS,
3429                 .num_ports      = 2,
3430                 .base_baud      = 921600,
3431                 .uart_offset    = 8,
3432         },
3433         [pbn_b2_bt_4_921600] = {
3434                 .flags          = FL_BASE2|FL_BASE_BARS,
3435                 .num_ports      = 4,
3436                 .base_baud      = 921600,
3437                 .uart_offset    = 8,
3438         },
3439 
3440         [pbn_b3_2_115200] = {
3441                 .flags          = FL_BASE3,
3442                 .num_ports      = 2,
3443                 .base_baud      = 115200,
3444                 .uart_offset    = 8,
3445         },
3446         [pbn_b3_4_115200] = {
3447                 .flags          = FL_BASE3,
3448                 .num_ports      = 4,
3449                 .base_baud      = 115200,
3450                 .uart_offset    = 8,
3451         },
3452         [pbn_b3_8_115200] = {
3453                 .flags          = FL_BASE3,
3454                 .num_ports      = 8,
3455                 .base_baud      = 115200,
3456                 .uart_offset    = 8,
3457         },
3458 
3459         [pbn_b4_bt_2_921600] = {
3460                 .flags          = FL_BASE4,
3461                 .num_ports      = 2,
3462                 .base_baud      = 921600,
3463                 .uart_offset    = 8,
3464         },
3465         [pbn_b4_bt_4_921600] = {
3466                 .flags          = FL_BASE4,
3467                 .num_ports      = 4,
3468                 .base_baud      = 921600,
3469                 .uart_offset    = 8,
3470         },
3471         [pbn_b4_bt_8_921600] = {
3472                 .flags          = FL_BASE4,
3473                 .num_ports      = 8,
3474                 .base_baud      = 921600,
3475                 .uart_offset    = 8,
3476         },
3477 
3478         /*
3479          * Entries following this are board-specific.
3480          */
3481 
3482         /*
3483          * Panacom - IOMEM
3484          */
3485         [pbn_panacom] = {
3486                 .flags          = FL_BASE2,
3487                 .num_ports      = 2,
3488                 .base_baud      = 921600,
3489                 .uart_offset    = 0x400,
3490                 .reg_shift      = 7,
3491         },
3492         [pbn_panacom2] = {
3493                 .flags          = FL_BASE2|FL_BASE_BARS,
3494                 .num_ports      = 2,
3495                 .base_baud      = 921600,
3496                 .uart_offset    = 0x400,
3497                 .reg_shift      = 7,
3498         },
3499         [pbn_panacom4] = {
3500                 .flags          = FL_BASE2|FL_BASE_BARS,
3501                 .num_ports      = 4,
3502                 .base_baud      = 921600,
3503                 .uart_offset    = 0x400,
3504                 .reg_shift      = 7,
3505         },
3506 
3507         /* I think this entry is broken - the first_offset looks wrong --rmk */
3508         [pbn_plx_romulus] = {
3509                 .flags          = FL_BASE2,
3510                 .num_ports      = 4,
3511                 .base_baud      = 921600,
3512                 .uart_offset    = 8 << 2,
3513                 .reg_shift      = 2,
3514                 .first_offset   = 0x03,
3515         },
3516 
3517         /*
3518          * EndRun Technologies
3519         * Uses the size of PCI Base region 0 to
3520         * signal now many ports are available
3521         * 2 port 952 Uart support
3522         */
3523         [pbn_endrun_2_4000000] = {
3524                 .flags          = FL_BASE0,
3525                 .num_ports      = 2,
3526                 .base_baud      = 4000000,
3527                 .uart_offset    = 0x200,
3528                 .first_offset   = 0x1000,
3529         },
3530 
3531         /*
3532          * This board uses the size of PCI Base region 0 to
3533          * signal now many ports are available
3534          */
3535         [pbn_oxsemi] = {
3536                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3537                 .num_ports      = 32,
3538                 .base_baud      = 115200,
3539                 .uart_offset    = 8,
3540         },
3541         [pbn_oxsemi_1_4000000] = {
3542                 .flags          = FL_BASE0,
3543                 .num_ports      = 1,
3544                 .base_baud      = 4000000,
3545                 .uart_offset    = 0x200,
3546                 .first_offset   = 0x1000,
3547         },
3548         [pbn_oxsemi_2_4000000] = {
3549                 .flags          = FL_BASE0,
3550                 .num_ports      = 2,
3551                 .base_baud      = 4000000,
3552                 .uart_offset    = 0x200,
3553                 .first_offset   = 0x1000,
3554         },
3555         [pbn_oxsemi_4_4000000] = {
3556                 .flags          = FL_BASE0,
3557                 .num_ports      = 4,
3558                 .base_baud      = 4000000,
3559                 .uart_offset    = 0x200,
3560                 .first_offset   = 0x1000,
3561         },
3562         [pbn_oxsemi_8_4000000] = {
3563                 .flags          = FL_BASE0,
3564                 .num_ports      = 8,
3565                 .base_baud      = 4000000,
3566                 .uart_offset    = 0x200,
3567                 .first_offset   = 0x1000,
3568         },
3569 
3570 
3571         /*
3572          * EKF addition for i960 Boards form EKF with serial port.
3573          * Max 256 ports.
3574          */
3575         [pbn_intel_i960] = {
3576                 .flags          = FL_BASE0,
3577                 .num_ports      = 32,
3578                 .base_baud      = 921600,
3579                 .uart_offset    = 8 << 2,
3580                 .reg_shift      = 2,
3581                 .first_offset   = 0x10000,
3582         },
3583         [pbn_sgi_ioc3] = {
3584                 .flags          = FL_BASE0|FL_NOIRQ,
3585                 .num_ports      = 1,
3586                 .base_baud      = 458333,
3587                 .uart_offset    = 8,
3588                 .reg_shift      = 0,
3589                 .first_offset   = 0x20178,
3590         },
3591 
3592         /*
3593          * Computone - uses IOMEM.
3594          */
3595         [pbn_computone_4] = {
3596                 .flags          = FL_BASE0,
3597                 .num_ports      = 4,
3598                 .base_baud      = 921600,
3599                 .uart_offset    = 0x40,
3600                 .reg_shift      = 2,
3601                 .first_offset   = 0x200,
3602         },
3603         [pbn_computone_6] = {
3604                 .flags          = FL_BASE0,
3605                 .num_ports      = 6,
3606                 .base_baud      = 921600,
3607                 .uart_offset    = 0x40,
3608                 .reg_shift      = 2,
3609                 .first_offset   = 0x200,
3610         },
3611         [pbn_computone_8] = {
3612                 .flags          = FL_BASE0,
3613                 .num_ports      = 8,
3614                 .base_baud      = 921600,
3615                 .uart_offset    = 0x40,
3616                 .reg_shift      = 2,
3617                 .first_offset   = 0x200,
3618         },
3619         [pbn_sbsxrsio] = {
3620                 .flags          = FL_BASE0,
3621                 .num_ports      = 8,
3622                 .base_baud      = 460800,
3623                 .uart_offset    = 256,
3624                 .reg_shift      = 4,
3625         },
3626         /*
3627          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3628          *  Only basic 16550A support.
3629          *  XR17C15[24] are not tested, but they should work.
3630          */
3631         [pbn_exar_XR17C152] = {
3632                 .flags          = FL_BASE0,
3633                 .num_ports      = 2,
3634                 .base_baud      = 921600,
3635                 .uart_offset    = 0x200,
3636         },
3637         [pbn_exar_XR17C154] = {
3638                 .flags          = FL_BASE0,
3639                 .num_ports      = 4,
3640                 .base_baud      = 921600,
3641                 .uart_offset    = 0x200,
3642         },
3643         [pbn_exar_XR17C158] = {
3644                 .flags          = FL_BASE0,
3645                 .num_ports      = 8,
3646                 .base_baud      = 921600,
3647                 .uart_offset    = 0x200,
3648         },
3649         [pbn_exar_XR17V352] = {
3650                 .flags          = FL_BASE0,
3651                 .num_ports      = 2,
3652                 .base_baud      = 7812500,
3653                 .uart_offset    = 0x400,
3654                 .reg_shift      = 0,
3655                 .first_offset   = 0,
3656         },
3657         [pbn_exar_XR17V354] = {
3658                 .flags          = FL_BASE0,
3659                 .num_ports      = 4,
3660                 .base_baud      = 7812500,
3661                 .uart_offset    = 0x400,
3662                 .reg_shift      = 0,
3663                 .first_offset   = 0,
3664         },
3665         [pbn_exar_XR17V358] = {
3666                 .flags          = FL_BASE0,
3667                 .num_ports      = 8,
3668                 .base_baud      = 7812500,
3669                 .uart_offset    = 0x400,
3670                 .reg_shift      = 0,
3671                 .first_offset   = 0,
3672         },
3673         [pbn_exar_XR17V4358] = {
3674                 .flags          = FL_BASE0,
3675                 .num_ports      = 12,
3676                 .base_baud      = 7812500,
3677                 .uart_offset    = 0x400,
3678                 .reg_shift      = 0,
3679                 .first_offset   = 0,
3680         },
3681         [pbn_exar_XR17V8358] = {
3682                 .flags          = FL_BASE0,
3683                 .num_ports      = 16,
3684                 .base_baud      = 7812500,
3685                 .uart_offset    = 0x400,
3686                 .reg_shift      = 0,
3687                 .first_offset   = 0,
3688         },
3689         [pbn_exar_ibm_saturn] = {
3690                 .flags          = FL_BASE0,
3691                 .num_ports      = 1,
3692                 .base_baud      = 921600,
3693                 .uart_offset    = 0x200,
3694         },
3695 
3696         /*
3697          * PA Semi PWRficient PA6T-1682M on-chip UART
3698          */
3699         [pbn_pasemi_1682M] = {
3700                 .flags          = FL_BASE0,
3701                 .num_ports      = 1,
3702                 .base_baud      = 8333333,
3703         },
3704         /*
3705          * National Instruments 843x
3706          */
3707         [pbn_ni8430_16] = {
3708                 .flags          = FL_BASE0,
3709                 .num_ports      = 16,
3710                 .base_baud      = 3686400,
3711                 .uart_offset    = 0x10,
3712                 .first_offset   = 0x800,
3713         },
3714         [pbn_ni8430_8] = {
3715                 .flags          = FL_BASE0,
3716                 .num_ports      = 8,
3717                 .base_baud      = 3686400,
3718                 .uart_offset    = 0x10,
3719                 .first_offset   = 0x800,
3720         },
3721         [pbn_ni8430_4] = {
3722                 .flags          = FL_BASE0,
3723                 .num_ports      = 4,
3724                 .base_baud      = 3686400,
3725                 .uart_offset    = 0x10,
3726                 .first_offset   = 0x800,
3727         },
3728         [pbn_ni8430_2] = {
3729                 .flags          = FL_BASE0,
3730                 .num_ports      = 2,
3731                 .base_baud      = 3686400,
3732                 .uart_offset    = 0x10,
3733                 .first_offset   = 0x800,
3734         },
3735         /*
3736          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3737          */
3738         [pbn_ADDIDATA_PCIe_1_3906250] = {
3739                 .flags          = FL_BASE0,
3740                 .num_ports      = 1,
3741                 .base_baud      = 3906250,
3742                 .uart_offset    = 0x200,
3743                 .first_offset   = 0x1000,
3744         },
3745         [pbn_ADDIDATA_PCIe_2_3906250] = {
3746                 .flags          = FL_BASE0,
3747                 .num_ports      = 2,
3748                 .base_baud      = 3906250,
3749                 .uart_offset    = 0x200,
3750                 .first_offset   = 0x1000,
3751         },
3752         [pbn_ADDIDATA_PCIe_4_3906250] = {
3753                 .flags          = FL_BASE0,
3754                 .num_ports      = 4,
3755                 .base_baud      = 3906250,
3756                 .uart_offset    = 0x200,
3757                 .first_offset   = 0x1000,
3758         },
3759         [pbn_ADDIDATA_PCIe_8_3906250] = {
3760                 .flags          = FL_BASE0,
3761                 .num_ports      = 8,
3762                 .base_baud      = 3906250,
3763                 .uart_offset    = 0x200,
3764                 .first_offset   = 0x1000,
3765         },
3766         [pbn_ce4100_1_115200] = {
3767                 .flags          = FL_BASE_BARS,
3768                 .num_ports      = 2,
3769                 .base_baud      = 921600,
3770                 .reg_shift      = 2,
3771         },
3772         [pbn_byt] = {
3773                 .flags          = FL_BASE0,
3774                 .num_ports      = 1,
3775                 .base_baud      = 2764800,
3776                 .reg_shift      = 2,
3777         },
3778         [pbn_qrk] = {
3779                 .flags          = FL_BASE0,
3780                 .num_ports      = 1,
3781                 .base_baud      = 2764800,
3782                 .reg_shift      = 2,
3783         },
3784         [pbn_omegapci] = {
3785                 .flags          = FL_BASE0,
3786                 .num_ports      = 8,
3787                 .base_baud      = 115200,
3788                 .uart_offset    = 0x200,
3789         },
3790         [pbn_NETMOS9900_2s_115200] = {
3791                 .flags          = FL_BASE0,
3792                 .num_ports      = 2,
3793                 .base_baud      = 115200,
3794         },
3795         [pbn_brcm_trumanage] = {
3796                 .flags          = FL_BASE0,
3797                 .num_ports      = 1,
3798                 .reg_shift      = 2,
3799                 .base_baud      = 115200,
3800         },
3801         [pbn_fintek_4] = {
3802                 .num_ports      = 4,
3803                 .uart_offset    = 8,
3804                 .base_baud      = 115200,
3805                 .first_offset   = 0x40,
3806         },
3807         [pbn_fintek_8] = {
3808                 .num_ports      = 8,
3809                 .uart_offset    = 8,
3810                 .base_baud      = 115200,
3811                 .first_offset   = 0x40,
3812         },
3813         [pbn_fintek_12] = {
3814                 .num_ports      = 12,
3815                 .uart_offset    = 8,
3816                 .base_baud      = 115200,
3817                 .first_offset   = 0x40,
3818         },
3819         [pbn_wch382_2] = {
3820                 .flags          = FL_BASE0,
3821                 .num_ports      = 2,
3822                 .base_baud      = 115200,
3823                 .uart_offset    = 8,
3824                 .first_offset   = 0xC0,
3825         },
3826         [pbn_wch384_4] = {
3827                 .flags          = FL_BASE0,
3828                 .num_ports      = 4,
3829                 .base_baud      = 115200,
3830                 .uart_offset    = 8,
3831                 .first_offset   = 0xC0,
3832         },
3833         /*
3834          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3835          */
3836         [pbn_pericom_PI7C9X7951] = {
3837                 .flags          = FL_BASE0,
3838                 .num_ports      = 1,
3839                 .base_baud      = 921600,
3840                 .uart_offset    = 0x8,
3841         },
3842         [pbn_pericom_PI7C9X7952] = {
3843                 .flags          = FL_BASE0,
3844                 .num_ports      = 2,
3845                 .base_baud      = 921600,
3846                 .uart_offset    = 0x8,
3847         },
3848         [pbn_pericom_PI7C9X7954] = {
3849                 .flags          = FL_BASE0,
3850                 .num_ports      = 4,
3851                 .base_baud      = 921600,
3852                 .uart_offset    = 0x8,
3853         },
3854         [pbn_pericom_PI7C9X7958] = {
3855                 .flags          = FL_BASE0,
3856                 .num_ports      = 8,
3857                 .base_baud      = 921600,
3858                 .uart_offset    = 0x8,
3859         },
3860 };
3861 
3862 static const struct pci_device_id blacklist[] = {
3863         /* softmodems */
3864         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3865         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3866         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3867 
3868         /* multi-io cards handled by parport_serial */
3869         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3870         { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3871         { PCI_DEVICE(0x4348, 0x7173), }, /* WCH CH355 4S */
3872         { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3873         { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3874 
3875         /* Moxa Smartio MUE boards handled by 8250_moxa */
3876         { PCI_VDEVICE(MOXA, 0x1024), },
3877         { PCI_VDEVICE(MOXA, 0x1025), },
3878         { PCI_VDEVICE(MOXA, 0x1045), },
3879         { PCI_VDEVICE(MOXA, 0x1144), },
3880         { PCI_VDEVICE(MOXA, 0x1160), },
3881         { PCI_VDEVICE(MOXA, 0x1161), },
3882         { PCI_VDEVICE(MOXA, 0x1182), },
3883         { PCI_VDEVICE(MOXA, 0x1183), },
3884         { PCI_VDEVICE(MOXA, 0x1322), },
3885         { PCI_VDEVICE(MOXA, 0x1342), },
3886         { PCI_VDEVICE(MOXA, 0x1381), },
3887         { PCI_VDEVICE(MOXA, 0x1683), },
3888 
3889         /* Intel platforms with MID UART */
3890         { PCI_VDEVICE(INTEL, 0x081b), },
3891         { PCI_VDEVICE(INTEL, 0x081c), },
3892         { PCI_VDEVICE(INTEL, 0x081d), },
3893         { PCI_VDEVICE(INTEL, 0x1191), },
3894         { PCI_VDEVICE(INTEL, 0x19d8), },
3895 };
3896 
3897 /*
3898  * Given a complete unknown PCI device, try to use some heuristics to
3899  * guess what the configuration might be, based on the pitiful PCI
3900  * serial specs.  Returns 0 on success, 1 on failure.
3901  */
3902 static int
3903 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3904 {
3905         const struct pci_device_id *bldev;
3906         int num_iomem, num_port, first_port = -1, i;
3907 
3908         /*
3909          * If it is not a communications device or the programming
3910          * interface is greater than 6, give up.
3911          *
3912          * (Should we try to make guesses for multiport serial devices
3913          * later?)
3914          */
3915         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3916              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3917             (dev->class & 0xff) > 6)
3918                 return -ENODEV;
3919 
3920         /*
3921          * Do not access blacklisted devices that are known not to
3922          * feature serial ports or are handled by other modules.
3923          */
3924         for (bldev = blacklist;
3925              bldev < blacklist + ARRAY_SIZE(blacklist);
3926              bldev++) {
3927                 if (dev->vendor == bldev->vendor &&
3928                     dev->device == bldev->device)
3929                         return -ENODEV;
3930         }
3931 
3932         num_iomem = num_port = 0;
3933         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3934                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3935                         num_port++;
3936                         if (first_port == -1)
3937                                 first_port = i;
3938                 }
3939                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3940                         num_iomem++;
3941         }
3942 
3943         /*
3944          * If there is 1 or 0 iomem regions, and exactly one port,
3945          * use it.  We guess the number of ports based on the IO
3946          * region size.
3947          */
3948         if (num_iomem <= 1 && num_port == 1) {
3949                 board->flags = first_port;
3950                 board->num_ports = pci_resource_len(dev, first_port) / 8;
3951                 return 0;
3952         }
3953 
3954         /*
3955          * Now guess if we've got a board which indexes by BARs.
3956          * Each IO BAR should be 8 bytes, and they should follow
3957          * consecutively.
3958          */
3959         first_port = -1;
3960         num_port = 0;
3961         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3962                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3963                     pci_resource_len(dev, i) == 8 &&
3964                     (first_port == -1 || (first_port + num_port) == i)) {
3965                         num_port++;
3966                         if (first_port == -1)
3967                                 first_port = i;
3968                 }
3969         }
3970 
3971         if (num_port > 1) {
3972                 board->flags = first_port | FL_BASE_BARS;
3973                 board->num_ports = num_port;
3974                 return 0;
3975         }
3976 
3977         return -ENODEV;
3978 }
3979 
3980 static inline int
3981 serial_pci_matches(const struct pciserial_board *board,
3982                    const struct pciserial_board *guessed)
3983 {
3984         return
3985             board->num_ports == guessed->num_ports &&
3986             board->base_baud == guessed->base_baud &&
3987             board->uart_offset == guessed->uart_offset &&
3988             board->reg_shift == guessed->reg_shift &&
3989             board->first_offset == guessed->first_offset;
3990 }
3991 
3992 struct serial_private *
3993 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3994 {
3995         struct uart_8250_port uart;
3996         struct serial_private *priv;
3997         struct pci_serial_quirk *quirk;
3998         int rc, nr_ports, i;
3999 
4000         nr_ports = board->num_ports;
4001 
4002         /*
4003          * Find an init and setup quirks.
4004          */
4005         quirk = find_quirk(dev);
4006 
4007         /*
4008          * Run the new-style initialization function.
4009          * The initialization function returns:
4010          *  <0  - error
4011          *   0  - use board->num_ports
4012          *  >0  - number of ports
4013          */
4014         if (quirk->init) {
4015                 rc = quirk->init(dev);
4016                 if (rc < 0) {
4017                         priv = ERR_PTR(rc);
4018                         goto err_out;
4019                 }
4020                 if (rc)
4021                         nr_ports = rc;
4022         }
4023 
4024         priv = kzalloc(sizeof(struct serial_private) +
4025                        sizeof(unsigned int) * nr_ports,
4026                        GFP_KERNEL);
4027         if (!priv) {
4028                 priv = ERR_PTR(-ENOMEM);
4029                 goto err_deinit;
4030         }
4031 
4032         priv->dev = dev;
4033         priv->quirk = quirk;
4034 
4035         memset(&uart, 0, sizeof(uart));
4036         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4037         uart.port.uartclk = board->base_baud * 16;
4038         uart.port.irq = get_pci_irq(dev, board);
4039         uart.port.dev = &dev->dev;
4040 
4041         for (i = 0; i < nr_ports; i++) {
4042                 if (quirk->setup(priv, board, &uart, i))
4043                         break;
4044 
4045                 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4046                         uart.port.iobase, uart.port.irq, uart.port.iotype);
4047 
4048                 priv->line[i] = serial8250_register_8250_port(&uart);
4049                 if (priv->line[i] < 0) {
4050                         dev_err(&dev->dev,
4051                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4052                                 uart.port.iobase, uart.port.irq,
4053                                 uart.port.iotype, priv->line[i]);
4054                         break;
4055                 }
4056         }
4057         priv->nr = i;
4058         return priv;
4059 
4060 err_deinit:
4061         if (quirk->exit)
4062                 quirk->exit(dev);
4063 err_out:
4064         return priv;
4065 }
4066 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4067 
4068 void pciserial_remove_ports(struct serial_private *priv)
4069 {
4070         struct pci_serial_quirk *quirk;
4071         int i;
4072 
4073         for (i = 0; i < priv->nr; i++)
4074                 serial8250_unregister_port(priv->line[i]);
4075 
4076         /*
4077          * Find the exit quirks.
4078          */
4079         quirk = find_quirk(priv->dev);
4080         if (quirk->exit)
4081                 quirk->exit(priv->dev);
4082 
4083         kfree(priv);
4084 }
4085 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4086 
4087 void pciserial_suspend_ports(struct serial_private *priv)
4088 {
4089         int i;
4090 
4091         for (i = 0; i < priv->nr; i++)
4092                 if (priv->line[i] >= 0)
4093                         serial8250_suspend_port(priv->line[i]);
4094 
4095         /*
4096          * Ensure that every init quirk is properly torn down
4097          */
4098         if (priv->quirk->exit)
4099                 priv->quirk->exit(priv->dev);
4100 }
4101 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4102 
4103 void pciserial_resume_ports(struct serial_private *priv)
4104 {
4105         int i;
4106 
4107         /*
4108          * Ensure that the board is correctly configured.
4109          */
4110         if (priv->quirk->init)
4111                 priv->quirk->init(priv->dev);
4112 
4113         for (i = 0; i < priv->nr; i++)
4114                 if (priv->line[i] >= 0)
4115                         serial8250_resume_port(priv->line[i]);
4116 }
4117 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4118 
4119 /*
4120  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
4121  * to the arrangement of serial ports on a PCI card.
4122  */
4123 static int
4124 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4125 {
4126         struct pci_serial_quirk *quirk;
4127         struct serial_private *priv;
4128         const struct pciserial_board *board;
4129         struct pciserial_board tmp;
4130         int rc;
4131 
4132         quirk = find_quirk(dev);
4133         if (quirk->probe) {
4134                 rc = quirk->probe(dev);
4135                 if (rc)
4136                         return rc;
4137         }
4138 
4139         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4140                 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4141                         ent->driver_data);
4142                 return -EINVAL;
4143         }
4144 
4145         board = &pci_boards[ent->driver_data];
4146 
4147         rc = pcim_enable_device(dev);
4148         pci_save_state(dev);
4149         if (rc)
4150                 return rc;
4151 
4152         if (ent->driver_data == pbn_default) {
4153                 /*
4154                  * Use a copy of the pci_board entry for this;
4155                  * avoid changing entries in the table.
4156                  */
4157                 memcpy(&tmp, board, sizeof(struct pciserial_board));
4158                 board = &tmp;
4159 
4160                 /*
4161                  * We matched one of our class entries.  Try to
4162                  * determine the parameters of this board.
4163                  */
4164                 rc = serial_pci_guess_board(dev, &tmp);
4165                 if (rc)
4166                         return rc;
4167         } else {
4168                 /*
4169                  * We matched an explicit entry.  If we are able to
4170                  * detect this boards settings with our heuristic,
4171                  * then we no longer need this entry.
4172                  */
4173                 memcpy(&tmp, &pci_boards[pbn_default],
4174                        sizeof(struct pciserial_board));
4175                 rc = serial_pci_guess_board(dev, &tmp);
4176                 if (rc == 0 && serial_pci_matches(board, &tmp))
4177                         moan_device("Redundant entry in serial pci_table.",
4178                                     dev);
4179         }
4180 
4181         priv = pciserial_init_ports(dev, board);
4182         if (IS_ERR(priv))
4183                 return PTR_ERR(priv);
4184 
4185         pci_set_drvdata(dev, priv);
4186         return 0;
4187 }
4188 
4189 static void pciserial_remove_one(struct pci_dev *dev)
4190 {
4191         struct serial_private *priv = pci_get_drvdata(dev);
4192 
4193         pciserial_remove_ports(priv);
4194 }
4195 
4196 #ifdef CONFIG_PM_SLEEP
4197 static int pciserial_suspend_one(struct device *dev)
4198 {
4199         struct pci_dev *pdev = to_pci_dev(dev);
4200         struct serial_private *priv = pci_get_drvdata(pdev);
4201 
4202         if (priv)
4203                 pciserial_suspend_ports(priv);
4204 
4205         return 0;
4206 }
4207 
4208 static int pciserial_resume_one(struct device *dev)
4209 {
4210         struct pci_dev *pdev = to_pci_dev(dev);
4211         struct serial_private *priv = pci_get_drvdata(pdev);
4212         int err;
4213 
4214         if (priv) {
4215                 /*
4216                  * The device may have been disabled.  Re-enable it.
4217                  */
4218                 err = pci_enable_device(pdev);
4219                 /* FIXME: We cannot simply error out here */
4220                 if (err)
4221                         dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4222                 pciserial_resume_ports(priv);
4223         }
4224         return 0;
4225 }
4226 #endif
4227 
4228 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4229                          pciserial_resume_one);
4230 
4231 static struct pci_device_id serial_pci_tbl[] = {
4232         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4233         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4234                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4235                 pbn_b2_8_921600 },
4236         /* Advantech also use 0x3618 and 0xf618 */
4237         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4238                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4239                 pbn_b0_4_921600 },
4240         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4241                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4242                 pbn_b0_4_921600 },
4243         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4244                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4245                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4246                 pbn_b1_8_1382400 },
4247         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4248                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4249                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4250                 pbn_b1_4_1382400 },
4251         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4252                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4253                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4254                 pbn_b1_2_1382400 },
4255         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4256                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4257                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4258                 pbn_b1_8_1382400 },
4259         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4260                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4261                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4262                 pbn_b1_4_1382400 },
4263         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4264                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4265                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4266                 pbn_b1_2_1382400 },
4267         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4268                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4269                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4270                 pbn_b1_8_921600 },
4271         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4272                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4273                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4274                 pbn_b1_8_921600 },
4275         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4276                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4277                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4278                 pbn_b1_4_921600 },
4279         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4280                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4281                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4282                 pbn_b1_4_921600 },
4283         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4284                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4285                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4286                 pbn_b1_2_921600 },
4287         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4288                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4289                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4290                 pbn_b1_8_921600 },
4291         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4292                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4293                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4294                 pbn_b1_8_921600 },
4295         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4296                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4297                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4298                 pbn_b1_4_921600 },
4299         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4300                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4301                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4302                 pbn_b1_2_1250000 },
4303         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4304                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4305                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4306                 pbn_b0_2_1843200 },
4307         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4308                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4309                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4310                 pbn_b0_4_1843200 },
4311         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4312                 PCI_VENDOR_ID_AFAVLAB,
4313                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4314                 pbn_b0_4_1152000 },
4315         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4316                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4317                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4318                 pbn_b0_2_1843200_200 },
4319         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4320                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4321                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4322                 pbn_b0_4_1843200_200 },
4323         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4324                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4325                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4326                 pbn_b0_8_1843200_200 },
4327         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4328                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4329                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4330                 pbn_b0_2_1843200_200 },
4331         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4332                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4333                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4334                 pbn_b0_4_1843200_200 },
4335         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4336                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4337                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4338                 pbn_b0_8_1843200_200 },
4339         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4340                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4341                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4342                 pbn_b0_2_1843200_200 },
4343         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4344                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4345                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4346                 pbn_b0_4_1843200_200 },
4347         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4348                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4349                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4350                 pbn_b0_8_1843200_200 },
4351         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4352                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4353                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4354                 pbn_b0_2_1843200_200 },
4355         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4356                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4357                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4358                 pbn_b0_4_1843200_200 },
4359         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4360                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4361                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4362                 pbn_b0_8_1843200_200 },
4363         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4364                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4365                 0, 0, pbn_exar_ibm_saturn },
4366 
4367         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4368                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4369                 pbn_b2_bt_1_115200 },
4370         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4371                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4372                 pbn_b2_bt_2_115200 },
4373         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4374                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4375                 pbn_b2_bt_4_115200 },
4376         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4377                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4378                 pbn_b2_bt_2_115200 },
4379         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4380                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4381                 pbn_b2_bt_4_115200 },
4382         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4383                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4384                 pbn_b2_8_115200 },
4385         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4386                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4387                 pbn_b2_8_460800 },
4388         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4389                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4390                 pbn_b2_8_115200 },
4391 
4392         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4393                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4394                 pbn_b2_bt_2_115200 },
4395         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4396                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4397                 pbn_b2_bt_2_921600 },
4398         /*
4399          * VScom SPCOM800, from sl@s.pl
4400          */
4401         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4402                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403                 pbn_b2_8_921600 },
4404         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4405                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406                 pbn_b2_4_921600 },
4407         /* Unknown card - subdevice 0x1584 */
4408         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4409                 PCI_VENDOR_ID_PLX,
4410                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4411                 pbn_b2_4_115200 },
4412         /* Unknown card - subdevice 0x1588 */
4413         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4414                 PCI_VENDOR_ID_PLX,
4415                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4416                 pbn_b2_8_115200 },
4417         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4418                 PCI_SUBVENDOR_ID_KEYSPAN,
4419                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4420                 pbn_panacom },
4421         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4422                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4423                 pbn_panacom4 },
4424         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4425                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4426                 pbn_panacom2 },
4427         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4428                 PCI_VENDOR_ID_ESDGMBH,
4429                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4430                 pbn_b2_4_115200 },
4431         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4432                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4433                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4434                 pbn_b2_4_460800 },
4435         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4436                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4437                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4438                 pbn_b2_8_460800 },
4439         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4440                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4441                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4442                 pbn_b2_16_460800 },
4443         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4444                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4445                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4446                 pbn_b2_16_460800 },
4447         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4448                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4449                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4450                 pbn_b2_4_460800 },
4451         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4452                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4453                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4454                 pbn_b2_8_460800 },
4455         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4456                 PCI_SUBVENDOR_ID_EXSYS,
4457                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4458                 pbn_b2_4_115200 },
4459         /*
4460          * Megawolf Romulus PCI Serial Card, from Mike Hudson
4461          * (Exoray@isys.ca)
4462          */
4463         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4464                 0x10b5, 0x106a, 0, 0,
4465                 pbn_plx_romulus },
4466         /*
4467         * EndRun Technologies. PCI express device range.
4468         *    EndRun PTP/1588 has 2 Native UARTs.
4469         */
4470         {       PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4471                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4472                 pbn_endrun_2_4000000 },
4473         /*
4474          * Quatech cards. These actually have configurable clocks but for
4475          * now we just use the default.
4476          *
4477          * 100 series are RS232, 200 series RS422,
4478          */
4479         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4480                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4481                 pbn_b1_4_115200 },
4482         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4483                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4484                 pbn_b1_2_115200 },
4485         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4486                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487                 pbn_b2_2_115200 },
4488         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4489                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490                 pbn_b1_2_115200 },
4491         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4492                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4493                 pbn_b2_2_115200 },
4494         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4495                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496                 pbn_b1_4_115200 },
4497         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4498                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4499                 pbn_b1_8_115200 },
4500         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4501                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4502                 pbn_b1_8_115200 },
4503         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4504                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4505                 pbn_b1_4_115200 },
4506         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4507                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4508                 pbn_b1_2_115200 },
4509         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4510                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4511                 pbn_b1_4_115200 },
4512         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4513                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514                 pbn_b1_2_115200 },
4515         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4516                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517                 pbn_b2_4_115200 },
4518         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4519                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4520                 pbn_b2_2_115200 },
4521         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4522                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4523                 pbn_b2_1_115200 },
4524         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4525                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4526                 pbn_b2_4_115200 },
4527         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4528                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4529                 pbn_b2_2_115200 },
4530         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4531                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532                 pbn_b2_1_115200 },
4533         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4534                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535                 pbn_b0_8_115200 },
4536 
4537         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4538                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4539                 0, 0,
4540                 pbn_b0_4_921600 },
4541         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4542                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4543                 0, 0,
4544                 pbn_b0_4_1152000 },
4545         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
4546                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547                 pbn_b0_bt_2_921600 },
4548 
4549                 /*
4550                  * The below card is a little controversial since it is the
4551                  * subject of a PCI vendor/device ID clash.  (See
4552                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4553                  * For now just used the hex ID 0x950a.
4554                  */
4555         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4556                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4557                 0, 0, pbn_b0_2_115200 },
4558         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4559                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4560                 0, 0, pbn_b0_2_115200 },
4561         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4562                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4563                 pbn_b0_2_1130000 },
4564         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4565                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4566                 pbn_b0_1_921600 },
4567         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4568                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4569                 pbn_b0_4_115200 },
4570         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4571                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4572                 pbn_b0_bt_2_921600 },
4573         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4574                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4575                 pbn_b2_8_1152000 },
4576 
4577         /*
4578          * Oxford Semiconductor Inc. Tornado PCI express device range.
4579          */
4580         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4581                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4582                 pbn_b0_1_4000000 },
4583         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4584                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4585                 pbn_b0_1_4000000 },
4586         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4587                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4588                 pbn_oxsemi_1_4000000 },
4589         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4590                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4591                 pbn_oxsemi_1_4000000 },
4592         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4593                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4594                 pbn_b0_1_4000000 },
4595         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4596                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4597                 pbn_b0_1_4000000 },
4598         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4599                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4600                 pbn_oxsemi_1_4000000 },
4601         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4602                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4603                 pbn_oxsemi_1_4000000 },
4604         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4605                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4606                 pbn_b0_1_4000000 },
4607         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4608                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4609                 pbn_b0_1_4000000 },
4610         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4611                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4612                 pbn_b0_1_4000000 },
4613         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4614                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4615                 pbn_b0_1_4000000 },
4616         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4617                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4618                 pbn_oxsemi_2_4000000 },
4619         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4620                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621                 pbn_oxsemi_2_4000000 },
4622         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4623                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4624                 pbn_oxsemi_4_4000000 },
4625         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4626                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627                 pbn_oxsemi_4_4000000 },
4628         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4629                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630                 pbn_oxsemi_8_4000000 },
4631         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4632                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633                 pbn_oxsemi_8_4000000 },
4634         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4635                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636                 pbn_oxsemi_1_4000000 },
4637         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4638                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639                 pbn_oxsemi_1_4000000 },
4640         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4641                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642                 pbn_oxsemi_1_4000000 },
4643         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4644                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4645                 pbn_oxsemi_1_4000000 },
4646         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4647                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648                 pbn_oxsemi_1_4000000 },
4649         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4650                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651                 pbn_oxsemi_1_4000000 },
4652         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4653                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4654                 pbn_oxsemi_1_4000000 },
4655         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4656                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4657                 pbn_oxsemi_1_4000000 },
4658         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4659                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4660                 pbn_oxsemi_1_4000000 },
4661         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4662                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4663                 pbn_oxsemi_1_4000000 },
4664         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4665                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666                 pbn_oxsemi_1_4000000 },
4667         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4668                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669                 pbn_oxsemi_1_4000000 },
4670         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4671                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672                 pbn_oxsemi_1_4000000 },
4673         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4674                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675                 pbn_oxsemi_1_4000000 },
4676         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4677                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678                 pbn_oxsemi_1_4000000 },
4679         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4680                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4681                 pbn_oxsemi_1_4000000 },
4682         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4683                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684                 pbn_oxsemi_1_4000000 },
4685         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4686                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687                 pbn_oxsemi_1_4000000 },
4688         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4689                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4690                 pbn_oxsemi_1_4000000 },
4691         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4692                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4693                 pbn_oxsemi_1_4000000 },
4694         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4695                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696                 pbn_oxsemi_1_4000000 },
4697         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4698                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4699                 pbn_oxsemi_1_4000000 },
4700         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4701                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4702                 pbn_oxsemi_1_4000000 },
4703         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4704                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4705                 pbn_oxsemi_1_4000000 },
4706         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4707                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708                 pbn_oxsemi_1_4000000 },
4709         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4710                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711                 pbn_oxsemi_1_4000000 },
4712         /*
4713          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4714          */
4715         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4716                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4717                 pbn_oxsemi_1_4000000 },
4718         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4719                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4720                 pbn_oxsemi_2_4000000 },
4721         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4722                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4723                 pbn_oxsemi_4_4000000 },
4724         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4725                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4726                 pbn_oxsemi_8_4000000 },
4727 
4728         /*
4729          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4730          */
4731         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4732                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4733                 pbn_oxsemi_2_4000000 },
4734 
4735         /*
4736          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4737          * from skokodyn@yahoo.com
4738          */
4739         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4740                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4741                 pbn_sbsxrsio },
4742         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4743                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4744                 pbn_sbsxrsio },
4745         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4746                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4747                 pbn_sbsxrsio },
4748         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4749                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4750                 pbn_sbsxrsio },
4751 
4752         /*
4753          * Digitan DS560-558, from jimd@esoft.com
4754          */
4755         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4756                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4757                 pbn_b1_1_115200 },
4758 
4759         /*
4760          * Titan Electronic cards
4761          *  The 400L and 800L have a custom setup quirk.
4762          */
4763         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4764                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4765                 pbn_b0_1_921600 },
4766         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4767                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4768                 pbn_b0_2_921600 },
4769         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4770                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4771                 pbn_b0_4_921600 },
4772         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4773                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4774                 pbn_b0_4_921600 },
4775         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4776                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4777                 pbn_b1_1_921600 },
4778         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4779                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780                 pbn_b1_bt_2_921600 },
4781         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4782                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783                 pbn_b0_bt_4_921600 },
4784         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4785                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4786                 pbn_b0_bt_8_921600 },
4787         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4788                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4789                 pbn_b4_bt_2_921600 },
4790         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4791                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4792                 pbn_b4_bt_4_921600 },
4793         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4794                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4795                 pbn_b4_bt_8_921600 },
4796         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4797                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4798                 pbn_b0_4_921600 },
4799         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4800                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4801                 pbn_b0_4_921600 },
4802         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4803                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4804                 pbn_b0_4_921600 },
4805         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4806                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4807                 pbn_oxsemi_1_4000000 },
4808         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4809                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4810                 pbn_oxsemi_2_4000000 },
4811         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4812                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4813                 pbn_oxsemi_4_4000000 },
4814         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4815                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4816                 pbn_oxsemi_8_4000000 },
4817         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4818                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4819                 pbn_oxsemi_2_4000000 },
4820         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4821                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4822                 pbn_oxsemi_2_4000000 },
4823         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4824                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4825                 pbn_b0_bt_2_921600 },
4826         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4827                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4828                 pbn_b0_4_921600 },
4829         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4830                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4831                 pbn_b0_4_921600 },
4832         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4833                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4834                 pbn_b0_4_921600 },
4835         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4836                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4837                 pbn_b0_4_921600 },
4838 
4839         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4840                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4841                 pbn_b2_1_460800 },
4842         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4843                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4844                 pbn_b2_1_460800 },
4845         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4846                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4847                 pbn_b2_1_460800 },
4848         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4849                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4850                 pbn_b2_bt_2_921600 },
4851         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4852                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4853                 pbn_b2_bt_2_921600 },
4854         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4855                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4856                 pbn_b2_bt_2_921600 },
4857         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4858                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4859                 pbn_b2_bt_4_921600 },
4860         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4861                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4862                 pbn_b2_bt_4_921600 },
4863         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4864                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4865                 pbn_b2_bt_4_921600 },
4866         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4867                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4868                 pbn_b0_1_921600 },
4869         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4870                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4871                 pbn_b0_1_921600 },
4872         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4873                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4874                 pbn_b0_1_921600 },
4875         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4876                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4877                 pbn_b0_bt_2_921600 },
4878         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4879                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4880                 pbn_b0_bt_2_921600 },
4881         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4882                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4883                 pbn_b0_bt_2_921600 },
4884         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4885                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4886                 pbn_b0_bt_4_921600 },
4887         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4888                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4889                 pbn_b0_bt_4_921600 },
4890         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4891                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4892                 pbn_b0_bt_4_921600 },
4893         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4894                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4895                 pbn_b0_bt_8_921600 },
4896         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4897                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4898                 pbn_b0_bt_8_921600 },
4899         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4900                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4901                 pbn_b0_bt_8_921600 },
4902 
4903         /*
4904          * Computone devices submitted by Doug McNash dmcnash@computone.com
4905          */
4906         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4907                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4908                 0, 0, pbn_computone_4 },
4909         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4910                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4911                 0, 0, pbn_computone_8 },
4912         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4913                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4914                 0, 0, pbn_computone_6 },
4915 
4916         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4917                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4918                 pbn_oxsemi },
4919         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4920                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4921                 pbn_b0_bt_1_921600 },
4922 
4923         /*
4924          * SUNIX (TIMEDIA)
4925          */
4926         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4927                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4928                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4929                 pbn_b0_bt_1_921600 },
4930 
4931         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4932                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4933                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4934                 pbn_b0_bt_1_921600 },
4935 
4936         /*
4937          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4938          */
4939         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4940                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4941                 pbn_b0_bt_8_115200 },
4942         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4943                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944                 pbn_b0_bt_8_115200 },
4945 
4946         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4947                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4948                 pbn_b0_bt_2_115200 },
4949         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4950                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4951                 pbn_b0_bt_2_115200 },
4952         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4953                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4954                 pbn_b0_bt_2_115200 },
4955         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4956                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4957                 pbn_b0_bt_2_115200 },
4958         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4959                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4960                 pbn_b0_bt_2_115200 },
4961         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4962                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4963                 pbn_b0_bt_4_460800 },
4964         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4965                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4966                 pbn_b0_bt_4_460800 },
4967         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4968                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4969                 pbn_b0_bt_2_460800 },
4970         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4971                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4972                 pbn_b0_bt_2_460800 },
4973         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4974                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4975                 pbn_b0_bt_2_460800 },
4976         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4977                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4978                 pbn_b0_bt_1_115200 },
4979         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4980                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4981                 pbn_b0_bt_1_460800 },
4982 
4983         /*
4984          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4985          * Cards are identified by their subsystem vendor IDs, which
4986          * (in hex) match the model number.
4987          *
4988          * Note that JC140x are RS422/485 cards which require ox950
4989          * ACR = 0x10, and as such are not currently fully supported.
4990          */
4991         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4992                 0x1204, 0x0004, 0, 0,
4993                 pbn_b0_4_921600 },
4994         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4995                 0x1208, 0x0004, 0, 0,
4996                 pbn_b0_4_921600 },
4997 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4998                 0x1402, 0x0002, 0, 0,
4999                 pbn_b0_2_921600 }, */
5000 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5001                 0x1404, 0x0004, 0, 0,
5002                 pbn_b0_4_921600 }, */
5003         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5004                 0x1208, 0x0004, 0, 0,
5005                 pbn_b0_4_921600 },
5006 
5007         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5008                 0x1204, 0x0004, 0, 0,
5009                 pbn_b0_4_921600 },
5010         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5011                 0x1208, 0x0004, 0, 0,
5012                 pbn_b0_4_921600 },
5013         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5014                 0x1208, 0x0004, 0, 0,
5015                 pbn_b0_4_921600 },
5016         /*
5017          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5018          */
5019         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5020                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5021                 pbn_b1_1_1382400 },
5022 
5023         /*
5024          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5025          */
5026         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5027                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5028                 pbn_b1_1_1382400 },
5029 
5030         /*
5031          * RAStel 2 port modem, gerg@moreton.com.au
5032          */
5033         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5034                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5035                 pbn_b2_bt_2_115200 },
5036 
5037         /*
5038          * EKF addition for i960 Boards form EKF with serial port
5039          */
5040         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5041                 0xE4BF, PCI_ANY_ID, 0, 0,
5042                 pbn_intel_i960 },
5043 
5044         /*
5045          * Xircom Cardbus/Ethernet combos
5046          */
5047         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5048                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5049                 pbn_b0_1_115200 },
5050         /*
5051          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5052          */
5053         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5054                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5055                 pbn_b0_1_115200 },
5056 
5057         /*
5058          * Untested PCI modems, sent in from various folks...
5059          */
5060 
5061         /*
5062          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5063          */
5064         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
5065                 0x1048, 0x1500, 0, 0,
5066                 pbn_b1_1_115200 },
5067 
5068         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5069                 0xFF00, 0, 0, 0,
5070                 pbn_sgi_ioc3 },
5071 
5072         /*
5073          * HP Diva card
5074          */
5075         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5076                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5077                 pbn_b1_1_115200 },
5078         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5079                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5080                 pbn_b0_5_115200 },
5081         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5082                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5083                 pbn_b2_1_115200 },
5084 
5085         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5086                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5087                 pbn_b3_2_115200 },
5088         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5089                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5090                 pbn_b3_4_115200 },
5091         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5092                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5093                 pbn_b3_8_115200 },
5094 
5095         /*
5096          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5097          */
5098         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5099                 PCI_ANY_ID, PCI_ANY_ID,
5100                 0,
5101                 0, pbn_exar_XR17C152 },
5102         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5103                 PCI_ANY_ID, PCI_ANY_ID,
5104                 0,
5105                 0, pbn_exar_XR17C154 },
5106         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5107                 PCI_ANY_ID, PCI_ANY_ID,
5108                 0,
5109                 0, pbn_exar_XR17C158 },
5110         /*
5111          * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5112          */
5113         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5114                 PCI_ANY_ID, PCI_ANY_ID,
5115                 0,
5116                 0, pbn_exar_XR17V352 },
5117         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5118                 PCI_ANY_ID, PCI_ANY_ID,
5119                 0,
5120                 0, pbn_exar_XR17V354 },
5121         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5122                 PCI_ANY_ID, PCI_ANY_ID,
5123                 0,
5124                 0, pbn_exar_XR17V358 },
5125         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5126                 PCI_ANY_ID, PCI_ANY_ID,
5127                 0,
5128                 0, pbn_exar_XR17V4358 },
5129         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5130                 PCI_ANY_ID, PCI_ANY_ID,
5131                 0,
5132                 0, pbn_exar_XR17V8358 },
5133         /*
5134          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5135          */
5136         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5137                 PCI_ANY_ID, PCI_ANY_ID,
5138                 0,
5139                 0, pbn_pericom_PI7C9X7951 },
5140         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5141                 PCI_ANY_ID, PCI_ANY_ID,
5142                 0,
5143                 0, pbn_pericom_PI7C9X7952 },
5144         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5145                 PCI_ANY_ID, PCI_ANY_ID,
5146                 0,
5147                 0, pbn_pericom_PI7C9X7954 },
5148         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5149                 PCI_ANY_ID, PCI_ANY_ID,
5150                 0,
5151                 0, pbn_pericom_PI7C9X7958 },
5152         /*
5153          * ACCES I/O Products quad
5154          */
5155         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
5156                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5157                 pbn_pericom_PI7C9X7954 },
5158         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
5159                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5160                 pbn_pericom_PI7C9X7954 },
5161         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
5162                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5163                 pbn_pericom_PI7C9X7954 },
5164         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
5165                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5166                 pbn_pericom_PI7C9X7954 },
5167         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
5168                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5169                 pbn_pericom_PI7C9X7954 },
5170         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
5171                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5172                 pbn_pericom_PI7C9X7954 },
5173         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
5174                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5175                 pbn_pericom_PI7C9X7954 },
5176         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
5177                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5178                 pbn_pericom_PI7C9X7954 },
5179         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
5180                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5181                 pbn_pericom_PI7C9X7954 },
5182         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
5183                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5184                 pbn_pericom_PI7C9X7954 },
5185         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
5186                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5187                 pbn_pericom_PI7C9X7954 },
5188         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
5189                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5190                 pbn_pericom_PI7C9X7954 },
5191         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
5192                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5193                 pbn_pericom_PI7C9X7954 },
5194         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
5195                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5196                 pbn_pericom_PI7C9X7954 },
5197         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
5198                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5199                 pbn_pericom_PI7C9X7954 },
5200         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
5201                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5202                 pbn_pericom_PI7C9X7954 },
5203         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
5204                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5205                 pbn_pericom_PI7C9X7954 },
5206         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
5207                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5208                 pbn_pericom_PI7C9X7954 },
5209         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
5210                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5211                 pbn_pericom_PI7C9X7954 },
5212         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
5213                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5214                 pbn_pericom_PI7C9X7954 },
5215         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
5216                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5217                 pbn_pericom_PI7C9X7954 },
5218         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
5219                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5220                 pbn_pericom_PI7C9X7954 },
5221         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
5222                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5223                 pbn_pericom_PI7C9X7954 },
5224         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
5225                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5226                 pbn_pericom_PI7C9X7954 },
5227         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
5228                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5229                 pbn_pericom_PI7C9X7958 },
5230         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
5231                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5232                 pbn_pericom_PI7C9X7958 },
5233         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
5234                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5235                 pbn_pericom_PI7C9X7958 },
5236         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
5237                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5238                 pbn_pericom_PI7C9X7958 },
5239         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
5240                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5241                 pbn_pericom_PI7C9X7958 },
5242         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
5243                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5244                 pbn_pericom_PI7C9X7958 },
5245         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
5246                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5247                 pbn_pericom_PI7C9X7958 },
5248         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
5249                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5250                 pbn_pericom_PI7C9X7958 },
5251         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
5252                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5253                 pbn_pericom_PI7C9X7958 },
5254         /*
5255          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5256          */
5257         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5258                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5259                 pbn_b0_1_115200 },
5260         /*
5261          * ITE
5262          */
5263         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5264                 PCI_ANY_ID, PCI_ANY_ID,
5265                 0, 0,
5266                 pbn_b1_bt_1_115200 },
5267 
5268         /*
5269          * IntaShield IS-200
5270          */
5271         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5272                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
5273                 pbn_b2_2_115200 },
5274         /*
5275          * IntaShield IS-400
5276          */
5277         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5278                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
5279                 pbn_b2_4_115200 },
5280         /*
5281          * Perle PCI-RAS cards
5282          */
5283         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5284                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5285                 0, 0, pbn_b2_4_921600 },
5286         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5287                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5288                 0, 0, pbn_b2_8_921600 },
5289 
5290         /*
5291          * Mainpine series cards: Fairly standard layout but fools
5292          * parts of the autodetect in some cases and uses otherwise
5293          * unmatched communications subclasses in the PCI Express case
5294          */
5295 
5296         {       /* RockForceDUO */
5297                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5298                 PCI_VENDOR_ID_MAINPINE, 0x0200,
5299                 0, 0, pbn_b0_2_115200 },
5300         {       /* RockForceQUATRO */
5301                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5302                 PCI_VENDOR_ID_MAINPINE, 0x0300,
5303                 0, 0, pbn_b0_4_115200 },
5304         {       /* RockForceDUO+ */
5305                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5306                 PCI_VENDOR_ID_MAINPINE, 0x0400,
5307                 0, 0, pbn_b0_2_115200 },
5308         {       /* RockForceQUATRO+ */
5309                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5310                 PCI_VENDOR_ID_MAINPINE, 0x0500,
5311                 0, 0, pbn_b0_4_115200 },
5312         {       /* RockForce+ */
5313                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5314                 PCI_VENDOR_ID_MAINPINE, 0x0600,
5315                 0, 0, pbn_b0_2_115200 },
5316         {       /* RockForce+ */
5317                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5318                 PCI_VENDOR_ID_MAINPINE, 0x0700,
5319                 0, 0, pbn_b0_4_115200 },
5320         {       /* RockForceOCTO+ */
5321                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5322                 PCI_VENDOR_ID_MAINPINE, 0x0800,
5323                 0, 0, pbn_b0_8_115200 },
5324         {       /* RockForceDUO+ */
5325                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5326                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5327                 0, 0, pbn_b0_2_115200 },
5328         {       /* RockForceQUARTRO+ */
5329                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5330                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5331                 0, 0, pbn_b0_4_115200 },
5332         {       /* RockForceOCTO+ */
5333                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5334                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5335                 0, 0, pbn_b0_8_115200 },
5336         {       /* RockForceD1 */
5337                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5338                 PCI_VENDOR_ID_MAINPINE, 0x2000,
5339                 0, 0, pbn_b0_1_115200 },
5340         {       /* RockForceF1 */
5341                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5342                 PCI_VENDOR_ID_MAINPINE, 0x2100,
5343                 0, 0, pbn_b0_1_115200 },
5344         {       /* RockForceD2 */
5345                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5346                 PCI_VENDOR_ID_MAINPINE, 0x2200,
5347                 0, 0, pbn_b0_2_115200 },
5348         {       /* RockForceF2 */
5349                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5350                 PCI_VENDOR_ID_MAINPINE, 0x2300,
5351                 0, 0, pbn_b0_2_115200 },
5352         {       /* RockForceD4 */
5353                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5354                 PCI_VENDOR_ID_MAINPINE, 0x2400,
5355                 0, 0, pbn_b0_4_115200 },
5356         {       /* RockForceF4 */
5357                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5358                 PCI_VENDOR_ID_MAINPINE, 0x2500,
5359                 0, 0, pbn_b0_4_115200 },
5360         {       /* RockForceD8 */
5361                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5362                 PCI_VENDOR_ID_MAINPINE, 0x2600,
5363                 0, 0, pbn_b0_8_115200 },
5364         {       /* RockForceF8 */
5365                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5366                 PCI_VENDOR_ID_MAINPINE, 0x2700,
5367                 0, 0, pbn_b0_8_115200 },
5368         {       /* IQ Express D1 */
5369                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5370                 PCI_VENDOR_ID_MAINPINE, 0x3000,
5371                 0, 0, pbn_b0_1_115200 },
5372         {       /* IQ Express F1 */
5373                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5374                 PCI_VENDOR_ID_MAINPINE, 0x3100,
5375                 0, 0, pbn_b0_1_115200 },
5376         {       /* IQ Express D2 */
5377                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5378                 PCI_VENDOR_ID_MAINPINE, 0x3200,
5379                 0, 0, pbn_b0_2_115200 },
5380         {       /* IQ Express F2 */
5381                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5382                 PCI_VENDOR_ID_MAINPINE, 0x3300,
5383                 0, 0, pbn_b0_2_115200 },
5384         {       /* IQ Express D4 */
5385                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5386                 PCI_VENDOR_ID_MAINPINE, 0x3400,
5387                 0, 0, pbn_b0_4_115200 },
5388         {       /* IQ Express F4 */
5389                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5390                 PCI_VENDOR_ID_MAINPINE, 0x3500,
5391                 0, 0, pbn_b0_4_115200 },
5392         {       /* IQ Express D8 */
5393                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5394                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5395                 0, 0, pbn_b0_8_115200 },
5396         {       /* IQ Express F8 */
5397                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5398                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5399                 0, 0, pbn_b0_8_115200 },
5400 
5401 
5402         /*
5403          * PA Semi PA6T-1682M on-chip UART
5404          */
5405         {       PCI_VENDOR_ID_PASEMI, 0xa004,
5406                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5407                 pbn_pasemi_1682M },
5408 
5409         /*
5410          * National Instruments
5411          */
5412         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5413                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5414                 pbn_b1_16_115200 },
5415         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5416                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5417                 pbn_b1_8_115200 },
5418         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5419                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5420                 pbn_b1_bt_4_115200 },
5421         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5422                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5423                 pbn_b1_bt_2_115200 },
5424         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5425                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5426                 pbn_b1_bt_4_115200 },
5427         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5428                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5429                 pbn_b1_bt_2_115200 },
5430         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5431                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5432                 pbn_b1_16_115200 },
5433         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5434                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5435                 pbn_b1_8_115200 },
5436         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5437                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5438                 pbn_b1_bt_4_115200 },
5439         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5440                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5441                 pbn_b1_bt_2_115200 },
5442         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5443                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5444                 pbn_b1_bt_4_115200 },
5445         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5446                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5447                 pbn_b1_bt_2_115200 },
5448         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5449                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5450                 pbn_ni8430_2 },
5451         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5452                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5453                 pbn_ni8430_2 },
5454         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5455                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5456                 pbn_ni8430_4 },
5457         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5458                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5459                 pbn_ni8430_4 },
5460         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5461                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5462                 pbn_ni8430_8 },
5463         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5464                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5465                 pbn_ni8430_8 },
5466         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5467                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5468                 pbn_ni8430_16 },
5469         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5470                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5471                 pbn_ni8430_16 },
5472         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5473                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5474                 pbn_ni8430_2 },
5475         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5476                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5477                 pbn_ni8430_2 },
5478         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5479                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5480                 pbn_ni8430_4 },
5481         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5482                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5483                 pbn_ni8430_4 },
5484 
5485         /*
5486         * ADDI-DATA GmbH communication cards <info@addi-data.com>
5487         */
5488         {       PCI_VENDOR_ID_ADDIDATA,
5489                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5490                 PCI_ANY_ID,
5491                 PCI_ANY_ID,
5492                 0,
5493                 0,
5494                 pbn_b0_4_115200 },
5495 
5496         {       PCI_VENDOR_ID_ADDIDATA,
5497                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5498                 PCI_ANY_ID,
5499                 PCI_ANY_ID,
5500                 0,
5501                 0,
5502                 pbn_b0_2_115200 },
5503 
5504         {       PCI_VENDOR_ID_ADDIDATA,
5505                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5506                 PCI_ANY_ID,
5507                 PCI_ANY_ID,
5508                 0,
5509                 0,
5510                 pbn_b0_1_115200 },
5511 
5512         {       PCI_VENDOR_ID_AMCC,
5513                 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5514                 PCI_ANY_ID,
5515                 PCI_ANY_ID,
5516                 0,
5517                 0,
5518                 pbn_b1_8_115200 },
5519 
5520         {       PCI_VENDOR_ID_ADDIDATA,
5521                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5522                 PCI_ANY_ID,
5523                 PCI_ANY_ID,
5524                 0,
5525                 0,
5526                 pbn_b0_4_115200 },
5527 
5528         {       PCI_VENDOR_ID_ADDIDATA,
5529                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5530                 PCI_ANY_ID,
5531                 PCI_ANY_ID,
5532                 0,
5533                 0,
5534                 pbn_b0_2_115200 },
5535 
5536         {       PCI_VENDOR_ID_ADDIDATA,
5537                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5538                 PCI_ANY_ID,
5539                 PCI_ANY_ID,
5540                 0,
5541                 0,
5542                 pbn_b0_1_115200 },
5543 
5544         {       PCI_VENDOR_ID_ADDIDATA,
5545                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5546                 PCI_ANY_ID,
5547                 PCI_ANY_ID,
5548                 0,
5549                 0,
5550                 pbn_b0_4_115200 },
5551 
5552         {       PCI_VENDOR_ID_ADDIDATA,
5553                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5554                 PCI_ANY_ID,
5555                 PCI_ANY_ID,
5556                 0,
5557                 0,
5558                 pbn_b0_2_115200 },
5559 
5560         {       PCI_VENDOR_ID_ADDIDATA,
5561                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5562                 PCI_ANY_ID,
5563                 PCI_ANY_ID,
5564                 0,
5565                 0,
5566                 pbn_b0_1_115200 },
5567 
5568         {       PCI_VENDOR_ID_ADDIDATA,
5569                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5570                 PCI_ANY_ID,
5571                 PCI_ANY_ID,
5572                 0,
5573                 0,
5574                 pbn_b0_8_115200 },
5575 
5576         {       PCI_VENDOR_ID_ADDIDATA,
5577                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5578                 PCI_ANY_ID,
5579                 PCI_ANY_ID,
5580                 0,
5581                 0,
5582                 pbn_ADDIDATA_PCIe_4_3906250 },
5583 
5584         {       PCI_VENDOR_ID_ADDIDATA,
5585                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5586                 PCI_ANY_ID,
5587                 PCI_ANY_ID,
5588                 0,
5589                 0,
5590                 pbn_ADDIDATA_PCIe_2_3906250 },
5591 
5592         {       PCI_VENDOR_ID_ADDIDATA,
5593                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5594                 PCI_ANY_ID,
5595                 PCI_ANY_ID,
5596                 0,
5597                 0,
5598                 pbn_ADDIDATA_PCIe_1_3906250 },
5599 
5600         {       PCI_VENDOR_ID_ADDIDATA,
5601                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5602                 PCI_ANY_ID,
5603                 PCI_ANY_ID,
5604                 0,
5605                 0,
5606                 pbn_ADDIDATA_PCIe_8_3906250 },
5607 
5608         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5609                 PCI_VENDOR_ID_IBM, 0x0299,
5610                 0, 0, pbn_b0_bt_2_115200 },
5611 
5612         /*
5613          * other NetMos 9835 devices are most likely handled by the
5614          * parport_serial driver, check drivers/parport/parport_serial.c
5615          * before adding them here.
5616          */
5617 
5618         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5619                 0xA000, 0x1000,
5620                 0, 0, pbn_b0_1_115200 },
5621 
5622         /* the 9901 is a rebranded 9912 */
5623         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5624                 0xA000, 0x1000,
5625                 0, 0, pbn_b0_1_115200 },
5626 
5627         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5628                 0xA000, 0x1000,
5629                 0, 0, pbn_b0_1_115200 },
5630 
5631         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5632                 0xA000, 0x1000,
5633                 0, 0, pbn_b0_1_115200 },
5634 
5635         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5636                 0xA000, 0x1000,
5637                 0, 0, pbn_b0_1_115200 },
5638 
5639         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5640                 0xA000, 0x3002,
5641                 0, 0, pbn_NETMOS9900_2s_115200 },
5642 
5643         /*
5644          * Best Connectivity and Rosewill PCI Multi I/O cards
5645          */
5646 
5647         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5648                 0xA000, 0x1000,
5649                 0, 0, pbn_b0_1_115200 },
5650 
5651         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5652                 0xA000, 0x3002,
5653                 0, 0, pbn_b0_bt_2_115200 },
5654 
5655         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5656                 0xA000, 0x3004,
5657                 0, 0, pbn_b0_bt_4_115200 },
5658         /* Intel CE4100 */
5659         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5660                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5661                 pbn_ce4100_1_115200 },
5662         /* Intel BayTrail */
5663         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5664                 PCI_ANY_ID,  PCI_ANY_ID,
5665                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5666                 pbn_byt },
5667         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5668                 PCI_ANY_ID,  PCI_ANY_ID,
5669                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5670                 pbn_byt },
5671         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5672                 PCI_ANY_ID,  PCI_ANY_ID,
5673                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5674                 pbn_byt },
5675         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5676                 PCI_ANY_ID,  PCI_ANY_ID,
5677                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5678                 pbn_byt },
5679 
5680         /* Intel Broadwell */
5681         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1,
5682                 PCI_ANY_ID,  PCI_ANY_ID,
5683                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5684                 pbn_byt },
5685         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2,
5686                 PCI_ANY_ID,  PCI_ANY_ID,
5687                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5688                 pbn_byt },
5689 
5690         /*
5691          * Intel Quark x1000
5692          */
5693         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5694                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5695                 pbn_qrk },
5696         /*
5697          * Cronyx Omega PCI
5698          */
5699         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5700                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5701                 pbn_omegapci },
5702 
5703         /*
5704          * Broadcom TruManage
5705          */
5706         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5707                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5708                 pbn_brcm_trumanage },
5709 
5710         /*
5711          * AgeStar as-prs2-009
5712          */
5713         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5714                 PCI_ANY_ID, PCI_ANY_ID,
5715                 0, 0, pbn_b0_bt_2_115200 },
5716 
5717         /*
5718          * WCH CH353 series devices: The 2S1P is handled by parport_serial
5719          * so not listed here.
5720          */
5721         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5722                 PCI_ANY_ID, PCI_ANY_ID,
5723                 0, 0, pbn_b0_bt_4_115200 },
5724 
5725         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5726                 PCI_ANY_ID, PCI_ANY_ID,
5727                 0, 0, pbn_b0_bt_2_115200 },
5728 
5729         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5730                 PCI_ANY_ID, PCI_ANY_ID,
5731                 0, 0, pbn_b0_bt_4_115200 },
5732 
5733         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5734                 PCI_ANY_ID, PCI_ANY_ID,
5735                 0, 0, pbn_wch382_2 },
5736 
5737         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5738                 PCI_ANY_ID, PCI_ANY_ID,
5739                 0, 0, pbn_wch384_4 },
5740 
5741         /*
5742          * Commtech, Inc. Fastcom adapters
5743          */
5744         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5745                 PCI_ANY_ID, PCI_ANY_ID,
5746                 0,
5747                 0, pbn_b0_2_1152000_200 },
5748         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5749                 PCI_ANY_ID, PCI_ANY_ID,
5750                 0,
5751                 0, pbn_b0_4_1152000_200 },
5752         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5753                 PCI_ANY_ID, PCI_ANY_ID,
5754                 0,
5755                 0, pbn_b0_4_1152000_200 },
5756         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5757                 PCI_ANY_ID, PCI_ANY_ID,
5758                 0,
5759                 0, pbn_b0_8_1152000_200 },
5760         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5761                 PCI_ANY_ID, PCI_ANY_ID,
5762                 0,
5763                 0, pbn_exar_XR17V352 },
5764         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5765                 PCI_ANY_ID, PCI_ANY_ID,
5766                 0,
5767                 0, pbn_exar_XR17V354 },
5768         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5769                 PCI_ANY_ID, PCI_ANY_ID,
5770                 0,
5771                 0, pbn_exar_XR17V358 },
5772 
5773         /* Fintek PCI serial cards */
5774         { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5775         { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5776         { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5777 
5778         /*
5779          * These entries match devices with class COMMUNICATION_SERIAL,
5780          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5781          */
5782         {       PCI_ANY_ID, PCI_ANY_ID,
5783                 PCI_ANY_ID, PCI_ANY_ID,
5784                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5785                 0xffff00, pbn_default },
5786         {       PCI_ANY_ID, PCI_ANY_ID,
5787                 PCI_ANY_ID, PCI_ANY_ID,
5788                 PCI_CLASS_COMMUNICATION_MODEM << 8,
5789                 0xffff00, pbn_default },
5790         {       PCI_ANY_ID, PCI_ANY_ID,
5791                 PCI_ANY_ID, PCI_ANY_ID,
5792                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5793                 0xffff00, pbn_default },
5794         { 0, }
5795 };
5796 
5797 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5798                                                 pci_channel_state_t state)
5799 {
5800         struct serial_private *priv = pci_get_drvdata(dev);
5801 
5802         if (state == pci_channel_io_perm_failure)
5803                 return PCI_ERS_RESULT_DISCONNECT;
5804 
5805         if (priv)
5806                 pciserial_suspend_ports(priv);
5807 
5808         pci_disable_device(dev);
5809 
5810         return PCI_ERS_RESULT_NEED_RESET;
5811 }
5812 
5813 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5814 {
5815         int rc;
5816 
5817         rc = pci_enable_device(dev);
5818 
5819         if (rc)
5820                 return PCI_ERS_RESULT_DISCONNECT;
5821 
5822         pci_restore_state(dev);
5823         pci_save_state(dev);
5824 
5825         return PCI_ERS_RESULT_RECOVERED;
5826 }
5827 
5828 static void serial8250_io_resume(struct pci_dev *dev)
5829 {
5830         struct serial_private *priv = pci_get_drvdata(dev);
5831 
5832         if (priv)
5833                 pciserial_resume_ports(priv);
5834 }
5835 
5836 static const struct pci_error_handlers serial8250_err_handler = {
5837         .error_detected = serial8250_io_error_detected,
5838         .slot_reset = serial8250_io_slot_reset,
5839         .resume = serial8250_io_resume,
5840 };
5841 
5842 static struct pci_driver serial_pci_driver = {
5843         .name           = "serial",
5844         .probe          = pciserial_init_one,
5845         .remove         = pciserial_remove_one,
5846         .driver         = {
5847                 .pm     = &pciserial_pm_ops,
5848         },
5849         .id_table       = serial_pci_tbl,
5850         .err_handler    = &serial8250_err_handler,
5851 };
5852 
5853 module_pci_driver(serial_pci_driver);
5854 
5855 MODULE_LICENSE("GPL");
5856 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5857 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
5858 

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