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Linux/drivers/tty/serial/8250/8250_pci.c

  1 /*
  2  *  Probe module for 8250/16550-type PCI serial ports.
  3  *
  4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  5  *
  6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License.
 11  */
 12 #undef DEBUG
 13 #include <linux/module.h>
 14 #include <linux/pci.h>
 15 #include <linux/string.h>
 16 #include <linux/kernel.h>
 17 #include <linux/slab.h>
 18 #include <linux/delay.h>
 19 #include <linux/tty.h>
 20 #include <linux/serial_reg.h>
 21 #include <linux/serial_core.h>
 22 #include <linux/8250_pci.h>
 23 #include <linux/bitops.h>
 24 #include <linux/rational.h>
 25 
 26 #include <asm/byteorder.h>
 27 #include <asm/io.h>
 28 
 29 #include <linux/dmaengine.h>
 30 #include <linux/platform_data/dma-dw.h>
 31 
 32 #include "8250.h"
 33 
 34 /*
 35  * init function returns:
 36  *  > 0 - number of ports
 37  *  = 0 - use board->num_ports
 38  *  < 0 - error
 39  */
 40 struct pci_serial_quirk {
 41         u32     vendor;
 42         u32     device;
 43         u32     subvendor;
 44         u32     subdevice;
 45         int     (*probe)(struct pci_dev *dev);
 46         int     (*init)(struct pci_dev *dev);
 47         int     (*setup)(struct serial_private *,
 48                          const struct pciserial_board *,
 49                          struct uart_8250_port *, int);
 50         void    (*exit)(struct pci_dev *dev);
 51 };
 52 
 53 #define PCI_NUM_BAR_RESOURCES   6
 54 
 55 struct serial_private {
 56         struct pci_dev          *dev;
 57         unsigned int            nr;
 58         struct pci_serial_quirk *quirk;
 59         int                     line[0];
 60 };
 61 
 62 static int pci_default_setup(struct serial_private*,
 63           const struct pciserial_board*, struct uart_8250_port *, int);
 64 
 65 static void moan_device(const char *str, struct pci_dev *dev)
 66 {
 67         dev_err(&dev->dev,
 68                "%s: %s\n"
 69                "Please send the output of lspci -vv, this\n"
 70                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
 71                "manufacturer and name of serial board or\n"
 72                "modem board to <linux-serial@vger.kernel.org>.\n",
 73                pci_name(dev), str, dev->vendor, dev->device,
 74                dev->subsystem_vendor, dev->subsystem_device);
 75 }
 76 
 77 static int
 78 setup_port(struct serial_private *priv, struct uart_8250_port *port,
 79            int bar, int offset, int regshift)
 80 {
 81         struct pci_dev *dev = priv->dev;
 82 
 83         if (bar >= PCI_NUM_BAR_RESOURCES)
 84                 return -EINVAL;
 85 
 86         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
 87                 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
 88                         return -ENOMEM;
 89 
 90                 port->port.iotype = UPIO_MEM;
 91                 port->port.iobase = 0;
 92                 port->port.mapbase = pci_resource_start(dev, bar) + offset;
 93                 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
 94                 port->port.regshift = regshift;
 95         } else {
 96                 port->port.iotype = UPIO_PORT;
 97                 port->port.iobase = pci_resource_start(dev, bar) + offset;
 98                 port->port.mapbase = 0;
 99                 port->port.membase = NULL;
100                 port->port.regshift = 0;
101         }
102         return 0;
103 }
104 
105 /*
106  * ADDI-DATA GmbH communication cards <info@addi-data.com>
107  */
108 static int addidata_apci7800_setup(struct serial_private *priv,
109                                 const struct pciserial_board *board,
110                                 struct uart_8250_port *port, int idx)
111 {
112         unsigned int bar = 0, offset = board->first_offset;
113         bar = FL_GET_BASE(board->flags);
114 
115         if (idx < 2) {
116                 offset += idx * board->uart_offset;
117         } else if ((idx >= 2) && (idx < 4)) {
118                 bar += 1;
119                 offset += ((idx - 2) * board->uart_offset);
120         } else if ((idx >= 4) && (idx < 6)) {
121                 bar += 2;
122                 offset += ((idx - 4) * board->uart_offset);
123         } else if (idx >= 6) {
124                 bar += 3;
125                 offset += ((idx - 6) * board->uart_offset);
126         }
127 
128         return setup_port(priv, port, bar, offset, board->reg_shift);
129 }
130 
131 /*
132  * AFAVLAB uses a different mixture of BARs and offsets
133  * Not that ugly ;) -- HW
134  */
135 static int
136 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
137               struct uart_8250_port *port, int idx)
138 {
139         unsigned int bar, offset = board->first_offset;
140 
141         bar = FL_GET_BASE(board->flags);
142         if (idx < 4)
143                 bar += idx;
144         else {
145                 bar = 4;
146                 offset += (idx - 4) * board->uart_offset;
147         }
148 
149         return setup_port(priv, port, bar, offset, board->reg_shift);
150 }
151 
152 /*
153  * HP's Remote Management Console.  The Diva chip came in several
154  * different versions.  N-class, L2000 and A500 have two Diva chips, each
155  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
156  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
157  * one Diva chip, but it has been expanded to 5 UARTs.
158  */
159 static int pci_hp_diva_init(struct pci_dev *dev)
160 {
161         int rc = 0;
162 
163         switch (dev->subsystem_device) {
164         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
165         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
166         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
167         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
168                 rc = 3;
169                 break;
170         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
171                 rc = 2;
172                 break;
173         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
174                 rc = 4;
175                 break;
176         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
177         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
178                 rc = 1;
179                 break;
180         }
181 
182         return rc;
183 }
184 
185 /*
186  * HP's Diva chip puts the 4th/5th serial port further out, and
187  * some serial ports are supposed to be hidden on certain models.
188  */
189 static int
190 pci_hp_diva_setup(struct serial_private *priv,
191                 const struct pciserial_board *board,
192                 struct uart_8250_port *port, int idx)
193 {
194         unsigned int offset = board->first_offset;
195         unsigned int bar = FL_GET_BASE(board->flags);
196 
197         switch (priv->dev->subsystem_device) {
198         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
199                 if (idx == 3)
200                         idx++;
201                 break;
202         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
203                 if (idx > 0)
204                         idx++;
205                 if (idx > 2)
206                         idx++;
207                 break;
208         }
209         if (idx > 2)
210                 offset = 0x18;
211 
212         offset += idx * board->uart_offset;
213 
214         return setup_port(priv, port, bar, offset, board->reg_shift);
215 }
216 
217 /*
218  * Added for EKF Intel i960 serial boards
219  */
220 static int pci_inteli960ni_init(struct pci_dev *dev)
221 {
222         u32 oldval;
223 
224         if (!(dev->subsystem_device & 0x1000))
225                 return -ENODEV;
226 
227         /* is firmware started? */
228         pci_read_config_dword(dev, 0x44, &oldval);
229         if (oldval == 0x00001000L) { /* RESET value */
230                 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
231                 return -ENODEV;
232         }
233         return 0;
234 }
235 
236 /*
237  * Some PCI serial cards using the PLX 9050 PCI interface chip require
238  * that the card interrupt be explicitly enabled or disabled.  This
239  * seems to be mainly needed on card using the PLX which also use I/O
240  * mapped memory.
241  */
242 static int pci_plx9050_init(struct pci_dev *dev)
243 {
244         u8 irq_config;
245         void __iomem *p;
246 
247         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
248                 moan_device("no memory in bar 0", dev);
249                 return 0;
250         }
251 
252         irq_config = 0x41;
253         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
254             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
255                 irq_config = 0x43;
256 
257         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
258             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
259                 /*
260                  * As the megawolf cards have the int pins active
261                  * high, and have 2 UART chips, both ints must be
262                  * enabled on the 9050. Also, the UARTS are set in
263                  * 16450 mode by default, so we have to enable the
264                  * 16C950 'enhanced' mode so that we can use the
265                  * deep FIFOs
266                  */
267                 irq_config = 0x5b;
268         /*
269          * enable/disable interrupts
270          */
271         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
272         if (p == NULL)
273                 return -ENOMEM;
274         writel(irq_config, p + 0x4c);
275 
276         /*
277          * Read the register back to ensure that it took effect.
278          */
279         readl(p + 0x4c);
280         iounmap(p);
281 
282         return 0;
283 }
284 
285 static void pci_plx9050_exit(struct pci_dev *dev)
286 {
287         u8 __iomem *p;
288 
289         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
290                 return;
291 
292         /*
293          * disable interrupts
294          */
295         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
296         if (p != NULL) {
297                 writel(0, p + 0x4c);
298 
299                 /*
300                  * Read the register back to ensure that it took effect.
301                  */
302                 readl(p + 0x4c);
303                 iounmap(p);
304         }
305 }
306 
307 #define NI8420_INT_ENABLE_REG   0x38
308 #define NI8420_INT_ENABLE_BIT   0x2000
309 
310 static void pci_ni8420_exit(struct pci_dev *dev)
311 {
312         void __iomem *p;
313         unsigned int bar = 0;
314 
315         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
316                 moan_device("no memory in bar", dev);
317                 return;
318         }
319 
320         p = pci_ioremap_bar(dev, bar);
321         if (p == NULL)
322                 return;
323 
324         /* Disable the CPU Interrupt */
325         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
326                p + NI8420_INT_ENABLE_REG);
327         iounmap(p);
328 }
329 
330 
331 /* MITE registers */
332 #define MITE_IOWBSR1    0xc4
333 #define MITE_IOWCR1     0xf4
334 #define MITE_LCIMR1     0x08
335 #define MITE_LCIMR2     0x10
336 
337 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
338 
339 static void pci_ni8430_exit(struct pci_dev *dev)
340 {
341         void __iomem *p;
342         unsigned int bar = 0;
343 
344         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
345                 moan_device("no memory in bar", dev);
346                 return;
347         }
348 
349         p = pci_ioremap_bar(dev, bar);
350         if (p == NULL)
351                 return;
352 
353         /* Disable the CPU Interrupt */
354         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
355         iounmap(p);
356 }
357 
358 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
359 static int
360 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
361                 struct uart_8250_port *port, int idx)
362 {
363         unsigned int bar, offset = board->first_offset;
364 
365         bar = 0;
366 
367         if (idx < 4) {
368                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
369                 offset += idx * board->uart_offset;
370         } else if (idx < 8) {
371                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
372                 offset += idx * board->uart_offset + 0xC00;
373         } else /* we have only 8 ports on PMC-OCTALPRO */
374                 return 1;
375 
376         return setup_port(priv, port, bar, offset, board->reg_shift);
377 }
378 
379 /*
380 * This does initialization for PMC OCTALPRO cards:
381 * maps the device memory, resets the UARTs (needed, bc
382 * if the module is removed and inserted again, the card
383 * is in the sleep mode) and enables global interrupt.
384 */
385 
386 /* global control register offset for SBS PMC-OctalPro */
387 #define OCT_REG_CR_OFF          0x500
388 
389 static int sbs_init(struct pci_dev *dev)
390 {
391         u8 __iomem *p;
392 
393         p = pci_ioremap_bar(dev, 0);
394 
395         if (p == NULL)
396                 return -ENOMEM;
397         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
398         writeb(0x10, p + OCT_REG_CR_OFF);
399         udelay(50);
400         writeb(0x0, p + OCT_REG_CR_OFF);
401 
402         /* Set bit-2 (INTENABLE) of Control Register */
403         writeb(0x4, p + OCT_REG_CR_OFF);
404         iounmap(p);
405 
406         return 0;
407 }
408 
409 /*
410  * Disables the global interrupt of PMC-OctalPro
411  */
412 
413 static void sbs_exit(struct pci_dev *dev)
414 {
415         u8 __iomem *p;
416 
417         p = pci_ioremap_bar(dev, 0);
418         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
419         if (p != NULL)
420                 writeb(0, p + OCT_REG_CR_OFF);
421         iounmap(p);
422 }
423 
424 /*
425  * SIIG serial cards have an PCI interface chip which also controls
426  * the UART clocking frequency. Each UART can be clocked independently
427  * (except cards equipped with 4 UARTs) and initial clocking settings
428  * are stored in the EEPROM chip. It can cause problems because this
429  * version of serial driver doesn't support differently clocked UART's
430  * on single PCI card. To prevent this, initialization functions set
431  * high frequency clocking for all UART's on given card. It is safe (I
432  * hope) because it doesn't touch EEPROM settings to prevent conflicts
433  * with other OSes (like M$ DOS).
434  *
435  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
436  *
437  * There is two family of SIIG serial cards with different PCI
438  * interface chip and different configuration methods:
439  *     - 10x cards have control registers in IO and/or memory space;
440  *     - 20x cards have control registers in standard PCI configuration space.
441  *
442  * Note: all 10x cards have PCI device ids 0x10..
443  *       all 20x cards have PCI device ids 0x20..
444  *
445  * There are also Quartet Serial cards which use Oxford Semiconductor
446  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
447  *
448  * Note: some SIIG cards are probed by the parport_serial object.
449  */
450 
451 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
452 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
453 
454 static int pci_siig10x_init(struct pci_dev *dev)
455 {
456         u16 data;
457         void __iomem *p;
458 
459         switch (dev->device & 0xfff8) {
460         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
461                 data = 0xffdf;
462                 break;
463         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
464                 data = 0xf7ff;
465                 break;
466         default:                        /* 1S1P, 4S */
467                 data = 0xfffb;
468                 break;
469         }
470 
471         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
472         if (p == NULL)
473                 return -ENOMEM;
474 
475         writew(readw(p + 0x28) & data, p + 0x28);
476         readw(p + 0x28);
477         iounmap(p);
478         return 0;
479 }
480 
481 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
482 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
483 
484 static int pci_siig20x_init(struct pci_dev *dev)
485 {
486         u8 data;
487 
488         /* Change clock frequency for the first UART. */
489         pci_read_config_byte(dev, 0x6f, &data);
490         pci_write_config_byte(dev, 0x6f, data & 0xef);
491 
492         /* If this card has 2 UART, we have to do the same with second UART. */
493         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
494             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
495                 pci_read_config_byte(dev, 0x73, &data);
496                 pci_write_config_byte(dev, 0x73, data & 0xef);
497         }
498         return 0;
499 }
500 
501 static int pci_siig_init(struct pci_dev *dev)
502 {
503         unsigned int type = dev->device & 0xff00;
504 
505         if (type == 0x1000)
506                 return pci_siig10x_init(dev);
507         else if (type == 0x2000)
508                 return pci_siig20x_init(dev);
509 
510         moan_device("Unknown SIIG card", dev);
511         return -ENODEV;
512 }
513 
514 static int pci_siig_setup(struct serial_private *priv,
515                           const struct pciserial_board *board,
516                           struct uart_8250_port *port, int idx)
517 {
518         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
519 
520         if (idx > 3) {
521                 bar = 4;
522                 offset = (idx - 4) * 8;
523         }
524 
525         return setup_port(priv, port, bar, offset, 0);
526 }
527 
528 /*
529  * Timedia has an explosion of boards, and to avoid the PCI table from
530  * growing *huge*, we use this function to collapse some 70 entries
531  * in the PCI table into one, for sanity's and compactness's sake.
532  */
533 static const unsigned short timedia_single_port[] = {
534         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
535 };
536 
537 static const unsigned short timedia_dual_port[] = {
538         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
539         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
540         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
541         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
542         0xD079, 0
543 };
544 
545 static const unsigned short timedia_quad_port[] = {
546         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
547         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
548         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
549         0xB157, 0
550 };
551 
552 static const unsigned short timedia_eight_port[] = {
553         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
554         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
555 };
556 
557 static const struct timedia_struct {
558         int num;
559         const unsigned short *ids;
560 } timedia_data[] = {
561         { 1, timedia_single_port },
562         { 2, timedia_dual_port },
563         { 4, timedia_quad_port },
564         { 8, timedia_eight_port }
565 };
566 
567 /*
568  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
569  * listing them individually, this driver merely grabs them all with
570  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
571  * and should be left free to be claimed by parport_serial instead.
572  */
573 static int pci_timedia_probe(struct pci_dev *dev)
574 {
575         /*
576          * Check the third digit of the subdevice ID
577          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
578          */
579         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
580                 dev_info(&dev->dev,
581                         "ignoring Timedia subdevice %04x for parport_serial\n",
582                         dev->subsystem_device);
583                 return -ENODEV;
584         }
585 
586         return 0;
587 }
588 
589 static int pci_timedia_init(struct pci_dev *dev)
590 {
591         const unsigned short *ids;
592         int i, j;
593 
594         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
595                 ids = timedia_data[i].ids;
596                 for (j = 0; ids[j]; j++)
597                         if (dev->subsystem_device == ids[j])
598                                 return timedia_data[i].num;
599         }
600         return 0;
601 }
602 
603 /*
604  * Timedia/SUNIX uses a mixture of BARs and offsets
605  * Ugh, this is ugly as all hell --- TYT
606  */
607 static int
608 pci_timedia_setup(struct serial_private *priv,
609                   const struct pciserial_board *board,
610                   struct uart_8250_port *port, int idx)
611 {
612         unsigned int bar = 0, offset = board->first_offset;
613 
614         switch (idx) {
615         case 0:
616                 bar = 0;
617                 break;
618         case 1:
619                 offset = board->uart_offset;
620                 bar = 0;
621                 break;
622         case 2:
623                 bar = 1;
624                 break;
625         case 3:
626                 offset = board->uart_offset;
627                 /* FALLTHROUGH */
628         case 4: /* BAR 2 */
629         case 5: /* BAR 3 */
630         case 6: /* BAR 4 */
631         case 7: /* BAR 5 */
632                 bar = idx - 2;
633         }
634 
635         return setup_port(priv, port, bar, offset, board->reg_shift);
636 }
637 
638 /*
639  * Some Titan cards are also a little weird
640  */
641 static int
642 titan_400l_800l_setup(struct serial_private *priv,
643                       const struct pciserial_board *board,
644                       struct uart_8250_port *port, int idx)
645 {
646         unsigned int bar, offset = board->first_offset;
647 
648         switch (idx) {
649         case 0:
650                 bar = 1;
651                 break;
652         case 1:
653                 bar = 2;
654                 break;
655         default:
656                 bar = 4;
657                 offset = (idx - 2) * board->uart_offset;
658         }
659 
660         return setup_port(priv, port, bar, offset, board->reg_shift);
661 }
662 
663 static int pci_xircom_init(struct pci_dev *dev)
664 {
665         msleep(100);
666         return 0;
667 }
668 
669 static int pci_ni8420_init(struct pci_dev *dev)
670 {
671         void __iomem *p;
672         unsigned int bar = 0;
673 
674         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
675                 moan_device("no memory in bar", dev);
676                 return 0;
677         }
678 
679         p = pci_ioremap_bar(dev, bar);
680         if (p == NULL)
681                 return -ENOMEM;
682 
683         /* Enable CPU Interrupt */
684         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
685                p + NI8420_INT_ENABLE_REG);
686 
687         iounmap(p);
688         return 0;
689 }
690 
691 #define MITE_IOWBSR1_WSIZE      0xa
692 #define MITE_IOWBSR1_WIN_OFFSET 0x800
693 #define MITE_IOWBSR1_WENAB      (1 << 7)
694 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
695 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
696 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
697 
698 static int pci_ni8430_init(struct pci_dev *dev)
699 {
700         void __iomem *p;
701         struct pci_bus_region region;
702         u32 device_window;
703         unsigned int bar = 0;
704 
705         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
706                 moan_device("no memory in bar", dev);
707                 return 0;
708         }
709 
710         p = pci_ioremap_bar(dev, bar);
711         if (p == NULL)
712                 return -ENOMEM;
713 
714         /*
715          * Set device window address and size in BAR0, while acknowledging that
716          * the resource structure may contain a translated address that differs
717          * from the address the device responds to.
718          */
719         pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
720         device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
721                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
722         writel(device_window, p + MITE_IOWBSR1);
723 
724         /* Set window access to go to RAMSEL IO address space */
725         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
726                p + MITE_IOWCR1);
727 
728         /* Enable IO Bus Interrupt 0 */
729         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
730 
731         /* Enable CPU Interrupt */
732         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
733 
734         iounmap(p);
735         return 0;
736 }
737 
738 /* UART Port Control Register */
739 #define NI8430_PORTCON  0x0f
740 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
741 
742 static int
743 pci_ni8430_setup(struct serial_private *priv,
744                  const struct pciserial_board *board,
745                  struct uart_8250_port *port, int idx)
746 {
747         struct pci_dev *dev = priv->dev;
748         void __iomem *p;
749         unsigned int bar, offset = board->first_offset;
750 
751         if (idx >= board->num_ports)
752                 return 1;
753 
754         bar = FL_GET_BASE(board->flags);
755         offset += idx * board->uart_offset;
756 
757         p = pci_ioremap_bar(dev, bar);
758         if (!p)
759                 return -ENOMEM;
760 
761         /* enable the transceiver */
762         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
763                p + offset + NI8430_PORTCON);
764 
765         iounmap(p);
766 
767         return setup_port(priv, port, bar, offset, board->reg_shift);
768 }
769 
770 static int pci_netmos_9900_setup(struct serial_private *priv,
771                                 const struct pciserial_board *board,
772                                 struct uart_8250_port *port, int idx)
773 {
774         unsigned int bar;
775 
776         if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
777             (priv->dev->subsystem_device & 0xff00) == 0x3000) {
778                 /* netmos apparently orders BARs by datasheet layout, so serial
779                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
780                  */
781                 bar = 3 * idx;
782 
783                 return setup_port(priv, port, bar, 0, board->reg_shift);
784         } else {
785                 return pci_default_setup(priv, board, port, idx);
786         }
787 }
788 
789 /* the 99xx series comes with a range of device IDs and a variety
790  * of capabilities:
791  *
792  * 9900 has varying capabilities and can cascade to sub-controllers
793  *   (cascading should be purely internal)
794  * 9904 is hardwired with 4 serial ports
795  * 9912 and 9922 are hardwired with 2 serial ports
796  */
797 static int pci_netmos_9900_numports(struct pci_dev *dev)
798 {
799         unsigned int c = dev->class;
800         unsigned int pi;
801         unsigned short sub_serports;
802 
803         pi = c & 0xff;
804 
805         if (pi == 2)
806                 return 1;
807 
808         if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
809                 /* two possibilities: 0x30ps encodes number of parallel and
810                  * serial ports, or 0x1000 indicates *something*. This is not
811                  * immediately obvious, since the 2s1p+4s configuration seems
812                  * to offer all functionality on functions 0..2, while still
813                  * advertising the same function 3 as the 4s+2s1p config.
814                  */
815                 sub_serports = dev->subsystem_device & 0xf;
816                 if (sub_serports > 0)
817                         return sub_serports;
818 
819                 dev_err(&dev->dev,
820                         "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
821                 return 0;
822         }
823 
824         moan_device("unknown NetMos/Mostech program interface", dev);
825         return 0;
826 }
827 
828 static int pci_netmos_init(struct pci_dev *dev)
829 {
830         /* subdevice 0x00PS means <P> parallel, <S> serial */
831         unsigned int num_serial = dev->subsystem_device & 0xf;
832 
833         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
834                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
835                 return 0;
836 
837         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
838                         dev->subsystem_device == 0x0299)
839                 return 0;
840 
841         switch (dev->device) { /* FALLTHROUGH on all */
842         case PCI_DEVICE_ID_NETMOS_9904:
843         case PCI_DEVICE_ID_NETMOS_9912:
844         case PCI_DEVICE_ID_NETMOS_9922:
845         case PCI_DEVICE_ID_NETMOS_9900:
846                 num_serial = pci_netmos_9900_numports(dev);
847                 break;
848 
849         default:
850                 break;
851         }
852 
853         if (num_serial == 0) {
854                 moan_device("unknown NetMos/Mostech device", dev);
855                 return -ENODEV;
856         }
857 
858         return num_serial;
859 }
860 
861 /*
862  * These chips are available with optionally one parallel port and up to
863  * two serial ports. Unfortunately they all have the same product id.
864  *
865  * Basic configuration is done over a region of 32 I/O ports. The base
866  * ioport is called INTA or INTC, depending on docs/other drivers.
867  *
868  * The region of the 32 I/O ports is configured in POSIO0R...
869  */
870 
871 /* registers */
872 #define ITE_887x_MISCR          0x9c
873 #define ITE_887x_INTCBAR        0x78
874 #define ITE_887x_UARTBAR        0x7c
875 #define ITE_887x_PS0BAR         0x10
876 #define ITE_887x_POSIO0         0x60
877 
878 /* I/O space size */
879 #define ITE_887x_IOSIZE         32
880 /* I/O space size (bits 26-24; 8 bytes = 011b) */
881 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
882 /* I/O space size (bits 26-24; 32 bytes = 101b) */
883 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
884 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
885 #define ITE_887x_POSIO_SPEED            (3 << 29)
886 /* enable IO_Space bit */
887 #define ITE_887x_POSIO_ENABLE           (1 << 31)
888 
889 static int pci_ite887x_init(struct pci_dev *dev)
890 {
891         /* inta_addr are the configuration addresses of the ITE */
892         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
893                                                         0x200, 0x280, 0 };
894         int ret, i, type;
895         struct resource *iobase = NULL;
896         u32 miscr, uartbar, ioport;
897 
898         /* search for the base-ioport */
899         i = 0;
900         while (inta_addr[i] && iobase == NULL) {
901                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
902                                                                 "ite887x");
903                 if (iobase != NULL) {
904                         /* write POSIO0R - speed | size | ioport */
905                         pci_write_config_dword(dev, ITE_887x_POSIO0,
906                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
907                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
908                         /* write INTCBAR - ioport */
909                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
910                                                                 inta_addr[i]);
911                         ret = inb(inta_addr[i]);
912                         if (ret != 0xff) {
913                                 /* ioport connected */
914                                 break;
915                         }
916                         release_region(iobase->start, ITE_887x_IOSIZE);
917                         iobase = NULL;
918                 }
919                 i++;
920         }
921 
922         if (!inta_addr[i]) {
923                 dev_err(&dev->dev, "ite887x: could not find iobase\n");
924                 return -ENODEV;
925         }
926 
927         /* start of undocumented type checking (see parport_pc.c) */
928         type = inb(iobase->start + 0x18) & 0x0f;
929 
930         switch (type) {
931         case 0x2:       /* ITE8871 (1P) */
932         case 0xa:       /* ITE8875 (1P) */
933                 ret = 0;
934                 break;
935         case 0xe:       /* ITE8872 (2S1P) */
936                 ret = 2;
937                 break;
938         case 0x6:       /* ITE8873 (1S) */
939                 ret = 1;
940                 break;
941         case 0x8:       /* ITE8874 (2S) */
942                 ret = 2;
943                 break;
944         default:
945                 moan_device("Unknown ITE887x", dev);
946                 ret = -ENODEV;
947         }
948 
949         /* configure all serial ports */
950         for (i = 0; i < ret; i++) {
951                 /* read the I/O port from the device */
952                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
953                                                                 &ioport);
954                 ioport &= 0x0000FF00;   /* the actual base address */
955                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
956                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
957                         ITE_887x_POSIO_IOSIZE_8 | ioport);
958 
959                 /* write the ioport to the UARTBAR */
960                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
961                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
962                 uartbar |= (ioport << (16 * i));        /* set the ioport */
963                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
964 
965                 /* get current config */
966                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
967                 /* disable interrupts (UARTx_Routing[3:0]) */
968                 miscr &= ~(0xf << (12 - 4 * i));
969                 /* activate the UART (UARTx_En) */
970                 miscr |= 1 << (23 - i);
971                 /* write new config with activated UART */
972                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
973         }
974 
975         if (ret <= 0) {
976                 /* the device has no UARTs if we get here */
977                 release_region(iobase->start, ITE_887x_IOSIZE);
978         }
979 
980         return ret;
981 }
982 
983 static void pci_ite887x_exit(struct pci_dev *dev)
984 {
985         u32 ioport;
986         /* the ioport is bit 0-15 in POSIO0R */
987         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
988         ioport &= 0xffff;
989         release_region(ioport, ITE_887x_IOSIZE);
990 }
991 
992 /*
993  * EndRun Technologies.
994  * Determine the number of ports available on the device.
995  */
996 #define PCI_VENDOR_ID_ENDRUN                    0x7401
997 #define PCI_DEVICE_ID_ENDRUN_1588       0xe100
998 
999 static int pci_endrun_init(struct pci_dev *dev)
1000 {
1001         u8 __iomem *p;
1002         unsigned long deviceID;
1003         unsigned int  number_uarts = 0;
1004 
1005         /* EndRun device is all 0xexxx */
1006         if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1007                 (dev->device & 0xf000) != 0xe000)
1008                 return 0;
1009 
1010         p = pci_iomap(dev, 0, 5);
1011         if (p == NULL)
1012                 return -ENOMEM;
1013 
1014         deviceID = ioread32(p);
1015         /* EndRun device */
1016         if (deviceID == 0x07000200) {
1017                 number_uarts = ioread8(p + 4);
1018                 dev_dbg(&dev->dev,
1019                         "%d ports detected on EndRun PCI Express device\n",
1020                         number_uarts);
1021         }
1022         pci_iounmap(dev, p);
1023         return number_uarts;
1024 }
1025 
1026 /*
1027  * Oxford Semiconductor Inc.
1028  * Check that device is part of the Tornado range of devices, then determine
1029  * the number of ports available on the device.
1030  */
1031 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1032 {
1033         u8 __iomem *p;
1034         unsigned long deviceID;
1035         unsigned int  number_uarts = 0;
1036 
1037         /* OxSemi Tornado devices are all 0xCxxx */
1038         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1039             (dev->device & 0xF000) != 0xC000)
1040                 return 0;
1041 
1042         p = pci_iomap(dev, 0, 5);
1043         if (p == NULL)
1044                 return -ENOMEM;
1045 
1046         deviceID = ioread32(p);
1047         /* Tornado device */
1048         if (deviceID == 0x07000200) {
1049                 number_uarts = ioread8(p + 4);
1050                 dev_dbg(&dev->dev,
1051                         "%d ports detected on Oxford PCI Express device\n",
1052                         number_uarts);
1053         }
1054         pci_iounmap(dev, p);
1055         return number_uarts;
1056 }
1057 
1058 static int pci_asix_setup(struct serial_private *priv,
1059                   const struct pciserial_board *board,
1060                   struct uart_8250_port *port, int idx)
1061 {
1062         port->bugs |= UART_BUG_PARITY;
1063         return pci_default_setup(priv, board, port, idx);
1064 }
1065 
1066 /* Quatech devices have their own extra interface features */
1067 
1068 struct quatech_feature {
1069         u16 devid;
1070         bool amcc;
1071 };
1072 
1073 #define QPCR_TEST_FOR1          0x3F
1074 #define QPCR_TEST_GET1          0x00
1075 #define QPCR_TEST_FOR2          0x40
1076 #define QPCR_TEST_GET2          0x40
1077 #define QPCR_TEST_FOR3          0x80
1078 #define QPCR_TEST_GET3          0x40
1079 #define QPCR_TEST_FOR4          0xC0
1080 #define QPCR_TEST_GET4          0x80
1081 
1082 #define QOPR_CLOCK_X1           0x0000
1083 #define QOPR_CLOCK_X2           0x0001
1084 #define QOPR_CLOCK_X4           0x0002
1085 #define QOPR_CLOCK_X8           0x0003
1086 #define QOPR_CLOCK_RATE_MASK    0x0003
1087 
1088 
1089 static struct quatech_feature quatech_cards[] = {
1090         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1091         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1092         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1093         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1094         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1095         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1096         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1097         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1098         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1099         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1100         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1101         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1102         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1103         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1104         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1105         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1106         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1107         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1108         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1109         { 0, }
1110 };
1111 
1112 static int pci_quatech_amcc(u16 devid)
1113 {
1114         struct quatech_feature *qf = &quatech_cards[0];
1115         while (qf->devid) {
1116                 if (qf->devid == devid)
1117                         return qf->amcc;
1118                 qf++;
1119         }
1120         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1121         return 0;
1122 };
1123 
1124 static int pci_quatech_rqopr(struct uart_8250_port *port)
1125 {
1126         unsigned long base = port->port.iobase;
1127         u8 LCR, val;
1128 
1129         LCR = inb(base + UART_LCR);
1130         outb(0xBF, base + UART_LCR);
1131         val = inb(base + UART_SCR);
1132         outb(LCR, base + UART_LCR);
1133         return val;
1134 }
1135 
1136 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1137 {
1138         unsigned long base = port->port.iobase;
1139         u8 LCR, val;
1140 
1141         LCR = inb(base + UART_LCR);
1142         outb(0xBF, base + UART_LCR);
1143         val = inb(base + UART_SCR);
1144         outb(qopr, base + UART_SCR);
1145         outb(LCR, base + UART_LCR);
1146 }
1147 
1148 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1149 {
1150         unsigned long base = port->port.iobase;
1151         u8 LCR, val, qmcr;
1152 
1153         LCR = inb(base + UART_LCR);
1154         outb(0xBF, base + UART_LCR);
1155         val = inb(base + UART_SCR);
1156         outb(val | 0x10, base + UART_SCR);
1157         qmcr = inb(base + UART_MCR);
1158         outb(val, base + UART_SCR);
1159         outb(LCR, base + UART_LCR);
1160 
1161         return qmcr;
1162 }
1163 
1164 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1165 {
1166         unsigned long base = port->port.iobase;
1167         u8 LCR, val;
1168 
1169         LCR = inb(base + UART_LCR);
1170         outb(0xBF, base + UART_LCR);
1171         val = inb(base + UART_SCR);
1172         outb(val | 0x10, base + UART_SCR);
1173         outb(qmcr, base + UART_MCR);
1174         outb(val, base + UART_SCR);
1175         outb(LCR, base + UART_LCR);
1176 }
1177 
1178 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1179 {
1180         unsigned long base = port->port.iobase;
1181         u8 LCR, val;
1182 
1183         LCR = inb(base + UART_LCR);
1184         outb(0xBF, base + UART_LCR);
1185         val = inb(base + UART_SCR);
1186         if (val & 0x20) {
1187                 outb(0x80, UART_LCR);
1188                 if (!(inb(UART_SCR) & 0x20)) {
1189                         outb(LCR, base + UART_LCR);
1190                         return 1;
1191                 }
1192         }
1193         return 0;
1194 }
1195 
1196 static int pci_quatech_test(struct uart_8250_port *port)
1197 {
1198         u8 reg, qopr;
1199 
1200         qopr = pci_quatech_rqopr(port);
1201         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1202         reg = pci_quatech_rqopr(port) & 0xC0;
1203         if (reg != QPCR_TEST_GET1)
1204                 return -EINVAL;
1205         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1206         reg = pci_quatech_rqopr(port) & 0xC0;
1207         if (reg != QPCR_TEST_GET2)
1208                 return -EINVAL;
1209         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1210         reg = pci_quatech_rqopr(port) & 0xC0;
1211         if (reg != QPCR_TEST_GET3)
1212                 return -EINVAL;
1213         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1214         reg = pci_quatech_rqopr(port) & 0xC0;
1215         if (reg != QPCR_TEST_GET4)
1216                 return -EINVAL;
1217 
1218         pci_quatech_wqopr(port, qopr);
1219         return 0;
1220 }
1221 
1222 static int pci_quatech_clock(struct uart_8250_port *port)
1223 {
1224         u8 qopr, reg, set;
1225         unsigned long clock;
1226 
1227         if (pci_quatech_test(port) < 0)
1228                 return 1843200;
1229 
1230         qopr = pci_quatech_rqopr(port);
1231 
1232         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1233         reg = pci_quatech_rqopr(port);
1234         if (reg & QOPR_CLOCK_X8) {
1235                 clock = 1843200;
1236                 goto out;
1237         }
1238         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1239         reg = pci_quatech_rqopr(port);
1240         if (!(reg & QOPR_CLOCK_X8)) {
1241                 clock = 1843200;
1242                 goto out;
1243         }
1244         reg &= QOPR_CLOCK_X8;
1245         if (reg == QOPR_CLOCK_X2) {
1246                 clock =  3685400;
1247                 set = QOPR_CLOCK_X2;
1248         } else if (reg == QOPR_CLOCK_X4) {
1249                 clock = 7372800;
1250                 set = QOPR_CLOCK_X4;
1251         } else if (reg == QOPR_CLOCK_X8) {
1252                 clock = 14745600;
1253                 set = QOPR_CLOCK_X8;
1254         } else {
1255                 clock = 1843200;
1256                 set = QOPR_CLOCK_X1;
1257         }
1258         qopr &= ~QOPR_CLOCK_RATE_MASK;
1259         qopr |= set;
1260 
1261 out:
1262         pci_quatech_wqopr(port, qopr);
1263         return clock;
1264 }
1265 
1266 static int pci_quatech_rs422(struct uart_8250_port *port)
1267 {
1268         u8 qmcr;
1269         int rs422 = 0;
1270 
1271         if (!pci_quatech_has_qmcr(port))
1272                 return 0;
1273         qmcr = pci_quatech_rqmcr(port);
1274         pci_quatech_wqmcr(port, 0xFF);
1275         if (pci_quatech_rqmcr(port))
1276                 rs422 = 1;
1277         pci_quatech_wqmcr(port, qmcr);
1278         return rs422;
1279 }
1280 
1281 static int pci_quatech_init(struct pci_dev *dev)
1282 {
1283         if (pci_quatech_amcc(dev->device)) {
1284                 unsigned long base = pci_resource_start(dev, 0);
1285                 if (base) {
1286                         u32 tmp;
1287 
1288                         outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1289                         tmp = inl(base + 0x3c);
1290                         outl(tmp | 0x01000000, base + 0x3c);
1291                         outl(tmp &= ~0x01000000, base + 0x3c);
1292                 }
1293         }
1294         return 0;
1295 }
1296 
1297 static int pci_quatech_setup(struct serial_private *priv,
1298                   const struct pciserial_board *board,
1299                   struct uart_8250_port *port, int idx)
1300 {
1301         /* Needed by pci_quatech calls below */
1302         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1303         /* Set up the clocking */
1304         port->port.uartclk = pci_quatech_clock(port);
1305         /* For now just warn about RS422 */
1306         if (pci_quatech_rs422(port))
1307                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1308         return pci_default_setup(priv, board, port, idx);
1309 }
1310 
1311 static void pci_quatech_exit(struct pci_dev *dev)
1312 {
1313 }
1314 
1315 static int pci_default_setup(struct serial_private *priv,
1316                   const struct pciserial_board *board,
1317                   struct uart_8250_port *port, int idx)
1318 {
1319         unsigned int bar, offset = board->first_offset, maxnr;
1320 
1321         bar = FL_GET_BASE(board->flags);
1322         if (board->flags & FL_BASE_BARS)
1323                 bar += idx;
1324         else
1325                 offset += idx * board->uart_offset;
1326 
1327         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1328                 (board->reg_shift + 3);
1329 
1330         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1331                 return 1;
1332 
1333         return setup_port(priv, port, bar, offset, board->reg_shift);
1334 }
1335 
1336 static int
1337 ce4100_serial_setup(struct serial_private *priv,
1338                   const struct pciserial_board *board,
1339                   struct uart_8250_port *port, int idx)
1340 {
1341         int ret;
1342 
1343         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1344         port->port.iotype = UPIO_MEM32;
1345         port->port.type = PORT_XSCALE;
1346         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1347         port->port.regshift = 2;
1348 
1349         return ret;
1350 }
1351 
1352 #define PCI_DEVICE_ID_INTEL_BYT_UART1   0x0f0a
1353 #define PCI_DEVICE_ID_INTEL_BYT_UART2   0x0f0c
1354 
1355 #define PCI_DEVICE_ID_INTEL_BSW_UART1   0x228a
1356 #define PCI_DEVICE_ID_INTEL_BSW_UART2   0x228c
1357 
1358 #define PCI_DEVICE_ID_INTEL_BDW_UART1   0x9ce3
1359 #define PCI_DEVICE_ID_INTEL_BDW_UART2   0x9ce4
1360 
1361 #define BYT_PRV_CLK                     0x800
1362 #define BYT_PRV_CLK_EN                  (1 << 0)
1363 #define BYT_PRV_CLK_M_VAL_SHIFT         1
1364 #define BYT_PRV_CLK_N_VAL_SHIFT         16
1365 #define BYT_PRV_CLK_UPDATE              (1 << 31)
1366 
1367 #define BYT_TX_OVF_INT                  0x820
1368 #define BYT_TX_OVF_INT_MASK             (1 << 1)
1369 
1370 static void
1371 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1372                 struct ktermios *old)
1373 {
1374         unsigned int baud = tty_termios_baud_rate(termios);
1375         unsigned long fref = 100000000, fuart = baud * 16;
1376         unsigned long w = BIT(15) - 1;
1377         unsigned long m, n;
1378         u32 reg;
1379 
1380         /* Get Fuart closer to Fref */
1381         fuart *= rounddown_pow_of_two(fref / fuart);
1382 
1383         /*
1384          * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1385          * dividers must be adjusted.
1386          *
1387          * uartclk = (m / n) * 100 MHz, where m <= n
1388          */
1389         rational_best_approximation(fuart, fref, w, w, &m, &n);
1390         p->uartclk = fuart;
1391 
1392         /* Reset the clock */
1393         reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1394         writel(reg, p->membase + BYT_PRV_CLK);
1395         reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1396         writel(reg, p->membase + BYT_PRV_CLK);
1397 
1398         p->status &= ~UPSTAT_AUTOCTS;
1399         if (termios->c_cflag & CRTSCTS)
1400                 p->status |= UPSTAT_AUTOCTS;
1401 
1402         serial8250_do_set_termios(p, termios, old);
1403 }
1404 
1405 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1406 {
1407         struct dw_dma_slave *dws = param;
1408 
1409         if (dws->dma_dev != chan->device->dev)
1410                 return false;
1411 
1412         chan->private = dws;
1413         return true;
1414 }
1415 
1416 static int
1417 byt_serial_setup(struct serial_private *priv,
1418                  const struct pciserial_board *board,
1419                  struct uart_8250_port *port, int idx)
1420 {
1421         struct pci_dev *pdev = priv->dev;
1422         struct device *dev = port->port.dev;
1423         struct uart_8250_dma *dma;
1424         struct dw_dma_slave *tx_param, *rx_param;
1425         struct pci_dev *dma_dev;
1426         int ret;
1427 
1428         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1429         if (!dma)
1430                 return -ENOMEM;
1431 
1432         tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1433         if (!tx_param)
1434                 return -ENOMEM;
1435 
1436         rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1437         if (!rx_param)
1438                 return -ENOMEM;
1439 
1440         switch (pdev->device) {
1441         case PCI_DEVICE_ID_INTEL_BYT_UART1:
1442         case PCI_DEVICE_ID_INTEL_BSW_UART1:
1443         case PCI_DEVICE_ID_INTEL_BDW_UART1:
1444                 rx_param->src_id = 3;
1445                 tx_param->dst_id = 2;
1446                 break;
1447         case PCI_DEVICE_ID_INTEL_BYT_UART2:
1448         case PCI_DEVICE_ID_INTEL_BSW_UART2:
1449         case PCI_DEVICE_ID_INTEL_BDW_UART2:
1450                 rx_param->src_id = 5;
1451                 tx_param->dst_id = 4;
1452                 break;
1453         default:
1454                 return -EINVAL;
1455         }
1456 
1457         rx_param->src_master = 1;
1458         rx_param->dst_master = 0;
1459 
1460         dma->rxconf.src_maxburst = 16;
1461 
1462         tx_param->src_master = 1;
1463         tx_param->dst_master = 0;
1464 
1465         dma->txconf.dst_maxburst = 16;
1466 
1467         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1468         rx_param->dma_dev = &dma_dev->dev;
1469         tx_param->dma_dev = &dma_dev->dev;
1470 
1471         dma->fn = byt_dma_filter;
1472         dma->rx_param = rx_param;
1473         dma->tx_param = tx_param;
1474 
1475         ret = pci_default_setup(priv, board, port, idx);
1476         port->port.iotype = UPIO_MEM;
1477         port->port.type = PORT_16550A;
1478         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1479         port->port.set_termios = byt_set_termios;
1480         port->port.fifosize = 64;
1481         port->tx_loadsz = 64;
1482         port->dma = dma;
1483         port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1484 
1485         /* Disable Tx counter interrupts */
1486         writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1487 
1488         return ret;
1489 }
1490 
1491 static int
1492 pci_omegapci_setup(struct serial_private *priv,
1493                       const struct pciserial_board *board,
1494                       struct uart_8250_port *port, int idx)
1495 {
1496         return setup_port(priv, port, 2, idx * 8, 0);
1497 }
1498 
1499 static int
1500 pci_brcm_trumanage_setup(struct serial_private *priv,
1501                          const struct pciserial_board *board,
1502                          struct uart_8250_port *port, int idx)
1503 {
1504         int ret = pci_default_setup(priv, board, port, idx);
1505 
1506         port->port.type = PORT_BRCM_TRUMANAGE;
1507         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1508         return ret;
1509 }
1510 
1511 /* RTS will control by MCR if this bit is 0 */
1512 #define FINTEK_RTS_CONTROL_BY_HW        BIT(4)
1513 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1514 #define FINTEK_RTS_INVERT               BIT(5)
1515 
1516 /* We should do proper H/W transceiver setting before change to RS485 mode */
1517 static int pci_fintek_rs485_config(struct uart_port *port,
1518                                struct serial_rs485 *rs485)
1519 {
1520         struct pci_dev *pci_dev = to_pci_dev(port->dev);
1521         u8 setting;
1522         u8 *index = (u8 *) port->private_data;
1523 
1524         pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1525 
1526         if (!rs485)
1527                 rs485 = &port->rs485;
1528         else if (rs485->flags & SER_RS485_ENABLED)
1529                 memset(rs485->padding, 0, sizeof(rs485->padding));
1530         else
1531                 memset(rs485, 0, sizeof(*rs485));
1532 
1533         /* F81504/508/512 not support RTS delay before or after send */
1534         rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1535 
1536         if (rs485->flags & SER_RS485_ENABLED) {
1537                 /* Enable RTS H/W control mode */
1538                 setting |= FINTEK_RTS_CONTROL_BY_HW;
1539 
1540                 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1541                         /* RTS driving high on TX */
1542                         setting &= ~FINTEK_RTS_INVERT;
1543                 } else {
1544                         /* RTS driving low on TX */
1545                         setting |= FINTEK_RTS_INVERT;
1546                 }
1547 
1548                 rs485->delay_rts_after_send = 0;
1549                 rs485->delay_rts_before_send = 0;
1550         } else {
1551                 /* Disable RTS H/W control mode */
1552                 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1553         }
1554 
1555         pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1556 
1557         if (rs485 != &port->rs485)
1558                 port->rs485 = *rs485;
1559 
1560         return 0;
1561 }
1562 
1563 static int pci_fintek_setup(struct serial_private *priv,
1564                             const struct pciserial_board *board,
1565                             struct uart_8250_port *port, int idx)
1566 {
1567         struct pci_dev *pdev = priv->dev;
1568         u8 *data;
1569         u8 config_base;
1570         u16 iobase;
1571 
1572         config_base = 0x40 + 0x08 * idx;
1573 
1574         /* Get the io address from configuration space */
1575         pci_read_config_word(pdev, config_base + 4, &iobase);
1576 
1577         dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1578 
1579         port->port.iotype = UPIO_PORT;
1580         port->port.iobase = iobase;
1581         port->port.rs485_config = pci_fintek_rs485_config;
1582 
1583         data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1584         if (!data)
1585                 return -ENOMEM;
1586 
1587         /* preserve index in PCI configuration space */
1588         *data = idx;
1589         port->port.private_data = data;
1590 
1591         return 0;
1592 }
1593 
1594 static int pci_fintek_init(struct pci_dev *dev)
1595 {
1596         unsigned long iobase;
1597         u32 max_port, i;
1598         u32 bar_data[3];
1599         u8 config_base;
1600         struct serial_private *priv = pci_get_drvdata(dev);
1601         struct uart_8250_port *port;
1602 
1603         switch (dev->device) {
1604         case 0x1104: /* 4 ports */
1605         case 0x1108: /* 8 ports */
1606                 max_port = dev->device & 0xff;
1607                 break;
1608         case 0x1112: /* 12 ports */
1609                 max_port = 12;
1610                 break;
1611         default:
1612                 return -EINVAL;
1613         }
1614 
1615         /* Get the io address dispatch from the BIOS */
1616         pci_read_config_dword(dev, 0x24, &bar_data[0]);
1617         pci_read_config_dword(dev, 0x20, &bar_data[1]);
1618         pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1619 
1620         for (i = 0; i < max_port; ++i) {
1621                 /* UART0 configuration offset start from 0x40 */
1622                 config_base = 0x40 + 0x08 * i;
1623 
1624                 /* Calculate Real IO Port */
1625                 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1626 
1627                 /* Enable UART I/O port */
1628                 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1629 
1630                 /* Select 128-byte FIFO and 8x FIFO threshold */
1631                 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1632 
1633                 /* LSB UART */
1634                 pci_write_config_byte(dev, config_base + 0x04,
1635                                 (u8)(iobase & 0xff));
1636 
1637                 /* MSB UART */
1638                 pci_write_config_byte(dev, config_base + 0x05,
1639                                 (u8)((iobase & 0xff00) >> 8));
1640 
1641                 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1642 
1643                 if (priv) {
1644                         /* re-apply RS232/485 mode when
1645                          * pciserial_resume_ports()
1646                          */
1647                         port = serial8250_get_port(priv->line[i]);
1648                         pci_fintek_rs485_config(&port->port, NULL);
1649                 } else {
1650                         /* First init without port data
1651                          * force init to RS232 Mode
1652                          */
1653                         pci_write_config_byte(dev, config_base + 0x07, 0x01);
1654                 }
1655         }
1656 
1657         return max_port;
1658 }
1659 
1660 static int skip_tx_en_setup(struct serial_private *priv,
1661                         const struct pciserial_board *board,
1662                         struct uart_8250_port *port, int idx)
1663 {
1664         port->port.flags |= UPF_NO_TXEN_TEST;
1665         dev_dbg(&priv->dev->dev,
1666                 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1667                 priv->dev->vendor, priv->dev->device,
1668                 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1669 
1670         return pci_default_setup(priv, board, port, idx);
1671 }
1672 
1673 static void kt_handle_break(struct uart_port *p)
1674 {
1675         struct uart_8250_port *up = up_to_u8250p(p);
1676         /*
1677          * On receipt of a BI, serial device in Intel ME (Intel
1678          * management engine) needs to have its fifos cleared for sane
1679          * SOL (Serial Over Lan) output.
1680          */
1681         serial8250_clear_and_reinit_fifos(up);
1682 }
1683 
1684 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1685 {
1686         struct uart_8250_port *up = up_to_u8250p(p);
1687         unsigned int val;
1688 
1689         /*
1690          * When the Intel ME (management engine) gets reset its serial
1691          * port registers could return 0 momentarily.  Functions like
1692          * serial8250_console_write, read and save the IER, perform
1693          * some operation and then restore it.  In order to avoid
1694          * setting IER register inadvertently to 0, if the value read
1695          * is 0, double check with ier value in uart_8250_port and use
1696          * that instead.  up->ier should be the same value as what is
1697          * currently configured.
1698          */
1699         val = inb(p->iobase + offset);
1700         if (offset == UART_IER) {
1701                 if (val == 0)
1702                         val = up->ier;
1703         }
1704         return val;
1705 }
1706 
1707 static int kt_serial_setup(struct serial_private *priv,
1708                            const struct pciserial_board *board,
1709                            struct uart_8250_port *port, int idx)
1710 {
1711         port->port.flags |= UPF_BUG_THRE;
1712         port->port.serial_in = kt_serial_in;
1713         port->port.handle_break = kt_handle_break;
1714         return skip_tx_en_setup(priv, board, port, idx);
1715 }
1716 
1717 static int pci_eg20t_init(struct pci_dev *dev)
1718 {
1719 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1720         return -ENODEV;
1721 #else
1722         return 0;
1723 #endif
1724 }
1725 
1726 #define PCI_DEVICE_ID_EXAR_XR17V4358    0x4358
1727 #define PCI_DEVICE_ID_EXAR_XR17V8358    0x8358
1728 
1729 static int
1730 pci_xr17c154_setup(struct serial_private *priv,
1731                   const struct pciserial_board *board,
1732                   struct uart_8250_port *port, int idx)
1733 {
1734         port->port.flags |= UPF_EXAR_EFR;
1735         return pci_default_setup(priv, board, port, idx);
1736 }
1737 
1738 static inline int
1739 xr17v35x_has_slave(struct serial_private *priv)
1740 {
1741         const int dev_id = priv->dev->device;
1742 
1743         return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1744                 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1745 }
1746 
1747 static int
1748 pci_xr17v35x_setup(struct serial_private *priv,
1749                   const struct pciserial_board *board,
1750                   struct uart_8250_port *port, int idx)
1751 {
1752         u8 __iomem *p;
1753 
1754         p = pci_ioremap_bar(priv->dev, 0);
1755         if (p == NULL)
1756                 return -ENOMEM;
1757 
1758         port->port.flags |= UPF_EXAR_EFR;
1759 
1760         /*
1761          * Setup the uart clock for the devices on expansion slot to
1762          * half the clock speed of the main chip (which is 125MHz)
1763          */
1764         if (xr17v35x_has_slave(priv) && idx >= 8)
1765                 port->port.uartclk = (7812500 * 16 / 2);
1766 
1767         /*
1768          * Setup Multipurpose Input/Output pins.
1769          */
1770         if (idx == 0) {
1771                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1772                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1773                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1774                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1775                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1776                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1777                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1778                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1779                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1780                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1781                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1782                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1783         }
1784         writeb(0x00, p + UART_EXAR_8XMODE);
1785         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1786         writeb(128, p + UART_EXAR_TXTRG);
1787         writeb(128, p + UART_EXAR_RXTRG);
1788         iounmap(p);
1789 
1790         return pci_default_setup(priv, board, port, idx);
1791 }
1792 
1793 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1794 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1795 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1796 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1797 
1798 static int
1799 pci_fastcom335_setup(struct serial_private *priv,
1800                   const struct pciserial_board *board,
1801                   struct uart_8250_port *port, int idx)
1802 {
1803         u8 __iomem *p;
1804 
1805         p = pci_ioremap_bar(priv->dev, 0);
1806         if (p == NULL)
1807                 return -ENOMEM;
1808 
1809         port->port.flags |= UPF_EXAR_EFR;
1810 
1811         /*
1812          * Setup Multipurpose Input/Output pins.
1813          */
1814         if (idx == 0) {
1815                 switch (priv->dev->device) {
1816                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1817                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1818                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1819                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1820                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1821                         break;
1822                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1823                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1824                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1825                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1826                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1827                         break;
1828                 }
1829                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1830                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1831                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1832         }
1833         writeb(0x00, p + UART_EXAR_8XMODE);
1834         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1835         writeb(32, p + UART_EXAR_TXTRG);
1836         writeb(32, p + UART_EXAR_RXTRG);
1837         iounmap(p);
1838 
1839         return pci_default_setup(priv, board, port, idx);
1840 }
1841 
1842 static int
1843 pci_wch_ch353_setup(struct serial_private *priv,
1844                     const struct pciserial_board *board,
1845                     struct uart_8250_port *port, int idx)
1846 {
1847         port->port.flags |= UPF_FIXED_TYPE;
1848         port->port.type = PORT_16550A;
1849         return pci_default_setup(priv, board, port, idx);
1850 }
1851 
1852 static int
1853 pci_wch_ch38x_setup(struct serial_private *priv,
1854                     const struct pciserial_board *board,
1855                     struct uart_8250_port *port, int idx)
1856 {
1857         port->port.flags |= UPF_FIXED_TYPE;
1858         port->port.type = PORT_16850;
1859         return pci_default_setup(priv, board, port, idx);
1860 }
1861 
1862 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1863 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1864 #define PCI_DEVICE_ID_OCTPRO            0x0001
1865 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1866 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1867 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1868 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1869 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1870 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1871 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1872 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1873 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1874 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1875 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1876 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1877 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1878 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1879 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1880 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1881 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1882 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1883 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1884 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1885 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1886 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1887 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1888 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
1889 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1890 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1891 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1892 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1893 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1894 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1895 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1896 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1897 #define PCI_VENDOR_ID_WCH               0x4348
1898 #define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
1899 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1900 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1901 #define PCI_DEVICE_ID_WCH_CH353_1S1P    0x5053
1902 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1903 #define PCI_VENDOR_ID_AGESTAR           0x5372
1904 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1905 #define PCI_VENDOR_ID_ASIX              0x9710
1906 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1907 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1908 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1909 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1910 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1911 #define PCI_DEVICE_ID_INTEL_QRK_UART    0x0936
1912 
1913 #define PCI_VENDOR_ID_SUNIX             0x1fd4
1914 #define PCI_DEVICE_ID_SUNIX_1999        0x1999
1915 
1916 #define PCIE_VENDOR_ID_WCH              0x1c00
1917 #define PCIE_DEVICE_ID_WCH_CH382_2S1P   0x3250
1918 #define PCIE_DEVICE_ID_WCH_CH384_4S     0x3470
1919 #define PCIE_DEVICE_ID_WCH_CH382_2S     0x3253
1920 
1921 #define PCI_VENDOR_ID_PERICOM                   0x12D8
1922 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951        0x7951
1923 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952        0x7952
1924 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954        0x7954
1925 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958        0x7958
1926 
1927 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1928 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1929 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1930 
1931 /*
1932  * Master list of serial port init/setup/exit quirks.
1933  * This does not describe the general nature of the port.
1934  * (ie, baud base, number and location of ports, etc)
1935  *
1936  * This list is ordered alphabetically by vendor then device.
1937  * Specific entries must come before more generic entries.
1938  */
1939 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1940         /*
1941         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1942         */
1943         {
1944                 .vendor         = PCI_VENDOR_ID_AMCC,
1945                 .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1946                 .subvendor      = PCI_ANY_ID,
1947                 .subdevice      = PCI_ANY_ID,
1948                 .setup          = addidata_apci7800_setup,
1949         },
1950         /*
1951          * AFAVLAB cards - these may be called via parport_serial
1952          *  It is not clear whether this applies to all products.
1953          */
1954         {
1955                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1956                 .device         = PCI_ANY_ID,
1957                 .subvendor      = PCI_ANY_ID,
1958                 .subdevice      = PCI_ANY_ID,
1959                 .setup          = afavlab_setup,
1960         },
1961         /*
1962          * HP Diva
1963          */
1964         {
1965                 .vendor         = PCI_VENDOR_ID_HP,
1966                 .device         = PCI_DEVICE_ID_HP_DIVA,
1967                 .subvendor      = PCI_ANY_ID,
1968                 .subdevice      = PCI_ANY_ID,
1969                 .init           = pci_hp_diva_init,
1970                 .setup          = pci_hp_diva_setup,
1971         },
1972         /*
1973          * Intel
1974          */
1975         {
1976                 .vendor         = PCI_VENDOR_ID_INTEL,
1977                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1978                 .subvendor      = 0xe4bf,
1979                 .subdevice      = PCI_ANY_ID,
1980                 .init           = pci_inteli960ni_init,
1981                 .setup          = pci_default_setup,
1982         },
1983         {
1984                 .vendor         = PCI_VENDOR_ID_INTEL,
1985                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1986                 .subvendor      = PCI_ANY_ID,
1987                 .subdevice      = PCI_ANY_ID,
1988                 .setup          = skip_tx_en_setup,
1989         },
1990         {
1991                 .vendor         = PCI_VENDOR_ID_INTEL,
1992                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1993                 .subvendor      = PCI_ANY_ID,
1994                 .subdevice      = PCI_ANY_ID,
1995                 .setup          = skip_tx_en_setup,
1996         },
1997         {
1998                 .vendor         = PCI_VENDOR_ID_INTEL,
1999                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
2000                 .subvendor      = PCI_ANY_ID,
2001                 .subdevice      = PCI_ANY_ID,
2002                 .setup          = skip_tx_en_setup,
2003         },
2004         {
2005                 .vendor         = PCI_VENDOR_ID_INTEL,
2006                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
2007                 .subvendor      = PCI_ANY_ID,
2008                 .subdevice      = PCI_ANY_ID,
2009                 .setup          = ce4100_serial_setup,
2010         },
2011         {
2012                 .vendor         = PCI_VENDOR_ID_INTEL,
2013                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2014                 .subvendor      = PCI_ANY_ID,
2015                 .subdevice      = PCI_ANY_ID,
2016                 .setup          = kt_serial_setup,
2017         },
2018         {
2019                 .vendor         = PCI_VENDOR_ID_INTEL,
2020                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART1,
2021                 .subvendor      = PCI_ANY_ID,
2022                 .subdevice      = PCI_ANY_ID,
2023                 .setup          = byt_serial_setup,
2024         },
2025         {
2026                 .vendor         = PCI_VENDOR_ID_INTEL,
2027                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART2,
2028                 .subvendor      = PCI_ANY_ID,
2029                 .subdevice      = PCI_ANY_ID,
2030                 .setup          = byt_serial_setup,
2031         },
2032         {
2033                 .vendor         = PCI_VENDOR_ID_INTEL,
2034                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART1,
2035                 .subvendor      = PCI_ANY_ID,
2036                 .subdevice      = PCI_ANY_ID,
2037                 .setup          = byt_serial_setup,
2038         },
2039         {
2040                 .vendor         = PCI_VENDOR_ID_INTEL,
2041                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART2,
2042                 .subvendor      = PCI_ANY_ID,
2043                 .subdevice      = PCI_ANY_ID,
2044                 .setup          = byt_serial_setup,
2045         },
2046         {
2047                 .vendor         = PCI_VENDOR_ID_INTEL,
2048                 .device         = PCI_DEVICE_ID_INTEL_BDW_UART1,
2049                 .subvendor      = PCI_ANY_ID,
2050                 .subdevice      = PCI_ANY_ID,
2051                 .setup          = byt_serial_setup,
2052         },
2053         {
2054                 .vendor         = PCI_VENDOR_ID_INTEL,
2055                 .device         = PCI_DEVICE_ID_INTEL_BDW_UART2,
2056                 .subvendor      = PCI_ANY_ID,
2057                 .subdevice      = PCI_ANY_ID,
2058                 .setup          = byt_serial_setup,
2059         },
2060         /*
2061          * ITE
2062          */
2063         {
2064                 .vendor         = PCI_VENDOR_ID_ITE,
2065                 .device         = PCI_DEVICE_ID_ITE_8872,
2066                 .subvendor      = PCI_ANY_ID,
2067                 .subdevice      = PCI_ANY_ID,
2068                 .init           = pci_ite887x_init,
2069                 .setup          = pci_default_setup,
2070                 .exit           = pci_ite887x_exit,
2071         },
2072         /*
2073          * National Instruments
2074          */
2075         {
2076                 .vendor         = PCI_VENDOR_ID_NI,
2077                 .device         = PCI_DEVICE_ID_NI_PCI23216,
2078                 .subvendor      = PCI_ANY_ID,
2079                 .subdevice      = PCI_ANY_ID,
2080                 .init           = pci_ni8420_init,
2081                 .setup          = pci_default_setup,
2082                 .exit           = pci_ni8420_exit,
2083         },
2084         {
2085                 .vendor         = PCI_VENDOR_ID_NI,
2086                 .device         = PCI_DEVICE_ID_NI_PCI2328,
2087                 .subvendor      = PCI_ANY_ID,
2088                 .subdevice      = PCI_ANY_ID,
2089                 .init           = pci_ni8420_init,
2090                 .setup          = pci_default_setup,
2091                 .exit           = pci_ni8420_exit,
2092         },
2093         {
2094                 .vendor         = PCI_VENDOR_ID_NI,
2095                 .device         = PCI_DEVICE_ID_NI_PCI2324,
2096                 .subvendor      = PCI_ANY_ID,
2097                 .subdevice      = PCI_ANY_ID,
2098                 .init           = pci_ni8420_init,
2099                 .setup          = pci_default_setup,
2100                 .exit           = pci_ni8420_exit,
2101         },
2102         {
2103                 .vendor         = PCI_VENDOR_ID_NI,
2104                 .device         = PCI_DEVICE_ID_NI_PCI2322,
2105                 .subvendor      = PCI_ANY_ID,
2106                 .subdevice      = PCI_ANY_ID,
2107                 .init           = pci_ni8420_init,
2108                 .setup          = pci_default_setup,
2109                 .exit           = pci_ni8420_exit,
2110         },
2111         {
2112                 .vendor         = PCI_VENDOR_ID_NI,
2113                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
2114                 .subvendor      = PCI_ANY_ID,
2115                 .subdevice      = PCI_ANY_ID,
2116                 .init           = pci_ni8420_init,
2117                 .setup          = pci_default_setup,
2118                 .exit           = pci_ni8420_exit,
2119         },
2120         {
2121                 .vendor         = PCI_VENDOR_ID_NI,
2122                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
2123                 .subvendor      = PCI_ANY_ID,
2124                 .subdevice      = PCI_ANY_ID,
2125                 .init           = pci_ni8420_init,
2126                 .setup          = pci_default_setup,
2127                 .exit           = pci_ni8420_exit,
2128         },
2129         {
2130                 .vendor         = PCI_VENDOR_ID_NI,
2131                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
2132                 .subvendor      = PCI_ANY_ID,
2133                 .subdevice      = PCI_ANY_ID,
2134                 .init           = pci_ni8420_init,
2135                 .setup          = pci_default_setup,
2136                 .exit           = pci_ni8420_exit,
2137         },
2138         {
2139                 .vendor         = PCI_VENDOR_ID_NI,
2140                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
2141                 .subvendor      = PCI_ANY_ID,
2142                 .subdevice      = PCI_ANY_ID,
2143                 .init           = pci_ni8420_init,
2144                 .setup          = pci_default_setup,
2145                 .exit           = pci_ni8420_exit,
2146         },
2147         {
2148                 .vendor         = PCI_VENDOR_ID_NI,
2149                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
2150                 .subvendor      = PCI_ANY_ID,
2151                 .subdevice      = PCI_ANY_ID,
2152                 .init           = pci_ni8420_init,
2153                 .setup          = pci_default_setup,
2154                 .exit           = pci_ni8420_exit,
2155         },
2156         {
2157                 .vendor         = PCI_VENDOR_ID_NI,
2158                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
2159                 .subvendor      = PCI_ANY_ID,
2160                 .subdevice      = PCI_ANY_ID,
2161                 .init           = pci_ni8420_init,
2162                 .setup          = pci_default_setup,
2163                 .exit           = pci_ni8420_exit,
2164         },
2165         {
2166                 .vendor         = PCI_VENDOR_ID_NI,
2167                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
2168                 .subvendor      = PCI_ANY_ID,
2169                 .subdevice      = PCI_ANY_ID,
2170                 .init           = pci_ni8420_init,
2171                 .setup          = pci_default_setup,
2172                 .exit           = pci_ni8420_exit,
2173         },
2174         {
2175                 .vendor         = PCI_VENDOR_ID_NI,
2176                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
2177                 .subvendor      = PCI_ANY_ID,
2178                 .subdevice      = PCI_ANY_ID,
2179                 .init           = pci_ni8420_init,
2180                 .setup          = pci_default_setup,
2181                 .exit           = pci_ni8420_exit,
2182         },
2183         {
2184                 .vendor         = PCI_VENDOR_ID_NI,
2185                 .device         = PCI_ANY_ID,
2186                 .subvendor      = PCI_ANY_ID,
2187                 .subdevice      = PCI_ANY_ID,
2188                 .init           = pci_ni8430_init,
2189                 .setup          = pci_ni8430_setup,
2190                 .exit           = pci_ni8430_exit,
2191         },
2192         /* Quatech */
2193         {
2194                 .vendor         = PCI_VENDOR_ID_QUATECH,
2195                 .device         = PCI_ANY_ID,
2196                 .subvendor      = PCI_ANY_ID,
2197                 .subdevice      = PCI_ANY_ID,
2198                 .init           = pci_quatech_init,
2199                 .setup          = pci_quatech_setup,
2200                 .exit           = pci_quatech_exit,
2201         },
2202         /*
2203          * Panacom
2204          */
2205         {
2206                 .vendor         = PCI_VENDOR_ID_PANACOM,
2207                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2208                 .subvendor      = PCI_ANY_ID,
2209                 .subdevice      = PCI_ANY_ID,
2210                 .init           = pci_plx9050_init,
2211                 .setup          = pci_default_setup,
2212                 .exit           = pci_plx9050_exit,
2213         },
2214         {
2215                 .vendor         = PCI_VENDOR_ID_PANACOM,
2216                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2217                 .subvendor      = PCI_ANY_ID,
2218                 .subdevice      = PCI_ANY_ID,
2219                 .init           = pci_plx9050_init,
2220                 .setup          = pci_default_setup,
2221                 .exit           = pci_plx9050_exit,
2222         },
2223         /*
2224          * PLX
2225          */
2226         {
2227                 .vendor         = PCI_VENDOR_ID_PLX,
2228                 .device         = PCI_DEVICE_ID_PLX_9050,
2229                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2230                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2231                 .init           = pci_plx9050_init,
2232                 .setup          = pci_default_setup,
2233                 .exit           = pci_plx9050_exit,
2234         },
2235         {
2236                 .vendor         = PCI_VENDOR_ID_PLX,
2237                 .device         = PCI_DEVICE_ID_PLX_9050,
2238                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2239                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2240                 .init           = pci_plx9050_init,
2241                 .setup          = pci_default_setup,
2242                 .exit           = pci_plx9050_exit,
2243         },
2244         {
2245                 .vendor         = PCI_VENDOR_ID_PLX,
2246                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2247                 .subvendor      = PCI_VENDOR_ID_PLX,
2248                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2249                 .init           = pci_plx9050_init,
2250                 .setup          = pci_default_setup,
2251                 .exit           = pci_plx9050_exit,
2252         },
2253         /*
2254          * SBS Technologies, Inc., PMC-OCTALPRO 232
2255          */
2256         {
2257                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2258                 .device         = PCI_DEVICE_ID_OCTPRO,
2259                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2260                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2261                 .init           = sbs_init,
2262                 .setup          = sbs_setup,
2263                 .exit           = sbs_exit,
2264         },
2265         /*
2266          * SBS Technologies, Inc., PMC-OCTALPRO 422
2267          */
2268         {
2269                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2270                 .device         = PCI_DEVICE_ID_OCTPRO,
2271                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2272                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2273                 .init           = sbs_init,
2274                 .setup          = sbs_setup,
2275                 .exit           = sbs_exit,
2276         },
2277         /*
2278          * SBS Technologies, Inc., P-Octal 232
2279          */
2280         {
2281                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2282                 .device         = PCI_DEVICE_ID_OCTPRO,
2283                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2284                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2285                 .init           = sbs_init,
2286                 .setup          = sbs_setup,
2287                 .exit           = sbs_exit,
2288         },
2289         /*
2290          * SBS Technologies, Inc., P-Octal 422
2291          */
2292         {
2293                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2294                 .device         = PCI_DEVICE_ID_OCTPRO,
2295                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2296                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2297                 .init           = sbs_init,
2298                 .setup          = sbs_setup,
2299                 .exit           = sbs_exit,
2300         },
2301         /*
2302          * SIIG cards - these may be called via parport_serial
2303          */
2304         {
2305                 .vendor         = PCI_VENDOR_ID_SIIG,
2306                 .device         = PCI_ANY_ID,
2307                 .subvendor      = PCI_ANY_ID,
2308                 .subdevice      = PCI_ANY_ID,
2309                 .init           = pci_siig_init,
2310                 .setup          = pci_siig_setup,
2311         },
2312         /*
2313          * Titan cards
2314          */
2315         {
2316                 .vendor         = PCI_VENDOR_ID_TITAN,
2317                 .device         = PCI_DEVICE_ID_TITAN_400L,
2318                 .subvendor      = PCI_ANY_ID,
2319                 .subdevice      = PCI_ANY_ID,
2320                 .setup          = titan_400l_800l_setup,
2321         },
2322         {
2323                 .vendor         = PCI_VENDOR_ID_TITAN,
2324                 .device         = PCI_DEVICE_ID_TITAN_800L,
2325                 .subvendor      = PCI_ANY_ID,
2326                 .subdevice      = PCI_ANY_ID,
2327                 .setup          = titan_400l_800l_setup,
2328         },
2329         /*
2330          * Timedia cards
2331          */
2332         {
2333                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2334                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2335                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2336                 .subdevice      = PCI_ANY_ID,
2337                 .probe          = pci_timedia_probe,
2338                 .init           = pci_timedia_init,
2339                 .setup          = pci_timedia_setup,
2340         },
2341         {
2342                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2343                 .device         = PCI_ANY_ID,
2344                 .subvendor      = PCI_ANY_ID,
2345                 .subdevice      = PCI_ANY_ID,
2346                 .setup          = pci_timedia_setup,
2347         },
2348         /*
2349          * SUNIX (Timedia) cards
2350          * Do not "probe" for these cards as there is at least one combination
2351          * card that should be handled by parport_pc that doesn't match the
2352          * rule in pci_timedia_probe.
2353          * It is part number is MIO5079A but its subdevice ID is 0x0102.
2354          * There are some boards with part number SER5037AL that report
2355          * subdevice ID 0x0002.
2356          */
2357         {
2358                 .vendor         = PCI_VENDOR_ID_SUNIX,
2359                 .device         = PCI_DEVICE_ID_SUNIX_1999,
2360                 .subvendor      = PCI_VENDOR_ID_SUNIX,
2361                 .subdevice      = PCI_ANY_ID,
2362                 .init           = pci_timedia_init,
2363                 .setup          = pci_timedia_setup,
2364         },
2365         /*
2366          * Exar cards
2367          */
2368         {
2369                 .vendor = PCI_VENDOR_ID_EXAR,
2370                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2371                 .subvendor      = PCI_ANY_ID,
2372                 .subdevice      = PCI_ANY_ID,
2373                 .setup          = pci_xr17c154_setup,
2374         },
2375         {
2376                 .vendor = PCI_VENDOR_ID_EXAR,
2377                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2378                 .subvendor      = PCI_ANY_ID,
2379                 .subdevice      = PCI_ANY_ID,
2380                 .setup          = pci_xr17c154_setup,
2381         },
2382         {
2383                 .vendor = PCI_VENDOR_ID_EXAR,
2384                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2385                 .subvendor      = PCI_ANY_ID,
2386                 .subdevice      = PCI_ANY_ID,
2387                 .setup          = pci_xr17c154_setup,
2388         },
2389         {
2390                 .vendor = PCI_VENDOR_ID_EXAR,
2391                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2392                 .subvendor      = PCI_ANY_ID,
2393                 .subdevice      = PCI_ANY_ID,
2394                 .setup          = pci_xr17v35x_setup,
2395         },
2396         {
2397                 .vendor = PCI_VENDOR_ID_EXAR,
2398                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2399                 .subvendor      = PCI_ANY_ID,
2400                 .subdevice      = PCI_ANY_ID,
2401                 .setup          = pci_xr17v35x_setup,
2402         },
2403         {
2404                 .vendor = PCI_VENDOR_ID_EXAR,
2405                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2406                 .subvendor      = PCI_ANY_ID,
2407                 .subdevice      = PCI_ANY_ID,
2408                 .setup          = pci_xr17v35x_setup,
2409         },
2410         {
2411                 .vendor = PCI_VENDOR_ID_EXAR,
2412                 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2413                 .subvendor      = PCI_ANY_ID,
2414                 .subdevice      = PCI_ANY_ID,
2415                 .setup          = pci_xr17v35x_setup,
2416         },
2417         {
2418                 .vendor = PCI_VENDOR_ID_EXAR,
2419                 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2420                 .subvendor      = PCI_ANY_ID,
2421                 .subdevice      = PCI_ANY_ID,
2422                 .setup          = pci_xr17v35x_setup,
2423         },
2424         /*
2425          * Xircom cards
2426          */
2427         {
2428                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2429                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2430                 .subvendor      = PCI_ANY_ID,
2431                 .subdevice      = PCI_ANY_ID,
2432                 .init           = pci_xircom_init,
2433                 .setup          = pci_default_setup,
2434         },
2435         /*
2436          * Netmos cards - these may be called via parport_serial
2437          */
2438         {
2439                 .vendor         = PCI_VENDOR_ID_NETMOS,
2440                 .device         = PCI_ANY_ID,
2441                 .subvendor      = PCI_ANY_ID,
2442                 .subdevice      = PCI_ANY_ID,
2443                 .init           = pci_netmos_init,
2444                 .setup          = pci_netmos_9900_setup,
2445         },
2446         /*
2447          * EndRun Technologies
2448         */
2449         {
2450                 .vendor         = PCI_VENDOR_ID_ENDRUN,
2451                 .device         = PCI_ANY_ID,
2452                 .subvendor      = PCI_ANY_ID,
2453                 .subdevice      = PCI_ANY_ID,
2454                 .init           = pci_endrun_init,
2455                 .setup          = pci_default_setup,
2456         },
2457         /*
2458          * For Oxford Semiconductor Tornado based devices
2459          */
2460         {
2461                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2462                 .device         = PCI_ANY_ID,
2463                 .subvendor      = PCI_ANY_ID,
2464                 .subdevice      = PCI_ANY_ID,
2465                 .init           = pci_oxsemi_tornado_init,
2466                 .setup          = pci_default_setup,
2467         },
2468         {
2469                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2470                 .device         = PCI_ANY_ID,
2471                 .subvendor      = PCI_ANY_ID,
2472                 .subdevice      = PCI_ANY_ID,
2473                 .init           = pci_oxsemi_tornado_init,
2474                 .setup          = pci_default_setup,
2475         },
2476         {
2477                 .vendor         = PCI_VENDOR_ID_DIGI,
2478                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2479                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2480                 .subdevice              = PCI_ANY_ID,
2481                 .init                   = pci_oxsemi_tornado_init,
2482                 .setup          = pci_default_setup,
2483         },
2484         {
2485                 .vendor         = PCI_VENDOR_ID_INTEL,
2486                 .device         = 0x8811,
2487                 .subvendor      = PCI_ANY_ID,
2488                 .subdevice      = PCI_ANY_ID,
2489                 .init           = pci_eg20t_init,
2490                 .setup          = pci_default_setup,
2491         },
2492         {
2493                 .vendor         = PCI_VENDOR_ID_INTEL,
2494                 .device         = 0x8812,
2495                 .subvendor      = PCI_ANY_ID,
2496                 .subdevice      = PCI_ANY_ID,
2497                 .init           = pci_eg20t_init,
2498                 .setup          = pci_default_setup,
2499         },
2500         {
2501                 .vendor         = PCI_VENDOR_ID_INTEL,
2502                 .device         = 0x8813,
2503                 .subvendor      = PCI_ANY_ID,
2504                 .subdevice      = PCI_ANY_ID,
2505                 .init           = pci_eg20t_init,
2506                 .setup          = pci_default_setup,
2507         },
2508         {
2509                 .vendor         = PCI_VENDOR_ID_INTEL,
2510                 .device         = 0x8814,
2511                 .subvendor      = PCI_ANY_ID,
2512                 .subdevice      = PCI_ANY_ID,
2513                 .init           = pci_eg20t_init,
2514                 .setup          = pci_default_setup,
2515         },
2516         {
2517                 .vendor         = 0x10DB,
2518                 .device         = 0x8027,
2519                 .subvendor      = PCI_ANY_ID,
2520                 .subdevice      = PCI_ANY_ID,
2521                 .init           = pci_eg20t_init,
2522                 .setup          = pci_default_setup,
2523         },
2524         {
2525                 .vendor         = 0x10DB,
2526                 .device         = 0x8028,
2527                 .subvendor      = PCI_ANY_ID,
2528                 .subdevice      = PCI_ANY_ID,
2529                 .init           = pci_eg20t_init,
2530                 .setup          = pci_default_setup,
2531         },
2532         {
2533                 .vendor         = 0x10DB,
2534                 .device         = 0x8029,
2535                 .subvendor      = PCI_ANY_ID,
2536                 .subdevice      = PCI_ANY_ID,
2537                 .init           = pci_eg20t_init,
2538                 .setup          = pci_default_setup,
2539         },
2540         {
2541                 .vendor         = 0x10DB,
2542                 .device         = 0x800C,
2543                 .subvendor      = PCI_ANY_ID,
2544                 .subdevice      = PCI_ANY_ID,
2545                 .init           = pci_eg20t_init,
2546                 .setup          = pci_default_setup,
2547         },
2548         {
2549                 .vendor         = 0x10DB,
2550                 .device         = 0x800D,
2551                 .subvendor      = PCI_ANY_ID,
2552                 .subdevice      = PCI_ANY_ID,
2553                 .init           = pci_eg20t_init,
2554                 .setup          = pci_default_setup,
2555         },
2556         /*
2557          * Cronyx Omega PCI (PLX-chip based)
2558          */
2559         {
2560                 .vendor         = PCI_VENDOR_ID_PLX,
2561                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2562                 .subvendor      = PCI_ANY_ID,
2563                 .subdevice      = PCI_ANY_ID,
2564                 .setup          = pci_omegapci_setup,
2565         },
2566         /* WCH CH353 1S1P card (16550 clone) */
2567         {
2568                 .vendor         = PCI_VENDOR_ID_WCH,
2569                 .device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2570                 .subvendor      = PCI_ANY_ID,
2571                 .subdevice      = PCI_ANY_ID,
2572                 .setup          = pci_wch_ch353_setup,
2573         },
2574         /* WCH CH353 2S1P card (16550 clone) */
2575         {
2576                 .vendor         = PCI_VENDOR_ID_WCH,
2577                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2578                 .subvendor      = PCI_ANY_ID,
2579                 .subdevice      = PCI_ANY_ID,
2580                 .setup          = pci_wch_ch353_setup,
2581         },
2582         /* WCH CH353 4S card (16550 clone) */
2583         {
2584                 .vendor         = PCI_VENDOR_ID_WCH,
2585                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2586                 .subvendor      = PCI_ANY_ID,
2587                 .subdevice      = PCI_ANY_ID,
2588                 .setup          = pci_wch_ch353_setup,
2589         },
2590         /* WCH CH353 2S1PF card (16550 clone) */
2591         {
2592                 .vendor         = PCI_VENDOR_ID_WCH,
2593                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2594                 .subvendor      = PCI_ANY_ID,
2595                 .subdevice      = PCI_ANY_ID,
2596                 .setup          = pci_wch_ch353_setup,
2597         },
2598         /* WCH CH352 2S card (16550 clone) */
2599         {
2600                 .vendor         = PCI_VENDOR_ID_WCH,
2601                 .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2602                 .subvendor      = PCI_ANY_ID,
2603                 .subdevice      = PCI_ANY_ID,
2604                 .setup          = pci_wch_ch353_setup,
2605         },
2606         /* WCH CH382 2S card (16850 clone) */
2607         {
2608                 .vendor         = PCIE_VENDOR_ID_WCH,
2609                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S,
2610                 .subvendor      = PCI_ANY_ID,
2611                 .subdevice      = PCI_ANY_ID,
2612                 .setup          = pci_wch_ch38x_setup,
2613         },
2614         /* WCH CH382 2S1P card (16850 clone) */
2615         {
2616                 .vendor         = PCIE_VENDOR_ID_WCH,
2617                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2618                 .subvendor      = PCI_ANY_ID,
2619                 .subdevice      = PCI_ANY_ID,
2620                 .setup          = pci_wch_ch38x_setup,
2621         },
2622         /* WCH CH384 4S card (16850 clone) */
2623         {
2624                 .vendor         = PCIE_VENDOR_ID_WCH,
2625                 .device         = PCIE_DEVICE_ID_WCH_CH384_4S,
2626                 .subvendor      = PCI_ANY_ID,
2627                 .subdevice      = PCI_ANY_ID,
2628                 .setup          = pci_wch_ch38x_setup,
2629         },
2630         /*
2631          * ASIX devices with FIFO bug
2632          */
2633         {
2634                 .vendor         = PCI_VENDOR_ID_ASIX,
2635                 .device         = PCI_ANY_ID,
2636                 .subvendor      = PCI_ANY_ID,
2637                 .subdevice      = PCI_ANY_ID,
2638                 .setup          = pci_asix_setup,
2639         },
2640         /*
2641          * Commtech, Inc. Fastcom adapters
2642          *
2643          */
2644         {
2645                 .vendor = PCI_VENDOR_ID_COMMTECH,
2646                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2647                 .subvendor      = PCI_ANY_ID,
2648                 .subdevice      = PCI_ANY_ID,
2649                 .setup          = pci_fastcom335_setup,
2650         },
2651         {
2652                 .vendor = PCI_VENDOR_ID_COMMTECH,
2653                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2654                 .subvendor      = PCI_ANY_ID,
2655                 .subdevice      = PCI_ANY_ID,
2656                 .setup          = pci_fastcom335_setup,
2657         },
2658         {
2659                 .vendor = PCI_VENDOR_ID_COMMTECH,
2660                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2661                 .subvendor      = PCI_ANY_ID,
2662                 .subdevice      = PCI_ANY_ID,
2663                 .setup          = pci_fastcom335_setup,
2664         },
2665         {
2666                 .vendor = PCI_VENDOR_ID_COMMTECH,
2667                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2668                 .subvendor      = PCI_ANY_ID,
2669                 .subdevice      = PCI_ANY_ID,
2670                 .setup          = pci_fastcom335_setup,
2671         },
2672         {
2673                 .vendor = PCI_VENDOR_ID_COMMTECH,
2674                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2675                 .subvendor      = PCI_ANY_ID,
2676                 .subdevice      = PCI_ANY_ID,
2677                 .setup          = pci_xr17v35x_setup,
2678         },
2679         {
2680                 .vendor = PCI_VENDOR_ID_COMMTECH,
2681                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2682                 .subvendor      = PCI_ANY_ID,
2683                 .subdevice      = PCI_ANY_ID,
2684                 .setup          = pci_xr17v35x_setup,
2685         },
2686         {
2687                 .vendor = PCI_VENDOR_ID_COMMTECH,
2688                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2689                 .subvendor      = PCI_ANY_ID,
2690                 .subdevice      = PCI_ANY_ID,
2691                 .setup          = pci_xr17v35x_setup,
2692         },
2693         /*
2694          * Broadcom TruManage (NetXtreme)
2695          */
2696         {
2697                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2698                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2699                 .subvendor      = PCI_ANY_ID,
2700                 .subdevice      = PCI_ANY_ID,
2701                 .setup          = pci_brcm_trumanage_setup,
2702         },
2703         {
2704                 .vendor         = 0x1c29,
2705                 .device         = 0x1104,
2706                 .subvendor      = PCI_ANY_ID,
2707                 .subdevice      = PCI_ANY_ID,
2708                 .setup          = pci_fintek_setup,
2709                 .init           = pci_fintek_init,
2710         },
2711         {
2712                 .vendor         = 0x1c29,
2713                 .device         = 0x1108,
2714                 .subvendor      = PCI_ANY_ID,
2715                 .subdevice      = PCI_ANY_ID,
2716                 .setup          = pci_fintek_setup,
2717                 .init           = pci_fintek_init,
2718         },
2719         {
2720                 .vendor         = 0x1c29,
2721                 .device         = 0x1112,
2722                 .subvendor      = PCI_ANY_ID,
2723                 .subdevice      = PCI_ANY_ID,
2724                 .setup          = pci_fintek_setup,
2725                 .init           = pci_fintek_init,
2726         },
2727 
2728         /*
2729          * Default "match everything" terminator entry
2730          */
2731         {
2732                 .vendor         = PCI_ANY_ID,
2733                 .device         = PCI_ANY_ID,
2734                 .subvendor      = PCI_ANY_ID,
2735                 .subdevice      = PCI_ANY_ID,
2736                 .setup          = pci_default_setup,
2737         }
2738 };
2739 
2740 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2741 {
2742         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2743 }
2744 
2745 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2746 {
2747         struct pci_serial_quirk *quirk;
2748 
2749         for (quirk = pci_serial_quirks; ; quirk++)
2750                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2751                     quirk_id_matches(quirk->device, dev->device) &&
2752                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2753                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2754                         break;
2755         return quirk;
2756 }
2757 
2758 static inline int get_pci_irq(struct pci_dev *dev,
2759                                 const struct pciserial_board *board)
2760 {
2761         if (board->flags & FL_NOIRQ)
2762                 return 0;
2763         else
2764                 return dev->irq;
2765 }
2766 
2767 /*
2768  * This is the configuration table for all of the PCI serial boards
2769  * which we support.  It is directly indexed by the pci_board_num_t enum
2770  * value, which is encoded in the pci_device_id PCI probe table's
2771  * driver_data member.
2772  *
2773  * The makeup of these names are:
2774  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2775  *
2776  *  bn          = PCI BAR number
2777  *  bt          = Index using PCI BARs
2778  *  n           = number of serial ports
2779  *  baud        = baud rate
2780  *  offsetinhex = offset for each sequential port (in hex)
2781  *
2782  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2783  *
2784  * Please note: in theory if n = 1, _bt infix should make no difference.
2785  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2786  */
2787 enum pci_board_num_t {
2788         pbn_default = 0,
2789 
2790         pbn_b0_1_115200,
2791         pbn_b0_2_115200,
2792         pbn_b0_4_115200,
2793         pbn_b0_5_115200,
2794         pbn_b0_8_115200,
2795 
2796         pbn_b0_1_921600,
2797         pbn_b0_2_921600,
2798         pbn_b0_4_921600,
2799 
2800         pbn_b0_2_1130000,
2801 
2802         pbn_b0_4_1152000,
2803 
2804         pbn_b0_2_1152000_200,
2805         pbn_b0_4_1152000_200,
2806         pbn_b0_8_1152000_200,
2807 
2808         pbn_b0_2_1843200,
2809         pbn_b0_4_1843200,
2810 
2811         pbn_b0_2_1843200_200,
2812         pbn_b0_4_1843200_200,
2813         pbn_b0_8_1843200_200,
2814 
2815         pbn_b0_1_4000000,
2816 
2817         pbn_b0_bt_1_115200,
2818         pbn_b0_bt_2_115200,
2819         pbn_b0_bt_4_115200,
2820         pbn_b0_bt_8_115200,
2821 
2822         pbn_b0_bt_1_460800,
2823         pbn_b0_bt_2_460800,
2824         pbn_b0_bt_4_460800,
2825 
2826         pbn_b0_bt_1_921600,
2827         pbn_b0_bt_2_921600,
2828         pbn_b0_bt_4_921600,
2829         pbn_b0_bt_8_921600,
2830 
2831         pbn_b1_1_115200,
2832         pbn_b1_2_115200,
2833         pbn_b1_4_115200,
2834         pbn_b1_8_115200,
2835         pbn_b1_16_115200,
2836 
2837         pbn_b1_1_921600,
2838         pbn_b1_2_921600,
2839         pbn_b1_4_921600,
2840         pbn_b1_8_921600,
2841 
2842         pbn_b1_2_1250000,
2843 
2844         pbn_b1_bt_1_115200,
2845         pbn_b1_bt_2_115200,
2846         pbn_b1_bt_4_115200,
2847 
2848         pbn_b1_bt_2_921600,
2849 
2850         pbn_b1_1_1382400,
2851         pbn_b1_2_1382400,
2852         pbn_b1_4_1382400,
2853         pbn_b1_8_1382400,
2854 
2855         pbn_b2_1_115200,
2856         pbn_b2_2_115200,
2857         pbn_b2_4_115200,
2858         pbn_b2_8_115200,
2859 
2860         pbn_b2_1_460800,
2861         pbn_b2_4_460800,
2862         pbn_b2_8_460800,
2863         pbn_b2_16_460800,
2864 
2865         pbn_b2_1_921600,
2866         pbn_b2_4_921600,
2867         pbn_b2_8_921600,
2868 
2869         pbn_b2_8_1152000,
2870 
2871         pbn_b2_bt_1_115200,
2872         pbn_b2_bt_2_115200,
2873         pbn_b2_bt_4_115200,
2874 
2875         pbn_b2_bt_2_921600,
2876         pbn_b2_bt_4_921600,
2877 
2878         pbn_b3_2_115200,
2879         pbn_b3_4_115200,
2880         pbn_b3_8_115200,
2881 
2882         pbn_b4_bt_2_921600,
2883         pbn_b4_bt_4_921600,
2884         pbn_b4_bt_8_921600,
2885 
2886         /*
2887          * Board-specific versions.
2888          */
2889         pbn_panacom,
2890         pbn_panacom2,
2891         pbn_panacom4,
2892         pbn_plx_romulus,
2893         pbn_endrun_2_4000000,
2894         pbn_oxsemi,
2895         pbn_oxsemi_1_4000000,
2896         pbn_oxsemi_2_4000000,
2897         pbn_oxsemi_4_4000000,
2898         pbn_oxsemi_8_4000000,
2899         pbn_intel_i960,
2900         pbn_sgi_ioc3,
2901         pbn_computone_4,
2902         pbn_computone_6,
2903         pbn_computone_8,
2904         pbn_sbsxrsio,
2905         pbn_exar_XR17C152,
2906         pbn_exar_XR17C154,
2907         pbn_exar_XR17C158,
2908         pbn_exar_XR17V352,
2909         pbn_exar_XR17V354,
2910         pbn_exar_XR17V358,
2911         pbn_exar_XR17V4358,
2912         pbn_exar_XR17V8358,
2913         pbn_exar_ibm_saturn,
2914         pbn_pasemi_1682M,
2915         pbn_ni8430_2,
2916         pbn_ni8430_4,
2917         pbn_ni8430_8,
2918         pbn_ni8430_16,
2919         pbn_ADDIDATA_PCIe_1_3906250,
2920         pbn_ADDIDATA_PCIe_2_3906250,
2921         pbn_ADDIDATA_PCIe_4_3906250,
2922         pbn_ADDIDATA_PCIe_8_3906250,
2923         pbn_ce4100_1_115200,
2924         pbn_byt,
2925         pbn_qrk,
2926         pbn_omegapci,
2927         pbn_NETMOS9900_2s_115200,
2928         pbn_brcm_trumanage,
2929         pbn_fintek_4,
2930         pbn_fintek_8,
2931         pbn_fintek_12,
2932         pbn_wch382_2,
2933         pbn_wch384_4,
2934         pbn_pericom_PI7C9X7951,
2935         pbn_pericom_PI7C9X7952,
2936         pbn_pericom_PI7C9X7954,
2937         pbn_pericom_PI7C9X7958,
2938 };
2939 
2940 /*
2941  * uart_offset - the space between channels
2942  * reg_shift   - describes how the UART registers are mapped
2943  *               to PCI memory by the card.
2944  * For example IER register on SBS, Inc. PMC-OctPro is located at
2945  * offset 0x10 from the UART base, while UART_IER is defined as 1
2946  * in include/linux/serial_reg.h,
2947  * see first lines of serial_in() and serial_out() in 8250.c
2948 */
2949 
2950 static struct pciserial_board pci_boards[] = {
2951         [pbn_default] = {
2952                 .flags          = FL_BASE0,
2953                 .num_ports      = 1,
2954                 .base_baud      = 115200,
2955                 .uart_offset    = 8,
2956         },
2957         [pbn_b0_1_115200] = {
2958                 .flags          = FL_BASE0,
2959                 .num_ports      = 1,
2960                 .base_baud      = 115200,
2961                 .uart_offset    = 8,
2962         },
2963         [pbn_b0_2_115200] = {
2964                 .flags          = FL_BASE0,
2965                 .num_ports      = 2,
2966                 .base_baud      = 115200,
2967                 .uart_offset    = 8,
2968         },
2969         [pbn_b0_4_115200] = {
2970                 .flags          = FL_BASE0,
2971                 .num_ports      = 4,
2972                 .base_baud      = 115200,
2973                 .uart_offset    = 8,
2974         },
2975         [pbn_b0_5_115200] = {
2976                 .flags          = FL_BASE0,
2977                 .num_ports      = 5,
2978                 .base_baud      = 115200,
2979                 .uart_offset    = 8,
2980         },
2981         [pbn_b0_8_115200] = {
2982                 .flags          = FL_BASE0,
2983                 .num_ports      = 8,
2984                 .base_baud      = 115200,
2985                 .uart_offset    = 8,
2986         },
2987         [pbn_b0_1_921600] = {
2988                 .flags          = FL_BASE0,
2989                 .num_ports      = 1,
2990                 .base_baud      = 921600,
2991                 .uart_offset    = 8,
2992         },
2993         [pbn_b0_2_921600] = {
2994                 .flags          = FL_BASE0,
2995                 .num_ports      = 2,
2996                 .base_baud      = 921600,
2997                 .uart_offset    = 8,
2998         },
2999         [pbn_b0_4_921600] = {
3000                 .flags          = FL_BASE0,
3001                 .num_ports      = 4,
3002                 .base_baud      = 921600,
3003                 .uart_offset    = 8,
3004         },
3005 
3006         [pbn_b0_2_1130000] = {
3007                 .flags          = FL_BASE0,
3008                 .num_ports      = 2,
3009                 .base_baud      = 1130000,
3010                 .uart_offset    = 8,
3011         },
3012 
3013         [pbn_b0_4_1152000] = {
3014                 .flags          = FL_BASE0,
3015                 .num_ports      = 4,
3016                 .base_baud      = 1152000,
3017                 .uart_offset    = 8,
3018         },
3019 
3020         [pbn_b0_2_1152000_200] = {
3021                 .flags          = FL_BASE0,
3022                 .num_ports      = 2,
3023                 .base_baud      = 1152000,
3024                 .uart_offset    = 0x200,
3025         },
3026 
3027         [pbn_b0_4_1152000_200] = {
3028                 .flags          = FL_BASE0,
3029                 .num_ports      = 4,
3030                 .base_baud      = 1152000,
3031                 .uart_offset    = 0x200,
3032         },
3033 
3034         [pbn_b0_8_1152000_200] = {
3035                 .flags          = FL_BASE0,
3036                 .num_ports      = 8,
3037                 .base_baud      = 1152000,
3038                 .uart_offset    = 0x200,
3039         },
3040 
3041         [pbn_b0_2_1843200] = {
3042                 .flags          = FL_BASE0,
3043                 .num_ports      = 2,
3044                 .base_baud      = 1843200,
3045                 .uart_offset    = 8,
3046         },
3047         [pbn_b0_4_1843200] = {
3048                 .flags          = FL_BASE0,
3049                 .num_ports      = 4,
3050                 .base_baud      = 1843200,
3051                 .uart_offset    = 8,
3052         },
3053 
3054         [pbn_b0_2_1843200_200] = {
3055                 .flags          = FL_BASE0,
3056                 .num_ports      = 2,
3057                 .base_baud      = 1843200,
3058                 .uart_offset    = 0x200,
3059         },
3060         [pbn_b0_4_1843200_200] = {
3061                 .flags          = FL_BASE0,
3062                 .num_ports      = 4,
3063                 .base_baud      = 1843200,
3064                 .uart_offset    = 0x200,
3065         },
3066         [pbn_b0_8_1843200_200] = {
3067                 .flags          = FL_BASE0,
3068                 .num_ports      = 8,
3069                 .base_baud      = 1843200,
3070                 .uart_offset    = 0x200,
3071         },
3072         [pbn_b0_1_4000000] = {
3073                 .flags          = FL_BASE0,
3074                 .num_ports      = 1,
3075                 .base_baud      = 4000000,
3076                 .uart_offset    = 8,
3077         },
3078 
3079         [pbn_b0_bt_1_115200] = {
3080                 .flags          = FL_BASE0|FL_BASE_BARS,
3081                 .num_ports      = 1,
3082                 .base_baud      = 115200,
3083                 .uart_offset    = 8,
3084         },
3085         [pbn_b0_bt_2_115200] = {
3086                 .flags          = FL_BASE0|FL_BASE_BARS,
3087                 .num_ports      = 2,
3088                 .base_baud      = 115200,
3089                 .uart_offset    = 8,
3090         },
3091         [pbn_b0_bt_4_115200] = {
3092                 .flags          = FL_BASE0|FL_BASE_BARS,
3093                 .num_ports      = 4,
3094                 .base_baud      = 115200,
3095                 .uart_offset    = 8,
3096         },
3097         [pbn_b0_bt_8_115200] = {
3098                 .flags          = FL_BASE0|FL_BASE_BARS,
3099                 .num_ports      = 8,
3100                 .base_baud      = 115200,
3101                 .uart_offset    = 8,
3102         },
3103 
3104         [pbn_b0_bt_1_460800] = {
3105                 .flags          = FL_BASE0|FL_BASE_BARS,
3106                 .num_ports      = 1,
3107                 .base_baud      = 460800,
3108                 .uart_offset    = 8,
3109         },
3110         [pbn_b0_bt_2_460800] = {
3111                 .flags          = FL_BASE0|FL_BASE_BARS,
3112                 .num_ports      = 2,
3113                 .base_baud      = 460800,
3114                 .uart_offset    = 8,
3115         },
3116         [pbn_b0_bt_4_460800] = {
3117                 .flags          = FL_BASE0|FL_BASE_BARS,
3118                 .num_ports      = 4,
3119                 .base_baud      = 460800,
3120                 .uart_offset    = 8,
3121         },
3122 
3123         [pbn_b0_bt_1_921600] = {
3124                 .flags          = FL_BASE0|FL_BASE_BARS,
3125                 .num_ports      = 1,
3126                 .base_baud      = 921600,
3127                 .uart_offset    = 8,
3128         },
3129         [pbn_b0_bt_2_921600] = {
3130                 .flags          = FL_BASE0|FL_BASE_BARS,
3131                 .num_ports      = 2,
3132                 .base_baud      = 921600,
3133                 .uart_offset    = 8,
3134         },
3135         [pbn_b0_bt_4_921600] = {
3136                 .flags          = FL_BASE0|FL_BASE_BARS,
3137                 .num_ports      = 4,
3138                 .base_baud      = 921600,
3139                 .uart_offset    = 8,
3140         },
3141         [pbn_b0_bt_8_921600] = {
3142                 .flags          = FL_BASE0|FL_BASE_BARS,
3143                 .num_ports      = 8,
3144                 .base_baud      = 921600,
3145                 .uart_offset    = 8,
3146         },
3147 
3148         [pbn_b1_1_115200] = {
3149                 .flags          = FL_BASE1,
3150                 .num_ports      = 1,
3151                 .base_baud      = 115200,
3152                 .uart_offset    = 8,
3153         },
3154         [pbn_b1_2_115200] = {
3155                 .flags          = FL_BASE1,
3156                 .num_ports      = 2,
3157                 .base_baud      = 115200,
3158                 .uart_offset    = 8,
3159         },
3160         [pbn_b1_4_115200] = {
3161                 .flags          = FL_BASE1,
3162                 .num_ports      = 4,
3163                 .base_baud      = 115200,
3164                 .uart_offset    = 8,
3165         },
3166         [pbn_b1_8_115200] = {
3167                 .flags          = FL_BASE1,
3168                 .num_ports      = 8,
3169                 .base_baud      = 115200,
3170                 .uart_offset    = 8,
3171         },
3172         [pbn_b1_16_115200] = {
3173                 .flags          = FL_BASE1,
3174                 .num_ports      = 16,
3175                 .base_baud      = 115200,
3176                 .uart_offset    = 8,
3177         },
3178 
3179         [pbn_b1_1_921600] = {
3180                 .flags          = FL_BASE1,
3181                 .num_ports      = 1,
3182                 .base_baud      = 921600,
3183                 .uart_offset    = 8,
3184         },
3185         [pbn_b1_2_921600] = {
3186                 .flags          = FL_BASE1,
3187                 .num_ports      = 2,
3188                 .base_baud      = 921600,
3189                 .uart_offset    = 8,
3190         },
3191         [pbn_b1_4_921600] = {
3192                 .flags          = FL_BASE1,
3193                 .num_ports      = 4,
3194                 .base_baud      = 921600,
3195                 .uart_offset    = 8,
3196         },
3197         [pbn_b1_8_921600] = {
3198                 .flags          = FL_BASE1,
3199                 .num_ports      = 8,
3200                 .base_baud      = 921600,
3201                 .uart_offset    = 8,
3202         },
3203         [pbn_b1_2_1250000] = {
3204                 .flags          = FL_BASE1,
3205                 .num_ports      = 2,
3206                 .base_baud      = 1250000,
3207                 .uart_offset    = 8,
3208         },
3209 
3210         [pbn_b1_bt_1_115200] = {
3211                 .flags          = FL_BASE1|FL_BASE_BARS,
3212                 .num_ports      = 1,
3213                 .base_baud      = 115200,
3214                 .uart_offset    = 8,
3215         },
3216         [pbn_b1_bt_2_115200] = {
3217                 .flags          = FL_BASE1|FL_BASE_BARS,
3218                 .num_ports      = 2,
3219                 .base_baud      = 115200,
3220                 .uart_offset    = 8,
3221         },
3222         [pbn_b1_bt_4_115200] = {
3223                 .flags          = FL_BASE1|FL_BASE_BARS,
3224                 .num_ports      = 4,
3225                 .base_baud      = 115200,
3226                 .uart_offset    = 8,
3227         },
3228 
3229         [pbn_b1_bt_2_921600] = {
3230                 .flags          = FL_BASE1|FL_BASE_BARS,
3231                 .num_ports      = 2,
3232                 .base_baud      = 921600,
3233                 .uart_offset    = 8,
3234         },
3235 
3236         [pbn_b1_1_1382400] = {
3237                 .flags          = FL_BASE1,
3238                 .num_ports      = 1,
3239                 .base_baud      = 1382400,
3240                 .uart_offset    = 8,
3241         },
3242         [pbn_b1_2_1382400] = {
3243                 .flags          = FL_BASE1,
3244                 .num_ports      = 2,
3245                 .base_baud      = 1382400,
3246                 .uart_offset    = 8,
3247         },
3248         [pbn_b1_4_1382400] = {
3249                 .flags          = FL_BASE1,
3250                 .num_ports      = 4,
3251                 .base_baud      = 1382400,
3252                 .uart_offset    = 8,
3253         },
3254         [pbn_b1_8_1382400] = {
3255                 .flags          = FL_BASE1,
3256                 .num_ports      = 8,
3257                 .base_baud      = 1382400,
3258                 .uart_offset    = 8,
3259         },
3260 
3261         [pbn_b2_1_115200] = {
3262                 .flags          = FL_BASE2,
3263                 .num_ports      = 1,
3264                 .base_baud      = 115200,
3265                 .uart_offset    = 8,
3266         },
3267         [pbn_b2_2_115200] = {
3268                 .flags          = FL_BASE2,
3269                 .num_ports      = 2,
3270                 .base_baud      = 115200,
3271                 .uart_offset    = 8,
3272         },
3273         [pbn_b2_4_115200] = {
3274                 .flags          = FL_BASE2,
3275                 .num_ports      = 4,
3276                 .base_baud      = 115200,
3277                 .uart_offset    = 8,
3278         },
3279         [pbn_b2_8_115200] = {
3280                 .flags          = FL_BASE2,
3281                 .num_ports      = 8,
3282                 .base_baud      = 115200,
3283                 .uart_offset    = 8,
3284         },
3285 
3286         [pbn_b2_1_460800] = {
3287                 .flags          = FL_BASE2,
3288                 .num_ports      = 1,
3289                 .base_baud      = 460800,
3290                 .uart_offset    = 8,
3291         },
3292         [pbn_b2_4_460800] = {
3293                 .flags          = FL_BASE2,
3294                 .num_ports      = 4,
3295                 .base_baud      = 460800,
3296                 .uart_offset    = 8,
3297         },
3298         [pbn_b2_8_460800] = {
3299                 .flags          = FL_BASE2,
3300                 .num_ports      = 8,
3301                 .base_baud      = 460800,
3302                 .uart_offset    = 8,
3303         },
3304         [pbn_b2_16_460800] = {
3305                 .flags          = FL_BASE2,
3306                 .num_ports      = 16,
3307                 .base_baud      = 460800,
3308                 .uart_offset    = 8,
3309          },
3310 
3311         [pbn_b2_1_921600] = {
3312                 .flags          = FL_BASE2,
3313                 .num_ports      = 1,
3314                 .base_baud      = 921600,
3315                 .uart_offset    = 8,
3316         },
3317         [pbn_b2_4_921600] = {
3318                 .flags          = FL_BASE2,
3319                 .num_ports      = 4,
3320                 .base_baud      = 921600,
3321                 .uart_offset    = 8,
3322         },
3323         [pbn_b2_8_921600] = {
3324                 .flags          = FL_BASE2,
3325                 .num_ports      = 8,
3326                 .base_baud      = 921600,
3327                 .uart_offset    = 8,
3328         },
3329 
3330         [pbn_b2_8_1152000] = {
3331                 .flags          = FL_BASE2,
3332                 .num_ports      = 8,
3333                 .base_baud      = 1152000,
3334                 .uart_offset    = 8,
3335         },
3336 
3337         [pbn_b2_bt_1_115200] = {
3338                 .flags          = FL_BASE2|FL_BASE_BARS,
3339                 .num_ports      = 1,
3340                 .base_baud      = 115200,
3341                 .uart_offset    = 8,
3342         },
3343         [pbn_b2_bt_2_115200] = {
3344                 .flags          = FL_BASE2|FL_BASE_BARS,
3345                 .num_ports      = 2,
3346                 .base_baud      = 115200,
3347                 .uart_offset    = 8,
3348         },
3349         [pbn_b2_bt_4_115200] = {
3350                 .flags          = FL_BASE2|FL_BASE_BARS,
3351                 .num_ports      = 4,
3352                 .base_baud      = 115200,
3353                 .uart_offset    = 8,
3354         },
3355 
3356         [pbn_b2_bt_2_921600] = {
3357                 .flags          = FL_BASE2|FL_BASE_BARS,
3358                 .num_ports      = 2,
3359                 .base_baud      = 921600,
3360                 .uart_offset    = 8,
3361         },
3362         [pbn_b2_bt_4_921600] = {
3363                 .flags          = FL_BASE2|FL_BASE_BARS,
3364                 .num_ports      = 4,
3365                 .base_baud      = 921600,
3366                 .uart_offset    = 8,
3367         },
3368 
3369         [pbn_b3_2_115200] = {
3370                 .flags          = FL_BASE3,
3371                 .num_ports      = 2,
3372                 .base_baud      = 115200,
3373                 .uart_offset    = 8,
3374         },
3375         [pbn_b3_4_115200] = {
3376                 .flags          = FL_BASE3,
3377                 .num_ports      = 4,
3378                 .base_baud      = 115200,
3379                 .uart_offset    = 8,
3380         },
3381         [pbn_b3_8_115200] = {
3382                 .flags          = FL_BASE3,
3383                 .num_ports      = 8,
3384                 .base_baud      = 115200,
3385                 .uart_offset    = 8,
3386         },
3387 
3388         [pbn_b4_bt_2_921600] = {
3389                 .flags          = FL_BASE4,
3390                 .num_ports      = 2,
3391                 .base_baud      = 921600,
3392                 .uart_offset    = 8,
3393         },
3394         [pbn_b4_bt_4_921600] = {
3395                 .flags          = FL_BASE4,
3396                 .num_ports      = 4,
3397                 .base_baud      = 921600,
3398                 .uart_offset    = 8,
3399         },
3400         [pbn_b4_bt_8_921600] = {
3401                 .flags          = FL_BASE4,
3402                 .num_ports      = 8,
3403                 .base_baud      = 921600,
3404                 .uart_offset    = 8,
3405         },
3406 
3407         /*
3408          * Entries following this are board-specific.
3409          */
3410 
3411         /*
3412          * Panacom - IOMEM
3413          */
3414         [pbn_panacom] = {
3415                 .flags          = FL_BASE2,
3416                 .num_ports      = 2,
3417                 .base_baud      = 921600,
3418                 .uart_offset    = 0x400,
3419                 .reg_shift      = 7,
3420         },
3421         [pbn_panacom2] = {
3422                 .flags          = FL_BASE2|FL_BASE_BARS,
3423                 .num_ports      = 2,
3424                 .base_baud      = 921600,
3425                 .uart_offset    = 0x400,
3426                 .reg_shift      = 7,
3427         },
3428         [pbn_panacom4] = {
3429                 .flags          = FL_BASE2|FL_BASE_BARS,
3430                 .num_ports      = 4,
3431                 .base_baud      = 921600,
3432                 .uart_offset    = 0x400,
3433                 .reg_shift      = 7,
3434         },
3435 
3436         /* I think this entry is broken - the first_offset looks wrong --rmk */
3437         [pbn_plx_romulus] = {
3438                 .flags          = FL_BASE2,
3439                 .num_ports      = 4,
3440                 .base_baud      = 921600,
3441                 .uart_offset    = 8 << 2,
3442                 .reg_shift      = 2,
3443                 .first_offset   = 0x03,
3444         },
3445 
3446         /*
3447          * EndRun Technologies
3448         * Uses the size of PCI Base region 0 to
3449         * signal now many ports are available
3450         * 2 port 952 Uart support
3451         */
3452         [pbn_endrun_2_4000000] = {
3453                 .flags          = FL_BASE0,
3454                 .num_ports      = 2,
3455                 .base_baud      = 4000000,
3456                 .uart_offset    = 0x200,
3457                 .first_offset   = 0x1000,
3458         },
3459 
3460         /*
3461          * This board uses the size of PCI Base region 0 to
3462          * signal now many ports are available
3463          */
3464         [pbn_oxsemi] = {
3465                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3466                 .num_ports      = 32,
3467                 .base_baud      = 115200,
3468                 .uart_offset    = 8,
3469         },
3470         [pbn_oxsemi_1_4000000] = {
3471                 .flags          = FL_BASE0,
3472                 .num_ports      = 1,
3473                 .base_baud      = 4000000,
3474                 .uart_offset    = 0x200,
3475                 .first_offset   = 0x1000,
3476         },
3477         [pbn_oxsemi_2_4000000] = {
3478                 .flags          = FL_BASE0,
3479                 .num_ports      = 2,
3480                 .base_baud      = 4000000,
3481                 .uart_offset    = 0x200,
3482                 .first_offset   = 0x1000,
3483         },
3484         [pbn_oxsemi_4_4000000] = {
3485                 .flags          = FL_BASE0,
3486                 .num_ports      = 4,
3487                 .base_baud      = 4000000,
3488                 .uart_offset    = 0x200,
3489                 .first_offset   = 0x1000,
3490         },
3491         [pbn_oxsemi_8_4000000] = {
3492                 .flags          = FL_BASE0,
3493                 .num_ports      = 8,
3494                 .base_baud      = 4000000,
3495                 .uart_offset    = 0x200,
3496                 .first_offset   = 0x1000,
3497         },
3498 
3499 
3500         /*
3501          * EKF addition for i960 Boards form EKF with serial port.
3502          * Max 256 ports.
3503          */
3504         [pbn_intel_i960] = {
3505                 .flags          = FL_BASE0,
3506                 .num_ports      = 32,
3507                 .base_baud      = 921600,
3508                 .uart_offset    = 8 << 2,
3509                 .reg_shift      = 2,
3510                 .first_offset   = 0x10000,
3511         },
3512         [pbn_sgi_ioc3] = {
3513                 .flags          = FL_BASE0|FL_NOIRQ,
3514                 .num_ports      = 1,
3515                 .base_baud      = 458333,
3516                 .uart_offset    = 8,
3517                 .reg_shift      = 0,
3518                 .first_offset   = 0x20178,
3519         },
3520 
3521         /*
3522          * Computone - uses IOMEM.
3523          */
3524         [pbn_computone_4] = {
3525                 .flags          = FL_BASE0,
3526                 .num_ports      = 4,
3527                 .base_baud      = 921600,
3528                 .uart_offset    = 0x40,
3529                 .reg_shift      = 2,
3530                 .first_offset   = 0x200,
3531         },
3532         [pbn_computone_6] = {
3533                 .flags          = FL_BASE0,
3534                 .num_ports      = 6,
3535                 .base_baud      = 921600,
3536                 .uart_offset    = 0x40,
3537                 .reg_shift      = 2,
3538                 .first_offset   = 0x200,
3539         },
3540         [pbn_computone_8] = {
3541                 .flags          = FL_BASE0,
3542                 .num_ports      = 8,
3543                 .base_baud      = 921600,
3544                 .uart_offset    = 0x40,
3545                 .reg_shift      = 2,
3546                 .first_offset   = 0x200,
3547         },
3548         [pbn_sbsxrsio] = {
3549                 .flags          = FL_BASE0,
3550                 .num_ports      = 8,
3551                 .base_baud      = 460800,
3552                 .uart_offset    = 256,
3553                 .reg_shift      = 4,
3554         },
3555         /*
3556          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3557          *  Only basic 16550A support.
3558          *  XR17C15[24] are not tested, but they should work.
3559          */
3560         [pbn_exar_XR17C152] = {
3561                 .flags          = FL_BASE0,
3562                 .num_ports      = 2,
3563                 .base_baud      = 921600,
3564                 .uart_offset    = 0x200,
3565         },
3566         [pbn_exar_XR17C154] = {
3567                 .flags          = FL_BASE0,
3568                 .num_ports      = 4,
3569                 .base_baud      = 921600,
3570                 .uart_offset    = 0x200,
3571         },
3572         [pbn_exar_XR17C158] = {
3573                 .flags          = FL_BASE0,
3574                 .num_ports      = 8,
3575                 .base_baud      = 921600,
3576                 .uart_offset    = 0x200,
3577         },
3578         [pbn_exar_XR17V352] = {
3579                 .flags          = FL_BASE0,
3580                 .num_ports      = 2,
3581                 .base_baud      = 7812500,
3582                 .uart_offset    = 0x400,
3583                 .reg_shift      = 0,
3584                 .first_offset   = 0,
3585         },
3586         [pbn_exar_XR17V354] = {
3587                 .flags          = FL_BASE0,
3588                 .num_ports      = 4,
3589                 .base_baud      = 7812500,
3590                 .uart_offset    = 0x400,
3591                 .reg_shift      = 0,
3592                 .first_offset   = 0,
3593         },
3594         [pbn_exar_XR17V358] = {
3595                 .flags          = FL_BASE0,
3596                 .num_ports      = 8,
3597                 .base_baud      = 7812500,
3598                 .uart_offset    = 0x400,
3599                 .reg_shift      = 0,
3600                 .first_offset   = 0,
3601         },
3602         [pbn_exar_XR17V4358] = {
3603                 .flags          = FL_BASE0,
3604                 .num_ports      = 12,
3605                 .base_baud      = 7812500,
3606                 .uart_offset    = 0x400,
3607                 .reg_shift      = 0,
3608                 .first_offset   = 0,
3609         },
3610         [pbn_exar_XR17V8358] = {
3611                 .flags          = FL_BASE0,
3612                 .num_ports      = 16,
3613                 .base_baud      = 7812500,
3614                 .uart_offset    = 0x400,
3615                 .reg_shift      = 0,
3616                 .first_offset   = 0,
3617         },
3618         [pbn_exar_ibm_saturn] = {
3619                 .flags          = FL_BASE0,
3620                 .num_ports      = 1,
3621                 .base_baud      = 921600,
3622                 .uart_offset    = 0x200,
3623         },
3624 
3625         /*
3626          * PA Semi PWRficient PA6T-1682M on-chip UART
3627          */
3628         [pbn_pasemi_1682M] = {
3629                 .flags          = FL_BASE0,
3630                 .num_ports      = 1,
3631                 .base_baud      = 8333333,
3632         },
3633         /*
3634          * National Instruments 843x
3635          */
3636         [pbn_ni8430_16] = {
3637                 .flags          = FL_BASE0,
3638                 .num_ports      = 16,
3639                 .base_baud      = 3686400,
3640                 .uart_offset    = 0x10,
3641                 .first_offset   = 0x800,
3642         },
3643         [pbn_ni8430_8] = {
3644                 .flags          = FL_BASE0,
3645                 .num_ports      = 8,
3646                 .base_baud      = 3686400,
3647                 .uart_offset    = 0x10,
3648                 .first_offset   = 0x800,
3649         },
3650         [pbn_ni8430_4] = {
3651                 .flags          = FL_BASE0,
3652                 .num_ports      = 4,
3653                 .base_baud      = 3686400,
3654                 .uart_offset    = 0x10,
3655                 .first_offset   = 0x800,
3656         },
3657         [pbn_ni8430_2] = {
3658                 .flags          = FL_BASE0,
3659                 .num_ports      = 2,
3660                 .base_baud      = 3686400,
3661                 .uart_offset    = 0x10,
3662                 .first_offset   = 0x800,
3663         },
3664         /*
3665          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3666          */
3667         [pbn_ADDIDATA_PCIe_1_3906250] = {
3668                 .flags          = FL_BASE0,
3669                 .num_ports      = 1,
3670                 .base_baud      = 3906250,
3671                 .uart_offset    = 0x200,
3672                 .first_offset   = 0x1000,
3673         },
3674         [pbn_ADDIDATA_PCIe_2_3906250] = {
3675                 .flags          = FL_BASE0,
3676                 .num_ports      = 2,
3677                 .base_baud      = 3906250,
3678                 .uart_offset    = 0x200,
3679                 .first_offset   = 0x1000,
3680         },
3681         [pbn_ADDIDATA_PCIe_4_3906250] = {
3682                 .flags          = FL_BASE0,
3683                 .num_ports      = 4,
3684                 .base_baud      = 3906250,
3685                 .uart_offset    = 0x200,
3686                 .first_offset   = 0x1000,
3687         },
3688         [pbn_ADDIDATA_PCIe_8_3906250] = {
3689                 .flags          = FL_BASE0,
3690                 .num_ports      = 8,
3691                 .base_baud      = 3906250,
3692                 .uart_offset    = 0x200,
3693                 .first_offset   = 0x1000,
3694         },
3695         [pbn_ce4100_1_115200] = {
3696                 .flags          = FL_BASE_BARS,
3697                 .num_ports      = 2,
3698                 .base_baud      = 921600,
3699                 .reg_shift      = 2,
3700         },
3701         [pbn_byt] = {
3702                 .flags          = FL_BASE0,
3703                 .num_ports      = 1,
3704                 .base_baud      = 2764800,
3705                 .reg_shift      = 2,
3706         },
3707         [pbn_qrk] = {
3708                 .flags          = FL_BASE0,
3709                 .num_ports      = 1,
3710                 .base_baud      = 2764800,
3711                 .reg_shift      = 2,
3712         },
3713         [pbn_omegapci] = {
3714                 .flags          = FL_BASE0,
3715                 .num_ports      = 8,
3716                 .base_baud      = 115200,
3717                 .uart_offset    = 0x200,
3718         },
3719         [pbn_NETMOS9900_2s_115200] = {
3720                 .flags          = FL_BASE0,
3721                 .num_ports      = 2,
3722                 .base_baud      = 115200,
3723         },
3724         [pbn_brcm_trumanage] = {
3725                 .flags          = FL_BASE0,
3726                 .num_ports      = 1,
3727                 .reg_shift      = 2,
3728                 .base_baud      = 115200,
3729         },
3730         [pbn_fintek_4] = {
3731                 .num_ports      = 4,
3732                 .uart_offset    = 8,
3733                 .base_baud      = 115200,
3734                 .first_offset   = 0x40,
3735         },
3736         [pbn_fintek_8] = {
3737                 .num_ports      = 8,
3738                 .uart_offset    = 8,
3739                 .base_baud      = 115200,
3740                 .first_offset   = 0x40,
3741         },
3742         [pbn_fintek_12] = {
3743                 .num_ports      = 12,
3744                 .uart_offset    = 8,
3745                 .base_baud      = 115200,
3746                 .first_offset   = 0x40,
3747         },
3748         [pbn_wch382_2] = {
3749                 .flags          = FL_BASE0,
3750                 .num_ports      = 2,
3751                 .base_baud      = 115200,
3752                 .uart_offset    = 8,
3753                 .first_offset   = 0xC0,
3754         },
3755         [pbn_wch384_4] = {
3756                 .flags          = FL_BASE0,
3757                 .num_ports      = 4,
3758                 .base_baud      = 115200,
3759                 .uart_offset    = 8,
3760                 .first_offset   = 0xC0,
3761         },
3762         /*
3763          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3764          */
3765         [pbn_pericom_PI7C9X7951] = {
3766                 .flags          = FL_BASE0,
3767                 .num_ports      = 1,
3768                 .base_baud      = 921600,
3769                 .uart_offset    = 0x8,
3770         },
3771         [pbn_pericom_PI7C9X7952] = {
3772                 .flags          = FL_BASE0,
3773                 .num_ports      = 2,
3774                 .base_baud      = 921600,
3775                 .uart_offset    = 0x8,
3776         },
3777         [pbn_pericom_PI7C9X7954] = {
3778                 .flags          = FL_BASE0,
3779                 .num_ports      = 4,
3780                 .base_baud      = 921600,
3781                 .uart_offset    = 0x8,
3782         },
3783         [pbn_pericom_PI7C9X7958] = {
3784                 .flags          = FL_BASE0,
3785                 .num_ports      = 8,
3786                 .base_baud      = 921600,
3787                 .uart_offset    = 0x8,
3788         },
3789 };
3790 
3791 static const struct pci_device_id blacklist[] = {
3792         /* softmodems */
3793         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3794         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3795         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3796 
3797         /* multi-io cards handled by parport_serial */
3798         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3799         { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3800         { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3801         { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3802 
3803         /* Moxa Smartio MUE boards handled by 8250_moxa */
3804         { PCI_VDEVICE(MOXA, 0x1024), },
3805         { PCI_VDEVICE(MOXA, 0x1025), },
3806         { PCI_VDEVICE(MOXA, 0x1045), },
3807         { PCI_VDEVICE(MOXA, 0x1144), },
3808         { PCI_VDEVICE(MOXA, 0x1160), },
3809         { PCI_VDEVICE(MOXA, 0x1161), },
3810         { PCI_VDEVICE(MOXA, 0x1182), },
3811         { PCI_VDEVICE(MOXA, 0x1183), },
3812         { PCI_VDEVICE(MOXA, 0x1322), },
3813         { PCI_VDEVICE(MOXA, 0x1342), },
3814         { PCI_VDEVICE(MOXA, 0x1381), },
3815         { PCI_VDEVICE(MOXA, 0x1683), },
3816 
3817         /* Intel platforms with MID UART */
3818         { PCI_VDEVICE(INTEL, 0x081b), },
3819         { PCI_VDEVICE(INTEL, 0x081c), },
3820         { PCI_VDEVICE(INTEL, 0x081d), },
3821         { PCI_VDEVICE(INTEL, 0x1191), },
3822         { PCI_VDEVICE(INTEL, 0x19d8), },
3823 };
3824 
3825 /*
3826  * Given a complete unknown PCI device, try to use some heuristics to
3827  * guess what the configuration might be, based on the pitiful PCI
3828  * serial specs.  Returns 0 on success, 1 on failure.
3829  */
3830 static int
3831 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3832 {
3833         const struct pci_device_id *bldev;
3834         int num_iomem, num_port, first_port = -1, i;
3835 
3836         /*
3837          * If it is not a communications device or the programming
3838          * interface is greater than 6, give up.
3839          *
3840          * (Should we try to make guesses for multiport serial devices
3841          * later?)
3842          */
3843         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3844              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3845             (dev->class & 0xff) > 6)
3846                 return -ENODEV;
3847 
3848         /*
3849          * Do not access blacklisted devices that are known not to
3850          * feature serial ports or are handled by other modules.
3851          */
3852         for (bldev = blacklist;
3853              bldev < blacklist + ARRAY_SIZE(blacklist);
3854              bldev++) {
3855                 if (dev->vendor == bldev->vendor &&
3856                     dev->device == bldev->device)
3857                         return -ENODEV;
3858         }
3859 
3860         num_iomem = num_port = 0;
3861         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3862                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3863                         num_port++;
3864                         if (first_port == -1)
3865                                 first_port = i;
3866                 }
3867                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3868                         num_iomem++;
3869         }
3870 
3871         /*
3872          * If there is 1 or 0 iomem regions, and exactly one port,
3873          * use it.  We guess the number of ports based on the IO
3874          * region size.
3875          */
3876         if (num_iomem <= 1 && num_port == 1) {
3877                 board->flags = first_port;
3878                 board->num_ports = pci_resource_len(dev, first_port) / 8;
3879                 return 0;
3880         }
3881 
3882         /*
3883          * Now guess if we've got a board which indexes by BARs.
3884          * Each IO BAR should be 8 bytes, and they should follow
3885          * consecutively.
3886          */
3887         first_port = -1;
3888         num_port = 0;
3889         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3890                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3891                     pci_resource_len(dev, i) == 8 &&
3892                     (first_port == -1 || (first_port + num_port) == i)) {
3893                         num_port++;
3894                         if (first_port == -1)
3895                                 first_port = i;
3896                 }
3897         }
3898 
3899         if (num_port > 1) {
3900                 board->flags = first_port | FL_BASE_BARS;
3901                 board->num_ports = num_port;
3902                 return 0;
3903         }
3904 
3905         return -ENODEV;
3906 }
3907 
3908 static inline int
3909 serial_pci_matches(const struct pciserial_board *board,
3910                    const struct pciserial_board *guessed)
3911 {
3912         return
3913             board->num_ports == guessed->num_ports &&
3914             board->base_baud == guessed->base_baud &&
3915             board->uart_offset == guessed->uart_offset &&
3916             board->reg_shift == guessed->reg_shift &&
3917             board->first_offset == guessed->first_offset;
3918 }
3919 
3920 struct serial_private *
3921 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3922 {
3923         struct uart_8250_port uart;
3924         struct serial_private *priv;
3925         struct pci_serial_quirk *quirk;
3926         int rc, nr_ports, i;
3927 
3928         nr_ports = board->num_ports;
3929 
3930         /*
3931          * Find an init and setup quirks.
3932          */
3933         quirk = find_quirk(dev);
3934 
3935         /*
3936          * Run the new-style initialization function.
3937          * The initialization function returns:
3938          *  <0  - error
3939          *   0  - use board->num_ports
3940          *  >0  - number of ports
3941          */
3942         if (quirk->init) {
3943                 rc = quirk->init(dev);
3944                 if (rc < 0) {
3945                         priv = ERR_PTR(rc);
3946                         goto err_out;
3947                 }
3948                 if (rc)
3949                         nr_ports = rc;
3950         }
3951 
3952         priv = kzalloc(sizeof(struct serial_private) +
3953                        sizeof(unsigned int) * nr_ports,
3954                        GFP_KERNEL);
3955         if (!priv) {
3956                 priv = ERR_PTR(-ENOMEM);
3957                 goto err_deinit;
3958         }
3959 
3960         priv->dev = dev;
3961         priv->quirk = quirk;
3962 
3963         memset(&uart, 0, sizeof(uart));
3964         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3965         uart.port.uartclk = board->base_baud * 16;
3966         uart.port.irq = get_pci_irq(dev, board);
3967         uart.port.dev = &dev->dev;
3968 
3969         for (i = 0; i < nr_ports; i++) {
3970                 if (quirk->setup(priv, board, &uart, i))
3971                         break;
3972 
3973                 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3974                         uart.port.iobase, uart.port.irq, uart.port.iotype);
3975 
3976                 priv->line[i] = serial8250_register_8250_port(&uart);
3977                 if (priv->line[i] < 0) {
3978                         dev_err(&dev->dev,
3979                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3980                                 uart.port.iobase, uart.port.irq,
3981                                 uart.port.iotype, priv->line[i]);
3982                         break;
3983                 }
3984         }
3985         priv->nr = i;
3986         return priv;
3987 
3988 err_deinit:
3989         if (quirk->exit)
3990                 quirk->exit(dev);
3991 err_out:
3992         return priv;
3993 }
3994 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3995 
3996 void pciserial_remove_ports(struct serial_private *priv)
3997 {
3998         struct pci_serial_quirk *quirk;
3999         int i;
4000 
4001         for (i = 0; i < priv->nr; i++)
4002                 serial8250_unregister_port(priv->line[i]);
4003 
4004         /*
4005          * Find the exit quirks.
4006          */
4007         quirk = find_quirk(priv->dev);
4008         if (quirk->exit)
4009                 quirk->exit(priv->dev);
4010 
4011         kfree(priv);
4012 }
4013 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4014 
4015 void pciserial_suspend_ports(struct serial_private *priv)
4016 {
4017         int i;
4018 
4019         for (i = 0; i < priv->nr; i++)
4020                 if (priv->line[i] >= 0)
4021                         serial8250_suspend_port(priv->line[i]);
4022 
4023         /*
4024          * Ensure that every init quirk is properly torn down
4025          */
4026         if (priv->quirk->exit)
4027                 priv->quirk->exit(priv->dev);
4028 }
4029 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4030 
4031 void pciserial_resume_ports(struct serial_private *priv)
4032 {
4033         int i;
4034 
4035         /*
4036          * Ensure that the board is correctly configured.
4037          */
4038         if (priv->quirk->init)
4039                 priv->quirk->init(priv->dev);
4040 
4041         for (i = 0; i < priv->nr; i++)
4042                 if (priv->line[i] >= 0)
4043                         serial8250_resume_port(priv->line[i]);
4044 }
4045 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4046 
4047 /*
4048  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
4049  * to the arrangement of serial ports on a PCI card.
4050  */
4051 static int
4052 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4053 {
4054         struct pci_serial_quirk *quirk;
4055         struct serial_private *priv;
4056         const struct pciserial_board *board;
4057         struct pciserial_board tmp;
4058         int rc;
4059 
4060         quirk = find_quirk(dev);
4061         if (quirk->probe) {
4062                 rc = quirk->probe(dev);
4063                 if (rc)
4064                         return rc;
4065         }
4066 
4067         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4068                 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4069                         ent->driver_data);
4070                 return -EINVAL;
4071         }
4072 
4073         board = &pci_boards[ent->driver_data];
4074 
4075         rc = pcim_enable_device(dev);
4076         pci_save_state(dev);
4077         if (rc)
4078                 return rc;
4079 
4080         if (ent->driver_data == pbn_default) {
4081                 /*
4082                  * Use a copy of the pci_board entry for this;
4083                  * avoid changing entries in the table.
4084                  */
4085                 memcpy(&tmp, board, sizeof(struct pciserial_board));
4086                 board = &tmp;
4087 
4088                 /*
4089                  * We matched one of our class entries.  Try to
4090                  * determine the parameters of this board.
4091                  */
4092                 rc = serial_pci_guess_board(dev, &tmp);
4093                 if (rc)
4094                         return rc;
4095         } else {
4096                 /*
4097                  * We matched an explicit entry.  If we are able to
4098                  * detect this boards settings with our heuristic,
4099                  * then we no longer need this entry.
4100                  */
4101                 memcpy(&tmp, &pci_boards[pbn_default],
4102                        sizeof(struct pciserial_board));
4103                 rc = serial_pci_guess_board(dev, &tmp);
4104                 if (rc == 0 && serial_pci_matches(board, &tmp))
4105                         moan_device("Redundant entry in serial pci_table.",
4106                                     dev);
4107         }
4108 
4109         priv = pciserial_init_ports(dev, board);
4110         if (IS_ERR(priv))
4111                 return PTR_ERR(priv);
4112 
4113         pci_set_drvdata(dev, priv);
4114         return 0;
4115 }
4116 
4117 static void pciserial_remove_one(struct pci_dev *dev)
4118 {
4119         struct serial_private *priv = pci_get_drvdata(dev);
4120 
4121         pciserial_remove_ports(priv);
4122 }
4123 
4124 #ifdef CONFIG_PM_SLEEP
4125 static int pciserial_suspend_one(struct device *dev)
4126 {
4127         struct pci_dev *pdev = to_pci_dev(dev);
4128         struct serial_private *priv = pci_get_drvdata(pdev);
4129 
4130         if (priv)
4131                 pciserial_suspend_ports(priv);
4132 
4133         return 0;
4134 }
4135 
4136 static int pciserial_resume_one(struct device *dev)
4137 {
4138         struct pci_dev *pdev = to_pci_dev(dev);
4139         struct serial_private *priv = pci_get_drvdata(pdev);
4140         int err;
4141 
4142         if (priv) {
4143                 /*
4144                  * The device may have been disabled.  Re-enable it.
4145                  */
4146                 err = pci_enable_device(pdev);
4147                 /* FIXME: We cannot simply error out here */
4148                 if (err)
4149                         dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4150                 pciserial_resume_ports(priv);
4151         }
4152         return 0;
4153 }
4154 #endif
4155 
4156 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4157                          pciserial_resume_one);
4158 
4159 static struct pci_device_id serial_pci_tbl[] = {
4160         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4161         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4162                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4163                 pbn_b2_8_921600 },
4164         /* Advantech also use 0x3618 and 0xf618 */
4165         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4166                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4167                 pbn_b0_4_921600 },
4168         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4169                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4170                 pbn_b0_4_921600 },
4171         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4172                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4173                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4174                 pbn_b1_8_1382400 },
4175         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4176                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4177                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4178                 pbn_b1_4_1382400 },
4179         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4180                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4181                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4182                 pbn_b1_2_1382400 },
4183         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4184                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4185                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4186                 pbn_b1_8_1382400 },
4187         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4188                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4189                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4190                 pbn_b1_4_1382400 },
4191         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4192                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4193                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4194                 pbn_b1_2_1382400 },
4195         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4196                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4197                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4198                 pbn_b1_8_921600 },
4199         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4200                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4201                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4202                 pbn_b1_8_921600 },
4203         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4204                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4205                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4206                 pbn_b1_4_921600 },
4207         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4208                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4209                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4210                 pbn_b1_4_921600 },
4211         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4212                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4213                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4214                 pbn_b1_2_921600 },
4215         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4216                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4217                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4218                 pbn_b1_8_921600 },
4219         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4220                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4221                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4222                 pbn_b1_8_921600 },
4223         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4224                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4225                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4226                 pbn_b1_4_921600 },
4227         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4228                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4229                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4230                 pbn_b1_2_1250000 },
4231         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4232                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4233                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4234                 pbn_b0_2_1843200 },
4235         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4236                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4237                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4238                 pbn_b0_4_1843200 },
4239         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4240                 PCI_VENDOR_ID_AFAVLAB,
4241                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4242                 pbn_b0_4_1152000 },
4243         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4244                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4245                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4246                 pbn_b0_2_1843200_200 },
4247         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4248                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4249                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4250                 pbn_b0_4_1843200_200 },
4251         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4252                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4253                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4254                 pbn_b0_8_1843200_200 },
4255         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4256                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4257                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4258                 pbn_b0_2_1843200_200 },
4259         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4260                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4261                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4262                 pbn_b0_4_1843200_200 },
4263         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4264                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4265                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4266                 pbn_b0_8_1843200_200 },
4267         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4268                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4269                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4270                 pbn_b0_2_1843200_200 },
4271         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4272                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4273                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4274                 pbn_b0_4_1843200_200 },
4275         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4276                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4277                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4278                 pbn_b0_8_1843200_200 },
4279         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4280                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4281                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4282                 pbn_b0_2_1843200_200 },
4283         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4284                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4285                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4286                 pbn_b0_4_1843200_200 },
4287         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4288                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4289                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4290                 pbn_b0_8_1843200_200 },
4291         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4292                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4293                 0, 0, pbn_exar_ibm_saturn },
4294 
4295         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4296                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4297                 pbn_b2_bt_1_115200 },
4298         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4299                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4300                 pbn_b2_bt_2_115200 },
4301         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4302                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4303                 pbn_b2_bt_4_115200 },
4304         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4305                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4306                 pbn_b2_bt_2_115200 },
4307         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4308                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4309                 pbn_b2_bt_4_115200 },
4310         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4311                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312                 pbn_b2_8_115200 },
4313         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4314                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315                 pbn_b2_8_460800 },
4316         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4317                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4318                 pbn_b2_8_115200 },
4319 
4320         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4321                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4322                 pbn_b2_bt_2_115200 },
4323         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4324                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4325                 pbn_b2_bt_2_921600 },
4326         /*
4327          * VScom SPCOM800, from sl@s.pl
4328          */
4329         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4330                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4331                 pbn_b2_8_921600 },
4332         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4333                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4334                 pbn_b2_4_921600 },
4335         /* Unknown card - subdevice 0x1584 */
4336         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4337                 PCI_VENDOR_ID_PLX,
4338                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4339                 pbn_b2_4_115200 },
4340         /* Unknown card - subdevice 0x1588 */
4341         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4342                 PCI_VENDOR_ID_PLX,
4343                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4344                 pbn_b2_8_115200 },
4345         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4346                 PCI_SUBVENDOR_ID_KEYSPAN,
4347                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4348                 pbn_panacom },
4349         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4350                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351                 pbn_panacom4 },
4352         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4353                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354                 pbn_panacom2 },
4355         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4356                 PCI_VENDOR_ID_ESDGMBH,
4357                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4358                 pbn_b2_4_115200 },
4359         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4360                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4361                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4362                 pbn_b2_4_460800 },
4363         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4364                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4365                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4366                 pbn_b2_8_460800 },
4367         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4368                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4369                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4370                 pbn_b2_16_460800 },
4371         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4372                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4373                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4374                 pbn_b2_16_460800 },
4375         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4376                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4377                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4378                 pbn_b2_4_460800 },
4379         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4380                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4381                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4382                 pbn_b2_8_460800 },
4383         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4384                 PCI_SUBVENDOR_ID_EXSYS,
4385                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4386                 pbn_b2_4_115200 },
4387         /*
4388          * Megawolf Romulus PCI Serial Card, from Mike Hudson
4389          * (Exoray@isys.ca)
4390          */
4391         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4392                 0x10b5, 0x106a, 0, 0,
4393                 pbn_plx_romulus },
4394         /*
4395         * EndRun Technologies. PCI express device range.
4396         *    EndRun PTP/1588 has 2 Native UARTs.
4397         */
4398         {       PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4399                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4400                 pbn_endrun_2_4000000 },
4401         /*
4402          * Quatech cards. These actually have configurable clocks but for
4403          * now we just use the default.
4404          *
4405          * 100 series are RS232, 200 series RS422,
4406          */
4407         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4408                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409                 pbn_b1_4_115200 },
4410         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4411                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4412                 pbn_b1_2_115200 },
4413         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4414                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415                 pbn_b2_2_115200 },
4416         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4417                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418                 pbn_b1_2_115200 },
4419         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4420                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4421                 pbn_b2_2_115200 },
4422         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4423                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4424                 pbn_b1_4_115200 },
4425         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4426                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427                 pbn_b1_8_115200 },
4428         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4429                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430                 pbn_b1_8_115200 },
4431         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4432                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4433                 pbn_b1_4_115200 },
4434         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4435                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4436                 pbn_b1_2_115200 },
4437         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4438                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439                 pbn_b1_4_115200 },
4440         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4441                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442                 pbn_b1_2_115200 },
4443         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4444                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445                 pbn_b2_4_115200 },
4446         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4447                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448                 pbn_b2_2_115200 },
4449         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4450                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451                 pbn_b2_1_115200 },
4452         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4453                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454                 pbn_b2_4_115200 },
4455         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4456                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457                 pbn_b2_2_115200 },
4458         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4459                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460                 pbn_b2_1_115200 },
4461         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4462                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4463                 pbn_b0_8_115200 },
4464 
4465         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4466                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4467                 0, 0,
4468                 pbn_b0_4_921600 },
4469         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4470                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4471                 0, 0,
4472                 pbn_b0_4_1152000 },
4473         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
4474                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4475                 pbn_b0_bt_2_921600 },
4476 
4477                 /*
4478                  * The below card is a little controversial since it is the
4479                  * subject of a PCI vendor/device ID clash.  (See
4480                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4481                  * For now just used the hex ID 0x950a.
4482                  */
4483         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4484                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4485                 0, 0, pbn_b0_2_115200 },
4486         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4487                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4488                 0, 0, pbn_b0_2_115200 },
4489         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4490                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4491                 pbn_b0_2_1130000 },
4492         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4493                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4494                 pbn_b0_1_921600 },
4495         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4496                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497                 pbn_b0_4_115200 },
4498         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4499                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500                 pbn_b0_bt_2_921600 },
4501         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4502                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503                 pbn_b2_8_1152000 },
4504 
4505         /*
4506          * Oxford Semiconductor Inc. Tornado PCI express device range.
4507          */
4508         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4509                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510                 pbn_b0_1_4000000 },
4511         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4512                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513                 pbn_b0_1_4000000 },
4514         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4515                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516                 pbn_oxsemi_1_4000000 },
4517         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4518                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4519                 pbn_oxsemi_1_4000000 },
4520         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4521                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4522                 pbn_b0_1_4000000 },
4523         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4524                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525                 pbn_b0_1_4000000 },
4526         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4527                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4528                 pbn_oxsemi_1_4000000 },
4529         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4530                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4531                 pbn_oxsemi_1_4000000 },
4532         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4533                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4534                 pbn_b0_1_4000000 },
4535         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4536                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4537                 pbn_b0_1_4000000 },
4538         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4539                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4540                 pbn_b0_1_4000000 },
4541         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4542                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4543                 pbn_b0_1_4000000 },
4544         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4545                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4546                 pbn_oxsemi_2_4000000 },
4547         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4548                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4549                 pbn_oxsemi_2_4000000 },
4550         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4551                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4552                 pbn_oxsemi_4_4000000 },
4553         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4554                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4555                 pbn_oxsemi_4_4000000 },
4556         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4557                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4558                 pbn_oxsemi_8_4000000 },
4559         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4560                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4561                 pbn_oxsemi_8_4000000 },
4562         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4563                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4564                 pbn_oxsemi_1_4000000 },
4565         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4566                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4567                 pbn_oxsemi_1_4000000 },
4568         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4569                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4570                 pbn_oxsemi_1_4000000 },
4571         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4572                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4573                 pbn_oxsemi_1_4000000 },
4574         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4575                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4576                 pbn_oxsemi_1_4000000 },
4577         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4578                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4579                 pbn_oxsemi_1_4000000 },
4580         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4581                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4582                 pbn_oxsemi_1_4000000 },
4583         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4584                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4585                 pbn_oxsemi_1_4000000 },
4586         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4587                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4588                 pbn_oxsemi_1_4000000 },
4589         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4590                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4591                 pbn_oxsemi_1_4000000 },
4592         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4593                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4594                 pbn_oxsemi_1_4000000 },
4595         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4596                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4597                 pbn_oxsemi_1_4000000 },
4598         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4599                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4600                 pbn_oxsemi_1_4000000 },
4601         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4602                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4603                 pbn_oxsemi_1_4000000 },
4604         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4605                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4606                 pbn_oxsemi_1_4000000 },
4607         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4608                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4609                 pbn_oxsemi_1_4000000 },
4610         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4611                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4612                 pbn_oxsemi_1_4000000 },
4613         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4614                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4615                 pbn_oxsemi_1_4000000 },
4616         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4617                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4618                 pbn_oxsemi_1_4000000 },
4619         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4620                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621                 pbn_oxsemi_1_4000000 },
4622         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4623                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4624                 pbn_oxsemi_1_4000000 },
4625         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4626                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627                 pbn_oxsemi_1_4000000 },
4628         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4629                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630                 pbn_oxsemi_1_4000000 },
4631         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4632                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633                 pbn_oxsemi_1_4000000 },
4634         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4635                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636                 pbn_oxsemi_1_4000000 },
4637         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4638                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639                 pbn_oxsemi_1_4000000 },
4640         /*
4641          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4642          */
4643         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4644                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4645                 pbn_oxsemi_1_4000000 },
4646         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4647                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4648                 pbn_oxsemi_2_4000000 },
4649         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4650                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4651                 pbn_oxsemi_4_4000000 },
4652         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4653                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4654                 pbn_oxsemi_8_4000000 },
4655 
4656         /*
4657          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4658          */
4659         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4660                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4661                 pbn_oxsemi_2_4000000 },
4662 
4663         /*
4664          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4665          * from skokodyn@yahoo.com
4666          */
4667         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4668                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4669                 pbn_sbsxrsio },
4670         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4671                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4672                 pbn_sbsxrsio },
4673         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4674                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4675                 pbn_sbsxrsio },
4676         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4677                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4678                 pbn_sbsxrsio },
4679 
4680         /*
4681          * Digitan DS560-558, from jimd@esoft.com
4682          */
4683         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4684                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4685                 pbn_b1_1_115200 },
4686 
4687         /*
4688          * Titan Electronic cards
4689          *  The 400L and 800L have a custom setup quirk.
4690          */
4691         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4692                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4693                 pbn_b0_1_921600 },
4694         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4695                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696                 pbn_b0_2_921600 },
4697         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4698                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4699                 pbn_b0_4_921600 },
4700         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4701                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4702                 pbn_b0_4_921600 },
4703         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4704                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4705                 pbn_b1_1_921600 },
4706         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4707                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708                 pbn_b1_bt_2_921600 },
4709         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4710                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711                 pbn_b0_bt_4_921600 },
4712         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4713                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714                 pbn_b0_bt_8_921600 },
4715         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4716                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4717                 pbn_b4_bt_2_921600 },
4718         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4719                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720                 pbn_b4_bt_4_921600 },
4721         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4722                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4723                 pbn_b4_bt_8_921600 },
4724         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4725                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726                 pbn_b0_4_921600 },
4727         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4728                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4729                 pbn_b0_4_921600 },
4730         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4731                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4732                 pbn_b0_4_921600 },
4733         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4734                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735                 pbn_oxsemi_1_4000000 },
4736         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4737                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4738                 pbn_oxsemi_2_4000000 },
4739         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4740                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4741                 pbn_oxsemi_4_4000000 },
4742         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4743                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4744                 pbn_oxsemi_8_4000000 },
4745         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4746                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4747                 pbn_oxsemi_2_4000000 },
4748         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4749                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4750                 pbn_oxsemi_2_4000000 },
4751         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4752                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4753                 pbn_b0_bt_2_921600 },
4754         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4755                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4756                 pbn_b0_4_921600 },
4757         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4758                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4759                 pbn_b0_4_921600 },
4760         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4761                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4762                 pbn_b0_4_921600 },
4763         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4764                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4765                 pbn_b0_4_921600 },
4766 
4767         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4768                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4769                 pbn_b2_1_460800 },
4770         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4771                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4772                 pbn_b2_1_460800 },
4773         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4774                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4775                 pbn_b2_1_460800 },
4776         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4777                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4778                 pbn_b2_bt_2_921600 },
4779         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4780                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4781                 pbn_b2_bt_2_921600 },
4782         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4783                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784                 pbn_b2_bt_2_921600 },
4785         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4786                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787                 pbn_b2_bt_4_921600 },
4788         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4789                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790                 pbn_b2_bt_4_921600 },
4791         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4792                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793                 pbn_b2_bt_4_921600 },
4794         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4795                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796                 pbn_b0_1_921600 },
4797         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4798                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799                 pbn_b0_1_921600 },
4800         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4801                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4802                 pbn_b0_1_921600 },
4803         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4804                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805                 pbn_b0_bt_2_921600 },
4806         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4807                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4808                 pbn_b0_bt_2_921600 },
4809         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4810                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811                 pbn_b0_bt_2_921600 },
4812         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4813                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814                 pbn_b0_bt_4_921600 },
4815         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4816                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4817                 pbn_b0_bt_4_921600 },
4818         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4819                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4820                 pbn_b0_bt_4_921600 },
4821         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4822                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4823                 pbn_b0_bt_8_921600 },
4824         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4825                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4826                 pbn_b0_bt_8_921600 },
4827         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4828                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4829                 pbn_b0_bt_8_921600 },
4830 
4831         /*
4832          * Computone devices submitted by Doug McNash dmcnash@computone.com
4833          */
4834         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4835                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4836                 0, 0, pbn_computone_4 },
4837         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4838                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4839                 0, 0, pbn_computone_8 },
4840         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4841                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4842                 0, 0, pbn_computone_6 },
4843 
4844         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4845                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4846                 pbn_oxsemi },
4847         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4848                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4849                 pbn_b0_bt_1_921600 },
4850 
4851         /*
4852          * SUNIX (TIMEDIA)
4853          */
4854         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4855                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4856                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4857                 pbn_b0_bt_1_921600 },
4858 
4859         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4860                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4861                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4862                 pbn_b0_bt_1_921600 },
4863 
4864         /*
4865          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4866          */
4867         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4868                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4869                 pbn_b0_bt_8_115200 },
4870         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4871                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4872                 pbn_b0_bt_8_115200 },
4873 
4874         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4875                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4876                 pbn_b0_bt_2_115200 },
4877         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4878                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4879                 pbn_b0_bt_2_115200 },
4880         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4881                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4882                 pbn_b0_bt_2_115200 },
4883         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4884                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4885                 pbn_b0_bt_2_115200 },
4886         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4887                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4888                 pbn_b0_bt_2_115200 },
4889         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4890                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891                 pbn_b0_bt_4_460800 },
4892         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4893                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894                 pbn_b0_bt_4_460800 },
4895         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4896                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4897                 pbn_b0_bt_2_460800 },
4898         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4899                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4900                 pbn_b0_bt_2_460800 },
4901         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4902                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4903                 pbn_b0_bt_2_460800 },
4904         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4905                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4906                 pbn_b0_bt_1_115200 },
4907         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4908                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4909                 pbn_b0_bt_1_460800 },
4910 
4911         /*
4912          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4913          * Cards are identified by their subsystem vendor IDs, which
4914          * (in hex) match the model number.
4915          *
4916          * Note that JC140x are RS422/485 cards which require ox950
4917          * ACR = 0x10, and as such are not currently fully supported.
4918          */
4919         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4920                 0x1204, 0x0004, 0, 0,
4921                 pbn_b0_4_921600 },
4922         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4923                 0x1208, 0x0004, 0, 0,
4924                 pbn_b0_4_921600 },
4925 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4926                 0x1402, 0x0002, 0, 0,
4927                 pbn_b0_2_921600 }, */
4928 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4929                 0x1404, 0x0004, 0, 0,
4930                 pbn_b0_4_921600 }, */
4931         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4932                 0x1208, 0x0004, 0, 0,
4933                 pbn_b0_4_921600 },
4934 
4935         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4936                 0x1204, 0x0004, 0, 0,
4937                 pbn_b0_4_921600 },
4938         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4939                 0x1208, 0x0004, 0, 0,
4940                 pbn_b0_4_921600 },
4941         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4942                 0x1208, 0x0004, 0, 0,
4943                 pbn_b0_4_921600 },
4944         /*
4945          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4946          */
4947         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4948                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4949                 pbn_b1_1_1382400 },
4950 
4951         /*
4952          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4953          */
4954         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4955                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4956                 pbn_b1_1_1382400 },
4957 
4958         /*
4959          * RAStel 2 port modem, gerg@moreton.com.au
4960          */
4961         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4962                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4963                 pbn_b2_bt_2_115200 },
4964 
4965         /*
4966          * EKF addition for i960 Boards form EKF with serial port
4967          */
4968         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4969                 0xE4BF, PCI_ANY_ID, 0, 0,
4970                 pbn_intel_i960 },
4971 
4972         /*
4973          * Xircom Cardbus/Ethernet combos
4974          */
4975         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4976                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4977                 pbn_b0_1_115200 },
4978         /*
4979          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4980          */
4981         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4982                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4983                 pbn_b0_1_115200 },
4984 
4985         /*
4986          * Untested PCI modems, sent in from various folks...
4987          */
4988 
4989         /*
4990          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4991          */
4992         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
4993                 0x1048, 0x1500, 0, 0,
4994                 pbn_b1_1_115200 },
4995 
4996         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4997                 0xFF00, 0, 0, 0,
4998                 pbn_sgi_ioc3 },
4999 
5000         /*
5001          * HP Diva card
5002          */
5003         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5004                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5005                 pbn_b1_1_115200 },
5006         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5007                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5008                 pbn_b0_5_115200 },
5009         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5010                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5011                 pbn_b2_1_115200 },
5012 
5013         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5014                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5015                 pbn_b3_2_115200 },
5016         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5017                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5018                 pbn_b3_4_115200 },
5019         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5020                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5021                 pbn_b3_8_115200 },
5022 
5023         /*
5024          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5025          */
5026         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5027                 PCI_ANY_ID, PCI_ANY_ID,
5028                 0,
5029                 0, pbn_exar_XR17C152 },
5030         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5031                 PCI_ANY_ID, PCI_ANY_ID,
5032                 0,
5033                 0, pbn_exar_XR17C154 },
5034         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5035                 PCI_ANY_ID, PCI_ANY_ID,
5036                 0,
5037                 0, pbn_exar_XR17C158 },
5038         /*
5039          * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5040          */
5041         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5042                 PCI_ANY_ID, PCI_ANY_ID,
5043                 0,
5044                 0, pbn_exar_XR17V352 },
5045         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5046                 PCI_ANY_ID, PCI_ANY_ID,
5047                 0,
5048                 0, pbn_exar_XR17V354 },
5049         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5050                 PCI_ANY_ID, PCI_ANY_ID,
5051                 0,
5052                 0, pbn_exar_XR17V358 },
5053         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5054                 PCI_ANY_ID, PCI_ANY_ID,
5055                 0,
5056                 0, pbn_exar_XR17V4358 },
5057         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5058                 PCI_ANY_ID, PCI_ANY_ID,
5059                 0,
5060                 0, pbn_exar_XR17V8358 },
5061         /*
5062          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5063          */
5064         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5065                 PCI_ANY_ID, PCI_ANY_ID,
5066                 0,
5067                 0, pbn_pericom_PI7C9X7951 },
5068         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5069                 PCI_ANY_ID, PCI_ANY_ID,
5070                 0,
5071                 0, pbn_pericom_PI7C9X7952 },
5072         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5073                 PCI_ANY_ID, PCI_ANY_ID,
5074                 0,
5075                 0, pbn_pericom_PI7C9X7954 },
5076         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5077                 PCI_ANY_ID, PCI_ANY_ID,
5078                 0,
5079                 0, pbn_pericom_PI7C9X7958 },
5080         /*
5081          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5082          */
5083         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5084                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5085                 pbn_b0_1_115200 },
5086         /*
5087          * ITE
5088          */
5089         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5090                 PCI_ANY_ID, PCI_ANY_ID,
5091                 0, 0,
5092                 pbn_b1_bt_1_115200 },
5093 
5094         /*
5095          * IntaShield IS-200
5096          */
5097         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5098                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
5099                 pbn_b2_2_115200 },
5100         /*
5101          * IntaShield IS-400
5102          */
5103         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5104                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
5105                 pbn_b2_4_115200 },
5106         /*
5107          * Perle PCI-RAS cards
5108          */
5109         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5110                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5111                 0, 0, pbn_b2_4_921600 },
5112         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5113                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5114                 0, 0, pbn_b2_8_921600 },
5115 
5116         /*
5117          * Mainpine series cards: Fairly standard layout but fools
5118          * parts of the autodetect in some cases and uses otherwise
5119          * unmatched communications subclasses in the PCI Express case
5120          */
5121 
5122         {       /* RockForceDUO */
5123                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5124                 PCI_VENDOR_ID_MAINPINE, 0x0200,
5125                 0, 0, pbn_b0_2_115200 },
5126         {       /* RockForceQUATRO */
5127                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5128                 PCI_VENDOR_ID_MAINPINE, 0x0300,
5129                 0, 0, pbn_b0_4_115200 },
5130         {       /* RockForceDUO+ */
5131                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5132                 PCI_VENDOR_ID_MAINPINE, 0x0400,
5133                 0, 0, pbn_b0_2_115200 },
5134         {       /* RockForceQUATRO+ */
5135                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5136                 PCI_VENDOR_ID_MAINPINE, 0x0500,
5137                 0, 0, pbn_b0_4_115200 },
5138         {       /* RockForce+ */
5139                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5140                 PCI_VENDOR_ID_MAINPINE, 0x0600,
5141                 0, 0, pbn_b0_2_115200 },
5142         {       /* RockForce+ */
5143                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5144                 PCI_VENDOR_ID_MAINPINE, 0x0700,
5145                 0, 0, pbn_b0_4_115200 },
5146         {       /* RockForceOCTO+ */
5147                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5148                 PCI_VENDOR_ID_MAINPINE, 0x0800,
5149                 0, 0, pbn_b0_8_115200 },
5150         {       /* RockForceDUO+ */
5151                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5152                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5153                 0, 0, pbn_b0_2_115200 },
5154         {       /* RockForceQUARTRO+ */
5155                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5156                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5157                 0, 0, pbn_b0_4_115200 },
5158         {       /* RockForceOCTO+ */
5159                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5160                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5161                 0, 0, pbn_b0_8_115200 },
5162         {       /* RockForceD1 */
5163                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5164                 PCI_VENDOR_ID_MAINPINE, 0x2000,
5165                 0, 0, pbn_b0_1_115200 },
5166         {       /* RockForceF1 */
5167                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5168                 PCI_VENDOR_ID_MAINPINE, 0x2100,
5169                 0, 0, pbn_b0_1_115200 },
5170         {       /* RockForceD2 */
5171                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5172                 PCI_VENDOR_ID_MAINPINE, 0x2200,
5173                 0, 0, pbn_b0_2_115200 },
5174         {       /* RockForceF2 */
5175                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5176                 PCI_VENDOR_ID_MAINPINE, 0x2300,
5177                 0, 0, pbn_b0_2_115200 },
5178         {       /* RockForceD4 */
5179                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5180                 PCI_VENDOR_ID_MAINPINE, 0x2400,
5181                 0, 0, pbn_b0_4_115200 },
5182         {       /* RockForceF4 */
5183                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5184                 PCI_VENDOR_ID_MAINPINE, 0x2500,
5185                 0, 0, pbn_b0_4_115200 },
5186         {       /* RockForceD8 */
5187                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5188                 PCI_VENDOR_ID_MAINPINE, 0x2600,
5189                 0, 0, pbn_b0_8_115200 },
5190         {       /* RockForceF8 */
5191                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5192                 PCI_VENDOR_ID_MAINPINE, 0x2700,
5193                 0, 0, pbn_b0_8_115200 },
5194         {       /* IQ Express D1 */
5195                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5196                 PCI_VENDOR_ID_MAINPINE, 0x3000,
5197                 0, 0, pbn_b0_1_115200 },
5198         {       /* IQ Express F1 */
5199                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5200                 PCI_VENDOR_ID_MAINPINE, 0x3100,
5201                 0, 0, pbn_b0_1_115200 },
5202         {       /* IQ Express D2 */
5203                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5204                 PCI_VENDOR_ID_MAINPINE, 0x3200,
5205                 0, 0, pbn_b0_2_115200 },
5206         {       /* IQ Express F2 */
5207                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5208                 PCI_VENDOR_ID_MAINPINE, 0x3300,
5209                 0, 0, pbn_b0_2_115200 },
5210         {       /* IQ Express D4 */
5211                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5212                 PCI_VENDOR_ID_MAINPINE, 0x3400,
5213                 0, 0, pbn_b0_4_115200 },
5214         {       /* IQ Express F4 */
5215                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5216                 PCI_VENDOR_ID_MAINPINE, 0x3500,
5217                 0, 0, pbn_b0_4_115200 },
5218         {       /* IQ Express D8 */
5219                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5220                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5221                 0, 0, pbn_b0_8_115200 },
5222         {       /* IQ Express F8 */
5223                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5224                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5225                 0, 0, pbn_b0_8_115200 },
5226 
5227 
5228         /*
5229          * PA Semi PA6T-1682M on-chip UART
5230          */
5231         {       PCI_VENDOR_ID_PASEMI, 0xa004,
5232                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5233                 pbn_pasemi_1682M },
5234 
5235         /*
5236          * National Instruments
5237          */
5238         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5239                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5240                 pbn_b1_16_115200 },
5241         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5242                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5243                 pbn_b1_8_115200 },
5244         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5245                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5246                 pbn_b1_bt_4_115200 },
5247         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5248                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5249                 pbn_b1_bt_2_115200 },
5250         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5251                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5252                 pbn_b1_bt_4_115200 },
5253         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5254                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5255                 pbn_b1_bt_2_115200 },
5256         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5257                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5258                 pbn_b1_16_115200 },
5259         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5260                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5261                 pbn_b1_8_115200 },
5262         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5263                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5264                 pbn_b1_bt_4_115200 },
5265         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5266                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5267                 pbn_b1_bt_2_115200 },
5268         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5269                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5270                 pbn_b1_bt_4_115200 },
5271         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5272                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5273                 pbn_b1_bt_2_115200 },
5274         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5275                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5276                 pbn_ni8430_2 },
5277         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5278                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5279                 pbn_ni8430_2 },
5280         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5281                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5282                 pbn_ni8430_4 },
5283         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5284                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5285                 pbn_ni8430_4 },
5286         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5287                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5288                 pbn_ni8430_8 },
5289         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5290                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5291                 pbn_ni8430_8 },
5292         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5293                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5294                 pbn_ni8430_16 },
5295         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5296                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5297                 pbn_ni8430_16 },
5298         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5299                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5300                 pbn_ni8430_2 },
5301         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5302                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5303                 pbn_ni8430_2 },
5304         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5305                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5306                 pbn_ni8430_4 },
5307         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5308                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5309                 pbn_ni8430_4 },
5310 
5311         /*
5312         * ADDI-DATA GmbH communication cards <info@addi-data.com>
5313         */
5314         {       PCI_VENDOR_ID_ADDIDATA,
5315                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5316                 PCI_ANY_ID,
5317                 PCI_ANY_ID,
5318                 0,
5319                 0,
5320                 pbn_b0_4_115200 },
5321 
5322         {       PCI_VENDOR_ID_ADDIDATA,
5323                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5324                 PCI_ANY_ID,
5325                 PCI_ANY_ID,
5326                 0,
5327                 0,
5328                 pbn_b0_2_115200 },
5329 
5330         {       PCI_VENDOR_ID_ADDIDATA,
5331                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5332                 PCI_ANY_ID,
5333                 PCI_ANY_ID,
5334                 0,
5335                 0,
5336                 pbn_b0_1_115200 },
5337 
5338         {       PCI_VENDOR_ID_AMCC,
5339                 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5340                 PCI_ANY_ID,
5341                 PCI_ANY_ID,
5342                 0,
5343                 0,
5344                 pbn_b1_8_115200 },
5345 
5346         {       PCI_VENDOR_ID_ADDIDATA,
5347                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5348                 PCI_ANY_ID,
5349                 PCI_ANY_ID,
5350                 0,
5351                 0,
5352                 pbn_b0_4_115200 },
5353 
5354         {       PCI_VENDOR_ID_ADDIDATA,
5355                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5356                 PCI_ANY_ID,
5357                 PCI_ANY_ID,
5358                 0,
5359                 0,
5360                 pbn_b0_2_115200 },
5361 
5362         {       PCI_VENDOR_ID_ADDIDATA,
5363                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5364                 PCI_ANY_ID,
5365                 PCI_ANY_ID,
5366                 0,
5367                 0,
5368                 pbn_b0_1_115200 },
5369 
5370         {       PCI_VENDOR_ID_ADDIDATA,
5371                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5372                 PCI_ANY_ID,
5373                 PCI_ANY_ID,
5374                 0,
5375                 0,
5376                 pbn_b0_4_115200 },
5377 
5378         {       PCI_VENDOR_ID_ADDIDATA,
5379                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5380                 PCI_ANY_ID,
5381                 PCI_ANY_ID,
5382                 0,
5383                 0,
5384                 pbn_b0_2_115200 },
5385 
5386         {       PCI_VENDOR_ID_ADDIDATA,
5387                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5388                 PCI_ANY_ID,
5389                 PCI_ANY_ID,
5390                 0,
5391                 0,
5392                 pbn_b0_1_115200 },
5393 
5394         {       PCI_VENDOR_ID_ADDIDATA,
5395                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5396                 PCI_ANY_ID,
5397                 PCI_ANY_ID,
5398                 0,
5399                 0,
5400                 pbn_b0_8_115200 },
5401 
5402         {       PCI_VENDOR_ID_ADDIDATA,
5403                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5404                 PCI_ANY_ID,
5405                 PCI_ANY_ID,
5406                 0,
5407                 0,
5408                 pbn_ADDIDATA_PCIe_4_3906250 },
5409 
5410         {       PCI_VENDOR_ID_ADDIDATA,
5411                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5412                 PCI_ANY_ID,
5413                 PCI_ANY_ID,
5414                 0,
5415                 0,
5416                 pbn_ADDIDATA_PCIe_2_3906250 },
5417 
5418         {       PCI_VENDOR_ID_ADDIDATA,
5419                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5420                 PCI_ANY_ID,
5421                 PCI_ANY_ID,
5422                 0,
5423                 0,
5424                 pbn_ADDIDATA_PCIe_1_3906250 },
5425 
5426         {       PCI_VENDOR_ID_ADDIDATA,
5427                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5428                 PCI_ANY_ID,
5429                 PCI_ANY_ID,
5430                 0,
5431                 0,
5432                 pbn_ADDIDATA_PCIe_8_3906250 },
5433 
5434         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5435                 PCI_VENDOR_ID_IBM, 0x0299,
5436                 0, 0, pbn_b0_bt_2_115200 },
5437 
5438         /*
5439          * other NetMos 9835 devices are most likely handled by the
5440          * parport_serial driver, check drivers/parport/parport_serial.c
5441          * before adding them here.
5442          */
5443 
5444         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5445                 0xA000, 0x1000,
5446                 0, 0, pbn_b0_1_115200 },
5447 
5448         /* the 9901 is a rebranded 9912 */
5449         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5450                 0xA000, 0x1000,
5451                 0, 0, pbn_b0_1_115200 },
5452 
5453         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5454                 0xA000, 0x1000,
5455                 0, 0, pbn_b0_1_115200 },
5456 
5457         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5458                 0xA000, 0x1000,
5459                 0, 0, pbn_b0_1_115200 },
5460 
5461         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5462                 0xA000, 0x1000,
5463                 0, 0, pbn_b0_1_115200 },
5464 
5465         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5466                 0xA000, 0x3002,
5467                 0, 0, pbn_NETMOS9900_2s_115200 },
5468 
5469         /*
5470          * Best Connectivity and Rosewill PCI Multi I/O cards
5471          */
5472 
5473         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5474                 0xA000, 0x1000,
5475                 0, 0, pbn_b0_1_115200 },
5476 
5477         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5478                 0xA000, 0x3002,
5479                 0, 0, pbn_b0_bt_2_115200 },
5480 
5481         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5482                 0xA000, 0x3004,
5483                 0, 0, pbn_b0_bt_4_115200 },
5484         /* Intel CE4100 */
5485         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5486                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5487                 pbn_ce4100_1_115200 },
5488         /* Intel BayTrail */
5489         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5490                 PCI_ANY_ID,  PCI_ANY_ID,
5491                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5492                 pbn_byt },
5493         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5494                 PCI_ANY_ID,  PCI_ANY_ID,
5495                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5496                 pbn_byt },
5497         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5498                 PCI_ANY_ID,  PCI_ANY_ID,
5499                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5500                 pbn_byt },
5501         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5502                 PCI_ANY_ID,  PCI_ANY_ID,
5503                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5504                 pbn_byt },
5505 
5506         /* Intel Broadwell */
5507         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1,
5508                 PCI_ANY_ID,  PCI_ANY_ID,
5509                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5510                 pbn_byt },
5511         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2,
5512                 PCI_ANY_ID,  PCI_ANY_ID,
5513                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5514                 pbn_byt },
5515 
5516         /*
5517          * Intel Quark x1000
5518          */
5519         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5520                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5521                 pbn_qrk },
5522         /*
5523          * Cronyx Omega PCI
5524          */
5525         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5526                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5527                 pbn_omegapci },
5528 
5529         /*
5530          * Broadcom TruManage
5531          */
5532         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5533                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5534                 pbn_brcm_trumanage },
5535 
5536         /*
5537          * AgeStar as-prs2-009
5538          */
5539         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5540                 PCI_ANY_ID, PCI_ANY_ID,
5541                 0, 0, pbn_b0_bt_2_115200 },
5542 
5543         /*
5544          * WCH CH353 series devices: The 2S1P is handled by parport_serial
5545          * so not listed here.
5546          */
5547         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5548                 PCI_ANY_ID, PCI_ANY_ID,
5549                 0, 0, pbn_b0_bt_4_115200 },
5550 
5551         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5552                 PCI_ANY_ID, PCI_ANY_ID,
5553                 0, 0, pbn_b0_bt_2_115200 },
5554 
5555         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5556                 PCI_ANY_ID, PCI_ANY_ID,
5557                 0, 0, pbn_wch382_2 },
5558 
5559         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5560                 PCI_ANY_ID, PCI_ANY_ID,
5561                 0, 0, pbn_wch384_4 },
5562 
5563         /*
5564          * Commtech, Inc. Fastcom adapters
5565          */
5566         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5567                 PCI_ANY_ID, PCI_ANY_ID,
5568                 0,
5569                 0, pbn_b0_2_1152000_200 },
5570         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5571                 PCI_ANY_ID, PCI_ANY_ID,
5572                 0,
5573                 0, pbn_b0_4_1152000_200 },
5574         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5575                 PCI_ANY_ID, PCI_ANY_ID,
5576                 0,
5577                 0, pbn_b0_4_1152000_200 },
5578         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5579                 PCI_ANY_ID, PCI_ANY_ID,
5580                 0,
5581                 0, pbn_b0_8_1152000_200 },
5582         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5583                 PCI_ANY_ID, PCI_ANY_ID,
5584                 0,
5585                 0, pbn_exar_XR17V352 },
5586         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5587                 PCI_ANY_ID, PCI_ANY_ID,
5588                 0,
5589                 0, pbn_exar_XR17V354 },
5590         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5591                 PCI_ANY_ID, PCI_ANY_ID,
5592                 0,
5593                 0, pbn_exar_XR17V358 },
5594 
5595         /* Fintek PCI serial cards */
5596         { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5597         { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5598         { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5599 
5600         /*
5601          * These entries match devices with class COMMUNICATION_SERIAL,
5602          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5603          */
5604         {       PCI_ANY_ID, PCI_ANY_ID,
5605                 PCI_ANY_ID, PCI_ANY_ID,
5606                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5607                 0xffff00, pbn_default },
5608         {       PCI_ANY_ID, PCI_ANY_ID,
5609                 PCI_ANY_ID, PCI_ANY_ID,
5610                 PCI_CLASS_COMMUNICATION_MODEM << 8,
5611                 0xffff00, pbn_default },
5612         {       PCI_ANY_ID, PCI_ANY_ID,
5613                 PCI_ANY_ID, PCI_ANY_ID,
5614                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5615                 0xffff00, pbn_default },
5616         { 0, }
5617 };
5618 
5619 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5620                                                 pci_channel_state_t state)
5621 {
5622         struct serial_private *priv = pci_get_drvdata(dev);
5623 
5624         if (state == pci_channel_io_perm_failure)
5625                 return PCI_ERS_RESULT_DISCONNECT;
5626 
5627         if (priv)
5628                 pciserial_suspend_ports(priv);
5629 
5630         pci_disable_device(dev);
5631 
5632         return PCI_ERS_RESULT_NEED_RESET;
5633 }
5634 
5635 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5636 {
5637         int rc;
5638 
5639         rc = pci_enable_device(dev);
5640 
5641         if (rc)
5642                 return PCI_ERS_RESULT_DISCONNECT;
5643 
5644         pci_restore_state(dev);
5645         pci_save_state(dev);
5646 
5647         return PCI_ERS_RESULT_RECOVERED;
5648 }
5649 
5650 static void serial8250_io_resume(struct pci_dev *dev)
5651 {
5652         struct serial_private *priv = pci_get_drvdata(dev);
5653 
5654         if (priv)
5655                 pciserial_resume_ports(priv);
5656 }
5657 
5658 static const struct pci_error_handlers serial8250_err_handler = {
5659         .error_detected = serial8250_io_error_detected,
5660         .slot_reset = serial8250_io_slot_reset,
5661         .resume = serial8250_io_resume,
5662 };
5663 
5664 static struct pci_driver serial_pci_driver = {
5665         .name           = "serial",
5666         .probe          = pciserial_init_one,
5667         .remove         = pciserial_remove_one,
5668         .driver         = {
5669                 .pm     = &pciserial_pm_ops,
5670         },
5671         .id_table       = serial_pci_tbl,
5672         .err_handler    = &serial8250_err_handler,
5673 };
5674 
5675 module_pci_driver(serial_pci_driver);
5676 
5677 MODULE_LICENSE("GPL");
5678 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5679 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
5680 

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