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Linux/drivers/tty/serial/8250/8250_pci.c

  1 /*
  2  *  Probe module for 8250/16550-type PCI serial ports.
  3  *
  4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  5  *
  6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License.
 11  */
 12 #undef DEBUG
 13 #include <linux/module.h>
 14 #include <linux/pci.h>
 15 #include <linux/string.h>
 16 #include <linux/kernel.h>
 17 #include <linux/slab.h>
 18 #include <linux/delay.h>
 19 #include <linux/tty.h>
 20 #include <linux/serial_reg.h>
 21 #include <linux/serial_core.h>
 22 #include <linux/8250_pci.h>
 23 #include <linux/bitops.h>
 24 #include <linux/rational.h>
 25 
 26 #include <asm/byteorder.h>
 27 #include <asm/io.h>
 28 
 29 #include <linux/dmaengine.h>
 30 #include <linux/platform_data/dma-dw.h>
 31 
 32 #include "8250.h"
 33 
 34 /*
 35  * init function returns:
 36  *  > 0 - number of ports
 37  *  = 0 - use board->num_ports
 38  *  < 0 - error
 39  */
 40 struct pci_serial_quirk {
 41         u32     vendor;
 42         u32     device;
 43         u32     subvendor;
 44         u32     subdevice;
 45         int     (*probe)(struct pci_dev *dev);
 46         int     (*init)(struct pci_dev *dev);
 47         int     (*setup)(struct serial_private *,
 48                          const struct pciserial_board *,
 49                          struct uart_8250_port *, int);
 50         void    (*exit)(struct pci_dev *dev);
 51 };
 52 
 53 #define PCI_NUM_BAR_RESOURCES   6
 54 
 55 struct serial_private {
 56         struct pci_dev          *dev;
 57         unsigned int            nr;
 58         struct pci_serial_quirk *quirk;
 59         int                     line[0];
 60 };
 61 
 62 static int pci_default_setup(struct serial_private*,
 63           const struct pciserial_board*, struct uart_8250_port *, int);
 64 
 65 static void moan_device(const char *str, struct pci_dev *dev)
 66 {
 67         dev_err(&dev->dev,
 68                "%s: %s\n"
 69                "Please send the output of lspci -vv, this\n"
 70                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
 71                "manufacturer and name of serial board or\n"
 72                "modem board to <linux-serial@vger.kernel.org>.\n",
 73                pci_name(dev), str, dev->vendor, dev->device,
 74                dev->subsystem_vendor, dev->subsystem_device);
 75 }
 76 
 77 static int
 78 setup_port(struct serial_private *priv, struct uart_8250_port *port,
 79            int bar, int offset, int regshift)
 80 {
 81         struct pci_dev *dev = priv->dev;
 82 
 83         if (bar >= PCI_NUM_BAR_RESOURCES)
 84                 return -EINVAL;
 85 
 86         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
 87                 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
 88                         return -ENOMEM;
 89 
 90                 port->port.iotype = UPIO_MEM;
 91                 port->port.iobase = 0;
 92                 port->port.mapbase = pci_resource_start(dev, bar) + offset;
 93                 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
 94                 port->port.regshift = regshift;
 95         } else {
 96                 port->port.iotype = UPIO_PORT;
 97                 port->port.iobase = pci_resource_start(dev, bar) + offset;
 98                 port->port.mapbase = 0;
 99                 port->port.membase = NULL;
100                 port->port.regshift = 0;
101         }
102         return 0;
103 }
104 
105 /*
106  * ADDI-DATA GmbH communication cards <info@addi-data.com>
107  */
108 static int addidata_apci7800_setup(struct serial_private *priv,
109                                 const struct pciserial_board *board,
110                                 struct uart_8250_port *port, int idx)
111 {
112         unsigned int bar = 0, offset = board->first_offset;
113         bar = FL_GET_BASE(board->flags);
114 
115         if (idx < 2) {
116                 offset += idx * board->uart_offset;
117         } else if ((idx >= 2) && (idx < 4)) {
118                 bar += 1;
119                 offset += ((idx - 2) * board->uart_offset);
120         } else if ((idx >= 4) && (idx < 6)) {
121                 bar += 2;
122                 offset += ((idx - 4) * board->uart_offset);
123         } else if (idx >= 6) {
124                 bar += 3;
125                 offset += ((idx - 6) * board->uart_offset);
126         }
127 
128         return setup_port(priv, port, bar, offset, board->reg_shift);
129 }
130 
131 /*
132  * AFAVLAB uses a different mixture of BARs and offsets
133  * Not that ugly ;) -- HW
134  */
135 static int
136 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
137               struct uart_8250_port *port, int idx)
138 {
139         unsigned int bar, offset = board->first_offset;
140 
141         bar = FL_GET_BASE(board->flags);
142         if (idx < 4)
143                 bar += idx;
144         else {
145                 bar = 4;
146                 offset += (idx - 4) * board->uart_offset;
147         }
148 
149         return setup_port(priv, port, bar, offset, board->reg_shift);
150 }
151 
152 /*
153  * HP's Remote Management Console.  The Diva chip came in several
154  * different versions.  N-class, L2000 and A500 have two Diva chips, each
155  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
156  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
157  * one Diva chip, but it has been expanded to 5 UARTs.
158  */
159 static int pci_hp_diva_init(struct pci_dev *dev)
160 {
161         int rc = 0;
162 
163         switch (dev->subsystem_device) {
164         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
165         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
166         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
167         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
168                 rc = 3;
169                 break;
170         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
171                 rc = 2;
172                 break;
173         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
174                 rc = 4;
175                 break;
176         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
177         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
178                 rc = 1;
179                 break;
180         }
181 
182         return rc;
183 }
184 
185 /*
186  * HP's Diva chip puts the 4th/5th serial port further out, and
187  * some serial ports are supposed to be hidden on certain models.
188  */
189 static int
190 pci_hp_diva_setup(struct serial_private *priv,
191                 const struct pciserial_board *board,
192                 struct uart_8250_port *port, int idx)
193 {
194         unsigned int offset = board->first_offset;
195         unsigned int bar = FL_GET_BASE(board->flags);
196 
197         switch (priv->dev->subsystem_device) {
198         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
199                 if (idx == 3)
200                         idx++;
201                 break;
202         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
203                 if (idx > 0)
204                         idx++;
205                 if (idx > 2)
206                         idx++;
207                 break;
208         }
209         if (idx > 2)
210                 offset = 0x18;
211 
212         offset += idx * board->uart_offset;
213 
214         return setup_port(priv, port, bar, offset, board->reg_shift);
215 }
216 
217 /*
218  * Added for EKF Intel i960 serial boards
219  */
220 static int pci_inteli960ni_init(struct pci_dev *dev)
221 {
222         u32 oldval;
223 
224         if (!(dev->subsystem_device & 0x1000))
225                 return -ENODEV;
226 
227         /* is firmware started? */
228         pci_read_config_dword(dev, 0x44, &oldval);
229         if (oldval == 0x00001000L) { /* RESET value */
230                 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
231                 return -ENODEV;
232         }
233         return 0;
234 }
235 
236 /*
237  * Some PCI serial cards using the PLX 9050 PCI interface chip require
238  * that the card interrupt be explicitly enabled or disabled.  This
239  * seems to be mainly needed on card using the PLX which also use I/O
240  * mapped memory.
241  */
242 static int pci_plx9050_init(struct pci_dev *dev)
243 {
244         u8 irq_config;
245         void __iomem *p;
246 
247         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
248                 moan_device("no memory in bar 0", dev);
249                 return 0;
250         }
251 
252         irq_config = 0x41;
253         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
254             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
255                 irq_config = 0x43;
256 
257         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
258             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
259                 /*
260                  * As the megawolf cards have the int pins active
261                  * high, and have 2 UART chips, both ints must be
262                  * enabled on the 9050. Also, the UARTS are set in
263                  * 16450 mode by default, so we have to enable the
264                  * 16C950 'enhanced' mode so that we can use the
265                  * deep FIFOs
266                  */
267                 irq_config = 0x5b;
268         /*
269          * enable/disable interrupts
270          */
271         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
272         if (p == NULL)
273                 return -ENOMEM;
274         writel(irq_config, p + 0x4c);
275 
276         /*
277          * Read the register back to ensure that it took effect.
278          */
279         readl(p + 0x4c);
280         iounmap(p);
281 
282         return 0;
283 }
284 
285 static void pci_plx9050_exit(struct pci_dev *dev)
286 {
287         u8 __iomem *p;
288 
289         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
290                 return;
291 
292         /*
293          * disable interrupts
294          */
295         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
296         if (p != NULL) {
297                 writel(0, p + 0x4c);
298 
299                 /*
300                  * Read the register back to ensure that it took effect.
301                  */
302                 readl(p + 0x4c);
303                 iounmap(p);
304         }
305 }
306 
307 #define NI8420_INT_ENABLE_REG   0x38
308 #define NI8420_INT_ENABLE_BIT   0x2000
309 
310 static void pci_ni8420_exit(struct pci_dev *dev)
311 {
312         void __iomem *p;
313         unsigned int bar = 0;
314 
315         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
316                 moan_device("no memory in bar", dev);
317                 return;
318         }
319 
320         p = pci_ioremap_bar(dev, bar);
321         if (p == NULL)
322                 return;
323 
324         /* Disable the CPU Interrupt */
325         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
326                p + NI8420_INT_ENABLE_REG);
327         iounmap(p);
328 }
329 
330 
331 /* MITE registers */
332 #define MITE_IOWBSR1    0xc4
333 #define MITE_IOWCR1     0xf4
334 #define MITE_LCIMR1     0x08
335 #define MITE_LCIMR2     0x10
336 
337 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
338 
339 static void pci_ni8430_exit(struct pci_dev *dev)
340 {
341         void __iomem *p;
342         unsigned int bar = 0;
343 
344         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
345                 moan_device("no memory in bar", dev);
346                 return;
347         }
348 
349         p = pci_ioremap_bar(dev, bar);
350         if (p == NULL)
351                 return;
352 
353         /* Disable the CPU Interrupt */
354         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
355         iounmap(p);
356 }
357 
358 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
359 static int
360 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
361                 struct uart_8250_port *port, int idx)
362 {
363         unsigned int bar, offset = board->first_offset;
364 
365         bar = 0;
366 
367         if (idx < 4) {
368                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
369                 offset += idx * board->uart_offset;
370         } else if (idx < 8) {
371                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
372                 offset += idx * board->uart_offset + 0xC00;
373         } else /* we have only 8 ports on PMC-OCTALPRO */
374                 return 1;
375 
376         return setup_port(priv, port, bar, offset, board->reg_shift);
377 }
378 
379 /*
380 * This does initialization for PMC OCTALPRO cards:
381 * maps the device memory, resets the UARTs (needed, bc
382 * if the module is removed and inserted again, the card
383 * is in the sleep mode) and enables global interrupt.
384 */
385 
386 /* global control register offset for SBS PMC-OctalPro */
387 #define OCT_REG_CR_OFF          0x500
388 
389 static int sbs_init(struct pci_dev *dev)
390 {
391         u8 __iomem *p;
392 
393         p = pci_ioremap_bar(dev, 0);
394 
395         if (p == NULL)
396                 return -ENOMEM;
397         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
398         writeb(0x10, p + OCT_REG_CR_OFF);
399         udelay(50);
400         writeb(0x0, p + OCT_REG_CR_OFF);
401 
402         /* Set bit-2 (INTENABLE) of Control Register */
403         writeb(0x4, p + OCT_REG_CR_OFF);
404         iounmap(p);
405 
406         return 0;
407 }
408 
409 /*
410  * Disables the global interrupt of PMC-OctalPro
411  */
412 
413 static void sbs_exit(struct pci_dev *dev)
414 {
415         u8 __iomem *p;
416 
417         p = pci_ioremap_bar(dev, 0);
418         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
419         if (p != NULL)
420                 writeb(0, p + OCT_REG_CR_OFF);
421         iounmap(p);
422 }
423 
424 /*
425  * SIIG serial cards have an PCI interface chip which also controls
426  * the UART clocking frequency. Each UART can be clocked independently
427  * (except cards equipped with 4 UARTs) and initial clocking settings
428  * are stored in the EEPROM chip. It can cause problems because this
429  * version of serial driver doesn't support differently clocked UART's
430  * on single PCI card. To prevent this, initialization functions set
431  * high frequency clocking for all UART's on given card. It is safe (I
432  * hope) because it doesn't touch EEPROM settings to prevent conflicts
433  * with other OSes (like M$ DOS).
434  *
435  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
436  *
437  * There is two family of SIIG serial cards with different PCI
438  * interface chip and different configuration methods:
439  *     - 10x cards have control registers in IO and/or memory space;
440  *     - 20x cards have control registers in standard PCI configuration space.
441  *
442  * Note: all 10x cards have PCI device ids 0x10..
443  *       all 20x cards have PCI device ids 0x20..
444  *
445  * There are also Quartet Serial cards which use Oxford Semiconductor
446  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
447  *
448  * Note: some SIIG cards are probed by the parport_serial object.
449  */
450 
451 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
452 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
453 
454 static int pci_siig10x_init(struct pci_dev *dev)
455 {
456         u16 data;
457         void __iomem *p;
458 
459         switch (dev->device & 0xfff8) {
460         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
461                 data = 0xffdf;
462                 break;
463         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
464                 data = 0xf7ff;
465                 break;
466         default:                        /* 1S1P, 4S */
467                 data = 0xfffb;
468                 break;
469         }
470 
471         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
472         if (p == NULL)
473                 return -ENOMEM;
474 
475         writew(readw(p + 0x28) & data, p + 0x28);
476         readw(p + 0x28);
477         iounmap(p);
478         return 0;
479 }
480 
481 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
482 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
483 
484 static int pci_siig20x_init(struct pci_dev *dev)
485 {
486         u8 data;
487 
488         /* Change clock frequency for the first UART. */
489         pci_read_config_byte(dev, 0x6f, &data);
490         pci_write_config_byte(dev, 0x6f, data & 0xef);
491 
492         /* If this card has 2 UART, we have to do the same with second UART. */
493         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
494             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
495                 pci_read_config_byte(dev, 0x73, &data);
496                 pci_write_config_byte(dev, 0x73, data & 0xef);
497         }
498         return 0;
499 }
500 
501 static int pci_siig_init(struct pci_dev *dev)
502 {
503         unsigned int type = dev->device & 0xff00;
504 
505         if (type == 0x1000)
506                 return pci_siig10x_init(dev);
507         else if (type == 0x2000)
508                 return pci_siig20x_init(dev);
509 
510         moan_device("Unknown SIIG card", dev);
511         return -ENODEV;
512 }
513 
514 static int pci_siig_setup(struct serial_private *priv,
515                           const struct pciserial_board *board,
516                           struct uart_8250_port *port, int idx)
517 {
518         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
519 
520         if (idx > 3) {
521                 bar = 4;
522                 offset = (idx - 4) * 8;
523         }
524 
525         return setup_port(priv, port, bar, offset, 0);
526 }
527 
528 /*
529  * Timedia has an explosion of boards, and to avoid the PCI table from
530  * growing *huge*, we use this function to collapse some 70 entries
531  * in the PCI table into one, for sanity's and compactness's sake.
532  */
533 static const unsigned short timedia_single_port[] = {
534         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
535 };
536 
537 static const unsigned short timedia_dual_port[] = {
538         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
539         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
540         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
541         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
542         0xD079, 0
543 };
544 
545 static const unsigned short timedia_quad_port[] = {
546         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
547         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
548         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
549         0xB157, 0
550 };
551 
552 static const unsigned short timedia_eight_port[] = {
553         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
554         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
555 };
556 
557 static const struct timedia_struct {
558         int num;
559         const unsigned short *ids;
560 } timedia_data[] = {
561         { 1, timedia_single_port },
562         { 2, timedia_dual_port },
563         { 4, timedia_quad_port },
564         { 8, timedia_eight_port }
565 };
566 
567 /*
568  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
569  * listing them individually, this driver merely grabs them all with
570  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
571  * and should be left free to be claimed by parport_serial instead.
572  */
573 static int pci_timedia_probe(struct pci_dev *dev)
574 {
575         /*
576          * Check the third digit of the subdevice ID
577          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
578          */
579         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
580                 dev_info(&dev->dev,
581                         "ignoring Timedia subdevice %04x for parport_serial\n",
582                         dev->subsystem_device);
583                 return -ENODEV;
584         }
585 
586         return 0;
587 }
588 
589 static int pci_timedia_init(struct pci_dev *dev)
590 {
591         const unsigned short *ids;
592         int i, j;
593 
594         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
595                 ids = timedia_data[i].ids;
596                 for (j = 0; ids[j]; j++)
597                         if (dev->subsystem_device == ids[j])
598                                 return timedia_data[i].num;
599         }
600         return 0;
601 }
602 
603 /*
604  * Timedia/SUNIX uses a mixture of BARs and offsets
605  * Ugh, this is ugly as all hell --- TYT
606  */
607 static int
608 pci_timedia_setup(struct serial_private *priv,
609                   const struct pciserial_board *board,
610                   struct uart_8250_port *port, int idx)
611 {
612         unsigned int bar = 0, offset = board->first_offset;
613 
614         switch (idx) {
615         case 0:
616                 bar = 0;
617                 break;
618         case 1:
619                 offset = board->uart_offset;
620                 bar = 0;
621                 break;
622         case 2:
623                 bar = 1;
624                 break;
625         case 3:
626                 offset = board->uart_offset;
627                 /* FALLTHROUGH */
628         case 4: /* BAR 2 */
629         case 5: /* BAR 3 */
630         case 6: /* BAR 4 */
631         case 7: /* BAR 5 */
632                 bar = idx - 2;
633         }
634 
635         return setup_port(priv, port, bar, offset, board->reg_shift);
636 }
637 
638 /*
639  * Some Titan cards are also a little weird
640  */
641 static int
642 titan_400l_800l_setup(struct serial_private *priv,
643                       const struct pciserial_board *board,
644                       struct uart_8250_port *port, int idx)
645 {
646         unsigned int bar, offset = board->first_offset;
647 
648         switch (idx) {
649         case 0:
650                 bar = 1;
651                 break;
652         case 1:
653                 bar = 2;
654                 break;
655         default:
656                 bar = 4;
657                 offset = (idx - 2) * board->uart_offset;
658         }
659 
660         return setup_port(priv, port, bar, offset, board->reg_shift);
661 }
662 
663 static int pci_xircom_init(struct pci_dev *dev)
664 {
665         msleep(100);
666         return 0;
667 }
668 
669 static int pci_ni8420_init(struct pci_dev *dev)
670 {
671         void __iomem *p;
672         unsigned int bar = 0;
673 
674         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
675                 moan_device("no memory in bar", dev);
676                 return 0;
677         }
678 
679         p = pci_ioremap_bar(dev, bar);
680         if (p == NULL)
681                 return -ENOMEM;
682 
683         /* Enable CPU Interrupt */
684         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
685                p + NI8420_INT_ENABLE_REG);
686 
687         iounmap(p);
688         return 0;
689 }
690 
691 #define MITE_IOWBSR1_WSIZE      0xa
692 #define MITE_IOWBSR1_WIN_OFFSET 0x800
693 #define MITE_IOWBSR1_WENAB      (1 << 7)
694 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
695 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
696 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
697 
698 static int pci_ni8430_init(struct pci_dev *dev)
699 {
700         void __iomem *p;
701         struct pci_bus_region region;
702         u32 device_window;
703         unsigned int bar = 0;
704 
705         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
706                 moan_device("no memory in bar", dev);
707                 return 0;
708         }
709 
710         p = pci_ioremap_bar(dev, bar);
711         if (p == NULL)
712                 return -ENOMEM;
713 
714         /*
715          * Set device window address and size in BAR0, while acknowledging that
716          * the resource structure may contain a translated address that differs
717          * from the address the device responds to.
718          */
719         pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
720         device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
721                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
722         writel(device_window, p + MITE_IOWBSR1);
723 
724         /* Set window access to go to RAMSEL IO address space */
725         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
726                p + MITE_IOWCR1);
727 
728         /* Enable IO Bus Interrupt 0 */
729         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
730 
731         /* Enable CPU Interrupt */
732         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
733 
734         iounmap(p);
735         return 0;
736 }
737 
738 /* UART Port Control Register */
739 #define NI8430_PORTCON  0x0f
740 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
741 
742 static int
743 pci_ni8430_setup(struct serial_private *priv,
744                  const struct pciserial_board *board,
745                  struct uart_8250_port *port, int idx)
746 {
747         struct pci_dev *dev = priv->dev;
748         void __iomem *p;
749         unsigned int bar, offset = board->first_offset;
750 
751         if (idx >= board->num_ports)
752                 return 1;
753 
754         bar = FL_GET_BASE(board->flags);
755         offset += idx * board->uart_offset;
756 
757         p = pci_ioremap_bar(dev, bar);
758         if (!p)
759                 return -ENOMEM;
760 
761         /* enable the transceiver */
762         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
763                p + offset + NI8430_PORTCON);
764 
765         iounmap(p);
766 
767         return setup_port(priv, port, bar, offset, board->reg_shift);
768 }
769 
770 static int pci_netmos_9900_setup(struct serial_private *priv,
771                                 const struct pciserial_board *board,
772                                 struct uart_8250_port *port, int idx)
773 {
774         unsigned int bar;
775 
776         if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
777             (priv->dev->subsystem_device & 0xff00) == 0x3000) {
778                 /* netmos apparently orders BARs by datasheet layout, so serial
779                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
780                  */
781                 bar = 3 * idx;
782 
783                 return setup_port(priv, port, bar, 0, board->reg_shift);
784         } else {
785                 return pci_default_setup(priv, board, port, idx);
786         }
787 }
788 
789 /* the 99xx series comes with a range of device IDs and a variety
790  * of capabilities:
791  *
792  * 9900 has varying capabilities and can cascade to sub-controllers
793  *   (cascading should be purely internal)
794  * 9904 is hardwired with 4 serial ports
795  * 9912 and 9922 are hardwired with 2 serial ports
796  */
797 static int pci_netmos_9900_numports(struct pci_dev *dev)
798 {
799         unsigned int c = dev->class;
800         unsigned int pi;
801         unsigned short sub_serports;
802 
803         pi = c & 0xff;
804 
805         if (pi == 2)
806                 return 1;
807 
808         if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
809                 /* two possibilities: 0x30ps encodes number of parallel and
810                  * serial ports, or 0x1000 indicates *something*. This is not
811                  * immediately obvious, since the 2s1p+4s configuration seems
812                  * to offer all functionality on functions 0..2, while still
813                  * advertising the same function 3 as the 4s+2s1p config.
814                  */
815                 sub_serports = dev->subsystem_device & 0xf;
816                 if (sub_serports > 0)
817                         return sub_serports;
818 
819                 dev_err(&dev->dev,
820                         "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
821                 return 0;
822         }
823 
824         moan_device("unknown NetMos/Mostech program interface", dev);
825         return 0;
826 }
827 
828 static int pci_netmos_init(struct pci_dev *dev)
829 {
830         /* subdevice 0x00PS means <P> parallel, <S> serial */
831         unsigned int num_serial = dev->subsystem_device & 0xf;
832 
833         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
834                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
835                 return 0;
836 
837         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
838                         dev->subsystem_device == 0x0299)
839                 return 0;
840 
841         switch (dev->device) { /* FALLTHROUGH on all */
842         case PCI_DEVICE_ID_NETMOS_9904:
843         case PCI_DEVICE_ID_NETMOS_9912:
844         case PCI_DEVICE_ID_NETMOS_9922:
845         case PCI_DEVICE_ID_NETMOS_9900:
846                 num_serial = pci_netmos_9900_numports(dev);
847                 break;
848 
849         default:
850                 break;
851         }
852 
853         if (num_serial == 0) {
854                 moan_device("unknown NetMos/Mostech device", dev);
855                 return -ENODEV;
856         }
857 
858         return num_serial;
859 }
860 
861 /*
862  * These chips are available with optionally one parallel port and up to
863  * two serial ports. Unfortunately they all have the same product id.
864  *
865  * Basic configuration is done over a region of 32 I/O ports. The base
866  * ioport is called INTA or INTC, depending on docs/other drivers.
867  *
868  * The region of the 32 I/O ports is configured in POSIO0R...
869  */
870 
871 /* registers */
872 #define ITE_887x_MISCR          0x9c
873 #define ITE_887x_INTCBAR        0x78
874 #define ITE_887x_UARTBAR        0x7c
875 #define ITE_887x_PS0BAR         0x10
876 #define ITE_887x_POSIO0         0x60
877 
878 /* I/O space size */
879 #define ITE_887x_IOSIZE         32
880 /* I/O space size (bits 26-24; 8 bytes = 011b) */
881 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
882 /* I/O space size (bits 26-24; 32 bytes = 101b) */
883 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
884 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
885 #define ITE_887x_POSIO_SPEED            (3 << 29)
886 /* enable IO_Space bit */
887 #define ITE_887x_POSIO_ENABLE           (1 << 31)
888 
889 static int pci_ite887x_init(struct pci_dev *dev)
890 {
891         /* inta_addr are the configuration addresses of the ITE */
892         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
893                                                         0x200, 0x280, 0 };
894         int ret, i, type;
895         struct resource *iobase = NULL;
896         u32 miscr, uartbar, ioport;
897 
898         /* search for the base-ioport */
899         i = 0;
900         while (inta_addr[i] && iobase == NULL) {
901                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
902                                                                 "ite887x");
903                 if (iobase != NULL) {
904                         /* write POSIO0R - speed | size | ioport */
905                         pci_write_config_dword(dev, ITE_887x_POSIO0,
906                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
907                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
908                         /* write INTCBAR - ioport */
909                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
910                                                                 inta_addr[i]);
911                         ret = inb(inta_addr[i]);
912                         if (ret != 0xff) {
913                                 /* ioport connected */
914                                 break;
915                         }
916                         release_region(iobase->start, ITE_887x_IOSIZE);
917                         iobase = NULL;
918                 }
919                 i++;
920         }
921 
922         if (!inta_addr[i]) {
923                 dev_err(&dev->dev, "ite887x: could not find iobase\n");
924                 return -ENODEV;
925         }
926 
927         /* start of undocumented type checking (see parport_pc.c) */
928         type = inb(iobase->start + 0x18) & 0x0f;
929 
930         switch (type) {
931         case 0x2:       /* ITE8871 (1P) */
932         case 0xa:       /* ITE8875 (1P) */
933                 ret = 0;
934                 break;
935         case 0xe:       /* ITE8872 (2S1P) */
936                 ret = 2;
937                 break;
938         case 0x6:       /* ITE8873 (1S) */
939                 ret = 1;
940                 break;
941         case 0x8:       /* ITE8874 (2S) */
942                 ret = 2;
943                 break;
944         default:
945                 moan_device("Unknown ITE887x", dev);
946                 ret = -ENODEV;
947         }
948 
949         /* configure all serial ports */
950         for (i = 0; i < ret; i++) {
951                 /* read the I/O port from the device */
952                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
953                                                                 &ioport);
954                 ioport &= 0x0000FF00;   /* the actual base address */
955                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
956                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
957                         ITE_887x_POSIO_IOSIZE_8 | ioport);
958 
959                 /* write the ioport to the UARTBAR */
960                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
961                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
962                 uartbar |= (ioport << (16 * i));        /* set the ioport */
963                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
964 
965                 /* get current config */
966                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
967                 /* disable interrupts (UARTx_Routing[3:0]) */
968                 miscr &= ~(0xf << (12 - 4 * i));
969                 /* activate the UART (UARTx_En) */
970                 miscr |= 1 << (23 - i);
971                 /* write new config with activated UART */
972                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
973         }
974 
975         if (ret <= 0) {
976                 /* the device has no UARTs if we get here */
977                 release_region(iobase->start, ITE_887x_IOSIZE);
978         }
979 
980         return ret;
981 }
982 
983 static void pci_ite887x_exit(struct pci_dev *dev)
984 {
985         u32 ioport;
986         /* the ioport is bit 0-15 in POSIO0R */
987         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
988         ioport &= 0xffff;
989         release_region(ioport, ITE_887x_IOSIZE);
990 }
991 
992 /*
993  * EndRun Technologies.
994  * Determine the number of ports available on the device.
995  */
996 #define PCI_VENDOR_ID_ENDRUN                    0x7401
997 #define PCI_DEVICE_ID_ENDRUN_1588       0xe100
998 
999 static int pci_endrun_init(struct pci_dev *dev)
1000 {
1001         u8 __iomem *p;
1002         unsigned long deviceID;
1003         unsigned int  number_uarts = 0;
1004 
1005         /* EndRun device is all 0xexxx */
1006         if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1007                 (dev->device & 0xf000) != 0xe000)
1008                 return 0;
1009 
1010         p = pci_iomap(dev, 0, 5);
1011         if (p == NULL)
1012                 return -ENOMEM;
1013 
1014         deviceID = ioread32(p);
1015         /* EndRun device */
1016         if (deviceID == 0x07000200) {
1017                 number_uarts = ioread8(p + 4);
1018                 dev_dbg(&dev->dev,
1019                         "%d ports detected on EndRun PCI Express device\n",
1020                         number_uarts);
1021         }
1022         pci_iounmap(dev, p);
1023         return number_uarts;
1024 }
1025 
1026 /*
1027  * Oxford Semiconductor Inc.
1028  * Check that device is part of the Tornado range of devices, then determine
1029  * the number of ports available on the device.
1030  */
1031 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1032 {
1033         u8 __iomem *p;
1034         unsigned long deviceID;
1035         unsigned int  number_uarts = 0;
1036 
1037         /* OxSemi Tornado devices are all 0xCxxx */
1038         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1039             (dev->device & 0xF000) != 0xC000)
1040                 return 0;
1041 
1042         p = pci_iomap(dev, 0, 5);
1043         if (p == NULL)
1044                 return -ENOMEM;
1045 
1046         deviceID = ioread32(p);
1047         /* Tornado device */
1048         if (deviceID == 0x07000200) {
1049                 number_uarts = ioread8(p + 4);
1050                 dev_dbg(&dev->dev,
1051                         "%d ports detected on Oxford PCI Express device\n",
1052                         number_uarts);
1053         }
1054         pci_iounmap(dev, p);
1055         return number_uarts;
1056 }
1057 
1058 static int pci_asix_setup(struct serial_private *priv,
1059                   const struct pciserial_board *board,
1060                   struct uart_8250_port *port, int idx)
1061 {
1062         port->bugs |= UART_BUG_PARITY;
1063         return pci_default_setup(priv, board, port, idx);
1064 }
1065 
1066 /* Quatech devices have their own extra interface features */
1067 
1068 struct quatech_feature {
1069         u16 devid;
1070         bool amcc;
1071 };
1072 
1073 #define QPCR_TEST_FOR1          0x3F
1074 #define QPCR_TEST_GET1          0x00
1075 #define QPCR_TEST_FOR2          0x40
1076 #define QPCR_TEST_GET2          0x40
1077 #define QPCR_TEST_FOR3          0x80
1078 #define QPCR_TEST_GET3          0x40
1079 #define QPCR_TEST_FOR4          0xC0
1080 #define QPCR_TEST_GET4          0x80
1081 
1082 #define QOPR_CLOCK_X1           0x0000
1083 #define QOPR_CLOCK_X2           0x0001
1084 #define QOPR_CLOCK_X4           0x0002
1085 #define QOPR_CLOCK_X8           0x0003
1086 #define QOPR_CLOCK_RATE_MASK    0x0003
1087 
1088 
1089 static struct quatech_feature quatech_cards[] = {
1090         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1091         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1092         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1093         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1094         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1095         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1096         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1097         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1098         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1099         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1100         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1101         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1102         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1103         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1104         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1105         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1106         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1107         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1108         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1109         { 0, }
1110 };
1111 
1112 static int pci_quatech_amcc(u16 devid)
1113 {
1114         struct quatech_feature *qf = &quatech_cards[0];
1115         while (qf->devid) {
1116                 if (qf->devid == devid)
1117                         return qf->amcc;
1118                 qf++;
1119         }
1120         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1121         return 0;
1122 };
1123 
1124 static int pci_quatech_rqopr(struct uart_8250_port *port)
1125 {
1126         unsigned long base = port->port.iobase;
1127         u8 LCR, val;
1128 
1129         LCR = inb(base + UART_LCR);
1130         outb(0xBF, base + UART_LCR);
1131         val = inb(base + UART_SCR);
1132         outb(LCR, base + UART_LCR);
1133         return val;
1134 }
1135 
1136 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1137 {
1138         unsigned long base = port->port.iobase;
1139         u8 LCR, val;
1140 
1141         LCR = inb(base + UART_LCR);
1142         outb(0xBF, base + UART_LCR);
1143         val = inb(base + UART_SCR);
1144         outb(qopr, base + UART_SCR);
1145         outb(LCR, base + UART_LCR);
1146 }
1147 
1148 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1149 {
1150         unsigned long base = port->port.iobase;
1151         u8 LCR, val, qmcr;
1152 
1153         LCR = inb(base + UART_LCR);
1154         outb(0xBF, base + UART_LCR);
1155         val = inb(base + UART_SCR);
1156         outb(val | 0x10, base + UART_SCR);
1157         qmcr = inb(base + UART_MCR);
1158         outb(val, base + UART_SCR);
1159         outb(LCR, base + UART_LCR);
1160 
1161         return qmcr;
1162 }
1163 
1164 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1165 {
1166         unsigned long base = port->port.iobase;
1167         u8 LCR, val;
1168 
1169         LCR = inb(base + UART_LCR);
1170         outb(0xBF, base + UART_LCR);
1171         val = inb(base + UART_SCR);
1172         outb(val | 0x10, base + UART_SCR);
1173         outb(qmcr, base + UART_MCR);
1174         outb(val, base + UART_SCR);
1175         outb(LCR, base + UART_LCR);
1176 }
1177 
1178 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1179 {
1180         unsigned long base = port->port.iobase;
1181         u8 LCR, val;
1182 
1183         LCR = inb(base + UART_LCR);
1184         outb(0xBF, base + UART_LCR);
1185         val = inb(base + UART_SCR);
1186         if (val & 0x20) {
1187                 outb(0x80, UART_LCR);
1188                 if (!(inb(UART_SCR) & 0x20)) {
1189                         outb(LCR, base + UART_LCR);
1190                         return 1;
1191                 }
1192         }
1193         return 0;
1194 }
1195 
1196 static int pci_quatech_test(struct uart_8250_port *port)
1197 {
1198         u8 reg, qopr;
1199 
1200         qopr = pci_quatech_rqopr(port);
1201         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1202         reg = pci_quatech_rqopr(port) & 0xC0;
1203         if (reg != QPCR_TEST_GET1)
1204                 return -EINVAL;
1205         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1206         reg = pci_quatech_rqopr(port) & 0xC0;
1207         if (reg != QPCR_TEST_GET2)
1208                 return -EINVAL;
1209         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1210         reg = pci_quatech_rqopr(port) & 0xC0;
1211         if (reg != QPCR_TEST_GET3)
1212                 return -EINVAL;
1213         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1214         reg = pci_quatech_rqopr(port) & 0xC0;
1215         if (reg != QPCR_TEST_GET4)
1216                 return -EINVAL;
1217 
1218         pci_quatech_wqopr(port, qopr);
1219         return 0;
1220 }
1221 
1222 static int pci_quatech_clock(struct uart_8250_port *port)
1223 {
1224         u8 qopr, reg, set;
1225         unsigned long clock;
1226 
1227         if (pci_quatech_test(port) < 0)
1228                 return 1843200;
1229 
1230         qopr = pci_quatech_rqopr(port);
1231 
1232         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1233         reg = pci_quatech_rqopr(port);
1234         if (reg & QOPR_CLOCK_X8) {
1235                 clock = 1843200;
1236                 goto out;
1237         }
1238         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1239         reg = pci_quatech_rqopr(port);
1240         if (!(reg & QOPR_CLOCK_X8)) {
1241                 clock = 1843200;
1242                 goto out;
1243         }
1244         reg &= QOPR_CLOCK_X8;
1245         if (reg == QOPR_CLOCK_X2) {
1246                 clock =  3685400;
1247                 set = QOPR_CLOCK_X2;
1248         } else if (reg == QOPR_CLOCK_X4) {
1249                 clock = 7372800;
1250                 set = QOPR_CLOCK_X4;
1251         } else if (reg == QOPR_CLOCK_X8) {
1252                 clock = 14745600;
1253                 set = QOPR_CLOCK_X8;
1254         } else {
1255                 clock = 1843200;
1256                 set = QOPR_CLOCK_X1;
1257         }
1258         qopr &= ~QOPR_CLOCK_RATE_MASK;
1259         qopr |= set;
1260 
1261 out:
1262         pci_quatech_wqopr(port, qopr);
1263         return clock;
1264 }
1265 
1266 static int pci_quatech_rs422(struct uart_8250_port *port)
1267 {
1268         u8 qmcr;
1269         int rs422 = 0;
1270 
1271         if (!pci_quatech_has_qmcr(port))
1272                 return 0;
1273         qmcr = pci_quatech_rqmcr(port);
1274         pci_quatech_wqmcr(port, 0xFF);
1275         if (pci_quatech_rqmcr(port))
1276                 rs422 = 1;
1277         pci_quatech_wqmcr(port, qmcr);
1278         return rs422;
1279 }
1280 
1281 static int pci_quatech_init(struct pci_dev *dev)
1282 {
1283         if (pci_quatech_amcc(dev->device)) {
1284                 unsigned long base = pci_resource_start(dev, 0);
1285                 if (base) {
1286                         u32 tmp;
1287 
1288                         outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1289                         tmp = inl(base + 0x3c);
1290                         outl(tmp | 0x01000000, base + 0x3c);
1291                         outl(tmp &= ~0x01000000, base + 0x3c);
1292                 }
1293         }
1294         return 0;
1295 }
1296 
1297 static int pci_quatech_setup(struct serial_private *priv,
1298                   const struct pciserial_board *board,
1299                   struct uart_8250_port *port, int idx)
1300 {
1301         /* Needed by pci_quatech calls below */
1302         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1303         /* Set up the clocking */
1304         port->port.uartclk = pci_quatech_clock(port);
1305         /* For now just warn about RS422 */
1306         if (pci_quatech_rs422(port))
1307                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1308         return pci_default_setup(priv, board, port, idx);
1309 }
1310 
1311 static void pci_quatech_exit(struct pci_dev *dev)
1312 {
1313 }
1314 
1315 static int pci_default_setup(struct serial_private *priv,
1316                   const struct pciserial_board *board,
1317                   struct uart_8250_port *port, int idx)
1318 {
1319         unsigned int bar, offset = board->first_offset, maxnr;
1320 
1321         bar = FL_GET_BASE(board->flags);
1322         if (board->flags & FL_BASE_BARS)
1323                 bar += idx;
1324         else
1325                 offset += idx * board->uart_offset;
1326 
1327         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1328                 (board->reg_shift + 3);
1329 
1330         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1331                 return 1;
1332 
1333         return setup_port(priv, port, bar, offset, board->reg_shift);
1334 }
1335 
1336 static int
1337 ce4100_serial_setup(struct serial_private *priv,
1338                   const struct pciserial_board *board,
1339                   struct uart_8250_port *port, int idx)
1340 {
1341         int ret;
1342 
1343         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1344         port->port.iotype = UPIO_MEM32;
1345         port->port.type = PORT_XSCALE;
1346         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1347         port->port.regshift = 2;
1348 
1349         return ret;
1350 }
1351 
1352 #define PCI_DEVICE_ID_INTEL_BYT_UART1   0x0f0a
1353 #define PCI_DEVICE_ID_INTEL_BYT_UART2   0x0f0c
1354 
1355 #define PCI_DEVICE_ID_INTEL_BSW_UART1   0x228a
1356 #define PCI_DEVICE_ID_INTEL_BSW_UART2   0x228c
1357 
1358 #define PCI_DEVICE_ID_INTEL_BDW_UART1   0x9ce3
1359 #define PCI_DEVICE_ID_INTEL_BDW_UART2   0x9ce4
1360 
1361 #define BYT_PRV_CLK                     0x800
1362 #define BYT_PRV_CLK_EN                  (1 << 0)
1363 #define BYT_PRV_CLK_M_VAL_SHIFT         1
1364 #define BYT_PRV_CLK_N_VAL_SHIFT         16
1365 #define BYT_PRV_CLK_UPDATE              (1 << 31)
1366 
1367 #define BYT_TX_OVF_INT                  0x820
1368 #define BYT_TX_OVF_INT_MASK             (1 << 1)
1369 
1370 static void
1371 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1372                 struct ktermios *old)
1373 {
1374         unsigned int baud = tty_termios_baud_rate(termios);
1375         unsigned long fref = 100000000, fuart = baud * 16;
1376         unsigned long w = BIT(15) - 1;
1377         unsigned long m, n;
1378         u32 reg;
1379 
1380         /* Gracefully handle the B0 case: fall back to B9600 */
1381         fuart = fuart ? fuart : 9600 * 16;
1382 
1383         /* Get Fuart closer to Fref */
1384         fuart *= rounddown_pow_of_two(fref / fuart);
1385 
1386         /*
1387          * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1388          * dividers must be adjusted.
1389          *
1390          * uartclk = (m / n) * 100 MHz, where m <= n
1391          */
1392         rational_best_approximation(fuart, fref, w, w, &m, &n);
1393         p->uartclk = fuart;
1394 
1395         /* Reset the clock */
1396         reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1397         writel(reg, p->membase + BYT_PRV_CLK);
1398         reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1399         writel(reg, p->membase + BYT_PRV_CLK);
1400 
1401         p->status &= ~UPSTAT_AUTOCTS;
1402         if (termios->c_cflag & CRTSCTS)
1403                 p->status |= UPSTAT_AUTOCTS;
1404 
1405         serial8250_do_set_termios(p, termios, old);
1406 }
1407 
1408 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1409 {
1410         struct dw_dma_slave *dws = param;
1411 
1412         if (dws->dma_dev != chan->device->dev)
1413                 return false;
1414 
1415         chan->private = dws;
1416         return true;
1417 }
1418 
1419 static unsigned int
1420 byt_get_mctrl(struct uart_port *port)
1421 {
1422         unsigned int ret = serial8250_do_get_mctrl(port);
1423 
1424         /* Force DCD and DSR signals to permanently be reported as active. */
1425         ret |= TIOCM_CAR | TIOCM_DSR;
1426 
1427         return ret;
1428 }
1429 
1430 static int
1431 byt_serial_setup(struct serial_private *priv,
1432                  const struct pciserial_board *board,
1433                  struct uart_8250_port *port, int idx)
1434 {
1435         struct pci_dev *pdev = priv->dev;
1436         struct device *dev = port->port.dev;
1437         struct uart_8250_dma *dma;
1438         struct dw_dma_slave *tx_param, *rx_param;
1439         struct pci_dev *dma_dev;
1440         int ret;
1441 
1442         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1443         if (!dma)
1444                 return -ENOMEM;
1445 
1446         tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1447         if (!tx_param)
1448                 return -ENOMEM;
1449 
1450         rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1451         if (!rx_param)
1452                 return -ENOMEM;
1453 
1454         switch (pdev->device) {
1455         case PCI_DEVICE_ID_INTEL_BYT_UART1:
1456         case PCI_DEVICE_ID_INTEL_BSW_UART1:
1457         case PCI_DEVICE_ID_INTEL_BDW_UART1:
1458                 rx_param->src_id = 3;
1459                 tx_param->dst_id = 2;
1460                 break;
1461         case PCI_DEVICE_ID_INTEL_BYT_UART2:
1462         case PCI_DEVICE_ID_INTEL_BSW_UART2:
1463         case PCI_DEVICE_ID_INTEL_BDW_UART2:
1464                 rx_param->src_id = 5;
1465                 tx_param->dst_id = 4;
1466                 break;
1467         default:
1468                 return -EINVAL;
1469         }
1470 
1471         rx_param->m_master = 0;
1472         rx_param->p_master = 1;
1473 
1474         dma->rxconf.src_maxburst = 16;
1475 
1476         tx_param->m_master = 0;
1477         tx_param->p_master = 1;
1478 
1479         dma->txconf.dst_maxburst = 16;
1480 
1481         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1482         rx_param->dma_dev = &dma_dev->dev;
1483         tx_param->dma_dev = &dma_dev->dev;
1484 
1485         dma->fn = byt_dma_filter;
1486         dma->rx_param = rx_param;
1487         dma->tx_param = tx_param;
1488 
1489         ret = pci_default_setup(priv, board, port, idx);
1490         port->port.iotype = UPIO_MEM;
1491         port->port.type = PORT_16550A;
1492         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1493         port->port.set_termios = byt_set_termios;
1494         port->port.get_mctrl = byt_get_mctrl;
1495         port->port.fifosize = 64;
1496         port->tx_loadsz = 64;
1497         port->dma = dma;
1498         port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1499 
1500         /* Disable Tx counter interrupts */
1501         writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1502 
1503         return ret;
1504 }
1505 
1506 static int
1507 pci_omegapci_setup(struct serial_private *priv,
1508                       const struct pciserial_board *board,
1509                       struct uart_8250_port *port, int idx)
1510 {
1511         return setup_port(priv, port, 2, idx * 8, 0);
1512 }
1513 
1514 static int
1515 pci_brcm_trumanage_setup(struct serial_private *priv,
1516                          const struct pciserial_board *board,
1517                          struct uart_8250_port *port, int idx)
1518 {
1519         int ret = pci_default_setup(priv, board, port, idx);
1520 
1521         port->port.type = PORT_BRCM_TRUMANAGE;
1522         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1523         return ret;
1524 }
1525 
1526 /* RTS will control by MCR if this bit is 0 */
1527 #define FINTEK_RTS_CONTROL_BY_HW        BIT(4)
1528 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1529 #define FINTEK_RTS_INVERT               BIT(5)
1530 
1531 /* We should do proper H/W transceiver setting before change to RS485 mode */
1532 static int pci_fintek_rs485_config(struct uart_port *port,
1533                                struct serial_rs485 *rs485)
1534 {
1535         struct pci_dev *pci_dev = to_pci_dev(port->dev);
1536         u8 setting;
1537         u8 *index = (u8 *) port->private_data;
1538 
1539         pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1540 
1541         if (!rs485)
1542                 rs485 = &port->rs485;
1543         else if (rs485->flags & SER_RS485_ENABLED)
1544                 memset(rs485->padding, 0, sizeof(rs485->padding));
1545         else
1546                 memset(rs485, 0, sizeof(*rs485));
1547 
1548         /* F81504/508/512 not support RTS delay before or after send */
1549         rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1550 
1551         if (rs485->flags & SER_RS485_ENABLED) {
1552                 /* Enable RTS H/W control mode */
1553                 setting |= FINTEK_RTS_CONTROL_BY_HW;
1554 
1555                 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1556                         /* RTS driving high on TX */
1557                         setting &= ~FINTEK_RTS_INVERT;
1558                 } else {
1559                         /* RTS driving low on TX */
1560                         setting |= FINTEK_RTS_INVERT;
1561                 }
1562 
1563                 rs485->delay_rts_after_send = 0;
1564                 rs485->delay_rts_before_send = 0;
1565         } else {
1566                 /* Disable RTS H/W control mode */
1567                 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1568         }
1569 
1570         pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1571 
1572         if (rs485 != &port->rs485)
1573                 port->rs485 = *rs485;
1574 
1575         return 0;
1576 }
1577 
1578 static int pci_fintek_setup(struct serial_private *priv,
1579                             const struct pciserial_board *board,
1580                             struct uart_8250_port *port, int idx)
1581 {
1582         struct pci_dev *pdev = priv->dev;
1583         u8 *data;
1584         u8 config_base;
1585         u16 iobase;
1586 
1587         config_base = 0x40 + 0x08 * idx;
1588 
1589         /* Get the io address from configuration space */
1590         pci_read_config_word(pdev, config_base + 4, &iobase);
1591 
1592         dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1593 
1594         port->port.iotype = UPIO_PORT;
1595         port->port.iobase = iobase;
1596         port->port.rs485_config = pci_fintek_rs485_config;
1597 
1598         data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1599         if (!data)
1600                 return -ENOMEM;
1601 
1602         /* preserve index in PCI configuration space */
1603         *data = idx;
1604         port->port.private_data = data;
1605 
1606         return 0;
1607 }
1608 
1609 static int pci_fintek_init(struct pci_dev *dev)
1610 {
1611         unsigned long iobase;
1612         u32 max_port, i;
1613         u32 bar_data[3];
1614         u8 config_base;
1615         struct serial_private *priv = pci_get_drvdata(dev);
1616         struct uart_8250_port *port;
1617 
1618         switch (dev->device) {
1619         case 0x1104: /* 4 ports */
1620         case 0x1108: /* 8 ports */
1621                 max_port = dev->device & 0xff;
1622                 break;
1623         case 0x1112: /* 12 ports */
1624                 max_port = 12;
1625                 break;
1626         default:
1627                 return -EINVAL;
1628         }
1629 
1630         /* Get the io address dispatch from the BIOS */
1631         pci_read_config_dword(dev, 0x24, &bar_data[0]);
1632         pci_read_config_dword(dev, 0x20, &bar_data[1]);
1633         pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1634 
1635         for (i = 0; i < max_port; ++i) {
1636                 /* UART0 configuration offset start from 0x40 */
1637                 config_base = 0x40 + 0x08 * i;
1638 
1639                 /* Calculate Real IO Port */
1640                 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1641 
1642                 /* Enable UART I/O port */
1643                 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1644 
1645                 /* Select 128-byte FIFO and 8x FIFO threshold */
1646                 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1647 
1648                 /* LSB UART */
1649                 pci_write_config_byte(dev, config_base + 0x04,
1650                                 (u8)(iobase & 0xff));
1651 
1652                 /* MSB UART */
1653                 pci_write_config_byte(dev, config_base + 0x05,
1654                                 (u8)((iobase & 0xff00) >> 8));
1655 
1656                 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1657 
1658                 if (priv) {
1659                         /* re-apply RS232/485 mode when
1660                          * pciserial_resume_ports()
1661                          */
1662                         port = serial8250_get_port(priv->line[i]);
1663                         pci_fintek_rs485_config(&port->port, NULL);
1664                 } else {
1665                         /* First init without port data
1666                          * force init to RS232 Mode
1667                          */
1668                         pci_write_config_byte(dev, config_base + 0x07, 0x01);
1669                 }
1670         }
1671 
1672         return max_port;
1673 }
1674 
1675 static int skip_tx_en_setup(struct serial_private *priv,
1676                         const struct pciserial_board *board,
1677                         struct uart_8250_port *port, int idx)
1678 {
1679         port->port.flags |= UPF_NO_TXEN_TEST;
1680         dev_dbg(&priv->dev->dev,
1681                 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1682                 priv->dev->vendor, priv->dev->device,
1683                 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1684 
1685         return pci_default_setup(priv, board, port, idx);
1686 }
1687 
1688 static void kt_handle_break(struct uart_port *p)
1689 {
1690         struct uart_8250_port *up = up_to_u8250p(p);
1691         /*
1692          * On receipt of a BI, serial device in Intel ME (Intel
1693          * management engine) needs to have its fifos cleared for sane
1694          * SOL (Serial Over Lan) output.
1695          */
1696         serial8250_clear_and_reinit_fifos(up);
1697 }
1698 
1699 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1700 {
1701         struct uart_8250_port *up = up_to_u8250p(p);
1702         unsigned int val;
1703 
1704         /*
1705          * When the Intel ME (management engine) gets reset its serial
1706          * port registers could return 0 momentarily.  Functions like
1707          * serial8250_console_write, read and save the IER, perform
1708          * some operation and then restore it.  In order to avoid
1709          * setting IER register inadvertently to 0, if the value read
1710          * is 0, double check with ier value in uart_8250_port and use
1711          * that instead.  up->ier should be the same value as what is
1712          * currently configured.
1713          */
1714         val = inb(p->iobase + offset);
1715         if (offset == UART_IER) {
1716                 if (val == 0)
1717                         val = up->ier;
1718         }
1719         return val;
1720 }
1721 
1722 static int kt_serial_setup(struct serial_private *priv,
1723                            const struct pciserial_board *board,
1724                            struct uart_8250_port *port, int idx)
1725 {
1726         port->port.flags |= UPF_BUG_THRE;
1727         port->port.serial_in = kt_serial_in;
1728         port->port.handle_break = kt_handle_break;
1729         return skip_tx_en_setup(priv, board, port, idx);
1730 }
1731 
1732 static int pci_eg20t_init(struct pci_dev *dev)
1733 {
1734 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1735         return -ENODEV;
1736 #else
1737         return 0;
1738 #endif
1739 }
1740 
1741 #define PCI_DEVICE_ID_EXAR_XR17V4358    0x4358
1742 #define PCI_DEVICE_ID_EXAR_XR17V8358    0x8358
1743 
1744 static int
1745 pci_xr17c154_setup(struct serial_private *priv,
1746                   const struct pciserial_board *board,
1747                   struct uart_8250_port *port, int idx)
1748 {
1749         port->port.flags |= UPF_EXAR_EFR;
1750         return pci_default_setup(priv, board, port, idx);
1751 }
1752 
1753 static inline int
1754 xr17v35x_has_slave(struct serial_private *priv)
1755 {
1756         const int dev_id = priv->dev->device;
1757 
1758         return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1759                 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1760 }
1761 
1762 static int
1763 pci_xr17v35x_setup(struct serial_private *priv,
1764                   const struct pciserial_board *board,
1765                   struct uart_8250_port *port, int idx)
1766 {
1767         u8 __iomem *p;
1768 
1769         p = pci_ioremap_bar(priv->dev, 0);
1770         if (p == NULL)
1771                 return -ENOMEM;
1772 
1773         port->port.flags |= UPF_EXAR_EFR;
1774 
1775         /*
1776          * Setup the uart clock for the devices on expansion slot to
1777          * half the clock speed of the main chip (which is 125MHz)
1778          */
1779         if (xr17v35x_has_slave(priv) && idx >= 8)
1780                 port->port.uartclk = (7812500 * 16 / 2);
1781 
1782         /*
1783          * Setup Multipurpose Input/Output pins.
1784          */
1785         if (idx == 0) {
1786                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1787                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1788                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1789                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1790                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1791                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1792                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1793                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1794                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1795                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1796                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1797                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1798         }
1799         writeb(0x00, p + UART_EXAR_8XMODE);
1800         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1801         writeb(128, p + UART_EXAR_TXTRG);
1802         writeb(128, p + UART_EXAR_RXTRG);
1803         iounmap(p);
1804 
1805         return pci_default_setup(priv, board, port, idx);
1806 }
1807 
1808 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1809 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1810 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1811 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1812 
1813 static int
1814 pci_fastcom335_setup(struct serial_private *priv,
1815                   const struct pciserial_board *board,
1816                   struct uart_8250_port *port, int idx)
1817 {
1818         u8 __iomem *p;
1819 
1820         p = pci_ioremap_bar(priv->dev, 0);
1821         if (p == NULL)
1822                 return -ENOMEM;
1823 
1824         port->port.flags |= UPF_EXAR_EFR;
1825 
1826         /*
1827          * Setup Multipurpose Input/Output pins.
1828          */
1829         if (idx == 0) {
1830                 switch (priv->dev->device) {
1831                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1832                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1833                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1834                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1835                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1836                         break;
1837                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1838                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1839                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1840                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1841                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1842                         break;
1843                 }
1844                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1845                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1846                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1847         }
1848         writeb(0x00, p + UART_EXAR_8XMODE);
1849         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1850         writeb(32, p + UART_EXAR_TXTRG);
1851         writeb(32, p + UART_EXAR_RXTRG);
1852         iounmap(p);
1853 
1854         return pci_default_setup(priv, board, port, idx);
1855 }
1856 
1857 static int
1858 pci_wch_ch353_setup(struct serial_private *priv,
1859                     const struct pciserial_board *board,
1860                     struct uart_8250_port *port, int idx)
1861 {
1862         port->port.flags |= UPF_FIXED_TYPE;
1863         port->port.type = PORT_16550A;
1864         return pci_default_setup(priv, board, port, idx);
1865 }
1866 
1867 static int
1868 pci_wch_ch38x_setup(struct serial_private *priv,
1869                     const struct pciserial_board *board,
1870                     struct uart_8250_port *port, int idx)
1871 {
1872         port->port.flags |= UPF_FIXED_TYPE;
1873         port->port.type = PORT_16850;
1874         return pci_default_setup(priv, board, port, idx);
1875 }
1876 
1877 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1878 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1879 #define PCI_DEVICE_ID_OCTPRO            0x0001
1880 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1881 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1882 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1883 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1884 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1885 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1886 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1887 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1888 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1889 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1890 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1891 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1892 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1893 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1894 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1895 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1896 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1897 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1898 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1899 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1900 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1901 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1902 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1903 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
1904 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1905 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1906 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1907 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1908 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1909 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1910 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1911 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1912 #define PCI_VENDOR_ID_WCH               0x4348
1913 #define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
1914 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1915 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1916 #define PCI_DEVICE_ID_WCH_CH353_1S1P    0x5053
1917 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1918 #define PCI_VENDOR_ID_AGESTAR           0x5372
1919 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1920 #define PCI_VENDOR_ID_ASIX              0x9710
1921 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1922 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1923 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1924 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1925 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1926 #define PCI_DEVICE_ID_INTEL_QRK_UART    0x0936
1927 
1928 #define PCI_VENDOR_ID_SUNIX             0x1fd4
1929 #define PCI_DEVICE_ID_SUNIX_1999        0x1999
1930 
1931 #define PCIE_VENDOR_ID_WCH              0x1c00
1932 #define PCIE_DEVICE_ID_WCH_CH382_2S1P   0x3250
1933 #define PCIE_DEVICE_ID_WCH_CH384_4S     0x3470
1934 #define PCIE_DEVICE_ID_WCH_CH382_2S     0x3253
1935 
1936 #define PCI_VENDOR_ID_PERICOM                   0x12D8
1937 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951        0x7951
1938 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952        0x7952
1939 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954        0x7954
1940 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958        0x7958
1941 
1942 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1943 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1944 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1945 
1946 /*
1947  * Master list of serial port init/setup/exit quirks.
1948  * This does not describe the general nature of the port.
1949  * (ie, baud base, number and location of ports, etc)
1950  *
1951  * This list is ordered alphabetically by vendor then device.
1952  * Specific entries must come before more generic entries.
1953  */
1954 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1955         /*
1956         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1957         */
1958         {
1959                 .vendor         = PCI_VENDOR_ID_AMCC,
1960                 .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1961                 .subvendor      = PCI_ANY_ID,
1962                 .subdevice      = PCI_ANY_ID,
1963                 .setup          = addidata_apci7800_setup,
1964         },
1965         /*
1966          * AFAVLAB cards - these may be called via parport_serial
1967          *  It is not clear whether this applies to all products.
1968          */
1969         {
1970                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1971                 .device         = PCI_ANY_ID,
1972                 .subvendor      = PCI_ANY_ID,
1973                 .subdevice      = PCI_ANY_ID,
1974                 .setup          = afavlab_setup,
1975         },
1976         /*
1977          * HP Diva
1978          */
1979         {
1980                 .vendor         = PCI_VENDOR_ID_HP,
1981                 .device         = PCI_DEVICE_ID_HP_DIVA,
1982                 .subvendor      = PCI_ANY_ID,
1983                 .subdevice      = PCI_ANY_ID,
1984                 .init           = pci_hp_diva_init,
1985                 .setup          = pci_hp_diva_setup,
1986         },
1987         /*
1988          * Intel
1989          */
1990         {
1991                 .vendor         = PCI_VENDOR_ID_INTEL,
1992                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1993                 .subvendor      = 0xe4bf,
1994                 .subdevice      = PCI_ANY_ID,
1995                 .init           = pci_inteli960ni_init,
1996                 .setup          = pci_default_setup,
1997         },
1998         {
1999                 .vendor         = PCI_VENDOR_ID_INTEL,
2000                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
2001                 .subvendor      = PCI_ANY_ID,
2002                 .subdevice      = PCI_ANY_ID,
2003                 .setup          = skip_tx_en_setup,
2004         },
2005         {
2006                 .vendor         = PCI_VENDOR_ID_INTEL,
2007                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
2008                 .subvendor      = PCI_ANY_ID,
2009                 .subdevice      = PCI_ANY_ID,
2010                 .setup          = skip_tx_en_setup,
2011         },
2012         {
2013                 .vendor         = PCI_VENDOR_ID_INTEL,
2014                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
2015                 .subvendor      = PCI_ANY_ID,
2016                 .subdevice      = PCI_ANY_ID,
2017                 .setup          = skip_tx_en_setup,
2018         },
2019         {
2020                 .vendor         = PCI_VENDOR_ID_INTEL,
2021                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
2022                 .subvendor      = PCI_ANY_ID,
2023                 .subdevice      = PCI_ANY_ID,
2024                 .setup          = ce4100_serial_setup,
2025         },
2026         {
2027                 .vendor         = PCI_VENDOR_ID_INTEL,
2028                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2029                 .subvendor      = PCI_ANY_ID,
2030                 .subdevice      = PCI_ANY_ID,
2031                 .setup          = kt_serial_setup,
2032         },
2033         {
2034                 .vendor         = PCI_VENDOR_ID_INTEL,
2035                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART1,
2036                 .subvendor      = PCI_ANY_ID,
2037                 .subdevice      = PCI_ANY_ID,
2038                 .setup          = byt_serial_setup,
2039         },
2040         {
2041                 .vendor         = PCI_VENDOR_ID_INTEL,
2042                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART2,
2043                 .subvendor      = PCI_ANY_ID,
2044                 .subdevice      = PCI_ANY_ID,
2045                 .setup          = byt_serial_setup,
2046         },
2047         {
2048                 .vendor         = PCI_VENDOR_ID_INTEL,
2049                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART1,
2050                 .subvendor      = PCI_ANY_ID,
2051                 .subdevice      = PCI_ANY_ID,
2052                 .setup          = byt_serial_setup,
2053         },
2054         {
2055                 .vendor         = PCI_VENDOR_ID_INTEL,
2056                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART2,
2057                 .subvendor      = PCI_ANY_ID,
2058                 .subdevice      = PCI_ANY_ID,
2059                 .setup          = byt_serial_setup,
2060         },
2061         {
2062                 .vendor         = PCI_VENDOR_ID_INTEL,
2063                 .device         = PCI_DEVICE_ID_INTEL_BDW_UART1,
2064                 .subvendor      = PCI_ANY_ID,
2065                 .subdevice      = PCI_ANY_ID,
2066                 .setup          = byt_serial_setup,
2067         },
2068         {
2069                 .vendor         = PCI_VENDOR_ID_INTEL,
2070                 .device         = PCI_DEVICE_ID_INTEL_BDW_UART2,
2071                 .subvendor      = PCI_ANY_ID,
2072                 .subdevice      = PCI_ANY_ID,
2073                 .setup          = byt_serial_setup,
2074         },
2075         /*
2076          * ITE
2077          */
2078         {
2079                 .vendor         = PCI_VENDOR_ID_ITE,
2080                 .device         = PCI_DEVICE_ID_ITE_8872,
2081                 .subvendor      = PCI_ANY_ID,
2082                 .subdevice      = PCI_ANY_ID,
2083                 .init           = pci_ite887x_init,
2084                 .setup          = pci_default_setup,
2085                 .exit           = pci_ite887x_exit,
2086         },
2087         /*
2088          * National Instruments
2089          */
2090         {
2091                 .vendor         = PCI_VENDOR_ID_NI,
2092                 .device         = PCI_DEVICE_ID_NI_PCI23216,
2093                 .subvendor      = PCI_ANY_ID,
2094                 .subdevice      = PCI_ANY_ID,
2095                 .init           = pci_ni8420_init,
2096                 .setup          = pci_default_setup,
2097                 .exit           = pci_ni8420_exit,
2098         },
2099         {
2100                 .vendor         = PCI_VENDOR_ID_NI,
2101                 .device         = PCI_DEVICE_ID_NI_PCI2328,
2102                 .subvendor      = PCI_ANY_ID,
2103                 .subdevice      = PCI_ANY_ID,
2104                 .init           = pci_ni8420_init,
2105                 .setup          = pci_default_setup,
2106                 .exit           = pci_ni8420_exit,
2107         },
2108         {
2109                 .vendor         = PCI_VENDOR_ID_NI,
2110                 .device         = PCI_DEVICE_ID_NI_PCI2324,
2111                 .subvendor      = PCI_ANY_ID,
2112                 .subdevice      = PCI_ANY_ID,
2113                 .init           = pci_ni8420_init,
2114                 .setup          = pci_default_setup,
2115                 .exit           = pci_ni8420_exit,
2116         },
2117         {
2118                 .vendor         = PCI_VENDOR_ID_NI,
2119                 .device         = PCI_DEVICE_ID_NI_PCI2322,
2120                 .subvendor      = PCI_ANY_ID,
2121                 .subdevice      = PCI_ANY_ID,
2122                 .init           = pci_ni8420_init,
2123                 .setup          = pci_default_setup,
2124                 .exit           = pci_ni8420_exit,
2125         },
2126         {
2127                 .vendor         = PCI_VENDOR_ID_NI,
2128                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
2129                 .subvendor      = PCI_ANY_ID,
2130                 .subdevice      = PCI_ANY_ID,
2131                 .init           = pci_ni8420_init,
2132                 .setup          = pci_default_setup,
2133                 .exit           = pci_ni8420_exit,
2134         },
2135         {
2136                 .vendor         = PCI_VENDOR_ID_NI,
2137                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
2138                 .subvendor      = PCI_ANY_ID,
2139                 .subdevice      = PCI_ANY_ID,
2140                 .init           = pci_ni8420_init,
2141                 .setup          = pci_default_setup,
2142                 .exit           = pci_ni8420_exit,
2143         },
2144         {
2145                 .vendor         = PCI_VENDOR_ID_NI,
2146                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
2147                 .subvendor      = PCI_ANY_ID,
2148                 .subdevice      = PCI_ANY_ID,
2149                 .init           = pci_ni8420_init,
2150                 .setup          = pci_default_setup,
2151                 .exit           = pci_ni8420_exit,
2152         },
2153         {
2154                 .vendor         = PCI_VENDOR_ID_NI,
2155                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
2156                 .subvendor      = PCI_ANY_ID,
2157                 .subdevice      = PCI_ANY_ID,
2158                 .init           = pci_ni8420_init,
2159                 .setup          = pci_default_setup,
2160                 .exit           = pci_ni8420_exit,
2161         },
2162         {
2163                 .vendor         = PCI_VENDOR_ID_NI,
2164                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
2165                 .subvendor      = PCI_ANY_ID,
2166                 .subdevice      = PCI_ANY_ID,
2167                 .init           = pci_ni8420_init,
2168                 .setup          = pci_default_setup,
2169                 .exit           = pci_ni8420_exit,
2170         },
2171         {
2172                 .vendor         = PCI_VENDOR_ID_NI,
2173                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
2174                 .subvendor      = PCI_ANY_ID,
2175                 .subdevice      = PCI_ANY_ID,
2176                 .init           = pci_ni8420_init,
2177                 .setup          = pci_default_setup,
2178                 .exit           = pci_ni8420_exit,
2179         },
2180         {
2181                 .vendor         = PCI_VENDOR_ID_NI,
2182                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
2183                 .subvendor      = PCI_ANY_ID,
2184                 .subdevice      = PCI_ANY_ID,
2185                 .init           = pci_ni8420_init,
2186                 .setup          = pci_default_setup,
2187                 .exit           = pci_ni8420_exit,
2188         },
2189         {
2190                 .vendor         = PCI_VENDOR_ID_NI,
2191                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
2192                 .subvendor      = PCI_ANY_ID,
2193                 .subdevice      = PCI_ANY_ID,
2194                 .init           = pci_ni8420_init,
2195                 .setup          = pci_default_setup,
2196                 .exit           = pci_ni8420_exit,
2197         },
2198         {
2199                 .vendor         = PCI_VENDOR_ID_NI,
2200                 .device         = PCI_ANY_ID,
2201                 .subvendor      = PCI_ANY_ID,
2202                 .subdevice      = PCI_ANY_ID,
2203                 .init           = pci_ni8430_init,
2204                 .setup          = pci_ni8430_setup,
2205                 .exit           = pci_ni8430_exit,
2206         },
2207         /* Quatech */
2208         {
2209                 .vendor         = PCI_VENDOR_ID_QUATECH,
2210                 .device         = PCI_ANY_ID,
2211                 .subvendor      = PCI_ANY_ID,
2212                 .subdevice      = PCI_ANY_ID,
2213                 .init           = pci_quatech_init,
2214                 .setup          = pci_quatech_setup,
2215                 .exit           = pci_quatech_exit,
2216         },
2217         /*
2218          * Panacom
2219          */
2220         {
2221                 .vendor         = PCI_VENDOR_ID_PANACOM,
2222                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2223                 .subvendor      = PCI_ANY_ID,
2224                 .subdevice      = PCI_ANY_ID,
2225                 .init           = pci_plx9050_init,
2226                 .setup          = pci_default_setup,
2227                 .exit           = pci_plx9050_exit,
2228         },
2229         {
2230                 .vendor         = PCI_VENDOR_ID_PANACOM,
2231                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2232                 .subvendor      = PCI_ANY_ID,
2233                 .subdevice      = PCI_ANY_ID,
2234                 .init           = pci_plx9050_init,
2235                 .setup          = pci_default_setup,
2236                 .exit           = pci_plx9050_exit,
2237         },
2238         /*
2239          * PLX
2240          */
2241         {
2242                 .vendor         = PCI_VENDOR_ID_PLX,
2243                 .device         = PCI_DEVICE_ID_PLX_9050,
2244                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2245                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2246                 .init           = pci_plx9050_init,
2247                 .setup          = pci_default_setup,
2248                 .exit           = pci_plx9050_exit,
2249         },
2250         {
2251                 .vendor         = PCI_VENDOR_ID_PLX,
2252                 .device         = PCI_DEVICE_ID_PLX_9050,
2253                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2254                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2255                 .init           = pci_plx9050_init,
2256                 .setup          = pci_default_setup,
2257                 .exit           = pci_plx9050_exit,
2258         },
2259         {
2260                 .vendor         = PCI_VENDOR_ID_PLX,
2261                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2262                 .subvendor      = PCI_VENDOR_ID_PLX,
2263                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2264                 .init           = pci_plx9050_init,
2265                 .setup          = pci_default_setup,
2266                 .exit           = pci_plx9050_exit,
2267         },
2268         /*
2269          * SBS Technologies, Inc., PMC-OCTALPRO 232
2270          */
2271         {
2272                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2273                 .device         = PCI_DEVICE_ID_OCTPRO,
2274                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2275                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2276                 .init           = sbs_init,
2277                 .setup          = sbs_setup,
2278                 .exit           = sbs_exit,
2279         },
2280         /*
2281          * SBS Technologies, Inc., PMC-OCTALPRO 422
2282          */
2283         {
2284                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2285                 .device         = PCI_DEVICE_ID_OCTPRO,
2286                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2287                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2288                 .init           = sbs_init,
2289                 .setup          = sbs_setup,
2290                 .exit           = sbs_exit,
2291         },
2292         /*
2293          * SBS Technologies, Inc., P-Octal 232
2294          */
2295         {
2296                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2297                 .device         = PCI_DEVICE_ID_OCTPRO,
2298                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2299                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2300                 .init           = sbs_init,
2301                 .setup          = sbs_setup,
2302                 .exit           = sbs_exit,
2303         },
2304         /*
2305          * SBS Technologies, Inc., P-Octal 422
2306          */
2307         {
2308                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2309                 .device         = PCI_DEVICE_ID_OCTPRO,
2310                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2311                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2312                 .init           = sbs_init,
2313                 .setup          = sbs_setup,
2314                 .exit           = sbs_exit,
2315         },
2316         /*
2317          * SIIG cards - these may be called via parport_serial
2318          */
2319         {
2320                 .vendor         = PCI_VENDOR_ID_SIIG,
2321                 .device         = PCI_ANY_ID,
2322                 .subvendor      = PCI_ANY_ID,
2323                 .subdevice      = PCI_ANY_ID,
2324                 .init           = pci_siig_init,
2325                 .setup          = pci_siig_setup,
2326         },
2327         /*
2328          * Titan cards
2329          */
2330         {
2331                 .vendor         = PCI_VENDOR_ID_TITAN,
2332                 .device         = PCI_DEVICE_ID_TITAN_400L,
2333                 .subvendor      = PCI_ANY_ID,
2334                 .subdevice      = PCI_ANY_ID,
2335                 .setup          = titan_400l_800l_setup,
2336         },
2337         {
2338                 .vendor         = PCI_VENDOR_ID_TITAN,
2339                 .device         = PCI_DEVICE_ID_TITAN_800L,
2340                 .subvendor      = PCI_ANY_ID,
2341                 .subdevice      = PCI_ANY_ID,
2342                 .setup          = titan_400l_800l_setup,
2343         },
2344         /*
2345          * Timedia cards
2346          */
2347         {
2348                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2349                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2350                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2351                 .subdevice      = PCI_ANY_ID,
2352                 .probe          = pci_timedia_probe,
2353                 .init           = pci_timedia_init,
2354                 .setup          = pci_timedia_setup,
2355         },
2356         {
2357                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2358                 .device         = PCI_ANY_ID,
2359                 .subvendor      = PCI_ANY_ID,
2360                 .subdevice      = PCI_ANY_ID,
2361                 .setup          = pci_timedia_setup,
2362         },
2363         /*
2364          * SUNIX (Timedia) cards
2365          * Do not "probe" for these cards as there is at least one combination
2366          * card that should be handled by parport_pc that doesn't match the
2367          * rule in pci_timedia_probe.
2368          * It is part number is MIO5079A but its subdevice ID is 0x0102.
2369          * There are some boards with part number SER5037AL that report
2370          * subdevice ID 0x0002.
2371          */
2372         {
2373                 .vendor         = PCI_VENDOR_ID_SUNIX,
2374                 .device         = PCI_DEVICE_ID_SUNIX_1999,
2375                 .subvendor      = PCI_VENDOR_ID_SUNIX,
2376                 .subdevice      = PCI_ANY_ID,
2377                 .init           = pci_timedia_init,
2378                 .setup          = pci_timedia_setup,
2379         },
2380         /*
2381          * Exar cards
2382          */
2383         {
2384                 .vendor = PCI_VENDOR_ID_EXAR,
2385                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2386                 .subvendor      = PCI_ANY_ID,
2387                 .subdevice      = PCI_ANY_ID,
2388                 .setup          = pci_xr17c154_setup,
2389         },
2390         {
2391                 .vendor = PCI_VENDOR_ID_EXAR,
2392                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2393                 .subvendor      = PCI_ANY_ID,
2394                 .subdevice      = PCI_ANY_ID,
2395                 .setup          = pci_xr17c154_setup,
2396         },
2397         {
2398                 .vendor = PCI_VENDOR_ID_EXAR,
2399                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2400                 .subvendor      = PCI_ANY_ID,
2401                 .subdevice      = PCI_ANY_ID,
2402                 .setup          = pci_xr17c154_setup,
2403         },
2404         {
2405                 .vendor = PCI_VENDOR_ID_EXAR,
2406                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2407                 .subvendor      = PCI_ANY_ID,
2408                 .subdevice      = PCI_ANY_ID,
2409                 .setup          = pci_xr17v35x_setup,
2410         },
2411         {
2412                 .vendor = PCI_VENDOR_ID_EXAR,
2413                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2414                 .subvendor      = PCI_ANY_ID,
2415                 .subdevice      = PCI_ANY_ID,
2416                 .setup          = pci_xr17v35x_setup,
2417         },
2418         {
2419                 .vendor = PCI_VENDOR_ID_EXAR,
2420                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2421                 .subvendor      = PCI_ANY_ID,
2422                 .subdevice      = PCI_ANY_ID,
2423                 .setup          = pci_xr17v35x_setup,
2424         },
2425         {
2426                 .vendor = PCI_VENDOR_ID_EXAR,
2427                 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2428                 .subvendor      = PCI_ANY_ID,
2429                 .subdevice      = PCI_ANY_ID,
2430                 .setup          = pci_xr17v35x_setup,
2431         },
2432         {
2433                 .vendor = PCI_VENDOR_ID_EXAR,
2434                 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2435                 .subvendor      = PCI_ANY_ID,
2436                 .subdevice      = PCI_ANY_ID,
2437                 .setup          = pci_xr17v35x_setup,
2438         },
2439         /*
2440          * Xircom cards
2441          */
2442         {
2443                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2444                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2445                 .subvendor      = PCI_ANY_ID,
2446                 .subdevice      = PCI_ANY_ID,
2447                 .init           = pci_xircom_init,
2448                 .setup          = pci_default_setup,
2449         },
2450         /*
2451          * Netmos cards - these may be called via parport_serial
2452          */
2453         {
2454                 .vendor         = PCI_VENDOR_ID_NETMOS,
2455                 .device         = PCI_ANY_ID,
2456                 .subvendor      = PCI_ANY_ID,
2457                 .subdevice      = PCI_ANY_ID,
2458                 .init           = pci_netmos_init,
2459                 .setup          = pci_netmos_9900_setup,
2460         },
2461         /*
2462          * EndRun Technologies
2463         */
2464         {
2465                 .vendor         = PCI_VENDOR_ID_ENDRUN,
2466                 .device         = PCI_ANY_ID,
2467                 .subvendor      = PCI_ANY_ID,
2468                 .subdevice      = PCI_ANY_ID,
2469                 .init           = pci_endrun_init,
2470                 .setup          = pci_default_setup,
2471         },
2472         /*
2473          * For Oxford Semiconductor Tornado based devices
2474          */
2475         {
2476                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2477                 .device         = PCI_ANY_ID,
2478                 .subvendor      = PCI_ANY_ID,
2479                 .subdevice      = PCI_ANY_ID,
2480                 .init           = pci_oxsemi_tornado_init,
2481                 .setup          = pci_default_setup,
2482         },
2483         {
2484                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2485                 .device         = PCI_ANY_ID,
2486                 .subvendor      = PCI_ANY_ID,
2487                 .subdevice      = PCI_ANY_ID,
2488                 .init           = pci_oxsemi_tornado_init,
2489                 .setup          = pci_default_setup,
2490         },
2491         {
2492                 .vendor         = PCI_VENDOR_ID_DIGI,
2493                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2494                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2495                 .subdevice              = PCI_ANY_ID,
2496                 .init                   = pci_oxsemi_tornado_init,
2497                 .setup          = pci_default_setup,
2498         },
2499         {
2500                 .vendor         = PCI_VENDOR_ID_INTEL,
2501                 .device         = 0x8811,
2502                 .subvendor      = PCI_ANY_ID,
2503                 .subdevice      = PCI_ANY_ID,
2504                 .init           = pci_eg20t_init,
2505                 .setup          = pci_default_setup,
2506         },
2507         {
2508                 .vendor         = PCI_VENDOR_ID_INTEL,
2509                 .device         = 0x8812,
2510                 .subvendor      = PCI_ANY_ID,
2511                 .subdevice      = PCI_ANY_ID,
2512                 .init           = pci_eg20t_init,
2513                 .setup          = pci_default_setup,
2514         },
2515         {
2516                 .vendor         = PCI_VENDOR_ID_INTEL,
2517                 .device         = 0x8813,
2518                 .subvendor      = PCI_ANY_ID,
2519                 .subdevice      = PCI_ANY_ID,
2520                 .init           = pci_eg20t_init,
2521                 .setup          = pci_default_setup,
2522         },
2523         {
2524                 .vendor         = PCI_VENDOR_ID_INTEL,
2525                 .device         = 0x8814,
2526                 .subvendor      = PCI_ANY_ID,
2527                 .subdevice      = PCI_ANY_ID,
2528                 .init           = pci_eg20t_init,
2529                 .setup          = pci_default_setup,
2530         },
2531         {
2532                 .vendor         = 0x10DB,
2533                 .device         = 0x8027,
2534                 .subvendor      = PCI_ANY_ID,
2535                 .subdevice      = PCI_ANY_ID,
2536                 .init           = pci_eg20t_init,
2537                 .setup          = pci_default_setup,
2538         },
2539         {
2540                 .vendor         = 0x10DB,
2541                 .device         = 0x8028,
2542                 .subvendor      = PCI_ANY_ID,
2543                 .subdevice      = PCI_ANY_ID,
2544                 .init           = pci_eg20t_init,
2545                 .setup          = pci_default_setup,
2546         },
2547         {
2548                 .vendor         = 0x10DB,
2549                 .device         = 0x8029,
2550                 .subvendor      = PCI_ANY_ID,
2551                 .subdevice      = PCI_ANY_ID,
2552                 .init           = pci_eg20t_init,
2553                 .setup          = pci_default_setup,
2554         },
2555         {
2556                 .vendor         = 0x10DB,
2557                 .device         = 0x800C,
2558                 .subvendor      = PCI_ANY_ID,
2559                 .subdevice      = PCI_ANY_ID,
2560                 .init           = pci_eg20t_init,
2561                 .setup          = pci_default_setup,
2562         },
2563         {
2564                 .vendor         = 0x10DB,
2565                 .device         = 0x800D,
2566                 .subvendor      = PCI_ANY_ID,
2567                 .subdevice      = PCI_ANY_ID,
2568                 .init           = pci_eg20t_init,
2569                 .setup          = pci_default_setup,
2570         },
2571         /*
2572          * Cronyx Omega PCI (PLX-chip based)
2573          */
2574         {
2575                 .vendor         = PCI_VENDOR_ID_PLX,
2576                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2577                 .subvendor      = PCI_ANY_ID,
2578                 .subdevice      = PCI_ANY_ID,
2579                 .setup          = pci_omegapci_setup,
2580         },
2581         /* WCH CH353 1S1P card (16550 clone) */
2582         {
2583                 .vendor         = PCI_VENDOR_ID_WCH,
2584                 .device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2585                 .subvendor      = PCI_ANY_ID,
2586                 .subdevice      = PCI_ANY_ID,
2587                 .setup          = pci_wch_ch353_setup,
2588         },
2589         /* WCH CH353 2S1P card (16550 clone) */
2590         {
2591                 .vendor         = PCI_VENDOR_ID_WCH,
2592                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2593                 .subvendor      = PCI_ANY_ID,
2594                 .subdevice      = PCI_ANY_ID,
2595                 .setup          = pci_wch_ch353_setup,
2596         },
2597         /* WCH CH353 4S card (16550 clone) */
2598         {
2599                 .vendor         = PCI_VENDOR_ID_WCH,
2600                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2601                 .subvendor      = PCI_ANY_ID,
2602                 .subdevice      = PCI_ANY_ID,
2603                 .setup          = pci_wch_ch353_setup,
2604         },
2605         /* WCH CH353 2S1PF card (16550 clone) */
2606         {
2607                 .vendor         = PCI_VENDOR_ID_WCH,
2608                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2609                 .subvendor      = PCI_ANY_ID,
2610                 .subdevice      = PCI_ANY_ID,
2611                 .setup          = pci_wch_ch353_setup,
2612         },
2613         /* WCH CH352 2S card (16550 clone) */
2614         {
2615                 .vendor         = PCI_VENDOR_ID_WCH,
2616                 .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2617                 .subvendor      = PCI_ANY_ID,
2618                 .subdevice      = PCI_ANY_ID,
2619                 .setup          = pci_wch_ch353_setup,
2620         },
2621         /* WCH CH382 2S card (16850 clone) */
2622         {
2623                 .vendor         = PCIE_VENDOR_ID_WCH,
2624                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S,
2625                 .subvendor      = PCI_ANY_ID,
2626                 .subdevice      = PCI_ANY_ID,
2627                 .setup          = pci_wch_ch38x_setup,
2628         },
2629         /* WCH CH382 2S1P card (16850 clone) */
2630         {
2631                 .vendor         = PCIE_VENDOR_ID_WCH,
2632                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2633                 .subvendor      = PCI_ANY_ID,
2634                 .subdevice      = PCI_ANY_ID,
2635                 .setup          = pci_wch_ch38x_setup,
2636         },
2637         /* WCH CH384 4S card (16850 clone) */
2638         {
2639                 .vendor         = PCIE_VENDOR_ID_WCH,
2640                 .device         = PCIE_DEVICE_ID_WCH_CH384_4S,
2641                 .subvendor      = PCI_ANY_ID,
2642                 .subdevice      = PCI_ANY_ID,
2643                 .setup          = pci_wch_ch38x_setup,
2644         },
2645         /*
2646          * ASIX devices with FIFO bug
2647          */
2648         {
2649                 .vendor         = PCI_VENDOR_ID_ASIX,
2650                 .device         = PCI_ANY_ID,
2651                 .subvendor      = PCI_ANY_ID,
2652                 .subdevice      = PCI_ANY_ID,
2653                 .setup          = pci_asix_setup,
2654         },
2655         /*
2656          * Commtech, Inc. Fastcom adapters
2657          *
2658          */
2659         {
2660                 .vendor = PCI_VENDOR_ID_COMMTECH,
2661                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2662                 .subvendor      = PCI_ANY_ID,
2663                 .subdevice      = PCI_ANY_ID,
2664                 .setup          = pci_fastcom335_setup,
2665         },
2666         {
2667                 .vendor = PCI_VENDOR_ID_COMMTECH,
2668                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2669                 .subvendor      = PCI_ANY_ID,
2670                 .subdevice      = PCI_ANY_ID,
2671                 .setup          = pci_fastcom335_setup,
2672         },
2673         {
2674                 .vendor = PCI_VENDOR_ID_COMMTECH,
2675                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2676                 .subvendor      = PCI_ANY_ID,
2677                 .subdevice      = PCI_ANY_ID,
2678                 .setup          = pci_fastcom335_setup,
2679         },
2680         {
2681                 .vendor = PCI_VENDOR_ID_COMMTECH,
2682                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2683                 .subvendor      = PCI_ANY_ID,
2684                 .subdevice      = PCI_ANY_ID,
2685                 .setup          = pci_fastcom335_setup,
2686         },
2687         {
2688                 .vendor = PCI_VENDOR_ID_COMMTECH,
2689                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2690                 .subvendor      = PCI_ANY_ID,
2691                 .subdevice      = PCI_ANY_ID,
2692                 .setup          = pci_xr17v35x_setup,
2693         },
2694         {
2695                 .vendor = PCI_VENDOR_ID_COMMTECH,
2696                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2697                 .subvendor      = PCI_ANY_ID,
2698                 .subdevice      = PCI_ANY_ID,
2699                 .setup          = pci_xr17v35x_setup,
2700         },
2701         {
2702                 .vendor = PCI_VENDOR_ID_COMMTECH,
2703                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2704                 .subvendor      = PCI_ANY_ID,
2705                 .subdevice      = PCI_ANY_ID,
2706                 .setup          = pci_xr17v35x_setup,
2707         },
2708         /*
2709          * Broadcom TruManage (NetXtreme)
2710          */
2711         {
2712                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2713                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2714                 .subvendor      = PCI_ANY_ID,
2715                 .subdevice      = PCI_ANY_ID,
2716                 .setup          = pci_brcm_trumanage_setup,
2717         },
2718         {
2719                 .vendor         = 0x1c29,
2720                 .device         = 0x1104,
2721                 .subvendor      = PCI_ANY_ID,
2722                 .subdevice      = PCI_ANY_ID,
2723                 .setup          = pci_fintek_setup,
2724                 .init           = pci_fintek_init,
2725         },
2726         {
2727                 .vendor         = 0x1c29,
2728                 .device         = 0x1108,
2729                 .subvendor      = PCI_ANY_ID,
2730                 .subdevice      = PCI_ANY_ID,
2731                 .setup          = pci_fintek_setup,
2732                 .init           = pci_fintek_init,
2733         },
2734         {
2735                 .vendor         = 0x1c29,
2736                 .device         = 0x1112,
2737                 .subvendor      = PCI_ANY_ID,
2738                 .subdevice      = PCI_ANY_ID,
2739                 .setup          = pci_fintek_setup,
2740                 .init           = pci_fintek_init,
2741         },
2742 
2743         /*
2744          * Default "match everything" terminator entry
2745          */
2746         {
2747                 .vendor         = PCI_ANY_ID,
2748                 .device         = PCI_ANY_ID,
2749                 .subvendor      = PCI_ANY_ID,
2750                 .subdevice      = PCI_ANY_ID,
2751                 .setup          = pci_default_setup,
2752         }
2753 };
2754 
2755 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2756 {
2757         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2758 }
2759 
2760 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2761 {
2762         struct pci_serial_quirk *quirk;
2763 
2764         for (quirk = pci_serial_quirks; ; quirk++)
2765                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2766                     quirk_id_matches(quirk->device, dev->device) &&
2767                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2768                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2769                         break;
2770         return quirk;
2771 }
2772 
2773 static inline int get_pci_irq(struct pci_dev *dev,
2774                                 const struct pciserial_board *board)
2775 {
2776         if (board->flags & FL_NOIRQ)
2777                 return 0;
2778         else
2779                 return dev->irq;
2780 }
2781 
2782 /*
2783  * This is the configuration table for all of the PCI serial boards
2784  * which we support.  It is directly indexed by the pci_board_num_t enum
2785  * value, which is encoded in the pci_device_id PCI probe table's
2786  * driver_data member.
2787  *
2788  * The makeup of these names are:
2789  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2790  *
2791  *  bn          = PCI BAR number
2792  *  bt          = Index using PCI BARs
2793  *  n           = number of serial ports
2794  *  baud        = baud rate
2795  *  offsetinhex = offset for each sequential port (in hex)
2796  *
2797  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2798  *
2799  * Please note: in theory if n = 1, _bt infix should make no difference.
2800  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2801  */
2802 enum pci_board_num_t {
2803         pbn_default = 0,
2804 
2805         pbn_b0_1_115200,
2806         pbn_b0_2_115200,
2807         pbn_b0_4_115200,
2808         pbn_b0_5_115200,
2809         pbn_b0_8_115200,
2810 
2811         pbn_b0_1_921600,
2812         pbn_b0_2_921600,
2813         pbn_b0_4_921600,
2814 
2815         pbn_b0_2_1130000,
2816 
2817         pbn_b0_4_1152000,
2818 
2819         pbn_b0_2_1152000_200,
2820         pbn_b0_4_1152000_200,
2821         pbn_b0_8_1152000_200,
2822 
2823         pbn_b0_2_1843200,
2824         pbn_b0_4_1843200,
2825 
2826         pbn_b0_2_1843200_200,
2827         pbn_b0_4_1843200_200,
2828         pbn_b0_8_1843200_200,
2829 
2830         pbn_b0_1_4000000,
2831 
2832         pbn_b0_bt_1_115200,
2833         pbn_b0_bt_2_115200,
2834         pbn_b0_bt_4_115200,
2835         pbn_b0_bt_8_115200,
2836 
2837         pbn_b0_bt_1_460800,
2838         pbn_b0_bt_2_460800,
2839         pbn_b0_bt_4_460800,
2840 
2841         pbn_b0_bt_1_921600,
2842         pbn_b0_bt_2_921600,
2843         pbn_b0_bt_4_921600,
2844         pbn_b0_bt_8_921600,
2845 
2846         pbn_b1_1_115200,
2847         pbn_b1_2_115200,
2848         pbn_b1_4_115200,
2849         pbn_b1_8_115200,
2850         pbn_b1_16_115200,
2851 
2852         pbn_b1_1_921600,
2853         pbn_b1_2_921600,
2854         pbn_b1_4_921600,
2855         pbn_b1_8_921600,
2856 
2857         pbn_b1_2_1250000,
2858 
2859         pbn_b1_bt_1_115200,
2860         pbn_b1_bt_2_115200,
2861         pbn_b1_bt_4_115200,
2862 
2863         pbn_b1_bt_2_921600,
2864 
2865         pbn_b1_1_1382400,
2866         pbn_b1_2_1382400,
2867         pbn_b1_4_1382400,
2868         pbn_b1_8_1382400,
2869 
2870         pbn_b2_1_115200,
2871         pbn_b2_2_115200,
2872         pbn_b2_4_115200,
2873         pbn_b2_8_115200,
2874 
2875         pbn_b2_1_460800,
2876         pbn_b2_4_460800,
2877         pbn_b2_8_460800,
2878         pbn_b2_16_460800,
2879 
2880         pbn_b2_1_921600,
2881         pbn_b2_4_921600,
2882         pbn_b2_8_921600,
2883 
2884         pbn_b2_8_1152000,
2885 
2886         pbn_b2_bt_1_115200,
2887         pbn_b2_bt_2_115200,
2888         pbn_b2_bt_4_115200,
2889 
2890         pbn_b2_bt_2_921600,
2891         pbn_b2_bt_4_921600,
2892 
2893         pbn_b3_2_115200,
2894         pbn_b3_4_115200,
2895         pbn_b3_8_115200,
2896 
2897         pbn_b4_bt_2_921600,
2898         pbn_b4_bt_4_921600,
2899         pbn_b4_bt_8_921600,
2900 
2901         /*
2902          * Board-specific versions.
2903          */
2904         pbn_panacom,
2905         pbn_panacom2,
2906         pbn_panacom4,
2907         pbn_plx_romulus,
2908         pbn_endrun_2_4000000,
2909         pbn_oxsemi,
2910         pbn_oxsemi_1_4000000,
2911         pbn_oxsemi_2_4000000,
2912         pbn_oxsemi_4_4000000,
2913         pbn_oxsemi_8_4000000,
2914         pbn_intel_i960,
2915         pbn_sgi_ioc3,
2916         pbn_computone_4,
2917         pbn_computone_6,
2918         pbn_computone_8,
2919         pbn_sbsxrsio,
2920         pbn_exar_XR17C152,
2921         pbn_exar_XR17C154,
2922         pbn_exar_XR17C158,
2923         pbn_exar_XR17V352,
2924         pbn_exar_XR17V354,
2925         pbn_exar_XR17V358,
2926         pbn_exar_XR17V4358,
2927         pbn_exar_XR17V8358,
2928         pbn_exar_ibm_saturn,
2929         pbn_pasemi_1682M,
2930         pbn_ni8430_2,
2931         pbn_ni8430_4,
2932         pbn_ni8430_8,
2933         pbn_ni8430_16,
2934         pbn_ADDIDATA_PCIe_1_3906250,
2935         pbn_ADDIDATA_PCIe_2_3906250,
2936         pbn_ADDIDATA_PCIe_4_3906250,
2937         pbn_ADDIDATA_PCIe_8_3906250,
2938         pbn_ce4100_1_115200,
2939         pbn_byt,
2940         pbn_qrk,
2941         pbn_omegapci,
2942         pbn_NETMOS9900_2s_115200,
2943         pbn_brcm_trumanage,
2944         pbn_fintek_4,
2945         pbn_fintek_8,
2946         pbn_fintek_12,
2947         pbn_wch382_2,
2948         pbn_wch384_4,
2949         pbn_pericom_PI7C9X7951,
2950         pbn_pericom_PI7C9X7952,
2951         pbn_pericom_PI7C9X7954,
2952         pbn_pericom_PI7C9X7958,
2953 };
2954 
2955 /*
2956  * uart_offset - the space between channels
2957  * reg_shift   - describes how the UART registers are mapped
2958  *               to PCI memory by the card.
2959  * For example IER register on SBS, Inc. PMC-OctPro is located at
2960  * offset 0x10 from the UART base, while UART_IER is defined as 1
2961  * in include/linux/serial_reg.h,
2962  * see first lines of serial_in() and serial_out() in 8250.c
2963 */
2964 
2965 static struct pciserial_board pci_boards[] = {
2966         [pbn_default] = {
2967                 .flags          = FL_BASE0,
2968                 .num_ports      = 1,
2969                 .base_baud      = 115200,
2970                 .uart_offset    = 8,
2971         },
2972         [pbn_b0_1_115200] = {
2973                 .flags          = FL_BASE0,
2974                 .num_ports      = 1,
2975                 .base_baud      = 115200,
2976                 .uart_offset    = 8,
2977         },
2978         [pbn_b0_2_115200] = {
2979                 .flags          = FL_BASE0,
2980                 .num_ports      = 2,
2981                 .base_baud      = 115200,
2982                 .uart_offset    = 8,
2983         },
2984         [pbn_b0_4_115200] = {
2985                 .flags          = FL_BASE0,
2986                 .num_ports      = 4,
2987                 .base_baud      = 115200,
2988                 .uart_offset    = 8,
2989         },
2990         [pbn_b0_5_115200] = {
2991                 .flags          = FL_BASE0,
2992                 .num_ports      = 5,
2993                 .base_baud      = 115200,
2994                 .uart_offset    = 8,
2995         },
2996         [pbn_b0_8_115200] = {
2997                 .flags          = FL_BASE0,
2998                 .num_ports      = 8,
2999                 .base_baud      = 115200,
3000                 .uart_offset    = 8,
3001         },
3002         [pbn_b0_1_921600] = {
3003                 .flags          = FL_BASE0,
3004                 .num_ports      = 1,
3005                 .base_baud      = 921600,
3006                 .uart_offset    = 8,
3007         },
3008         [pbn_b0_2_921600] = {
3009                 .flags          = FL_BASE0,
3010                 .num_ports      = 2,
3011                 .base_baud      = 921600,
3012                 .uart_offset    = 8,
3013         },
3014         [pbn_b0_4_921600] = {
3015                 .flags          = FL_BASE0,
3016                 .num_ports      = 4,
3017                 .base_baud      = 921600,
3018                 .uart_offset    = 8,
3019         },
3020 
3021         [pbn_b0_2_1130000] = {
3022                 .flags          = FL_BASE0,
3023                 .num_ports      = 2,
3024                 .base_baud      = 1130000,
3025                 .uart_offset    = 8,
3026         },
3027 
3028         [pbn_b0_4_1152000] = {
3029                 .flags          = FL_BASE0,
3030                 .num_ports      = 4,
3031                 .base_baud      = 1152000,
3032                 .uart_offset    = 8,
3033         },
3034 
3035         [pbn_b0_2_1152000_200] = {
3036                 .flags          = FL_BASE0,
3037                 .num_ports      = 2,
3038                 .base_baud      = 1152000,
3039                 .uart_offset    = 0x200,
3040         },
3041 
3042         [pbn_b0_4_1152000_200] = {
3043                 .flags          = FL_BASE0,
3044                 .num_ports      = 4,
3045                 .base_baud      = 1152000,
3046                 .uart_offset    = 0x200,
3047         },
3048 
3049         [pbn_b0_8_1152000_200] = {
3050                 .flags          = FL_BASE0,
3051                 .num_ports      = 8,
3052                 .base_baud      = 1152000,
3053                 .uart_offset    = 0x200,
3054         },
3055 
3056         [pbn_b0_2_1843200] = {
3057                 .flags          = FL_BASE0,
3058                 .num_ports      = 2,
3059                 .base_baud      = 1843200,
3060                 .uart_offset    = 8,
3061         },
3062         [pbn_b0_4_1843200] = {
3063                 .flags          = FL_BASE0,
3064                 .num_ports      = 4,
3065                 .base_baud      = 1843200,
3066                 .uart_offset    = 8,
3067         },
3068 
3069         [pbn_b0_2_1843200_200] = {
3070                 .flags          = FL_BASE0,
3071                 .num_ports      = 2,
3072                 .base_baud      = 1843200,
3073                 .uart_offset    = 0x200,
3074         },
3075         [pbn_b0_4_1843200_200] = {
3076                 .flags          = FL_BASE0,
3077                 .num_ports      = 4,
3078                 .base_baud      = 1843200,
3079                 .uart_offset    = 0x200,
3080         },
3081         [pbn_b0_8_1843200_200] = {
3082                 .flags          = FL_BASE0,
3083                 .num_ports      = 8,
3084                 .base_baud      = 1843200,
3085                 .uart_offset    = 0x200,
3086         },
3087         [pbn_b0_1_4000000] = {
3088                 .flags          = FL_BASE0,
3089                 .num_ports      = 1,
3090                 .base_baud      = 4000000,
3091                 .uart_offset    = 8,
3092         },
3093 
3094         [pbn_b0_bt_1_115200] = {
3095                 .flags          = FL_BASE0|FL_BASE_BARS,
3096                 .num_ports      = 1,
3097                 .base_baud      = 115200,
3098                 .uart_offset    = 8,
3099         },
3100         [pbn_b0_bt_2_115200] = {
3101                 .flags          = FL_BASE0|FL_BASE_BARS,
3102                 .num_ports      = 2,
3103                 .base_baud      = 115200,
3104                 .uart_offset    = 8,
3105         },
3106         [pbn_b0_bt_4_115200] = {
3107                 .flags          = FL_BASE0|FL_BASE_BARS,
3108                 .num_ports      = 4,
3109                 .base_baud      = 115200,
3110                 .uart_offset    = 8,
3111         },
3112         [pbn_b0_bt_8_115200] = {
3113                 .flags          = FL_BASE0|FL_BASE_BARS,
3114                 .num_ports      = 8,
3115                 .base_baud      = 115200,
3116                 .uart_offset    = 8,
3117         },
3118 
3119         [pbn_b0_bt_1_460800] = {
3120                 .flags          = FL_BASE0|FL_BASE_BARS,
3121                 .num_ports      = 1,
3122                 .base_baud      = 460800,
3123                 .uart_offset    = 8,
3124         },
3125         [pbn_b0_bt_2_460800] = {
3126                 .flags          = FL_BASE0|FL_BASE_BARS,
3127                 .num_ports      = 2,
3128                 .base_baud      = 460800,
3129                 .uart_offset    = 8,
3130         },
3131         [pbn_b0_bt_4_460800] = {
3132                 .flags          = FL_BASE0|FL_BASE_BARS,
3133                 .num_ports      = 4,
3134                 .base_baud      = 460800,
3135                 .uart_offset    = 8,
3136         },
3137 
3138         [pbn_b0_bt_1_921600] = {
3139                 .flags          = FL_BASE0|FL_BASE_BARS,
3140                 .num_ports      = 1,
3141                 .base_baud      = 921600,
3142                 .uart_offset    = 8,
3143         },
3144         [pbn_b0_bt_2_921600] = {
3145                 .flags          = FL_BASE0|FL_BASE_BARS,
3146                 .num_ports      = 2,
3147                 .base_baud      = 921600,
3148                 .uart_offset    = 8,
3149         },
3150         [pbn_b0_bt_4_921600] = {
3151                 .flags          = FL_BASE0|FL_BASE_BARS,
3152                 .num_ports      = 4,
3153                 .base_baud      = 921600,
3154                 .uart_offset    = 8,
3155         },
3156         [pbn_b0_bt_8_921600] = {
3157                 .flags          = FL_BASE0|FL_BASE_BARS,
3158                 .num_ports      = 8,
3159                 .base_baud      = 921600,
3160                 .uart_offset    = 8,
3161         },
3162 
3163         [pbn_b1_1_115200] = {
3164                 .flags          = FL_BASE1,
3165                 .num_ports      = 1,
3166                 .base_baud      = 115200,
3167                 .uart_offset    = 8,
3168         },
3169         [pbn_b1_2_115200] = {
3170                 .flags          = FL_BASE1,
3171                 .num_ports      = 2,
3172                 .base_baud      = 115200,
3173                 .uart_offset    = 8,
3174         },
3175         [pbn_b1_4_115200] = {
3176                 .flags          = FL_BASE1,
3177                 .num_ports      = 4,
3178                 .base_baud      = 115200,
3179                 .uart_offset    = 8,
3180         },
3181         [pbn_b1_8_115200] = {
3182                 .flags          = FL_BASE1,
3183                 .num_ports      = 8,
3184                 .base_baud      = 115200,
3185                 .uart_offset    = 8,
3186         },
3187         [pbn_b1_16_115200] = {
3188                 .flags          = FL_BASE1,
3189                 .num_ports      = 16,
3190                 .base_baud      = 115200,
3191                 .uart_offset    = 8,
3192         },
3193 
3194         [pbn_b1_1_921600] = {
3195                 .flags          = FL_BASE1,
3196                 .num_ports      = 1,
3197                 .base_baud      = 921600,
3198                 .uart_offset    = 8,
3199         },
3200         [pbn_b1_2_921600] = {
3201                 .flags          = FL_BASE1,
3202                 .num_ports      = 2,
3203                 .base_baud      = 921600,
3204                 .uart_offset    = 8,
3205         },
3206         [pbn_b1_4_921600] = {
3207                 .flags          = FL_BASE1,
3208                 .num_ports      = 4,
3209                 .base_baud      = 921600,
3210                 .uart_offset    = 8,
3211         },
3212         [pbn_b1_8_921600] = {
3213                 .flags          = FL_BASE1,
3214                 .num_ports      = 8,
3215                 .base_baud      = 921600,
3216                 .uart_offset    = 8,
3217         },
3218         [pbn_b1_2_1250000] = {
3219                 .flags          = FL_BASE1,
3220                 .num_ports      = 2,
3221                 .base_baud      = 1250000,
3222                 .uart_offset    = 8,
3223         },
3224 
3225         [pbn_b1_bt_1_115200] = {
3226                 .flags          = FL_BASE1|FL_BASE_BARS,
3227                 .num_ports      = 1,
3228                 .base_baud      = 115200,
3229                 .uart_offset    = 8,
3230         },
3231         [pbn_b1_bt_2_115200] = {
3232                 .flags          = FL_BASE1|FL_BASE_BARS,
3233                 .num_ports      = 2,
3234                 .base_baud      = 115200,
3235                 .uart_offset    = 8,
3236         },
3237         [pbn_b1_bt_4_115200] = {
3238                 .flags          = FL_BASE1|FL_BASE_BARS,
3239                 .num_ports      = 4,
3240                 .base_baud      = 115200,
3241                 .uart_offset    = 8,
3242         },
3243 
3244         [pbn_b1_bt_2_921600] = {
3245                 .flags          = FL_BASE1|FL_BASE_BARS,
3246                 .num_ports      = 2,
3247                 .base_baud      = 921600,
3248                 .uart_offset    = 8,
3249         },
3250 
3251         [pbn_b1_1_1382400] = {
3252                 .flags          = FL_BASE1,
3253                 .num_ports      = 1,
3254                 .base_baud      = 1382400,
3255                 .uart_offset    = 8,
3256         },
3257         [pbn_b1_2_1382400] = {
3258                 .flags          = FL_BASE1,
3259                 .num_ports      = 2,
3260                 .base_baud      = 1382400,
3261                 .uart_offset    = 8,
3262         },
3263         [pbn_b1_4_1382400] = {
3264                 .flags          = FL_BASE1,
3265                 .num_ports      = 4,
3266                 .base_baud      = 1382400,
3267                 .uart_offset    = 8,
3268         },
3269         [pbn_b1_8_1382400] = {
3270                 .flags          = FL_BASE1,
3271                 .num_ports      = 8,
3272                 .base_baud      = 1382400,
3273                 .uart_offset    = 8,
3274         },
3275 
3276         [pbn_b2_1_115200] = {
3277                 .flags          = FL_BASE2,
3278                 .num_ports      = 1,
3279                 .base_baud      = 115200,
3280                 .uart_offset    = 8,
3281         },
3282         [pbn_b2_2_115200] = {
3283                 .flags          = FL_BASE2,
3284                 .num_ports      = 2,
3285                 .base_baud      = 115200,
3286                 .uart_offset    = 8,
3287         },
3288         [pbn_b2_4_115200] = {
3289                 .flags          = FL_BASE2,
3290                 .num_ports      = 4,
3291                 .base_baud      = 115200,
3292                 .uart_offset    = 8,
3293         },
3294         [pbn_b2_8_115200] = {
3295                 .flags          = FL_BASE2,
3296                 .num_ports      = 8,
3297                 .base_baud      = 115200,
3298                 .uart_offset    = 8,
3299         },
3300 
3301         [pbn_b2_1_460800] = {
3302                 .flags          = FL_BASE2,
3303                 .num_ports      = 1,
3304                 .base_baud      = 460800,
3305                 .uart_offset    = 8,
3306         },
3307         [pbn_b2_4_460800] = {
3308                 .flags          = FL_BASE2,
3309                 .num_ports      = 4,
3310                 .base_baud      = 460800,
3311                 .uart_offset    = 8,
3312         },
3313         [pbn_b2_8_460800] = {
3314                 .flags          = FL_BASE2,
3315                 .num_ports      = 8,
3316                 .base_baud      = 460800,
3317                 .uart_offset    = 8,
3318         },
3319         [pbn_b2_16_460800] = {
3320                 .flags          = FL_BASE2,
3321                 .num_ports      = 16,
3322                 .base_baud      = 460800,
3323                 .uart_offset    = 8,
3324          },
3325 
3326         [pbn_b2_1_921600] = {
3327                 .flags          = FL_BASE2,
3328                 .num_ports      = 1,
3329                 .base_baud      = 921600,
3330                 .uart_offset    = 8,
3331         },
3332         [pbn_b2_4_921600] = {
3333                 .flags          = FL_BASE2,
3334                 .num_ports      = 4,
3335                 .base_baud      = 921600,
3336                 .uart_offset    = 8,
3337         },
3338         [pbn_b2_8_921600] = {
3339                 .flags          = FL_BASE2,
3340                 .num_ports      = 8,
3341                 .base_baud      = 921600,
3342                 .uart_offset    = 8,
3343         },
3344 
3345         [pbn_b2_8_1152000] = {
3346                 .flags          = FL_BASE2,
3347                 .num_ports      = 8,
3348                 .base_baud      = 1152000,
3349                 .uart_offset    = 8,
3350         },
3351 
3352         [pbn_b2_bt_1_115200] = {
3353                 .flags          = FL_BASE2|FL_BASE_BARS,
3354                 .num_ports      = 1,
3355                 .base_baud      = 115200,
3356                 .uart_offset    = 8,
3357         },
3358         [pbn_b2_bt_2_115200] = {
3359                 .flags          = FL_BASE2|FL_BASE_BARS,
3360                 .num_ports      = 2,
3361                 .base_baud      = 115200,
3362                 .uart_offset    = 8,
3363         },
3364         [pbn_b2_bt_4_115200] = {
3365                 .flags          = FL_BASE2|FL_BASE_BARS,
3366                 .num_ports      = 4,
3367                 .base_baud      = 115200,
3368                 .uart_offset    = 8,
3369         },
3370 
3371         [pbn_b2_bt_2_921600] = {
3372                 .flags          = FL_BASE2|FL_BASE_BARS,
3373                 .num_ports      = 2,
3374                 .base_baud      = 921600,
3375                 .uart_offset    = 8,
3376         },
3377         [pbn_b2_bt_4_921600] = {
3378                 .flags          = FL_BASE2|FL_BASE_BARS,
3379                 .num_ports      = 4,
3380                 .base_baud      = 921600,
3381                 .uart_offset    = 8,
3382         },
3383 
3384         [pbn_b3_2_115200] = {
3385                 .flags          = FL_BASE3,
3386                 .num_ports      = 2,
3387                 .base_baud      = 115200,
3388                 .uart_offset    = 8,
3389         },
3390         [pbn_b3_4_115200] = {
3391                 .flags          = FL_BASE3,
3392                 .num_ports      = 4,
3393                 .base_baud      = 115200,
3394                 .uart_offset    = 8,
3395         },
3396         [pbn_b3_8_115200] = {
3397                 .flags          = FL_BASE3,
3398                 .num_ports      = 8,
3399                 .base_baud      = 115200,
3400                 .uart_offset    = 8,
3401         },
3402 
3403         [pbn_b4_bt_2_921600] = {
3404                 .flags          = FL_BASE4,
3405                 .num_ports      = 2,
3406                 .base_baud      = 921600,
3407                 .uart_offset    = 8,
3408         },
3409         [pbn_b4_bt_4_921600] = {
3410                 .flags          = FL_BASE4,
3411                 .num_ports      = 4,
3412                 .base_baud      = 921600,
3413                 .uart_offset    = 8,
3414         },
3415         [pbn_b4_bt_8_921600] = {
3416                 .flags          = FL_BASE4,
3417                 .num_ports      = 8,
3418                 .base_baud      = 921600,
3419                 .uart_offset    = 8,
3420         },
3421 
3422         /*
3423          * Entries following this are board-specific.
3424          */
3425 
3426         /*
3427          * Panacom - IOMEM
3428          */
3429         [pbn_panacom] = {
3430                 .flags          = FL_BASE2,
3431                 .num_ports      = 2,
3432                 .base_baud      = 921600,
3433                 .uart_offset    = 0x400,
3434                 .reg_shift      = 7,
3435         },
3436         [pbn_panacom2] = {
3437                 .flags          = FL_BASE2|FL_BASE_BARS,
3438                 .num_ports      = 2,
3439                 .base_baud      = 921600,
3440                 .uart_offset    = 0x400,
3441                 .reg_shift      = 7,
3442         },
3443         [pbn_panacom4] = {
3444                 .flags          = FL_BASE2|FL_BASE_BARS,
3445                 .num_ports      = 4,
3446                 .base_baud      = 921600,
3447                 .uart_offset    = 0x400,
3448                 .reg_shift      = 7,
3449         },
3450 
3451         /* I think this entry is broken - the first_offset looks wrong --rmk */
3452         [pbn_plx_romulus] = {
3453                 .flags          = FL_BASE2,
3454                 .num_ports      = 4,
3455                 .base_baud      = 921600,
3456                 .uart_offset    = 8 << 2,
3457                 .reg_shift      = 2,
3458                 .first_offset   = 0x03,
3459         },
3460 
3461         /*
3462          * EndRun Technologies
3463         * Uses the size of PCI Base region 0 to
3464         * signal now many ports are available
3465         * 2 port 952 Uart support
3466         */
3467         [pbn_endrun_2_4000000] = {
3468                 .flags          = FL_BASE0,
3469                 .num_ports      = 2,
3470                 .base_baud      = 4000000,
3471                 .uart_offset    = 0x200,
3472                 .first_offset   = 0x1000,
3473         },
3474 
3475         /*
3476          * This board uses the size of PCI Base region 0 to
3477          * signal now many ports are available
3478          */
3479         [pbn_oxsemi] = {
3480                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3481                 .num_ports      = 32,
3482                 .base_baud      = 115200,
3483                 .uart_offset    = 8,
3484         },
3485         [pbn_oxsemi_1_4000000] = {
3486                 .flags          = FL_BASE0,
3487                 .num_ports      = 1,
3488                 .base_baud      = 4000000,
3489                 .uart_offset    = 0x200,
3490                 .first_offset   = 0x1000,
3491         },
3492         [pbn_oxsemi_2_4000000] = {
3493                 .flags          = FL_BASE0,
3494                 .num_ports      = 2,
3495                 .base_baud      = 4000000,
3496                 .uart_offset    = 0x200,
3497                 .first_offset   = 0x1000,
3498         },
3499         [pbn_oxsemi_4_4000000] = {
3500                 .flags          = FL_BASE0,
3501                 .num_ports      = 4,
3502                 .base_baud      = 4000000,
3503                 .uart_offset    = 0x200,
3504                 .first_offset   = 0x1000,
3505         },
3506         [pbn_oxsemi_8_4000000] = {
3507                 .flags          = FL_BASE0,
3508                 .num_ports      = 8,
3509                 .base_baud      = 4000000,
3510                 .uart_offset    = 0x200,
3511                 .first_offset   = 0x1000,
3512         },
3513 
3514 
3515         /*
3516          * EKF addition for i960 Boards form EKF with serial port.
3517          * Max 256 ports.
3518          */
3519         [pbn_intel_i960] = {
3520                 .flags          = FL_BASE0,
3521                 .num_ports      = 32,
3522                 .base_baud      = 921600,
3523                 .uart_offset    = 8 << 2,
3524                 .reg_shift      = 2,
3525                 .first_offset   = 0x10000,
3526         },
3527         [pbn_sgi_ioc3] = {
3528                 .flags          = FL_BASE0|FL_NOIRQ,
3529                 .num_ports      = 1,
3530                 .base_baud      = 458333,
3531                 .uart_offset    = 8,
3532                 .reg_shift      = 0,
3533                 .first_offset   = 0x20178,
3534         },
3535 
3536         /*
3537          * Computone - uses IOMEM.
3538          */
3539         [pbn_computone_4] = {
3540                 .flags          = FL_BASE0,
3541                 .num_ports      = 4,
3542                 .base_baud      = 921600,
3543                 .uart_offset    = 0x40,
3544                 .reg_shift      = 2,
3545                 .first_offset   = 0x200,
3546         },
3547         [pbn_computone_6] = {
3548                 .flags          = FL_BASE0,
3549                 .num_ports      = 6,
3550                 .base_baud      = 921600,
3551                 .uart_offset    = 0x40,
3552                 .reg_shift      = 2,
3553                 .first_offset   = 0x200,
3554         },
3555         [pbn_computone_8] = {
3556                 .flags          = FL_BASE0,
3557                 .num_ports      = 8,
3558                 .base_baud      = 921600,
3559                 .uart_offset    = 0x40,
3560                 .reg_shift      = 2,
3561                 .first_offset   = 0x200,
3562         },
3563         [pbn_sbsxrsio] = {
3564                 .flags          = FL_BASE0,
3565                 .num_ports      = 8,
3566                 .base_baud      = 460800,
3567                 .uart_offset    = 256,
3568                 .reg_shift      = 4,
3569         },
3570         /*
3571          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3572          *  Only basic 16550A support.
3573          *  XR17C15[24] are not tested, but they should work.
3574          */
3575         [pbn_exar_XR17C152] = {
3576                 .flags          = FL_BASE0,
3577                 .num_ports      = 2,
3578                 .base_baud      = 921600,
3579                 .uart_offset    = 0x200,
3580         },
3581         [pbn_exar_XR17C154] = {
3582                 .flags          = FL_BASE0,
3583                 .num_ports      = 4,
3584                 .base_baud      = 921600,
3585                 .uart_offset    = 0x200,
3586         },
3587         [pbn_exar_XR17C158] = {
3588                 .flags          = FL_BASE0,
3589                 .num_ports      = 8,
3590                 .base_baud      = 921600,
3591                 .uart_offset    = 0x200,
3592         },
3593         [pbn_exar_XR17V352] = {
3594                 .flags          = FL_BASE0,
3595                 .num_ports      = 2,
3596                 .base_baud      = 7812500,
3597                 .uart_offset    = 0x400,
3598                 .reg_shift      = 0,
3599                 .first_offset   = 0,
3600         },
3601         [pbn_exar_XR17V354] = {
3602                 .flags          = FL_BASE0,
3603                 .num_ports      = 4,
3604                 .base_baud      = 7812500,
3605                 .uart_offset    = 0x400,
3606                 .reg_shift      = 0,
3607                 .first_offset   = 0,
3608         },
3609         [pbn_exar_XR17V358] = {
3610                 .flags          = FL_BASE0,
3611                 .num_ports      = 8,
3612                 .base_baud      = 7812500,
3613                 .uart_offset    = 0x400,
3614                 .reg_shift      = 0,
3615                 .first_offset   = 0,
3616         },
3617         [pbn_exar_XR17V4358] = {
3618                 .flags          = FL_BASE0,
3619                 .num_ports      = 12,
3620                 .base_baud      = 7812500,
3621                 .uart_offset    = 0x400,
3622                 .reg_shift      = 0,
3623                 .first_offset   = 0,
3624         },
3625         [pbn_exar_XR17V8358] = {
3626                 .flags          = FL_BASE0,
3627                 .num_ports      = 16,
3628                 .base_baud      = 7812500,
3629                 .uart_offset    = 0x400,
3630                 .reg_shift      = 0,
3631                 .first_offset   = 0,
3632         },
3633         [pbn_exar_ibm_saturn] = {
3634                 .flags          = FL_BASE0,
3635                 .num_ports      = 1,
3636                 .base_baud      = 921600,
3637                 .uart_offset    = 0x200,
3638         },
3639 
3640         /*
3641          * PA Semi PWRficient PA6T-1682M on-chip UART
3642          */
3643         [pbn_pasemi_1682M] = {
3644                 .flags          = FL_BASE0,
3645                 .num_ports      = 1,
3646                 .base_baud      = 8333333,
3647         },
3648         /*
3649          * National Instruments 843x
3650          */
3651         [pbn_ni8430_16] = {
3652                 .flags          = FL_BASE0,
3653                 .num_ports      = 16,
3654                 .base_baud      = 3686400,
3655                 .uart_offset    = 0x10,
3656                 .first_offset   = 0x800,
3657         },
3658         [pbn_ni8430_8] = {
3659                 .flags          = FL_BASE0,
3660                 .num_ports      = 8,
3661                 .base_baud      = 3686400,
3662                 .uart_offset    = 0x10,
3663                 .first_offset   = 0x800,
3664         },
3665         [pbn_ni8430_4] = {
3666                 .flags          = FL_BASE0,
3667                 .num_ports      = 4,
3668                 .base_baud      = 3686400,
3669                 .uart_offset    = 0x10,
3670                 .first_offset   = 0x800,
3671         },
3672         [pbn_ni8430_2] = {
3673                 .flags          = FL_BASE0,
3674                 .num_ports      = 2,
3675                 .base_baud      = 3686400,
3676                 .uart_offset    = 0x10,
3677                 .first_offset   = 0x800,
3678         },
3679         /*
3680          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3681          */
3682         [pbn_ADDIDATA_PCIe_1_3906250] = {
3683                 .flags          = FL_BASE0,
3684                 .num_ports      = 1,
3685                 .base_baud      = 3906250,
3686                 .uart_offset    = 0x200,
3687                 .first_offset   = 0x1000,
3688         },
3689         [pbn_ADDIDATA_PCIe_2_3906250] = {
3690                 .flags          = FL_BASE0,
3691                 .num_ports      = 2,
3692                 .base_baud      = 3906250,
3693                 .uart_offset    = 0x200,
3694                 .first_offset   = 0x1000,
3695         },
3696         [pbn_ADDIDATA_PCIe_4_3906250] = {
3697                 .flags          = FL_BASE0,
3698                 .num_ports      = 4,
3699                 .base_baud      = 3906250,
3700                 .uart_offset    = 0x200,
3701                 .first_offset   = 0x1000,
3702         },
3703         [pbn_ADDIDATA_PCIe_8_3906250] = {
3704                 .flags          = FL_BASE0,
3705                 .num_ports      = 8,
3706                 .base_baud      = 3906250,
3707                 .uart_offset    = 0x200,
3708                 .first_offset   = 0x1000,
3709         },
3710         [pbn_ce4100_1_115200] = {
3711                 .flags          = FL_BASE_BARS,
3712                 .num_ports      = 2,
3713                 .base_baud      = 921600,
3714                 .reg_shift      = 2,
3715         },
3716         [pbn_byt] = {
3717                 .flags          = FL_BASE0,
3718                 .num_ports      = 1,
3719                 .base_baud      = 2764800,
3720                 .reg_shift      = 2,
3721         },
3722         [pbn_qrk] = {
3723                 .flags          = FL_BASE0,
3724                 .num_ports      = 1,
3725                 .base_baud      = 2764800,
3726                 .reg_shift      = 2,
3727         },
3728         [pbn_omegapci] = {
3729                 .flags          = FL_BASE0,
3730                 .num_ports      = 8,
3731                 .base_baud      = 115200,
3732                 .uart_offset    = 0x200,
3733         },
3734         [pbn_NETMOS9900_2s_115200] = {
3735                 .flags          = FL_BASE0,
3736                 .num_ports      = 2,
3737                 .base_baud      = 115200,
3738         },
3739         [pbn_brcm_trumanage] = {
3740                 .flags          = FL_BASE0,
3741                 .num_ports      = 1,
3742                 .reg_shift      = 2,
3743                 .base_baud      = 115200,
3744         },
3745         [pbn_fintek_4] = {
3746                 .num_ports      = 4,
3747                 .uart_offset    = 8,
3748                 .base_baud      = 115200,
3749                 .first_offset   = 0x40,
3750         },
3751         [pbn_fintek_8] = {
3752                 .num_ports      = 8,
3753                 .uart_offset    = 8,
3754                 .base_baud      = 115200,
3755                 .first_offset   = 0x40,
3756         },
3757         [pbn_fintek_12] = {
3758                 .num_ports      = 12,
3759                 .uart_offset    = 8,
3760                 .base_baud      = 115200,
3761                 .first_offset   = 0x40,
3762         },
3763         [pbn_wch382_2] = {
3764                 .flags          = FL_BASE0,
3765                 .num_ports      = 2,
3766                 .base_baud      = 115200,
3767                 .uart_offset    = 8,
3768                 .first_offset   = 0xC0,
3769         },
3770         [pbn_wch384_4] = {
3771                 .flags          = FL_BASE0,
3772                 .num_ports      = 4,
3773                 .base_baud      = 115200,
3774                 .uart_offset    = 8,
3775                 .first_offset   = 0xC0,
3776         },
3777         /*
3778          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3779          */
3780         [pbn_pericom_PI7C9X7951] = {
3781                 .flags          = FL_BASE0,
3782                 .num_ports      = 1,
3783                 .base_baud      = 921600,
3784                 .uart_offset    = 0x8,
3785         },
3786         [pbn_pericom_PI7C9X7952] = {
3787                 .flags          = FL_BASE0,
3788                 .num_ports      = 2,
3789                 .base_baud      = 921600,
3790                 .uart_offset    = 0x8,
3791         },
3792         [pbn_pericom_PI7C9X7954] = {
3793                 .flags          = FL_BASE0,
3794                 .num_ports      = 4,
3795                 .base_baud      = 921600,
3796                 .uart_offset    = 0x8,
3797         },
3798         [pbn_pericom_PI7C9X7958] = {
3799                 .flags          = FL_BASE0,
3800                 .num_ports      = 8,
3801                 .base_baud      = 921600,
3802                 .uart_offset    = 0x8,
3803         },
3804 };
3805 
3806 static const struct pci_device_id blacklist[] = {
3807         /* softmodems */
3808         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3809         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3810         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3811 
3812         /* multi-io cards handled by parport_serial */
3813         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3814         { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3815         { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3816         { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3817 
3818         /* Moxa Smartio MUE boards handled by 8250_moxa */
3819         { PCI_VDEVICE(MOXA, 0x1024), },
3820         { PCI_VDEVICE(MOXA, 0x1025), },
3821         { PCI_VDEVICE(MOXA, 0x1045), },
3822         { PCI_VDEVICE(MOXA, 0x1144), },
3823         { PCI_VDEVICE(MOXA, 0x1160), },
3824         { PCI_VDEVICE(MOXA, 0x1161), },
3825         { PCI_VDEVICE(MOXA, 0x1182), },
3826         { PCI_VDEVICE(MOXA, 0x1183), },
3827         { PCI_VDEVICE(MOXA, 0x1322), },
3828         { PCI_VDEVICE(MOXA, 0x1342), },
3829         { PCI_VDEVICE(MOXA, 0x1381), },
3830         { PCI_VDEVICE(MOXA, 0x1683), },
3831 
3832         /* Intel platforms with MID UART */
3833         { PCI_VDEVICE(INTEL, 0x081b), },
3834         { PCI_VDEVICE(INTEL, 0x081c), },
3835         { PCI_VDEVICE(INTEL, 0x081d), },
3836         { PCI_VDEVICE(INTEL, 0x1191), },
3837         { PCI_VDEVICE(INTEL, 0x19d8), },
3838 };
3839 
3840 /*
3841  * Given a complete unknown PCI device, try to use some heuristics to
3842  * guess what the configuration might be, based on the pitiful PCI
3843  * serial specs.  Returns 0 on success, 1 on failure.
3844  */
3845 static int
3846 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3847 {
3848         const struct pci_device_id *bldev;
3849         int num_iomem, num_port, first_port = -1, i;
3850 
3851         /*
3852          * If it is not a communications device or the programming
3853          * interface is greater than 6, give up.
3854          *
3855          * (Should we try to make guesses for multiport serial devices
3856          * later?)
3857          */
3858         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3859              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3860             (dev->class & 0xff) > 6)
3861                 return -ENODEV;
3862 
3863         /*
3864          * Do not access blacklisted devices that are known not to
3865          * feature serial ports or are handled by other modules.
3866          */
3867         for (bldev = blacklist;
3868              bldev < blacklist + ARRAY_SIZE(blacklist);
3869              bldev++) {
3870                 if (dev->vendor == bldev->vendor &&
3871                     dev->device == bldev->device)
3872                         return -ENODEV;
3873         }
3874 
3875         num_iomem = num_port = 0;
3876         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3877                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3878                         num_port++;
3879                         if (first_port == -1)
3880                                 first_port = i;
3881                 }
3882                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3883                         num_iomem++;
3884         }
3885 
3886         /*
3887          * If there is 1 or 0 iomem regions, and exactly one port,
3888          * use it.  We guess the number of ports based on the IO
3889          * region size.
3890          */
3891         if (num_iomem <= 1 && num_port == 1) {
3892                 board->flags = first_port;
3893                 board->num_ports = pci_resource_len(dev, first_port) / 8;
3894                 return 0;
3895         }
3896 
3897         /*
3898          * Now guess if we've got a board which indexes by BARs.
3899          * Each IO BAR should be 8 bytes, and they should follow
3900          * consecutively.
3901          */
3902         first_port = -1;
3903         num_port = 0;
3904         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3905                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3906                     pci_resource_len(dev, i) == 8 &&
3907                     (first_port == -1 || (first_port + num_port) == i)) {
3908                         num_port++;
3909                         if (first_port == -1)
3910                                 first_port = i;
3911                 }
3912         }
3913 
3914         if (num_port > 1) {
3915                 board->flags = first_port | FL_BASE_BARS;
3916                 board->num_ports = num_port;
3917                 return 0;
3918         }
3919 
3920         return -ENODEV;
3921 }
3922 
3923 static inline int
3924 serial_pci_matches(const struct pciserial_board *board,
3925                    const struct pciserial_board *guessed)
3926 {
3927         return
3928             board->num_ports == guessed->num_ports &&
3929             board->base_baud == guessed->base_baud &&
3930             board->uart_offset == guessed->uart_offset &&
3931             board->reg_shift == guessed->reg_shift &&
3932             board->first_offset == guessed->first_offset;
3933 }
3934 
3935 struct serial_private *
3936 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3937 {
3938         struct uart_8250_port uart;
3939         struct serial_private *priv;
3940         struct pci_serial_quirk *quirk;
3941         int rc, nr_ports, i;
3942 
3943         nr_ports = board->num_ports;
3944 
3945         /*
3946          * Find an init and setup quirks.
3947          */
3948         quirk = find_quirk(dev);
3949 
3950         /*
3951          * Run the new-style initialization function.
3952          * The initialization function returns:
3953          *  <0  - error
3954          *   0  - use board->num_ports
3955          *  >0  - number of ports
3956          */
3957         if (quirk->init) {
3958                 rc = quirk->init(dev);
3959                 if (rc < 0) {
3960                         priv = ERR_PTR(rc);
3961                         goto err_out;
3962                 }
3963                 if (rc)
3964                         nr_ports = rc;
3965         }
3966 
3967         priv = kzalloc(sizeof(struct serial_private) +
3968                        sizeof(unsigned int) * nr_ports,
3969                        GFP_KERNEL);
3970         if (!priv) {
3971                 priv = ERR_PTR(-ENOMEM);
3972                 goto err_deinit;
3973         }
3974 
3975         priv->dev = dev;
3976         priv->quirk = quirk;
3977 
3978         memset(&uart, 0, sizeof(uart));
3979         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3980         uart.port.uartclk = board->base_baud * 16;
3981         uart.port.irq = get_pci_irq(dev, board);
3982         uart.port.dev = &dev->dev;
3983 
3984         for (i = 0; i < nr_ports; i++) {
3985                 if (quirk->setup(priv, board, &uart, i))
3986                         break;
3987 
3988                 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3989                         uart.port.iobase, uart.port.irq, uart.port.iotype);
3990 
3991                 priv->line[i] = serial8250_register_8250_port(&uart);
3992                 if (priv->line[i] < 0) {
3993                         dev_err(&dev->dev,
3994                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3995                                 uart.port.iobase, uart.port.irq,
3996                                 uart.port.iotype, priv->line[i]);
3997                         break;
3998                 }
3999         }
4000         priv->nr = i;
4001         return priv;
4002 
4003 err_deinit:
4004         if (quirk->exit)
4005                 quirk->exit(dev);
4006 err_out:
4007         return priv;
4008 }
4009 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4010 
4011 void pciserial_remove_ports(struct serial_private *priv)
4012 {
4013         struct pci_serial_quirk *quirk;
4014         int i;
4015 
4016         for (i = 0; i < priv->nr; i++)
4017                 serial8250_unregister_port(priv->line[i]);
4018 
4019         /*
4020          * Find the exit quirks.
4021          */
4022         quirk = find_quirk(priv->dev);
4023         if (quirk->exit)
4024                 quirk->exit(priv->dev);
4025 
4026         kfree(priv);
4027 }
4028 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4029 
4030 void pciserial_suspend_ports(struct serial_private *priv)
4031 {
4032         int i;
4033 
4034         for (i = 0; i < priv->nr; i++)
4035                 if (priv->line[i] >= 0)
4036                         serial8250_suspend_port(priv->line[i]);
4037 
4038         /*
4039          * Ensure that every init quirk is properly torn down
4040          */
4041         if (priv->quirk->exit)
4042                 priv->quirk->exit(priv->dev);
4043 }
4044 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4045 
4046 void pciserial_resume_ports(struct serial_private *priv)
4047 {
4048         int i;
4049 
4050         /*
4051          * Ensure that the board is correctly configured.
4052          */
4053         if (priv->quirk->init)
4054                 priv->quirk->init(priv->dev);
4055 
4056         for (i = 0; i < priv->nr; i++)
4057                 if (priv->line[i] >= 0)
4058                         serial8250_resume_port(priv->line[i]);
4059 }
4060 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4061 
4062 /*
4063  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
4064  * to the arrangement of serial ports on a PCI card.
4065  */
4066 static int
4067 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4068 {
4069         struct pci_serial_quirk *quirk;
4070         struct serial_private *priv;
4071         const struct pciserial_board *board;
4072         struct pciserial_board tmp;
4073         int rc;
4074 
4075         quirk = find_quirk(dev);
4076         if (quirk->probe) {
4077                 rc = quirk->probe(dev);
4078                 if (rc)
4079                         return rc;
4080         }
4081 
4082         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4083                 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4084                         ent->driver_data);
4085                 return -EINVAL;
4086         }
4087 
4088         board = &pci_boards[ent->driver_data];
4089 
4090         rc = pcim_enable_device(dev);
4091         pci_save_state(dev);
4092         if (rc)
4093                 return rc;
4094 
4095         if (ent->driver_data == pbn_default) {
4096                 /*
4097                  * Use a copy of the pci_board entry for this;
4098                  * avoid changing entries in the table.
4099                  */
4100                 memcpy(&tmp, board, sizeof(struct pciserial_board));
4101                 board = &tmp;
4102 
4103                 /*
4104                  * We matched one of our class entries.  Try to
4105                  * determine the parameters of this board.
4106                  */
4107                 rc = serial_pci_guess_board(dev, &tmp);
4108                 if (rc)
4109                         return rc;
4110         } else {
4111                 /*
4112                  * We matched an explicit entry.  If we are able to
4113                  * detect this boards settings with our heuristic,
4114                  * then we no longer need this entry.
4115                  */
4116                 memcpy(&tmp, &pci_boards[pbn_default],
4117                        sizeof(struct pciserial_board));
4118                 rc = serial_pci_guess_board(dev, &tmp);
4119                 if (rc == 0 && serial_pci_matches(board, &tmp))
4120                         moan_device("Redundant entry in serial pci_table.",
4121                                     dev);
4122         }
4123 
4124         priv = pciserial_init_ports(dev, board);
4125         if (IS_ERR(priv))
4126                 return PTR_ERR(priv);
4127 
4128         pci_set_drvdata(dev, priv);
4129         return 0;
4130 }
4131 
4132 static void pciserial_remove_one(struct pci_dev *dev)
4133 {
4134         struct serial_private *priv = pci_get_drvdata(dev);
4135 
4136         pciserial_remove_ports(priv);
4137 }
4138 
4139 #ifdef CONFIG_PM_SLEEP
4140 static int pciserial_suspend_one(struct device *dev)
4141 {
4142         struct pci_dev *pdev = to_pci_dev(dev);
4143         struct serial_private *priv = pci_get_drvdata(pdev);
4144 
4145         if (priv)
4146                 pciserial_suspend_ports(priv);
4147 
4148         return 0;
4149 }
4150 
4151 static int pciserial_resume_one(struct device *dev)
4152 {
4153         struct pci_dev *pdev = to_pci_dev(dev);
4154         struct serial_private *priv = pci_get_drvdata(pdev);
4155         int err;
4156 
4157         if (priv) {
4158                 /*
4159                  * The device may have been disabled.  Re-enable it.
4160                  */
4161                 err = pci_enable_device(pdev);
4162                 /* FIXME: We cannot simply error out here */
4163                 if (err)
4164                         dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4165                 pciserial_resume_ports(priv);
4166         }
4167         return 0;
4168 }
4169 #endif
4170 
4171 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4172                          pciserial_resume_one);
4173 
4174 static struct pci_device_id serial_pci_tbl[] = {
4175         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4176         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4177                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4178                 pbn_b2_8_921600 },
4179         /* Advantech also use 0x3618 and 0xf618 */
4180         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4181                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4182                 pbn_b0_4_921600 },
4183         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4184                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4185                 pbn_b0_4_921600 },
4186         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4187                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4188                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4189                 pbn_b1_8_1382400 },
4190         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4191                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4192                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4193                 pbn_b1_4_1382400 },
4194         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4195                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4196                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4197                 pbn_b1_2_1382400 },
4198         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4199                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4200                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4201                 pbn_b1_8_1382400 },
4202         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4203                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4204                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4205                 pbn_b1_4_1382400 },
4206         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4207                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4208                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4209                 pbn_b1_2_1382400 },
4210         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4211                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4212                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4213                 pbn_b1_8_921600 },
4214         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4215                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4216                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4217                 pbn_b1_8_921600 },
4218         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4219                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4220                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4221                 pbn_b1_4_921600 },
4222         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4223                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4224                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4225                 pbn_b1_4_921600 },
4226         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4227                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4228                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4229                 pbn_b1_2_921600 },
4230         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4231                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4232                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4233                 pbn_b1_8_921600 },
4234         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4235                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4236                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4237                 pbn_b1_8_921600 },
4238         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4239                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4240                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4241                 pbn_b1_4_921600 },
4242         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4243                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4244                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4245                 pbn_b1_2_1250000 },
4246         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4247                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4248                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4249                 pbn_b0_2_1843200 },
4250         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4251                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4252                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4253                 pbn_b0_4_1843200 },
4254         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4255                 PCI_VENDOR_ID_AFAVLAB,
4256                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4257                 pbn_b0_4_1152000 },
4258         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4259                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4260                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4261                 pbn_b0_2_1843200_200 },
4262         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4263                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4264                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4265                 pbn_b0_4_1843200_200 },
4266         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4267                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4268                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4269                 pbn_b0_8_1843200_200 },
4270         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4271                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4272                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4273                 pbn_b0_2_1843200_200 },
4274         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4275                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4276                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4277                 pbn_b0_4_1843200_200 },
4278         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4279                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4280                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4281                 pbn_b0_8_1843200_200 },
4282         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4283                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4284                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4285                 pbn_b0_2_1843200_200 },
4286         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4287                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4288                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4289                 pbn_b0_4_1843200_200 },
4290         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4291                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4292                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4293                 pbn_b0_8_1843200_200 },
4294         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4295                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4296                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4297                 pbn_b0_2_1843200_200 },
4298         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4299                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4300                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4301                 pbn_b0_4_1843200_200 },
4302         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4303                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4304                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4305                 pbn_b0_8_1843200_200 },
4306         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4307                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4308                 0, 0, pbn_exar_ibm_saturn },
4309 
4310         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4311                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312                 pbn_b2_bt_1_115200 },
4313         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4314                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315                 pbn_b2_bt_2_115200 },
4316         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4317                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4318                 pbn_b2_bt_4_115200 },
4319         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4320                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4321                 pbn_b2_bt_2_115200 },
4322         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4323                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4324                 pbn_b2_bt_4_115200 },
4325         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4326                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327                 pbn_b2_8_115200 },
4328         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4329                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4330                 pbn_b2_8_460800 },
4331         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4332                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333                 pbn_b2_8_115200 },
4334 
4335         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4336                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4337                 pbn_b2_bt_2_115200 },
4338         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4339                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4340                 pbn_b2_bt_2_921600 },
4341         /*
4342          * VScom SPCOM800, from sl@s.pl
4343          */
4344         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4345                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4346                 pbn_b2_8_921600 },
4347         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4348                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4349                 pbn_b2_4_921600 },
4350         /* Unknown card - subdevice 0x1584 */
4351         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4352                 PCI_VENDOR_ID_PLX,
4353                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4354                 pbn_b2_4_115200 },
4355         /* Unknown card - subdevice 0x1588 */
4356         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4357                 PCI_VENDOR_ID_PLX,
4358                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4359                 pbn_b2_8_115200 },
4360         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4361                 PCI_SUBVENDOR_ID_KEYSPAN,
4362                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4363                 pbn_panacom },
4364         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4365                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4366                 pbn_panacom4 },
4367         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4368                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4369                 pbn_panacom2 },
4370         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4371                 PCI_VENDOR_ID_ESDGMBH,
4372                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4373                 pbn_b2_4_115200 },
4374         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4375                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4376                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4377                 pbn_b2_4_460800 },
4378         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4379                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4380                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4381                 pbn_b2_8_460800 },
4382         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4383                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4384                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4385                 pbn_b2_16_460800 },
4386         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4387                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4388                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4389                 pbn_b2_16_460800 },
4390         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4391                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4392                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4393                 pbn_b2_4_460800 },
4394         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4395                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4396                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4397                 pbn_b2_8_460800 },
4398         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4399                 PCI_SUBVENDOR_ID_EXSYS,
4400                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4401                 pbn_b2_4_115200 },
4402         /*
4403          * Megawolf Romulus PCI Serial Card, from Mike Hudson
4404          * (Exoray@isys.ca)
4405          */
4406         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4407                 0x10b5, 0x106a, 0, 0,
4408                 pbn_plx_romulus },
4409         /*
4410         * EndRun Technologies. PCI express device range.
4411         *    EndRun PTP/1588 has 2 Native UARTs.
4412         */
4413         {       PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4414                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415                 pbn_endrun_2_4000000 },
4416         /*
4417          * Quatech cards. These actually have configurable clocks but for
4418          * now we just use the default.
4419          *
4420          * 100 series are RS232, 200 series RS422,
4421          */
4422         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4423                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4424                 pbn_b1_4_115200 },
4425         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4426                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427                 pbn_b1_2_115200 },
4428         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4429                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430                 pbn_b2_2_115200 },
4431         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4432                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4433                 pbn_b1_2_115200 },
4434         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4435                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4436                 pbn_b2_2_115200 },
4437         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4438                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439                 pbn_b1_4_115200 },
4440         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4441                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442                 pbn_b1_8_115200 },
4443         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4444                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445                 pbn_b1_8_115200 },
4446         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4447                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448                 pbn_b1_4_115200 },
4449         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4450                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451                 pbn_b1_2_115200 },
4452         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4453                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454                 pbn_b1_4_115200 },
4455         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4456                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457                 pbn_b1_2_115200 },
4458         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4459                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460                 pbn_b2_4_115200 },
4461         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4462                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4463                 pbn_b2_2_115200 },
4464         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4465                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4466                 pbn_b2_1_115200 },
4467         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4468                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4469                 pbn_b2_4_115200 },
4470         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4471                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4472                 pbn_b2_2_115200 },
4473         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4474                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4475                 pbn_b2_1_115200 },
4476         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4477                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4478                 pbn_b0_8_115200 },
4479 
4480         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4481                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4482                 0, 0,
4483                 pbn_b0_4_921600 },
4484         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4485                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4486                 0, 0,
4487                 pbn_b0_4_1152000 },
4488         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
4489                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490                 pbn_b0_bt_2_921600 },
4491 
4492                 /*
4493                  * The below card is a little controversial since it is the
4494                  * subject of a PCI vendor/device ID clash.  (See
4495                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4496                  * For now just used the hex ID 0x950a.
4497                  */
4498         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4499                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4500                 0, 0, pbn_b0_2_115200 },
4501         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4502                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4503                 0, 0, pbn_b0_2_115200 },
4504         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4505                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4506                 pbn_b0_2_1130000 },
4507         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4508                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4509                 pbn_b0_1_921600 },
4510         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4511                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4512                 pbn_b0_4_115200 },
4513         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4514                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4515                 pbn_b0_bt_2_921600 },
4516         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4517                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4518                 pbn_b2_8_1152000 },
4519 
4520         /*
4521          * Oxford Semiconductor Inc. Tornado PCI express device range.
4522          */
4523         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4524                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525                 pbn_b0_1_4000000 },
4526         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4527                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4528                 pbn_b0_1_4000000 },
4529         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4530                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4531                 pbn_oxsemi_1_4000000 },
4532         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4533                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4534                 pbn_oxsemi_1_4000000 },
4535         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4536                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4537                 pbn_b0_1_4000000 },
4538         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4539                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4540                 pbn_b0_1_4000000 },
4541         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4542                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4543                 pbn_oxsemi_1_4000000 },
4544         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4545                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4546                 pbn_oxsemi_1_4000000 },
4547         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4548                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4549                 pbn_b0_1_4000000 },
4550         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4551                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4552                 pbn_b0_1_4000000 },
4553         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4554                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4555                 pbn_b0_1_4000000 },
4556         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4557                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4558                 pbn_b0_1_4000000 },
4559         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4560                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4561                 pbn_oxsemi_2_4000000 },
4562         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4563                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4564                 pbn_oxsemi_2_4000000 },
4565         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4566                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4567                 pbn_oxsemi_4_4000000 },
4568         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4569                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4570                 pbn_oxsemi_4_4000000 },
4571         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4572                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4573                 pbn_oxsemi_8_4000000 },
4574         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4575                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4576                 pbn_oxsemi_8_4000000 },
4577         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4578                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4579                 pbn_oxsemi_1_4000000 },
4580         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4581                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4582                 pbn_oxsemi_1_4000000 },
4583         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4584                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4585                 pbn_oxsemi_1_4000000 },
4586         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4587                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4588                 pbn_oxsemi_1_4000000 },
4589         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4590                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4591                 pbn_oxsemi_1_4000000 },
4592         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4593                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4594                 pbn_oxsemi_1_4000000 },
4595         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4596                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4597                 pbn_oxsemi_1_4000000 },
4598         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4599                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4600                 pbn_oxsemi_1_4000000 },
4601         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4602                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4603                 pbn_oxsemi_1_4000000 },
4604         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4605                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4606                 pbn_oxsemi_1_4000000 },
4607         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4608                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4609                 pbn_oxsemi_1_4000000 },
4610         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4611                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4612                 pbn_oxsemi_1_4000000 },
4613         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4614                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4615                 pbn_oxsemi_1_4000000 },
4616         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4617                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4618                 pbn_oxsemi_1_4000000 },
4619         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4620                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621                 pbn_oxsemi_1_4000000 },
4622         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4623                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4624                 pbn_oxsemi_1_4000000 },
4625         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4626                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627                 pbn_oxsemi_1_4000000 },
4628         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4629                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630                 pbn_oxsemi_1_4000000 },
4631         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4632                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633                 pbn_oxsemi_1_4000000 },
4634         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4635                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636                 pbn_oxsemi_1_4000000 },
4637         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4638                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639                 pbn_oxsemi_1_4000000 },
4640         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4641                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642                 pbn_oxsemi_1_4000000 },
4643         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4644                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4645                 pbn_oxsemi_1_4000000 },
4646         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4647                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648                 pbn_oxsemi_1_4000000 },
4649         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4650                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651                 pbn_oxsemi_1_4000000 },
4652         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4653                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4654                 pbn_oxsemi_1_4000000 },
4655         /*
4656          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4657          */
4658         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4659                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4660                 pbn_oxsemi_1_4000000 },
4661         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4662                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4663                 pbn_oxsemi_2_4000000 },
4664         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4665                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4666                 pbn_oxsemi_4_4000000 },
4667         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4668                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4669                 pbn_oxsemi_8_4000000 },
4670 
4671         /*
4672          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4673          */
4674         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4675                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4676                 pbn_oxsemi_2_4000000 },
4677 
4678         /*
4679          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4680          * from skokodyn@yahoo.com
4681          */
4682         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4683                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4684                 pbn_sbsxrsio },
4685         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4686                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4687                 pbn_sbsxrsio },
4688         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4689                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4690                 pbn_sbsxrsio },
4691         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4692                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4693                 pbn_sbsxrsio },
4694 
4695         /*
4696          * Digitan DS560-558, from jimd@esoft.com
4697          */
4698         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4699                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4700                 pbn_b1_1_115200 },
4701 
4702         /*
4703          * Titan Electronic cards
4704          *  The 400L and 800L have a custom setup quirk.
4705          */
4706         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4707                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708                 pbn_b0_1_921600 },
4709         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4710                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711                 pbn_b0_2_921600 },
4712         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4713                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714                 pbn_b0_4_921600 },
4715         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4716                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4717                 pbn_b0_4_921600 },
4718         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4719                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720                 pbn_b1_1_921600 },
4721         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4722                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4723                 pbn_b1_bt_2_921600 },
4724         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4725                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726                 pbn_b0_bt_4_921600 },
4727         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4728                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4729                 pbn_b0_bt_8_921600 },
4730         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4731                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4732                 pbn_b4_bt_2_921600 },
4733         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4734                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735                 pbn_b4_bt_4_921600 },
4736         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4737                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4738                 pbn_b4_bt_8_921600 },
4739         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4740                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4741                 pbn_b0_4_921600 },
4742         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4743                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4744                 pbn_b0_4_921600 },
4745         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4746                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4747                 pbn_b0_4_921600 },
4748         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4749                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4750                 pbn_oxsemi_1_4000000 },
4751         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4752                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4753                 pbn_oxsemi_2_4000000 },
4754         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4755                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4756                 pbn_oxsemi_4_4000000 },
4757         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4758                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4759                 pbn_oxsemi_8_4000000 },
4760         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4761                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4762                 pbn_oxsemi_2_4000000 },
4763         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4764                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4765                 pbn_oxsemi_2_4000000 },
4766         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4767                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4768                 pbn_b0_bt_2_921600 },
4769         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4770                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4771                 pbn_b0_4_921600 },
4772         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4773                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4774                 pbn_b0_4_921600 },
4775         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4776                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4777                 pbn_b0_4_921600 },
4778         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4779                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780                 pbn_b0_4_921600 },
4781 
4782         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4783                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784                 pbn_b2_1_460800 },
4785         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4786                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787                 pbn_b2_1_460800 },
4788         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4789                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790                 pbn_b2_1_460800 },
4791         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4792                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793                 pbn_b2_bt_2_921600 },
4794         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4795                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796                 pbn_b2_bt_2_921600 },
4797         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4798                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799                 pbn_b2_bt_2_921600 },
4800         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4801                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4802                 pbn_b2_bt_4_921600 },
4803         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4804                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805                 pbn_b2_bt_4_921600 },
4806         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4807                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4808                 pbn_b2_bt_4_921600 },
4809         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4810                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811                 pbn_b0_1_921600 },
4812         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4813                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814                 pbn_b0_1_921600 },
4815         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4816                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4817                 pbn_b0_1_921600 },
4818         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4819                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4820                 pbn_b0_bt_2_921600 },
4821         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4822                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4823                 pbn_b0_bt_2_921600 },
4824         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4825                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4826                 pbn_b0_bt_2_921600 },
4827         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4828                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4829                 pbn_b0_bt_4_921600 },
4830         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4831                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4832                 pbn_b0_bt_4_921600 },
4833         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4834                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4835                 pbn_b0_bt_4_921600 },
4836         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4837                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4838                 pbn_b0_bt_8_921600 },
4839         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4840                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4841                 pbn_b0_bt_8_921600 },
4842         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4843                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4844                 pbn_b0_bt_8_921600 },
4845 
4846         /*
4847          * Computone devices submitted by Doug McNash dmcnash@computone.com
4848          */
4849         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4850                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4851                 0, 0, pbn_computone_4 },
4852         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4853                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4854                 0, 0, pbn_computone_8 },
4855         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4856                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4857                 0, 0, pbn_computone_6 },
4858 
4859         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4860                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4861                 pbn_oxsemi },
4862         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4863                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4864                 pbn_b0_bt_1_921600 },
4865 
4866         /*
4867          * SUNIX (TIMEDIA)
4868          */
4869         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4870                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4871                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4872                 pbn_b0_bt_1_921600 },
4873 
4874         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4875                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4876                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4877                 pbn_b0_bt_1_921600 },
4878 
4879         /*
4880          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4881          */
4882         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4883                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4884                 pbn_b0_bt_8_115200 },
4885         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4886                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4887                 pbn_b0_bt_8_115200 },
4888 
4889         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4890                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891                 pbn_b0_bt_2_115200 },
4892         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4893                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894                 pbn_b0_bt_2_115200 },
4895         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4896                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4897                 pbn_b0_bt_2_115200 },
4898         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4899                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4900                 pbn_b0_bt_2_115200 },
4901         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4902                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4903                 pbn_b0_bt_2_115200 },
4904         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4905                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4906                 pbn_b0_bt_4_460800 },
4907         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4908                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4909                 pbn_b0_bt_4_460800 },
4910         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4911                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4912                 pbn_b0_bt_2_460800 },
4913         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4914                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4915                 pbn_b0_bt_2_460800 },
4916         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4917                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4918                 pbn_b0_bt_2_460800 },
4919         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4920                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4921                 pbn_b0_bt_1_115200 },
4922         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4923                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4924                 pbn_b0_bt_1_460800 },
4925 
4926         /*
4927          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4928          * Cards are identified by their subsystem vendor IDs, which
4929          * (in hex) match the model number.
4930          *
4931          * Note that JC140x are RS422/485 cards which require ox950
4932          * ACR = 0x10, and as such are not currently fully supported.
4933          */
4934         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4935                 0x1204, 0x0004, 0, 0,
4936                 pbn_b0_4_921600 },
4937         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4938                 0x1208, 0x0004, 0, 0,
4939                 pbn_b0_4_921600 },
4940 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4941                 0x1402, 0x0002, 0, 0,
4942                 pbn_b0_2_921600 }, */
4943 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4944                 0x1404, 0x0004, 0, 0,
4945                 pbn_b0_4_921600 }, */
4946         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4947                 0x1208, 0x0004, 0, 0,
4948                 pbn_b0_4_921600 },
4949 
4950         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4951                 0x1204, 0x0004, 0, 0,
4952                 pbn_b0_4_921600 },
4953         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4954                 0x1208, 0x0004, 0, 0,
4955                 pbn_b0_4_921600 },
4956         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4957                 0x1208, 0x0004, 0, 0,
4958                 pbn_b0_4_921600 },
4959         /*
4960          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4961          */
4962         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4963                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4964                 pbn_b1_1_1382400 },
4965 
4966         /*
4967          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4968          */
4969         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4970                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4971                 pbn_b1_1_1382400 },
4972 
4973         /*
4974          * RAStel 2 port modem, gerg@moreton.com.au
4975          */
4976         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4977                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4978                 pbn_b2_bt_2_115200 },
4979 
4980         /*
4981          * EKF addition for i960 Boards form EKF with serial port
4982          */
4983         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4984                 0xE4BF, PCI_ANY_ID, 0, 0,
4985                 pbn_intel_i960 },
4986 
4987         /*
4988          * Xircom Cardbus/Ethernet combos
4989          */
4990         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4991                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4992                 pbn_b0_1_115200 },
4993         /*
4994          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4995          */
4996         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4997                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4998                 pbn_b0_1_115200 },
4999 
5000         /*
5001          * Untested PCI modems, sent in from various folks...
5002          */
5003 
5004         /*
5005          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5006          */
5007         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
5008                 0x1048, 0x1500, 0, 0,
5009                 pbn_b1_1_115200 },
5010 
5011         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5012                 0xFF00, 0, 0, 0,
5013                 pbn_sgi_ioc3 },
5014 
5015         /*
5016          * HP Diva card
5017          */
5018         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5019                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5020                 pbn_b1_1_115200 },
5021         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5022                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5023                 pbn_b0_5_115200 },
5024         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5025                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5026                 pbn_b2_1_115200 },
5027 
5028         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5029                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5030                 pbn_b3_2_115200 },
5031         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5032                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5033                 pbn_b3_4_115200 },
5034         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5035                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5036                 pbn_b3_8_115200 },
5037 
5038         /*
5039          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5040          */
5041         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5042                 PCI_ANY_ID, PCI_ANY_ID,
5043                 0,
5044                 0, pbn_exar_XR17C152 },
5045         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5046                 PCI_ANY_ID, PCI_ANY_ID,
5047                 0,
5048                 0, pbn_exar_XR17C154 },
5049         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5050                 PCI_ANY_ID, PCI_ANY_ID,
5051                 0,
5052                 0, pbn_exar_XR17C158 },
5053         /*
5054          * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5055          */
5056         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5057                 PCI_ANY_ID, PCI_ANY_ID,
5058                 0,
5059                 0, pbn_exar_XR17V352 },
5060         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5061                 PCI_ANY_ID, PCI_ANY_ID,
5062                 0,
5063                 0, pbn_exar_XR17V354 },
5064         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5065                 PCI_ANY_ID, PCI_ANY_ID,
5066                 0,
5067                 0, pbn_exar_XR17V358 },
5068         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5069                 PCI_ANY_ID, PCI_ANY_ID,
5070                 0,
5071                 0, pbn_exar_XR17V4358 },
5072         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5073                 PCI_ANY_ID, PCI_ANY_ID,
5074                 0,
5075                 0, pbn_exar_XR17V8358 },
5076         /*
5077          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5078          */
5079         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5080                 PCI_ANY_ID, PCI_ANY_ID,
5081                 0,
5082                 0, pbn_pericom_PI7C9X7951 },
5083         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5084                 PCI_ANY_ID, PCI_ANY_ID,
5085                 0,
5086                 0, pbn_pericom_PI7C9X7952 },
5087         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5088                 PCI_ANY_ID, PCI_ANY_ID,
5089                 0,
5090                 0, pbn_pericom_PI7C9X7954 },
5091         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5092                 PCI_ANY_ID, PCI_ANY_ID,
5093                 0,
5094                 0, pbn_pericom_PI7C9X7958 },
5095         /*
5096          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5097          */
5098         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5099                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5100                 pbn_b0_1_115200 },
5101         /*
5102          * ITE
5103          */
5104         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5105                 PCI_ANY_ID, PCI_ANY_ID,
5106                 0, 0,
5107                 pbn_b1_bt_1_115200 },
5108 
5109         /*
5110          * IntaShield IS-200
5111          */
5112         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5113                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
5114                 pbn_b2_2_115200 },
5115         /*
5116          * IntaShield IS-400
5117          */
5118         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5119                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
5120                 pbn_b2_4_115200 },
5121         /*
5122          * Perle PCI-RAS cards
5123          */
5124         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5125                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5126                 0, 0, pbn_b2_4_921600 },
5127         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5128                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5129                 0, 0, pbn_b2_8_921600 },
5130 
5131         /*
5132          * Mainpine series cards: Fairly standard layout but fools
5133          * parts of the autodetect in some cases and uses otherwise
5134          * unmatched communications subclasses in the PCI Express case
5135          */
5136 
5137         {       /* RockForceDUO */
5138                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5139                 PCI_VENDOR_ID_MAINPINE, 0x0200,
5140                 0, 0, pbn_b0_2_115200 },
5141         {       /* RockForceQUATRO */
5142                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5143                 PCI_VENDOR_ID_MAINPINE, 0x0300,
5144                 0, 0, pbn_b0_4_115200 },
5145         {       /* RockForceDUO+ */
5146                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5147                 PCI_VENDOR_ID_MAINPINE, 0x0400,
5148                 0, 0, pbn_b0_2_115200 },
5149         {       /* RockForceQUATRO+ */
5150                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5151                 PCI_VENDOR_ID_MAINPINE, 0x0500,
5152                 0, 0, pbn_b0_4_115200 },
5153         {       /* RockForce+ */
5154                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5155                 PCI_VENDOR_ID_MAINPINE, 0x0600,
5156                 0, 0, pbn_b0_2_115200 },
5157         {       /* RockForce+ */
5158                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5159                 PCI_VENDOR_ID_MAINPINE, 0x0700,
5160                 0, 0, pbn_b0_4_115200 },
5161         {       /* RockForceOCTO+ */
5162                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5163                 PCI_VENDOR_ID_MAINPINE, 0x0800,
5164                 0, 0, pbn_b0_8_115200 },
5165         {       /* RockForceDUO+ */
5166                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5167                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5168                 0, 0, pbn_b0_2_115200 },
5169         {       /* RockForceQUARTRO+ */
5170                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5171                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5172                 0, 0, pbn_b0_4_115200 },
5173         {       /* RockForceOCTO+ */
5174                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5175                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5176                 0, 0, pbn_b0_8_115200 },
5177         {       /* RockForceD1 */
5178                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5179                 PCI_VENDOR_ID_MAINPINE, 0x2000,
5180                 0, 0, pbn_b0_1_115200 },
5181         {       /* RockForceF1 */
5182                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5183                 PCI_VENDOR_ID_MAINPINE, 0x2100,
5184                 0, 0, pbn_b0_1_115200 },
5185         {       /* RockForceD2 */
5186                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5187                 PCI_VENDOR_ID_MAINPINE, 0x2200,
5188                 0, 0, pbn_b0_2_115200 },
5189         {       /* RockForceF2 */
5190                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5191                 PCI_VENDOR_ID_MAINPINE, 0x2300,
5192                 0, 0, pbn_b0_2_115200 },
5193         {       /* RockForceD4 */
5194                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5195                 PCI_VENDOR_ID_MAINPINE, 0x2400,
5196                 0, 0, pbn_b0_4_115200 },
5197         {       /* RockForceF4 */
5198                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5199                 PCI_VENDOR_ID_MAINPINE, 0x2500,
5200                 0, 0, pbn_b0_4_115200 },
5201         {       /* RockForceD8 */
5202                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5203                 PCI_VENDOR_ID_MAINPINE, 0x2600,
5204                 0, 0, pbn_b0_8_115200 },
5205         {       /* RockForceF8 */
5206                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5207                 PCI_VENDOR_ID_MAINPINE, 0x2700,
5208                 0, 0, pbn_b0_8_115200 },
5209         {       /* IQ Express D1 */
5210                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5211                 PCI_VENDOR_ID_MAINPINE, 0x3000,
5212                 0, 0, pbn_b0_1_115200 },
5213         {       /* IQ Express F1 */
5214                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5215                 PCI_VENDOR_ID_MAINPINE, 0x3100,
5216                 0, 0, pbn_b0_1_115200 },
5217         {       /* IQ Express D2 */
5218                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5219                 PCI_VENDOR_ID_MAINPINE, 0x3200,
5220                 0, 0, pbn_b0_2_115200 },
5221         {       /* IQ Express F2 */
5222                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5223                 PCI_VENDOR_ID_MAINPINE, 0x3300,
5224                 0, 0, pbn_b0_2_115200 },
5225         {       /* IQ Express D4 */
5226                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5227                 PCI_VENDOR_ID_MAINPINE, 0x3400,
5228                 0, 0, pbn_b0_4_115200 },
5229         {       /* IQ Express F4 */
5230                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5231                 PCI_VENDOR_ID_MAINPINE, 0x3500,
5232                 0, 0, pbn_b0_4_115200 },
5233         {       /* IQ Express D8 */
5234                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5235                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5236                 0, 0, pbn_b0_8_115200 },
5237         {       /* IQ Express F8 */
5238                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5239                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5240                 0, 0, pbn_b0_8_115200 },
5241 
5242 
5243         /*
5244          * PA Semi PA6T-1682M on-chip UART
5245          */
5246         {       PCI_VENDOR_ID_PASEMI, 0xa004,
5247                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5248                 pbn_pasemi_1682M },
5249 
5250         /*
5251          * National Instruments
5252          */
5253         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5254                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5255                 pbn_b1_16_115200 },
5256         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5257                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5258                 pbn_b1_8_115200 },
5259         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5260                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5261                 pbn_b1_bt_4_115200 },
5262         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5263                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5264                 pbn_b1_bt_2_115200 },
5265         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5266                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5267                 pbn_b1_bt_4_115200 },
5268         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5269                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5270                 pbn_b1_bt_2_115200 },
5271         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5272                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5273                 pbn_b1_16_115200 },
5274         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5275                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5276                 pbn_b1_8_115200 },
5277         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5278                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5279                 pbn_b1_bt_4_115200 },
5280         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5281                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5282                 pbn_b1_bt_2_115200 },
5283         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5284                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5285                 pbn_b1_bt_4_115200 },
5286         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5287                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5288                 pbn_b1_bt_2_115200 },
5289         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5290                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5291                 pbn_ni8430_2 },
5292         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5293                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5294                 pbn_ni8430_2 },
5295         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5296                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5297                 pbn_ni8430_4 },
5298         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5299                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5300                 pbn_ni8430_4 },
5301         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5302                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5303                 pbn_ni8430_8 },
5304         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5305                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5306                 pbn_ni8430_8 },
5307         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5308                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5309                 pbn_ni8430_16 },
5310         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5311                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5312                 pbn_ni8430_16 },
5313         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5314                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5315                 pbn_ni8430_2 },
5316         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5317                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5318                 pbn_ni8430_2 },
5319         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5320                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5321                 pbn_ni8430_4 },
5322         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5323                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5324                 pbn_ni8430_4 },
5325 
5326         /*
5327         * ADDI-DATA GmbH communication cards <info@addi-data.com>
5328         */
5329         {       PCI_VENDOR_ID_ADDIDATA,
5330                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5331                 PCI_ANY_ID,
5332                 PCI_ANY_ID,
5333                 0,
5334                 0,
5335                 pbn_b0_4_115200 },
5336 
5337         {       PCI_VENDOR_ID_ADDIDATA,
5338                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5339                 PCI_ANY_ID,
5340                 PCI_ANY_ID,
5341                 0,
5342                 0,
5343                 pbn_b0_2_115200 },
5344 
5345         {       PCI_VENDOR_ID_ADDIDATA,
5346                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5347                 PCI_ANY_ID,
5348                 PCI_ANY_ID,
5349                 0,
5350                 0,
5351                 pbn_b0_1_115200 },
5352 
5353         {       PCI_VENDOR_ID_AMCC,
5354                 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5355                 PCI_ANY_ID,
5356                 PCI_ANY_ID,
5357                 0,
5358                 0,
5359                 pbn_b1_8_115200 },
5360 
5361         {       PCI_VENDOR_ID_ADDIDATA,
5362                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5363                 PCI_ANY_ID,
5364                 PCI_ANY_ID,
5365                 0,
5366                 0,
5367                 pbn_b0_4_115200 },
5368 
5369         {       PCI_VENDOR_ID_ADDIDATA,
5370                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5371                 PCI_ANY_ID,
5372                 PCI_ANY_ID,
5373                 0,
5374                 0,
5375                 pbn_b0_2_115200 },
5376 
5377         {       PCI_VENDOR_ID_ADDIDATA,
5378                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5379                 PCI_ANY_ID,
5380                 PCI_ANY_ID,
5381                 0,
5382                 0,
5383                 pbn_b0_1_115200 },
5384 
5385         {       PCI_VENDOR_ID_ADDIDATA,
5386                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5387                 PCI_ANY_ID,
5388                 PCI_ANY_ID,
5389                 0,
5390                 0,
5391                 pbn_b0_4_115200 },
5392 
5393         {       PCI_VENDOR_ID_ADDIDATA,
5394                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5395                 PCI_ANY_ID,
5396                 PCI_ANY_ID,
5397                 0,
5398                 0,
5399                 pbn_b0_2_115200 },
5400 
5401         {       PCI_VENDOR_ID_ADDIDATA,
5402                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5403                 PCI_ANY_ID,
5404                 PCI_ANY_ID,
5405                 0,
5406                 0,
5407                 pbn_b0_1_115200 },
5408 
5409         {       PCI_VENDOR_ID_ADDIDATA,
5410                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5411                 PCI_ANY_ID,
5412                 PCI_ANY_ID,
5413                 0,
5414                 0,
5415                 pbn_b0_8_115200 },
5416 
5417         {       PCI_VENDOR_ID_ADDIDATA,
5418                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5419                 PCI_ANY_ID,
5420                 PCI_ANY_ID,
5421                 0,
5422                 0,
5423                 pbn_ADDIDATA_PCIe_4_3906250 },
5424 
5425         {       PCI_VENDOR_ID_ADDIDATA,
5426                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5427                 PCI_ANY_ID,
5428                 PCI_ANY_ID,
5429                 0,
5430                 0,
5431                 pbn_ADDIDATA_PCIe_2_3906250 },
5432 
5433         {       PCI_VENDOR_ID_ADDIDATA,
5434                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5435                 PCI_ANY_ID,
5436                 PCI_ANY_ID,
5437                 0,
5438                 0,
5439                 pbn_ADDIDATA_PCIe_1_3906250 },
5440 
5441         {       PCI_VENDOR_ID_ADDIDATA,
5442                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5443                 PCI_ANY_ID,
5444                 PCI_ANY_ID,
5445                 0,
5446                 0,
5447                 pbn_ADDIDATA_PCIe_8_3906250 },
5448 
5449         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5450                 PCI_VENDOR_ID_IBM, 0x0299,
5451                 0, 0, pbn_b0_bt_2_115200 },
5452 
5453         /*
5454          * other NetMos 9835 devices are most likely handled by the
5455          * parport_serial driver, check drivers/parport/parport_serial.c
5456          * before adding them here.
5457          */
5458 
5459         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5460                 0xA000, 0x1000,
5461                 0, 0, pbn_b0_1_115200 },
5462 
5463         /* the 9901 is a rebranded 9912 */
5464         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5465                 0xA000, 0x1000,
5466                 0, 0, pbn_b0_1_115200 },
5467 
5468         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5469                 0xA000, 0x1000,
5470                 0, 0, pbn_b0_1_115200 },
5471 
5472         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5473                 0xA000, 0x1000,
5474                 0, 0, pbn_b0_1_115200 },
5475 
5476         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5477                 0xA000, 0x1000,
5478                 0, 0, pbn_b0_1_115200 },
5479 
5480         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5481                 0xA000, 0x3002,
5482                 0, 0, pbn_NETMOS9900_2s_115200 },
5483 
5484         /*
5485          * Best Connectivity and Rosewill PCI Multi I/O cards
5486          */
5487 
5488         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5489                 0xA000, 0x1000,
5490                 0, 0, pbn_b0_1_115200 },
5491 
5492         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5493                 0xA000, 0x3002,
5494                 0, 0, pbn_b0_bt_2_115200 },
5495 
5496         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5497                 0xA000, 0x3004,
5498                 0, 0, pbn_b0_bt_4_115200 },
5499         /* Intel CE4100 */
5500         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5501                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5502                 pbn_ce4100_1_115200 },
5503         /* Intel BayTrail */
5504         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5505                 PCI_ANY_ID,  PCI_ANY_ID,
5506                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5507                 pbn_byt },
5508         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5509                 PCI_ANY_ID,  PCI_ANY_ID,
5510                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5511                 pbn_byt },
5512         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5513                 PCI_ANY_ID,  PCI_ANY_ID,
5514                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5515                 pbn_byt },
5516         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5517                 PCI_ANY_ID,  PCI_ANY_ID,
5518                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5519                 pbn_byt },
5520 
5521         /* Intel Broadwell */
5522         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1,
5523                 PCI_ANY_ID,  PCI_ANY_ID,
5524                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5525                 pbn_byt },
5526         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2,
5527                 PCI_ANY_ID,  PCI_ANY_ID,
5528                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5529                 pbn_byt },
5530 
5531         /*
5532          * Intel Quark x1000
5533          */
5534         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5535                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5536                 pbn_qrk },
5537         /*
5538          * Cronyx Omega PCI
5539          */
5540         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5541                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5542                 pbn_omegapci },
5543 
5544         /*
5545          * Broadcom TruManage
5546          */
5547         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5548                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5549                 pbn_brcm_trumanage },
5550 
5551         /*
5552          * AgeStar as-prs2-009
5553          */
5554         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5555                 PCI_ANY_ID, PCI_ANY_ID,
5556                 0, 0, pbn_b0_bt_2_115200 },
5557 
5558         /*
5559          * WCH CH353 series devices: The 2S1P is handled by parport_serial
5560          * so not listed here.
5561          */
5562         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5563                 PCI_ANY_ID, PCI_ANY_ID,
5564                 0, 0, pbn_b0_bt_4_115200 },
5565 
5566         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5567                 PCI_ANY_ID, PCI_ANY_ID,
5568                 0, 0, pbn_b0_bt_2_115200 },
5569 
5570         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5571                 PCI_ANY_ID, PCI_ANY_ID,
5572                 0, 0, pbn_wch382_2 },
5573 
5574         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5575                 PCI_ANY_ID, PCI_ANY_ID,
5576                 0, 0, pbn_wch384_4 },
5577 
5578         /*
5579          * Commtech, Inc. Fastcom adapters
5580          */
5581         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5582                 PCI_ANY_ID, PCI_ANY_ID,
5583                 0,
5584                 0, pbn_b0_2_1152000_200 },
5585         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5586                 PCI_ANY_ID, PCI_ANY_ID,
5587                 0,
5588                 0, pbn_b0_4_1152000_200 },
5589         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5590                 PCI_ANY_ID, PCI_ANY_ID,
5591                 0,
5592                 0, pbn_b0_4_1152000_200 },
5593         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5594                 PCI_ANY_ID, PCI_ANY_ID,
5595                 0,
5596                 0, pbn_b0_8_1152000_200 },
5597         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5598                 PCI_ANY_ID, PCI_ANY_ID,
5599                 0,
5600                 0, pbn_exar_XR17V352 },
5601         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5602                 PCI_ANY_ID, PCI_ANY_ID,
5603                 0,
5604                 0, pbn_exar_XR17V354 },
5605         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5606                 PCI_ANY_ID, PCI_ANY_ID,
5607                 0,
5608                 0, pbn_exar_XR17V358 },
5609 
5610         /* Fintek PCI serial cards */
5611         { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5612         { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5613         { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5614 
5615         /*
5616          * These entries match devices with class COMMUNICATION_SERIAL,
5617          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5618          */
5619         {       PCI_ANY_ID, PCI_ANY_ID,
5620                 PCI_ANY_ID, PCI_ANY_ID,
5621                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5622                 0xffff00, pbn_default },
5623         {       PCI_ANY_ID, PCI_ANY_ID,
5624                 PCI_ANY_ID, PCI_ANY_ID,
5625                 PCI_CLASS_COMMUNICATION_MODEM << 8,
5626                 0xffff00, pbn_default },
5627         {       PCI_ANY_ID, PCI_ANY_ID,
5628                 PCI_ANY_ID, PCI_ANY_ID,
5629                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5630                 0xffff00, pbn_default },
5631         { 0, }
5632 };
5633 
5634 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5635                                                 pci_channel_state_t state)
5636 {
5637         struct serial_private *priv = pci_get_drvdata(dev);
5638 
5639         if (state == pci_channel_io_perm_failure)
5640                 return PCI_ERS_RESULT_DISCONNECT;
5641 
5642         if (priv)
5643                 pciserial_suspend_ports(priv);
5644 
5645         pci_disable_device(dev);
5646 
5647         return PCI_ERS_RESULT_NEED_RESET;
5648 }
5649 
5650 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5651 {
5652         int rc;
5653 
5654         rc = pci_enable_device(dev);
5655 
5656         if (rc)
5657                 return PCI_ERS_RESULT_DISCONNECT;
5658 
5659         pci_restore_state(dev);
5660         pci_save_state(dev);
5661 
5662         return PCI_ERS_RESULT_RECOVERED;
5663 }
5664 
5665 static void serial8250_io_resume(struct pci_dev *dev)
5666 {
5667         struct serial_private *priv = pci_get_drvdata(dev);
5668 
5669         if (priv)
5670                 pciserial_resume_ports(priv);
5671 }
5672 
5673 static const struct pci_error_handlers serial8250_err_handler = {
5674         .error_detected = serial8250_io_error_detected,
5675         .slot_reset = serial8250_io_slot_reset,
5676         .resume = serial8250_io_resume,
5677 };
5678 
5679 static struct pci_driver serial_pci_driver = {
5680         .name           = "serial",
5681         .probe          = pciserial_init_one,
5682         .remove         = pciserial_remove_one,
5683         .driver         = {
5684                 .pm     = &pciserial_pm_ops,
5685         },
5686         .id_table       = serial_pci_tbl,
5687         .err_handler    = &serial8250_err_handler,
5688 };
5689 
5690 module_pci_driver(serial_pci_driver);
5691 
5692 MODULE_LICENSE("GPL");
5693 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5694 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
5695 

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