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Linux/drivers/tty/serial/8250/8250_pci.c

  1 /*
  2  *  Probe module for 8250/16550-type PCI serial ports.
  3  *
  4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  5  *
  6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License.
 11  */
 12 #undef DEBUG
 13 #include <linux/module.h>
 14 #include <linux/pci.h>
 15 #include <linux/string.h>
 16 #include <linux/kernel.h>
 17 #include <linux/slab.h>
 18 #include <linux/delay.h>
 19 #include <linux/tty.h>
 20 #include <linux/serial_reg.h>
 21 #include <linux/serial_core.h>
 22 #include <linux/8250_pci.h>
 23 #include <linux/bitops.h>
 24 #include <linux/rational.h>
 25 
 26 #include <asm/byteorder.h>
 27 #include <asm/io.h>
 28 
 29 #include <linux/dmaengine.h>
 30 #include <linux/platform_data/dma-dw.h>
 31 
 32 #include "8250.h"
 33 
 34 /*
 35  * init function returns:
 36  *  > 0 - number of ports
 37  *  = 0 - use board->num_ports
 38  *  < 0 - error
 39  */
 40 struct pci_serial_quirk {
 41         u32     vendor;
 42         u32     device;
 43         u32     subvendor;
 44         u32     subdevice;
 45         int     (*probe)(struct pci_dev *dev);
 46         int     (*init)(struct pci_dev *dev);
 47         int     (*setup)(struct serial_private *,
 48                          const struct pciserial_board *,
 49                          struct uart_8250_port *, int);
 50         void    (*exit)(struct pci_dev *dev);
 51 };
 52 
 53 #define PCI_NUM_BAR_RESOURCES   6
 54 
 55 struct serial_private {
 56         struct pci_dev          *dev;
 57         unsigned int            nr;
 58         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
 59         struct pci_serial_quirk *quirk;
 60         int                     line[0];
 61 };
 62 
 63 static int pci_default_setup(struct serial_private*,
 64           const struct pciserial_board*, struct uart_8250_port *, int);
 65 
 66 static void moan_device(const char *str, struct pci_dev *dev)
 67 {
 68         dev_err(&dev->dev,
 69                "%s: %s\n"
 70                "Please send the output of lspci -vv, this\n"
 71                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
 72                "manufacturer and name of serial board or\n"
 73                "modem board to <linux-serial@vger.kernel.org>.\n",
 74                pci_name(dev), str, dev->vendor, dev->device,
 75                dev->subsystem_vendor, dev->subsystem_device);
 76 }
 77 
 78 static int
 79 setup_port(struct serial_private *priv, struct uart_8250_port *port,
 80            int bar, int offset, int regshift)
 81 {
 82         struct pci_dev *dev = priv->dev;
 83 
 84         if (bar >= PCI_NUM_BAR_RESOURCES)
 85                 return -EINVAL;
 86 
 87         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
 88                 if (!priv->remapped_bar[bar])
 89                         priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
 90                 if (!priv->remapped_bar[bar])
 91                         return -ENOMEM;
 92 
 93                 port->port.iotype = UPIO_MEM;
 94                 port->port.iobase = 0;
 95                 port->port.mapbase = pci_resource_start(dev, bar) + offset;
 96                 port->port.membase = priv->remapped_bar[bar] + offset;
 97                 port->port.regshift = regshift;
 98         } else {
 99                 port->port.iotype = UPIO_PORT;
100                 port->port.iobase = pci_resource_start(dev, bar) + offset;
101                 port->port.mapbase = 0;
102                 port->port.membase = NULL;
103                 port->port.regshift = 0;
104         }
105         return 0;
106 }
107 
108 /*
109  * ADDI-DATA GmbH communication cards <info@addi-data.com>
110  */
111 static int addidata_apci7800_setup(struct serial_private *priv,
112                                 const struct pciserial_board *board,
113                                 struct uart_8250_port *port, int idx)
114 {
115         unsigned int bar = 0, offset = board->first_offset;
116         bar = FL_GET_BASE(board->flags);
117 
118         if (idx < 2) {
119                 offset += idx * board->uart_offset;
120         } else if ((idx >= 2) && (idx < 4)) {
121                 bar += 1;
122                 offset += ((idx - 2) * board->uart_offset);
123         } else if ((idx >= 4) && (idx < 6)) {
124                 bar += 2;
125                 offset += ((idx - 4) * board->uart_offset);
126         } else if (idx >= 6) {
127                 bar += 3;
128                 offset += ((idx - 6) * board->uart_offset);
129         }
130 
131         return setup_port(priv, port, bar, offset, board->reg_shift);
132 }
133 
134 /*
135  * AFAVLAB uses a different mixture of BARs and offsets
136  * Not that ugly ;) -- HW
137  */
138 static int
139 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
140               struct uart_8250_port *port, int idx)
141 {
142         unsigned int bar, offset = board->first_offset;
143 
144         bar = FL_GET_BASE(board->flags);
145         if (idx < 4)
146                 bar += idx;
147         else {
148                 bar = 4;
149                 offset += (idx - 4) * board->uart_offset;
150         }
151 
152         return setup_port(priv, port, bar, offset, board->reg_shift);
153 }
154 
155 /*
156  * HP's Remote Management Console.  The Diva chip came in several
157  * different versions.  N-class, L2000 and A500 have two Diva chips, each
158  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
159  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
160  * one Diva chip, but it has been expanded to 5 UARTs.
161  */
162 static int pci_hp_diva_init(struct pci_dev *dev)
163 {
164         int rc = 0;
165 
166         switch (dev->subsystem_device) {
167         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
168         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
169         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
170         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
171                 rc = 3;
172                 break;
173         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
174                 rc = 2;
175                 break;
176         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
177                 rc = 4;
178                 break;
179         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
180         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
181                 rc = 1;
182                 break;
183         }
184 
185         return rc;
186 }
187 
188 /*
189  * HP's Diva chip puts the 4th/5th serial port further out, and
190  * some serial ports are supposed to be hidden on certain models.
191  */
192 static int
193 pci_hp_diva_setup(struct serial_private *priv,
194                 const struct pciserial_board *board,
195                 struct uart_8250_port *port, int idx)
196 {
197         unsigned int offset = board->first_offset;
198         unsigned int bar = FL_GET_BASE(board->flags);
199 
200         switch (priv->dev->subsystem_device) {
201         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
202                 if (idx == 3)
203                         idx++;
204                 break;
205         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
206                 if (idx > 0)
207                         idx++;
208                 if (idx > 2)
209                         idx++;
210                 break;
211         }
212         if (idx > 2)
213                 offset = 0x18;
214 
215         offset += idx * board->uart_offset;
216 
217         return setup_port(priv, port, bar, offset, board->reg_shift);
218 }
219 
220 /*
221  * Added for EKF Intel i960 serial boards
222  */
223 static int pci_inteli960ni_init(struct pci_dev *dev)
224 {
225         u32 oldval;
226 
227         if (!(dev->subsystem_device & 0x1000))
228                 return -ENODEV;
229 
230         /* is firmware started? */
231         pci_read_config_dword(dev, 0x44, &oldval);
232         if (oldval == 0x00001000L) { /* RESET value */
233                 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
234                 return -ENODEV;
235         }
236         return 0;
237 }
238 
239 /*
240  * Some PCI serial cards using the PLX 9050 PCI interface chip require
241  * that the card interrupt be explicitly enabled or disabled.  This
242  * seems to be mainly needed on card using the PLX which also use I/O
243  * mapped memory.
244  */
245 static int pci_plx9050_init(struct pci_dev *dev)
246 {
247         u8 irq_config;
248         void __iomem *p;
249 
250         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
251                 moan_device("no memory in bar 0", dev);
252                 return 0;
253         }
254 
255         irq_config = 0x41;
256         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
257             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
258                 irq_config = 0x43;
259 
260         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
261             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
262                 /*
263                  * As the megawolf cards have the int pins active
264                  * high, and have 2 UART chips, both ints must be
265                  * enabled on the 9050. Also, the UARTS are set in
266                  * 16450 mode by default, so we have to enable the
267                  * 16C950 'enhanced' mode so that we can use the
268                  * deep FIFOs
269                  */
270                 irq_config = 0x5b;
271         /*
272          * enable/disable interrupts
273          */
274         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
275         if (p == NULL)
276                 return -ENOMEM;
277         writel(irq_config, p + 0x4c);
278 
279         /*
280          * Read the register back to ensure that it took effect.
281          */
282         readl(p + 0x4c);
283         iounmap(p);
284 
285         return 0;
286 }
287 
288 static void pci_plx9050_exit(struct pci_dev *dev)
289 {
290         u8 __iomem *p;
291 
292         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
293                 return;
294 
295         /*
296          * disable interrupts
297          */
298         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
299         if (p != NULL) {
300                 writel(0, p + 0x4c);
301 
302                 /*
303                  * Read the register back to ensure that it took effect.
304                  */
305                 readl(p + 0x4c);
306                 iounmap(p);
307         }
308 }
309 
310 #define NI8420_INT_ENABLE_REG   0x38
311 #define NI8420_INT_ENABLE_BIT   0x2000
312 
313 static void pci_ni8420_exit(struct pci_dev *dev)
314 {
315         void __iomem *p;
316         unsigned int bar = 0;
317 
318         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
319                 moan_device("no memory in bar", dev);
320                 return;
321         }
322 
323         p = pci_ioremap_bar(dev, bar);
324         if (p == NULL)
325                 return;
326 
327         /* Disable the CPU Interrupt */
328         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
329                p + NI8420_INT_ENABLE_REG);
330         iounmap(p);
331 }
332 
333 
334 /* MITE registers */
335 #define MITE_IOWBSR1    0xc4
336 #define MITE_IOWCR1     0xf4
337 #define MITE_LCIMR1     0x08
338 #define MITE_LCIMR2     0x10
339 
340 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
341 
342 static void pci_ni8430_exit(struct pci_dev *dev)
343 {
344         void __iomem *p;
345         unsigned int bar = 0;
346 
347         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
348                 moan_device("no memory in bar", dev);
349                 return;
350         }
351 
352         p = pci_ioremap_bar(dev, bar);
353         if (p == NULL)
354                 return;
355 
356         /* Disable the CPU Interrupt */
357         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
358         iounmap(p);
359 }
360 
361 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
362 static int
363 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
364                 struct uart_8250_port *port, int idx)
365 {
366         unsigned int bar, offset = board->first_offset;
367 
368         bar = 0;
369 
370         if (idx < 4) {
371                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
372                 offset += idx * board->uart_offset;
373         } else if (idx < 8) {
374                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
375                 offset += idx * board->uart_offset + 0xC00;
376         } else /* we have only 8 ports on PMC-OCTALPRO */
377                 return 1;
378 
379         return setup_port(priv, port, bar, offset, board->reg_shift);
380 }
381 
382 /*
383 * This does initialization for PMC OCTALPRO cards:
384 * maps the device memory, resets the UARTs (needed, bc
385 * if the module is removed and inserted again, the card
386 * is in the sleep mode) and enables global interrupt.
387 */
388 
389 /* global control register offset for SBS PMC-OctalPro */
390 #define OCT_REG_CR_OFF          0x500
391 
392 static int sbs_init(struct pci_dev *dev)
393 {
394         u8 __iomem *p;
395 
396         p = pci_ioremap_bar(dev, 0);
397 
398         if (p == NULL)
399                 return -ENOMEM;
400         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
401         writeb(0x10, p + OCT_REG_CR_OFF);
402         udelay(50);
403         writeb(0x0, p + OCT_REG_CR_OFF);
404 
405         /* Set bit-2 (INTENABLE) of Control Register */
406         writeb(0x4, p + OCT_REG_CR_OFF);
407         iounmap(p);
408 
409         return 0;
410 }
411 
412 /*
413  * Disables the global interrupt of PMC-OctalPro
414  */
415 
416 static void sbs_exit(struct pci_dev *dev)
417 {
418         u8 __iomem *p;
419 
420         p = pci_ioremap_bar(dev, 0);
421         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
422         if (p != NULL)
423                 writeb(0, p + OCT_REG_CR_OFF);
424         iounmap(p);
425 }
426 
427 /*
428  * SIIG serial cards have an PCI interface chip which also controls
429  * the UART clocking frequency. Each UART can be clocked independently
430  * (except cards equipped with 4 UARTs) and initial clocking settings
431  * are stored in the EEPROM chip. It can cause problems because this
432  * version of serial driver doesn't support differently clocked UART's
433  * on single PCI card. To prevent this, initialization functions set
434  * high frequency clocking for all UART's on given card. It is safe (I
435  * hope) because it doesn't touch EEPROM settings to prevent conflicts
436  * with other OSes (like M$ DOS).
437  *
438  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
439  *
440  * There is two family of SIIG serial cards with different PCI
441  * interface chip and different configuration methods:
442  *     - 10x cards have control registers in IO and/or memory space;
443  *     - 20x cards have control registers in standard PCI configuration space.
444  *
445  * Note: all 10x cards have PCI device ids 0x10..
446  *       all 20x cards have PCI device ids 0x20..
447  *
448  * There are also Quartet Serial cards which use Oxford Semiconductor
449  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
450  *
451  * Note: some SIIG cards are probed by the parport_serial object.
452  */
453 
454 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
455 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
456 
457 static int pci_siig10x_init(struct pci_dev *dev)
458 {
459         u16 data;
460         void __iomem *p;
461 
462         switch (dev->device & 0xfff8) {
463         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
464                 data = 0xffdf;
465                 break;
466         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
467                 data = 0xf7ff;
468                 break;
469         default:                        /* 1S1P, 4S */
470                 data = 0xfffb;
471                 break;
472         }
473 
474         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
475         if (p == NULL)
476                 return -ENOMEM;
477 
478         writew(readw(p + 0x28) & data, p + 0x28);
479         readw(p + 0x28);
480         iounmap(p);
481         return 0;
482 }
483 
484 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
485 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
486 
487 static int pci_siig20x_init(struct pci_dev *dev)
488 {
489         u8 data;
490 
491         /* Change clock frequency for the first UART. */
492         pci_read_config_byte(dev, 0x6f, &data);
493         pci_write_config_byte(dev, 0x6f, data & 0xef);
494 
495         /* If this card has 2 UART, we have to do the same with second UART. */
496         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
497             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
498                 pci_read_config_byte(dev, 0x73, &data);
499                 pci_write_config_byte(dev, 0x73, data & 0xef);
500         }
501         return 0;
502 }
503 
504 static int pci_siig_init(struct pci_dev *dev)
505 {
506         unsigned int type = dev->device & 0xff00;
507 
508         if (type == 0x1000)
509                 return pci_siig10x_init(dev);
510         else if (type == 0x2000)
511                 return pci_siig20x_init(dev);
512 
513         moan_device("Unknown SIIG card", dev);
514         return -ENODEV;
515 }
516 
517 static int pci_siig_setup(struct serial_private *priv,
518                           const struct pciserial_board *board,
519                           struct uart_8250_port *port, int idx)
520 {
521         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
522 
523         if (idx > 3) {
524                 bar = 4;
525                 offset = (idx - 4) * 8;
526         }
527 
528         return setup_port(priv, port, bar, offset, 0);
529 }
530 
531 /*
532  * Timedia has an explosion of boards, and to avoid the PCI table from
533  * growing *huge*, we use this function to collapse some 70 entries
534  * in the PCI table into one, for sanity's and compactness's sake.
535  */
536 static const unsigned short timedia_single_port[] = {
537         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
538 };
539 
540 static const unsigned short timedia_dual_port[] = {
541         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
542         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
543         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
544         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
545         0xD079, 0
546 };
547 
548 static const unsigned short timedia_quad_port[] = {
549         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
550         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
551         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
552         0xB157, 0
553 };
554 
555 static const unsigned short timedia_eight_port[] = {
556         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
557         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
558 };
559 
560 static const struct timedia_struct {
561         int num;
562         const unsigned short *ids;
563 } timedia_data[] = {
564         { 1, timedia_single_port },
565         { 2, timedia_dual_port },
566         { 4, timedia_quad_port },
567         { 8, timedia_eight_port }
568 };
569 
570 /*
571  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
572  * listing them individually, this driver merely grabs them all with
573  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
574  * and should be left free to be claimed by parport_serial instead.
575  */
576 static int pci_timedia_probe(struct pci_dev *dev)
577 {
578         /*
579          * Check the third digit of the subdevice ID
580          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
581          */
582         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
583                 dev_info(&dev->dev,
584                         "ignoring Timedia subdevice %04x for parport_serial\n",
585                         dev->subsystem_device);
586                 return -ENODEV;
587         }
588 
589         return 0;
590 }
591 
592 static int pci_timedia_init(struct pci_dev *dev)
593 {
594         const unsigned short *ids;
595         int i, j;
596 
597         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
598                 ids = timedia_data[i].ids;
599                 for (j = 0; ids[j]; j++)
600                         if (dev->subsystem_device == ids[j])
601                                 return timedia_data[i].num;
602         }
603         return 0;
604 }
605 
606 /*
607  * Timedia/SUNIX uses a mixture of BARs and offsets
608  * Ugh, this is ugly as all hell --- TYT
609  */
610 static int
611 pci_timedia_setup(struct serial_private *priv,
612                   const struct pciserial_board *board,
613                   struct uart_8250_port *port, int idx)
614 {
615         unsigned int bar = 0, offset = board->first_offset;
616 
617         switch (idx) {
618         case 0:
619                 bar = 0;
620                 break;
621         case 1:
622                 offset = board->uart_offset;
623                 bar = 0;
624                 break;
625         case 2:
626                 bar = 1;
627                 break;
628         case 3:
629                 offset = board->uart_offset;
630                 /* FALLTHROUGH */
631         case 4: /* BAR 2 */
632         case 5: /* BAR 3 */
633         case 6: /* BAR 4 */
634         case 7: /* BAR 5 */
635                 bar = idx - 2;
636         }
637 
638         return setup_port(priv, port, bar, offset, board->reg_shift);
639 }
640 
641 /*
642  * Some Titan cards are also a little weird
643  */
644 static int
645 titan_400l_800l_setup(struct serial_private *priv,
646                       const struct pciserial_board *board,
647                       struct uart_8250_port *port, int idx)
648 {
649         unsigned int bar, offset = board->first_offset;
650 
651         switch (idx) {
652         case 0:
653                 bar = 1;
654                 break;
655         case 1:
656                 bar = 2;
657                 break;
658         default:
659                 bar = 4;
660                 offset = (idx - 2) * board->uart_offset;
661         }
662 
663         return setup_port(priv, port, bar, offset, board->reg_shift);
664 }
665 
666 static int pci_xircom_init(struct pci_dev *dev)
667 {
668         msleep(100);
669         return 0;
670 }
671 
672 static int pci_ni8420_init(struct pci_dev *dev)
673 {
674         void __iomem *p;
675         unsigned int bar = 0;
676 
677         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
678                 moan_device("no memory in bar", dev);
679                 return 0;
680         }
681 
682         p = pci_ioremap_bar(dev, bar);
683         if (p == NULL)
684                 return -ENOMEM;
685 
686         /* Enable CPU Interrupt */
687         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
688                p + NI8420_INT_ENABLE_REG);
689 
690         iounmap(p);
691         return 0;
692 }
693 
694 #define MITE_IOWBSR1_WSIZE      0xa
695 #define MITE_IOWBSR1_WIN_OFFSET 0x800
696 #define MITE_IOWBSR1_WENAB      (1 << 7)
697 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
698 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
699 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
700 
701 static int pci_ni8430_init(struct pci_dev *dev)
702 {
703         void __iomem *p;
704         struct pci_bus_region region;
705         u32 device_window;
706         unsigned int bar = 0;
707 
708         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
709                 moan_device("no memory in bar", dev);
710                 return 0;
711         }
712 
713         p = pci_ioremap_bar(dev, bar);
714         if (p == NULL)
715                 return -ENOMEM;
716 
717         /*
718          * Set device window address and size in BAR0, while acknowledging that
719          * the resource structure may contain a translated address that differs
720          * from the address the device responds to.
721          */
722         pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
723         device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
724                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
725         writel(device_window, p + MITE_IOWBSR1);
726 
727         /* Set window access to go to RAMSEL IO address space */
728         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
729                p + MITE_IOWCR1);
730 
731         /* Enable IO Bus Interrupt 0 */
732         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
733 
734         /* Enable CPU Interrupt */
735         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
736 
737         iounmap(p);
738         return 0;
739 }
740 
741 /* UART Port Control Register */
742 #define NI8430_PORTCON  0x0f
743 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
744 
745 static int
746 pci_ni8430_setup(struct serial_private *priv,
747                  const struct pciserial_board *board,
748                  struct uart_8250_port *port, int idx)
749 {
750         struct pci_dev *dev = priv->dev;
751         void __iomem *p;
752         unsigned int bar, offset = board->first_offset;
753 
754         if (idx >= board->num_ports)
755                 return 1;
756 
757         bar = FL_GET_BASE(board->flags);
758         offset += idx * board->uart_offset;
759 
760         p = pci_ioremap_bar(dev, bar);
761         if (!p)
762                 return -ENOMEM;
763 
764         /* enable the transceiver */
765         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
766                p + offset + NI8430_PORTCON);
767 
768         iounmap(p);
769 
770         return setup_port(priv, port, bar, offset, board->reg_shift);
771 }
772 
773 static int pci_netmos_9900_setup(struct serial_private *priv,
774                                 const struct pciserial_board *board,
775                                 struct uart_8250_port *port, int idx)
776 {
777         unsigned int bar;
778 
779         if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
780             (priv->dev->subsystem_device & 0xff00) == 0x3000) {
781                 /* netmos apparently orders BARs by datasheet layout, so serial
782                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
783                  */
784                 bar = 3 * idx;
785 
786                 return setup_port(priv, port, bar, 0, board->reg_shift);
787         } else {
788                 return pci_default_setup(priv, board, port, idx);
789         }
790 }
791 
792 /* the 99xx series comes with a range of device IDs and a variety
793  * of capabilities:
794  *
795  * 9900 has varying capabilities and can cascade to sub-controllers
796  *   (cascading should be purely internal)
797  * 9904 is hardwired with 4 serial ports
798  * 9912 and 9922 are hardwired with 2 serial ports
799  */
800 static int pci_netmos_9900_numports(struct pci_dev *dev)
801 {
802         unsigned int c = dev->class;
803         unsigned int pi;
804         unsigned short sub_serports;
805 
806         pi = (c & 0xff);
807 
808         if (pi == 2) {
809                 return 1;
810         } else if ((pi == 0) &&
811                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
812                 /* two possibilities: 0x30ps encodes number of parallel and
813                  * serial ports, or 0x1000 indicates *something*. This is not
814                  * immediately obvious, since the 2s1p+4s configuration seems
815                  * to offer all functionality on functions 0..2, while still
816                  * advertising the same function 3 as the 4s+2s1p config.
817                  */
818                 sub_serports = dev->subsystem_device & 0xf;
819                 if (sub_serports > 0) {
820                         return sub_serports;
821                 } else {
822                         dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
823                         return 0;
824                 }
825         }
826 
827         moan_device("unknown NetMos/Mostech program interface", dev);
828         return 0;
829 }
830 
831 static int pci_netmos_init(struct pci_dev *dev)
832 {
833         /* subdevice 0x00PS means <P> parallel, <S> serial */
834         unsigned int num_serial = dev->subsystem_device & 0xf;
835 
836         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
837                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
838                 return 0;
839 
840         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
841                         dev->subsystem_device == 0x0299)
842                 return 0;
843 
844         switch (dev->device) { /* FALLTHROUGH on all */
845                 case PCI_DEVICE_ID_NETMOS_9904:
846                 case PCI_DEVICE_ID_NETMOS_9912:
847                 case PCI_DEVICE_ID_NETMOS_9922:
848                 case PCI_DEVICE_ID_NETMOS_9900:
849                         num_serial = pci_netmos_9900_numports(dev);
850                         break;
851 
852                 default:
853                         if (num_serial == 0 ) {
854                                 moan_device("unknown NetMos/Mostech device", dev);
855                         }
856         }
857 
858         if (num_serial == 0)
859                 return -ENODEV;
860 
861         return num_serial;
862 }
863 
864 /*
865  * These chips are available with optionally one parallel port and up to
866  * two serial ports. Unfortunately they all have the same product id.
867  *
868  * Basic configuration is done over a region of 32 I/O ports. The base
869  * ioport is called INTA or INTC, depending on docs/other drivers.
870  *
871  * The region of the 32 I/O ports is configured in POSIO0R...
872  */
873 
874 /* registers */
875 #define ITE_887x_MISCR          0x9c
876 #define ITE_887x_INTCBAR        0x78
877 #define ITE_887x_UARTBAR        0x7c
878 #define ITE_887x_PS0BAR         0x10
879 #define ITE_887x_POSIO0         0x60
880 
881 /* I/O space size */
882 #define ITE_887x_IOSIZE         32
883 /* I/O space size (bits 26-24; 8 bytes = 011b) */
884 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
885 /* I/O space size (bits 26-24; 32 bytes = 101b) */
886 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
887 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
888 #define ITE_887x_POSIO_SPEED            (3 << 29)
889 /* enable IO_Space bit */
890 #define ITE_887x_POSIO_ENABLE           (1 << 31)
891 
892 static int pci_ite887x_init(struct pci_dev *dev)
893 {
894         /* inta_addr are the configuration addresses of the ITE */
895         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
896                                                         0x200, 0x280, 0 };
897         int ret, i, type;
898         struct resource *iobase = NULL;
899         u32 miscr, uartbar, ioport;
900 
901         /* search for the base-ioport */
902         i = 0;
903         while (inta_addr[i] && iobase == NULL) {
904                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
905                                                                 "ite887x");
906                 if (iobase != NULL) {
907                         /* write POSIO0R - speed | size | ioport */
908                         pci_write_config_dword(dev, ITE_887x_POSIO0,
909                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
910                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
911                         /* write INTCBAR - ioport */
912                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
913                                                                 inta_addr[i]);
914                         ret = inb(inta_addr[i]);
915                         if (ret != 0xff) {
916                                 /* ioport connected */
917                                 break;
918                         }
919                         release_region(iobase->start, ITE_887x_IOSIZE);
920                         iobase = NULL;
921                 }
922                 i++;
923         }
924 
925         if (!inta_addr[i]) {
926                 dev_err(&dev->dev, "ite887x: could not find iobase\n");
927                 return -ENODEV;
928         }
929 
930         /* start of undocumented type checking (see parport_pc.c) */
931         type = inb(iobase->start + 0x18) & 0x0f;
932 
933         switch (type) {
934         case 0x2:       /* ITE8871 (1P) */
935         case 0xa:       /* ITE8875 (1P) */
936                 ret = 0;
937                 break;
938         case 0xe:       /* ITE8872 (2S1P) */
939                 ret = 2;
940                 break;
941         case 0x6:       /* ITE8873 (1S) */
942                 ret = 1;
943                 break;
944         case 0x8:       /* ITE8874 (2S) */
945                 ret = 2;
946                 break;
947         default:
948                 moan_device("Unknown ITE887x", dev);
949                 ret = -ENODEV;
950         }
951 
952         /* configure all serial ports */
953         for (i = 0; i < ret; i++) {
954                 /* read the I/O port from the device */
955                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
956                                                                 &ioport);
957                 ioport &= 0x0000FF00;   /* the actual base address */
958                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
959                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
960                         ITE_887x_POSIO_IOSIZE_8 | ioport);
961 
962                 /* write the ioport to the UARTBAR */
963                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
964                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
965                 uartbar |= (ioport << (16 * i));        /* set the ioport */
966                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
967 
968                 /* get current config */
969                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
970                 /* disable interrupts (UARTx_Routing[3:0]) */
971                 miscr &= ~(0xf << (12 - 4 * i));
972                 /* activate the UART (UARTx_En) */
973                 miscr |= 1 << (23 - i);
974                 /* write new config with activated UART */
975                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
976         }
977 
978         if (ret <= 0) {
979                 /* the device has no UARTs if we get here */
980                 release_region(iobase->start, ITE_887x_IOSIZE);
981         }
982 
983         return ret;
984 }
985 
986 static void pci_ite887x_exit(struct pci_dev *dev)
987 {
988         u32 ioport;
989         /* the ioport is bit 0-15 in POSIO0R */
990         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
991         ioport &= 0xffff;
992         release_region(ioport, ITE_887x_IOSIZE);
993 }
994 
995 /*
996  * EndRun Technologies.
997  * Determine the number of ports available on the device.
998  */
999 #define PCI_VENDOR_ID_ENDRUN                    0x7401
1000 #define PCI_DEVICE_ID_ENDRUN_1588       0xe100
1001 
1002 static int pci_endrun_init(struct pci_dev *dev)
1003 {
1004         u8 __iomem *p;
1005         unsigned long deviceID;
1006         unsigned int  number_uarts = 0;
1007 
1008         /* EndRun device is all 0xexxx */
1009         if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1010                 (dev->device & 0xf000) != 0xe000)
1011                 return 0;
1012 
1013         p = pci_iomap(dev, 0, 5);
1014         if (p == NULL)
1015                 return -ENOMEM;
1016 
1017         deviceID = ioread32(p);
1018         /* EndRun device */
1019         if (deviceID == 0x07000200) {
1020                 number_uarts = ioread8(p + 4);
1021                 dev_dbg(&dev->dev,
1022                         "%d ports detected on EndRun PCI Express device\n",
1023                         number_uarts);
1024         }
1025         pci_iounmap(dev, p);
1026         return number_uarts;
1027 }
1028 
1029 /*
1030  * Oxford Semiconductor Inc.
1031  * Check that device is part of the Tornado range of devices, then determine
1032  * the number of ports available on the device.
1033  */
1034 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1035 {
1036         u8 __iomem *p;
1037         unsigned long deviceID;
1038         unsigned int  number_uarts = 0;
1039 
1040         /* OxSemi Tornado devices are all 0xCxxx */
1041         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1042             (dev->device & 0xF000) != 0xC000)
1043                 return 0;
1044 
1045         p = pci_iomap(dev, 0, 5);
1046         if (p == NULL)
1047                 return -ENOMEM;
1048 
1049         deviceID = ioread32(p);
1050         /* Tornado device */
1051         if (deviceID == 0x07000200) {
1052                 number_uarts = ioread8(p + 4);
1053                 dev_dbg(&dev->dev,
1054                         "%d ports detected on Oxford PCI Express device\n",
1055                         number_uarts);
1056         }
1057         pci_iounmap(dev, p);
1058         return number_uarts;
1059 }
1060 
1061 static int pci_asix_setup(struct serial_private *priv,
1062                   const struct pciserial_board *board,
1063                   struct uart_8250_port *port, int idx)
1064 {
1065         port->bugs |= UART_BUG_PARITY;
1066         return pci_default_setup(priv, board, port, idx);
1067 }
1068 
1069 /* Quatech devices have their own extra interface features */
1070 
1071 struct quatech_feature {
1072         u16 devid;
1073         bool amcc;
1074 };
1075 
1076 #define QPCR_TEST_FOR1          0x3F
1077 #define QPCR_TEST_GET1          0x00
1078 #define QPCR_TEST_FOR2          0x40
1079 #define QPCR_TEST_GET2          0x40
1080 #define QPCR_TEST_FOR3          0x80
1081 #define QPCR_TEST_GET3          0x40
1082 #define QPCR_TEST_FOR4          0xC0
1083 #define QPCR_TEST_GET4          0x80
1084 
1085 #define QOPR_CLOCK_X1           0x0000
1086 #define QOPR_CLOCK_X2           0x0001
1087 #define QOPR_CLOCK_X4           0x0002
1088 #define QOPR_CLOCK_X8           0x0003
1089 #define QOPR_CLOCK_RATE_MASK    0x0003
1090 
1091 
1092 static struct quatech_feature quatech_cards[] = {
1093         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1094         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1095         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1096         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1097         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1098         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1099         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1100         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1101         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1102         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1103         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1104         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1105         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1106         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1107         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1108         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1109         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1110         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1111         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1112         { 0, }
1113 };
1114 
1115 static int pci_quatech_amcc(u16 devid)
1116 {
1117         struct quatech_feature *qf = &quatech_cards[0];
1118         while (qf->devid) {
1119                 if (qf->devid == devid)
1120                         return qf->amcc;
1121                 qf++;
1122         }
1123         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1124         return 0;
1125 };
1126 
1127 static int pci_quatech_rqopr(struct uart_8250_port *port)
1128 {
1129         unsigned long base = port->port.iobase;
1130         u8 LCR, val;
1131 
1132         LCR = inb(base + UART_LCR);
1133         outb(0xBF, base + UART_LCR);
1134         val = inb(base + UART_SCR);
1135         outb(LCR, base + UART_LCR);
1136         return val;
1137 }
1138 
1139 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1140 {
1141         unsigned long base = port->port.iobase;
1142         u8 LCR, val;
1143 
1144         LCR = inb(base + UART_LCR);
1145         outb(0xBF, base + UART_LCR);
1146         val = inb(base + UART_SCR);
1147         outb(qopr, base + UART_SCR);
1148         outb(LCR, base + UART_LCR);
1149 }
1150 
1151 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1152 {
1153         unsigned long base = port->port.iobase;
1154         u8 LCR, val, qmcr;
1155 
1156         LCR = inb(base + UART_LCR);
1157         outb(0xBF, base + UART_LCR);
1158         val = inb(base + UART_SCR);
1159         outb(val | 0x10, base + UART_SCR);
1160         qmcr = inb(base + UART_MCR);
1161         outb(val, base + UART_SCR);
1162         outb(LCR, base + UART_LCR);
1163 
1164         return qmcr;
1165 }
1166 
1167 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1168 {
1169         unsigned long base = port->port.iobase;
1170         u8 LCR, val;
1171 
1172         LCR = inb(base + UART_LCR);
1173         outb(0xBF, base + UART_LCR);
1174         val = inb(base + UART_SCR);
1175         outb(val | 0x10, base + UART_SCR);
1176         outb(qmcr, base + UART_MCR);
1177         outb(val, base + UART_SCR);
1178         outb(LCR, base + UART_LCR);
1179 }
1180 
1181 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1182 {
1183         unsigned long base = port->port.iobase;
1184         u8 LCR, val;
1185 
1186         LCR = inb(base + UART_LCR);
1187         outb(0xBF, base + UART_LCR);
1188         val = inb(base + UART_SCR);
1189         if (val & 0x20) {
1190                 outb(0x80, UART_LCR);
1191                 if (!(inb(UART_SCR) & 0x20)) {
1192                         outb(LCR, base + UART_LCR);
1193                         return 1;
1194                 }
1195         }
1196         return 0;
1197 }
1198 
1199 static int pci_quatech_test(struct uart_8250_port *port)
1200 {
1201         u8 reg;
1202         u8 qopr = pci_quatech_rqopr(port);
1203         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1204         reg = pci_quatech_rqopr(port) & 0xC0;
1205         if (reg != QPCR_TEST_GET1)
1206                 return -EINVAL;
1207         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1208         reg = pci_quatech_rqopr(port) & 0xC0;
1209         if (reg != QPCR_TEST_GET2)
1210                 return -EINVAL;
1211         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1212         reg = pci_quatech_rqopr(port) & 0xC0;
1213         if (reg != QPCR_TEST_GET3)
1214                 return -EINVAL;
1215         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1216         reg = pci_quatech_rqopr(port) & 0xC0;
1217         if (reg != QPCR_TEST_GET4)
1218                 return -EINVAL;
1219 
1220         pci_quatech_wqopr(port, qopr);
1221         return 0;
1222 }
1223 
1224 static int pci_quatech_clock(struct uart_8250_port *port)
1225 {
1226         u8 qopr, reg, set;
1227         unsigned long clock;
1228 
1229         if (pci_quatech_test(port) < 0)
1230                 return 1843200;
1231 
1232         qopr = pci_quatech_rqopr(port);
1233 
1234         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1235         reg = pci_quatech_rqopr(port);
1236         if (reg & QOPR_CLOCK_X8) {
1237                 clock = 1843200;
1238                 goto out;
1239         }
1240         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1241         reg = pci_quatech_rqopr(port);
1242         if (!(reg & QOPR_CLOCK_X8)) {
1243                 clock = 1843200;
1244                 goto out;
1245         }
1246         reg &= QOPR_CLOCK_X8;
1247         if (reg == QOPR_CLOCK_X2) {
1248                 clock =  3685400;
1249                 set = QOPR_CLOCK_X2;
1250         } else if (reg == QOPR_CLOCK_X4) {
1251                 clock = 7372800;
1252                 set = QOPR_CLOCK_X4;
1253         } else if (reg == QOPR_CLOCK_X8) {
1254                 clock = 14745600;
1255                 set = QOPR_CLOCK_X8;
1256         } else {
1257                 clock = 1843200;
1258                 set = QOPR_CLOCK_X1;
1259         }
1260         qopr &= ~QOPR_CLOCK_RATE_MASK;
1261         qopr |= set;
1262 
1263 out:
1264         pci_quatech_wqopr(port, qopr);
1265         return clock;
1266 }
1267 
1268 static int pci_quatech_rs422(struct uart_8250_port *port)
1269 {
1270         u8 qmcr;
1271         int rs422 = 0;
1272 
1273         if (!pci_quatech_has_qmcr(port))
1274                 return 0;
1275         qmcr = pci_quatech_rqmcr(port);
1276         pci_quatech_wqmcr(port, 0xFF);
1277         if (pci_quatech_rqmcr(port))
1278                 rs422 = 1;
1279         pci_quatech_wqmcr(port, qmcr);
1280         return rs422;
1281 }
1282 
1283 static int pci_quatech_init(struct pci_dev *dev)
1284 {
1285         if (pci_quatech_amcc(dev->device)) {
1286                 unsigned long base = pci_resource_start(dev, 0);
1287                 if (base) {
1288                         u32 tmp;
1289                         outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1290                         tmp = inl(base + 0x3c);
1291                         outl(tmp | 0x01000000, base + 0x3c);
1292                         outl(tmp &= ~0x01000000, base + 0x3c);
1293                 }
1294         }
1295         return 0;
1296 }
1297 
1298 static int pci_quatech_setup(struct serial_private *priv,
1299                   const struct pciserial_board *board,
1300                   struct uart_8250_port *port, int idx)
1301 {
1302         /* Needed by pci_quatech calls below */
1303         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1304         /* Set up the clocking */
1305         port->port.uartclk = pci_quatech_clock(port);
1306         /* For now just warn about RS422 */
1307         if (pci_quatech_rs422(port))
1308                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1309         return pci_default_setup(priv, board, port, idx);
1310 }
1311 
1312 static void pci_quatech_exit(struct pci_dev *dev)
1313 {
1314 }
1315 
1316 static int pci_default_setup(struct serial_private *priv,
1317                   const struct pciserial_board *board,
1318                   struct uart_8250_port *port, int idx)
1319 {
1320         unsigned int bar, offset = board->first_offset, maxnr;
1321 
1322         bar = FL_GET_BASE(board->flags);
1323         if (board->flags & FL_BASE_BARS)
1324                 bar += idx;
1325         else
1326                 offset += idx * board->uart_offset;
1327 
1328         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1329                 (board->reg_shift + 3);
1330 
1331         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1332                 return 1;
1333 
1334         return setup_port(priv, port, bar, offset, board->reg_shift);
1335 }
1336 
1337 static int pci_pericom_setup(struct serial_private *priv,
1338                   const struct pciserial_board *board,
1339                   struct uart_8250_port *port, int idx)
1340 {
1341         unsigned int bar, offset = board->first_offset, maxnr;
1342 
1343         bar = FL_GET_BASE(board->flags);
1344         if (board->flags & FL_BASE_BARS)
1345                 bar += idx;
1346         else
1347                 offset += idx * board->uart_offset;
1348 
1349         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1350                 (board->reg_shift + 3);
1351 
1352         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1353                 return 1;
1354 
1355         port->port.uartclk = 14745600;
1356 
1357         return setup_port(priv, port, bar, offset, board->reg_shift);
1358 }
1359 
1360 static int
1361 ce4100_serial_setup(struct serial_private *priv,
1362                   const struct pciserial_board *board,
1363                   struct uart_8250_port *port, int idx)
1364 {
1365         int ret;
1366 
1367         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1368         port->port.iotype = UPIO_MEM32;
1369         port->port.type = PORT_XSCALE;
1370         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1371         port->port.regshift = 2;
1372 
1373         return ret;
1374 }
1375 
1376 #define PCI_DEVICE_ID_INTEL_BYT_UART1   0x0f0a
1377 #define PCI_DEVICE_ID_INTEL_BYT_UART2   0x0f0c
1378 
1379 #define PCI_DEVICE_ID_INTEL_BSW_UART1   0x228a
1380 #define PCI_DEVICE_ID_INTEL_BSW_UART2   0x228c
1381 
1382 #define PCI_DEVICE_ID_INTEL_BDW_UART1   0x9ce3
1383 #define PCI_DEVICE_ID_INTEL_BDW_UART2   0x9ce4
1384 
1385 #define BYT_PRV_CLK                     0x800
1386 #define BYT_PRV_CLK_EN                  (1 << 0)
1387 #define BYT_PRV_CLK_M_VAL_SHIFT         1
1388 #define BYT_PRV_CLK_N_VAL_SHIFT         16
1389 #define BYT_PRV_CLK_UPDATE              (1 << 31)
1390 
1391 #define BYT_TX_OVF_INT                  0x820
1392 #define BYT_TX_OVF_INT_MASK             (1 << 1)
1393 
1394 static void
1395 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1396                 struct ktermios *old)
1397 {
1398         unsigned int baud = tty_termios_baud_rate(termios);
1399         unsigned long fref = 100000000, fuart = baud * 16;
1400         unsigned long w = BIT(15) - 1;
1401         unsigned long m, n;
1402         u32 reg;
1403 
1404         /* Get Fuart closer to Fref */
1405         fuart *= rounddown_pow_of_two(fref / fuart);
1406 
1407         /*
1408          * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1409          * dividers must be adjusted.
1410          *
1411          * uartclk = (m / n) * 100 MHz, where m <= n
1412          */
1413         rational_best_approximation(fuart, fref, w, w, &m, &n);
1414         p->uartclk = fuart;
1415 
1416         /* Reset the clock */
1417         reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1418         writel(reg, p->membase + BYT_PRV_CLK);
1419         reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1420         writel(reg, p->membase + BYT_PRV_CLK);
1421 
1422         p->status &= ~UPSTAT_AUTOCTS;
1423         if (termios->c_cflag & CRTSCTS)
1424                 p->status |= UPSTAT_AUTOCTS;
1425 
1426         serial8250_do_set_termios(p, termios, old);
1427 }
1428 
1429 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1430 {
1431         struct dw_dma_slave *dws = param;
1432 
1433         if (dws->dma_dev != chan->device->dev)
1434                 return false;
1435 
1436         chan->private = dws;
1437         return true;
1438 }
1439 
1440 static int
1441 byt_serial_setup(struct serial_private *priv,
1442                  const struct pciserial_board *board,
1443                  struct uart_8250_port *port, int idx)
1444 {
1445         struct pci_dev *pdev = priv->dev;
1446         struct device *dev = port->port.dev;
1447         struct uart_8250_dma *dma;
1448         struct dw_dma_slave *tx_param, *rx_param;
1449         struct pci_dev *dma_dev;
1450         int ret;
1451 
1452         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1453         if (!dma)
1454                 return -ENOMEM;
1455 
1456         tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1457         if (!tx_param)
1458                 return -ENOMEM;
1459 
1460         rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1461         if (!rx_param)
1462                 return -ENOMEM;
1463 
1464         switch (pdev->device) {
1465         case PCI_DEVICE_ID_INTEL_BYT_UART1:
1466         case PCI_DEVICE_ID_INTEL_BSW_UART1:
1467         case PCI_DEVICE_ID_INTEL_BDW_UART1:
1468                 rx_param->src_id = 3;
1469                 tx_param->dst_id = 2;
1470                 break;
1471         case PCI_DEVICE_ID_INTEL_BYT_UART2:
1472         case PCI_DEVICE_ID_INTEL_BSW_UART2:
1473         case PCI_DEVICE_ID_INTEL_BDW_UART2:
1474                 rx_param->src_id = 5;
1475                 tx_param->dst_id = 4;
1476                 break;
1477         default:
1478                 return -EINVAL;
1479         }
1480 
1481         rx_param->src_master = 1;
1482         rx_param->dst_master = 0;
1483 
1484         dma->rxconf.src_maxburst = 16;
1485 
1486         tx_param->src_master = 1;
1487         tx_param->dst_master = 0;
1488 
1489         dma->txconf.dst_maxburst = 16;
1490 
1491         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1492         rx_param->dma_dev = &dma_dev->dev;
1493         tx_param->dma_dev = &dma_dev->dev;
1494 
1495         dma->fn = byt_dma_filter;
1496         dma->rx_param = rx_param;
1497         dma->tx_param = tx_param;
1498 
1499         ret = pci_default_setup(priv, board, port, idx);
1500         port->port.iotype = UPIO_MEM;
1501         port->port.type = PORT_16550A;
1502         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1503         port->port.set_termios = byt_set_termios;
1504         port->port.fifosize = 64;
1505         port->tx_loadsz = 64;
1506         port->dma = dma;
1507         port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1508 
1509         /* Disable Tx counter interrupts */
1510         writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1511 
1512         return ret;
1513 }
1514 
1515 static int
1516 pci_omegapci_setup(struct serial_private *priv,
1517                       const struct pciserial_board *board,
1518                       struct uart_8250_port *port, int idx)
1519 {
1520         return setup_port(priv, port, 2, idx * 8, 0);
1521 }
1522 
1523 static int
1524 pci_brcm_trumanage_setup(struct serial_private *priv,
1525                          const struct pciserial_board *board,
1526                          struct uart_8250_port *port, int idx)
1527 {
1528         int ret = pci_default_setup(priv, board, port, idx);
1529 
1530         port->port.type = PORT_BRCM_TRUMANAGE;
1531         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1532         return ret;
1533 }
1534 
1535 /* RTS will control by MCR if this bit is 0 */
1536 #define FINTEK_RTS_CONTROL_BY_HW        BIT(4)
1537 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1538 #define FINTEK_RTS_INVERT               BIT(5)
1539 
1540 /* We should do proper H/W transceiver setting before change to RS485 mode */
1541 static int pci_fintek_rs485_config(struct uart_port *port,
1542                                struct serial_rs485 *rs485)
1543 {
1544         u8 setting;
1545         u8 *index = (u8 *) port->private_data;
1546         struct pci_dev *pci_dev = container_of(port->dev, struct pci_dev,
1547                                                 dev);
1548 
1549         pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1550 
1551         if (!rs485)
1552                 rs485 = &port->rs485;
1553         else if (rs485->flags & SER_RS485_ENABLED)
1554                 memset(rs485->padding, 0, sizeof(rs485->padding));
1555         else
1556                 memset(rs485, 0, sizeof(*rs485));
1557 
1558         /* F81504/508/512 not support RTS delay before or after send */
1559         rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1560 
1561         if (rs485->flags & SER_RS485_ENABLED) {
1562                 /* Enable RTS H/W control mode */
1563                 setting |= FINTEK_RTS_CONTROL_BY_HW;
1564 
1565                 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1566                         /* RTS driving high on TX */
1567                         setting &= ~FINTEK_RTS_INVERT;
1568                 } else {
1569                         /* RTS driving low on TX */
1570                         setting |= FINTEK_RTS_INVERT;
1571                 }
1572 
1573                 rs485->delay_rts_after_send = 0;
1574                 rs485->delay_rts_before_send = 0;
1575         } else {
1576                 /* Disable RTS H/W control mode */
1577                 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1578         }
1579 
1580         pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1581 
1582         if (rs485 != &port->rs485)
1583                 port->rs485 = *rs485;
1584 
1585         return 0;
1586 }
1587 
1588 static int pci_fintek_setup(struct serial_private *priv,
1589                             const struct pciserial_board *board,
1590                             struct uart_8250_port *port, int idx)
1591 {
1592         struct pci_dev *pdev = priv->dev;
1593         u8 *data;
1594         u8 config_base;
1595         u16 iobase;
1596 
1597         config_base = 0x40 + 0x08 * idx;
1598 
1599         /* Get the io address from configuration space */
1600         pci_read_config_word(pdev, config_base + 4, &iobase);
1601 
1602         dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1603 
1604         port->port.iotype = UPIO_PORT;
1605         port->port.iobase = iobase;
1606         port->port.rs485_config = pci_fintek_rs485_config;
1607 
1608         data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1609         if (!data)
1610                 return -ENOMEM;
1611 
1612         /* preserve index in PCI configuration space */
1613         *data = idx;
1614         port->port.private_data = data;
1615 
1616         return 0;
1617 }
1618 
1619 static int pci_fintek_init(struct pci_dev *dev)
1620 {
1621         unsigned long iobase;
1622         u32 max_port, i;
1623         u32 bar_data[3];
1624         u8 config_base;
1625         struct serial_private *priv = pci_get_drvdata(dev);
1626         struct uart_8250_port *port;
1627 
1628         switch (dev->device) {
1629         case 0x1104: /* 4 ports */
1630         case 0x1108: /* 8 ports */
1631                 max_port = dev->device & 0xff;
1632                 break;
1633         case 0x1112: /* 12 ports */
1634                 max_port = 12;
1635                 break;
1636         default:
1637                 return -EINVAL;
1638         }
1639 
1640         /* Get the io address dispatch from the BIOS */
1641         pci_read_config_dword(dev, 0x24, &bar_data[0]);
1642         pci_read_config_dword(dev, 0x20, &bar_data[1]);
1643         pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1644 
1645         for (i = 0; i < max_port; ++i) {
1646                 /* UART0 configuration offset start from 0x40 */
1647                 config_base = 0x40 + 0x08 * i;
1648 
1649                 /* Calculate Real IO Port */
1650                 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1651 
1652                 /* Enable UART I/O port */
1653                 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1654 
1655                 /* Select 128-byte FIFO and 8x FIFO threshold */
1656                 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1657 
1658                 /* LSB UART */
1659                 pci_write_config_byte(dev, config_base + 0x04,
1660                                 (u8)(iobase & 0xff));
1661 
1662                 /* MSB UART */
1663                 pci_write_config_byte(dev, config_base + 0x05,
1664                                 (u8)((iobase & 0xff00) >> 8));
1665 
1666                 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1667 
1668                 if (priv) {
1669                         /* re-apply RS232/485 mode when
1670                          * pciserial_resume_ports()
1671                          */
1672                         port = serial8250_get_port(priv->line[i]);
1673                         pci_fintek_rs485_config(&port->port, NULL);
1674                 } else {
1675                         /* First init without port data
1676                          * force init to RS232 Mode
1677                          */
1678                         pci_write_config_byte(dev, config_base + 0x07, 0x01);
1679                 }
1680         }
1681 
1682         return max_port;
1683 }
1684 
1685 static int skip_tx_en_setup(struct serial_private *priv,
1686                         const struct pciserial_board *board,
1687                         struct uart_8250_port *port, int idx)
1688 {
1689         port->port.flags |= UPF_NO_TXEN_TEST;
1690         dev_dbg(&priv->dev->dev,
1691                 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1692                 priv->dev->vendor, priv->dev->device,
1693                 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1694 
1695         return pci_default_setup(priv, board, port, idx);
1696 }
1697 
1698 static void kt_handle_break(struct uart_port *p)
1699 {
1700         struct uart_8250_port *up = up_to_u8250p(p);
1701         /*
1702          * On receipt of a BI, serial device in Intel ME (Intel
1703          * management engine) needs to have its fifos cleared for sane
1704          * SOL (Serial Over Lan) output.
1705          */
1706         serial8250_clear_and_reinit_fifos(up);
1707 }
1708 
1709 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1710 {
1711         struct uart_8250_port *up = up_to_u8250p(p);
1712         unsigned int val;
1713 
1714         /*
1715          * When the Intel ME (management engine) gets reset its serial
1716          * port registers could return 0 momentarily.  Functions like
1717          * serial8250_console_write, read and save the IER, perform
1718          * some operation and then restore it.  In order to avoid
1719          * setting IER register inadvertently to 0, if the value read
1720          * is 0, double check with ier value in uart_8250_port and use
1721          * that instead.  up->ier should be the same value as what is
1722          * currently configured.
1723          */
1724         val = inb(p->iobase + offset);
1725         if (offset == UART_IER) {
1726                 if (val == 0)
1727                         val = up->ier;
1728         }
1729         return val;
1730 }
1731 
1732 static int kt_serial_setup(struct serial_private *priv,
1733                            const struct pciserial_board *board,
1734                            struct uart_8250_port *port, int idx)
1735 {
1736         port->port.flags |= UPF_BUG_THRE;
1737         port->port.serial_in = kt_serial_in;
1738         port->port.handle_break = kt_handle_break;
1739         return skip_tx_en_setup(priv, board, port, idx);
1740 }
1741 
1742 static int pci_eg20t_init(struct pci_dev *dev)
1743 {
1744 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1745         return -ENODEV;
1746 #else
1747         return 0;
1748 #endif
1749 }
1750 
1751 #define PCI_DEVICE_ID_EXAR_XR17V4358    0x4358
1752 #define PCI_DEVICE_ID_EXAR_XR17V8358    0x8358
1753 
1754 static int
1755 pci_xr17c154_setup(struct serial_private *priv,
1756                   const struct pciserial_board *board,
1757                   struct uart_8250_port *port, int idx)
1758 {
1759         port->port.flags |= UPF_EXAR_EFR;
1760         return pci_default_setup(priv, board, port, idx);
1761 }
1762 
1763 static inline int
1764 xr17v35x_has_slave(struct serial_private *priv)
1765 {
1766         const int dev_id = priv->dev->device;
1767 
1768         return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1769                 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1770 }
1771 
1772 static int
1773 pci_xr17v35x_setup(struct serial_private *priv,
1774                   const struct pciserial_board *board,
1775                   struct uart_8250_port *port, int idx)
1776 {
1777         u8 __iomem *p;
1778 
1779         p = pci_ioremap_bar(priv->dev, 0);
1780         if (p == NULL)
1781                 return -ENOMEM;
1782 
1783         port->port.flags |= UPF_EXAR_EFR;
1784 
1785         /*
1786          * Setup the uart clock for the devices on expansion slot to
1787          * half the clock speed of the main chip (which is 125MHz)
1788          */
1789         if (xr17v35x_has_slave(priv) && idx >= 8)
1790                 port->port.uartclk = (7812500 * 16 / 2);
1791 
1792         /*
1793          * Setup Multipurpose Input/Output pins.
1794          */
1795         if (idx == 0) {
1796                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1797                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1798                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1799                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1800                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1801                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1802                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1803                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1804                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1805                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1806                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1807                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1808         }
1809         writeb(0x00, p + UART_EXAR_8XMODE);
1810         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1811         writeb(128, p + UART_EXAR_TXTRG);
1812         writeb(128, p + UART_EXAR_RXTRG);
1813         iounmap(p);
1814 
1815         return pci_default_setup(priv, board, port, idx);
1816 }
1817 
1818 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1819 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1820 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1821 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1822 
1823 static int
1824 pci_fastcom335_setup(struct serial_private *priv,
1825                   const struct pciserial_board *board,
1826                   struct uart_8250_port *port, int idx)
1827 {
1828         u8 __iomem *p;
1829 
1830         p = pci_ioremap_bar(priv->dev, 0);
1831         if (p == NULL)
1832                 return -ENOMEM;
1833 
1834         port->port.flags |= UPF_EXAR_EFR;
1835 
1836         /*
1837          * Setup Multipurpose Input/Output pins.
1838          */
1839         if (idx == 0) {
1840                 switch (priv->dev->device) {
1841                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1842                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1843                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1844                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1845                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1846                         break;
1847                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1848                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1849                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1850                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1851                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1852                         break;
1853                 }
1854                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1855                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1856                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1857         }
1858         writeb(0x00, p + UART_EXAR_8XMODE);
1859         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1860         writeb(32, p + UART_EXAR_TXTRG);
1861         writeb(32, p + UART_EXAR_RXTRG);
1862         iounmap(p);
1863 
1864         return pci_default_setup(priv, board, port, idx);
1865 }
1866 
1867 static int
1868 pci_wch_ch353_setup(struct serial_private *priv,
1869                     const struct pciserial_board *board,
1870                     struct uart_8250_port *port, int idx)
1871 {
1872         port->port.flags |= UPF_FIXED_TYPE;
1873         port->port.type = PORT_16550A;
1874         return pci_default_setup(priv, board, port, idx);
1875 }
1876 
1877 static int
1878 pci_wch_ch38x_setup(struct serial_private *priv,
1879                     const struct pciserial_board *board,
1880                     struct uart_8250_port *port, int idx)
1881 {
1882         port->port.flags |= UPF_FIXED_TYPE;
1883         port->port.type = PORT_16850;
1884         return pci_default_setup(priv, board, port, idx);
1885 }
1886 
1887 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1888 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1889 #define PCI_DEVICE_ID_OCTPRO            0x0001
1890 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1891 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1892 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1893 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1894 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1895 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1896 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1897 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1898 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1899 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1900 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1901 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1902 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1903 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1904 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1905 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1906 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1907 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1908 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1909 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1910 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1911 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1912 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1913 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
1914 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1915 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1916 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1917 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1918 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1919 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1920 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1921 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1922 #define PCI_VENDOR_ID_WCH               0x4348
1923 #define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
1924 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1925 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1926 #define PCI_DEVICE_ID_WCH_CH353_1S1P    0x5053
1927 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1928 #define PCI_VENDOR_ID_AGESTAR           0x5372
1929 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1930 #define PCI_VENDOR_ID_ASIX              0x9710
1931 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1932 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1933 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1934 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1935 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1936 #define PCI_DEVICE_ID_INTEL_QRK_UART    0x0936
1937 
1938 #define PCI_VENDOR_ID_SUNIX             0x1fd4
1939 #define PCI_DEVICE_ID_SUNIX_1999        0x1999
1940 
1941 #define PCIE_VENDOR_ID_WCH              0x1c00
1942 #define PCIE_DEVICE_ID_WCH_CH382_2S1P   0x3250
1943 #define PCIE_DEVICE_ID_WCH_CH384_4S     0x3470
1944 #define PCIE_DEVICE_ID_WCH_CH382_2S     0x3253
1945 
1946 #define PCI_VENDOR_ID_PERICOM                   0x12D8
1947 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951        0x7951
1948 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952        0x7952
1949 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954        0x7954
1950 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958        0x7958
1951 
1952 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1953 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1954 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1955 
1956 /*
1957  * Master list of serial port init/setup/exit quirks.
1958  * This does not describe the general nature of the port.
1959  * (ie, baud base, number and location of ports, etc)
1960  *
1961  * This list is ordered alphabetically by vendor then device.
1962  * Specific entries must come before more generic entries.
1963  */
1964 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1965         /*
1966         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1967         */
1968         {
1969                 .vendor         = PCI_VENDOR_ID_AMCC,
1970                 .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1971                 .subvendor      = PCI_ANY_ID,
1972                 .subdevice      = PCI_ANY_ID,
1973                 .setup          = addidata_apci7800_setup,
1974         },
1975         /*
1976          * AFAVLAB cards - these may be called via parport_serial
1977          *  It is not clear whether this applies to all products.
1978          */
1979         {
1980                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1981                 .device         = PCI_ANY_ID,
1982                 .subvendor      = PCI_ANY_ID,
1983                 .subdevice      = PCI_ANY_ID,
1984                 .setup          = afavlab_setup,
1985         },
1986         /*
1987          * HP Diva
1988          */
1989         {
1990                 .vendor         = PCI_VENDOR_ID_HP,
1991                 .device         = PCI_DEVICE_ID_HP_DIVA,
1992                 .subvendor      = PCI_ANY_ID,
1993                 .subdevice      = PCI_ANY_ID,
1994                 .init           = pci_hp_diva_init,
1995                 .setup          = pci_hp_diva_setup,
1996         },
1997         /*
1998          * Intel
1999          */
2000         {
2001                 .vendor         = PCI_VENDOR_ID_INTEL,
2002                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
2003                 .subvendor      = 0xe4bf,
2004                 .subdevice      = PCI_ANY_ID,
2005                 .init           = pci_inteli960ni_init,
2006                 .setup          = pci_default_setup,
2007         },
2008         {
2009                 .vendor         = PCI_VENDOR_ID_INTEL,
2010                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
2011                 .subvendor      = PCI_ANY_ID,
2012                 .subdevice      = PCI_ANY_ID,
2013                 .setup          = skip_tx_en_setup,
2014         },
2015         {
2016                 .vendor         = PCI_VENDOR_ID_INTEL,
2017                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
2018                 .subvendor      = PCI_ANY_ID,
2019                 .subdevice      = PCI_ANY_ID,
2020                 .setup          = skip_tx_en_setup,
2021         },
2022         {
2023                 .vendor         = PCI_VENDOR_ID_INTEL,
2024                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
2025                 .subvendor      = PCI_ANY_ID,
2026                 .subdevice      = PCI_ANY_ID,
2027                 .setup          = skip_tx_en_setup,
2028         },
2029         {
2030                 .vendor         = PCI_VENDOR_ID_INTEL,
2031                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
2032                 .subvendor      = PCI_ANY_ID,
2033                 .subdevice      = PCI_ANY_ID,
2034                 .setup          = ce4100_serial_setup,
2035         },
2036         {
2037                 .vendor         = PCI_VENDOR_ID_INTEL,
2038                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2039                 .subvendor      = PCI_ANY_ID,
2040                 .subdevice      = PCI_ANY_ID,
2041                 .setup          = kt_serial_setup,
2042         },
2043         {
2044                 .vendor         = PCI_VENDOR_ID_INTEL,
2045                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART1,
2046                 .subvendor      = PCI_ANY_ID,
2047                 .subdevice      = PCI_ANY_ID,
2048                 .setup          = byt_serial_setup,
2049         },
2050         {
2051                 .vendor         = PCI_VENDOR_ID_INTEL,
2052                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART2,
2053                 .subvendor      = PCI_ANY_ID,
2054                 .subdevice      = PCI_ANY_ID,
2055                 .setup          = byt_serial_setup,
2056         },
2057         {
2058                 .vendor         = PCI_VENDOR_ID_INTEL,
2059                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART1,
2060                 .subvendor      = PCI_ANY_ID,
2061                 .subdevice      = PCI_ANY_ID,
2062                 .setup          = byt_serial_setup,
2063         },
2064         {
2065                 .vendor         = PCI_VENDOR_ID_INTEL,
2066                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART2,
2067                 .subvendor      = PCI_ANY_ID,
2068                 .subdevice      = PCI_ANY_ID,
2069                 .setup          = byt_serial_setup,
2070         },
2071         {
2072                 .vendor         = PCI_VENDOR_ID_INTEL,
2073                 .device         = PCI_DEVICE_ID_INTEL_BDW_UART1,
2074                 .subvendor      = PCI_ANY_ID,
2075                 .subdevice      = PCI_ANY_ID,
2076                 .setup          = byt_serial_setup,
2077         },
2078         {
2079                 .vendor         = PCI_VENDOR_ID_INTEL,
2080                 .device         = PCI_DEVICE_ID_INTEL_BDW_UART2,
2081                 .subvendor      = PCI_ANY_ID,
2082                 .subdevice      = PCI_ANY_ID,
2083                 .setup          = byt_serial_setup,
2084         },
2085         /*
2086          * ITE
2087          */
2088         {
2089                 .vendor         = PCI_VENDOR_ID_ITE,
2090                 .device         = PCI_DEVICE_ID_ITE_8872,
2091                 .subvendor      = PCI_ANY_ID,
2092                 .subdevice      = PCI_ANY_ID,
2093                 .init           = pci_ite887x_init,
2094                 .setup          = pci_default_setup,
2095                 .exit           = pci_ite887x_exit,
2096         },
2097         /*
2098          * National Instruments
2099          */
2100         {
2101                 .vendor         = PCI_VENDOR_ID_NI,
2102                 .device         = PCI_DEVICE_ID_NI_PCI23216,
2103                 .subvendor      = PCI_ANY_ID,
2104                 .subdevice      = PCI_ANY_ID,
2105                 .init           = pci_ni8420_init,
2106                 .setup          = pci_default_setup,
2107                 .exit           = pci_ni8420_exit,
2108         },
2109         {
2110                 .vendor         = PCI_VENDOR_ID_NI,
2111                 .device         = PCI_DEVICE_ID_NI_PCI2328,
2112                 .subvendor      = PCI_ANY_ID,
2113                 .subdevice      = PCI_ANY_ID,
2114                 .init           = pci_ni8420_init,
2115                 .setup          = pci_default_setup,
2116                 .exit           = pci_ni8420_exit,
2117         },
2118         {
2119                 .vendor         = PCI_VENDOR_ID_NI,
2120                 .device         = PCI_DEVICE_ID_NI_PCI2324,
2121                 .subvendor      = PCI_ANY_ID,
2122                 .subdevice      = PCI_ANY_ID,
2123                 .init           = pci_ni8420_init,
2124                 .setup          = pci_default_setup,
2125                 .exit           = pci_ni8420_exit,
2126         },
2127         {
2128                 .vendor         = PCI_VENDOR_ID_NI,
2129                 .device         = PCI_DEVICE_ID_NI_PCI2322,
2130                 .subvendor      = PCI_ANY_ID,
2131                 .subdevice      = PCI_ANY_ID,
2132                 .init           = pci_ni8420_init,
2133                 .setup          = pci_default_setup,
2134                 .exit           = pci_ni8420_exit,
2135         },
2136         {
2137                 .vendor         = PCI_VENDOR_ID_NI,
2138                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
2139                 .subvendor      = PCI_ANY_ID,
2140                 .subdevice      = PCI_ANY_ID,
2141                 .init           = pci_ni8420_init,
2142                 .setup          = pci_default_setup,
2143                 .exit           = pci_ni8420_exit,
2144         },
2145         {
2146                 .vendor         = PCI_VENDOR_ID_NI,
2147                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
2148                 .subvendor      = PCI_ANY_ID,
2149                 .subdevice      = PCI_ANY_ID,
2150                 .init           = pci_ni8420_init,
2151                 .setup          = pci_default_setup,
2152                 .exit           = pci_ni8420_exit,
2153         },
2154         {
2155                 .vendor         = PCI_VENDOR_ID_NI,
2156                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
2157                 .subvendor      = PCI_ANY_ID,
2158                 .subdevice      = PCI_ANY_ID,
2159                 .init           = pci_ni8420_init,
2160                 .setup          = pci_default_setup,
2161                 .exit           = pci_ni8420_exit,
2162         },
2163         {
2164                 .vendor         = PCI_VENDOR_ID_NI,
2165                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
2166                 .subvendor      = PCI_ANY_ID,
2167                 .subdevice      = PCI_ANY_ID,
2168                 .init           = pci_ni8420_init,
2169                 .setup          = pci_default_setup,
2170                 .exit           = pci_ni8420_exit,
2171         },
2172         {
2173                 .vendor         = PCI_VENDOR_ID_NI,
2174                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
2175                 .subvendor      = PCI_ANY_ID,
2176                 .subdevice      = PCI_ANY_ID,
2177                 .init           = pci_ni8420_init,
2178                 .setup          = pci_default_setup,
2179                 .exit           = pci_ni8420_exit,
2180         },
2181         {
2182                 .vendor         = PCI_VENDOR_ID_NI,
2183                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
2184                 .subvendor      = PCI_ANY_ID,
2185                 .subdevice      = PCI_ANY_ID,
2186                 .init           = pci_ni8420_init,
2187                 .setup          = pci_default_setup,
2188                 .exit           = pci_ni8420_exit,
2189         },
2190         {
2191                 .vendor         = PCI_VENDOR_ID_NI,
2192                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
2193                 .subvendor      = PCI_ANY_ID,
2194                 .subdevice      = PCI_ANY_ID,
2195                 .init           = pci_ni8420_init,
2196                 .setup          = pci_default_setup,
2197                 .exit           = pci_ni8420_exit,
2198         },
2199         {
2200                 .vendor         = PCI_VENDOR_ID_NI,
2201                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
2202                 .subvendor      = PCI_ANY_ID,
2203                 .subdevice      = PCI_ANY_ID,
2204                 .init           = pci_ni8420_init,
2205                 .setup          = pci_default_setup,
2206                 .exit           = pci_ni8420_exit,
2207         },
2208         {
2209                 .vendor         = PCI_VENDOR_ID_NI,
2210                 .device         = PCI_ANY_ID,
2211                 .subvendor      = PCI_ANY_ID,
2212                 .subdevice      = PCI_ANY_ID,
2213                 .init           = pci_ni8430_init,
2214                 .setup          = pci_ni8430_setup,
2215                 .exit           = pci_ni8430_exit,
2216         },
2217         /* Quatech */
2218         {
2219                 .vendor         = PCI_VENDOR_ID_QUATECH,
2220                 .device         = PCI_ANY_ID,
2221                 .subvendor      = PCI_ANY_ID,
2222                 .subdevice      = PCI_ANY_ID,
2223                 .init           = pci_quatech_init,
2224                 .setup          = pci_quatech_setup,
2225                 .exit           = pci_quatech_exit,
2226         },
2227         /*
2228          * Panacom
2229          */
2230         {
2231                 .vendor         = PCI_VENDOR_ID_PANACOM,
2232                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2233                 .subvendor      = PCI_ANY_ID,
2234                 .subdevice      = PCI_ANY_ID,
2235                 .init           = pci_plx9050_init,
2236                 .setup          = pci_default_setup,
2237                 .exit           = pci_plx9050_exit,
2238         },
2239         {
2240                 .vendor         = PCI_VENDOR_ID_PANACOM,
2241                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2242                 .subvendor      = PCI_ANY_ID,
2243                 .subdevice      = PCI_ANY_ID,
2244                 .init           = pci_plx9050_init,
2245                 .setup          = pci_default_setup,
2246                 .exit           = pci_plx9050_exit,
2247         },
2248         /*
2249          * Pericom
2250          */
2251         {
2252                 .vendor         = PCI_VENDOR_ID_PERICOM,
2253                 .device         = PCI_ANY_ID,
2254                 .subvendor      = PCI_ANY_ID,
2255                 .subdevice      = PCI_ANY_ID,
2256                 .setup          = pci_pericom_setup,
2257         },
2258         /*
2259          * PLX
2260          */
2261         {
2262                 .vendor         = PCI_VENDOR_ID_PLX,
2263                 .device         = PCI_DEVICE_ID_PLX_9050,
2264                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2265                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2266                 .init           = pci_plx9050_init,
2267                 .setup          = pci_default_setup,
2268                 .exit           = pci_plx9050_exit,
2269         },
2270         {
2271                 .vendor         = PCI_VENDOR_ID_PLX,
2272                 .device         = PCI_DEVICE_ID_PLX_9050,
2273                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2274                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2275                 .init           = pci_plx9050_init,
2276                 .setup          = pci_default_setup,
2277                 .exit           = pci_plx9050_exit,
2278         },
2279         {
2280                 .vendor         = PCI_VENDOR_ID_PLX,
2281                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2282                 .subvendor      = PCI_VENDOR_ID_PLX,
2283                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2284                 .init           = pci_plx9050_init,
2285                 .setup          = pci_default_setup,
2286                 .exit           = pci_plx9050_exit,
2287         },
2288         /*
2289          * SBS Technologies, Inc., PMC-OCTALPRO 232
2290          */
2291         {
2292                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2293                 .device         = PCI_DEVICE_ID_OCTPRO,
2294                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2295                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2296                 .init           = sbs_init,
2297                 .setup          = sbs_setup,
2298                 .exit           = sbs_exit,
2299         },
2300         /*
2301          * SBS Technologies, Inc., PMC-OCTALPRO 422
2302          */
2303         {
2304                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2305                 .device         = PCI_DEVICE_ID_OCTPRO,
2306                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2307                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2308                 .init           = sbs_init,
2309                 .setup          = sbs_setup,
2310                 .exit           = sbs_exit,
2311         },
2312         /*
2313          * SBS Technologies, Inc., P-Octal 232
2314          */
2315         {
2316                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2317                 .device         = PCI_DEVICE_ID_OCTPRO,
2318                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2319                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2320                 .init           = sbs_init,
2321                 .setup          = sbs_setup,
2322                 .exit           = sbs_exit,
2323         },
2324         /*
2325          * SBS Technologies, Inc., P-Octal 422
2326          */
2327         {
2328                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2329                 .device         = PCI_DEVICE_ID_OCTPRO,
2330                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2331                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2332                 .init           = sbs_init,
2333                 .setup          = sbs_setup,
2334                 .exit           = sbs_exit,
2335         },
2336         /*
2337          * SIIG cards - these may be called via parport_serial
2338          */
2339         {
2340                 .vendor         = PCI_VENDOR_ID_SIIG,
2341                 .device         = PCI_ANY_ID,
2342                 .subvendor      = PCI_ANY_ID,
2343                 .subdevice      = PCI_ANY_ID,
2344                 .init           = pci_siig_init,
2345                 .setup          = pci_siig_setup,
2346         },
2347         /*
2348          * Titan cards
2349          */
2350         {
2351                 .vendor         = PCI_VENDOR_ID_TITAN,
2352                 .device         = PCI_DEVICE_ID_TITAN_400L,
2353                 .subvendor      = PCI_ANY_ID,
2354                 .subdevice      = PCI_ANY_ID,
2355                 .setup          = titan_400l_800l_setup,
2356         },
2357         {
2358                 .vendor         = PCI_VENDOR_ID_TITAN,
2359                 .device         = PCI_DEVICE_ID_TITAN_800L,
2360                 .subvendor      = PCI_ANY_ID,
2361                 .subdevice      = PCI_ANY_ID,
2362                 .setup          = titan_400l_800l_setup,
2363         },
2364         /*
2365          * Timedia cards
2366          */
2367         {
2368                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2369                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2370                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2371                 .subdevice      = PCI_ANY_ID,
2372                 .probe          = pci_timedia_probe,
2373                 .init           = pci_timedia_init,
2374                 .setup          = pci_timedia_setup,
2375         },
2376         {
2377                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2378                 .device         = PCI_ANY_ID,
2379                 .subvendor      = PCI_ANY_ID,
2380                 .subdevice      = PCI_ANY_ID,
2381                 .setup          = pci_timedia_setup,
2382         },
2383         /*
2384          * SUNIX (Timedia) cards
2385          * Do not "probe" for these cards as there is at least one combination
2386          * card that should be handled by parport_pc that doesn't match the
2387          * rule in pci_timedia_probe.
2388          * It is part number is MIO5079A but its subdevice ID is 0x0102.
2389          * There are some boards with part number SER5037AL that report
2390          * subdevice ID 0x0002.
2391          */
2392         {
2393                 .vendor         = PCI_VENDOR_ID_SUNIX,
2394                 .device         = PCI_DEVICE_ID_SUNIX_1999,
2395                 .subvendor      = PCI_VENDOR_ID_SUNIX,
2396                 .subdevice      = PCI_ANY_ID,
2397                 .init           = pci_timedia_init,
2398                 .setup          = pci_timedia_setup,
2399         },
2400         /*
2401          * Exar cards
2402          */
2403         {
2404                 .vendor = PCI_VENDOR_ID_EXAR,
2405                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2406                 .subvendor      = PCI_ANY_ID,
2407                 .subdevice      = PCI_ANY_ID,
2408                 .setup          = pci_xr17c154_setup,
2409         },
2410         {
2411                 .vendor = PCI_VENDOR_ID_EXAR,
2412                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2413                 .subvendor      = PCI_ANY_ID,
2414                 .subdevice      = PCI_ANY_ID,
2415                 .setup          = pci_xr17c154_setup,
2416         },
2417         {
2418                 .vendor = PCI_VENDOR_ID_EXAR,
2419                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2420                 .subvendor      = PCI_ANY_ID,
2421                 .subdevice      = PCI_ANY_ID,
2422                 .setup          = pci_xr17c154_setup,
2423         },
2424         {
2425                 .vendor = PCI_VENDOR_ID_EXAR,
2426                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2427                 .subvendor      = PCI_ANY_ID,
2428                 .subdevice      = PCI_ANY_ID,
2429                 .setup          = pci_xr17v35x_setup,
2430         },
2431         {
2432                 .vendor = PCI_VENDOR_ID_EXAR,
2433                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2434                 .subvendor      = PCI_ANY_ID,
2435                 .subdevice      = PCI_ANY_ID,
2436                 .setup          = pci_xr17v35x_setup,
2437         },
2438         {
2439                 .vendor = PCI_VENDOR_ID_EXAR,
2440                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2441                 .subvendor      = PCI_ANY_ID,
2442                 .subdevice      = PCI_ANY_ID,
2443                 .setup          = pci_xr17v35x_setup,
2444         },
2445         {
2446                 .vendor = PCI_VENDOR_ID_EXAR,
2447                 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2448                 .subvendor      = PCI_ANY_ID,
2449                 .subdevice      = PCI_ANY_ID,
2450                 .setup          = pci_xr17v35x_setup,
2451         },
2452         {
2453                 .vendor = PCI_VENDOR_ID_EXAR,
2454                 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2455                 .subvendor      = PCI_ANY_ID,
2456                 .subdevice      = PCI_ANY_ID,
2457                 .setup          = pci_xr17v35x_setup,
2458         },
2459         /*
2460          * Xircom cards
2461          */
2462         {
2463                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2464                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2465                 .subvendor      = PCI_ANY_ID,
2466                 .subdevice      = PCI_ANY_ID,
2467                 .init           = pci_xircom_init,
2468                 .setup          = pci_default_setup,
2469         },
2470         /*
2471          * Netmos cards - these may be called via parport_serial
2472          */
2473         {
2474                 .vendor         = PCI_VENDOR_ID_NETMOS,
2475                 .device         = PCI_ANY_ID,
2476                 .subvendor      = PCI_ANY_ID,
2477                 .subdevice      = PCI_ANY_ID,
2478                 .init           = pci_netmos_init,
2479                 .setup          = pci_netmos_9900_setup,
2480         },
2481         /*
2482          * EndRun Technologies
2483         */
2484         {
2485                 .vendor         = PCI_VENDOR_ID_ENDRUN,
2486                 .device         = PCI_ANY_ID,
2487                 .subvendor      = PCI_ANY_ID,
2488                 .subdevice      = PCI_ANY_ID,
2489                 .init           = pci_endrun_init,
2490                 .setup          = pci_default_setup,
2491         },
2492         /*
2493          * For Oxford Semiconductor Tornado based devices
2494          */
2495         {
2496                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2497                 .device         = PCI_ANY_ID,
2498                 .subvendor      = PCI_ANY_ID,
2499                 .subdevice      = PCI_ANY_ID,
2500                 .init           = pci_oxsemi_tornado_init,
2501                 .setup          = pci_default_setup,
2502         },
2503         {
2504                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2505                 .device         = PCI_ANY_ID,
2506                 .subvendor      = PCI_ANY_ID,
2507                 .subdevice      = PCI_ANY_ID,
2508                 .init           = pci_oxsemi_tornado_init,
2509                 .setup          = pci_default_setup,
2510         },
2511         {
2512                 .vendor         = PCI_VENDOR_ID_DIGI,
2513                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2514                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2515                 .subdevice              = PCI_ANY_ID,
2516                 .init                   = pci_oxsemi_tornado_init,
2517                 .setup          = pci_default_setup,
2518         },
2519         {
2520                 .vendor         = PCI_VENDOR_ID_INTEL,
2521                 .device         = 0x8811,
2522                 .subvendor      = PCI_ANY_ID,
2523                 .subdevice      = PCI_ANY_ID,
2524                 .init           = pci_eg20t_init,
2525                 .setup          = pci_default_setup,
2526         },
2527         {
2528                 .vendor         = PCI_VENDOR_ID_INTEL,
2529                 .device         = 0x8812,
2530                 .subvendor      = PCI_ANY_ID,
2531                 .subdevice      = PCI_ANY_ID,
2532                 .init           = pci_eg20t_init,
2533                 .setup          = pci_default_setup,
2534         },
2535         {
2536                 .vendor         = PCI_VENDOR_ID_INTEL,
2537                 .device         = 0x8813,
2538                 .subvendor      = PCI_ANY_ID,
2539                 .subdevice      = PCI_ANY_ID,
2540                 .init           = pci_eg20t_init,
2541                 .setup          = pci_default_setup,
2542         },
2543         {
2544                 .vendor         = PCI_VENDOR_ID_INTEL,
2545                 .device         = 0x8814,
2546                 .subvendor      = PCI_ANY_ID,
2547                 .subdevice      = PCI_ANY_ID,
2548                 .init           = pci_eg20t_init,
2549                 .setup          = pci_default_setup,
2550         },
2551         {
2552                 .vendor         = 0x10DB,
2553                 .device         = 0x8027,
2554                 .subvendor      = PCI_ANY_ID,
2555                 .subdevice      = PCI_ANY_ID,
2556                 .init           = pci_eg20t_init,
2557                 .setup          = pci_default_setup,
2558         },
2559         {
2560                 .vendor         = 0x10DB,
2561                 .device         = 0x8028,
2562                 .subvendor      = PCI_ANY_ID,
2563                 .subdevice      = PCI_ANY_ID,
2564                 .init           = pci_eg20t_init,
2565                 .setup          = pci_default_setup,
2566         },
2567         {
2568                 .vendor         = 0x10DB,
2569                 .device         = 0x8029,
2570                 .subvendor      = PCI_ANY_ID,
2571                 .subdevice      = PCI_ANY_ID,
2572                 .init           = pci_eg20t_init,
2573                 .setup          = pci_default_setup,
2574         },
2575         {
2576                 .vendor         = 0x10DB,
2577                 .device         = 0x800C,
2578                 .subvendor      = PCI_ANY_ID,
2579                 .subdevice      = PCI_ANY_ID,
2580                 .init           = pci_eg20t_init,
2581                 .setup          = pci_default_setup,
2582         },
2583         {
2584                 .vendor         = 0x10DB,
2585                 .device         = 0x800D,
2586                 .subvendor      = PCI_ANY_ID,
2587                 .subdevice      = PCI_ANY_ID,
2588                 .init           = pci_eg20t_init,
2589                 .setup          = pci_default_setup,
2590         },
2591         /*
2592          * Cronyx Omega PCI (PLX-chip based)
2593          */
2594         {
2595                 .vendor         = PCI_VENDOR_ID_PLX,
2596                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2597                 .subvendor      = PCI_ANY_ID,
2598                 .subdevice      = PCI_ANY_ID,
2599                 .setup          = pci_omegapci_setup,
2600         },
2601         /* WCH CH353 1S1P card (16550 clone) */
2602         {
2603                 .vendor         = PCI_VENDOR_ID_WCH,
2604                 .device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2605                 .subvendor      = PCI_ANY_ID,
2606                 .subdevice      = PCI_ANY_ID,
2607                 .setup          = pci_wch_ch353_setup,
2608         },
2609         /* WCH CH353 2S1P card (16550 clone) */
2610         {
2611                 .vendor         = PCI_VENDOR_ID_WCH,
2612                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2613                 .subvendor      = PCI_ANY_ID,
2614                 .subdevice      = PCI_ANY_ID,
2615                 .setup          = pci_wch_ch353_setup,
2616         },
2617         /* WCH CH353 4S card (16550 clone) */
2618         {
2619                 .vendor         = PCI_VENDOR_ID_WCH,
2620                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2621                 .subvendor      = PCI_ANY_ID,
2622                 .subdevice      = PCI_ANY_ID,
2623                 .setup          = pci_wch_ch353_setup,
2624         },
2625         /* WCH CH353 2S1PF card (16550 clone) */
2626         {
2627                 .vendor         = PCI_VENDOR_ID_WCH,
2628                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2629                 .subvendor      = PCI_ANY_ID,
2630                 .subdevice      = PCI_ANY_ID,
2631                 .setup          = pci_wch_ch353_setup,
2632         },
2633         /* WCH CH352 2S card (16550 clone) */
2634         {
2635                 .vendor         = PCI_VENDOR_ID_WCH,
2636                 .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2637                 .subvendor      = PCI_ANY_ID,
2638                 .subdevice      = PCI_ANY_ID,
2639                 .setup          = pci_wch_ch353_setup,
2640         },
2641         /* WCH CH382 2S card (16850 clone) */
2642         {
2643                 .vendor         = PCIE_VENDOR_ID_WCH,
2644                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S,
2645                 .subvendor      = PCI_ANY_ID,
2646                 .subdevice      = PCI_ANY_ID,
2647                 .setup          = pci_wch_ch38x_setup,
2648         },
2649         /* WCH CH382 2S1P card (16850 clone) */
2650         {
2651                 .vendor         = PCIE_VENDOR_ID_WCH,
2652                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2653                 .subvendor      = PCI_ANY_ID,
2654                 .subdevice      = PCI_ANY_ID,
2655                 .setup          = pci_wch_ch38x_setup,
2656         },
2657         /* WCH CH384 4S card (16850 clone) */
2658         {
2659                 .vendor         = PCIE_VENDOR_ID_WCH,
2660                 .device         = PCIE_DEVICE_ID_WCH_CH384_4S,
2661                 .subvendor      = PCI_ANY_ID,
2662                 .subdevice      = PCI_ANY_ID,
2663                 .setup          = pci_wch_ch38x_setup,
2664         },
2665         /*
2666          * ASIX devices with FIFO bug
2667          */
2668         {
2669                 .vendor         = PCI_VENDOR_ID_ASIX,
2670                 .device         = PCI_ANY_ID,
2671                 .subvendor      = PCI_ANY_ID,
2672                 .subdevice      = PCI_ANY_ID,
2673                 .setup          = pci_asix_setup,
2674         },
2675         /*
2676          * Commtech, Inc. Fastcom adapters
2677          *
2678          */
2679         {
2680                 .vendor = PCI_VENDOR_ID_COMMTECH,
2681                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2682                 .subvendor      = PCI_ANY_ID,
2683                 .subdevice      = PCI_ANY_ID,
2684                 .setup          = pci_fastcom335_setup,
2685         },
2686         {
2687                 .vendor = PCI_VENDOR_ID_COMMTECH,
2688                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2689                 .subvendor      = PCI_ANY_ID,
2690                 .subdevice      = PCI_ANY_ID,
2691                 .setup          = pci_fastcom335_setup,
2692         },
2693         {
2694                 .vendor = PCI_VENDOR_ID_COMMTECH,
2695                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2696                 .subvendor      = PCI_ANY_ID,
2697                 .subdevice      = PCI_ANY_ID,
2698                 .setup          = pci_fastcom335_setup,
2699         },
2700         {
2701                 .vendor = PCI_VENDOR_ID_COMMTECH,
2702                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2703                 .subvendor      = PCI_ANY_ID,
2704                 .subdevice      = PCI_ANY_ID,
2705                 .setup          = pci_fastcom335_setup,
2706         },
2707         {
2708                 .vendor = PCI_VENDOR_ID_COMMTECH,
2709                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2710                 .subvendor      = PCI_ANY_ID,
2711                 .subdevice      = PCI_ANY_ID,
2712                 .setup          = pci_xr17v35x_setup,
2713         },
2714         {
2715                 .vendor = PCI_VENDOR_ID_COMMTECH,
2716                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2717                 .subvendor      = PCI_ANY_ID,
2718                 .subdevice      = PCI_ANY_ID,
2719                 .setup          = pci_xr17v35x_setup,
2720         },
2721         {
2722                 .vendor = PCI_VENDOR_ID_COMMTECH,
2723                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2724                 .subvendor      = PCI_ANY_ID,
2725                 .subdevice      = PCI_ANY_ID,
2726                 .setup          = pci_xr17v35x_setup,
2727         },
2728         /*
2729          * Broadcom TruManage (NetXtreme)
2730          */
2731         {
2732                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2733                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2734                 .subvendor      = PCI_ANY_ID,
2735                 .subdevice      = PCI_ANY_ID,
2736                 .setup          = pci_brcm_trumanage_setup,
2737         },
2738         {
2739                 .vendor         = 0x1c29,
2740                 .device         = 0x1104,
2741                 .subvendor      = PCI_ANY_ID,
2742                 .subdevice      = PCI_ANY_ID,
2743                 .setup          = pci_fintek_setup,
2744                 .init           = pci_fintek_init,
2745         },
2746         {
2747                 .vendor         = 0x1c29,
2748                 .device         = 0x1108,
2749                 .subvendor      = PCI_ANY_ID,
2750                 .subdevice      = PCI_ANY_ID,
2751                 .setup          = pci_fintek_setup,
2752                 .init           = pci_fintek_init,
2753         },
2754         {
2755                 .vendor         = 0x1c29,
2756                 .device         = 0x1112,
2757                 .subvendor      = PCI_ANY_ID,
2758                 .subdevice      = PCI_ANY_ID,
2759                 .setup          = pci_fintek_setup,
2760                 .init           = pci_fintek_init,
2761         },
2762 
2763         /*
2764          * Default "match everything" terminator entry
2765          */
2766         {
2767                 .vendor         = PCI_ANY_ID,
2768                 .device         = PCI_ANY_ID,
2769                 .subvendor      = PCI_ANY_ID,
2770                 .subdevice      = PCI_ANY_ID,
2771                 .setup          = pci_default_setup,
2772         }
2773 };
2774 
2775 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2776 {
2777         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2778 }
2779 
2780 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2781 {
2782         struct pci_serial_quirk *quirk;
2783 
2784         for (quirk = pci_serial_quirks; ; quirk++)
2785                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2786                     quirk_id_matches(quirk->device, dev->device) &&
2787                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2788                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2789                         break;
2790         return quirk;
2791 }
2792 
2793 static inline int get_pci_irq(struct pci_dev *dev,
2794                                 const struct pciserial_board *board)
2795 {
2796         if (board->flags & FL_NOIRQ)
2797                 return 0;
2798         else
2799                 return dev->irq;
2800 }
2801 
2802 /*
2803  * This is the configuration table for all of the PCI serial boards
2804  * which we support.  It is directly indexed by the pci_board_num_t enum
2805  * value, which is encoded in the pci_device_id PCI probe table's
2806  * driver_data member.
2807  *
2808  * The makeup of these names are:
2809  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2810  *
2811  *  bn          = PCI BAR number
2812  *  bt          = Index using PCI BARs
2813  *  n           = number of serial ports
2814  *  baud        = baud rate
2815  *  offsetinhex = offset for each sequential port (in hex)
2816  *
2817  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2818  *
2819  * Please note: in theory if n = 1, _bt infix should make no difference.
2820  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2821  */
2822 enum pci_board_num_t {
2823         pbn_default = 0,
2824 
2825         pbn_b0_1_115200,
2826         pbn_b0_2_115200,
2827         pbn_b0_4_115200,
2828         pbn_b0_5_115200,
2829         pbn_b0_8_115200,
2830 
2831         pbn_b0_1_921600,
2832         pbn_b0_2_921600,
2833         pbn_b0_4_921600,
2834 
2835         pbn_b0_2_1130000,
2836 
2837         pbn_b0_4_1152000,
2838 
2839         pbn_b0_2_1152000_200,
2840         pbn_b0_4_1152000_200,
2841         pbn_b0_8_1152000_200,
2842 
2843         pbn_b0_2_1843200,
2844         pbn_b0_4_1843200,
2845 
2846         pbn_b0_2_1843200_200,
2847         pbn_b0_4_1843200_200,
2848         pbn_b0_8_1843200_200,
2849 
2850         pbn_b0_1_4000000,
2851 
2852         pbn_b0_bt_1_115200,
2853         pbn_b0_bt_2_115200,
2854         pbn_b0_bt_4_115200,
2855         pbn_b0_bt_8_115200,
2856 
2857         pbn_b0_bt_1_460800,
2858         pbn_b0_bt_2_460800,
2859         pbn_b0_bt_4_460800,
2860 
2861         pbn_b0_bt_1_921600,
2862         pbn_b0_bt_2_921600,
2863         pbn_b0_bt_4_921600,
2864         pbn_b0_bt_8_921600,
2865 
2866         pbn_b1_1_115200,
2867         pbn_b1_2_115200,
2868         pbn_b1_4_115200,
2869         pbn_b1_8_115200,
2870         pbn_b1_16_115200,
2871 
2872         pbn_b1_1_921600,
2873         pbn_b1_2_921600,
2874         pbn_b1_4_921600,
2875         pbn_b1_8_921600,
2876 
2877         pbn_b1_2_1250000,
2878 
2879         pbn_b1_bt_1_115200,
2880         pbn_b1_bt_2_115200,
2881         pbn_b1_bt_4_115200,
2882 
2883         pbn_b1_bt_2_921600,
2884 
2885         pbn_b1_1_1382400,
2886         pbn_b1_2_1382400,
2887         pbn_b1_4_1382400,
2888         pbn_b1_8_1382400,
2889 
2890         pbn_b2_1_115200,
2891         pbn_b2_2_115200,
2892         pbn_b2_4_115200,
2893         pbn_b2_8_115200,
2894 
2895         pbn_b2_1_460800,
2896         pbn_b2_4_460800,
2897         pbn_b2_8_460800,
2898         pbn_b2_16_460800,
2899 
2900         pbn_b2_1_921600,
2901         pbn_b2_4_921600,
2902         pbn_b2_8_921600,
2903 
2904         pbn_b2_8_1152000,
2905 
2906         pbn_b2_bt_1_115200,
2907         pbn_b2_bt_2_115200,
2908         pbn_b2_bt_4_115200,
2909 
2910         pbn_b2_bt_2_921600,
2911         pbn_b2_bt_4_921600,
2912 
2913         pbn_b3_2_115200,
2914         pbn_b3_4_115200,
2915         pbn_b3_8_115200,
2916 
2917         pbn_b4_bt_2_921600,
2918         pbn_b4_bt_4_921600,
2919         pbn_b4_bt_8_921600,
2920 
2921         /*
2922          * Board-specific versions.
2923          */
2924         pbn_panacom,
2925         pbn_panacom2,
2926         pbn_panacom4,
2927         pbn_plx_romulus,
2928         pbn_endrun_2_4000000,
2929         pbn_oxsemi,
2930         pbn_oxsemi_1_4000000,
2931         pbn_oxsemi_2_4000000,
2932         pbn_oxsemi_4_4000000,
2933         pbn_oxsemi_8_4000000,
2934         pbn_intel_i960,
2935         pbn_sgi_ioc3,
2936         pbn_computone_4,
2937         pbn_computone_6,
2938         pbn_computone_8,
2939         pbn_sbsxrsio,
2940         pbn_exar_XR17C152,
2941         pbn_exar_XR17C154,
2942         pbn_exar_XR17C158,
2943         pbn_exar_XR17V352,
2944         pbn_exar_XR17V354,
2945         pbn_exar_XR17V358,
2946         pbn_exar_XR17V4358,
2947         pbn_exar_XR17V8358,
2948         pbn_exar_ibm_saturn,
2949         pbn_pasemi_1682M,
2950         pbn_ni8430_2,
2951         pbn_ni8430_4,
2952         pbn_ni8430_8,
2953         pbn_ni8430_16,
2954         pbn_ADDIDATA_PCIe_1_3906250,
2955         pbn_ADDIDATA_PCIe_2_3906250,
2956         pbn_ADDIDATA_PCIe_4_3906250,
2957         pbn_ADDIDATA_PCIe_8_3906250,
2958         pbn_ce4100_1_115200,
2959         pbn_byt,
2960         pbn_qrk,
2961         pbn_omegapci,
2962         pbn_NETMOS9900_2s_115200,
2963         pbn_brcm_trumanage,
2964         pbn_fintek_4,
2965         pbn_fintek_8,
2966         pbn_fintek_12,
2967         pbn_wch382_2,
2968         pbn_wch384_4,
2969         pbn_pericom_PI7C9X7951,
2970         pbn_pericom_PI7C9X7952,
2971         pbn_pericom_PI7C9X7954,
2972         pbn_pericom_PI7C9X7958,
2973 };
2974 
2975 /*
2976  * uart_offset - the space between channels
2977  * reg_shift   - describes how the UART registers are mapped
2978  *               to PCI memory by the card.
2979  * For example IER register on SBS, Inc. PMC-OctPro is located at
2980  * offset 0x10 from the UART base, while UART_IER is defined as 1
2981  * in include/linux/serial_reg.h,
2982  * see first lines of serial_in() and serial_out() in 8250.c
2983 */
2984 
2985 static struct pciserial_board pci_boards[] = {
2986         [pbn_default] = {
2987                 .flags          = FL_BASE0,
2988                 .num_ports      = 1,
2989                 .base_baud      = 115200,
2990                 .uart_offset    = 8,
2991         },
2992         [pbn_b0_1_115200] = {
2993                 .flags          = FL_BASE0,
2994                 .num_ports      = 1,
2995                 .base_baud      = 115200,
2996                 .uart_offset    = 8,
2997         },
2998         [pbn_b0_2_115200] = {
2999                 .flags          = FL_BASE0,
3000                 .num_ports      = 2,
3001                 .base_baud      = 115200,
3002                 .uart_offset    = 8,
3003         },
3004         [pbn_b0_4_115200] = {
3005                 .flags          = FL_BASE0,
3006                 .num_ports      = 4,
3007                 .base_baud      = 115200,
3008                 .uart_offset    = 8,
3009         },
3010         [pbn_b0_5_115200] = {
3011                 .flags          = FL_BASE0,
3012                 .num_ports      = 5,
3013                 .base_baud      = 115200,
3014                 .uart_offset    = 8,
3015         },
3016         [pbn_b0_8_115200] = {
3017                 .flags          = FL_BASE0,
3018                 .num_ports      = 8,
3019                 .base_baud      = 115200,
3020                 .uart_offset    = 8,
3021         },
3022         [pbn_b0_1_921600] = {
3023                 .flags          = FL_BASE0,
3024                 .num_ports      = 1,
3025                 .base_baud      = 921600,
3026                 .uart_offset    = 8,
3027         },
3028         [pbn_b0_2_921600] = {
3029                 .flags          = FL_BASE0,
3030                 .num_ports      = 2,
3031                 .base_baud      = 921600,
3032                 .uart_offset    = 8,
3033         },
3034         [pbn_b0_4_921600] = {
3035                 .flags          = FL_BASE0,
3036                 .num_ports      = 4,
3037                 .base_baud      = 921600,
3038                 .uart_offset    = 8,
3039         },
3040 
3041         [pbn_b0_2_1130000] = {
3042                 .flags          = FL_BASE0,
3043                 .num_ports      = 2,
3044                 .base_baud      = 1130000,
3045                 .uart_offset    = 8,
3046         },
3047 
3048         [pbn_b0_4_1152000] = {
3049                 .flags          = FL_BASE0,
3050                 .num_ports      = 4,
3051                 .base_baud      = 1152000,
3052                 .uart_offset    = 8,
3053         },
3054 
3055         [pbn_b0_2_1152000_200] = {
3056                 .flags          = FL_BASE0,
3057                 .num_ports      = 2,
3058                 .base_baud      = 1152000,
3059                 .uart_offset    = 0x200,
3060         },
3061 
3062         [pbn_b0_4_1152000_200] = {
3063                 .flags          = FL_BASE0,
3064                 .num_ports      = 4,
3065                 .base_baud      = 1152000,
3066                 .uart_offset    = 0x200,
3067         },
3068 
3069         [pbn_b0_8_1152000_200] = {
3070                 .flags          = FL_BASE0,
3071                 .num_ports      = 8,
3072                 .base_baud      = 1152000,
3073                 .uart_offset    = 0x200,
3074         },
3075 
3076         [pbn_b0_2_1843200] = {
3077                 .flags          = FL_BASE0,
3078                 .num_ports      = 2,
3079                 .base_baud      = 1843200,
3080                 .uart_offset    = 8,
3081         },
3082         [pbn_b0_4_1843200] = {
3083                 .flags          = FL_BASE0,
3084                 .num_ports      = 4,
3085                 .base_baud      = 1843200,
3086                 .uart_offset    = 8,
3087         },
3088 
3089         [pbn_b0_2_1843200_200] = {
3090                 .flags          = FL_BASE0,
3091                 .num_ports      = 2,
3092                 .base_baud      = 1843200,
3093                 .uart_offset    = 0x200,
3094         },
3095         [pbn_b0_4_1843200_200] = {
3096                 .flags          = FL_BASE0,
3097                 .num_ports      = 4,
3098                 .base_baud      = 1843200,
3099                 .uart_offset    = 0x200,
3100         },
3101         [pbn_b0_8_1843200_200] = {
3102                 .flags          = FL_BASE0,
3103                 .num_ports      = 8,
3104                 .base_baud      = 1843200,
3105                 .uart_offset    = 0x200,
3106         },
3107         [pbn_b0_1_4000000] = {
3108                 .flags          = FL_BASE0,
3109                 .num_ports      = 1,
3110                 .base_baud      = 4000000,
3111                 .uart_offset    = 8,
3112         },
3113 
3114         [pbn_b0_bt_1_115200] = {
3115                 .flags          = FL_BASE0|FL_BASE_BARS,
3116                 .num_ports      = 1,
3117                 .base_baud      = 115200,
3118                 .uart_offset    = 8,
3119         },
3120         [pbn_b0_bt_2_115200] = {
3121                 .flags          = FL_BASE0|FL_BASE_BARS,
3122                 .num_ports      = 2,
3123                 .base_baud      = 115200,
3124                 .uart_offset    = 8,
3125         },
3126         [pbn_b0_bt_4_115200] = {
3127                 .flags          = FL_BASE0|FL_BASE_BARS,
3128                 .num_ports      = 4,
3129                 .base_baud      = 115200,
3130                 .uart_offset    = 8,
3131         },
3132         [pbn_b0_bt_8_115200] = {
3133                 .flags          = FL_BASE0|FL_BASE_BARS,
3134                 .num_ports      = 8,
3135                 .base_baud      = 115200,
3136                 .uart_offset    = 8,
3137         },
3138 
3139         [pbn_b0_bt_1_460800] = {
3140                 .flags          = FL_BASE0|FL_BASE_BARS,
3141                 .num_ports      = 1,
3142                 .base_baud      = 460800,
3143                 .uart_offset    = 8,
3144         },
3145         [pbn_b0_bt_2_460800] = {
3146                 .flags          = FL_BASE0|FL_BASE_BARS,
3147                 .num_ports      = 2,
3148                 .base_baud      = 460800,
3149                 .uart_offset    = 8,
3150         },
3151         [pbn_b0_bt_4_460800] = {
3152                 .flags          = FL_BASE0|FL_BASE_BARS,
3153                 .num_ports      = 4,
3154                 .base_baud      = 460800,
3155                 .uart_offset    = 8,
3156         },
3157 
3158         [pbn_b0_bt_1_921600] = {
3159                 .flags          = FL_BASE0|FL_BASE_BARS,
3160                 .num_ports      = 1,
3161                 .base_baud      = 921600,
3162                 .uart_offset    = 8,
3163         },
3164         [pbn_b0_bt_2_921600] = {
3165                 .flags          = FL_BASE0|FL_BASE_BARS,
3166                 .num_ports      = 2,
3167                 .base_baud      = 921600,
3168                 .uart_offset    = 8,
3169         },
3170         [pbn_b0_bt_4_921600] = {
3171                 .flags          = FL_BASE0|FL_BASE_BARS,
3172                 .num_ports      = 4,
3173                 .base_baud      = 921600,
3174                 .uart_offset    = 8,
3175         },
3176         [pbn_b0_bt_8_921600] = {
3177                 .flags          = FL_BASE0|FL_BASE_BARS,
3178                 .num_ports      = 8,
3179                 .base_baud      = 921600,
3180                 .uart_offset    = 8,
3181         },
3182 
3183         [pbn_b1_1_115200] = {
3184                 .flags          = FL_BASE1,
3185                 .num_ports      = 1,
3186                 .base_baud      = 115200,
3187                 .uart_offset    = 8,
3188         },
3189         [pbn_b1_2_115200] = {
3190                 .flags          = FL_BASE1,
3191                 .num_ports      = 2,
3192                 .base_baud      = 115200,
3193                 .uart_offset    = 8,
3194         },
3195         [pbn_b1_4_115200] = {
3196                 .flags          = FL_BASE1,
3197                 .num_ports      = 4,
3198                 .base_baud      = 115200,
3199                 .uart_offset    = 8,
3200         },
3201         [pbn_b1_8_115200] = {
3202                 .flags          = FL_BASE1,
3203                 .num_ports      = 8,
3204                 .base_baud      = 115200,
3205                 .uart_offset    = 8,
3206         },
3207         [pbn_b1_16_115200] = {
3208                 .flags          = FL_BASE1,
3209                 .num_ports      = 16,
3210                 .base_baud      = 115200,
3211                 .uart_offset    = 8,
3212         },
3213 
3214         [pbn_b1_1_921600] = {
3215                 .flags          = FL_BASE1,
3216                 .num_ports      = 1,
3217                 .base_baud      = 921600,
3218                 .uart_offset    = 8,
3219         },
3220         [pbn_b1_2_921600] = {
3221                 .flags          = FL_BASE1,
3222                 .num_ports      = 2,
3223                 .base_baud      = 921600,
3224                 .uart_offset    = 8,
3225         },
3226         [pbn_b1_4_921600] = {
3227                 .flags          = FL_BASE1,
3228                 .num_ports      = 4,
3229                 .base_baud      = 921600,
3230                 .uart_offset    = 8,
3231         },
3232         [pbn_b1_8_921600] = {
3233                 .flags          = FL_BASE1,
3234                 .num_ports      = 8,
3235                 .base_baud      = 921600,
3236                 .uart_offset    = 8,
3237         },
3238         [pbn_b1_2_1250000] = {
3239                 .flags          = FL_BASE1,
3240                 .num_ports      = 2,
3241                 .base_baud      = 1250000,
3242                 .uart_offset    = 8,
3243         },
3244 
3245         [pbn_b1_bt_1_115200] = {
3246                 .flags          = FL_BASE1|FL_BASE_BARS,
3247                 .num_ports      = 1,
3248                 .base_baud      = 115200,
3249                 .uart_offset    = 8,
3250         },
3251         [pbn_b1_bt_2_115200] = {
3252                 .flags          = FL_BASE1|FL_BASE_BARS,
3253                 .num_ports      = 2,
3254                 .base_baud      = 115200,
3255                 .uart_offset    = 8,
3256         },
3257         [pbn_b1_bt_4_115200] = {
3258                 .flags          = FL_BASE1|FL_BASE_BARS,
3259                 .num_ports      = 4,
3260                 .base_baud      = 115200,
3261                 .uart_offset    = 8,
3262         },
3263 
3264         [pbn_b1_bt_2_921600] = {
3265                 .flags          = FL_BASE1|FL_BASE_BARS,
3266                 .num_ports      = 2,
3267                 .base_baud      = 921600,
3268                 .uart_offset    = 8,
3269         },
3270 
3271         [pbn_b1_1_1382400] = {
3272                 .flags          = FL_BASE1,
3273                 .num_ports      = 1,
3274                 .base_baud      = 1382400,
3275                 .uart_offset    = 8,
3276         },
3277         [pbn_b1_2_1382400] = {
3278                 .flags          = FL_BASE1,
3279                 .num_ports      = 2,
3280                 .base_baud      = 1382400,
3281                 .uart_offset    = 8,
3282         },
3283         [pbn_b1_4_1382400] = {
3284                 .flags          = FL_BASE1,
3285                 .num_ports      = 4,
3286                 .base_baud      = 1382400,
3287                 .uart_offset    = 8,
3288         },
3289         [pbn_b1_8_1382400] = {
3290                 .flags          = FL_BASE1,
3291                 .num_ports      = 8,
3292                 .base_baud      = 1382400,
3293                 .uart_offset    = 8,
3294         },
3295 
3296         [pbn_b2_1_115200] = {
3297                 .flags          = FL_BASE2,
3298                 .num_ports      = 1,
3299                 .base_baud      = 115200,
3300                 .uart_offset    = 8,
3301         },
3302         [pbn_b2_2_115200] = {
3303                 .flags          = FL_BASE2,
3304                 .num_ports      = 2,
3305                 .base_baud      = 115200,
3306                 .uart_offset    = 8,
3307         },
3308         [pbn_b2_4_115200] = {
3309                 .flags          = FL_BASE2,
3310                 .num_ports      = 4,
3311                 .base_baud      = 115200,
3312                 .uart_offset    = 8,
3313         },
3314         [pbn_b2_8_115200] = {
3315                 .flags          = FL_BASE2,
3316                 .num_ports      = 8,
3317                 .base_baud      = 115200,
3318                 .uart_offset    = 8,
3319         },
3320 
3321         [pbn_b2_1_460800] = {
3322                 .flags          = FL_BASE2,
3323                 .num_ports      = 1,
3324                 .base_baud      = 460800,
3325                 .uart_offset    = 8,
3326         },
3327         [pbn_b2_4_460800] = {
3328                 .flags          = FL_BASE2,
3329                 .num_ports      = 4,
3330                 .base_baud      = 460800,
3331                 .uart_offset    = 8,
3332         },
3333         [pbn_b2_8_460800] = {
3334                 .flags          = FL_BASE2,
3335                 .num_ports      = 8,
3336                 .base_baud      = 460800,
3337                 .uart_offset    = 8,
3338         },
3339         [pbn_b2_16_460800] = {
3340                 .flags          = FL_BASE2,
3341                 .num_ports      = 16,
3342                 .base_baud      = 460800,
3343                 .uart_offset    = 8,
3344          },
3345 
3346         [pbn_b2_1_921600] = {
3347                 .flags          = FL_BASE2,
3348                 .num_ports      = 1,
3349                 .base_baud      = 921600,
3350                 .uart_offset    = 8,
3351         },
3352         [pbn_b2_4_921600] = {
3353                 .flags          = FL_BASE2,
3354                 .num_ports      = 4,
3355                 .base_baud      = 921600,
3356                 .uart_offset    = 8,
3357         },
3358         [pbn_b2_8_921600] = {
3359                 .flags          = FL_BASE2,
3360                 .num_ports      = 8,
3361                 .base_baud      = 921600,
3362                 .uart_offset    = 8,
3363         },
3364 
3365         [pbn_b2_8_1152000] = {
3366                 .flags          = FL_BASE2,
3367                 .num_ports      = 8,
3368                 .base_baud      = 1152000,
3369                 .uart_offset    = 8,
3370         },
3371 
3372         [pbn_b2_bt_1_115200] = {
3373                 .flags          = FL_BASE2|FL_BASE_BARS,
3374                 .num_ports      = 1,
3375                 .base_baud      = 115200,
3376                 .uart_offset    = 8,
3377         },
3378         [pbn_b2_bt_2_115200] = {
3379                 .flags          = FL_BASE2|FL_BASE_BARS,
3380                 .num_ports      = 2,
3381                 .base_baud      = 115200,
3382                 .uart_offset    = 8,
3383         },
3384         [pbn_b2_bt_4_115200] = {
3385                 .flags          = FL_BASE2|FL_BASE_BARS,
3386                 .num_ports      = 4,
3387                 .base_baud      = 115200,
3388                 .uart_offset    = 8,
3389         },
3390 
3391         [pbn_b2_bt_2_921600] = {
3392                 .flags          = FL_BASE2|FL_BASE_BARS,
3393                 .num_ports      = 2,
3394                 .base_baud      = 921600,
3395                 .uart_offset    = 8,
3396         },
3397         [pbn_b2_bt_4_921600] = {
3398                 .flags          = FL_BASE2|FL_BASE_BARS,
3399                 .num_ports      = 4,
3400                 .base_baud      = 921600,
3401                 .uart_offset    = 8,
3402         },
3403 
3404         [pbn_b3_2_115200] = {
3405                 .flags          = FL_BASE3,
3406                 .num_ports      = 2,
3407                 .base_baud      = 115200,
3408                 .uart_offset    = 8,
3409         },
3410         [pbn_b3_4_115200] = {
3411                 .flags          = FL_BASE3,
3412                 .num_ports      = 4,
3413                 .base_baud      = 115200,
3414                 .uart_offset    = 8,
3415         },
3416         [pbn_b3_8_115200] = {
3417                 .flags          = FL_BASE3,
3418                 .num_ports      = 8,
3419                 .base_baud      = 115200,
3420                 .uart_offset    = 8,
3421         },
3422 
3423         [pbn_b4_bt_2_921600] = {
3424                 .flags          = FL_BASE4,
3425                 .num_ports      = 2,
3426                 .base_baud      = 921600,
3427                 .uart_offset    = 8,
3428         },
3429         [pbn_b4_bt_4_921600] = {
3430                 .flags          = FL_BASE4,
3431                 .num_ports      = 4,
3432                 .base_baud      = 921600,
3433                 .uart_offset    = 8,
3434         },
3435         [pbn_b4_bt_8_921600] = {
3436                 .flags          = FL_BASE4,
3437                 .num_ports      = 8,
3438                 .base_baud      = 921600,
3439                 .uart_offset    = 8,
3440         },
3441 
3442         /*
3443          * Entries following this are board-specific.
3444          */
3445 
3446         /*
3447          * Panacom - IOMEM
3448          */
3449         [pbn_panacom] = {
3450                 .flags          = FL_BASE2,
3451                 .num_ports      = 2,
3452                 .base_baud      = 921600,
3453                 .uart_offset    = 0x400,
3454                 .reg_shift      = 7,
3455         },
3456         [pbn_panacom2] = {
3457                 .flags          = FL_BASE2|FL_BASE_BARS,
3458                 .num_ports      = 2,
3459                 .base_baud      = 921600,
3460                 .uart_offset    = 0x400,
3461                 .reg_shift      = 7,
3462         },
3463         [pbn_panacom4] = {
3464                 .flags          = FL_BASE2|FL_BASE_BARS,
3465                 .num_ports      = 4,
3466                 .base_baud      = 921600,
3467                 .uart_offset    = 0x400,
3468                 .reg_shift      = 7,
3469         },
3470 
3471         /* I think this entry is broken - the first_offset looks wrong --rmk */
3472         [pbn_plx_romulus] = {
3473                 .flags          = FL_BASE2,
3474                 .num_ports      = 4,
3475                 .base_baud      = 921600,
3476                 .uart_offset    = 8 << 2,
3477                 .reg_shift      = 2,
3478                 .first_offset   = 0x03,
3479         },
3480 
3481         /*
3482          * EndRun Technologies
3483         * Uses the size of PCI Base region 0 to
3484         * signal now many ports are available
3485         * 2 port 952 Uart support
3486         */
3487         [pbn_endrun_2_4000000] = {
3488                 .flags          = FL_BASE0,
3489                 .num_ports      = 2,
3490                 .base_baud      = 4000000,
3491                 .uart_offset    = 0x200,
3492                 .first_offset   = 0x1000,
3493         },
3494 
3495         /*
3496          * This board uses the size of PCI Base region 0 to
3497          * signal now many ports are available
3498          */
3499         [pbn_oxsemi] = {
3500                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3501                 .num_ports      = 32,
3502                 .base_baud      = 115200,
3503                 .uart_offset    = 8,
3504         },
3505         [pbn_oxsemi_1_4000000] = {
3506                 .flags          = FL_BASE0,
3507                 .num_ports      = 1,
3508                 .base_baud      = 4000000,
3509                 .uart_offset    = 0x200,
3510                 .first_offset   = 0x1000,
3511         },
3512         [pbn_oxsemi_2_4000000] = {
3513                 .flags          = FL_BASE0,
3514                 .num_ports      = 2,
3515                 .base_baud      = 4000000,
3516                 .uart_offset    = 0x200,
3517                 .first_offset   = 0x1000,
3518         },
3519         [pbn_oxsemi_4_4000000] = {
3520                 .flags          = FL_BASE0,
3521                 .num_ports      = 4,
3522                 .base_baud      = 4000000,
3523                 .uart_offset    = 0x200,
3524                 .first_offset   = 0x1000,
3525         },
3526         [pbn_oxsemi_8_4000000] = {
3527                 .flags          = FL_BASE0,
3528                 .num_ports      = 8,
3529                 .base_baud      = 4000000,
3530                 .uart_offset    = 0x200,
3531                 .first_offset   = 0x1000,
3532         },
3533 
3534 
3535         /*
3536          * EKF addition for i960 Boards form EKF with serial port.
3537          * Max 256 ports.
3538          */
3539         [pbn_intel_i960] = {
3540                 .flags          = FL_BASE0,
3541                 .num_ports      = 32,
3542                 .base_baud      = 921600,
3543                 .uart_offset    = 8 << 2,
3544                 .reg_shift      = 2,
3545                 .first_offset   = 0x10000,
3546         },
3547         [pbn_sgi_ioc3] = {
3548                 .flags          = FL_BASE0|FL_NOIRQ,
3549                 .num_ports      = 1,
3550                 .base_baud      = 458333,
3551                 .uart_offset    = 8,
3552                 .reg_shift      = 0,
3553                 .first_offset   = 0x20178,
3554         },
3555 
3556         /*
3557          * Computone - uses IOMEM.
3558          */
3559         [pbn_computone_4] = {
3560                 .flags          = FL_BASE0,
3561                 .num_ports      = 4,
3562                 .base_baud      = 921600,
3563                 .uart_offset    = 0x40,
3564                 .reg_shift      = 2,
3565                 .first_offset   = 0x200,
3566         },
3567         [pbn_computone_6] = {
3568                 .flags          = FL_BASE0,
3569                 .num_ports      = 6,
3570                 .base_baud      = 921600,
3571                 .uart_offset    = 0x40,
3572                 .reg_shift      = 2,
3573                 .first_offset   = 0x200,
3574         },
3575         [pbn_computone_8] = {
3576                 .flags          = FL_BASE0,
3577                 .num_ports      = 8,
3578                 .base_baud      = 921600,
3579                 .uart_offset    = 0x40,
3580                 .reg_shift      = 2,
3581                 .first_offset   = 0x200,
3582         },
3583         [pbn_sbsxrsio] = {
3584                 .flags          = FL_BASE0,
3585                 .num_ports      = 8,
3586                 .base_baud      = 460800,
3587                 .uart_offset    = 256,
3588                 .reg_shift      = 4,
3589         },
3590         /*
3591          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3592          *  Only basic 16550A support.
3593          *  XR17C15[24] are not tested, but they should work.
3594          */
3595         [pbn_exar_XR17C152] = {
3596                 .flags          = FL_BASE0,
3597                 .num_ports      = 2,
3598                 .base_baud      = 921600,
3599                 .uart_offset    = 0x200,
3600         },
3601         [pbn_exar_XR17C154] = {
3602                 .flags          = FL_BASE0,
3603                 .num_ports      = 4,
3604                 .base_baud      = 921600,
3605                 .uart_offset    = 0x200,
3606         },
3607         [pbn_exar_XR17C158] = {
3608                 .flags          = FL_BASE0,
3609                 .num_ports      = 8,
3610                 .base_baud      = 921600,
3611                 .uart_offset    = 0x200,
3612         },
3613         [pbn_exar_XR17V352] = {
3614                 .flags          = FL_BASE0,
3615                 .num_ports      = 2,
3616                 .base_baud      = 7812500,
3617                 .uart_offset    = 0x400,
3618                 .reg_shift      = 0,
3619                 .first_offset   = 0,
3620         },
3621         [pbn_exar_XR17V354] = {
3622                 .flags          = FL_BASE0,
3623                 .num_ports      = 4,
3624                 .base_baud      = 7812500,
3625                 .uart_offset    = 0x400,
3626                 .reg_shift      = 0,
3627                 .first_offset   = 0,
3628         },
3629         [pbn_exar_XR17V358] = {
3630                 .flags          = FL_BASE0,
3631                 .num_ports      = 8,
3632                 .base_baud      = 7812500,
3633                 .uart_offset    = 0x400,
3634                 .reg_shift      = 0,
3635                 .first_offset   = 0,
3636         },
3637         [pbn_exar_XR17V4358] = {
3638                 .flags          = FL_BASE0,
3639                 .num_ports      = 12,
3640                 .base_baud      = 7812500,
3641                 .uart_offset    = 0x400,
3642                 .reg_shift      = 0,
3643                 .first_offset   = 0,
3644         },
3645         [pbn_exar_XR17V8358] = {
3646                 .flags          = FL_BASE0,
3647                 .num_ports      = 16,
3648                 .base_baud      = 7812500,
3649                 .uart_offset    = 0x400,
3650                 .reg_shift      = 0,
3651                 .first_offset   = 0,
3652         },
3653         [pbn_exar_ibm_saturn] = {
3654                 .flags          = FL_BASE0,
3655                 .num_ports      = 1,
3656                 .base_baud      = 921600,
3657                 .uart_offset    = 0x200,
3658         },
3659 
3660         /*
3661          * PA Semi PWRficient PA6T-1682M on-chip UART
3662          */
3663         [pbn_pasemi_1682M] = {
3664                 .flags          = FL_BASE0,
3665                 .num_ports      = 1,
3666                 .base_baud      = 8333333,
3667         },
3668         /*
3669          * National Instruments 843x
3670          */
3671         [pbn_ni8430_16] = {
3672                 .flags          = FL_BASE0,
3673                 .num_ports      = 16,
3674                 .base_baud      = 3686400,
3675                 .uart_offset    = 0x10,
3676                 .first_offset   = 0x800,
3677         },
3678         [pbn_ni8430_8] = {
3679                 .flags          = FL_BASE0,
3680                 .num_ports      = 8,
3681                 .base_baud      = 3686400,
3682                 .uart_offset    = 0x10,
3683                 .first_offset   = 0x800,
3684         },
3685         [pbn_ni8430_4] = {
3686                 .flags          = FL_BASE0,
3687                 .num_ports      = 4,
3688                 .base_baud      = 3686400,
3689                 .uart_offset    = 0x10,
3690                 .first_offset   = 0x800,
3691         },
3692         [pbn_ni8430_2] = {
3693                 .flags          = FL_BASE0,
3694                 .num_ports      = 2,
3695                 .base_baud      = 3686400,
3696                 .uart_offset    = 0x10,
3697                 .first_offset   = 0x800,
3698         },
3699         /*
3700          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3701          */
3702         [pbn_ADDIDATA_PCIe_1_3906250] = {
3703                 .flags          = FL_BASE0,
3704                 .num_ports      = 1,
3705                 .base_baud      = 3906250,
3706                 .uart_offset    = 0x200,
3707                 .first_offset   = 0x1000,
3708         },
3709         [pbn_ADDIDATA_PCIe_2_3906250] = {
3710                 .flags          = FL_BASE0,
3711                 .num_ports      = 2,
3712                 .base_baud      = 3906250,
3713                 .uart_offset    = 0x200,
3714                 .first_offset   = 0x1000,
3715         },
3716         [pbn_ADDIDATA_PCIe_4_3906250] = {
3717                 .flags          = FL_BASE0,
3718                 .num_ports      = 4,
3719                 .base_baud      = 3906250,
3720                 .uart_offset    = 0x200,
3721                 .first_offset   = 0x1000,
3722         },
3723         [pbn_ADDIDATA_PCIe_8_3906250] = {
3724                 .flags          = FL_BASE0,
3725                 .num_ports      = 8,
3726                 .base_baud      = 3906250,
3727                 .uart_offset    = 0x200,
3728                 .first_offset   = 0x1000,
3729         },
3730         [pbn_ce4100_1_115200] = {
3731                 .flags          = FL_BASE_BARS,
3732                 .num_ports      = 2,
3733                 .base_baud      = 921600,
3734                 .reg_shift      = 2,
3735         },
3736         /*
3737          * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3738          * but is overridden by byt_set_termios.
3739          */
3740         [pbn_byt] = {
3741                 .flags          = FL_BASE0,
3742                 .num_ports      = 1,
3743                 .base_baud      = 2764800,
3744                 .uart_offset    = 0x80,
3745                 .reg_shift      = 2,
3746         },
3747         [pbn_qrk] = {
3748                 .flags          = FL_BASE0,
3749                 .num_ports      = 1,
3750                 .base_baud      = 2764800,
3751                 .reg_shift      = 2,
3752         },
3753         [pbn_omegapci] = {
3754                 .flags          = FL_BASE0,
3755                 .num_ports      = 8,
3756                 .base_baud      = 115200,
3757                 .uart_offset    = 0x200,
3758         },
3759         [pbn_NETMOS9900_2s_115200] = {
3760                 .flags          = FL_BASE0,
3761                 .num_ports      = 2,
3762                 .base_baud      = 115200,
3763         },
3764         [pbn_brcm_trumanage] = {
3765                 .flags          = FL_BASE0,
3766                 .num_ports      = 1,
3767                 .reg_shift      = 2,
3768                 .base_baud      = 115200,
3769         },
3770         [pbn_fintek_4] = {
3771                 .num_ports      = 4,
3772                 .uart_offset    = 8,
3773                 .base_baud      = 115200,
3774                 .first_offset   = 0x40,
3775         },
3776         [pbn_fintek_8] = {
3777                 .num_ports      = 8,
3778                 .uart_offset    = 8,
3779                 .base_baud      = 115200,
3780                 .first_offset   = 0x40,
3781         },
3782         [pbn_fintek_12] = {
3783                 .num_ports      = 12,
3784                 .uart_offset    = 8,
3785                 .base_baud      = 115200,
3786                 .first_offset   = 0x40,
3787         },
3788         [pbn_wch382_2] = {
3789                 .flags          = FL_BASE0,
3790                 .num_ports      = 2,
3791                 .base_baud      = 115200,
3792                 .uart_offset    = 8,
3793                 .first_offset   = 0xC0,
3794         },
3795         [pbn_wch384_4] = {
3796                 .flags          = FL_BASE0,
3797                 .num_ports      = 4,
3798                 .base_baud      = 115200,
3799                 .uart_offset    = 8,
3800                 .first_offset   = 0xC0,
3801         },
3802         /*
3803          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3804          */
3805         [pbn_pericom_PI7C9X7951] = {
3806                 .flags          = FL_BASE0,
3807                 .num_ports      = 1,
3808                 .base_baud      = 921600,
3809                 .uart_offset    = 0x8,
3810         },
3811         [pbn_pericom_PI7C9X7952] = {
3812                 .flags          = FL_BASE0,
3813                 .num_ports      = 2,
3814                 .base_baud      = 921600,
3815                 .uart_offset    = 0x8,
3816         },
3817         [pbn_pericom_PI7C9X7954] = {
3818                 .flags          = FL_BASE0,
3819                 .num_ports      = 4,
3820                 .base_baud      = 921600,
3821                 .uart_offset    = 0x8,
3822         },
3823         [pbn_pericom_PI7C9X7958] = {
3824                 .flags          = FL_BASE0,
3825                 .num_ports      = 8,
3826                 .base_baud      = 921600,
3827                 .uart_offset    = 0x8,
3828         },
3829 };
3830 
3831 static const struct pci_device_id blacklist[] = {
3832         /* softmodems */
3833         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3834         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3835         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3836 
3837         /* multi-io cards handled by parport_serial */
3838         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3839         { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3840         { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3841         { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3842 
3843         /* Intel platforms with MID UART */
3844         { PCI_VDEVICE(INTEL, 0x081b), },
3845         { PCI_VDEVICE(INTEL, 0x081c), },
3846         { PCI_VDEVICE(INTEL, 0x081d), },
3847         { PCI_VDEVICE(INTEL, 0x1191), },
3848         { PCI_VDEVICE(INTEL, 0x19d8), },
3849 };
3850 
3851 /*
3852  * Given a complete unknown PCI device, try to use some heuristics to
3853  * guess what the configuration might be, based on the pitiful PCI
3854  * serial specs.  Returns 0 on success, 1 on failure.
3855  */
3856 static int
3857 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3858 {
3859         const struct pci_device_id *bldev;
3860         int num_iomem, num_port, first_port = -1, i;
3861 
3862         /*
3863          * If it is not a communications device or the programming
3864          * interface is greater than 6, give up.
3865          *
3866          * (Should we try to make guesses for multiport serial devices
3867          * later?)
3868          */
3869         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3870              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3871             (dev->class & 0xff) > 6)
3872                 return -ENODEV;
3873 
3874         /*
3875          * Do not access blacklisted devices that are known not to
3876          * feature serial ports or are handled by other modules.
3877          */
3878         for (bldev = blacklist;
3879              bldev < blacklist + ARRAY_SIZE(blacklist);
3880              bldev++) {
3881                 if (dev->vendor == bldev->vendor &&
3882                     dev->device == bldev->device)
3883                         return -ENODEV;
3884         }
3885 
3886         num_iomem = num_port = 0;
3887         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3888                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3889                         num_port++;
3890                         if (first_port == -1)
3891                                 first_port = i;
3892                 }
3893                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3894                         num_iomem++;
3895         }
3896 
3897         /*
3898          * If there is 1 or 0 iomem regions, and exactly one port,
3899          * use it.  We guess the number of ports based on the IO
3900          * region size.
3901          */
3902         if (num_iomem <= 1 && num_port == 1) {
3903                 board->flags = first_port;
3904                 board->num_ports = pci_resource_len(dev, first_port) / 8;
3905                 return 0;
3906         }
3907 
3908         /*
3909          * Now guess if we've got a board which indexes by BARs.
3910          * Each IO BAR should be 8 bytes, and they should follow
3911          * consecutively.
3912          */
3913         first_port = -1;
3914         num_port = 0;
3915         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3916                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3917                     pci_resource_len(dev, i) == 8 &&
3918                     (first_port == -1 || (first_port + num_port) == i)) {
3919                         num_port++;
3920                         if (first_port == -1)
3921                                 first_port = i;
3922                 }
3923         }
3924 
3925         if (num_port > 1) {
3926                 board->flags = first_port | FL_BASE_BARS;
3927                 board->num_ports = num_port;
3928                 return 0;
3929         }
3930 
3931         return -ENODEV;
3932 }
3933 
3934 static inline int
3935 serial_pci_matches(const struct pciserial_board *board,
3936                    const struct pciserial_board *guessed)
3937 {
3938         return
3939             board->num_ports == guessed->num_ports &&
3940             board->base_baud == guessed->base_baud &&
3941             board->uart_offset == guessed->uart_offset &&
3942             board->reg_shift == guessed->reg_shift &&
3943             board->first_offset == guessed->first_offset;
3944 }
3945 
3946 struct serial_private *
3947 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3948 {
3949         struct uart_8250_port uart;
3950         struct serial_private *priv;
3951         struct pci_serial_quirk *quirk;
3952         int rc, nr_ports, i;
3953 
3954         nr_ports = board->num_ports;
3955 
3956         /*
3957          * Find an init and setup quirks.
3958          */
3959         quirk = find_quirk(dev);
3960 
3961         /*
3962          * Run the new-style initialization function.
3963          * The initialization function returns:
3964          *  <0  - error
3965          *   0  - use board->num_ports
3966          *  >0  - number of ports
3967          */
3968         if (quirk->init) {
3969                 rc = quirk->init(dev);
3970                 if (rc < 0) {
3971                         priv = ERR_PTR(rc);
3972                         goto err_out;
3973                 }
3974                 if (rc)
3975                         nr_ports = rc;
3976         }
3977 
3978         priv = kzalloc(sizeof(struct serial_private) +
3979                        sizeof(unsigned int) * nr_ports,
3980                        GFP_KERNEL);
3981         if (!priv) {
3982                 priv = ERR_PTR(-ENOMEM);
3983                 goto err_deinit;
3984         }
3985 
3986         priv->dev = dev;
3987         priv->quirk = quirk;
3988 
3989         memset(&uart, 0, sizeof(uart));
3990         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3991         uart.port.uartclk = board->base_baud * 16;
3992         uart.port.irq = get_pci_irq(dev, board);
3993         uart.port.dev = &dev->dev;
3994 
3995         for (i = 0; i < nr_ports; i++) {
3996                 if (quirk->setup(priv, board, &uart, i))
3997                         break;
3998 
3999                 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4000                         uart.port.iobase, uart.port.irq, uart.port.iotype);
4001 
4002                 priv->line[i] = serial8250_register_8250_port(&uart);
4003                 if (priv->line[i] < 0) {
4004                         dev_err(&dev->dev,
4005                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4006                                 uart.port.iobase, uart.port.irq,
4007                                 uart.port.iotype, priv->line[i]);
4008                         break;
4009                 }
4010         }
4011         priv->nr = i;
4012         return priv;
4013 
4014 err_deinit:
4015         if (quirk->exit)
4016                 quirk->exit(dev);
4017 err_out:
4018         return priv;
4019 }
4020 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4021 
4022 void pciserial_remove_ports(struct serial_private *priv)
4023 {
4024         struct pci_serial_quirk *quirk;
4025         int i;
4026 
4027         for (i = 0; i < priv->nr; i++)
4028                 serial8250_unregister_port(priv->line[i]);
4029 
4030         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4031                 if (priv->remapped_bar[i])
4032                         iounmap(priv->remapped_bar[i]);
4033                 priv->remapped_bar[i] = NULL;
4034         }
4035 
4036         /*
4037          * Find the exit quirks.
4038          */
4039         quirk = find_quirk(priv->dev);
4040         if (quirk->exit)
4041                 quirk->exit(priv->dev);
4042 
4043         kfree(priv);
4044 }
4045 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4046 
4047 void pciserial_suspend_ports(struct serial_private *priv)
4048 {
4049         int i;
4050 
4051         for (i = 0; i < priv->nr; i++)
4052                 if (priv->line[i] >= 0)
4053                         serial8250_suspend_port(priv->line[i]);
4054 
4055         /*
4056          * Ensure that every init quirk is properly torn down
4057          */
4058         if (priv->quirk->exit)
4059                 priv->quirk->exit(priv->dev);
4060 }
4061 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4062 
4063 void pciserial_resume_ports(struct serial_private *priv)
4064 {
4065         int i;
4066 
4067         /*
4068          * Ensure that the board is correctly configured.
4069          */
4070         if (priv->quirk->init)
4071                 priv->quirk->init(priv->dev);
4072 
4073         for (i = 0; i < priv->nr; i++)
4074                 if (priv->line[i] >= 0)
4075                         serial8250_resume_port(priv->line[i]);
4076 }
4077 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4078 
4079 /*
4080  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
4081  * to the arrangement of serial ports on a PCI card.
4082  */
4083 static int
4084 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4085 {
4086         struct pci_serial_quirk *quirk;
4087         struct serial_private *priv;
4088         const struct pciserial_board *board;
4089         struct pciserial_board tmp;
4090         int rc;
4091 
4092         quirk = find_quirk(dev);
4093         if (quirk->probe) {
4094                 rc = quirk->probe(dev);
4095                 if (rc)
4096                         return rc;
4097         }
4098 
4099         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4100                 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4101                         ent->driver_data);
4102                 return -EINVAL;
4103         }
4104 
4105         board = &pci_boards[ent->driver_data];
4106 
4107         rc = pci_enable_device(dev);
4108         pci_save_state(dev);
4109         if (rc)
4110                 return rc;
4111 
4112         if (ent->driver_data == pbn_default) {
4113                 /*
4114                  * Use a copy of the pci_board entry for this;
4115                  * avoid changing entries in the table.
4116                  */
4117                 memcpy(&tmp, board, sizeof(struct pciserial_board));
4118                 board = &tmp;
4119 
4120                 /*
4121                  * We matched one of our class entries.  Try to
4122                  * determine the parameters of this board.
4123                  */
4124                 rc = serial_pci_guess_board(dev, &tmp);
4125                 if (rc)
4126                         goto disable;
4127         } else {
4128                 /*
4129                  * We matched an explicit entry.  If we are able to
4130                  * detect this boards settings with our heuristic,
4131                  * then we no longer need this entry.
4132                  */
4133                 memcpy(&tmp, &pci_boards[pbn_default],
4134                        sizeof(struct pciserial_board));
4135                 rc = serial_pci_guess_board(dev, &tmp);
4136                 if (rc == 0 && serial_pci_matches(board, &tmp))
4137                         moan_device("Redundant entry in serial pci_table.",
4138                                     dev);
4139         }
4140 
4141         priv = pciserial_init_ports(dev, board);
4142         if (!IS_ERR(priv)) {
4143                 pci_set_drvdata(dev, priv);
4144                 return 0;
4145         }
4146 
4147         rc = PTR_ERR(priv);
4148 
4149  disable:
4150         pci_disable_device(dev);
4151         return rc;
4152 }
4153 
4154 static void pciserial_remove_one(struct pci_dev *dev)
4155 {
4156         struct serial_private *priv = pci_get_drvdata(dev);
4157 
4158         pciserial_remove_ports(priv);
4159 
4160         pci_disable_device(dev);
4161 }
4162 
4163 #ifdef CONFIG_PM_SLEEP
4164 static int pciserial_suspend_one(struct device *dev)
4165 {
4166         struct pci_dev *pdev = to_pci_dev(dev);
4167         struct serial_private *priv = pci_get_drvdata(pdev);
4168 
4169         if (priv)
4170                 pciserial_suspend_ports(priv);
4171 
4172         return 0;
4173 }
4174 
4175 static int pciserial_resume_one(struct device *dev)
4176 {
4177         struct pci_dev *pdev = to_pci_dev(dev);
4178         struct serial_private *priv = pci_get_drvdata(pdev);
4179         int err;
4180 
4181         if (priv) {
4182                 /*
4183                  * The device may have been disabled.  Re-enable it.
4184                  */
4185                 err = pci_enable_device(pdev);
4186                 /* FIXME: We cannot simply error out here */
4187                 if (err)
4188                         dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4189                 pciserial_resume_ports(priv);
4190         }
4191         return 0;
4192 }
4193 #endif
4194 
4195 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4196                          pciserial_resume_one);
4197 
4198 static struct pci_device_id serial_pci_tbl[] = {
4199         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4200         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4201                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4202                 pbn_b2_8_921600 },
4203         /* Advantech also use 0x3618 and 0xf618 */
4204         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4205                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4206                 pbn_b0_4_921600 },
4207         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4208                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4209                 pbn_b0_4_921600 },
4210         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4211                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4212                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4213                 pbn_b1_8_1382400 },
4214         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4215                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4216                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4217                 pbn_b1_4_1382400 },
4218         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4219                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4220                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4221                 pbn_b1_2_1382400 },
4222         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4223                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4224                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4225                 pbn_b1_8_1382400 },
4226         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4227                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4228                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4229                 pbn_b1_4_1382400 },
4230         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4231                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4232                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4233                 pbn_b1_2_1382400 },
4234         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4235                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4236                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4237                 pbn_b1_8_921600 },
4238         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4239                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4240                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4241                 pbn_b1_8_921600 },
4242         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4243                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4244                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4245                 pbn_b1_4_921600 },
4246         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4247                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4248                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4249                 pbn_b1_4_921600 },
4250         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4251                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4252                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4253                 pbn_b1_2_921600 },
4254         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4255                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4256                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4257                 pbn_b1_8_921600 },
4258         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4259                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4260                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4261                 pbn_b1_8_921600 },
4262         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4263                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4264                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4265                 pbn_b1_4_921600 },
4266         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4267                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4268                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4269                 pbn_b1_2_1250000 },
4270         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4271                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4272                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4273                 pbn_b0_2_1843200 },
4274         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4275                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4276                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4277                 pbn_b0_4_1843200 },
4278         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4279                 PCI_VENDOR_ID_AFAVLAB,
4280                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4281                 pbn_b0_4_1152000 },
4282         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4283                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4284                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4285                 pbn_b0_2_1843200_200 },
4286         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4287                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4288                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4289                 pbn_b0_4_1843200_200 },
4290         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4291                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4292                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4293                 pbn_b0_8_1843200_200 },
4294         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4295                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4296                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4297                 pbn_b0_2_1843200_200 },
4298         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4299                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4300                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4301                 pbn_b0_4_1843200_200 },
4302         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4303                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4304                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4305                 pbn_b0_8_1843200_200 },
4306         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4307                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4308                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4309                 pbn_b0_2_1843200_200 },
4310         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4311                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4312                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4313                 pbn_b0_4_1843200_200 },
4314         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4315                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4316                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4317                 pbn_b0_8_1843200_200 },
4318         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4319                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4320                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4321                 pbn_b0_2_1843200_200 },
4322         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4323                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4324                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4325                 pbn_b0_4_1843200_200 },
4326         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4327                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4328                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4329                 pbn_b0_8_1843200_200 },
4330         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4331                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4332                 0, 0, pbn_exar_ibm_saturn },
4333 
4334         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4335                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336                 pbn_b2_bt_1_115200 },
4337         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4338                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339                 pbn_b2_bt_2_115200 },
4340         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4341                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342                 pbn_b2_bt_4_115200 },
4343         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4344                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345                 pbn_b2_bt_2_115200 },
4346         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4347                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348                 pbn_b2_bt_4_115200 },
4349         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4350                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351                 pbn_b2_8_115200 },
4352         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4353                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354                 pbn_b2_8_460800 },
4355         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4356                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357                 pbn_b2_8_115200 },
4358 
4359         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4360                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4361                 pbn_b2_bt_2_115200 },
4362         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4363                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4364                 pbn_b2_bt_2_921600 },
4365         /*
4366          * VScom SPCOM800, from sl@s.pl
4367          */
4368         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4369                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4370                 pbn_b2_8_921600 },
4371         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4372                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4373                 pbn_b2_4_921600 },
4374         /* Unknown card - subdevice 0x1584 */
4375         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4376                 PCI_VENDOR_ID_PLX,
4377                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4378                 pbn_b2_4_115200 },
4379         /* Unknown card - subdevice 0x1588 */
4380         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4381                 PCI_VENDOR_ID_PLX,
4382                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4383                 pbn_b2_8_115200 },
4384         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4385                 PCI_SUBVENDOR_ID_KEYSPAN,
4386                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4387                 pbn_panacom },
4388         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4389                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4390                 pbn_panacom4 },
4391         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4392                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4393                 pbn_panacom2 },
4394         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4395                 PCI_VENDOR_ID_ESDGMBH,
4396                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4397                 pbn_b2_4_115200 },
4398         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4399                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4400                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4401                 pbn_b2_4_460800 },
4402         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4403                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4404                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4405                 pbn_b2_8_460800 },
4406         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4407                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4408                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4409                 pbn_b2_16_460800 },
4410         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4411                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4412                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4413                 pbn_b2_16_460800 },
4414         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4415                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4416                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4417                 pbn_b2_4_460800 },
4418         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4419                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4420                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4421                 pbn_b2_8_460800 },
4422         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4423                 PCI_SUBVENDOR_ID_EXSYS,
4424                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4425                 pbn_b2_4_115200 },
4426         /*
4427          * Megawolf Romulus PCI Serial Card, from Mike Hudson
4428          * (Exoray@isys.ca)
4429          */
4430         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4431                 0x10b5, 0x106a, 0, 0,
4432                 pbn_plx_romulus },
4433         /*
4434         * EndRun Technologies. PCI express device range.
4435         *    EndRun PTP/1588 has 2 Native UARTs.
4436         */
4437         {       PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4438                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439                 pbn_endrun_2_4000000 },
4440         /*
4441          * Quatech cards. These actually have configurable clocks but for
4442          * now we just use the default.
4443          *
4444          * 100 series are RS232, 200 series RS422,
4445          */
4446         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4447                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448                 pbn_b1_4_115200 },
4449         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4450                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451                 pbn_b1_2_115200 },
4452         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4453                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454                 pbn_b2_2_115200 },
4455         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4456                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457                 pbn_b1_2_115200 },
4458         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4459                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460                 pbn_b2_2_115200 },
4461         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4462                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4463                 pbn_b1_4_115200 },
4464         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4465                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4466                 pbn_b1_8_115200 },
4467         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4468                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4469                 pbn_b1_8_115200 },
4470         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4471                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4472                 pbn_b1_4_115200 },
4473         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4474                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4475                 pbn_b1_2_115200 },
4476         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4477                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4478                 pbn_b1_4_115200 },
4479         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4480                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4481                 pbn_b1_2_115200 },
4482         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4483                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4484                 pbn_b2_4_115200 },
4485         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4486                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487                 pbn_b2_2_115200 },
4488         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4489                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490                 pbn_b2_1_115200 },
4491         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4492                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4493                 pbn_b2_4_115200 },
4494         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4495                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496                 pbn_b2_2_115200 },
4497         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4498                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4499                 pbn_b2_1_115200 },
4500         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4501                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4502                 pbn_b0_8_115200 },
4503 
4504         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4505                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4506                 0, 0,
4507                 pbn_b0_4_921600 },
4508         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4509                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4510                 0, 0,
4511                 pbn_b0_4_1152000 },
4512         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
4513                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514                 pbn_b0_bt_2_921600 },
4515 
4516                 /*
4517                  * The below card is a little controversial since it is the
4518                  * subject of a PCI vendor/device ID clash.  (See
4519                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4520                  * For now just used the hex ID 0x950a.
4521                  */
4522         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4523                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4524                 0, 0, pbn_b0_2_115200 },
4525         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4526                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4527                 0, 0, pbn_b0_2_115200 },
4528         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4529                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4530                 pbn_b0_2_1130000 },
4531         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4532                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4533                 pbn_b0_1_921600 },
4534         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4535                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4536                 pbn_b0_4_115200 },
4537         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4538                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4539                 pbn_b0_bt_2_921600 },
4540         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4541                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4542                 pbn_b2_8_1152000 },
4543 
4544         /*
4545          * Oxford Semiconductor Inc. Tornado PCI express device range.
4546          */
4547         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4548                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4549                 pbn_b0_1_4000000 },
4550         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4551                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4552                 pbn_b0_1_4000000 },
4553         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4554                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4555                 pbn_oxsemi_1_4000000 },
4556         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4557                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4558                 pbn_oxsemi_1_4000000 },
4559         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4560                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4561                 pbn_b0_1_4000000 },
4562         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4563                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4564                 pbn_b0_1_4000000 },
4565         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4566                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4567                 pbn_oxsemi_1_4000000 },
4568         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4569                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4570                 pbn_oxsemi_1_4000000 },
4571         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4572                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4573                 pbn_b0_1_4000000 },
4574         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4575                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4576                 pbn_b0_1_4000000 },
4577         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4578                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4579                 pbn_b0_1_4000000 },
4580         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4581                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4582                 pbn_b0_1_4000000 },
4583         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4584                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4585                 pbn_oxsemi_2_4000000 },
4586         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4587                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4588                 pbn_oxsemi_2_4000000 },
4589         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4590                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4591                 pbn_oxsemi_4_4000000 },
4592         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4593                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4594                 pbn_oxsemi_4_4000000 },
4595         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4596                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4597                 pbn_oxsemi_8_4000000 },
4598         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4599                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4600                 pbn_oxsemi_8_4000000 },
4601         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4602                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4603                 pbn_oxsemi_1_4000000 },
4604         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4605                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4606                 pbn_oxsemi_1_4000000 },
4607         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4608                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4609                 pbn_oxsemi_1_4000000 },
4610         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4611                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4612                 pbn_oxsemi_1_4000000 },
4613         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4614                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4615                 pbn_oxsemi_1_4000000 },
4616         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4617                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4618                 pbn_oxsemi_1_4000000 },
4619         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4620                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621                 pbn_oxsemi_1_4000000 },
4622         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4623                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4624                 pbn_oxsemi_1_4000000 },
4625         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4626                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627                 pbn_oxsemi_1_4000000 },
4628         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4629                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630                 pbn_oxsemi_1_4000000 },
4631         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4632                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633                 pbn_oxsemi_1_4000000 },
4634         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4635                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636                 pbn_oxsemi_1_4000000 },
4637         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4638                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639                 pbn_oxsemi_1_4000000 },
4640         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4641                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642                 pbn_oxsemi_1_4000000 },
4643         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4644                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4645                 pbn_oxsemi_1_4000000 },
4646         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4647                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648                 pbn_oxsemi_1_4000000 },
4649         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4650                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651                 pbn_oxsemi_1_4000000 },
4652         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4653                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4654                 pbn_oxsemi_1_4000000 },
4655         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4656                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4657                 pbn_oxsemi_1_4000000 },
4658         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4659                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4660                 pbn_oxsemi_1_4000000 },
4661         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4662                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4663                 pbn_oxsemi_1_4000000 },
4664         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4665                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666                 pbn_oxsemi_1_4000000 },
4667         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4668                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669                 pbn_oxsemi_1_4000000 },
4670         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4671                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672                 pbn_oxsemi_1_4000000 },
4673         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4674                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675                 pbn_oxsemi_1_4000000 },
4676         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4677                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678                 pbn_oxsemi_1_4000000 },
4679         /*
4680          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4681          */
4682         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4683                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4684                 pbn_oxsemi_1_4000000 },
4685         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4686                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4687                 pbn_oxsemi_2_4000000 },
4688         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4689                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4690                 pbn_oxsemi_4_4000000 },
4691         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4692                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4693                 pbn_oxsemi_8_4000000 },
4694 
4695         /*
4696          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4697          */
4698         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4699                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4700                 pbn_oxsemi_2_4000000 },
4701 
4702         /*
4703          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4704          * from skokodyn@yahoo.com
4705          */
4706         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4707                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4708                 pbn_sbsxrsio },
4709         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4710                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4711                 pbn_sbsxrsio },
4712         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4713                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4714                 pbn_sbsxrsio },
4715         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4716                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4717                 pbn_sbsxrsio },
4718 
4719         /*
4720          * Digitan DS560-558, from jimd@esoft.com
4721          */
4722         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4723                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4724                 pbn_b1_1_115200 },
4725 
4726         /*
4727          * Titan Electronic cards
4728          *  The 400L and 800L have a custom setup quirk.
4729          */
4730         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4731                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4732                 pbn_b0_1_921600 },
4733         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4734                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735                 pbn_b0_2_921600 },
4736         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4737                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4738                 pbn_b0_4_921600 },
4739         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4740                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4741                 pbn_b0_4_921600 },
4742         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4743                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4744                 pbn_b1_1_921600 },
4745         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4746                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4747                 pbn_b1_bt_2_921600 },
4748         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4749                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4750                 pbn_b0_bt_4_921600 },
4751         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4752                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4753                 pbn_b0_bt_8_921600 },
4754         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4755                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4756                 pbn_b4_bt_2_921600 },
4757         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4758                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4759                 pbn_b4_bt_4_921600 },
4760         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4761                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4762                 pbn_b4_bt_8_921600 },
4763         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4764                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4765                 pbn_b0_4_921600 },
4766         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4767                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4768                 pbn_b0_4_921600 },
4769         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4770                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4771                 pbn_b0_4_921600 },
4772         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4773                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4774                 pbn_oxsemi_1_4000000 },
4775         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4776                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4777                 pbn_oxsemi_2_4000000 },
4778         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4779                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780                 pbn_oxsemi_4_4000000 },
4781         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4782                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783                 pbn_oxsemi_8_4000000 },
4784         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4785                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4786                 pbn_oxsemi_2_4000000 },
4787         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4788                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4789                 pbn_oxsemi_2_4000000 },
4790         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4791                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4792                 pbn_b0_bt_2_921600 },
4793         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4794                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4795                 pbn_b0_4_921600 },
4796         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4797                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4798                 pbn_b0_4_921600 },
4799         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4800                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4801                 pbn_b0_4_921600 },
4802         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4803                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4804                 pbn_b0_4_921600 },
4805 
4806         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4807                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4808                 pbn_b2_1_460800 },
4809         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4810                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811                 pbn_b2_1_460800 },
4812         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4813                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814                 pbn_b2_1_460800 },
4815         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4816                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4817                 pbn_b2_bt_2_921600 },
4818         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4819                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4820                 pbn_b2_bt_2_921600 },
4821         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4822                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4823                 pbn_b2_bt_2_921600 },
4824         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4825                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4826                 pbn_b2_bt_4_921600 },
4827         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4828                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4829                 pbn_b2_bt_4_921600 },
4830         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4831                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4832                 pbn_b2_bt_4_921600 },
4833         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4834                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4835                 pbn_b0_1_921600 },
4836         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4837                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4838                 pbn_b0_1_921600 },
4839         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4840                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4841                 pbn_b0_1_921600 },
4842         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4843                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4844                 pbn_b0_bt_2_921600 },
4845         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4846                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4847                 pbn_b0_bt_2_921600 },
4848         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4849                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4850                 pbn_b0_bt_2_921600 },
4851         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4852                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4853                 pbn_b0_bt_4_921600 },
4854         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4855                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4856                 pbn_b0_bt_4_921600 },
4857         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4858                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4859                 pbn_b0_bt_4_921600 },
4860         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4861                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4862                 pbn_b0_bt_8_921600 },
4863         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4864                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4865                 pbn_b0_bt_8_921600 },
4866         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4867                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4868                 pbn_b0_bt_8_921600 },
4869 
4870         /*
4871          * Computone devices submitted by Doug McNash dmcnash@computone.com
4872          */
4873         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4874                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4875                 0, 0, pbn_computone_4 },
4876         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4877                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4878                 0, 0, pbn_computone_8 },
4879         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4880                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4881                 0, 0, pbn_computone_6 },
4882 
4883         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4884                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4885                 pbn_oxsemi },
4886         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4887                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4888                 pbn_b0_bt_1_921600 },
4889 
4890         /*
4891          * SUNIX (TIMEDIA)
4892          */
4893         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4894                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4895                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4896                 pbn_b0_bt_1_921600 },
4897 
4898         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4899                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4900                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4901                 pbn_b0_bt_1_921600 },
4902 
4903         /*
4904          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4905          */
4906         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4907                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908                 pbn_b0_bt_8_115200 },
4909         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4910                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4911                 pbn_b0_bt_8_115200 },
4912 
4913         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4914                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4915                 pbn_b0_bt_2_115200 },
4916         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4917                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4918                 pbn_b0_bt_2_115200 },
4919         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4920                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4921                 pbn_b0_bt_2_115200 },
4922         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4923                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4924                 pbn_b0_bt_2_115200 },
4925         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4926                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4927                 pbn_b0_bt_2_115200 },
4928         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4929                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4930                 pbn_b0_bt_4_460800 },
4931         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4932                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4933                 pbn_b0_bt_4_460800 },
4934         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4935                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4936                 pbn_b0_bt_2_460800 },
4937         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4938                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4939                 pbn_b0_bt_2_460800 },
4940         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4941                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4942                 pbn_b0_bt_2_460800 },
4943         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4944                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4945                 pbn_b0_bt_1_115200 },
4946         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4947                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4948                 pbn_b0_bt_1_460800 },
4949 
4950         /*
4951          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4952          * Cards are identified by their subsystem vendor IDs, which
4953          * (in hex) match the model number.
4954          *
4955          * Note that JC140x are RS422/485 cards which require ox950
4956          * ACR = 0x10, and as such are not currently fully supported.
4957          */
4958         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4959                 0x1204, 0x0004, 0, 0,
4960                 pbn_b0_4_921600 },
4961         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4962                 0x1208, 0x0004, 0, 0,
4963                 pbn_b0_4_921600 },
4964 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4965                 0x1402, 0x0002, 0, 0,
4966                 pbn_b0_2_921600 }, */
4967 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4968                 0x1404, 0x0004, 0, 0,
4969                 pbn_b0_4_921600 }, */
4970         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4971                 0x1208, 0x0004, 0, 0,
4972                 pbn_b0_4_921600 },
4973 
4974         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4975                 0x1204, 0x0004, 0, 0,
4976                 pbn_b0_4_921600 },
4977         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4978                 0x1208, 0x0004, 0, 0,
4979                 pbn_b0_4_921600 },
4980         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4981                 0x1208, 0x0004, 0, 0,
4982                 pbn_b0_4_921600 },
4983         /*
4984          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4985          */
4986         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4987                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4988                 pbn_b1_1_1382400 },
4989 
4990         /*
4991          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4992          */
4993         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4994                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4995                 pbn_b1_1_1382400 },
4996 
4997         /*
4998          * RAStel 2 port modem, gerg@moreton.com.au
4999          */
5000         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5001                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5002                 pbn_b2_bt_2_115200 },
5003 
5004         /*
5005          * EKF addition for i960 Boards form EKF with serial port
5006          */
5007         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5008                 0xE4BF, PCI_ANY_ID, 0, 0,
5009                 pbn_intel_i960 },
5010 
5011         /*
5012          * Xircom Cardbus/Ethernet combos
5013          */
5014         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5015                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5016                 pbn_b0_1_115200 },
5017         /*
5018          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5019          */
5020         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5021                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5022                 pbn_b0_1_115200 },
5023 
5024         /*
5025          * Untested PCI modems, sent in from various folks...
5026          */
5027 
5028         /*
5029          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5030          */
5031         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
5032                 0x1048, 0x1500, 0, 0,
5033                 pbn_b1_1_115200 },
5034 
5035         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5036                 0xFF00, 0, 0, 0,
5037                 pbn_sgi_ioc3 },
5038 
5039         /*
5040          * HP Diva card
5041          */
5042         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5043                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5044                 pbn_b1_1_115200 },
5045         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5046                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5047                 pbn_b0_5_115200 },
5048         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5049                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5050                 pbn_b2_1_115200 },
5051 
5052         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5053                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5054                 pbn_b3_2_115200 },
5055         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5056                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5057                 pbn_b3_4_115200 },
5058         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5059                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5060                 pbn_b3_8_115200 },
5061 
5062         /*
5063          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5064          */
5065         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5066                 PCI_ANY_ID, PCI_ANY_ID,
5067                 0,
5068                 0, pbn_exar_XR17C152 },
5069         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5070                 PCI_ANY_ID, PCI_ANY_ID,
5071                 0,
5072                 0, pbn_exar_XR17C154 },
5073         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5074                 PCI_ANY_ID, PCI_ANY_ID,
5075                 0,
5076                 0, pbn_exar_XR17C158 },
5077         /*
5078          * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5079          */
5080         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5081                 PCI_ANY_ID, PCI_ANY_ID,
5082                 0,
5083                 0, pbn_exar_XR17V352 },
5084         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5085                 PCI_ANY_ID, PCI_ANY_ID,
5086                 0,
5087                 0, pbn_exar_XR17V354 },
5088         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5089                 PCI_ANY_ID, PCI_ANY_ID,
5090                 0,
5091                 0, pbn_exar_XR17V358 },
5092         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5093                 PCI_ANY_ID, PCI_ANY_ID,
5094                 0,
5095                 0, pbn_exar_XR17V4358 },
5096         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5097                 PCI_ANY_ID, PCI_ANY_ID,
5098                 0,
5099                 0, pbn_exar_XR17V8358 },
5100         /*
5101          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5102          */
5103         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5104                 PCI_ANY_ID, PCI_ANY_ID,
5105                 0,
5106                 0, pbn_pericom_PI7C9X7951 },
5107         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5108                 PCI_ANY_ID, PCI_ANY_ID,
5109                 0,
5110                 0, pbn_pericom_PI7C9X7952 },
5111         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5112                 PCI_ANY_ID, PCI_ANY_ID,
5113                 0,
5114                 0, pbn_pericom_PI7C9X7954 },
5115         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5116                 PCI_ANY_ID, PCI_ANY_ID,
5117                 0,
5118                 0, pbn_pericom_PI7C9X7958 },
5119         /*
5120          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5121          */
5122         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5123                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5124                 pbn_b0_1_115200 },
5125         /*
5126          * ITE
5127          */
5128         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5129                 PCI_ANY_ID, PCI_ANY_ID,
5130                 0, 0,
5131                 pbn_b1_bt_1_115200 },
5132 
5133         /*
5134          * IntaShield IS-200
5135          */
5136         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5137                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
5138                 pbn_b2_2_115200 },
5139         /*
5140          * IntaShield IS-400
5141          */
5142         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5143                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
5144                 pbn_b2_4_115200 },
5145         /*
5146          * Perle PCI-RAS cards
5147          */
5148         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5149                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5150                 0, 0, pbn_b2_4_921600 },
5151         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5152                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5153                 0, 0, pbn_b2_8_921600 },
5154 
5155         /*
5156          * Mainpine series cards: Fairly standard layout but fools
5157          * parts of the autodetect in some cases and uses otherwise
5158          * unmatched communications subclasses in the PCI Express case
5159          */
5160 
5161         {       /* RockForceDUO */
5162                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5163                 PCI_VENDOR_ID_MAINPINE, 0x0200,
5164                 0, 0, pbn_b0_2_115200 },
5165         {       /* RockForceQUATRO */
5166                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5167                 PCI_VENDOR_ID_MAINPINE, 0x0300,
5168                 0, 0, pbn_b0_4_115200 },
5169         {       /* RockForceDUO+ */
5170                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5171                 PCI_VENDOR_ID_MAINPINE, 0x0400,
5172                 0, 0, pbn_b0_2_115200 },
5173         {       /* RockForceQUATRO+ */
5174                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5175                 PCI_VENDOR_ID_MAINPINE, 0x0500,
5176                 0, 0, pbn_b0_4_115200 },
5177         {       /* RockForce+ */
5178                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5179                 PCI_VENDOR_ID_MAINPINE, 0x0600,
5180                 0, 0, pbn_b0_2_115200 },
5181         {       /* RockForce+ */
5182                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5183                 PCI_VENDOR_ID_MAINPINE, 0x0700,
5184                 0, 0, pbn_b0_4_115200 },
5185         {       /* RockForceOCTO+ */
5186                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5187                 PCI_VENDOR_ID_MAINPINE, 0x0800,
5188                 0, 0, pbn_b0_8_115200 },
5189         {       /* RockForceDUO+ */
5190                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5191                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5192                 0, 0, pbn_b0_2_115200 },
5193         {       /* RockForceQUARTRO+ */
5194                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5195                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5196                 0, 0, pbn_b0_4_115200 },
5197         {       /* RockForceOCTO+ */
5198                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5199                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5200                 0, 0, pbn_b0_8_115200 },
5201         {       /* RockForceD1 */
5202                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5203                 PCI_VENDOR_ID_MAINPINE, 0x2000,
5204                 0, 0, pbn_b0_1_115200 },
5205         {       /* RockForceF1 */
5206                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5207                 PCI_VENDOR_ID_MAINPINE, 0x2100,
5208                 0, 0, pbn_b0_1_115200 },
5209         {       /* RockForceD2 */
5210                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5211                 PCI_VENDOR_ID_MAINPINE, 0x2200,
5212                 0, 0, pbn_b0_2_115200 },
5213         {       /* RockForceF2 */
5214                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5215                 PCI_VENDOR_ID_MAINPINE, 0x2300,
5216                 0, 0, pbn_b0_2_115200 },
5217         {       /* RockForceD4 */
5218                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5219                 PCI_VENDOR_ID_MAINPINE, 0x2400,
5220                 0, 0, pbn_b0_4_115200 },
5221         {       /* RockForceF4 */
5222                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5223                 PCI_VENDOR_ID_MAINPINE, 0x2500,
5224                 0, 0, pbn_b0_4_115200 },
5225         {       /* RockForceD8 */
5226                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5227                 PCI_VENDOR_ID_MAINPINE, 0x2600,
5228                 0, 0, pbn_b0_8_115200 },
5229         {       /* RockForceF8 */
5230                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5231                 PCI_VENDOR_ID_MAINPINE, 0x2700,
5232                 0, 0, pbn_b0_8_115200 },
5233         {       /* IQ Express D1 */
5234                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5235                 PCI_VENDOR_ID_MAINPINE, 0x3000,
5236                 0, 0, pbn_b0_1_115200 },
5237         {       /* IQ Express F1 */
5238                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5239                 PCI_VENDOR_ID_MAINPINE, 0x3100,
5240                 0, 0, pbn_b0_1_115200 },
5241         {       /* IQ Express D2 */
5242                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5243                 PCI_VENDOR_ID_MAINPINE, 0x3200,
5244                 0, 0, pbn_b0_2_115200 },
5245         {       /* IQ Express F2 */
5246                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5247                 PCI_VENDOR_ID_MAINPINE, 0x3300,
5248                 0, 0, pbn_b0_2_115200 },
5249         {       /* IQ Express D4 */
5250                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5251                 PCI_VENDOR_ID_MAINPINE, 0x3400,
5252                 0, 0, pbn_b0_4_115200 },
5253         {       /* IQ Express F4 */
5254                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5255                 PCI_VENDOR_ID_MAINPINE, 0x3500,
5256                 0, 0, pbn_b0_4_115200 },
5257         {       /* IQ Express D8 */
5258                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5259                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5260                 0, 0, pbn_b0_8_115200 },
5261         {       /* IQ Express F8 */
5262                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5263                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5264                 0, 0, pbn_b0_8_115200 },
5265 
5266 
5267         /*
5268          * PA Semi PA6T-1682M on-chip UART
5269          */
5270         {       PCI_VENDOR_ID_PASEMI, 0xa004,
5271                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5272                 pbn_pasemi_1682M },
5273 
5274         /*
5275          * National Instruments
5276          */
5277         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5278                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5279                 pbn_b1_16_115200 },
5280         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5281                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5282                 pbn_b1_8_115200 },
5283         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5284                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5285                 pbn_b1_bt_4_115200 },
5286         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5287                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5288                 pbn_b1_bt_2_115200 },
5289         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5290                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5291                 pbn_b1_bt_4_115200 },
5292         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5293                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5294                 pbn_b1_bt_2_115200 },
5295         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5296                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5297                 pbn_b1_16_115200 },
5298         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5299                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5300                 pbn_b1_8_115200 },
5301         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5302                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5303                 pbn_b1_bt_4_115200 },
5304         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5305                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5306                 pbn_b1_bt_2_115200 },
5307         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5308                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5309                 pbn_b1_bt_4_115200 },
5310         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5311                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5312                 pbn_b1_bt_2_115200 },
5313         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5314                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5315                 pbn_ni8430_2 },
5316         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5317                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5318                 pbn_ni8430_2 },
5319         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5320                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5321                 pbn_ni8430_4 },
5322         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5323                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5324                 pbn_ni8430_4 },
5325         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5326                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5327                 pbn_ni8430_8 },
5328         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5329                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5330                 pbn_ni8430_8 },
5331         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5332                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5333                 pbn_ni8430_16 },
5334         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5335                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5336                 pbn_ni8430_16 },
5337         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5338                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5339                 pbn_ni8430_2 },
5340         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5341                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5342                 pbn_ni8430_2 },
5343         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5344                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5345                 pbn_ni8430_4 },
5346         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5347                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5348                 pbn_ni8430_4 },
5349 
5350         /*
5351         * ADDI-DATA GmbH communication cards <info@addi-data.com>
5352         */
5353         {       PCI_VENDOR_ID_ADDIDATA,
5354                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5355                 PCI_ANY_ID,
5356                 PCI_ANY_ID,
5357                 0,
5358                 0,
5359                 pbn_b0_4_115200 },
5360 
5361         {       PCI_VENDOR_ID_ADDIDATA,
5362                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5363                 PCI_ANY_ID,
5364                 PCI_ANY_ID,
5365                 0,
5366                 0,
5367                 pbn_b0_2_115200 },
5368 
5369         {       PCI_VENDOR_ID_ADDIDATA,
5370                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5371                 PCI_ANY_ID,
5372                 PCI_ANY_ID,
5373                 0,
5374                 0,
5375                 pbn_b0_1_115200 },
5376 
5377         {       PCI_VENDOR_ID_AMCC,
5378                 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5379                 PCI_ANY_ID,
5380                 PCI_ANY_ID,
5381                 0,
5382                 0,
5383                 pbn_b1_8_115200 },
5384 
5385         {       PCI_VENDOR_ID_ADDIDATA,
5386                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5387                 PCI_ANY_ID,
5388                 PCI_ANY_ID,
5389                 0,
5390                 0,
5391                 pbn_b0_4_115200 },
5392 
5393         {       PCI_VENDOR_ID_ADDIDATA,
5394                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5395                 PCI_ANY_ID,
5396                 PCI_ANY_ID,
5397                 0,
5398                 0,
5399                 pbn_b0_2_115200 },
5400 
5401         {       PCI_VENDOR_ID_ADDIDATA,
5402                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5403                 PCI_ANY_ID,
5404                 PCI_ANY_ID,
5405                 0,
5406                 0,
5407                 pbn_b0_1_115200 },
5408 
5409         {       PCI_VENDOR_ID_ADDIDATA,
5410                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5411                 PCI_ANY_ID,
5412                 PCI_ANY_ID,
5413                 0,
5414                 0,
5415                 pbn_b0_4_115200 },
5416 
5417         {       PCI_VENDOR_ID_ADDIDATA,
5418                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5419                 PCI_ANY_ID,
5420                 PCI_ANY_ID,
5421                 0,
5422                 0,
5423                 pbn_b0_2_115200 },
5424 
5425         {       PCI_VENDOR_ID_ADDIDATA,
5426                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5427                 PCI_ANY_ID,
5428                 PCI_ANY_ID,
5429                 0,
5430                 0,
5431                 pbn_b0_1_115200 },
5432 
5433         {       PCI_VENDOR_ID_ADDIDATA,
5434                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5435                 PCI_ANY_ID,
5436                 PCI_ANY_ID,
5437                 0,
5438                 0,
5439                 pbn_b0_8_115200 },
5440 
5441         {       PCI_VENDOR_ID_ADDIDATA,
5442                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5443                 PCI_ANY_ID,
5444                 PCI_ANY_ID,
5445                 0,
5446                 0,
5447                 pbn_ADDIDATA_PCIe_4_3906250 },
5448 
5449         {       PCI_VENDOR_ID_ADDIDATA,
5450                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5451                 PCI_ANY_ID,
5452                 PCI_ANY_ID,
5453                 0,
5454                 0,
5455                 pbn_ADDIDATA_PCIe_2_3906250 },
5456 
5457         {       PCI_VENDOR_ID_ADDIDATA,
5458                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5459                 PCI_ANY_ID,
5460                 PCI_ANY_ID,
5461                 0,
5462                 0,
5463                 pbn_ADDIDATA_PCIe_1_3906250 },
5464 
5465         {       PCI_VENDOR_ID_ADDIDATA,
5466                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5467                 PCI_ANY_ID,
5468                 PCI_ANY_ID,
5469                 0,
5470                 0,
5471                 pbn_ADDIDATA_PCIe_8_3906250 },
5472 
5473         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5474                 PCI_VENDOR_ID_IBM, 0x0299,
5475                 0, 0, pbn_b0_bt_2_115200 },
5476 
5477         /*
5478          * other NetMos 9835 devices are most likely handled by the
5479          * parport_serial driver, check drivers/parport/parport_serial.c
5480          * before adding them here.
5481          */
5482 
5483         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5484                 0xA000, 0x1000,
5485                 0, 0, pbn_b0_1_115200 },
5486 
5487         /* the 9901 is a rebranded 9912 */
5488         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5489                 0xA000, 0x1000,
5490                 0, 0, pbn_b0_1_115200 },
5491 
5492         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5493                 0xA000, 0x1000,
5494                 0, 0, pbn_b0_1_115200 },
5495 
5496         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5497                 0xA000, 0x1000,
5498                 0, 0, pbn_b0_1_115200 },
5499 
5500         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5501                 0xA000, 0x1000,
5502                 0, 0, pbn_b0_1_115200 },
5503 
5504         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5505                 0xA000, 0x3002,
5506                 0, 0, pbn_NETMOS9900_2s_115200 },
5507 
5508         /*
5509          * Best Connectivity and Rosewill PCI Multi I/O cards
5510          */
5511 
5512         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5513                 0xA000, 0x1000,
5514                 0, 0, pbn_b0_1_115200 },
5515 
5516         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5517                 0xA000, 0x3002,
5518                 0, 0, pbn_b0_bt_2_115200 },
5519 
5520         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5521                 0xA000, 0x3004,
5522                 0, 0, pbn_b0_bt_4_115200 },
5523         /* Intel CE4100 */
5524         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5525                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5526                 pbn_ce4100_1_115200 },
5527         /* Intel BayTrail */
5528         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5529                 PCI_ANY_ID,  PCI_ANY_ID,
5530                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5531                 pbn_byt },
5532         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5533                 PCI_ANY_ID,  PCI_ANY_ID,
5534                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5535                 pbn_byt },
5536         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5537                 PCI_ANY_ID,  PCI_ANY_ID,
5538                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5539                 pbn_byt },
5540         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5541                 PCI_ANY_ID,  PCI_ANY_ID,
5542                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5543                 pbn_byt },
5544 
5545         /* Intel Broadwell */
5546         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1,
5547                 PCI_ANY_ID,  PCI_ANY_ID,
5548                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5549                 pbn_byt },
5550         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2,
5551                 PCI_ANY_ID,  PCI_ANY_ID,
5552                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5553                 pbn_byt },
5554 
5555         /*
5556          * Intel Quark x1000
5557          */
5558         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5559                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5560                 pbn_qrk },
5561         /*
5562          * Cronyx Omega PCI
5563          */
5564         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5565                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5566                 pbn_omegapci },
5567 
5568         /*
5569          * Broadcom TruManage
5570          */
5571         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5572                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5573                 pbn_brcm_trumanage },
5574 
5575         /*
5576          * AgeStar as-prs2-009
5577          */
5578         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5579                 PCI_ANY_ID, PCI_ANY_ID,
5580                 0, 0, pbn_b0_bt_2_115200 },
5581 
5582         /*
5583          * WCH CH353 series devices: The 2S1P is handled by parport_serial
5584          * so not listed here.
5585          */
5586         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5587                 PCI_ANY_ID, PCI_ANY_ID,
5588                 0, 0, pbn_b0_bt_4_115200 },
5589 
5590         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5591                 PCI_ANY_ID, PCI_ANY_ID,
5592                 0, 0, pbn_b0_bt_2_115200 },
5593 
5594         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5595                 PCI_ANY_ID, PCI_ANY_ID,
5596                 0, 0, pbn_wch382_2 },
5597 
5598         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5599                 PCI_ANY_ID, PCI_ANY_ID,
5600                 0, 0, pbn_wch384_4 },
5601 
5602         /*
5603          * Commtech, Inc. Fastcom adapters
5604          */
5605         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5606                 PCI_ANY_ID, PCI_ANY_ID,
5607                 0,
5608                 0, pbn_b0_2_1152000_200 },
5609         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5610                 PCI_ANY_ID, PCI_ANY_ID,
5611                 0,
5612                 0, pbn_b0_4_1152000_200 },
5613         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5614                 PCI_ANY_ID, PCI_ANY_ID,
5615                 0,
5616                 0, pbn_b0_4_1152000_200 },
5617         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5618                 PCI_ANY_ID, PCI_ANY_ID,
5619                 0,
5620                 0, pbn_b0_8_1152000_200 },
5621         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5622                 PCI_ANY_ID, PCI_ANY_ID,
5623                 0,
5624                 0, pbn_exar_XR17V352 },
5625         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5626                 PCI_ANY_ID, PCI_ANY_ID,
5627                 0,
5628                 0, pbn_exar_XR17V354 },
5629         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5630                 PCI_ANY_ID, PCI_ANY_ID,
5631                 0,
5632                 0, pbn_exar_XR17V358 },
5633 
5634         /* Fintek PCI serial cards */
5635         { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5636         { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5637         { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5638 
5639         /*
5640          * These entries match devices with class COMMUNICATION_SERIAL,
5641          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5642          */
5643         {       PCI_ANY_ID, PCI_ANY_ID,
5644                 PCI_ANY_ID, PCI_ANY_ID,
5645                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5646                 0xffff00, pbn_default },
5647         {       PCI_ANY_ID, PCI_ANY_ID,
5648                 PCI_ANY_ID, PCI_ANY_ID,
5649                 PCI_CLASS_COMMUNICATION_MODEM << 8,
5650                 0xffff00, pbn_default },
5651         {       PCI_ANY_ID, PCI_ANY_ID,
5652                 PCI_ANY_ID, PCI_ANY_ID,
5653                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5654                 0xffff00, pbn_default },
5655         { 0, }
5656 };
5657 
5658 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5659                                                 pci_channel_state_t state)
5660 {
5661         struct serial_private *priv = pci_get_drvdata(dev);
5662 
5663         if (state == pci_channel_io_perm_failure)
5664                 return PCI_ERS_RESULT_DISCONNECT;
5665 
5666         if (priv)
5667                 pciserial_suspend_ports(priv);
5668 
5669         pci_disable_device(dev);
5670 
5671         return PCI_ERS_RESULT_NEED_RESET;
5672 }
5673 
5674 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5675 {
5676         int rc;
5677 
5678         rc = pci_enable_device(dev);
5679 
5680         if (rc)
5681                 return PCI_ERS_RESULT_DISCONNECT;
5682 
5683         pci_restore_state(dev);
5684         pci_save_state(dev);
5685 
5686         return PCI_ERS_RESULT_RECOVERED;
5687 }
5688 
5689 static void serial8250_io_resume(struct pci_dev *dev)
5690 {
5691         struct serial_private *priv = pci_get_drvdata(dev);
5692 
5693         if (priv)
5694                 pciserial_resume_ports(priv);
5695 }
5696 
5697 static const struct pci_error_handlers serial8250_err_handler = {
5698         .error_detected = serial8250_io_error_detected,
5699         .slot_reset = serial8250_io_slot_reset,
5700         .resume = serial8250_io_resume,
5701 };
5702 
5703 static struct pci_driver serial_pci_driver = {
5704         .name           = "serial",
5705         .probe          = pciserial_init_one,
5706         .remove         = pciserial_remove_one,
5707         .driver         = {
5708                 .pm     = &pciserial_pm_ops,
5709         },
5710         .id_table       = serial_pci_tbl,
5711         .err_handler    = &serial8250_err_handler,
5712 };
5713 
5714 module_pci_driver(serial_pci_driver);
5715 
5716 MODULE_LICENSE("GPL");
5717 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5718 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
5719 

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