Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4

Linux/drivers/tty/serial/8250/8250_dw.c

  1 /*
  2  * Synopsys DesignWare 8250 driver.
  3  *
  4  * Copyright 2011 Picochip, Jamie Iles.
  5  * Copyright 2013 Intel Corporation
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  *
 12  * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
 13  * LCR is written whilst busy.  If it is, then a busy detect interrupt is
 14  * raised, the LCR needs to be rewritten and the uart status register read.
 15  */
 16 #include <linux/device.h>
 17 #include <linux/io.h>
 18 #include <linux/module.h>
 19 #include <linux/serial_8250.h>
 20 #include <linux/serial_reg.h>
 21 #include <linux/of.h>
 22 #include <linux/of_irq.h>
 23 #include <linux/of_platform.h>
 24 #include <linux/platform_device.h>
 25 #include <linux/slab.h>
 26 #include <linux/acpi.h>
 27 #include <linux/clk.h>
 28 #include <linux/reset.h>
 29 #include <linux/pm_runtime.h>
 30 
 31 #include <asm/byteorder.h>
 32 
 33 #include "8250.h"
 34 
 35 /* Offsets for the DesignWare specific registers */
 36 #define DW_UART_USR     0x1f /* UART Status Register */
 37 #define DW_UART_CPR     0xf4 /* Component Parameter Register */
 38 #define DW_UART_UCV     0xf8 /* UART Component Version */
 39 
 40 /* Component Parameter Register bits */
 41 #define DW_UART_CPR_ABP_DATA_WIDTH      (3 << 0)
 42 #define DW_UART_CPR_AFCE_MODE           (1 << 4)
 43 #define DW_UART_CPR_THRE_MODE           (1 << 5)
 44 #define DW_UART_CPR_SIR_MODE            (1 << 6)
 45 #define DW_UART_CPR_SIR_LP_MODE         (1 << 7)
 46 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
 47 #define DW_UART_CPR_FIFO_ACCESS         (1 << 9)
 48 #define DW_UART_CPR_FIFO_STAT           (1 << 10)
 49 #define DW_UART_CPR_SHADOW              (1 << 11)
 50 #define DW_UART_CPR_ENCODED_PARMS       (1 << 12)
 51 #define DW_UART_CPR_DMA_EXTRA           (1 << 13)
 52 #define DW_UART_CPR_FIFO_MODE           (0xff << 16)
 53 /* Helper for fifo size calculation */
 54 #define DW_UART_CPR_FIFO_SIZE(a)        (((a >> 16) & 0xff) * 16)
 55 
 56 
 57 struct dw8250_data {
 58         u8                      usr_reg;
 59         int                     line;
 60         int                     msr_mask_on;
 61         int                     msr_mask_off;
 62         struct clk              *clk;
 63         struct clk              *pclk;
 64         struct reset_control    *rst;
 65         struct uart_8250_dma    dma;
 66 
 67         unsigned int            skip_autocfg:1;
 68         unsigned int            uart_16550_compatible:1;
 69 };
 70 
 71 #define BYT_PRV_CLK                     0x800
 72 #define BYT_PRV_CLK_EN                  (1 << 0)
 73 #define BYT_PRV_CLK_M_VAL_SHIFT         1
 74 #define BYT_PRV_CLK_N_VAL_SHIFT         16
 75 #define BYT_PRV_CLK_UPDATE              (1 << 31)
 76 
 77 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
 78 {
 79         struct dw8250_data *d = p->private_data;
 80 
 81         /* Override any modem control signals if needed */
 82         if (offset == UART_MSR) {
 83                 value |= d->msr_mask_on;
 84                 value &= ~d->msr_mask_off;
 85         }
 86 
 87         return value;
 88 }
 89 
 90 static void dw8250_force_idle(struct uart_port *p)
 91 {
 92         struct uart_8250_port *up = up_to_u8250p(p);
 93 
 94         serial8250_clear_and_reinit_fifos(up);
 95         (void)p->serial_in(p, UART_RX);
 96 }
 97 
 98 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
 99 {
100         writeb(value, p->membase + (offset << p->regshift));
101 
102         /* Make sure LCR write wasn't ignored */
103         if (offset == UART_LCR) {
104                 int tries = 1000;
105                 while (tries--) {
106                         unsigned int lcr = p->serial_in(p, UART_LCR);
107                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
108                                 return;
109                         dw8250_force_idle(p);
110                         writeb(value, p->membase + (UART_LCR << p->regshift));
111                 }
112                 /*
113                  * FIXME: this deadlocks if port->lock is already held
114                  * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
115                  */
116         }
117 }
118 
119 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
120 {
121         unsigned int value = readb(p->membase + (offset << p->regshift));
122 
123         return dw8250_modify_msr(p, offset, value);
124 }
125 
126 #ifdef CONFIG_64BIT
127 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
128 {
129         unsigned int value;
130 
131         value = (u8)__raw_readq(p->membase + (offset << p->regshift));
132 
133         return dw8250_modify_msr(p, offset, value);
134 }
135 
136 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
137 {
138         value &= 0xff;
139         __raw_writeq(value, p->membase + (offset << p->regshift));
140         /* Read back to ensure register write ordering. */
141         __raw_readq(p->membase + (UART_LCR << p->regshift));
142 
143         /* Make sure LCR write wasn't ignored */
144         if (offset == UART_LCR) {
145                 int tries = 1000;
146                 while (tries--) {
147                         unsigned int lcr = p->serial_in(p, UART_LCR);
148                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
149                                 return;
150                         dw8250_force_idle(p);
151                         __raw_writeq(value & 0xff,
152                                      p->membase + (UART_LCR << p->regshift));
153                 }
154                 /*
155                  * FIXME: this deadlocks if port->lock is already held
156                  * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
157                  */
158         }
159 }
160 #endif /* CONFIG_64BIT */
161 
162 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
163 {
164         writel(value, p->membase + (offset << p->regshift));
165 
166         /* Make sure LCR write wasn't ignored */
167         if (offset == UART_LCR) {
168                 int tries = 1000;
169                 while (tries--) {
170                         unsigned int lcr = p->serial_in(p, UART_LCR);
171                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
172                                 return;
173                         dw8250_force_idle(p);
174                         writel(value, p->membase + (UART_LCR << p->regshift));
175                 }
176                 /*
177                  * FIXME: this deadlocks if port->lock is already held
178                  * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
179                  */
180         }
181 }
182 
183 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
184 {
185         unsigned int value = readl(p->membase + (offset << p->regshift));
186 
187         return dw8250_modify_msr(p, offset, value);
188 }
189 
190 static int dw8250_handle_irq(struct uart_port *p)
191 {
192         struct dw8250_data *d = p->private_data;
193         unsigned int iir = p->serial_in(p, UART_IIR);
194 
195         if (serial8250_handle_irq(p, iir)) {
196                 return 1;
197         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
198                 /* Clear the USR */
199                 (void)p->serial_in(p, d->usr_reg);
200 
201                 return 1;
202         }
203 
204         return 0;
205 }
206 
207 static void
208 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
209 {
210         if (!state)
211                 pm_runtime_get_sync(port->dev);
212 
213         serial8250_do_pm(port, state, old);
214 
215         if (state)
216                 pm_runtime_put_sync_suspend(port->dev);
217 }
218 
219 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
220                                struct ktermios *old)
221 {
222         unsigned int baud = tty_termios_baud_rate(termios);
223         struct dw8250_data *d = p->private_data;
224         unsigned int rate;
225         int ret;
226 
227         if (IS_ERR(d->clk) || !old)
228                 goto out;
229 
230         clk_disable_unprepare(d->clk);
231         rate = clk_round_rate(d->clk, baud * 16);
232         ret = clk_set_rate(d->clk, rate);
233         clk_prepare_enable(d->clk);
234 
235         if (!ret)
236                 p->uartclk = rate;
237 
238         p->status &= ~UPSTAT_AUTOCTS;
239         if (termios->c_cflag & CRTSCTS)
240                 p->status |= UPSTAT_AUTOCTS;
241 
242 out:
243         serial8250_do_set_termios(p, termios, old);
244 }
245 
246 /*
247  * dw8250_fallback_dma_filter will prevent the UART from getting just any free
248  * channel on platforms that have DMA engines, but don't have any channels
249  * assigned to the UART.
250  *
251  * REVISIT: This is a work around for limitation in the DMA Engine API. Once the
252  * core problem is fixed, this function is no longer needed.
253  */
254 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
255 {
256         return false;
257 }
258 
259 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
260 {
261         return param == chan->device->dev->parent;
262 }
263 
264 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
265 {
266         if (p->dev->of_node) {
267                 struct device_node *np = p->dev->of_node;
268                 int id;
269 
270                 /* get index of serial line, if found in DT aliases */
271                 id = of_alias_get_id(np, "serial");
272                 if (id >= 0)
273                         p->line = id;
274 #ifdef CONFIG_64BIT
275                 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
276                         p->serial_in = dw8250_serial_inq;
277                         p->serial_out = dw8250_serial_outq;
278                         p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
279                         p->type = PORT_OCTEON;
280                         data->usr_reg = 0x27;
281                         data->skip_autocfg = true;
282                 }
283 #endif
284         } else if (has_acpi_companion(p->dev)) {
285                 p->iotype = UPIO_MEM32;
286                 p->regshift = 2;
287                 p->serial_in = dw8250_serial_in32;
288                 p->set_termios = dw8250_set_termios;
289                 /* So far none of there implement the Busy Functionality */
290                 data->uart_16550_compatible = true;
291         }
292 
293         /* Platforms with iDMA */
294         if (platform_get_resource_byname(to_platform_device(p->dev),
295                                          IORESOURCE_MEM, "lpss_priv")) {
296                 p->set_termios = dw8250_set_termios;
297                 data->dma.rx_param = p->dev->parent;
298                 data->dma.tx_param = p->dev->parent;
299                 data->dma.fn = dw8250_idma_filter;
300         }
301 }
302 
303 static void dw8250_setup_port(struct uart_port *p)
304 {
305         struct uart_8250_port *up = up_to_u8250p(p);
306         u32 reg;
307 
308         /*
309          * If the Component Version Register returns zero, we know that
310          * ADDITIONAL_FEATURES are not enabled. No need to go any further.
311          */
312         reg = readl(p->membase + DW_UART_UCV);
313         if (!reg)
314                 return;
315 
316         dev_dbg(p->dev, "Designware UART version %c.%c%c\n",
317                 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
318 
319         reg = readl(p->membase + DW_UART_CPR);
320         if (!reg)
321                 return;
322 
323         /* Select the type based on fifo */
324         if (reg & DW_UART_CPR_FIFO_MODE) {
325                 p->type = PORT_16550A;
326                 p->flags |= UPF_FIXED_TYPE;
327                 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
328                 up->capabilities = UART_CAP_FIFO;
329         }
330 
331         if (reg & DW_UART_CPR_AFCE_MODE)
332                 up->capabilities |= UART_CAP_AFE;
333 }
334 
335 static int dw8250_probe(struct platform_device *pdev)
336 {
337         struct uart_8250_port uart = {};
338         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
339         int irq = platform_get_irq(pdev, 0);
340         struct uart_port *p = &uart.port;
341         struct dw8250_data *data;
342         int err;
343         u32 val;
344 
345         if (!regs) {
346                 dev_err(&pdev->dev, "no registers defined\n");
347                 return -EINVAL;
348         }
349 
350         if (irq < 0) {
351                 if (irq != -EPROBE_DEFER)
352                         dev_err(&pdev->dev, "cannot get irq\n");
353                 return irq;
354         }
355 
356         spin_lock_init(&p->lock);
357         p->mapbase      = regs->start;
358         p->irq          = irq;
359         p->handle_irq   = dw8250_handle_irq;
360         p->pm           = dw8250_do_pm;
361         p->type         = PORT_8250;
362         p->flags        = UPF_SHARE_IRQ | UPF_FIXED_PORT;
363         p->dev          = &pdev->dev;
364         p->iotype       = UPIO_MEM;
365         p->serial_in    = dw8250_serial_in;
366         p->serial_out   = dw8250_serial_out;
367 
368         p->membase = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
369         if (!p->membase)
370                 return -ENOMEM;
371 
372         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
373         if (!data)
374                 return -ENOMEM;
375 
376         data->dma.fn = dw8250_fallback_dma_filter;
377         data->usr_reg = DW_UART_USR;
378         p->private_data = data;
379 
380         data->uart_16550_compatible = device_property_read_bool(p->dev,
381                                                 "snps,uart-16550-compatible");
382 
383         err = device_property_read_u32(p->dev, "reg-shift", &val);
384         if (!err)
385                 p->regshift = val;
386 
387         err = device_property_read_u32(p->dev, "reg-io-width", &val);
388         if (!err && val == 4) {
389                 p->iotype = UPIO_MEM32;
390                 p->serial_in = dw8250_serial_in32;
391                 p->serial_out = dw8250_serial_out32;
392         }
393 
394         if (device_property_read_bool(p->dev, "dcd-override")) {
395                 /* Always report DCD as active */
396                 data->msr_mask_on |= UART_MSR_DCD;
397                 data->msr_mask_off |= UART_MSR_DDCD;
398         }
399 
400         if (device_property_read_bool(p->dev, "dsr-override")) {
401                 /* Always report DSR as active */
402                 data->msr_mask_on |= UART_MSR_DSR;
403                 data->msr_mask_off |= UART_MSR_DDSR;
404         }
405 
406         if (device_property_read_bool(p->dev, "cts-override")) {
407                 /* Always report CTS as active */
408                 data->msr_mask_on |= UART_MSR_CTS;
409                 data->msr_mask_off |= UART_MSR_DCTS;
410         }
411 
412         if (device_property_read_bool(p->dev, "ri-override")) {
413                 /* Always report Ring indicator as inactive */
414                 data->msr_mask_off |= UART_MSR_RI;
415                 data->msr_mask_off |= UART_MSR_TERI;
416         }
417 
418         /* Always ask for fixed clock rate from a property. */
419         device_property_read_u32(p->dev, "clock-frequency", &p->uartclk);
420 
421         /* If there is separate baudclk, get the rate from it. */
422         data->clk = devm_clk_get(&pdev->dev, "baudclk");
423         if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
424                 data->clk = devm_clk_get(&pdev->dev, NULL);
425         if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
426                 return -EPROBE_DEFER;
427         if (!IS_ERR_OR_NULL(data->clk)) {
428                 err = clk_prepare_enable(data->clk);
429                 if (err)
430                         dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n",
431                                  err);
432                 else
433                         p->uartclk = clk_get_rate(data->clk);
434         }
435 
436         /* If no clock rate is defined, fail. */
437         if (!p->uartclk) {
438                 dev_err(&pdev->dev, "clock rate not defined\n");
439                 return -EINVAL;
440         }
441 
442         data->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
443         if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) {
444                 err = -EPROBE_DEFER;
445                 goto err_clk;
446         }
447         if (!IS_ERR(data->pclk)) {
448                 err = clk_prepare_enable(data->pclk);
449                 if (err) {
450                         dev_err(&pdev->dev, "could not enable apb_pclk\n");
451                         goto err_clk;
452                 }
453         }
454 
455         data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
456         if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
457                 err = -EPROBE_DEFER;
458                 goto err_pclk;
459         }
460         if (!IS_ERR(data->rst))
461                 reset_control_deassert(data->rst);
462 
463         dw8250_quirks(p, data);
464 
465         /* If the Busy Functionality is not implemented, don't handle it */
466         if (data->uart_16550_compatible) {
467                 p->serial_out = NULL;
468                 p->handle_irq = NULL;
469         }
470 
471         if (!data->skip_autocfg)
472                 dw8250_setup_port(p);
473 
474         /* If we have a valid fifosize, try hooking up DMA */
475         if (p->fifosize) {
476                 data->dma.rxconf.src_maxburst = p->fifosize / 4;
477                 data->dma.txconf.dst_maxburst = p->fifosize / 4;
478                 uart.dma = &data->dma;
479         }
480 
481         data->line = serial8250_register_8250_port(&uart);
482         if (data->line < 0) {
483                 err = data->line;
484                 goto err_reset;
485         }
486 
487         platform_set_drvdata(pdev, data);
488 
489         pm_runtime_set_active(&pdev->dev);
490         pm_runtime_enable(&pdev->dev);
491 
492         return 0;
493 
494 err_reset:
495         if (!IS_ERR(data->rst))
496                 reset_control_assert(data->rst);
497 
498 err_pclk:
499         if (!IS_ERR(data->pclk))
500                 clk_disable_unprepare(data->pclk);
501 
502 err_clk:
503         if (!IS_ERR(data->clk))
504                 clk_disable_unprepare(data->clk);
505 
506         return err;
507 }
508 
509 static int dw8250_remove(struct platform_device *pdev)
510 {
511         struct dw8250_data *data = platform_get_drvdata(pdev);
512 
513         pm_runtime_get_sync(&pdev->dev);
514 
515         serial8250_unregister_port(data->line);
516 
517         if (!IS_ERR(data->rst))
518                 reset_control_assert(data->rst);
519 
520         if (!IS_ERR(data->pclk))
521                 clk_disable_unprepare(data->pclk);
522 
523         if (!IS_ERR(data->clk))
524                 clk_disable_unprepare(data->clk);
525 
526         pm_runtime_disable(&pdev->dev);
527         pm_runtime_put_noidle(&pdev->dev);
528 
529         return 0;
530 }
531 
532 #ifdef CONFIG_PM_SLEEP
533 static int dw8250_suspend(struct device *dev)
534 {
535         struct dw8250_data *data = dev_get_drvdata(dev);
536 
537         serial8250_suspend_port(data->line);
538 
539         return 0;
540 }
541 
542 static int dw8250_resume(struct device *dev)
543 {
544         struct dw8250_data *data = dev_get_drvdata(dev);
545 
546         serial8250_resume_port(data->line);
547 
548         return 0;
549 }
550 #endif /* CONFIG_PM_SLEEP */
551 
552 #ifdef CONFIG_PM
553 static int dw8250_runtime_suspend(struct device *dev)
554 {
555         struct dw8250_data *data = dev_get_drvdata(dev);
556 
557         if (!IS_ERR(data->clk))
558                 clk_disable_unprepare(data->clk);
559 
560         if (!IS_ERR(data->pclk))
561                 clk_disable_unprepare(data->pclk);
562 
563         return 0;
564 }
565 
566 static int dw8250_runtime_resume(struct device *dev)
567 {
568         struct dw8250_data *data = dev_get_drvdata(dev);
569 
570         if (!IS_ERR(data->pclk))
571                 clk_prepare_enable(data->pclk);
572 
573         if (!IS_ERR(data->clk))
574                 clk_prepare_enable(data->clk);
575 
576         return 0;
577 }
578 #endif
579 
580 static const struct dev_pm_ops dw8250_pm_ops = {
581         SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
582         SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
583 };
584 
585 static const struct of_device_id dw8250_of_match[] = {
586         { .compatible = "snps,dw-apb-uart" },
587         { .compatible = "cavium,octeon-3860-uart" },
588         { /* Sentinel */ }
589 };
590 MODULE_DEVICE_TABLE(of, dw8250_of_match);
591 
592 static const struct acpi_device_id dw8250_acpi_match[] = {
593         { "INT33C4", 0 },
594         { "INT33C5", 0 },
595         { "INT3434", 0 },
596         { "INT3435", 0 },
597         { "80860F0A", 0 },
598         { "8086228A", 0 },
599         { "APMC0D08", 0},
600         { "AMD0020", 0 },
601         { },
602 };
603 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
604 
605 static struct platform_driver dw8250_platform_driver = {
606         .driver = {
607                 .name           = "dw-apb-uart",
608                 .pm             = &dw8250_pm_ops,
609                 .of_match_table = dw8250_of_match,
610                 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
611         },
612         .probe                  = dw8250_probe,
613         .remove                 = dw8250_remove,
614 };
615 
616 module_platform_driver(dw8250_platform_driver);
617 
618 MODULE_AUTHOR("Jamie Iles");
619 MODULE_LICENSE("GPL");
620 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
621 MODULE_ALIAS("platform:dw-apb-uart");
622 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us