Version:  2.0.40 2.2.26 2.4.37 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6

Linux/drivers/tty/serial/8250/8250_dw.c

  1 /*
  2  * Synopsys DesignWare 8250 driver.
  3  *
  4  * Copyright 2011 Picochip, Jamie Iles.
  5  * Copyright 2013 Intel Corporation
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  *
 12  * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
 13  * LCR is written whilst busy.  If it is, then a busy detect interrupt is
 14  * raised, the LCR needs to be rewritten and the uart status register read.
 15  */
 16 #include <linux/device.h>
 17 #include <linux/io.h>
 18 #include <linux/module.h>
 19 #include <linux/serial_8250.h>
 20 #include <linux/serial_reg.h>
 21 #include <linux/of.h>
 22 #include <linux/of_irq.h>
 23 #include <linux/of_platform.h>
 24 #include <linux/platform_device.h>
 25 #include <linux/slab.h>
 26 #include <linux/acpi.h>
 27 #include <linux/clk.h>
 28 #include <linux/reset.h>
 29 #include <linux/pm_runtime.h>
 30 
 31 #include <asm/byteorder.h>
 32 
 33 #include "8250.h"
 34 
 35 /* Offsets for the DesignWare specific registers */
 36 #define DW_UART_USR     0x1f /* UART Status Register */
 37 #define DW_UART_CPR     0xf4 /* Component Parameter Register */
 38 #define DW_UART_UCV     0xf8 /* UART Component Version */
 39 
 40 /* Component Parameter Register bits */
 41 #define DW_UART_CPR_ABP_DATA_WIDTH      (3 << 0)
 42 #define DW_UART_CPR_AFCE_MODE           (1 << 4)
 43 #define DW_UART_CPR_THRE_MODE           (1 << 5)
 44 #define DW_UART_CPR_SIR_MODE            (1 << 6)
 45 #define DW_UART_CPR_SIR_LP_MODE         (1 << 7)
 46 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
 47 #define DW_UART_CPR_FIFO_ACCESS         (1 << 9)
 48 #define DW_UART_CPR_FIFO_STAT           (1 << 10)
 49 #define DW_UART_CPR_SHADOW              (1 << 11)
 50 #define DW_UART_CPR_ENCODED_PARMS       (1 << 12)
 51 #define DW_UART_CPR_DMA_EXTRA           (1 << 13)
 52 #define DW_UART_CPR_FIFO_MODE           (0xff << 16)
 53 /* Helper for fifo size calculation */
 54 #define DW_UART_CPR_FIFO_SIZE(a)        (((a >> 16) & 0xff) * 16)
 55 
 56 
 57 struct dw8250_data {
 58         u8                      usr_reg;
 59         int                     line;
 60         int                     msr_mask_on;
 61         int                     msr_mask_off;
 62         struct clk              *clk;
 63         struct clk              *pclk;
 64         struct reset_control    *rst;
 65         struct uart_8250_dma    dma;
 66 
 67         unsigned int            skip_autocfg:1;
 68         unsigned int            uart_16550_compatible:1;
 69 };
 70 
 71 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
 72 {
 73         struct dw8250_data *d = p->private_data;
 74 
 75         /* Override any modem control signals if needed */
 76         if (offset == UART_MSR) {
 77                 value |= d->msr_mask_on;
 78                 value &= ~d->msr_mask_off;
 79         }
 80 
 81         return value;
 82 }
 83 
 84 static void dw8250_force_idle(struct uart_port *p)
 85 {
 86         struct uart_8250_port *up = up_to_u8250p(p);
 87 
 88         serial8250_clear_and_reinit_fifos(up);
 89         (void)p->serial_in(p, UART_RX);
 90 }
 91 
 92 static void dw8250_check_lcr(struct uart_port *p, int value)
 93 {
 94         void __iomem *offset = p->membase + (UART_LCR << p->regshift);
 95         int tries = 1000;
 96 
 97         /* Make sure LCR write wasn't ignored */
 98         while (tries--) {
 99                 unsigned int lcr = p->serial_in(p, UART_LCR);
100 
101                 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
102                         return;
103 
104                 dw8250_force_idle(p);
105 
106 #ifdef CONFIG_64BIT
107                 __raw_writeq(value & 0xff, offset);
108 #else
109                 if (p->iotype == UPIO_MEM32)
110                         writel(value, offset);
111                 else if (p->iotype == UPIO_MEM32BE)
112                         iowrite32be(value, offset);
113                 else
114                         writeb(value, offset);
115 #endif
116         }
117         /*
118          * FIXME: this deadlocks if port->lock is already held
119          * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
120          */
121 }
122 
123 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
124 {
125         struct dw8250_data *d = p->private_data;
126 
127         writeb(value, p->membase + (offset << p->regshift));
128 
129         if (offset == UART_LCR && !d->uart_16550_compatible)
130                 dw8250_check_lcr(p, value);
131 }
132 
133 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
134 {
135         unsigned int value = readb(p->membase + (offset << p->regshift));
136 
137         return dw8250_modify_msr(p, offset, value);
138 }
139 
140 #ifdef CONFIG_64BIT
141 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
142 {
143         unsigned int value;
144 
145         value = (u8)__raw_readq(p->membase + (offset << p->regshift));
146 
147         return dw8250_modify_msr(p, offset, value);
148 }
149 
150 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
151 {
152         struct dw8250_data *d = p->private_data;
153 
154         value &= 0xff;
155         __raw_writeq(value, p->membase + (offset << p->regshift));
156         /* Read back to ensure register write ordering. */
157         __raw_readq(p->membase + (UART_LCR << p->regshift));
158 
159         if (offset == UART_LCR && !d->uart_16550_compatible)
160                 dw8250_check_lcr(p, value);
161 }
162 #endif /* CONFIG_64BIT */
163 
164 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
165 {
166         struct dw8250_data *d = p->private_data;
167 
168         writel(value, p->membase + (offset << p->regshift));
169 
170         if (offset == UART_LCR && !d->uart_16550_compatible)
171                 dw8250_check_lcr(p, value);
172 }
173 
174 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
175 {
176         unsigned int value = readl(p->membase + (offset << p->regshift));
177 
178         return dw8250_modify_msr(p, offset, value);
179 }
180 
181 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
182 {
183         struct dw8250_data *d = p->private_data;
184 
185         iowrite32be(value, p->membase + (offset << p->regshift));
186 
187         if (offset == UART_LCR && !d->uart_16550_compatible)
188                 dw8250_check_lcr(p, value);
189 }
190 
191 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
192 {
193        unsigned int value = ioread32be(p->membase + (offset << p->regshift));
194 
195        return dw8250_modify_msr(p, offset, value);
196 }
197 
198 
199 static int dw8250_handle_irq(struct uart_port *p)
200 {
201         struct dw8250_data *d = p->private_data;
202         unsigned int iir = p->serial_in(p, UART_IIR);
203 
204         if (serial8250_handle_irq(p, iir))
205                 return 1;
206 
207         if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
208                 /* Clear the USR */
209                 (void)p->serial_in(p, d->usr_reg);
210 
211                 return 1;
212         }
213 
214         return 0;
215 }
216 
217 static void
218 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
219 {
220         if (!state)
221                 pm_runtime_get_sync(port->dev);
222 
223         serial8250_do_pm(port, state, old);
224 
225         if (state)
226                 pm_runtime_put_sync_suspend(port->dev);
227 }
228 
229 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
230                                struct ktermios *old)
231 {
232         unsigned int baud = tty_termios_baud_rate(termios);
233         struct dw8250_data *d = p->private_data;
234         unsigned int rate;
235         int ret;
236 
237         if (IS_ERR(d->clk) || !old)
238                 goto out;
239 
240         clk_disable_unprepare(d->clk);
241         rate = clk_round_rate(d->clk, baud * 16);
242         ret = clk_set_rate(d->clk, rate);
243         clk_prepare_enable(d->clk);
244 
245         if (!ret)
246                 p->uartclk = rate;
247 
248         p->status &= ~UPSTAT_AUTOCTS;
249         if (termios->c_cflag & CRTSCTS)
250                 p->status |= UPSTAT_AUTOCTS;
251 
252 out:
253         serial8250_do_set_termios(p, termios, old);
254 }
255 
256 /*
257  * dw8250_fallback_dma_filter will prevent the UART from getting just any free
258  * channel on platforms that have DMA engines, but don't have any channels
259  * assigned to the UART.
260  *
261  * REVISIT: This is a work around for limitation in the DMA Engine API. Once the
262  * core problem is fixed, this function is no longer needed.
263  */
264 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
265 {
266         return false;
267 }
268 
269 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
270 {
271         return param == chan->device->dev->parent;
272 }
273 
274 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
275 {
276         if (p->dev->of_node) {
277                 struct device_node *np = p->dev->of_node;
278                 int id;
279 
280                 /* get index of serial line, if found in DT aliases */
281                 id = of_alias_get_id(np, "serial");
282                 if (id >= 0)
283                         p->line = id;
284 #ifdef CONFIG_64BIT
285                 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
286                         p->serial_in = dw8250_serial_inq;
287                         p->serial_out = dw8250_serial_outq;
288                         p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
289                         p->type = PORT_OCTEON;
290                         data->usr_reg = 0x27;
291                         data->skip_autocfg = true;
292                 }
293 #endif
294                 if (of_device_is_big_endian(p->dev->of_node)) {
295                         p->iotype = UPIO_MEM32BE;
296                         p->serial_in = dw8250_serial_in32be;
297                         p->serial_out = dw8250_serial_out32be;
298                 }
299         } else if (has_acpi_companion(p->dev)) {
300                 p->iotype = UPIO_MEM32;
301                 p->regshift = 2;
302                 p->serial_in = dw8250_serial_in32;
303                 p->set_termios = dw8250_set_termios;
304                 /* So far none of there implement the Busy Functionality */
305                 data->uart_16550_compatible = true;
306         }
307 
308         /* Platforms with iDMA */
309         if (platform_get_resource_byname(to_platform_device(p->dev),
310                                          IORESOURCE_MEM, "lpss_priv")) {
311                 p->set_termios = dw8250_set_termios;
312                 data->dma.rx_param = p->dev->parent;
313                 data->dma.tx_param = p->dev->parent;
314                 data->dma.fn = dw8250_idma_filter;
315         }
316 }
317 
318 static void dw8250_setup_port(struct uart_port *p)
319 {
320         struct uart_8250_port *up = up_to_u8250p(p);
321         u32 reg;
322 
323         /*
324          * If the Component Version Register returns zero, we know that
325          * ADDITIONAL_FEATURES are not enabled. No need to go any further.
326          */
327         if (p->iotype == UPIO_MEM32BE)
328                 reg = ioread32be(p->membase + DW_UART_UCV);
329         else
330                 reg = readl(p->membase + DW_UART_UCV);
331         if (!reg)
332                 return;
333 
334         dev_dbg(p->dev, "Designware UART version %c.%c%c\n",
335                 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
336 
337         if (p->iotype == UPIO_MEM32BE)
338                 reg = ioread32be(p->membase + DW_UART_CPR);
339         else
340                 reg = readl(p->membase + DW_UART_CPR);
341         if (!reg)
342                 return;
343 
344         /* Select the type based on fifo */
345         if (reg & DW_UART_CPR_FIFO_MODE) {
346                 p->type = PORT_16550A;
347                 p->flags |= UPF_FIXED_TYPE;
348                 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
349                 up->capabilities = UART_CAP_FIFO;
350         }
351 
352         if (reg & DW_UART_CPR_AFCE_MODE)
353                 up->capabilities |= UART_CAP_AFE;
354 }
355 
356 static int dw8250_probe(struct platform_device *pdev)
357 {
358         struct uart_8250_port uart = {};
359         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
360         int irq = platform_get_irq(pdev, 0);
361         struct uart_port *p = &uart.port;
362         struct dw8250_data *data;
363         int err;
364         u32 val;
365 
366         if (!regs) {
367                 dev_err(&pdev->dev, "no registers defined\n");
368                 return -EINVAL;
369         }
370 
371         if (irq < 0) {
372                 if (irq != -EPROBE_DEFER)
373                         dev_err(&pdev->dev, "cannot get irq\n");
374                 return irq;
375         }
376 
377         spin_lock_init(&p->lock);
378         p->mapbase      = regs->start;
379         p->irq          = irq;
380         p->handle_irq   = dw8250_handle_irq;
381         p->pm           = dw8250_do_pm;
382         p->type         = PORT_8250;
383         p->flags        = UPF_SHARE_IRQ | UPF_FIXED_PORT;
384         p->dev          = &pdev->dev;
385         p->iotype       = UPIO_MEM;
386         p->serial_in    = dw8250_serial_in;
387         p->serial_out   = dw8250_serial_out;
388 
389         p->membase = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
390         if (!p->membase)
391                 return -ENOMEM;
392 
393         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
394         if (!data)
395                 return -ENOMEM;
396 
397         data->dma.fn = dw8250_fallback_dma_filter;
398         data->usr_reg = DW_UART_USR;
399         p->private_data = data;
400 
401         data->uart_16550_compatible = device_property_read_bool(p->dev,
402                                                 "snps,uart-16550-compatible");
403 
404         err = device_property_read_u32(p->dev, "reg-shift", &val);
405         if (!err)
406                 p->regshift = val;
407 
408         err = device_property_read_u32(p->dev, "reg-io-width", &val);
409         if (!err && val == 4) {
410                 p->iotype = UPIO_MEM32;
411                 p->serial_in = dw8250_serial_in32;
412                 p->serial_out = dw8250_serial_out32;
413         }
414 
415         if (device_property_read_bool(p->dev, "dcd-override")) {
416                 /* Always report DCD as active */
417                 data->msr_mask_on |= UART_MSR_DCD;
418                 data->msr_mask_off |= UART_MSR_DDCD;
419         }
420 
421         if (device_property_read_bool(p->dev, "dsr-override")) {
422                 /* Always report DSR as active */
423                 data->msr_mask_on |= UART_MSR_DSR;
424                 data->msr_mask_off |= UART_MSR_DDSR;
425         }
426 
427         if (device_property_read_bool(p->dev, "cts-override")) {
428                 /* Always report CTS as active */
429                 data->msr_mask_on |= UART_MSR_CTS;
430                 data->msr_mask_off |= UART_MSR_DCTS;
431         }
432 
433         if (device_property_read_bool(p->dev, "ri-override")) {
434                 /* Always report Ring indicator as inactive */
435                 data->msr_mask_off |= UART_MSR_RI;
436                 data->msr_mask_off |= UART_MSR_TERI;
437         }
438 
439         /* Always ask for fixed clock rate from a property. */
440         device_property_read_u32(p->dev, "clock-frequency", &p->uartclk);
441 
442         /* If there is separate baudclk, get the rate from it. */
443         data->clk = devm_clk_get(&pdev->dev, "baudclk");
444         if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
445                 data->clk = devm_clk_get(&pdev->dev, NULL);
446         if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
447                 return -EPROBE_DEFER;
448         if (!IS_ERR_OR_NULL(data->clk)) {
449                 err = clk_prepare_enable(data->clk);
450                 if (err)
451                         dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n",
452                                  err);
453                 else
454                         p->uartclk = clk_get_rate(data->clk);
455         }
456 
457         /* If no clock rate is defined, fail. */
458         if (!p->uartclk) {
459                 dev_err(&pdev->dev, "clock rate not defined\n");
460                 return -EINVAL;
461         }
462 
463         data->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
464         if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) {
465                 err = -EPROBE_DEFER;
466                 goto err_clk;
467         }
468         if (!IS_ERR(data->pclk)) {
469                 err = clk_prepare_enable(data->pclk);
470                 if (err) {
471                         dev_err(&pdev->dev, "could not enable apb_pclk\n");
472                         goto err_clk;
473                 }
474         }
475 
476         data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
477         if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
478                 err = -EPROBE_DEFER;
479                 goto err_pclk;
480         }
481         if (!IS_ERR(data->rst))
482                 reset_control_deassert(data->rst);
483 
484         dw8250_quirks(p, data);
485 
486         /* If the Busy Functionality is not implemented, don't handle it */
487         if (data->uart_16550_compatible)
488                 p->handle_irq = NULL;
489 
490         if (!data->skip_autocfg)
491                 dw8250_setup_port(p);
492 
493         /* If we have a valid fifosize, try hooking up DMA */
494         if (p->fifosize) {
495                 data->dma.rxconf.src_maxburst = p->fifosize / 4;
496                 data->dma.txconf.dst_maxburst = p->fifosize / 4;
497                 uart.dma = &data->dma;
498         }
499 
500         data->line = serial8250_register_8250_port(&uart);
501         if (data->line < 0) {
502                 err = data->line;
503                 goto err_reset;
504         }
505 
506         platform_set_drvdata(pdev, data);
507 
508         pm_runtime_set_active(&pdev->dev);
509         pm_runtime_enable(&pdev->dev);
510 
511         return 0;
512 
513 err_reset:
514         if (!IS_ERR(data->rst))
515                 reset_control_assert(data->rst);
516 
517 err_pclk:
518         if (!IS_ERR(data->pclk))
519                 clk_disable_unprepare(data->pclk);
520 
521 err_clk:
522         if (!IS_ERR(data->clk))
523                 clk_disable_unprepare(data->clk);
524 
525         return err;
526 }
527 
528 static int dw8250_remove(struct platform_device *pdev)
529 {
530         struct dw8250_data *data = platform_get_drvdata(pdev);
531 
532         pm_runtime_get_sync(&pdev->dev);
533 
534         serial8250_unregister_port(data->line);
535 
536         if (!IS_ERR(data->rst))
537                 reset_control_assert(data->rst);
538 
539         if (!IS_ERR(data->pclk))
540                 clk_disable_unprepare(data->pclk);
541 
542         if (!IS_ERR(data->clk))
543                 clk_disable_unprepare(data->clk);
544 
545         pm_runtime_disable(&pdev->dev);
546         pm_runtime_put_noidle(&pdev->dev);
547 
548         return 0;
549 }
550 
551 #ifdef CONFIG_PM_SLEEP
552 static int dw8250_suspend(struct device *dev)
553 {
554         struct dw8250_data *data = dev_get_drvdata(dev);
555 
556         serial8250_suspend_port(data->line);
557 
558         return 0;
559 }
560 
561 static int dw8250_resume(struct device *dev)
562 {
563         struct dw8250_data *data = dev_get_drvdata(dev);
564 
565         serial8250_resume_port(data->line);
566 
567         return 0;
568 }
569 #endif /* CONFIG_PM_SLEEP */
570 
571 #ifdef CONFIG_PM
572 static int dw8250_runtime_suspend(struct device *dev)
573 {
574         struct dw8250_data *data = dev_get_drvdata(dev);
575 
576         if (!IS_ERR(data->clk))
577                 clk_disable_unprepare(data->clk);
578 
579         if (!IS_ERR(data->pclk))
580                 clk_disable_unprepare(data->pclk);
581 
582         return 0;
583 }
584 
585 static int dw8250_runtime_resume(struct device *dev)
586 {
587         struct dw8250_data *data = dev_get_drvdata(dev);
588 
589         if (!IS_ERR(data->pclk))
590                 clk_prepare_enable(data->pclk);
591 
592         if (!IS_ERR(data->clk))
593                 clk_prepare_enable(data->clk);
594 
595         return 0;
596 }
597 #endif
598 
599 static const struct dev_pm_ops dw8250_pm_ops = {
600         SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
601         SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
602 };
603 
604 static const struct of_device_id dw8250_of_match[] = {
605         { .compatible = "snps,dw-apb-uart" },
606         { .compatible = "cavium,octeon-3860-uart" },
607         { /* Sentinel */ }
608 };
609 MODULE_DEVICE_TABLE(of, dw8250_of_match);
610 
611 static const struct acpi_device_id dw8250_acpi_match[] = {
612         { "INT33C4", 0 },
613         { "INT33C5", 0 },
614         { "INT3434", 0 },
615         { "INT3435", 0 },
616         { "80860F0A", 0 },
617         { "8086228A", 0 },
618         { "APMC0D08", 0},
619         { "AMD0020", 0 },
620         { },
621 };
622 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
623 
624 static struct platform_driver dw8250_platform_driver = {
625         .driver = {
626                 .name           = "dw-apb-uart",
627                 .pm             = &dw8250_pm_ops,
628                 .of_match_table = dw8250_of_match,
629                 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
630         },
631         .probe                  = dw8250_probe,
632         .remove                 = dw8250_remove,
633 };
634 
635 module_platform_driver(dw8250_platform_driver);
636 
637 MODULE_AUTHOR("Jamie Iles");
638 MODULE_LICENSE("GPL");
639 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
640 MODULE_ALIAS("platform:dw-apb-uart");
641 

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