Version:  2.0.40 2.2.26 2.4.37 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19

Linux/drivers/tty/serial/8250/8250_dw.c

  1 /*
  2  * Synopsys DesignWare 8250 driver.
  3  *
  4  * Copyright 2011 Picochip, Jamie Iles.
  5  * Copyright 2013 Intel Corporation
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  *
 12  * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
 13  * LCR is written whilst busy.  If it is, then a busy detect interrupt is
 14  * raised, the LCR needs to be rewritten and the uart status register read.
 15  */
 16 #include <linux/device.h>
 17 #include <linux/io.h>
 18 #include <linux/module.h>
 19 #include <linux/serial_8250.h>
 20 #include <linux/serial_core.h>
 21 #include <linux/serial_reg.h>
 22 #include <linux/of.h>
 23 #include <linux/of_irq.h>
 24 #include <linux/of_platform.h>
 25 #include <linux/platform_device.h>
 26 #include <linux/slab.h>
 27 #include <linux/acpi.h>
 28 #include <linux/clk.h>
 29 #include <linux/reset.h>
 30 #include <linux/pm_runtime.h>
 31 
 32 #include <asm/byteorder.h>
 33 
 34 #include "8250.h"
 35 
 36 /* Offsets for the DesignWare specific registers */
 37 #define DW_UART_USR     0x1f /* UART Status Register */
 38 #define DW_UART_CPR     0xf4 /* Component Parameter Register */
 39 #define DW_UART_UCV     0xf8 /* UART Component Version */
 40 
 41 /* Component Parameter Register bits */
 42 #define DW_UART_CPR_ABP_DATA_WIDTH      (3 << 0)
 43 #define DW_UART_CPR_AFCE_MODE           (1 << 4)
 44 #define DW_UART_CPR_THRE_MODE           (1 << 5)
 45 #define DW_UART_CPR_SIR_MODE            (1 << 6)
 46 #define DW_UART_CPR_SIR_LP_MODE         (1 << 7)
 47 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
 48 #define DW_UART_CPR_FIFO_ACCESS         (1 << 9)
 49 #define DW_UART_CPR_FIFO_STAT           (1 << 10)
 50 #define DW_UART_CPR_SHADOW              (1 << 11)
 51 #define DW_UART_CPR_ENCODED_PARMS       (1 << 12)
 52 #define DW_UART_CPR_DMA_EXTRA           (1 << 13)
 53 #define DW_UART_CPR_FIFO_MODE           (0xff << 16)
 54 /* Helper for fifo size calculation */
 55 #define DW_UART_CPR_FIFO_SIZE(a)        (((a >> 16) & 0xff) * 16)
 56 
 57 
 58 struct dw8250_data {
 59         u8                      usr_reg;
 60         int                     last_mcr;
 61         int                     line;
 62         struct clk              *clk;
 63         struct clk              *pclk;
 64         struct reset_control    *rst;
 65         struct uart_8250_dma    dma;
 66 };
 67 
 68 #define BYT_PRV_CLK                     0x800
 69 #define BYT_PRV_CLK_EN                  (1 << 0)
 70 #define BYT_PRV_CLK_M_VAL_SHIFT         1
 71 #define BYT_PRV_CLK_N_VAL_SHIFT         16
 72 #define BYT_PRV_CLK_UPDATE              (1 << 31)
 73 
 74 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
 75 {
 76         struct dw8250_data *d = p->private_data;
 77 
 78         /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
 79         if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
 80                 value |= UART_MSR_CTS;
 81                 value &= ~UART_MSR_DCTS;
 82         }
 83 
 84         return value;
 85 }
 86 
 87 static void dw8250_force_idle(struct uart_port *p)
 88 {
 89         struct uart_8250_port *up = up_to_u8250p(p);
 90 
 91         serial8250_clear_and_reinit_fifos(up);
 92         (void)p->serial_in(p, UART_RX);
 93 }
 94 
 95 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
 96 {
 97         struct dw8250_data *d = p->private_data;
 98 
 99         if (offset == UART_MCR)
100                 d->last_mcr = value;
101 
102         writeb(value, p->membase + (offset << p->regshift));
103 
104         /* Make sure LCR write wasn't ignored */
105         if (offset == UART_LCR) {
106                 int tries = 1000;
107                 while (tries--) {
108                         unsigned int lcr = p->serial_in(p, UART_LCR);
109                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
110                                 return;
111                         dw8250_force_idle(p);
112                         writeb(value, p->membase + (UART_LCR << p->regshift));
113                 }
114                 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
115         }
116 }
117 
118 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
119 {
120         unsigned int value = readb(p->membase + (offset << p->regshift));
121 
122         return dw8250_modify_msr(p, offset, value);
123 }
124 
125 #ifdef CONFIG_64BIT
126 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
127 {
128         unsigned int value;
129 
130         value = (u8)__raw_readq(p->membase + (offset << p->regshift));
131 
132         return dw8250_modify_msr(p, offset, value);
133 }
134 
135 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
136 {
137         struct dw8250_data *d = p->private_data;
138 
139         if (offset == UART_MCR)
140                 d->last_mcr = value;
141 
142         value &= 0xff;
143         __raw_writeq(value, p->membase + (offset << p->regshift));
144         /* Read back to ensure register write ordering. */
145         __raw_readq(p->membase + (UART_LCR << p->regshift));
146 
147         /* Make sure LCR write wasn't ignored */
148         if (offset == UART_LCR) {
149                 int tries = 1000;
150                 while (tries--) {
151                         unsigned int lcr = p->serial_in(p, UART_LCR);
152                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
153                                 return;
154                         dw8250_force_idle(p);
155                         __raw_writeq(value & 0xff,
156                                      p->membase + (UART_LCR << p->regshift));
157                 }
158                 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
159         }
160 }
161 #endif /* CONFIG_64BIT */
162 
163 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
164 {
165         struct dw8250_data *d = p->private_data;
166 
167         if (offset == UART_MCR)
168                 d->last_mcr = value;
169 
170         writel(value, p->membase + (offset << p->regshift));
171 
172         /* Make sure LCR write wasn't ignored */
173         if (offset == UART_LCR) {
174                 int tries = 1000;
175                 while (tries--) {
176                         unsigned int lcr = p->serial_in(p, UART_LCR);
177                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
178                                 return;
179                         dw8250_force_idle(p);
180                         writel(value, p->membase + (UART_LCR << p->regshift));
181                 }
182                 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
183         }
184 }
185 
186 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
187 {
188         unsigned int value = readl(p->membase + (offset << p->regshift));
189 
190         return dw8250_modify_msr(p, offset, value);
191 }
192 
193 static int dw8250_handle_irq(struct uart_port *p)
194 {
195         struct dw8250_data *d = p->private_data;
196         unsigned int iir = p->serial_in(p, UART_IIR);
197 
198         if (serial8250_handle_irq(p, iir)) {
199                 return 1;
200         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
201                 /* Clear the USR */
202                 (void)p->serial_in(p, d->usr_reg);
203 
204                 return 1;
205         }
206 
207         return 0;
208 }
209 
210 static void
211 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
212 {
213         if (!state)
214                 pm_runtime_get_sync(port->dev);
215 
216         serial8250_do_pm(port, state, old);
217 
218         if (state)
219                 pm_runtime_put_sync_suspend(port->dev);
220 }
221 
222 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
223                                struct ktermios *old)
224 {
225         unsigned int baud = tty_termios_baud_rate(termios);
226         struct dw8250_data *d = p->private_data;
227         unsigned int rate;
228         int ret;
229 
230         if (IS_ERR(d->clk) || !old)
231                 goto out;
232 
233         /* Not requesting clock rates below 1.8432Mhz */
234         if (baud < 115200)
235                 baud = 115200;
236 
237         clk_disable_unprepare(d->clk);
238         rate = clk_round_rate(d->clk, baud * 16);
239         ret = clk_set_rate(d->clk, rate);
240         clk_prepare_enable(d->clk);
241 
242         if (!ret)
243                 p->uartclk = rate;
244 out:
245         serial8250_do_set_termios(p, termios, old);
246 }
247 
248 static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
249 {
250         return false;
251 }
252 
253 static void dw8250_setup_port(struct uart_8250_port *up)
254 {
255         struct uart_port        *p = &up->port;
256         u32                     reg = readl(p->membase + DW_UART_UCV);
257 
258         /*
259          * If the Component Version Register returns zero, we know that
260          * ADDITIONAL_FEATURES are not enabled. No need to go any further.
261          */
262         if (!reg)
263                 return;
264 
265         dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
266                 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
267 
268         reg = readl(p->membase + DW_UART_CPR);
269         if (!reg)
270                 return;
271 
272         /* Select the type based on fifo */
273         if (reg & DW_UART_CPR_FIFO_MODE) {
274                 p->type = PORT_16550A;
275                 p->flags |= UPF_FIXED_TYPE;
276                 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
277                 up->tx_loadsz = p->fifosize;
278                 up->capabilities = UART_CAP_FIFO;
279         }
280 
281         if (reg & DW_UART_CPR_AFCE_MODE)
282                 up->capabilities |= UART_CAP_AFE;
283 }
284 
285 static int dw8250_probe_of(struct uart_port *p,
286                            struct dw8250_data *data)
287 {
288         struct device_node      *np = p->dev->of_node;
289         struct uart_8250_port *up = up_to_u8250p(p);
290         u32                     val;
291         bool has_ucv = true;
292         int id;
293 
294 #ifdef CONFIG_64BIT
295         if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
296                 p->serial_in = dw8250_serial_inq;
297                 p->serial_out = dw8250_serial_outq;
298                 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
299                 p->type = PORT_OCTEON;
300                 data->usr_reg = 0x27;
301                 has_ucv = false;
302         } else
303 #endif
304         if (!of_property_read_u32(np, "reg-io-width", &val)) {
305                 switch (val) {
306                 case 1:
307                         break;
308                 case 4:
309                         p->iotype = UPIO_MEM32;
310                         p->serial_in = dw8250_serial_in32;
311                         p->serial_out = dw8250_serial_out32;
312                         break;
313                 default:
314                         dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
315                         return -EINVAL;
316                 }
317         }
318         if (has_ucv)
319                 dw8250_setup_port(up);
320 
321         /* if we have a valid fifosize, try hooking up DMA here */
322         if (p->fifosize) {
323                 up->dma = &data->dma;
324 
325                 up->dma->rxconf.src_maxburst = p->fifosize / 4;
326                 up->dma->txconf.dst_maxburst = p->fifosize / 4;
327         }
328 
329         if (!of_property_read_u32(np, "reg-shift", &val))
330                 p->regshift = val;
331 
332         /* get index of serial line, if found in DT aliases */
333         id = of_alias_get_id(np, "serial");
334         if (id >= 0)
335                 p->line = id;
336 
337         /* clock got configured through clk api, all done */
338         if (p->uartclk)
339                 return 0;
340 
341         /* try to find out clock frequency from DT as fallback */
342         if (of_property_read_u32(np, "clock-frequency", &val)) {
343                 dev_err(p->dev, "clk or clock-frequency not defined\n");
344                 return -EINVAL;
345         }
346         p->uartclk = val;
347 
348         return 0;
349 }
350 
351 static int dw8250_probe_acpi(struct uart_8250_port *up,
352                              struct dw8250_data *data)
353 {
354         struct uart_port *p = &up->port;
355 
356         dw8250_setup_port(up);
357 
358         p->iotype = UPIO_MEM32;
359         p->serial_in = dw8250_serial_in32;
360         p->serial_out = dw8250_serial_out32;
361         p->regshift = 2;
362 
363         up->dma = &data->dma;
364 
365         up->dma->rxconf.src_maxburst = p->fifosize / 4;
366         up->dma->txconf.dst_maxburst = p->fifosize / 4;
367 
368         up->port.set_termios = dw8250_set_termios;
369 
370         return 0;
371 }
372 
373 static int dw8250_probe(struct platform_device *pdev)
374 {
375         struct uart_8250_port uart = {};
376         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
377         struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
378         struct dw8250_data *data;
379         int err;
380 
381         if (!regs || !irq) {
382                 dev_err(&pdev->dev, "no registers/irq defined\n");
383                 return -EINVAL;
384         }
385 
386         spin_lock_init(&uart.port.lock);
387         uart.port.mapbase = regs->start;
388         uart.port.irq = irq->start;
389         uart.port.handle_irq = dw8250_handle_irq;
390         uart.port.pm = dw8250_do_pm;
391         uart.port.type = PORT_8250;
392         uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
393         uart.port.dev = &pdev->dev;
394 
395         uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
396                                          resource_size(regs));
397         if (!uart.port.membase)
398                 return -ENOMEM;
399 
400         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
401         if (!data)
402                 return -ENOMEM;
403 
404         data->usr_reg = DW_UART_USR;
405         data->clk = devm_clk_get(&pdev->dev, "baudclk");
406         if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
407                 data->clk = devm_clk_get(&pdev->dev, NULL);
408         if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
409                 return -EPROBE_DEFER;
410         if (!IS_ERR(data->clk)) {
411                 err = clk_prepare_enable(data->clk);
412                 if (err)
413                         dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n",
414                                  err);
415                 else
416                         uart.port.uartclk = clk_get_rate(data->clk);
417         }
418 
419         data->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
420         if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) {
421                 err = -EPROBE_DEFER;
422                 goto err_clk;
423         }
424         if (!IS_ERR(data->pclk)) {
425                 err = clk_prepare_enable(data->pclk);
426                 if (err) {
427                         dev_err(&pdev->dev, "could not enable apb_pclk\n");
428                         goto err_clk;
429                 }
430         }
431 
432         data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
433         if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
434                 err = -EPROBE_DEFER;
435                 goto err_pclk;
436         }
437         if (!IS_ERR(data->rst))
438                 reset_control_deassert(data->rst);
439 
440         data->dma.rx_param = data;
441         data->dma.tx_param = data;
442         data->dma.fn = dw8250_dma_filter;
443 
444         uart.port.iotype = UPIO_MEM;
445         uart.port.serial_in = dw8250_serial_in;
446         uart.port.serial_out = dw8250_serial_out;
447         uart.port.private_data = data;
448 
449         if (pdev->dev.of_node) {
450                 err = dw8250_probe_of(&uart.port, data);
451                 if (err)
452                         goto err_reset;
453         } else if (ACPI_HANDLE(&pdev->dev)) {
454                 err = dw8250_probe_acpi(&uart, data);
455                 if (err)
456                         goto err_reset;
457         } else {
458                 err = -ENODEV;
459                 goto err_reset;
460         }
461 
462         data->line = serial8250_register_8250_port(&uart);
463         if (data->line < 0) {
464                 err = data->line;
465                 goto err_reset;
466         }
467 
468         platform_set_drvdata(pdev, data);
469 
470         pm_runtime_set_active(&pdev->dev);
471         pm_runtime_enable(&pdev->dev);
472 
473         return 0;
474 
475 err_reset:
476         if (!IS_ERR(data->rst))
477                 reset_control_assert(data->rst);
478 
479 err_pclk:
480         if (!IS_ERR(data->pclk))
481                 clk_disable_unprepare(data->pclk);
482 
483 err_clk:
484         if (!IS_ERR(data->clk))
485                 clk_disable_unprepare(data->clk);
486 
487         return err;
488 }
489 
490 static int dw8250_remove(struct platform_device *pdev)
491 {
492         struct dw8250_data *data = platform_get_drvdata(pdev);
493 
494         pm_runtime_get_sync(&pdev->dev);
495 
496         serial8250_unregister_port(data->line);
497 
498         if (!IS_ERR(data->rst))
499                 reset_control_assert(data->rst);
500 
501         if (!IS_ERR(data->pclk))
502                 clk_disable_unprepare(data->pclk);
503 
504         if (!IS_ERR(data->clk))
505                 clk_disable_unprepare(data->clk);
506 
507         pm_runtime_disable(&pdev->dev);
508         pm_runtime_put_noidle(&pdev->dev);
509 
510         return 0;
511 }
512 
513 #ifdef CONFIG_PM_SLEEP
514 static int dw8250_suspend(struct device *dev)
515 {
516         struct dw8250_data *data = dev_get_drvdata(dev);
517 
518         serial8250_suspend_port(data->line);
519 
520         return 0;
521 }
522 
523 static int dw8250_resume(struct device *dev)
524 {
525         struct dw8250_data *data = dev_get_drvdata(dev);
526 
527         serial8250_resume_port(data->line);
528 
529         return 0;
530 }
531 #endif /* CONFIG_PM_SLEEP */
532 
533 #ifdef CONFIG_PM
534 static int dw8250_runtime_suspend(struct device *dev)
535 {
536         struct dw8250_data *data = dev_get_drvdata(dev);
537 
538         if (!IS_ERR(data->clk))
539                 clk_disable_unprepare(data->clk);
540 
541         if (!IS_ERR(data->pclk))
542                 clk_disable_unprepare(data->pclk);
543 
544         return 0;
545 }
546 
547 static int dw8250_runtime_resume(struct device *dev)
548 {
549         struct dw8250_data *data = dev_get_drvdata(dev);
550 
551         if (!IS_ERR(data->pclk))
552                 clk_prepare_enable(data->pclk);
553 
554         if (!IS_ERR(data->clk))
555                 clk_prepare_enable(data->clk);
556 
557         return 0;
558 }
559 #endif
560 
561 static const struct dev_pm_ops dw8250_pm_ops = {
562         SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
563         SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
564 };
565 
566 static const struct of_device_id dw8250_of_match[] = {
567         { .compatible = "snps,dw-apb-uart" },
568         { .compatible = "cavium,octeon-3860-uart" },
569         { /* Sentinel */ }
570 };
571 MODULE_DEVICE_TABLE(of, dw8250_of_match);
572 
573 static const struct acpi_device_id dw8250_acpi_match[] = {
574         { "INT33C4", 0 },
575         { "INT33C5", 0 },
576         { "INT3434", 0 },
577         { "INT3435", 0 },
578         { "80860F0A", 0 },
579         { "8086228A", 0 },
580         { },
581 };
582 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
583 
584 static struct platform_driver dw8250_platform_driver = {
585         .driver = {
586                 .name           = "dw-apb-uart",
587                 .pm             = &dw8250_pm_ops,
588                 .of_match_table = dw8250_of_match,
589                 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
590         },
591         .probe                  = dw8250_probe,
592         .remove                 = dw8250_remove,
593 };
594 
595 module_platform_driver(dw8250_platform_driver);
596 
597 MODULE_AUTHOR("Jamie Iles");
598 MODULE_LICENSE("GPL");
599 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
600 

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