Version:  2.0.40 2.2.26 2.4.37 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2

Linux/drivers/tty/serial/8250/8250_dw.c

  1 /*
  2  * Synopsys DesignWare 8250 driver.
  3  *
  4  * Copyright 2011 Picochip, Jamie Iles.
  5  * Copyright 2013 Intel Corporation
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  *
 12  * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
 13  * LCR is written whilst busy.  If it is, then a busy detect interrupt is
 14  * raised, the LCR needs to be rewritten and the uart status register read.
 15  */
 16 #include <linux/device.h>
 17 #include <linux/io.h>
 18 #include <linux/module.h>
 19 #include <linux/serial_8250.h>
 20 #include <linux/serial_reg.h>
 21 #include <linux/of.h>
 22 #include <linux/of_irq.h>
 23 #include <linux/of_platform.h>
 24 #include <linux/platform_device.h>
 25 #include <linux/slab.h>
 26 #include <linux/acpi.h>
 27 #include <linux/clk.h>
 28 #include <linux/reset.h>
 29 #include <linux/pm_runtime.h>
 30 
 31 #include <asm/byteorder.h>
 32 
 33 #include "8250.h"
 34 
 35 /* Offsets for the DesignWare specific registers */
 36 #define DW_UART_USR     0x1f /* UART Status Register */
 37 #define DW_UART_CPR     0xf4 /* Component Parameter Register */
 38 #define DW_UART_UCV     0xf8 /* UART Component Version */
 39 
 40 /* Component Parameter Register bits */
 41 #define DW_UART_CPR_ABP_DATA_WIDTH      (3 << 0)
 42 #define DW_UART_CPR_AFCE_MODE           (1 << 4)
 43 #define DW_UART_CPR_THRE_MODE           (1 << 5)
 44 #define DW_UART_CPR_SIR_MODE            (1 << 6)
 45 #define DW_UART_CPR_SIR_LP_MODE         (1 << 7)
 46 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
 47 #define DW_UART_CPR_FIFO_ACCESS         (1 << 9)
 48 #define DW_UART_CPR_FIFO_STAT           (1 << 10)
 49 #define DW_UART_CPR_SHADOW              (1 << 11)
 50 #define DW_UART_CPR_ENCODED_PARMS       (1 << 12)
 51 #define DW_UART_CPR_DMA_EXTRA           (1 << 13)
 52 #define DW_UART_CPR_FIFO_MODE           (0xff << 16)
 53 /* Helper for fifo size calculation */
 54 #define DW_UART_CPR_FIFO_SIZE(a)        (((a >> 16) & 0xff) * 16)
 55 
 56 
 57 struct dw8250_data {
 58         u8                      usr_reg;
 59         int                     last_mcr;
 60         int                     line;
 61         int                     msr_mask_on;
 62         int                     msr_mask_off;
 63         struct clk              *clk;
 64         struct clk              *pclk;
 65         struct reset_control    *rst;
 66         struct uart_8250_dma    dma;
 67 };
 68 
 69 #define BYT_PRV_CLK                     0x800
 70 #define BYT_PRV_CLK_EN                  (1 << 0)
 71 #define BYT_PRV_CLK_M_VAL_SHIFT         1
 72 #define BYT_PRV_CLK_N_VAL_SHIFT         16
 73 #define BYT_PRV_CLK_UPDATE              (1 << 31)
 74 
 75 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
 76 {
 77         struct dw8250_data *d = p->private_data;
 78 
 79         /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
 80         if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
 81                 value |= UART_MSR_CTS;
 82                 value &= ~UART_MSR_DCTS;
 83         }
 84 
 85         /* Override any modem control signals if needed */
 86         if (offset == UART_MSR) {
 87                 value |= d->msr_mask_on;
 88                 value &= ~d->msr_mask_off;
 89         }
 90 
 91         return value;
 92 }
 93 
 94 static void dw8250_force_idle(struct uart_port *p)
 95 {
 96         struct uart_8250_port *up = up_to_u8250p(p);
 97 
 98         serial8250_clear_and_reinit_fifos(up);
 99         (void)p->serial_in(p, UART_RX);
100 }
101 
102 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
103 {
104         struct dw8250_data *d = p->private_data;
105 
106         if (offset == UART_MCR)
107                 d->last_mcr = value;
108 
109         writeb(value, p->membase + (offset << p->regshift));
110 
111         /* Make sure LCR write wasn't ignored */
112         if (offset == UART_LCR) {
113                 int tries = 1000;
114                 while (tries--) {
115                         unsigned int lcr = p->serial_in(p, UART_LCR);
116                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
117                                 return;
118                         dw8250_force_idle(p);
119                         writeb(value, p->membase + (UART_LCR << p->regshift));
120                 }
121                 /*
122                  * FIXME: this deadlocks if port->lock is already held
123                  * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
124                  */
125         }
126 }
127 
128 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
129 {
130         unsigned int value = readb(p->membase + (offset << p->regshift));
131 
132         return dw8250_modify_msr(p, offset, value);
133 }
134 
135 #ifdef CONFIG_64BIT
136 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
137 {
138         unsigned int value;
139 
140         value = (u8)__raw_readq(p->membase + (offset << p->regshift));
141 
142         return dw8250_modify_msr(p, offset, value);
143 }
144 
145 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
146 {
147         struct dw8250_data *d = p->private_data;
148 
149         if (offset == UART_MCR)
150                 d->last_mcr = value;
151 
152         value &= 0xff;
153         __raw_writeq(value, p->membase + (offset << p->regshift));
154         /* Read back to ensure register write ordering. */
155         __raw_readq(p->membase + (UART_LCR << p->regshift));
156 
157         /* Make sure LCR write wasn't ignored */
158         if (offset == UART_LCR) {
159                 int tries = 1000;
160                 while (tries--) {
161                         unsigned int lcr = p->serial_in(p, UART_LCR);
162                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
163                                 return;
164                         dw8250_force_idle(p);
165                         __raw_writeq(value & 0xff,
166                                      p->membase + (UART_LCR << p->regshift));
167                 }
168                 /*
169                  * FIXME: this deadlocks if port->lock is already held
170                  * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
171                  */
172         }
173 }
174 #endif /* CONFIG_64BIT */
175 
176 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
177 {
178         struct dw8250_data *d = p->private_data;
179 
180         if (offset == UART_MCR)
181                 d->last_mcr = value;
182 
183         writel(value, p->membase + (offset << p->regshift));
184 
185         /* Make sure LCR write wasn't ignored */
186         if (offset == UART_LCR) {
187                 int tries = 1000;
188                 while (tries--) {
189                         unsigned int lcr = p->serial_in(p, UART_LCR);
190                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
191                                 return;
192                         dw8250_force_idle(p);
193                         writel(value, p->membase + (UART_LCR << p->regshift));
194                 }
195                 /*
196                  * FIXME: this deadlocks if port->lock is already held
197                  * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
198                  */
199         }
200 }
201 
202 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
203 {
204         unsigned int value = readl(p->membase + (offset << p->regshift));
205 
206         return dw8250_modify_msr(p, offset, value);
207 }
208 
209 static int dw8250_handle_irq(struct uart_port *p)
210 {
211         struct dw8250_data *d = p->private_data;
212         unsigned int iir = p->serial_in(p, UART_IIR);
213 
214         if (serial8250_handle_irq(p, iir)) {
215                 return 1;
216         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
217                 /* Clear the USR */
218                 (void)p->serial_in(p, d->usr_reg);
219 
220                 return 1;
221         }
222 
223         return 0;
224 }
225 
226 static void
227 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
228 {
229         if (!state)
230                 pm_runtime_get_sync(port->dev);
231 
232         serial8250_do_pm(port, state, old);
233 
234         if (state)
235                 pm_runtime_put_sync_suspend(port->dev);
236 }
237 
238 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
239                                struct ktermios *old)
240 {
241         unsigned int baud = tty_termios_baud_rate(termios);
242         struct dw8250_data *d = p->private_data;
243         unsigned int rate;
244         int ret;
245 
246         if (IS_ERR(d->clk) || !old)
247                 goto out;
248 
249         /* Not requesting clock rates below 1.8432Mhz */
250         if (baud < 115200)
251                 baud = 115200;
252 
253         clk_disable_unprepare(d->clk);
254         rate = clk_round_rate(d->clk, baud * 16);
255         ret = clk_set_rate(d->clk, rate);
256         clk_prepare_enable(d->clk);
257 
258         if (!ret)
259                 p->uartclk = rate;
260 out:
261         serial8250_do_set_termios(p, termios, old);
262 }
263 
264 static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
265 {
266         return false;
267 }
268 
269 static void dw8250_setup_port(struct uart_8250_port *up)
270 {
271         struct uart_port        *p = &up->port;
272         u32                     reg = readl(p->membase + DW_UART_UCV);
273 
274         /*
275          * If the Component Version Register returns zero, we know that
276          * ADDITIONAL_FEATURES are not enabled. No need to go any further.
277          */
278         if (!reg)
279                 return;
280 
281         dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
282                 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
283 
284         reg = readl(p->membase + DW_UART_CPR);
285         if (!reg)
286                 return;
287 
288         /* Select the type based on fifo */
289         if (reg & DW_UART_CPR_FIFO_MODE) {
290                 p->type = PORT_16550A;
291                 p->flags |= UPF_FIXED_TYPE;
292                 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
293                 up->tx_loadsz = p->fifosize;
294                 up->capabilities = UART_CAP_FIFO;
295         }
296 
297         if (reg & DW_UART_CPR_AFCE_MODE)
298                 up->capabilities |= UART_CAP_AFE;
299 }
300 
301 static int dw8250_probe_of(struct uart_port *p,
302                            struct dw8250_data *data)
303 {
304         struct device_node      *np = p->dev->of_node;
305         struct uart_8250_port *up = up_to_u8250p(p);
306         u32                     val;
307         bool has_ucv = true;
308         int id;
309 
310 #ifdef CONFIG_64BIT
311         if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
312                 p->serial_in = dw8250_serial_inq;
313                 p->serial_out = dw8250_serial_outq;
314                 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
315                 p->type = PORT_OCTEON;
316                 data->usr_reg = 0x27;
317                 has_ucv = false;
318         } else
319 #endif
320         if (!of_property_read_u32(np, "reg-io-width", &val)) {
321                 switch (val) {
322                 case 1:
323                         break;
324                 case 4:
325                         p->iotype = UPIO_MEM32;
326                         p->serial_in = dw8250_serial_in32;
327                         p->serial_out = dw8250_serial_out32;
328                         break;
329                 default:
330                         dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
331                         return -EINVAL;
332                 }
333         }
334         if (has_ucv)
335                 dw8250_setup_port(up);
336 
337         /* if we have a valid fifosize, try hooking up DMA here */
338         if (p->fifosize) {
339                 up->dma = &data->dma;
340 
341                 up->dma->rxconf.src_maxburst = p->fifosize / 4;
342                 up->dma->txconf.dst_maxburst = p->fifosize / 4;
343         }
344 
345         if (!of_property_read_u32(np, "reg-shift", &val))
346                 p->regshift = val;
347 
348         /* get index of serial line, if found in DT aliases */
349         id = of_alias_get_id(np, "serial");
350         if (id >= 0)
351                 p->line = id;
352 
353         if (of_property_read_bool(np, "dcd-override")) {
354                 /* Always report DCD as active */
355                 data->msr_mask_on |= UART_MSR_DCD;
356                 data->msr_mask_off |= UART_MSR_DDCD;
357         }
358 
359         if (of_property_read_bool(np, "dsr-override")) {
360                 /* Always report DSR as active */
361                 data->msr_mask_on |= UART_MSR_DSR;
362                 data->msr_mask_off |= UART_MSR_DDSR;
363         }
364 
365         if (of_property_read_bool(np, "cts-override")) {
366                 /* Always report CTS as active */
367                 data->msr_mask_on |= UART_MSR_CTS;
368                 data->msr_mask_off |= UART_MSR_DCTS;
369         }
370 
371         if (of_property_read_bool(np, "ri-override")) {
372                 /* Always report Ring indicator as inactive */
373                 data->msr_mask_off |= UART_MSR_RI;
374                 data->msr_mask_off |= UART_MSR_TERI;
375         }
376 
377         return 0;
378 }
379 
380 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
381 {
382         struct device *dev = param;
383 
384         if (dev != chan->device->dev->parent)
385                 return false;
386 
387         return true;
388 }
389 
390 static int dw8250_probe_acpi(struct uart_8250_port *up,
391                              struct dw8250_data *data)
392 {
393         struct uart_port *p = &up->port;
394 
395         dw8250_setup_port(up);
396 
397         p->iotype = UPIO_MEM32;
398         p->serial_in = dw8250_serial_in32;
399         p->serial_out = dw8250_serial_out32;
400         p->regshift = 2;
401 
402         /* Platforms with iDMA */
403         if (platform_get_resource_byname(to_platform_device(up->port.dev),
404                                          IORESOURCE_MEM, "lpss_priv")) {
405                 data->dma.rx_param = up->port.dev->parent;
406                 data->dma.tx_param = up->port.dev->parent;
407                 data->dma.fn = dw8250_idma_filter;
408         }
409 
410         up->dma = &data->dma;
411         up->dma->rxconf.src_maxburst = p->fifosize / 4;
412         up->dma->txconf.dst_maxburst = p->fifosize / 4;
413 
414         up->port.set_termios = dw8250_set_termios;
415 
416         return 0;
417 }
418 
419 static int dw8250_probe(struct platform_device *pdev)
420 {
421         struct uart_8250_port uart = {};
422         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
423         int irq = platform_get_irq(pdev, 0);
424         struct dw8250_data *data;
425         int err;
426 
427         if (!regs) {
428                 dev_err(&pdev->dev, "no registers defined\n");
429                 return -EINVAL;
430         }
431 
432         if (irq < 0) {
433                 if (irq != -EPROBE_DEFER)
434                         dev_err(&pdev->dev, "cannot get irq\n");
435                 return irq;
436         }
437 
438         spin_lock_init(&uart.port.lock);
439         uart.port.mapbase = regs->start;
440         uart.port.irq = irq;
441         uart.port.handle_irq = dw8250_handle_irq;
442         uart.port.pm = dw8250_do_pm;
443         uart.port.type = PORT_8250;
444         uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
445         uart.port.dev = &pdev->dev;
446 
447         uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
448                                          resource_size(regs));
449         if (!uart.port.membase)
450                 return -ENOMEM;
451 
452         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
453         if (!data)
454                 return -ENOMEM;
455 
456         data->usr_reg = DW_UART_USR;
457 
458         /* Always ask for fixed clock rate from a property. */
459         device_property_read_u32(&pdev->dev, "clock-frequency",
460                                  &uart.port.uartclk);
461 
462         /* If there is separate baudclk, get the rate from it. */
463         data->clk = devm_clk_get(&pdev->dev, "baudclk");
464         if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
465                 data->clk = devm_clk_get(&pdev->dev, NULL);
466         if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
467                 return -EPROBE_DEFER;
468         if (!IS_ERR_OR_NULL(data->clk)) {
469                 err = clk_prepare_enable(data->clk);
470                 if (err)
471                         dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n",
472                                  err);
473                 else
474                         uart.port.uartclk = clk_get_rate(data->clk);
475         }
476 
477         /* If no clock rate is defined, fail. */
478         if (!uart.port.uartclk) {
479                 dev_err(&pdev->dev, "clock rate not defined\n");
480                 return -EINVAL;
481         }
482 
483         data->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
484         if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) {
485                 err = -EPROBE_DEFER;
486                 goto err_clk;
487         }
488         if (!IS_ERR(data->pclk)) {
489                 err = clk_prepare_enable(data->pclk);
490                 if (err) {
491                         dev_err(&pdev->dev, "could not enable apb_pclk\n");
492                         goto err_clk;
493                 }
494         }
495 
496         data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
497         if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
498                 err = -EPROBE_DEFER;
499                 goto err_pclk;
500         }
501         if (!IS_ERR(data->rst))
502                 reset_control_deassert(data->rst);
503 
504         data->dma.rx_param = data;
505         data->dma.tx_param = data;
506         data->dma.fn = dw8250_dma_filter;
507 
508         uart.port.iotype = UPIO_MEM;
509         uart.port.serial_in = dw8250_serial_in;
510         uart.port.serial_out = dw8250_serial_out;
511         uart.port.private_data = data;
512 
513         if (pdev->dev.of_node) {
514                 err = dw8250_probe_of(&uart.port, data);
515                 if (err)
516                         goto err_reset;
517         } else if (ACPI_HANDLE(&pdev->dev)) {
518                 err = dw8250_probe_acpi(&uart, data);
519                 if (err)
520                         goto err_reset;
521         } else {
522                 err = -ENODEV;
523                 goto err_reset;
524         }
525 
526         data->line = serial8250_register_8250_port(&uart);
527         if (data->line < 0) {
528                 err = data->line;
529                 goto err_reset;
530         }
531 
532         platform_set_drvdata(pdev, data);
533 
534         pm_runtime_set_active(&pdev->dev);
535         pm_runtime_enable(&pdev->dev);
536 
537         return 0;
538 
539 err_reset:
540         if (!IS_ERR(data->rst))
541                 reset_control_assert(data->rst);
542 
543 err_pclk:
544         if (!IS_ERR(data->pclk))
545                 clk_disable_unprepare(data->pclk);
546 
547 err_clk:
548         if (!IS_ERR(data->clk))
549                 clk_disable_unprepare(data->clk);
550 
551         return err;
552 }
553 
554 static int dw8250_remove(struct platform_device *pdev)
555 {
556         struct dw8250_data *data = platform_get_drvdata(pdev);
557 
558         pm_runtime_get_sync(&pdev->dev);
559 
560         serial8250_unregister_port(data->line);
561 
562         if (!IS_ERR(data->rst))
563                 reset_control_assert(data->rst);
564 
565         if (!IS_ERR(data->pclk))
566                 clk_disable_unprepare(data->pclk);
567 
568         if (!IS_ERR(data->clk))
569                 clk_disable_unprepare(data->clk);
570 
571         pm_runtime_disable(&pdev->dev);
572         pm_runtime_put_noidle(&pdev->dev);
573 
574         return 0;
575 }
576 
577 #ifdef CONFIG_PM_SLEEP
578 static int dw8250_suspend(struct device *dev)
579 {
580         struct dw8250_data *data = dev_get_drvdata(dev);
581 
582         serial8250_suspend_port(data->line);
583 
584         return 0;
585 }
586 
587 static int dw8250_resume(struct device *dev)
588 {
589         struct dw8250_data *data = dev_get_drvdata(dev);
590 
591         serial8250_resume_port(data->line);
592 
593         return 0;
594 }
595 #endif /* CONFIG_PM_SLEEP */
596 
597 #ifdef CONFIG_PM
598 static int dw8250_runtime_suspend(struct device *dev)
599 {
600         struct dw8250_data *data = dev_get_drvdata(dev);
601 
602         if (!IS_ERR(data->clk))
603                 clk_disable_unprepare(data->clk);
604 
605         if (!IS_ERR(data->pclk))
606                 clk_disable_unprepare(data->pclk);
607 
608         return 0;
609 }
610 
611 static int dw8250_runtime_resume(struct device *dev)
612 {
613         struct dw8250_data *data = dev_get_drvdata(dev);
614 
615         if (!IS_ERR(data->pclk))
616                 clk_prepare_enable(data->pclk);
617 
618         if (!IS_ERR(data->clk))
619                 clk_prepare_enable(data->clk);
620 
621         return 0;
622 }
623 #endif
624 
625 static const struct dev_pm_ops dw8250_pm_ops = {
626         SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
627         SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
628 };
629 
630 static const struct of_device_id dw8250_of_match[] = {
631         { .compatible = "snps,dw-apb-uart" },
632         { .compatible = "cavium,octeon-3860-uart" },
633         { /* Sentinel */ }
634 };
635 MODULE_DEVICE_TABLE(of, dw8250_of_match);
636 
637 static const struct acpi_device_id dw8250_acpi_match[] = {
638         { "INT33C4", 0 },
639         { "INT33C5", 0 },
640         { "INT3434", 0 },
641         { "INT3435", 0 },
642         { "80860F0A", 0 },
643         { "8086228A", 0 },
644         { "APMC0D08", 0},
645         { "AMD0020", 0 },
646         { },
647 };
648 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
649 
650 static struct platform_driver dw8250_platform_driver = {
651         .driver = {
652                 .name           = "dw-apb-uart",
653                 .pm             = &dw8250_pm_ops,
654                 .of_match_table = dw8250_of_match,
655                 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
656         },
657         .probe                  = dw8250_probe,
658         .remove                 = dw8250_remove,
659 };
660 
661 module_platform_driver(dw8250_platform_driver);
662 
663 MODULE_AUTHOR("Jamie Iles");
664 MODULE_LICENSE("GPL");
665 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
666 MODULE_ALIAS("platform:dw-apb-uart");
667 

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