Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/tty/serial/8250/8250_core.c

  1 /*
  2  *  Driver for 8250/16550-type serial ports
  3  *
  4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  5  *
  6  *  Copyright (C) 2001 Russell King.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * A note about mapbase / membase
 14  *
 15  *  mapbase is the physical address of the IO port.
 16  *  membase is an 'ioremapped' cookie.
 17  */
 18 
 19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 20 #define SUPPORT_SYSRQ
 21 #endif
 22 
 23 #include <linux/module.h>
 24 #include <linux/moduleparam.h>
 25 #include <linux/ioport.h>
 26 #include <linux/init.h>
 27 #include <linux/console.h>
 28 #include <linux/sysrq.h>
 29 #include <linux/delay.h>
 30 #include <linux/platform_device.h>
 31 #include <linux/tty.h>
 32 #include <linux/ratelimit.h>
 33 #include <linux/tty_flip.h>
 34 #include <linux/serial_reg.h>
 35 #include <linux/serial_core.h>
 36 #include <linux/serial.h>
 37 #include <linux/serial_8250.h>
 38 #include <linux/nmi.h>
 39 #include <linux/mutex.h>
 40 #include <linux/slab.h>
 41 #ifdef CONFIG_SPARC
 42 #include <linux/sunserialcore.h>
 43 #endif
 44 
 45 #include <asm/io.h>
 46 #include <asm/irq.h>
 47 
 48 #include "8250.h"
 49 
 50 /*
 51  * Configuration:
 52  *   share_irqs - whether we pass IRQF_SHARED to request_irq().  This option
 53  *                is unsafe when used on edge-triggered interrupts.
 54  */
 55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
 56 
 57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
 58 
 59 static struct uart_driver serial8250_reg;
 60 
 61 static int serial_index(struct uart_port *port)
 62 {
 63         return (serial8250_reg.minor - 64) + port->line;
 64 }
 65 
 66 static unsigned int skip_txen_test; /* force skip of txen test at init time */
 67 
 68 /*
 69  * Debugging.
 70  */
 71 #if 0
 72 #define DEBUG_AUTOCONF(fmt...)  printk(fmt)
 73 #else
 74 #define DEBUG_AUTOCONF(fmt...)  do { } while (0)
 75 #endif
 76 
 77 #if 0
 78 #define DEBUG_INTR(fmt...)      printk(fmt)
 79 #else
 80 #define DEBUG_INTR(fmt...)      do { } while (0)
 81 #endif
 82 
 83 #define PASS_LIMIT      512
 84 
 85 #define BOTH_EMPTY      (UART_LSR_TEMT | UART_LSR_THRE)
 86 
 87 
 88 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
 89 #define CONFIG_SERIAL_DETECT_IRQ 1
 90 #endif
 91 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
 92 #define CONFIG_SERIAL_MANY_PORTS 1
 93 #endif
 94 
 95 /*
 96  * HUB6 is always on.  This will be removed once the header
 97  * files have been cleaned.
 98  */
 99 #define CONFIG_HUB6 1
100 
101 #include <asm/serial.h>
102 /*
103  * SERIAL_PORT_DFNS tells us about built-in ports that have no
104  * standard enumeration mechanism.   Platforms that can find all
105  * serial ports via mechanisms like ACPI or PCI need not supply it.
106  */
107 #ifndef SERIAL_PORT_DFNS
108 #define SERIAL_PORT_DFNS
109 #endif
110 
111 static const struct old_serial_port old_serial_port[] = {
112         SERIAL_PORT_DFNS /* defined in asm/serial.h */
113 };
114 
115 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
116 
117 #ifdef CONFIG_SERIAL_8250_RSA
118 
119 #define PORT_RSA_MAX 4
120 static unsigned long probe_rsa[PORT_RSA_MAX];
121 static unsigned int probe_rsa_count;
122 #endif /* CONFIG_SERIAL_8250_RSA  */
123 
124 struct irq_info {
125         struct                  hlist_node node;
126         int                     irq;
127         spinlock_t              lock;   /* Protects list not the hash */
128         struct list_head        *head;
129 };
130 
131 #define NR_IRQ_HASH             32      /* Can be adjusted later */
132 static struct hlist_head irq_lists[NR_IRQ_HASH];
133 static DEFINE_MUTEX(hash_mutex);        /* Used to walk the hash */
134 
135 /*
136  * Here we define the default xmit fifo size used for each type of UART.
137  */
138 static const struct serial8250_config uart_config[] = {
139         [PORT_UNKNOWN] = {
140                 .name           = "unknown",
141                 .fifo_size      = 1,
142                 .tx_loadsz      = 1,
143         },
144         [PORT_8250] = {
145                 .name           = "8250",
146                 .fifo_size      = 1,
147                 .tx_loadsz      = 1,
148         },
149         [PORT_16450] = {
150                 .name           = "16450",
151                 .fifo_size      = 1,
152                 .tx_loadsz      = 1,
153         },
154         [PORT_16550] = {
155                 .name           = "16550",
156                 .fifo_size      = 1,
157                 .tx_loadsz      = 1,
158         },
159         [PORT_16550A] = {
160                 .name           = "16550A",
161                 .fifo_size      = 16,
162                 .tx_loadsz      = 16,
163                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164                 .flags          = UART_CAP_FIFO,
165         },
166         [PORT_CIRRUS] = {
167                 .name           = "Cirrus",
168                 .fifo_size      = 1,
169                 .tx_loadsz      = 1,
170         },
171         [PORT_16650] = {
172                 .name           = "ST16650",
173                 .fifo_size      = 1,
174                 .tx_loadsz      = 1,
175                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
176         },
177         [PORT_16650V2] = {
178                 .name           = "ST16650V2",
179                 .fifo_size      = 32,
180                 .tx_loadsz      = 16,
181                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
182                                   UART_FCR_T_TRIG_00,
183                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184         },
185         [PORT_16750] = {
186                 .name           = "TI16750",
187                 .fifo_size      = 64,
188                 .tx_loadsz      = 64,
189                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
190                                   UART_FCR7_64BYTE,
191                 .flags          = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
192         },
193         [PORT_STARTECH] = {
194                 .name           = "Startech",
195                 .fifo_size      = 1,
196                 .tx_loadsz      = 1,
197         },
198         [PORT_16C950] = {
199                 .name           = "16C950/954",
200                 .fifo_size      = 128,
201                 .tx_loadsz      = 128,
202                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203                 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204                 .flags          = UART_CAP_FIFO | UART_CAP_SLEEP,
205         },
206         [PORT_16654] = {
207                 .name           = "ST16654",
208                 .fifo_size      = 64,
209                 .tx_loadsz      = 32,
210                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
211                                   UART_FCR_T_TRIG_10,
212                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
213         },
214         [PORT_16850] = {
215                 .name           = "XR16850",
216                 .fifo_size      = 128,
217                 .tx_loadsz      = 128,
218                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220         },
221         [PORT_RSA] = {
222                 .name           = "RSA",
223                 .fifo_size      = 2048,
224                 .tx_loadsz      = 2048,
225                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226                 .flags          = UART_CAP_FIFO,
227         },
228         [PORT_NS16550A] = {
229                 .name           = "NS16550A",
230                 .fifo_size      = 16,
231                 .tx_loadsz      = 16,
232                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233                 .flags          = UART_CAP_FIFO | UART_NATSEMI,
234         },
235         [PORT_XSCALE] = {
236                 .name           = "XScale",
237                 .fifo_size      = 32,
238                 .tx_loadsz      = 32,
239                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240                 .flags          = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
241         },
242         [PORT_OCTEON] = {
243                 .name           = "OCTEON",
244                 .fifo_size      = 64,
245                 .tx_loadsz      = 64,
246                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
247                 .flags          = UART_CAP_FIFO,
248         },
249         [PORT_AR7] = {
250                 .name           = "AR7",
251                 .fifo_size      = 16,
252                 .tx_loadsz      = 16,
253                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
254                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
255         },
256         [PORT_U6_16550A] = {
257                 .name           = "U6_16550A",
258                 .fifo_size      = 64,
259                 .tx_loadsz      = 64,
260                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
261                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
262         },
263         [PORT_TEGRA] = {
264                 .name           = "Tegra",
265                 .fifo_size      = 32,
266                 .tx_loadsz      = 8,
267                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
268                                   UART_FCR_T_TRIG_01,
269                 .flags          = UART_CAP_FIFO | UART_CAP_RTOIE,
270         },
271         [PORT_XR17D15X] = {
272                 .name           = "XR17D15X",
273                 .fifo_size      = 64,
274                 .tx_loadsz      = 64,
275                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
276                 .flags          = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
277                                   UART_CAP_SLEEP,
278         },
279         [PORT_XR17V35X] = {
280                 .name           = "XR17V35X",
281                 .fifo_size      = 256,
282                 .tx_loadsz      = 256,
283                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
284                                   UART_FCR_T_TRIG_11,
285                 .flags          = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
286                                   UART_CAP_SLEEP,
287         },
288         [PORT_LPC3220] = {
289                 .name           = "LPC3220",
290                 .fifo_size      = 64,
291                 .tx_loadsz      = 32,
292                 .fcr            = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
293                                   UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
294                 .flags          = UART_CAP_FIFO,
295         },
296         [PORT_BRCM_TRUMANAGE] = {
297                 .name           = "TruManage",
298                 .fifo_size      = 1,
299                 .tx_loadsz      = 1024,
300                 .flags          = UART_CAP_HFIFO,
301         },
302         [PORT_8250_CIR] = {
303                 .name           = "CIR port"
304         },
305         [PORT_ALTR_16550_F32] = {
306                 .name           = "Altera 16550 FIFO32",
307                 .fifo_size      = 32,
308                 .tx_loadsz      = 32,
309                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
310                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
311         },
312         [PORT_ALTR_16550_F64] = {
313                 .name           = "Altera 16550 FIFO64",
314                 .fifo_size      = 64,
315                 .tx_loadsz      = 64,
316                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
317                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
318         },
319         [PORT_ALTR_16550_F128] = {
320                 .name           = "Altera 16550 FIFO128",
321                 .fifo_size      = 128,
322                 .tx_loadsz      = 128,
323                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
324                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
325         },
326 };
327 
328 /* Uart divisor latch read */
329 static int default_serial_dl_read(struct uart_8250_port *up)
330 {
331         return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
332 }
333 
334 /* Uart divisor latch write */
335 static void default_serial_dl_write(struct uart_8250_port *up, int value)
336 {
337         serial_out(up, UART_DLL, value & 0xff);
338         serial_out(up, UART_DLM, value >> 8 & 0xff);
339 }
340 
341 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
342 
343 /* Au1x00/RT288x UART hardware has a weird register layout */
344 static const u8 au_io_in_map[] = {
345         [UART_RX]  = 0,
346         [UART_IER] = 2,
347         [UART_IIR] = 3,
348         [UART_LCR] = 5,
349         [UART_MCR] = 6,
350         [UART_LSR] = 7,
351         [UART_MSR] = 8,
352 };
353 
354 static const u8 au_io_out_map[] = {
355         [UART_TX]  = 1,
356         [UART_IER] = 2,
357         [UART_FCR] = 4,
358         [UART_LCR] = 5,
359         [UART_MCR] = 6,
360 };
361 
362 static unsigned int au_serial_in(struct uart_port *p, int offset)
363 {
364         offset = au_io_in_map[offset] << p->regshift;
365         return __raw_readl(p->membase + offset);
366 }
367 
368 static void au_serial_out(struct uart_port *p, int offset, int value)
369 {
370         offset = au_io_out_map[offset] << p->regshift;
371         __raw_writel(value, p->membase + offset);
372 }
373 
374 /* Au1x00 haven't got a standard divisor latch */
375 static int au_serial_dl_read(struct uart_8250_port *up)
376 {
377         return __raw_readl(up->port.membase + 0x28);
378 }
379 
380 static void au_serial_dl_write(struct uart_8250_port *up, int value)
381 {
382         __raw_writel(value, up->port.membase + 0x28);
383 }
384 
385 #endif
386 
387 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
388 {
389         offset = offset << p->regshift;
390         outb(p->hub6 - 1 + offset, p->iobase);
391         return inb(p->iobase + 1);
392 }
393 
394 static void hub6_serial_out(struct uart_port *p, int offset, int value)
395 {
396         offset = offset << p->regshift;
397         outb(p->hub6 - 1 + offset, p->iobase);
398         outb(value, p->iobase + 1);
399 }
400 
401 static unsigned int mem_serial_in(struct uart_port *p, int offset)
402 {
403         offset = offset << p->regshift;
404         return readb(p->membase + offset);
405 }
406 
407 static void mem_serial_out(struct uart_port *p, int offset, int value)
408 {
409         offset = offset << p->regshift;
410         writeb(value, p->membase + offset);
411 }
412 
413 static void mem32_serial_out(struct uart_port *p, int offset, int value)
414 {
415         offset = offset << p->regshift;
416         writel(value, p->membase + offset);
417 }
418 
419 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
420 {
421         offset = offset << p->regshift;
422         return readl(p->membase + offset);
423 }
424 
425 static unsigned int io_serial_in(struct uart_port *p, int offset)
426 {
427         offset = offset << p->regshift;
428         return inb(p->iobase + offset);
429 }
430 
431 static void io_serial_out(struct uart_port *p, int offset, int value)
432 {
433         offset = offset << p->regshift;
434         outb(value, p->iobase + offset);
435 }
436 
437 static int serial8250_default_handle_irq(struct uart_port *port);
438 static int exar_handle_irq(struct uart_port *port);
439 
440 static void set_io_from_upio(struct uart_port *p)
441 {
442         struct uart_8250_port *up =
443                 container_of(p, struct uart_8250_port, port);
444 
445         up->dl_read = default_serial_dl_read;
446         up->dl_write = default_serial_dl_write;
447 
448         switch (p->iotype) {
449         case UPIO_HUB6:
450                 p->serial_in = hub6_serial_in;
451                 p->serial_out = hub6_serial_out;
452                 break;
453 
454         case UPIO_MEM:
455                 p->serial_in = mem_serial_in;
456                 p->serial_out = mem_serial_out;
457                 break;
458 
459         case UPIO_MEM32:
460                 p->serial_in = mem32_serial_in;
461                 p->serial_out = mem32_serial_out;
462                 break;
463 
464 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
465         case UPIO_AU:
466                 p->serial_in = au_serial_in;
467                 p->serial_out = au_serial_out;
468                 up->dl_read = au_serial_dl_read;
469                 up->dl_write = au_serial_dl_write;
470                 break;
471 #endif
472 
473         default:
474                 p->serial_in = io_serial_in;
475                 p->serial_out = io_serial_out;
476                 break;
477         }
478         /* Remember loaded iotype */
479         up->cur_iotype = p->iotype;
480         p->handle_irq = serial8250_default_handle_irq;
481 }
482 
483 static void
484 serial_port_out_sync(struct uart_port *p, int offset, int value)
485 {
486         switch (p->iotype) {
487         case UPIO_MEM:
488         case UPIO_MEM32:
489         case UPIO_AU:
490                 p->serial_out(p, offset, value);
491                 p->serial_in(p, UART_LCR);      /* safe, no side-effects */
492                 break;
493         default:
494                 p->serial_out(p, offset, value);
495         }
496 }
497 
498 /*
499  * For the 16C950
500  */
501 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
502 {
503         serial_out(up, UART_SCR, offset);
504         serial_out(up, UART_ICR, value);
505 }
506 
507 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
508 {
509         unsigned int value;
510 
511         serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
512         serial_out(up, UART_SCR, offset);
513         value = serial_in(up, UART_ICR);
514         serial_icr_write(up, UART_ACR, up->acr);
515 
516         return value;
517 }
518 
519 /*
520  * FIFO support.
521  */
522 static void serial8250_clear_fifos(struct uart_8250_port *p)
523 {
524         if (p->capabilities & UART_CAP_FIFO) {
525                 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
526                 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
527                                UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
528                 serial_out(p, UART_FCR, 0);
529         }
530 }
531 
532 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
533 {
534         unsigned char fcr;
535 
536         serial8250_clear_fifos(p);
537         fcr = uart_config[p->port.type].fcr;
538         serial_out(p, UART_FCR, fcr);
539 }
540 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
541 
542 /*
543  * IER sleep support.  UARTs which have EFRs need the "extended
544  * capability" bit enabled.  Note that on XR16C850s, we need to
545  * reset LCR to write to IER.
546  */
547 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
548 {
549         /*
550          * Exar UARTs have a SLEEP register that enables or disables
551          * each UART to enter sleep mode separately.  On the XR17V35x the
552          * register is accessible to each UART at the UART_EXAR_SLEEP
553          * offset but the UART channel may only write to the corresponding
554          * bit.
555          */
556         if ((p->port.type == PORT_XR17V35X) ||
557            (p->port.type == PORT_XR17D15X)) {
558                 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
559                 return;
560         }
561 
562         if (p->capabilities & UART_CAP_SLEEP) {
563                 if (p->capabilities & UART_CAP_EFR) {
564                         serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
565                         serial_out(p, UART_EFR, UART_EFR_ECB);
566                         serial_out(p, UART_LCR, 0);
567                 }
568                 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
569                 if (p->capabilities & UART_CAP_EFR) {
570                         serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
571                         serial_out(p, UART_EFR, 0);
572                         serial_out(p, UART_LCR, 0);
573                 }
574         }
575 }
576 
577 #ifdef CONFIG_SERIAL_8250_RSA
578 /*
579  * Attempts to turn on the RSA FIFO.  Returns zero on failure.
580  * We set the port uart clock rate if we succeed.
581  */
582 static int __enable_rsa(struct uart_8250_port *up)
583 {
584         unsigned char mode;
585         int result;
586 
587         mode = serial_in(up, UART_RSA_MSR);
588         result = mode & UART_RSA_MSR_FIFO;
589 
590         if (!result) {
591                 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
592                 mode = serial_in(up, UART_RSA_MSR);
593                 result = mode & UART_RSA_MSR_FIFO;
594         }
595 
596         if (result)
597                 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
598 
599         return result;
600 }
601 
602 static void enable_rsa(struct uart_8250_port *up)
603 {
604         if (up->port.type == PORT_RSA) {
605                 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
606                         spin_lock_irq(&up->port.lock);
607                         __enable_rsa(up);
608                         spin_unlock_irq(&up->port.lock);
609                 }
610                 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
611                         serial_out(up, UART_RSA_FRR, 0);
612         }
613 }
614 
615 /*
616  * Attempts to turn off the RSA FIFO.  Returns zero on failure.
617  * It is unknown why interrupts were disabled in here.  However,
618  * the caller is expected to preserve this behaviour by grabbing
619  * the spinlock before calling this function.
620  */
621 static void disable_rsa(struct uart_8250_port *up)
622 {
623         unsigned char mode;
624         int result;
625 
626         if (up->port.type == PORT_RSA &&
627             up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
628                 spin_lock_irq(&up->port.lock);
629 
630                 mode = serial_in(up, UART_RSA_MSR);
631                 result = !(mode & UART_RSA_MSR_FIFO);
632 
633                 if (!result) {
634                         serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
635                         mode = serial_in(up, UART_RSA_MSR);
636                         result = !(mode & UART_RSA_MSR_FIFO);
637                 }
638 
639                 if (result)
640                         up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
641                 spin_unlock_irq(&up->port.lock);
642         }
643 }
644 #endif /* CONFIG_SERIAL_8250_RSA */
645 
646 /*
647  * This is a quickie test to see how big the FIFO is.
648  * It doesn't work at all the time, more's the pity.
649  */
650 static int size_fifo(struct uart_8250_port *up)
651 {
652         unsigned char old_fcr, old_mcr, old_lcr;
653         unsigned short old_dl;
654         int count;
655 
656         old_lcr = serial_in(up, UART_LCR);
657         serial_out(up, UART_LCR, 0);
658         old_fcr = serial_in(up, UART_FCR);
659         old_mcr = serial_in(up, UART_MCR);
660         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
661                     UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
662         serial_out(up, UART_MCR, UART_MCR_LOOP);
663         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
664         old_dl = serial_dl_read(up);
665         serial_dl_write(up, 0x0001);
666         serial_out(up, UART_LCR, 0x03);
667         for (count = 0; count < 256; count++)
668                 serial_out(up, UART_TX, count);
669         mdelay(20);/* FIXME - schedule_timeout */
670         for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
671              (count < 256); count++)
672                 serial_in(up, UART_RX);
673         serial_out(up, UART_FCR, old_fcr);
674         serial_out(up, UART_MCR, old_mcr);
675         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
676         serial_dl_write(up, old_dl);
677         serial_out(up, UART_LCR, old_lcr);
678 
679         return count;
680 }
681 
682 /*
683  * Read UART ID using the divisor method - set DLL and DLM to zero
684  * and the revision will be in DLL and device type in DLM.  We
685  * preserve the device state across this.
686  */
687 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
688 {
689         unsigned char old_dll, old_dlm, old_lcr;
690         unsigned int id;
691 
692         old_lcr = serial_in(p, UART_LCR);
693         serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
694 
695         old_dll = serial_in(p, UART_DLL);
696         old_dlm = serial_in(p, UART_DLM);
697 
698         serial_out(p, UART_DLL, 0);
699         serial_out(p, UART_DLM, 0);
700 
701         id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
702 
703         serial_out(p, UART_DLL, old_dll);
704         serial_out(p, UART_DLM, old_dlm);
705         serial_out(p, UART_LCR, old_lcr);
706 
707         return id;
708 }
709 
710 /*
711  * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
712  * When this function is called we know it is at least a StarTech
713  * 16650 V2, but it might be one of several StarTech UARTs, or one of
714  * its clones.  (We treat the broken original StarTech 16650 V1 as a
715  * 16550, and why not?  Startech doesn't seem to even acknowledge its
716  * existence.)
717  *
718  * What evil have men's minds wrought...
719  */
720 static void autoconfig_has_efr(struct uart_8250_port *up)
721 {
722         unsigned int id1, id2, id3, rev;
723 
724         /*
725          * Everything with an EFR has SLEEP
726          */
727         up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
728 
729         /*
730          * First we check to see if it's an Oxford Semiconductor UART.
731          *
732          * If we have to do this here because some non-National
733          * Semiconductor clone chips lock up if you try writing to the
734          * LSR register (which serial_icr_read does)
735          */
736 
737         /*
738          * Check for Oxford Semiconductor 16C950.
739          *
740          * EFR [4] must be set else this test fails.
741          *
742          * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
743          * claims that it's needed for 952 dual UART's (which are not
744          * recommended for new designs).
745          */
746         up->acr = 0;
747         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
748         serial_out(up, UART_EFR, UART_EFR_ECB);
749         serial_out(up, UART_LCR, 0x00);
750         id1 = serial_icr_read(up, UART_ID1);
751         id2 = serial_icr_read(up, UART_ID2);
752         id3 = serial_icr_read(up, UART_ID3);
753         rev = serial_icr_read(up, UART_REV);
754 
755         DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
756 
757         if (id1 == 0x16 && id2 == 0xC9 &&
758             (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
759                 up->port.type = PORT_16C950;
760 
761                 /*
762                  * Enable work around for the Oxford Semiconductor 952 rev B
763                  * chip which causes it to seriously miscalculate baud rates
764                  * when DLL is 0.
765                  */
766                 if (id3 == 0x52 && rev == 0x01)
767                         up->bugs |= UART_BUG_QUOT;
768                 return;
769         }
770 
771         /*
772          * We check for a XR16C850 by setting DLL and DLM to 0, and then
773          * reading back DLL and DLM.  The chip type depends on the DLM
774          * value read back:
775          *  0x10 - XR16C850 and the DLL contains the chip revision.
776          *  0x12 - XR16C2850.
777          *  0x14 - XR16C854.
778          */
779         id1 = autoconfig_read_divisor_id(up);
780         DEBUG_AUTOCONF("850id=%04x ", id1);
781 
782         id2 = id1 >> 8;
783         if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
784                 up->port.type = PORT_16850;
785                 return;
786         }
787 
788         /*
789          * It wasn't an XR16C850.
790          *
791          * We distinguish between the '654 and the '650 by counting
792          * how many bytes are in the FIFO.  I'm using this for now,
793          * since that's the technique that was sent to me in the
794          * serial driver update, but I'm not convinced this works.
795          * I've had problems doing this in the past.  -TYT
796          */
797         if (size_fifo(up) == 64)
798                 up->port.type = PORT_16654;
799         else
800                 up->port.type = PORT_16650V2;
801 }
802 
803 /*
804  * We detected a chip without a FIFO.  Only two fall into
805  * this category - the original 8250 and the 16450.  The
806  * 16450 has a scratch register (accessible with LCR=0)
807  */
808 static void autoconfig_8250(struct uart_8250_port *up)
809 {
810         unsigned char scratch, status1, status2;
811 
812         up->port.type = PORT_8250;
813 
814         scratch = serial_in(up, UART_SCR);
815         serial_out(up, UART_SCR, 0xa5);
816         status1 = serial_in(up, UART_SCR);
817         serial_out(up, UART_SCR, 0x5a);
818         status2 = serial_in(up, UART_SCR);
819         serial_out(up, UART_SCR, scratch);
820 
821         if (status1 == 0xa5 && status2 == 0x5a)
822                 up->port.type = PORT_16450;
823 }
824 
825 static int broken_efr(struct uart_8250_port *up)
826 {
827         /*
828          * Exar ST16C2550 "A2" devices incorrectly detect as
829          * having an EFR, and report an ID of 0x0201.  See
830          * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html 
831          */
832         if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
833                 return 1;
834 
835         return 0;
836 }
837 
838 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
839 {
840         unsigned char status;
841 
842         status = serial_in(up, 0x04); /* EXCR2 */
843 #define PRESL(x) ((x) & 0x30)
844         if (PRESL(status) == 0x10) {
845                 /* already in high speed mode */
846                 return 0;
847         } else {
848                 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
849                 status |= 0x10;  /* 1.625 divisor for baud_base --> 921600 */
850                 serial_out(up, 0x04, status);
851         }
852         return 1;
853 }
854 
855 /*
856  * We know that the chip has FIFOs.  Does it have an EFR?  The
857  * EFR is located in the same register position as the IIR and
858  * we know the top two bits of the IIR are currently set.  The
859  * EFR should contain zero.  Try to read the EFR.
860  */
861 static void autoconfig_16550a(struct uart_8250_port *up)
862 {
863         unsigned char status1, status2;
864         unsigned int iersave;
865 
866         up->port.type = PORT_16550A;
867         up->capabilities |= UART_CAP_FIFO;
868 
869         /*
870          * XR17V35x UARTs have an extra divisor register, DLD
871          * that gets enabled with when DLAB is set which will
872          * cause the device to incorrectly match and assign
873          * port type to PORT_16650.  The EFR for this UART is
874          * found at offset 0x09. Instead check the Deice ID (DVID)
875          * register for a 2, 4 or 8 port UART.
876          */
877         if (up->port.flags & UPF_EXAR_EFR) {
878                 status1 = serial_in(up, UART_EXAR_DVID);
879                 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
880                         DEBUG_AUTOCONF("Exar XR17V35x ");
881                         up->port.type = PORT_XR17V35X;
882                         up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
883                                                 UART_CAP_SLEEP;
884 
885                         return;
886                 }
887 
888         }
889 
890         /*
891          * Check for presence of the EFR when DLAB is set.
892          * Only ST16C650V1 UARTs pass this test.
893          */
894         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
895         if (serial_in(up, UART_EFR) == 0) {
896                 serial_out(up, UART_EFR, 0xA8);
897                 if (serial_in(up, UART_EFR) != 0) {
898                         DEBUG_AUTOCONF("EFRv1 ");
899                         up->port.type = PORT_16650;
900                         up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
901                 } else {
902                         DEBUG_AUTOCONF("Motorola 8xxx DUART ");
903                 }
904                 serial_out(up, UART_EFR, 0);
905                 return;
906         }
907 
908         /*
909          * Maybe it requires 0xbf to be written to the LCR.
910          * (other ST16C650V2 UARTs, TI16C752A, etc)
911          */
912         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
913         if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
914                 DEBUG_AUTOCONF("EFRv2 ");
915                 autoconfig_has_efr(up);
916                 return;
917         }
918 
919         /*
920          * Check for a National Semiconductor SuperIO chip.
921          * Attempt to switch to bank 2, read the value of the LOOP bit
922          * from EXCR1. Switch back to bank 0, change it in MCR. Then
923          * switch back to bank 2, read it from EXCR1 again and check
924          * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
925          */
926         serial_out(up, UART_LCR, 0);
927         status1 = serial_in(up, UART_MCR);
928         serial_out(up, UART_LCR, 0xE0);
929         status2 = serial_in(up, 0x02); /* EXCR1 */
930 
931         if (!((status2 ^ status1) & UART_MCR_LOOP)) {
932                 serial_out(up, UART_LCR, 0);
933                 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
934                 serial_out(up, UART_LCR, 0xE0);
935                 status2 = serial_in(up, 0x02); /* EXCR1 */
936                 serial_out(up, UART_LCR, 0);
937                 serial_out(up, UART_MCR, status1);
938 
939                 if ((status2 ^ status1) & UART_MCR_LOOP) {
940                         unsigned short quot;
941 
942                         serial_out(up, UART_LCR, 0xE0);
943 
944                         quot = serial_dl_read(up);
945                         quot <<= 3;
946 
947                         if (ns16550a_goto_highspeed(up))
948                                 serial_dl_write(up, quot);
949 
950                         serial_out(up, UART_LCR, 0);
951 
952                         up->port.uartclk = 921600*16;
953                         up->port.type = PORT_NS16550A;
954                         up->capabilities |= UART_NATSEMI;
955                         return;
956                 }
957         }
958 
959         /*
960          * No EFR.  Try to detect a TI16750, which only sets bit 5 of
961          * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
962          * Try setting it with and without DLAB set.  Cheap clones
963          * set bit 5 without DLAB set.
964          */
965         serial_out(up, UART_LCR, 0);
966         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
967         status1 = serial_in(up, UART_IIR) >> 5;
968         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
969         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
970         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
971         status2 = serial_in(up, UART_IIR) >> 5;
972         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
973         serial_out(up, UART_LCR, 0);
974 
975         DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
976 
977         if (status1 == 6 && status2 == 7) {
978                 up->port.type = PORT_16750;
979                 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
980                 return;
981         }
982 
983         /*
984          * Try writing and reading the UART_IER_UUE bit (b6).
985          * If it works, this is probably one of the Xscale platform's
986          * internal UARTs.
987          * We're going to explicitly set the UUE bit to 0 before
988          * trying to write and read a 1 just to make sure it's not
989          * already a 1 and maybe locked there before we even start start.
990          */
991         iersave = serial_in(up, UART_IER);
992         serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
993         if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
994                 /*
995                  * OK it's in a known zero state, try writing and reading
996                  * without disturbing the current state of the other bits.
997                  */
998                 serial_out(up, UART_IER, iersave | UART_IER_UUE);
999                 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1000                         /*
1001                          * It's an Xscale.
1002                          * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1003                          */
1004                         DEBUG_AUTOCONF("Xscale ");
1005                         up->port.type = PORT_XSCALE;
1006                         up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1007                         return;
1008                 }
1009         } else {
1010                 /*
1011                  * If we got here we couldn't force the IER_UUE bit to 0.
1012                  * Log it and continue.
1013                  */
1014                 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1015         }
1016         serial_out(up, UART_IER, iersave);
1017 
1018         /*
1019          * Exar uarts have EFR in a weird location
1020          */
1021         if (up->port.flags & UPF_EXAR_EFR) {
1022                 DEBUG_AUTOCONF("Exar XR17D15x ");
1023                 up->port.type = PORT_XR17D15X;
1024                 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1025                                     UART_CAP_SLEEP;
1026 
1027                 return;
1028         }
1029 
1030         /*
1031          * We distinguish between 16550A and U6 16550A by counting
1032          * how many bytes are in the FIFO.
1033          */
1034         if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1035                 up->port.type = PORT_U6_16550A;
1036                 up->capabilities |= UART_CAP_AFE;
1037         }
1038 }
1039 
1040 /*
1041  * This routine is called by rs_init() to initialize a specific serial
1042  * port.  It determines what type of UART chip this serial port is
1043  * using: 8250, 16450, 16550, 16550A.  The important question is
1044  * whether or not this UART is a 16550A or not, since this will
1045  * determine whether or not we can use its FIFO features or not.
1046  */
1047 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1048 {
1049         unsigned char status1, scratch, scratch2, scratch3;
1050         unsigned char save_lcr, save_mcr;
1051         struct uart_port *port = &up->port;
1052         unsigned long flags;
1053         unsigned int old_capabilities;
1054 
1055         if (!port->iobase && !port->mapbase && !port->membase)
1056                 return;
1057 
1058         DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1059                        serial_index(port), port->iobase, port->membase);
1060 
1061         /*
1062          * We really do need global IRQs disabled here - we're going to
1063          * be frobbing the chips IRQ enable register to see if it exists.
1064          */
1065         spin_lock_irqsave(&port->lock, flags);
1066 
1067         up->capabilities = 0;
1068         up->bugs = 0;
1069 
1070         if (!(port->flags & UPF_BUGGY_UART)) {
1071                 /*
1072                  * Do a simple existence test first; if we fail this,
1073                  * there's no point trying anything else.
1074                  *
1075                  * 0x80 is used as a nonsense port to prevent against
1076                  * false positives due to ISA bus float.  The
1077                  * assumption is that 0x80 is a non-existent port;
1078                  * which should be safe since include/asm/io.h also
1079                  * makes this assumption.
1080                  *
1081                  * Note: this is safe as long as MCR bit 4 is clear
1082                  * and the device is in "PC" mode.
1083                  */
1084                 scratch = serial_in(up, UART_IER);
1085                 serial_out(up, UART_IER, 0);
1086 #ifdef __i386__
1087                 outb(0xff, 0x080);
1088 #endif
1089                 /*
1090                  * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1091                  * 16C754B) allow only to modify them if an EFR bit is set.
1092                  */
1093                 scratch2 = serial_in(up, UART_IER) & 0x0f;
1094                 serial_out(up, UART_IER, 0x0F);
1095 #ifdef __i386__
1096                 outb(0, 0x080);
1097 #endif
1098                 scratch3 = serial_in(up, UART_IER) & 0x0f;
1099                 serial_out(up, UART_IER, scratch);
1100                 if (scratch2 != 0 || scratch3 != 0x0F) {
1101                         /*
1102                          * We failed; there's nothing here
1103                          */
1104                         spin_unlock_irqrestore(&port->lock, flags);
1105                         DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1106                                        scratch2, scratch3);
1107                         goto out;
1108                 }
1109         }
1110 
1111         save_mcr = serial_in(up, UART_MCR);
1112         save_lcr = serial_in(up, UART_LCR);
1113 
1114         /*
1115          * Check to see if a UART is really there.  Certain broken
1116          * internal modems based on the Rockwell chipset fail this
1117          * test, because they apparently don't implement the loopback
1118          * test mode.  So this test is skipped on the COM 1 through
1119          * COM 4 ports.  This *should* be safe, since no board
1120          * manufacturer would be stupid enough to design a board
1121          * that conflicts with COM 1-4 --- we hope!
1122          */
1123         if (!(port->flags & UPF_SKIP_TEST)) {
1124                 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1125                 status1 = serial_in(up, UART_MSR) & 0xF0;
1126                 serial_out(up, UART_MCR, save_mcr);
1127                 if (status1 != 0x90) {
1128                         spin_unlock_irqrestore(&port->lock, flags);
1129                         DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1130                                        status1);
1131                         goto out;
1132                 }
1133         }
1134 
1135         /*
1136          * We're pretty sure there's a port here.  Lets find out what
1137          * type of port it is.  The IIR top two bits allows us to find
1138          * out if it's 8250 or 16450, 16550, 16550A or later.  This
1139          * determines what we test for next.
1140          *
1141          * We also initialise the EFR (if any) to zero for later.  The
1142          * EFR occupies the same register location as the FCR and IIR.
1143          */
1144         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1145         serial_out(up, UART_EFR, 0);
1146         serial_out(up, UART_LCR, 0);
1147 
1148         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1149         scratch = serial_in(up, UART_IIR) >> 6;
1150 
1151         switch (scratch) {
1152         case 0:
1153                 autoconfig_8250(up);
1154                 break;
1155         case 1:
1156                 port->type = PORT_UNKNOWN;
1157                 break;
1158         case 2:
1159                 port->type = PORT_16550;
1160                 break;
1161         case 3:
1162                 autoconfig_16550a(up);
1163                 break;
1164         }
1165 
1166 #ifdef CONFIG_SERIAL_8250_RSA
1167         /*
1168          * Only probe for RSA ports if we got the region.
1169          */
1170         if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1171                 int i;
1172 
1173                 for (i = 0 ; i < probe_rsa_count; ++i) {
1174                         if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1175                                 port->type = PORT_RSA;
1176                                 break;
1177                         }
1178                 }
1179         }
1180 #endif
1181 
1182         serial_out(up, UART_LCR, save_lcr);
1183 
1184         port->fifosize = uart_config[up->port.type].fifo_size;
1185         old_capabilities = up->capabilities; 
1186         up->capabilities = uart_config[port->type].flags;
1187         up->tx_loadsz = uart_config[port->type].tx_loadsz;
1188 
1189         if (port->type == PORT_UNKNOWN)
1190                 goto out_lock;
1191 
1192         /*
1193          * Reset the UART.
1194          */
1195 #ifdef CONFIG_SERIAL_8250_RSA
1196         if (port->type == PORT_RSA)
1197                 serial_out(up, UART_RSA_FRR, 0);
1198 #endif
1199         serial_out(up, UART_MCR, save_mcr);
1200         serial8250_clear_fifos(up);
1201         serial_in(up, UART_RX);
1202         if (up->capabilities & UART_CAP_UUE)
1203                 serial_out(up, UART_IER, UART_IER_UUE);
1204         else
1205                 serial_out(up, UART_IER, 0);
1206 
1207 out_lock:
1208         spin_unlock_irqrestore(&port->lock, flags);
1209         if (up->capabilities != old_capabilities) {
1210                 printk(KERN_WARNING
1211                        "ttyS%d: detected caps %08x should be %08x\n",
1212                        serial_index(port), old_capabilities,
1213                        up->capabilities);
1214         }
1215 out:
1216         DEBUG_AUTOCONF("iir=%d ", scratch);
1217         DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1218 }
1219 
1220 static void autoconfig_irq(struct uart_8250_port *up)
1221 {
1222         struct uart_port *port = &up->port;
1223         unsigned char save_mcr, save_ier;
1224         unsigned char save_ICP = 0;
1225         unsigned int ICP = 0;
1226         unsigned long irqs;
1227         int irq;
1228 
1229         if (port->flags & UPF_FOURPORT) {
1230                 ICP = (port->iobase & 0xfe0) | 0x1f;
1231                 save_ICP = inb_p(ICP);
1232                 outb_p(0x80, ICP);
1233                 inb_p(ICP);
1234         }
1235 
1236         /* forget possible initially masked and pending IRQ */
1237         probe_irq_off(probe_irq_on());
1238         save_mcr = serial_in(up, UART_MCR);
1239         save_ier = serial_in(up, UART_IER);
1240         serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1241 
1242         irqs = probe_irq_on();
1243         serial_out(up, UART_MCR, 0);
1244         udelay(10);
1245         if (port->flags & UPF_FOURPORT) {
1246                 serial_out(up, UART_MCR,
1247                             UART_MCR_DTR | UART_MCR_RTS);
1248         } else {
1249                 serial_out(up, UART_MCR,
1250                             UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1251         }
1252         serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1253         serial_in(up, UART_LSR);
1254         serial_in(up, UART_RX);
1255         serial_in(up, UART_IIR);
1256         serial_in(up, UART_MSR);
1257         serial_out(up, UART_TX, 0xFF);
1258         udelay(20);
1259         irq = probe_irq_off(irqs);
1260 
1261         serial_out(up, UART_MCR, save_mcr);
1262         serial_out(up, UART_IER, save_ier);
1263 
1264         if (port->flags & UPF_FOURPORT)
1265                 outb_p(save_ICP, ICP);
1266 
1267         port->irq = (irq > 0) ? irq : 0;
1268 }
1269 
1270 static inline void __stop_tx(struct uart_8250_port *p)
1271 {
1272         if (p->ier & UART_IER_THRI) {
1273                 p->ier &= ~UART_IER_THRI;
1274                 serial_out(p, UART_IER, p->ier);
1275         }
1276 }
1277 
1278 static void serial8250_stop_tx(struct uart_port *port)
1279 {
1280         struct uart_8250_port *up =
1281                 container_of(port, struct uart_8250_port, port);
1282 
1283         __stop_tx(up);
1284 
1285         /*
1286          * We really want to stop the transmitter from sending.
1287          */
1288         if (port->type == PORT_16C950) {
1289                 up->acr |= UART_ACR_TXDIS;
1290                 serial_icr_write(up, UART_ACR, up->acr);
1291         }
1292 }
1293 
1294 static void serial8250_start_tx(struct uart_port *port)
1295 {
1296         struct uart_8250_port *up =
1297                 container_of(port, struct uart_8250_port, port);
1298 
1299         if (up->dma && !serial8250_tx_dma(up)) {
1300                 return;
1301         } else if (!(up->ier & UART_IER_THRI)) {
1302                 up->ier |= UART_IER_THRI;
1303                 serial_port_out(port, UART_IER, up->ier);
1304 
1305                 if (up->bugs & UART_BUG_TXEN) {
1306                         unsigned char lsr;
1307                         lsr = serial_in(up, UART_LSR);
1308                         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1309                         if (lsr & UART_LSR_TEMT)
1310                                 serial8250_tx_chars(up);
1311                 }
1312         }
1313 
1314         /*
1315          * Re-enable the transmitter if we disabled it.
1316          */
1317         if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1318                 up->acr &= ~UART_ACR_TXDIS;
1319                 serial_icr_write(up, UART_ACR, up->acr);
1320         }
1321 }
1322 
1323 static void serial8250_stop_rx(struct uart_port *port)
1324 {
1325         struct uart_8250_port *up =
1326                 container_of(port, struct uart_8250_port, port);
1327 
1328         up->ier &= ~UART_IER_RLSI;
1329         up->port.read_status_mask &= ~UART_LSR_DR;
1330         serial_port_out(port, UART_IER, up->ier);
1331 }
1332 
1333 static void serial8250_enable_ms(struct uart_port *port)
1334 {
1335         struct uart_8250_port *up =
1336                 container_of(port, struct uart_8250_port, port);
1337 
1338         /* no MSR capabilities */
1339         if (up->bugs & UART_BUG_NOMSR)
1340                 return;
1341 
1342         up->ier |= UART_IER_MSI;
1343         serial_port_out(port, UART_IER, up->ier);
1344 }
1345 
1346 /*
1347  * serial8250_rx_chars: processes according to the passed in LSR
1348  * value, and returns the remaining LSR bits not handled
1349  * by this Rx routine.
1350  */
1351 unsigned char
1352 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1353 {
1354         struct uart_port *port = &up->port;
1355         unsigned char ch;
1356         int max_count = 256;
1357         char flag;
1358 
1359         do {
1360                 if (likely(lsr & UART_LSR_DR))
1361                         ch = serial_in(up, UART_RX);
1362                 else
1363                         /*
1364                          * Intel 82571 has a Serial Over Lan device that will
1365                          * set UART_LSR_BI without setting UART_LSR_DR when
1366                          * it receives a break. To avoid reading from the
1367                          * receive buffer without UART_LSR_DR bit set, we
1368                          * just force the read character to be 0
1369                          */
1370                         ch = 0;
1371 
1372                 flag = TTY_NORMAL;
1373                 port->icount.rx++;
1374 
1375                 lsr |= up->lsr_saved_flags;
1376                 up->lsr_saved_flags = 0;
1377 
1378                 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1379                         if (lsr & UART_LSR_BI) {
1380                                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1381                                 port->icount.brk++;
1382                                 /*
1383                                  * We do the SysRQ and SAK checking
1384                                  * here because otherwise the break
1385                                  * may get masked by ignore_status_mask
1386                                  * or read_status_mask.
1387                                  */
1388                                 if (uart_handle_break(port))
1389                                         goto ignore_char;
1390                         } else if (lsr & UART_LSR_PE)
1391                                 port->icount.parity++;
1392                         else if (lsr & UART_LSR_FE)
1393                                 port->icount.frame++;
1394                         if (lsr & UART_LSR_OE)
1395                                 port->icount.overrun++;
1396 
1397                         /*
1398                          * Mask off conditions which should be ignored.
1399                          */
1400                         lsr &= port->read_status_mask;
1401 
1402                         if (lsr & UART_LSR_BI) {
1403                                 DEBUG_INTR("handling break....");
1404                                 flag = TTY_BREAK;
1405                         } else if (lsr & UART_LSR_PE)
1406                                 flag = TTY_PARITY;
1407                         else if (lsr & UART_LSR_FE)
1408                                 flag = TTY_FRAME;
1409                 }
1410                 if (uart_handle_sysrq_char(port, ch))
1411                         goto ignore_char;
1412 
1413                 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1414 
1415 ignore_char:
1416                 lsr = serial_in(up, UART_LSR);
1417         } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1418         spin_unlock(&port->lock);
1419         tty_flip_buffer_push(&port->state->port);
1420         spin_lock(&port->lock);
1421         return lsr;
1422 }
1423 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1424 
1425 void serial8250_tx_chars(struct uart_8250_port *up)
1426 {
1427         struct uart_port *port = &up->port;
1428         struct circ_buf *xmit = &port->state->xmit;
1429         int count;
1430 
1431         if (port->x_char) {
1432                 serial_out(up, UART_TX, port->x_char);
1433                 port->icount.tx++;
1434                 port->x_char = 0;
1435                 return;
1436         }
1437         if (uart_tx_stopped(port)) {
1438                 serial8250_stop_tx(port);
1439                 return;
1440         }
1441         if (uart_circ_empty(xmit)) {
1442                 __stop_tx(up);
1443                 return;
1444         }
1445 
1446         count = up->tx_loadsz;
1447         do {
1448                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1449                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1450                 port->icount.tx++;
1451                 if (uart_circ_empty(xmit))
1452                         break;
1453                 if (up->capabilities & UART_CAP_HFIFO) {
1454                         if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1455                             BOTH_EMPTY)
1456                                 break;
1457                 }
1458         } while (--count > 0);
1459 
1460         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1461                 uart_write_wakeup(port);
1462 
1463         DEBUG_INTR("THRE...");
1464 
1465         if (uart_circ_empty(xmit))
1466                 __stop_tx(up);
1467 }
1468 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1469 
1470 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1471 {
1472         struct uart_port *port = &up->port;
1473         unsigned int status = serial_in(up, UART_MSR);
1474 
1475         status |= up->msr_saved_flags;
1476         up->msr_saved_flags = 0;
1477         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1478             port->state != NULL) {
1479                 if (status & UART_MSR_TERI)
1480                         port->icount.rng++;
1481                 if (status & UART_MSR_DDSR)
1482                         port->icount.dsr++;
1483                 if (status & UART_MSR_DDCD)
1484                         uart_handle_dcd_change(port, status & UART_MSR_DCD);
1485                 if (status & UART_MSR_DCTS)
1486                         uart_handle_cts_change(port, status & UART_MSR_CTS);
1487 
1488                 wake_up_interruptible(&port->state->port.delta_msr_wait);
1489         }
1490 
1491         return status;
1492 }
1493 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1494 
1495 /*
1496  * This handles the interrupt from one port.
1497  */
1498 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1499 {
1500         unsigned char status;
1501         unsigned long flags;
1502         struct uart_8250_port *up =
1503                 container_of(port, struct uart_8250_port, port);
1504         int dma_err = 0;
1505 
1506         if (iir & UART_IIR_NO_INT)
1507                 return 0;
1508 
1509         spin_lock_irqsave(&port->lock, flags);
1510 
1511         status = serial_port_in(port, UART_LSR);
1512 
1513         DEBUG_INTR("status = %x...", status);
1514 
1515         if (status & (UART_LSR_DR | UART_LSR_BI)) {
1516                 if (up->dma)
1517                         dma_err = serial8250_rx_dma(up, iir);
1518 
1519                 if (!up->dma || dma_err)
1520                         status = serial8250_rx_chars(up, status);
1521         }
1522         serial8250_modem_status(up);
1523         if (!up->dma && (status & UART_LSR_THRE))
1524                 serial8250_tx_chars(up);
1525 
1526         spin_unlock_irqrestore(&port->lock, flags);
1527         return 1;
1528 }
1529 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1530 
1531 static int serial8250_default_handle_irq(struct uart_port *port)
1532 {
1533         unsigned int iir = serial_port_in(port, UART_IIR);
1534 
1535         return serial8250_handle_irq(port, iir);
1536 }
1537 
1538 /*
1539  * These Exar UARTs have an extra interrupt indicator that could
1540  * fire for a few unimplemented interrupts.  One of which is a
1541  * wakeup event when coming out of sleep.  Put this here just
1542  * to be on the safe side that these interrupts don't go unhandled.
1543  */
1544 static int exar_handle_irq(struct uart_port *port)
1545 {
1546         unsigned char int0, int1, int2, int3;
1547         unsigned int iir = serial_port_in(port, UART_IIR);
1548         int ret;
1549 
1550         ret = serial8250_handle_irq(port, iir);
1551 
1552         if ((port->type == PORT_XR17V35X) ||
1553            (port->type == PORT_XR17D15X)) {
1554                 int0 = serial_port_in(port, 0x80);
1555                 int1 = serial_port_in(port, 0x81);
1556                 int2 = serial_port_in(port, 0x82);
1557                 int3 = serial_port_in(port, 0x83);
1558         }
1559 
1560         return ret;
1561 }
1562 
1563 /*
1564  * This is the serial driver's interrupt routine.
1565  *
1566  * Arjan thinks the old way was overly complex, so it got simplified.
1567  * Alan disagrees, saying that need the complexity to handle the weird
1568  * nature of ISA shared interrupts.  (This is a special exception.)
1569  *
1570  * In order to handle ISA shared interrupts properly, we need to check
1571  * that all ports have been serviced, and therefore the ISA interrupt
1572  * line has been de-asserted.
1573  *
1574  * This means we need to loop through all ports. checking that they
1575  * don't have an interrupt pending.
1576  */
1577 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1578 {
1579         struct irq_info *i = dev_id;
1580         struct list_head *l, *end = NULL;
1581         int pass_counter = 0, handled = 0;
1582 
1583         DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1584 
1585         spin_lock(&i->lock);
1586 
1587         l = i->head;
1588         do {
1589                 struct uart_8250_port *up;
1590                 struct uart_port *port;
1591 
1592                 up = list_entry(l, struct uart_8250_port, list);
1593                 port = &up->port;
1594 
1595                 if (port->handle_irq(port)) {
1596                         handled = 1;
1597                         end = NULL;
1598                 } else if (end == NULL)
1599                         end = l;
1600 
1601                 l = l->next;
1602 
1603                 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1604                         /* If we hit this, we're dead. */
1605                         printk_ratelimited(KERN_ERR
1606                                 "serial8250: too much work for irq%d\n", irq);
1607                         break;
1608                 }
1609         } while (l != end);
1610 
1611         spin_unlock(&i->lock);
1612 
1613         DEBUG_INTR("end.\n");
1614 
1615         return IRQ_RETVAL(handled);
1616 }
1617 
1618 /*
1619  * To support ISA shared interrupts, we need to have one interrupt
1620  * handler that ensures that the IRQ line has been deasserted
1621  * before returning.  Failing to do this will result in the IRQ
1622  * line being stuck active, and, since ISA irqs are edge triggered,
1623  * no more IRQs will be seen.
1624  */
1625 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1626 {
1627         spin_lock_irq(&i->lock);
1628 
1629         if (!list_empty(i->head)) {
1630                 if (i->head == &up->list)
1631                         i->head = i->head->next;
1632                 list_del(&up->list);
1633         } else {
1634                 BUG_ON(i->head != &up->list);
1635                 i->head = NULL;
1636         }
1637         spin_unlock_irq(&i->lock);
1638         /* List empty so throw away the hash node */
1639         if (i->head == NULL) {
1640                 hlist_del(&i->node);
1641                 kfree(i);
1642         }
1643 }
1644 
1645 static int serial_link_irq_chain(struct uart_8250_port *up)
1646 {
1647         struct hlist_head *h;
1648         struct hlist_node *n;
1649         struct irq_info *i;
1650         int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1651 
1652         mutex_lock(&hash_mutex);
1653 
1654         h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1655 
1656         hlist_for_each(n, h) {
1657                 i = hlist_entry(n, struct irq_info, node);
1658                 if (i->irq == up->port.irq)
1659                         break;
1660         }
1661 
1662         if (n == NULL) {
1663                 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1664                 if (i == NULL) {
1665                         mutex_unlock(&hash_mutex);
1666                         return -ENOMEM;
1667                 }
1668                 spin_lock_init(&i->lock);
1669                 i->irq = up->port.irq;
1670                 hlist_add_head(&i->node, h);
1671         }
1672         mutex_unlock(&hash_mutex);
1673 
1674         spin_lock_irq(&i->lock);
1675 
1676         if (i->head) {
1677                 list_add(&up->list, i->head);
1678                 spin_unlock_irq(&i->lock);
1679 
1680                 ret = 0;
1681         } else {
1682                 INIT_LIST_HEAD(&up->list);
1683                 i->head = &up->list;
1684                 spin_unlock_irq(&i->lock);
1685                 irq_flags |= up->port.irqflags;
1686                 ret = request_irq(up->port.irq, serial8250_interrupt,
1687                                   irq_flags, "serial", i);
1688                 if (ret < 0)
1689                         serial_do_unlink(i, up);
1690         }
1691 
1692         return ret;
1693 }
1694 
1695 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1696 {
1697         /*
1698          * yes, some broken gcc emit "warning: 'i' may be used uninitialized"
1699          * but no, we are not going to take a patch that assigns NULL below.
1700          */
1701         struct irq_info *i;
1702         struct hlist_node *n;
1703         struct hlist_head *h;
1704 
1705         mutex_lock(&hash_mutex);
1706 
1707         h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1708 
1709         hlist_for_each(n, h) {
1710                 i = hlist_entry(n, struct irq_info, node);
1711                 if (i->irq == up->port.irq)
1712                         break;
1713         }
1714 
1715         BUG_ON(n == NULL);
1716         BUG_ON(i->head == NULL);
1717 
1718         if (list_empty(i->head))
1719                 free_irq(up->port.irq, i);
1720 
1721         serial_do_unlink(i, up);
1722         mutex_unlock(&hash_mutex);
1723 }
1724 
1725 /*
1726  * This function is used to handle ports that do not have an
1727  * interrupt.  This doesn't work very well for 16450's, but gives
1728  * barely passable results for a 16550A.  (Although at the expense
1729  * of much CPU overhead).
1730  */
1731 static void serial8250_timeout(unsigned long data)
1732 {
1733         struct uart_8250_port *up = (struct uart_8250_port *)data;
1734 
1735         up->port.handle_irq(&up->port);
1736         mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1737 }
1738 
1739 static void serial8250_backup_timeout(unsigned long data)
1740 {
1741         struct uart_8250_port *up = (struct uart_8250_port *)data;
1742         unsigned int iir, ier = 0, lsr;
1743         unsigned long flags;
1744 
1745         spin_lock_irqsave(&up->port.lock, flags);
1746 
1747         /*
1748          * Must disable interrupts or else we risk racing with the interrupt
1749          * based handler.
1750          */
1751         if (up->port.irq) {
1752                 ier = serial_in(up, UART_IER);
1753                 serial_out(up, UART_IER, 0);
1754         }
1755 
1756         iir = serial_in(up, UART_IIR);
1757 
1758         /*
1759          * This should be a safe test for anyone who doesn't trust the
1760          * IIR bits on their UART, but it's specifically designed for
1761          * the "Diva" UART used on the management processor on many HP
1762          * ia64 and parisc boxes.
1763          */
1764         lsr = serial_in(up, UART_LSR);
1765         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1766         if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1767             (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1768             (lsr & UART_LSR_THRE)) {
1769                 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1770                 iir |= UART_IIR_THRI;
1771         }
1772 
1773         if (!(iir & UART_IIR_NO_INT))
1774                 serial8250_tx_chars(up);
1775 
1776         if (up->port.irq)
1777                 serial_out(up, UART_IER, ier);
1778 
1779         spin_unlock_irqrestore(&up->port.lock, flags);
1780 
1781         /* Standard timer interval plus 0.2s to keep the port running */
1782         mod_timer(&up->timer,
1783                 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1784 }
1785 
1786 static unsigned int serial8250_tx_empty(struct uart_port *port)
1787 {
1788         struct uart_8250_port *up =
1789                 container_of(port, struct uart_8250_port, port);
1790         unsigned long flags;
1791         unsigned int lsr;
1792 
1793         spin_lock_irqsave(&port->lock, flags);
1794         lsr = serial_port_in(port, UART_LSR);
1795         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1796         spin_unlock_irqrestore(&port->lock, flags);
1797 
1798         return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1799 }
1800 
1801 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1802 {
1803         struct uart_8250_port *up =
1804                 container_of(port, struct uart_8250_port, port);
1805         unsigned int status;
1806         unsigned int ret;
1807 
1808         status = serial8250_modem_status(up);
1809 
1810         ret = 0;
1811         if (status & UART_MSR_DCD)
1812                 ret |= TIOCM_CAR;
1813         if (status & UART_MSR_RI)
1814                 ret |= TIOCM_RNG;
1815         if (status & UART_MSR_DSR)
1816                 ret |= TIOCM_DSR;
1817         if (status & UART_MSR_CTS)
1818                 ret |= TIOCM_CTS;
1819         return ret;
1820 }
1821 
1822 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1823 {
1824         struct uart_8250_port *up =
1825                 container_of(port, struct uart_8250_port, port);
1826         unsigned char mcr = 0;
1827 
1828         if (mctrl & TIOCM_RTS)
1829                 mcr |= UART_MCR_RTS;
1830         if (mctrl & TIOCM_DTR)
1831                 mcr |= UART_MCR_DTR;
1832         if (mctrl & TIOCM_OUT1)
1833                 mcr |= UART_MCR_OUT1;
1834         if (mctrl & TIOCM_OUT2)
1835                 mcr |= UART_MCR_OUT2;
1836         if (mctrl & TIOCM_LOOP)
1837                 mcr |= UART_MCR_LOOP;
1838 
1839         mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1840 
1841         serial_port_out(port, UART_MCR, mcr);
1842 }
1843 
1844 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1845 {
1846         struct uart_8250_port *up =
1847                 container_of(port, struct uart_8250_port, port);
1848         unsigned long flags;
1849 
1850         spin_lock_irqsave(&port->lock, flags);
1851         if (break_state == -1)
1852                 up->lcr |= UART_LCR_SBC;
1853         else
1854                 up->lcr &= ~UART_LCR_SBC;
1855         serial_port_out(port, UART_LCR, up->lcr);
1856         spin_unlock_irqrestore(&port->lock, flags);
1857 }
1858 
1859 /*
1860  *      Wait for transmitter & holding register to empty
1861  */
1862 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1863 {
1864         unsigned int status, tmout = 10000;
1865 
1866         /* Wait up to 10ms for the character(s) to be sent. */
1867         for (;;) {
1868                 status = serial_in(up, UART_LSR);
1869 
1870                 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1871 
1872                 if ((status & bits) == bits)
1873                         break;
1874                 if (--tmout == 0)
1875                         break;
1876                 udelay(1);
1877         }
1878 
1879         /* Wait up to 1s for flow control if necessary */
1880         if (up->port.flags & UPF_CONS_FLOW) {
1881                 unsigned int tmout;
1882                 for (tmout = 1000000; tmout; tmout--) {
1883                         unsigned int msr = serial_in(up, UART_MSR);
1884                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1885                         if (msr & UART_MSR_CTS)
1886                                 break;
1887                         udelay(1);
1888                         touch_nmi_watchdog();
1889                 }
1890         }
1891 }
1892 
1893 #ifdef CONFIG_CONSOLE_POLL
1894 /*
1895  * Console polling routines for writing and reading from the uart while
1896  * in an interrupt or debug context.
1897  */
1898 
1899 static int serial8250_get_poll_char(struct uart_port *port)
1900 {
1901         unsigned char lsr = serial_port_in(port, UART_LSR);
1902 
1903         if (!(lsr & UART_LSR_DR))
1904                 return NO_POLL_CHAR;
1905 
1906         return serial_port_in(port, UART_RX);
1907 }
1908 
1909 
1910 static void serial8250_put_poll_char(struct uart_port *port,
1911                          unsigned char c)
1912 {
1913         unsigned int ier;
1914         struct uart_8250_port *up =
1915                 container_of(port, struct uart_8250_port, port);
1916 
1917         /*
1918          *      First save the IER then disable the interrupts
1919          */
1920         ier = serial_port_in(port, UART_IER);
1921         if (up->capabilities & UART_CAP_UUE)
1922                 serial_port_out(port, UART_IER, UART_IER_UUE);
1923         else
1924                 serial_port_out(port, UART_IER, 0);
1925 
1926         wait_for_xmitr(up, BOTH_EMPTY);
1927         /*
1928          *      Send the character out.
1929          *      If a LF, also do CR...
1930          */
1931         serial_port_out(port, UART_TX, c);
1932         if (c == 10) {
1933                 wait_for_xmitr(up, BOTH_EMPTY);
1934                 serial_port_out(port, UART_TX, 13);
1935         }
1936 
1937         /*
1938          *      Finally, wait for transmitter to become empty
1939          *      and restore the IER
1940          */
1941         wait_for_xmitr(up, BOTH_EMPTY);
1942         serial_port_out(port, UART_IER, ier);
1943 }
1944 
1945 #endif /* CONFIG_CONSOLE_POLL */
1946 
1947 static int serial8250_startup(struct uart_port *port)
1948 {
1949         struct uart_8250_port *up =
1950                 container_of(port, struct uart_8250_port, port);
1951         unsigned long flags;
1952         unsigned char lsr, iir;
1953         int retval;
1954 
1955         if (port->type == PORT_8250_CIR)
1956                 return -ENODEV;
1957 
1958         if (!port->fifosize)
1959                 port->fifosize = uart_config[port->type].fifo_size;
1960         if (!up->tx_loadsz)
1961                 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1962         if (!up->capabilities)
1963                 up->capabilities = uart_config[port->type].flags;
1964         up->mcr = 0;
1965 
1966         if (port->iotype != up->cur_iotype)
1967                 set_io_from_upio(port);
1968 
1969         if (port->type == PORT_16C950) {
1970                 /* Wake up and initialize UART */
1971                 up->acr = 0;
1972                 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1973                 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1974                 serial_port_out(port, UART_IER, 0);
1975                 serial_port_out(port, UART_LCR, 0);
1976                 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1977                 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1978                 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1979                 serial_port_out(port, UART_LCR, 0);
1980         }
1981 
1982 #ifdef CONFIG_SERIAL_8250_RSA
1983         /*
1984          * If this is an RSA port, see if we can kick it up to the
1985          * higher speed clock.
1986          */
1987         enable_rsa(up);
1988 #endif
1989 
1990         /*
1991          * Clear the FIFO buffers and disable them.
1992          * (they will be reenabled in set_termios())
1993          */
1994         serial8250_clear_fifos(up);
1995 
1996         /*
1997          * Clear the interrupt registers.
1998          */
1999         serial_port_in(port, UART_LSR);
2000         serial_port_in(port, UART_RX);
2001         serial_port_in(port, UART_IIR);
2002         serial_port_in(port, UART_MSR);
2003 
2004         /*
2005          * At this point, there's no way the LSR could still be 0xff;
2006          * if it is, then bail out, because there's likely no UART
2007          * here.
2008          */
2009         if (!(port->flags & UPF_BUGGY_UART) &&
2010             (serial_port_in(port, UART_LSR) == 0xff)) {
2011                 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2012                                    serial_index(port));
2013                 return -ENODEV;
2014         }
2015 
2016         /*
2017          * For a XR16C850, we need to set the trigger levels
2018          */
2019         if (port->type == PORT_16850) {
2020                 unsigned char fctr;
2021 
2022                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2023 
2024                 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2025                 serial_port_out(port, UART_FCTR,
2026                                 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2027                 serial_port_out(port, UART_TRG, UART_TRG_96);
2028                 serial_port_out(port, UART_FCTR,
2029                                 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2030                 serial_port_out(port, UART_TRG, UART_TRG_96);
2031 
2032                 serial_port_out(port, UART_LCR, 0);
2033         }
2034 
2035         if (port->irq) {
2036                 unsigned char iir1;
2037                 /*
2038                  * Test for UARTs that do not reassert THRE when the
2039                  * transmitter is idle and the interrupt has already
2040                  * been cleared.  Real 16550s should always reassert
2041                  * this interrupt whenever the transmitter is idle and
2042                  * the interrupt is enabled.  Delays are necessary to
2043                  * allow register changes to become visible.
2044                  */
2045                 spin_lock_irqsave(&port->lock, flags);
2046                 if (up->port.irqflags & IRQF_SHARED)
2047                         disable_irq_nosync(port->irq);
2048 
2049                 wait_for_xmitr(up, UART_LSR_THRE);
2050                 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2051                 udelay(1); /* allow THRE to set */
2052                 iir1 = serial_port_in(port, UART_IIR);
2053                 serial_port_out(port, UART_IER, 0);
2054                 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2055                 udelay(1); /* allow a working UART time to re-assert THRE */
2056                 iir = serial_port_in(port, UART_IIR);
2057                 serial_port_out(port, UART_IER, 0);
2058 
2059                 if (port->irqflags & IRQF_SHARED)
2060                         enable_irq(port->irq);
2061                 spin_unlock_irqrestore(&port->lock, flags);
2062 
2063                 /*
2064                  * If the interrupt is not reasserted, or we otherwise
2065                  * don't trust the iir, setup a timer to kick the UART
2066                  * on a regular basis.
2067                  */
2068                 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2069                     up->port.flags & UPF_BUG_THRE) {
2070                         up->bugs |= UART_BUG_THRE;
2071                         pr_debug("ttyS%d - using backup timer\n",
2072                                  serial_index(port));
2073                 }
2074         }
2075 
2076         /*
2077          * The above check will only give an accurate result the first time
2078          * the port is opened so this value needs to be preserved.
2079          */
2080         if (up->bugs & UART_BUG_THRE) {
2081                 up->timer.function = serial8250_backup_timeout;
2082                 up->timer.data = (unsigned long)up;
2083                 mod_timer(&up->timer, jiffies +
2084                         uart_poll_timeout(port) + HZ / 5);
2085         }
2086 
2087         /*
2088          * If the "interrupt" for this port doesn't correspond with any
2089          * hardware interrupt, we use a timer-based system.  The original
2090          * driver used to do this with IRQ0.
2091          */
2092         if (!port->irq) {
2093                 up->timer.data = (unsigned long)up;
2094                 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2095         } else {
2096                 retval = serial_link_irq_chain(up);
2097                 if (retval)
2098                         return retval;
2099         }
2100 
2101         /*
2102          * Now, initialize the UART
2103          */
2104         serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2105 
2106         spin_lock_irqsave(&port->lock, flags);
2107         if (up->port.flags & UPF_FOURPORT) {
2108                 if (!up->port.irq)
2109                         up->port.mctrl |= TIOCM_OUT1;
2110         } else
2111                 /*
2112                  * Most PC uarts need OUT2 raised to enable interrupts.
2113                  */
2114                 if (port->irq)
2115                         up->port.mctrl |= TIOCM_OUT2;
2116 
2117         serial8250_set_mctrl(port, port->mctrl);
2118 
2119         /* Serial over Lan (SoL) hack:
2120            Intel 8257x Gigabit ethernet chips have a
2121            16550 emulation, to be used for Serial Over Lan.
2122            Those chips take a longer time than a normal
2123            serial device to signalize that a transmission
2124            data was queued. Due to that, the above test generally
2125            fails. One solution would be to delay the reading of
2126            iir. However, this is not reliable, since the timeout
2127            is variable. So, let's just don't test if we receive
2128            TX irq. This way, we'll never enable UART_BUG_TXEN.
2129          */
2130         if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2131                 goto dont_test_tx_en;
2132 
2133         /*
2134          * Do a quick test to see if we receive an
2135          * interrupt when we enable the TX irq.
2136          */
2137         serial_port_out(port, UART_IER, UART_IER_THRI);
2138         lsr = serial_port_in(port, UART_LSR);
2139         iir = serial_port_in(port, UART_IIR);
2140         serial_port_out(port, UART_IER, 0);
2141 
2142         if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2143                 if (!(up->bugs & UART_BUG_TXEN)) {
2144                         up->bugs |= UART_BUG_TXEN;
2145                         pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2146                                  serial_index(port));
2147                 }
2148         } else {
2149                 up->bugs &= ~UART_BUG_TXEN;
2150         }
2151 
2152 dont_test_tx_en:
2153         spin_unlock_irqrestore(&port->lock, flags);
2154 
2155         /*
2156          * Clear the interrupt registers again for luck, and clear the
2157          * saved flags to avoid getting false values from polling
2158          * routines or the previous session.
2159          */
2160         serial_port_in(port, UART_LSR);
2161         serial_port_in(port, UART_RX);
2162         serial_port_in(port, UART_IIR);
2163         serial_port_in(port, UART_MSR);
2164         up->lsr_saved_flags = 0;
2165         up->msr_saved_flags = 0;
2166 
2167         /*
2168          * Request DMA channels for both RX and TX.
2169          */
2170         if (up->dma) {
2171                 retval = serial8250_request_dma(up);
2172                 if (retval) {
2173                         pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2174                                             serial_index(port));
2175                         up->dma = NULL;
2176                 }
2177         }
2178 
2179         /*
2180          * Finally, enable interrupts.  Note: Modem status interrupts
2181          * are set via set_termios(), which will be occurring imminently
2182          * anyway, so we don't enable them here.
2183          */
2184         up->ier = UART_IER_RLSI | UART_IER_RDI;
2185         serial_port_out(port, UART_IER, up->ier);
2186 
2187         if (port->flags & UPF_FOURPORT) {
2188                 unsigned int icp;
2189                 /*
2190                  * Enable interrupts on the AST Fourport board
2191                  */
2192                 icp = (port->iobase & 0xfe0) | 0x01f;
2193                 outb_p(0x80, icp);
2194                 inb_p(icp);
2195         }
2196 
2197         return 0;
2198 }
2199 
2200 static void serial8250_shutdown(struct uart_port *port)
2201 {
2202         struct uart_8250_port *up =
2203                 container_of(port, struct uart_8250_port, port);
2204         unsigned long flags;
2205 
2206         /*
2207          * Disable interrupts from this port
2208          */
2209         up->ier = 0;
2210         serial_port_out(port, UART_IER, 0);
2211 
2212         if (up->dma)
2213                 serial8250_release_dma(up);
2214 
2215         spin_lock_irqsave(&port->lock, flags);
2216         if (port->flags & UPF_FOURPORT) {
2217                 /* reset interrupts on the AST Fourport board */
2218                 inb((port->iobase & 0xfe0) | 0x1f);
2219                 port->mctrl |= TIOCM_OUT1;
2220         } else
2221                 port->mctrl &= ~TIOCM_OUT2;
2222 
2223         serial8250_set_mctrl(port, port->mctrl);
2224         spin_unlock_irqrestore(&port->lock, flags);
2225 
2226         /*
2227          * Disable break condition and FIFOs
2228          */
2229         serial_port_out(port, UART_LCR,
2230                         serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2231         serial8250_clear_fifos(up);
2232 
2233 #ifdef CONFIG_SERIAL_8250_RSA
2234         /*
2235          * Reset the RSA board back to 115kbps compat mode.
2236          */
2237         disable_rsa(up);
2238 #endif
2239 
2240         /*
2241          * Read data port to reset things, and then unlink from
2242          * the IRQ chain.
2243          */
2244         serial_port_in(port, UART_RX);
2245 
2246         del_timer_sync(&up->timer);
2247         up->timer.function = serial8250_timeout;
2248         if (port->irq)
2249                 serial_unlink_irq_chain(up);
2250 }
2251 
2252 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2253 {
2254         unsigned int quot;
2255 
2256         /*
2257          * Handle magic divisors for baud rates above baud_base on
2258          * SMSC SuperIO chips.
2259          */
2260         if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2261             baud == (port->uartclk/4))
2262                 quot = 0x8001;
2263         else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2264                  baud == (port->uartclk/8))
2265                 quot = 0x8002;
2266         else
2267                 quot = uart_get_divisor(port, baud);
2268 
2269         return quot;
2270 }
2271 
2272 void
2273 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2274                           struct ktermios *old)
2275 {
2276         struct uart_8250_port *up =
2277                 container_of(port, struct uart_8250_port, port);
2278         unsigned char cval, fcr = 0;
2279         unsigned long flags;
2280         unsigned int baud, quot;
2281         int fifo_bug = 0;
2282 
2283         switch (termios->c_cflag & CSIZE) {
2284         case CS5:
2285                 cval = UART_LCR_WLEN5;
2286                 break;
2287         case CS6:
2288                 cval = UART_LCR_WLEN6;
2289                 break;
2290         case CS7:
2291                 cval = UART_LCR_WLEN7;
2292                 break;
2293         default:
2294         case CS8:
2295                 cval = UART_LCR_WLEN8;
2296                 break;
2297         }
2298 
2299         if (termios->c_cflag & CSTOPB)
2300                 cval |= UART_LCR_STOP;
2301         if (termios->c_cflag & PARENB) {
2302                 cval |= UART_LCR_PARITY;
2303                 if (up->bugs & UART_BUG_PARITY)
2304                         fifo_bug = 1;
2305         }
2306         if (!(termios->c_cflag & PARODD))
2307                 cval |= UART_LCR_EPAR;
2308 #ifdef CMSPAR
2309         if (termios->c_cflag & CMSPAR)
2310                 cval |= UART_LCR_SPAR;
2311 #endif
2312 
2313         /*
2314          * Ask the core to calculate the divisor for us.
2315          */
2316         baud = uart_get_baud_rate(port, termios, old,
2317                                   port->uartclk / 16 / 0xffff,
2318                                   port->uartclk / 16);
2319         quot = serial8250_get_divisor(port, baud);
2320 
2321         /*
2322          * Oxford Semi 952 rev B workaround
2323          */
2324         if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2325                 quot++;
2326 
2327         if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2328                 fcr = uart_config[port->type].fcr;
2329                 if ((baud < 2400 && !up->dma) || fifo_bug) {
2330                         fcr &= ~UART_FCR_TRIGGER_MASK;
2331                         fcr |= UART_FCR_TRIGGER_1;
2332                 }
2333         }
2334 
2335         /*
2336          * MCR-based auto flow control.  When AFE is enabled, RTS will be
2337          * deasserted when the receive FIFO contains more characters than
2338          * the trigger, or the MCR RTS bit is cleared.  In the case where
2339          * the remote UART is not using CTS auto flow control, we must
2340          * have sufficient FIFO entries for the latency of the remote
2341          * UART to respond.  IOW, at least 32 bytes of FIFO.
2342          */
2343         if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2344                 up->mcr &= ~UART_MCR_AFE;
2345                 if (termios->c_cflag & CRTSCTS)
2346                         up->mcr |= UART_MCR_AFE;
2347         }
2348 
2349         /*
2350          * Ok, we're now changing the port state.  Do it with
2351          * interrupts disabled.
2352          */
2353         spin_lock_irqsave(&port->lock, flags);
2354 
2355         /*
2356          * Update the per-port timeout.
2357          */
2358         uart_update_timeout(port, termios->c_cflag, baud);
2359 
2360         port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2361         if (termios->c_iflag & INPCK)
2362                 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2363         if (termios->c_iflag & (BRKINT | PARMRK))
2364                 port->read_status_mask |= UART_LSR_BI;
2365 
2366         /*
2367          * Characteres to ignore
2368          */
2369         port->ignore_status_mask = 0;
2370         if (termios->c_iflag & IGNPAR)
2371                 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2372         if (termios->c_iflag & IGNBRK) {
2373                 port->ignore_status_mask |= UART_LSR_BI;
2374                 /*
2375                  * If we're ignoring parity and break indicators,
2376                  * ignore overruns too (for real raw support).
2377                  */
2378                 if (termios->c_iflag & IGNPAR)
2379                         port->ignore_status_mask |= UART_LSR_OE;
2380         }
2381 
2382         /*
2383          * ignore all characters if CREAD is not set
2384          */
2385         if ((termios->c_cflag & CREAD) == 0)
2386                 port->ignore_status_mask |= UART_LSR_DR;
2387 
2388         /*
2389          * CTS flow control flag and modem status interrupts
2390          */
2391         up->ier &= ~UART_IER_MSI;
2392         if (!(up->bugs & UART_BUG_NOMSR) &&
2393                         UART_ENABLE_MS(&up->port, termios->c_cflag))
2394                 up->ier |= UART_IER_MSI;
2395         if (up->capabilities & UART_CAP_UUE)
2396                 up->ier |= UART_IER_UUE;
2397         if (up->capabilities & UART_CAP_RTOIE)
2398                 up->ier |= UART_IER_RTOIE;
2399 
2400         serial_port_out(port, UART_IER, up->ier);
2401 
2402         if (up->capabilities & UART_CAP_EFR) {
2403                 unsigned char efr = 0;
2404                 /*
2405                  * TI16C752/Startech hardware flow control.  FIXME:
2406                  * - TI16C752 requires control thresholds to be set.
2407                  * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2408                  */
2409                 if (termios->c_cflag & CRTSCTS)
2410                         efr |= UART_EFR_CTS;
2411 
2412                 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2413                 if (port->flags & UPF_EXAR_EFR)
2414                         serial_port_out(port, UART_XR_EFR, efr);
2415                 else
2416                         serial_port_out(port, UART_EFR, efr);
2417         }
2418 
2419         /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2420         if (is_omap1510_8250(up)) {
2421                 if (baud == 115200) {
2422                         quot = 1;
2423                         serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2424                 } else
2425                         serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2426         }
2427 
2428         /*
2429          * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2430          * otherwise just set DLAB
2431          */
2432         if (up->capabilities & UART_NATSEMI)
2433                 serial_port_out(port, UART_LCR, 0xe0);
2434         else
2435                 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
2436 
2437         serial_dl_write(up, quot);
2438 
2439         /*
2440          * XR17V35x UARTs have an extra fractional divisor register (DLD)
2441          *
2442          * We need to recalculate all of the registers, because DLM and DLL
2443          * are already rounded to a whole integer.
2444          *
2445          * When recalculating we use a 32x clock instead of a 16x clock to
2446          * allow 1-bit for rounding in the fractional part.
2447          */
2448         if (up->port.type == PORT_XR17V35X) {
2449                 unsigned int baud_x32 = (port->uartclk * 2) / baud;
2450                 u16 quot = baud_x32 / 32;
2451                 u8 quot_frac = DIV_ROUND_CLOSEST(baud_x32 % 32, 2);
2452 
2453                 serial_dl_write(up, quot);
2454                 serial_port_out(port, 0x2, quot_frac & 0xf);
2455         }
2456 
2457         /*
2458          * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2459          * is written without DLAB set, this mode will be disabled.
2460          */
2461         if (port->type == PORT_16750)
2462                 serial_port_out(port, UART_FCR, fcr);
2463 
2464         serial_port_out(port, UART_LCR, cval);          /* reset DLAB */
2465         up->lcr = cval;                                 /* Save LCR */
2466         if (port->type != PORT_16750) {
2467                 /* emulated UARTs (Lucent Venus 167x) need two steps */
2468                 if (fcr & UART_FCR_ENABLE_FIFO)
2469                         serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2470                 serial_port_out(port, UART_FCR, fcr);           /* set fcr */
2471         }
2472         serial8250_set_mctrl(port, port->mctrl);
2473         spin_unlock_irqrestore(&port->lock, flags);
2474         /* Don't rewrite B0 */
2475         if (tty_termios_baud_rate(termios))
2476                 tty_termios_encode_baud_rate(termios, baud, baud);
2477 }
2478 EXPORT_SYMBOL(serial8250_do_set_termios);
2479 
2480 static void
2481 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2482                        struct ktermios *old)
2483 {
2484         if (port->set_termios)
2485                 port->set_termios(port, termios, old);
2486         else
2487                 serial8250_do_set_termios(port, termios, old);
2488 }
2489 
2490 static void
2491 serial8250_set_ldisc(struct uart_port *port, int new)
2492 {
2493         if (new == N_PPS) {
2494                 port->flags |= UPF_HARDPPS_CD;
2495                 serial8250_enable_ms(port);
2496         } else
2497                 port->flags &= ~UPF_HARDPPS_CD;
2498 }
2499 
2500 
2501 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2502                       unsigned int oldstate)
2503 {
2504         struct uart_8250_port *p =
2505                 container_of(port, struct uart_8250_port, port);
2506 
2507         serial8250_set_sleep(p, state != 0);
2508 }
2509 EXPORT_SYMBOL(serial8250_do_pm);
2510 
2511 static void
2512 serial8250_pm(struct uart_port *port, unsigned int state,
2513               unsigned int oldstate)
2514 {
2515         if (port->pm)
2516                 port->pm(port, state, oldstate);
2517         else
2518                 serial8250_do_pm(port, state, oldstate);
2519 }
2520 
2521 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2522 {
2523         if (pt->port.iotype == UPIO_AU)
2524                 return 0x1000;
2525         if (is_omap1_8250(pt))
2526                 return 0x16 << pt->port.regshift;
2527 
2528         return 8 << pt->port.regshift;
2529 }
2530 
2531 /*
2532  * Resource handling.
2533  */
2534 static int serial8250_request_std_resource(struct uart_8250_port *up)
2535 {
2536         unsigned int size = serial8250_port_size(up);
2537         struct uart_port *port = &up->port;
2538         int ret = 0;
2539 
2540         switch (port->iotype) {
2541         case UPIO_AU:
2542         case UPIO_TSI:
2543         case UPIO_MEM32:
2544         case UPIO_MEM:
2545                 if (!port->mapbase)
2546                         break;
2547 
2548                 if (!request_mem_region(port->mapbase, size, "serial")) {
2549                         ret = -EBUSY;
2550                         break;
2551                 }
2552 
2553                 if (port->flags & UPF_IOREMAP) {
2554                         port->membase = ioremap_nocache(port->mapbase, size);
2555                         if (!port->membase) {
2556                                 release_mem_region(port->mapbase, size);
2557                                 ret = -ENOMEM;
2558                         }
2559                 }
2560                 break;
2561 
2562         case UPIO_HUB6:
2563         case UPIO_PORT:
2564                 if (!request_region(port->iobase, size, "serial"))
2565                         ret = -EBUSY;
2566                 break;
2567         }
2568         return ret;
2569 }
2570 
2571 static void serial8250_release_std_resource(struct uart_8250_port *up)
2572 {
2573         unsigned int size = serial8250_port_size(up);
2574         struct uart_port *port = &up->port;
2575 
2576         switch (port->iotype) {
2577         case UPIO_AU:
2578         case UPIO_TSI:
2579         case UPIO_MEM32:
2580         case UPIO_MEM:
2581                 if (!port->mapbase)
2582                         break;
2583 
2584                 if (port->flags & UPF_IOREMAP) {
2585                         iounmap(port->membase);
2586                         port->membase = NULL;
2587                 }
2588 
2589                 release_mem_region(port->mapbase, size);
2590                 break;
2591 
2592         case UPIO_HUB6:
2593         case UPIO_PORT:
2594                 release_region(port->iobase, size);
2595                 break;
2596         }
2597 }
2598 
2599 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2600 {
2601         unsigned long start = UART_RSA_BASE << up->port.regshift;
2602         unsigned int size = 8 << up->port.regshift;
2603         struct uart_port *port = &up->port;
2604         int ret = -EINVAL;
2605 
2606         switch (port->iotype) {
2607         case UPIO_HUB6:
2608         case UPIO_PORT:
2609                 start += port->iobase;
2610                 if (request_region(start, size, "serial-rsa"))
2611                         ret = 0;
2612                 else
2613                         ret = -EBUSY;
2614                 break;
2615         }
2616 
2617         return ret;
2618 }
2619 
2620 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2621 {
2622         unsigned long offset = UART_RSA_BASE << up->port.regshift;
2623         unsigned int size = 8 << up->port.regshift;
2624         struct uart_port *port = &up->port;
2625 
2626         switch (port->iotype) {
2627         case UPIO_HUB6:
2628         case UPIO_PORT:
2629                 release_region(port->iobase + offset, size);
2630                 break;
2631         }
2632 }
2633 
2634 static void serial8250_release_port(struct uart_port *port)
2635 {
2636         struct uart_8250_port *up =
2637                 container_of(port, struct uart_8250_port, port);
2638 
2639         serial8250_release_std_resource(up);
2640         if (port->type == PORT_RSA)
2641                 serial8250_release_rsa_resource(up);
2642 }
2643 
2644 static int serial8250_request_port(struct uart_port *port)
2645 {
2646         struct uart_8250_port *up =
2647                 container_of(port, struct uart_8250_port, port);
2648         int ret;
2649 
2650         if (port->type == PORT_8250_CIR)
2651                 return -ENODEV;
2652 
2653         ret = serial8250_request_std_resource(up);
2654         if (ret == 0 && port->type == PORT_RSA) {
2655                 ret = serial8250_request_rsa_resource(up);
2656                 if (ret < 0)
2657                         serial8250_release_std_resource(up);
2658         }
2659 
2660         return ret;
2661 }
2662 
2663 static void serial8250_config_port(struct uart_port *port, int flags)
2664 {
2665         struct uart_8250_port *up =
2666                 container_of(port, struct uart_8250_port, port);
2667         int probeflags = PROBE_ANY;
2668         int ret;
2669 
2670         if (port->type == PORT_8250_CIR)
2671                 return;
2672 
2673         /*
2674          * Find the region that we can probe for.  This in turn
2675          * tells us whether we can probe for the type of port.
2676          */
2677         ret = serial8250_request_std_resource(up);
2678         if (ret < 0)
2679                 return;
2680 
2681         ret = serial8250_request_rsa_resource(up);
2682         if (ret < 0)
2683                 probeflags &= ~PROBE_RSA;
2684 
2685         if (port->iotype != up->cur_iotype)
2686                 set_io_from_upio(port);
2687 
2688         if (flags & UART_CONFIG_TYPE)
2689                 autoconfig(up, probeflags);
2690 
2691         /* if access method is AU, it is a 16550 with a quirk */
2692         if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2693                 up->bugs |= UART_BUG_NOMSR;
2694 
2695         /* HW bugs may trigger IRQ while IIR == NO_INT */
2696         if (port->type == PORT_TEGRA)
2697                 up->bugs |= UART_BUG_NOMSR;
2698 
2699         if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2700                 autoconfig_irq(up);
2701 
2702         if (port->type != PORT_RSA && probeflags & PROBE_RSA)
2703                 serial8250_release_rsa_resource(up);
2704         if (port->type == PORT_UNKNOWN)
2705                 serial8250_release_std_resource(up);
2706 
2707         /* Fixme: probably not the best place for this */
2708         if ((port->type == PORT_XR17V35X) ||
2709            (port->type == PORT_XR17D15X))
2710                 port->handle_irq = exar_handle_irq;
2711 }
2712 
2713 static int
2714 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2715 {
2716         if (ser->irq >= nr_irqs || ser->irq < 0 ||
2717             ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2718             ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2719             ser->type == PORT_STARTECH)
2720                 return -EINVAL;
2721         return 0;
2722 }
2723 
2724 static const char *
2725 serial8250_type(struct uart_port *port)
2726 {
2727         int type = port->type;
2728 
2729         if (type >= ARRAY_SIZE(uart_config))
2730                 type = 0;
2731         return uart_config[type].name;
2732 }
2733 
2734 static struct uart_ops serial8250_pops = {
2735         .tx_empty       = serial8250_tx_empty,
2736         .set_mctrl      = serial8250_set_mctrl,
2737         .get_mctrl      = serial8250_get_mctrl,
2738         .stop_tx        = serial8250_stop_tx,
2739         .start_tx       = serial8250_start_tx,
2740         .stop_rx        = serial8250_stop_rx,
2741         .enable_ms      = serial8250_enable_ms,
2742         .break_ctl      = serial8250_break_ctl,
2743         .startup        = serial8250_startup,
2744         .shutdown       = serial8250_shutdown,
2745         .set_termios    = serial8250_set_termios,
2746         .set_ldisc      = serial8250_set_ldisc,
2747         .pm             = serial8250_pm,
2748         .type           = serial8250_type,
2749         .release_port   = serial8250_release_port,
2750         .request_port   = serial8250_request_port,
2751         .config_port    = serial8250_config_port,
2752         .verify_port    = serial8250_verify_port,
2753 #ifdef CONFIG_CONSOLE_POLL
2754         .poll_get_char = serial8250_get_poll_char,
2755         .poll_put_char = serial8250_put_poll_char,
2756 #endif
2757 };
2758 
2759 static struct uart_8250_port serial8250_ports[UART_NR];
2760 
2761 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2762         unsigned short *capabilities);
2763 
2764 void serial8250_set_isa_configurator(
2765         void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2766 {
2767         serial8250_isa_config = v;
2768 }
2769 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2770 
2771 static void __init serial8250_isa_init_ports(void)
2772 {
2773         struct uart_8250_port *up;
2774         static int first = 1;
2775         int i, irqflag = 0;
2776 
2777         if (!first)
2778                 return;
2779         first = 0;
2780 
2781         if (nr_uarts > UART_NR)
2782                 nr_uarts = UART_NR;
2783 
2784         for (i = 0; i < nr_uarts; i++) {
2785                 struct uart_8250_port *up = &serial8250_ports[i];
2786                 struct uart_port *port = &up->port;
2787 
2788                 port->line = i;
2789                 spin_lock_init(&port->lock);
2790 
2791                 init_timer(&up->timer);
2792                 up->timer.function = serial8250_timeout;
2793                 up->cur_iotype = 0xFF;
2794 
2795                 /*
2796                  * ALPHA_KLUDGE_MCR needs to be killed.
2797                  */
2798                 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2799                 up->mcr_force = ALPHA_KLUDGE_MCR;
2800 
2801                 port->ops = &serial8250_pops;
2802         }
2803 
2804         if (share_irqs)
2805                 irqflag = IRQF_SHARED;
2806 
2807         for (i = 0, up = serial8250_ports;
2808              i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2809              i++, up++) {
2810                 struct uart_port *port = &up->port;
2811 
2812                 port->iobase   = old_serial_port[i].port;
2813                 port->irq      = irq_canonicalize(old_serial_port[i].irq);
2814                 port->irqflags = old_serial_port[i].irqflags;
2815                 port->uartclk  = old_serial_port[i].baud_base * 16;
2816                 port->flags    = old_serial_port[i].flags;
2817                 port->hub6     = old_serial_port[i].hub6;
2818                 port->membase  = old_serial_port[i].iomem_base;
2819                 port->iotype   = old_serial_port[i].io_type;
2820                 port->regshift = old_serial_port[i].iomem_reg_shift;
2821                 set_io_from_upio(port);
2822                 port->irqflags |= irqflag;
2823                 if (serial8250_isa_config != NULL)
2824                         serial8250_isa_config(i, &up->port, &up->capabilities);
2825 
2826         }
2827 }
2828 
2829 static void
2830 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2831 {
2832         up->port.type = type;
2833         if (!up->port.fifosize)
2834                 up->port.fifosize = uart_config[type].fifo_size;
2835         if (!up->tx_loadsz)
2836                 up->tx_loadsz = uart_config[type].tx_loadsz;
2837         if (!up->capabilities)
2838                 up->capabilities = uart_config[type].flags;
2839 }
2840 
2841 static void __init
2842 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2843 {
2844         int i;
2845 
2846         for (i = 0; i < nr_uarts; i++) {
2847                 struct uart_8250_port *up = &serial8250_ports[i];
2848 
2849                 if (up->port.dev)
2850                         continue;
2851 
2852                 up->port.dev = dev;
2853 
2854                 if (up->port.flags & UPF_FIXED_TYPE)
2855                         serial8250_init_fixed_type_port(up, up->port.type);
2856 
2857                 uart_add_one_port(drv, &up->port);
2858         }
2859 }
2860 
2861 #ifdef CONFIG_SERIAL_8250_CONSOLE
2862 
2863 static void serial8250_console_putchar(struct uart_port *port, int ch)
2864 {
2865         struct uart_8250_port *up =
2866                 container_of(port, struct uart_8250_port, port);
2867 
2868         wait_for_xmitr(up, UART_LSR_THRE);
2869         serial_port_out(port, UART_TX, ch);
2870 }
2871 
2872 /*
2873  *      Print a string to the serial port trying not to disturb
2874  *      any possible real use of the port...
2875  *
2876  *      The console_lock must be held when we get here.
2877  */
2878 static void
2879 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2880 {
2881         struct uart_8250_port *up = &serial8250_ports[co->index];
2882         struct uart_port *port = &up->port;
2883         unsigned long flags;
2884         unsigned int ier;
2885         int locked = 1;
2886 
2887         touch_nmi_watchdog();
2888 
2889         if (port->sysrq || oops_in_progress)
2890                 locked = spin_trylock_irqsave(&port->lock, flags);
2891         else
2892                 spin_lock_irqsave(&port->lock, flags);
2893 
2894         /*
2895          *      First save the IER then disable the interrupts
2896          */
2897         ier = serial_port_in(port, UART_IER);
2898 
2899         if (up->capabilities & UART_CAP_UUE)
2900                 serial_port_out(port, UART_IER, UART_IER_UUE);
2901         else
2902                 serial_port_out(port, UART_IER, 0);
2903 
2904         uart_console_write(port, s, count, serial8250_console_putchar);
2905 
2906         /*
2907          *      Finally, wait for transmitter to become empty
2908          *      and restore the IER
2909          */
2910         wait_for_xmitr(up, BOTH_EMPTY);
2911         serial_port_out(port, UART_IER, ier);
2912 
2913         /*
2914          *      The receive handling will happen properly because the
2915          *      receive ready bit will still be set; it is not cleared
2916          *      on read.  However, modem control will not, we must
2917          *      call it if we have saved something in the saved flags
2918          *      while processing with interrupts off.
2919          */
2920         if (up->msr_saved_flags)
2921                 serial8250_modem_status(up);
2922 
2923         if (locked)
2924                 spin_unlock_irqrestore(&port->lock, flags);
2925 }
2926 
2927 static int __init serial8250_console_setup(struct console *co, char *options)
2928 {
2929         struct uart_port *port;
2930         int baud = 9600;
2931         int bits = 8;
2932         int parity = 'n';
2933         int flow = 'n';
2934 
2935         /*
2936          * Check whether an invalid uart number has been specified, and
2937          * if so, search for the first available port that does have
2938          * console support.
2939          */
2940         if (co->index >= nr_uarts)
2941                 co->index = 0;
2942         port = &serial8250_ports[co->index].port;
2943         if (!port->iobase && !port->membase)
2944                 return -ENODEV;
2945 
2946         if (options)
2947                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2948 
2949         return uart_set_options(port, co, baud, parity, bits, flow);
2950 }
2951 
2952 static int serial8250_console_early_setup(void)
2953 {
2954         return serial8250_find_port_for_earlycon();
2955 }
2956 
2957 static struct console serial8250_console = {
2958         .name           = "ttyS",
2959         .write          = serial8250_console_write,
2960         .device         = uart_console_device,
2961         .setup          = serial8250_console_setup,
2962         .early_setup    = serial8250_console_early_setup,
2963         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
2964         .index          = -1,
2965         .data           = &serial8250_reg,
2966 };
2967 
2968 static int __init serial8250_console_init(void)
2969 {
2970         serial8250_isa_init_ports();
2971         register_console(&serial8250_console);
2972         return 0;
2973 }
2974 console_initcall(serial8250_console_init);
2975 
2976 int serial8250_find_port(struct uart_port *p)
2977 {
2978         int line;
2979         struct uart_port *port;
2980 
2981         for (line = 0; line < nr_uarts; line++) {
2982                 port = &serial8250_ports[line].port;
2983                 if (uart_match_port(p, port))
2984                         return line;
2985         }
2986         return -ENODEV;
2987 }
2988 
2989 #define SERIAL8250_CONSOLE      &serial8250_console
2990 #else
2991 #define SERIAL8250_CONSOLE      NULL
2992 #endif
2993 
2994 static struct uart_driver serial8250_reg = {
2995         .owner                  = THIS_MODULE,
2996         .driver_name            = "serial",
2997         .dev_name               = "ttyS",
2998         .major                  = TTY_MAJOR,
2999         .minor                  = 64,
3000         .cons                   = SERIAL8250_CONSOLE,
3001 };
3002 
3003 /*
3004  * early_serial_setup - early registration for 8250 ports
3005  *
3006  * Setup an 8250 port structure prior to console initialisation.  Use
3007  * after console initialisation will cause undefined behaviour.
3008  */
3009 int __init early_serial_setup(struct uart_port *port)
3010 {
3011         struct uart_port *p;
3012 
3013         if (port->line >= ARRAY_SIZE(serial8250_ports))
3014                 return -ENODEV;
3015 
3016         serial8250_isa_init_ports();
3017         p = &serial8250_ports[port->line].port;
3018         p->iobase       = port->iobase;
3019         p->membase      = port->membase;
3020         p->irq          = port->irq;
3021         p->irqflags     = port->irqflags;
3022         p->uartclk      = port->uartclk;
3023         p->fifosize     = port->fifosize;
3024         p->regshift     = port->regshift;
3025         p->iotype       = port->iotype;
3026         p->flags        = port->flags;
3027         p->mapbase      = port->mapbase;
3028         p->private_data = port->private_data;
3029         p->type         = port->type;
3030         p->line         = port->line;
3031 
3032         set_io_from_upio(p);
3033         if (port->serial_in)
3034                 p->serial_in = port->serial_in;
3035         if (port->serial_out)
3036                 p->serial_out = port->serial_out;
3037         if (port->handle_irq)
3038                 p->handle_irq = port->handle_irq;
3039         else
3040                 p->handle_irq = serial8250_default_handle_irq;
3041 
3042         return 0;
3043 }
3044 
3045 /**
3046  *      serial8250_suspend_port - suspend one serial port
3047  *      @line:  serial line number
3048  *
3049  *      Suspend one serial port.
3050  */
3051 void serial8250_suspend_port(int line)
3052 {
3053         uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3054 }
3055 
3056 /**
3057  *      serial8250_resume_port - resume one serial port
3058  *      @line:  serial line number
3059  *
3060  *      Resume one serial port.
3061  */
3062 void serial8250_resume_port(int line)
3063 {
3064         struct uart_8250_port *up = &serial8250_ports[line];
3065         struct uart_port *port = &up->port;
3066 
3067         if (up->capabilities & UART_NATSEMI) {
3068                 /* Ensure it's still in high speed mode */
3069                 serial_port_out(port, UART_LCR, 0xE0);
3070 
3071                 ns16550a_goto_highspeed(up);
3072 
3073                 serial_port_out(port, UART_LCR, 0);
3074                 port->uartclk = 921600*16;
3075         }
3076         uart_resume_port(&serial8250_reg, port);
3077 }
3078 
3079 /*
3080  * Register a set of serial devices attached to a platform device.  The
3081  * list is terminated with a zero flags entry, which means we expect
3082  * all entries to have at least UPF_BOOT_AUTOCONF set.
3083  */
3084 static int serial8250_probe(struct platform_device *dev)
3085 {
3086         struct plat_serial8250_port *p = dev_get_platdata(&dev->dev);
3087         struct uart_8250_port uart;
3088         int ret, i, irqflag = 0;
3089 
3090         memset(&uart, 0, sizeof(uart));
3091 
3092         if (share_irqs)
3093                 irqflag = IRQF_SHARED;
3094 
3095         for (i = 0; p && p->flags != 0; p++, i++) {
3096                 uart.port.iobase        = p->iobase;
3097                 uart.port.membase       = p->membase;
3098                 uart.port.irq           = p->irq;
3099                 uart.port.irqflags      = p->irqflags;
3100                 uart.port.uartclk       = p->uartclk;
3101                 uart.port.regshift      = p->regshift;
3102                 uart.port.iotype        = p->iotype;
3103                 uart.port.flags         = p->flags;
3104                 uart.port.mapbase       = p->mapbase;
3105                 uart.port.hub6          = p->hub6;
3106                 uart.port.private_data  = p->private_data;
3107                 uart.port.type          = p->type;
3108                 uart.port.serial_in     = p->serial_in;
3109                 uart.port.serial_out    = p->serial_out;
3110                 uart.port.handle_irq    = p->handle_irq;
3111                 uart.port.handle_break  = p->handle_break;
3112                 uart.port.set_termios   = p->set_termios;
3113                 uart.port.pm            = p->pm;
3114                 uart.port.dev           = &dev->dev;
3115                 uart.port.irqflags      |= irqflag;
3116                 ret = serial8250_register_8250_port(&uart);
3117                 if (ret < 0) {
3118                         dev_err(&dev->dev, "unable to register port at index %d "
3119                                 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3120                                 p->iobase, (unsigned long long)p->mapbase,
3121                                 p->irq, ret);
3122                 }
3123         }
3124         return 0;
3125 }
3126 
3127 /*
3128  * Remove serial ports registered against a platform device.
3129  */
3130 static int serial8250_remove(struct platform_device *dev)
3131 {
3132         int i;
3133 
3134         for (i = 0; i < nr_uarts; i++) {
3135                 struct uart_8250_port *up = &serial8250_ports[i];
3136 
3137                 if (up->port.dev == &dev->dev)
3138                         serial8250_unregister_port(i);
3139         }
3140         return 0;
3141 }
3142 
3143 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3144 {
3145         int i;
3146 
3147         for (i = 0; i < UART_NR; i++) {
3148                 struct uart_8250_port *up = &serial8250_ports[i];
3149 
3150                 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3151                         uart_suspend_port(&serial8250_reg, &up->port);
3152         }
3153 
3154         return 0;
3155 }
3156 
3157 static int serial8250_resume(struct platform_device *dev)
3158 {
3159         int i;
3160 
3161         for (i = 0; i < UART_NR; i++) {
3162                 struct uart_8250_port *up = &serial8250_ports[i];
3163 
3164                 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3165                         serial8250_resume_port(i);
3166         }
3167 
3168         return 0;
3169 }
3170 
3171 static struct platform_driver serial8250_isa_driver = {
3172         .probe          = serial8250_probe,
3173         .remove         = serial8250_remove,
3174         .suspend        = serial8250_suspend,
3175         .resume         = serial8250_resume,
3176         .driver         = {
3177                 .name   = "serial8250",
3178                 .owner  = THIS_MODULE,
3179         },
3180 };
3181 
3182 /*
3183  * This "device" covers _all_ ISA 8250-compatible serial devices listed
3184  * in the table in include/asm/serial.h
3185  */
3186 static struct platform_device *serial8250_isa_devs;
3187 
3188 /*
3189  * serial8250_register_8250_port and serial8250_unregister_port allows for
3190  * 16x50 serial ports to be configured at run-time, to support PCMCIA
3191  * modems and PCI multiport cards.
3192  */
3193 static DEFINE_MUTEX(serial_mutex);
3194 
3195 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3196 {
3197         int i;
3198 
3199         /*
3200          * First, find a port entry which matches.
3201          */
3202         for (i = 0; i < nr_uarts; i++)
3203                 if (uart_match_port(&serial8250_ports[i].port, port))
3204                         return &serial8250_ports[i];
3205 
3206         /*
3207          * We didn't find a matching entry, so look for the first
3208          * free entry.  We look for one which hasn't been previously
3209          * used (indicated by zero iobase).
3210          */
3211         for (i = 0; i < nr_uarts; i++)
3212                 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3213                     serial8250_ports[i].port.iobase == 0)
3214                         return &serial8250_ports[i];
3215 
3216         /*
3217          * That also failed.  Last resort is to find any entry which
3218          * doesn't have a real port associated with it.
3219          */
3220         for (i = 0; i < nr_uarts; i++)
3221                 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3222                         return &serial8250_ports[i];
3223 
3224         return NULL;
3225 }
3226 
3227 /**
3228  *      serial8250_register_8250_port - register a serial port
3229  *      @up: serial port template
3230  *
3231  *      Configure the serial port specified by the request. If the
3232  *      port exists and is in use, it is hung up and unregistered
3233  *      first.
3234  *
3235  *      The port is then probed and if necessary the IRQ is autodetected
3236  *      If this fails an error is returned.
3237  *
3238  *      On success the port is ready to use and the line number is returned.
3239  */
3240 int serial8250_register_8250_port(struct uart_8250_port *up)
3241 {
3242         struct uart_8250_port *uart;
3243         int ret = -ENOSPC;
3244 
3245         if (up->port.uartclk == 0)
3246                 return -EINVAL;
3247 
3248         mutex_lock(&serial_mutex);
3249 
3250         uart = serial8250_find_match_or_unused(&up->port);
3251         if (uart && uart->port.type != PORT_8250_CIR) {
3252                 if (uart->port.dev)
3253                         uart_remove_one_port(&serial8250_reg, &uart->port);
3254 
3255                 uart->port.iobase       = up->port.iobase;
3256                 uart->port.membase      = up->port.membase;
3257                 uart->port.irq          = up->port.irq;
3258                 uart->port.irqflags     = up->port.irqflags;
3259                 uart->port.uartclk      = up->port.uartclk;
3260                 uart->port.fifosize     = up->port.fifosize;
3261                 uart->port.regshift     = up->port.regshift;
3262                 uart->port.iotype       = up->port.iotype;
3263                 uart->port.flags        = up->port.flags | UPF_BOOT_AUTOCONF;
3264                 uart->bugs              = up->bugs;
3265                 uart->port.mapbase      = up->port.mapbase;
3266                 uart->port.private_data = up->port.private_data;
3267                 uart->port.fifosize     = up->port.fifosize;
3268                 uart->tx_loadsz         = up->tx_loadsz;
3269                 uart->capabilities      = up->capabilities;
3270 
3271                 /* Take tx_loadsz from fifosize if it wasn't set separately */
3272                 if (uart->port.fifosize && !uart->tx_loadsz)
3273                         uart->tx_loadsz = uart->port.fifosize;
3274 
3275                 if (up->port.dev)
3276                         uart->port.dev = up->port.dev;
3277 
3278                 if (up->port.flags & UPF_FIXED_TYPE)
3279                         serial8250_init_fixed_type_port(uart, up->port.type);
3280 
3281                 set_io_from_upio(&uart->port);
3282                 /* Possibly override default I/O functions.  */
3283                 if (up->port.serial_in)
3284                         uart->port.serial_in = up->port.serial_in;
3285                 if (up->port.serial_out)
3286                         uart->port.serial_out = up->port.serial_out;
3287                 if (up->port.handle_irq)
3288                         uart->port.handle_irq = up->port.handle_irq;
3289                 /*  Possibly override set_termios call */
3290                 if (up->port.set_termios)
3291                         uart->port.set_termios = up->port.set_termios;
3292                 if (up->port.pm)
3293                         uart->port.pm = up->port.pm;
3294                 if (up->port.handle_break)
3295                         uart->port.handle_break = up->port.handle_break;
3296                 if (up->dl_read)
3297                         uart->dl_read = up->dl_read;
3298                 if (up->dl_write)
3299                         uart->dl_write = up->dl_write;
3300                 if (up->dma)
3301                         uart->dma = up->dma;
3302 
3303                 if (serial8250_isa_config != NULL)
3304                         serial8250_isa_config(0, &uart->port,
3305                                         &uart->capabilities);
3306 
3307                 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3308                 if (ret == 0)
3309                         ret = uart->port.line;
3310         }
3311         mutex_unlock(&serial_mutex);
3312 
3313         return ret;
3314 }
3315 EXPORT_SYMBOL(serial8250_register_8250_port);
3316 
3317 /**
3318  *      serial8250_unregister_port - remove a 16x50 serial port at runtime
3319  *      @line: serial line number
3320  *
3321  *      Remove one serial port.  This may not be called from interrupt
3322  *      context.  We hand the port back to the our control.
3323  */
3324 void serial8250_unregister_port(int line)
3325 {
3326         struct uart_8250_port *uart = &serial8250_ports[line];
3327 
3328         mutex_lock(&serial_mutex);
3329         uart_remove_one_port(&serial8250_reg, &uart->port);
3330         if (serial8250_isa_devs) {
3331                 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3332                 uart->port.type = PORT_UNKNOWN;
3333                 uart->port.dev = &serial8250_isa_devs->dev;
3334                 uart->capabilities = uart_config[uart->port.type].flags;
3335                 uart_add_one_port(&serial8250_reg, &uart->port);
3336         } else {
3337                 uart->port.dev = NULL;
3338         }
3339         mutex_unlock(&serial_mutex);
3340 }
3341 EXPORT_SYMBOL(serial8250_unregister_port);
3342 
3343 static int __init serial8250_init(void)
3344 {
3345         int ret;
3346 
3347         serial8250_isa_init_ports();
3348 
3349         printk(KERN_INFO "Serial: 8250/16550 driver, "
3350                 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3351                 share_irqs ? "en" : "dis");
3352 
3353 #ifdef CONFIG_SPARC
3354         ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3355 #else
3356         serial8250_reg.nr = UART_NR;
3357         ret = uart_register_driver(&serial8250_reg);
3358 #endif
3359         if (ret)
3360                 goto out;
3361 
3362         ret = serial8250_pnp_init();
3363         if (ret)
3364                 goto unreg_uart_drv;
3365 
3366         serial8250_isa_devs = platform_device_alloc("serial8250",
3367                                                     PLAT8250_DEV_LEGACY);
3368         if (!serial8250_isa_devs) {
3369                 ret = -ENOMEM;
3370                 goto unreg_pnp;
3371         }
3372 
3373         ret = platform_device_add(serial8250_isa_devs);
3374         if (ret)
3375                 goto put_dev;
3376 
3377         serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3378 
3379         ret = platform_driver_register(&serial8250_isa_driver);
3380         if (ret == 0)
3381                 goto out;
3382 
3383         platform_device_del(serial8250_isa_devs);
3384 put_dev:
3385         platform_device_put(serial8250_isa_devs);
3386 unreg_pnp:
3387         serial8250_pnp_exit();
3388 unreg_uart_drv:
3389 #ifdef CONFIG_SPARC
3390         sunserial_unregister_minors(&serial8250_reg, UART_NR);
3391 #else
3392         uart_unregister_driver(&serial8250_reg);
3393 #endif
3394 out:
3395         return ret;
3396 }
3397 
3398 static void __exit serial8250_exit(void)
3399 {
3400         struct platform_device *isa_dev = serial8250_isa_devs;
3401 
3402         /*
3403          * This tells serial8250_unregister_port() not to re-register
3404          * the ports (thereby making serial8250_isa_driver permanently
3405          * in use.)
3406          */
3407         serial8250_isa_devs = NULL;
3408 
3409         platform_driver_unregister(&serial8250_isa_driver);
3410         platform_device_unregister(isa_dev);
3411 
3412         serial8250_pnp_exit();
3413 
3414 #ifdef CONFIG_SPARC
3415         sunserial_unregister_minors(&serial8250_reg, UART_NR);
3416 #else
3417         uart_unregister_driver(&serial8250_reg);
3418 #endif
3419 }
3420 
3421 module_init(serial8250_init);
3422 module_exit(serial8250_exit);
3423 
3424 EXPORT_SYMBOL(serial8250_suspend_port);
3425 EXPORT_SYMBOL(serial8250_resume_port);
3426 
3427 MODULE_LICENSE("GPL");
3428 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3429 
3430 module_param(share_irqs, uint, 0644);
3431 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3432         " (unsafe)");
3433 
3434 module_param(nr_uarts, uint, 0644);
3435 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3436 
3437 module_param(skip_txen_test, uint, 0644);
3438 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3439 
3440 #ifdef CONFIG_SERIAL_8250_RSA
3441 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3442 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3443 #endif
3444 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
3445 
3446 #ifdef CONFIG_SERIAL_8250_DEPRECATED_OPTIONS
3447 #ifndef MODULE
3448 /* This module was renamed to 8250_core in 3.7.  Keep the old "8250" name
3449  * working as well for the module options so we don't break people.  We
3450  * need to keep the names identical and the convenient macros will happily
3451  * refuse to let us do that by failing the build with redefinition errors
3452  * of global variables.  So we stick them inside a dummy function to avoid
3453  * those conflicts.  The options still get parsed, and the redefined
3454  * MODULE_PARAM_PREFIX lets us keep the "8250." syntax alive.
3455  *
3456  * This is hacky.  I'm sorry.
3457  */
3458 static void __used s8250_options(void)
3459 {
3460 #undef MODULE_PARAM_PREFIX
3461 #define MODULE_PARAM_PREFIX "8250_core."
3462 
3463         module_param_cb(share_irqs, &param_ops_uint, &share_irqs, 0644);
3464         module_param_cb(nr_uarts, &param_ops_uint, &nr_uarts, 0644);
3465         module_param_cb(skip_txen_test, &param_ops_uint, &skip_txen_test, 0644);
3466 #ifdef CONFIG_SERIAL_8250_RSA
3467         __module_param_call(MODULE_PARAM_PREFIX, probe_rsa,
3468                 &param_array_ops, .arr = &__param_arr_probe_rsa,
3469                 0444, -1);
3470 #endif
3471 }
3472 #else
3473 MODULE_ALIAS("8250_core");
3474 #endif
3475 #endif
3476 

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