Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/tty/serial/8250/8250_core.c

  1 /*
  2  *  Driver for 8250/16550-type serial ports
  3  *
  4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  5  *
  6  *  Copyright (C) 2001 Russell King.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * A note about mapbase / membase
 14  *
 15  *  mapbase is the physical address of the IO port.
 16  *  membase is an 'ioremapped' cookie.
 17  */
 18 
 19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 20 #define SUPPORT_SYSRQ
 21 #endif
 22 
 23 #include <linux/module.h>
 24 #include <linux/moduleparam.h>
 25 #include <linux/ioport.h>
 26 #include <linux/init.h>
 27 #include <linux/console.h>
 28 #include <linux/sysrq.h>
 29 #include <linux/delay.h>
 30 #include <linux/platform_device.h>
 31 #include <linux/tty.h>
 32 #include <linux/ratelimit.h>
 33 #include <linux/tty_flip.h>
 34 #include <linux/serial_core.h>
 35 #include <linux/serial.h>
 36 #include <linux/serial_8250.h>
 37 #include <linux/nmi.h>
 38 #include <linux/mutex.h>
 39 #include <linux/slab.h>
 40 #ifdef CONFIG_SPARC
 41 #include <linux/sunserialcore.h>
 42 #endif
 43 
 44 #include <asm/io.h>
 45 #include <asm/irq.h>
 46 
 47 #include "8250.h"
 48 
 49 /*
 50  * Configuration:
 51  *   share_irqs - whether we pass IRQF_SHARED to request_irq().  This option
 52  *                is unsafe when used on edge-triggered interrupts.
 53  */
 54 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
 55 
 56 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
 57 
 58 static struct uart_driver serial8250_reg;
 59 
 60 static int serial_index(struct uart_port *port)
 61 {
 62         return (serial8250_reg.minor - 64) + port->line;
 63 }
 64 
 65 static unsigned int skip_txen_test; /* force skip of txen test at init time */
 66 
 67 /*
 68  * Debugging.
 69  */
 70 #if 0
 71 #define DEBUG_AUTOCONF(fmt...)  printk(fmt)
 72 #else
 73 #define DEBUG_AUTOCONF(fmt...)  do { } while (0)
 74 #endif
 75 
 76 #if 0
 77 #define DEBUG_INTR(fmt...)      printk(fmt)
 78 #else
 79 #define DEBUG_INTR(fmt...)      do { } while (0)
 80 #endif
 81 
 82 #define PASS_LIMIT      512
 83 
 84 #define BOTH_EMPTY      (UART_LSR_TEMT | UART_LSR_THRE)
 85 
 86 
 87 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
 88 #define CONFIG_SERIAL_DETECT_IRQ 1
 89 #endif
 90 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
 91 #define CONFIG_SERIAL_MANY_PORTS 1
 92 #endif
 93 
 94 /*
 95  * HUB6 is always on.  This will be removed once the header
 96  * files have been cleaned.
 97  */
 98 #define CONFIG_HUB6 1
 99 
100 #include <asm/serial.h>
101 /*
102  * SERIAL_PORT_DFNS tells us about built-in ports that have no
103  * standard enumeration mechanism.   Platforms that can find all
104  * serial ports via mechanisms like ACPI or PCI need not supply it.
105  */
106 #ifndef SERIAL_PORT_DFNS
107 #define SERIAL_PORT_DFNS
108 #endif
109 
110 static const struct old_serial_port old_serial_port[] = {
111         SERIAL_PORT_DFNS /* defined in asm/serial.h */
112 };
113 
114 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
115 
116 #ifdef CONFIG_SERIAL_8250_RSA
117 
118 #define PORT_RSA_MAX 4
119 static unsigned long probe_rsa[PORT_RSA_MAX];
120 static unsigned int probe_rsa_count;
121 #endif /* CONFIG_SERIAL_8250_RSA  */
122 
123 struct irq_info {
124         struct                  hlist_node node;
125         int                     irq;
126         spinlock_t              lock;   /* Protects list not the hash */
127         struct list_head        *head;
128 };
129 
130 #define NR_IRQ_HASH             32      /* Can be adjusted later */
131 static struct hlist_head irq_lists[NR_IRQ_HASH];
132 static DEFINE_MUTEX(hash_mutex);        /* Used to walk the hash */
133 
134 /*
135  * Here we define the default xmit fifo size used for each type of UART.
136  */
137 static const struct serial8250_config uart_config[] = {
138         [PORT_UNKNOWN] = {
139                 .name           = "unknown",
140                 .fifo_size      = 1,
141                 .tx_loadsz      = 1,
142         },
143         [PORT_8250] = {
144                 .name           = "8250",
145                 .fifo_size      = 1,
146                 .tx_loadsz      = 1,
147         },
148         [PORT_16450] = {
149                 .name           = "16450",
150                 .fifo_size      = 1,
151                 .tx_loadsz      = 1,
152         },
153         [PORT_16550] = {
154                 .name           = "16550",
155                 .fifo_size      = 1,
156                 .tx_loadsz      = 1,
157         },
158         [PORT_16550A] = {
159                 .name           = "16550A",
160                 .fifo_size      = 16,
161                 .tx_loadsz      = 16,
162                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
163                 .rxtrig_bytes   = {1, 4, 8, 14},
164                 .flags          = UART_CAP_FIFO,
165         },
166         [PORT_CIRRUS] = {
167                 .name           = "Cirrus",
168                 .fifo_size      = 1,
169                 .tx_loadsz      = 1,
170         },
171         [PORT_16650] = {
172                 .name           = "ST16650",
173                 .fifo_size      = 1,
174                 .tx_loadsz      = 1,
175                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
176         },
177         [PORT_16650V2] = {
178                 .name           = "ST16650V2",
179                 .fifo_size      = 32,
180                 .tx_loadsz      = 16,
181                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
182                                   UART_FCR_T_TRIG_00,
183                 .rxtrig_bytes   = {8, 16, 24, 28},
184                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
185         },
186         [PORT_16750] = {
187                 .name           = "TI16750",
188                 .fifo_size      = 64,
189                 .tx_loadsz      = 64,
190                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
191                                   UART_FCR7_64BYTE,
192                 .rxtrig_bytes   = {1, 16, 32, 56},
193                 .flags          = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
194         },
195         [PORT_STARTECH] = {
196                 .name           = "Startech",
197                 .fifo_size      = 1,
198                 .tx_loadsz      = 1,
199         },
200         [PORT_16C950] = {
201                 .name           = "16C950/954",
202                 .fifo_size      = 128,
203                 .tx_loadsz      = 128,
204                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
205                 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
206                 .flags          = UART_CAP_FIFO | UART_CAP_SLEEP,
207         },
208         [PORT_16654] = {
209                 .name           = "ST16654",
210                 .fifo_size      = 64,
211                 .tx_loadsz      = 32,
212                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
213                                   UART_FCR_T_TRIG_10,
214                 .rxtrig_bytes   = {8, 16, 56, 60},
215                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
216         },
217         [PORT_16850] = {
218                 .name           = "XR16850",
219                 .fifo_size      = 128,
220                 .tx_loadsz      = 128,
221                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
222                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
223         },
224         [PORT_RSA] = {
225                 .name           = "RSA",
226                 .fifo_size      = 2048,
227                 .tx_loadsz      = 2048,
228                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
229                 .flags          = UART_CAP_FIFO,
230         },
231         [PORT_NS16550A] = {
232                 .name           = "NS16550A",
233                 .fifo_size      = 16,
234                 .tx_loadsz      = 16,
235                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
236                 .flags          = UART_CAP_FIFO | UART_NATSEMI,
237         },
238         [PORT_XSCALE] = {
239                 .name           = "XScale",
240                 .fifo_size      = 32,
241                 .tx_loadsz      = 32,
242                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243                 .flags          = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
244         },
245         [PORT_OCTEON] = {
246                 .name           = "OCTEON",
247                 .fifo_size      = 64,
248                 .tx_loadsz      = 64,
249                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
250                 .flags          = UART_CAP_FIFO,
251         },
252         [PORT_AR7] = {
253                 .name           = "AR7",
254                 .fifo_size      = 16,
255                 .tx_loadsz      = 16,
256                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
257                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
258         },
259         [PORT_U6_16550A] = {
260                 .name           = "U6_16550A",
261                 .fifo_size      = 64,
262                 .tx_loadsz      = 64,
263                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
264                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
265         },
266         [PORT_TEGRA] = {
267                 .name           = "Tegra",
268                 .fifo_size      = 32,
269                 .tx_loadsz      = 8,
270                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
271                                   UART_FCR_T_TRIG_01,
272                 .rxtrig_bytes   = {1, 4, 8, 14},
273                 .flags          = UART_CAP_FIFO | UART_CAP_RTOIE,
274         },
275         [PORT_XR17D15X] = {
276                 .name           = "XR17D15X",
277                 .fifo_size      = 64,
278                 .tx_loadsz      = 64,
279                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
280                 .flags          = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
281                                   UART_CAP_SLEEP,
282         },
283         [PORT_XR17V35X] = {
284                 .name           = "XR17V35X",
285                 .fifo_size      = 256,
286                 .tx_loadsz      = 256,
287                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
288                                   UART_FCR_T_TRIG_11,
289                 .flags          = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
290                                   UART_CAP_SLEEP,
291         },
292         [PORT_LPC3220] = {
293                 .name           = "LPC3220",
294                 .fifo_size      = 64,
295                 .tx_loadsz      = 32,
296                 .fcr            = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
297                                   UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
298                 .flags          = UART_CAP_FIFO,
299         },
300         [PORT_BRCM_TRUMANAGE] = {
301                 .name           = "TruManage",
302                 .fifo_size      = 1,
303                 .tx_loadsz      = 1024,
304                 .flags          = UART_CAP_HFIFO,
305         },
306         [PORT_8250_CIR] = {
307                 .name           = "CIR port"
308         },
309         [PORT_ALTR_16550_F32] = {
310                 .name           = "Altera 16550 FIFO32",
311                 .fifo_size      = 32,
312                 .tx_loadsz      = 32,
313                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
314                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
315         },
316         [PORT_ALTR_16550_F64] = {
317                 .name           = "Altera 16550 FIFO64",
318                 .fifo_size      = 64,
319                 .tx_loadsz      = 64,
320                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
321                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
322         },
323         [PORT_ALTR_16550_F128] = {
324                 .name           = "Altera 16550 FIFO128",
325                 .fifo_size      = 128,
326                 .tx_loadsz      = 128,
327                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
328                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
329         },
330 };
331 
332 /* Uart divisor latch read */
333 static int default_serial_dl_read(struct uart_8250_port *up)
334 {
335         return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
336 }
337 
338 /* Uart divisor latch write */
339 static void default_serial_dl_write(struct uart_8250_port *up, int value)
340 {
341         serial_out(up, UART_DLL, value & 0xff);
342         serial_out(up, UART_DLM, value >> 8 & 0xff);
343 }
344 
345 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
346 
347 /* Au1x00/RT288x UART hardware has a weird register layout */
348 static const u8 au_io_in_map[] = {
349         [UART_RX]  = 0,
350         [UART_IER] = 2,
351         [UART_IIR] = 3,
352         [UART_LCR] = 5,
353         [UART_MCR] = 6,
354         [UART_LSR] = 7,
355         [UART_MSR] = 8,
356 };
357 
358 static const u8 au_io_out_map[] = {
359         [UART_TX]  = 1,
360         [UART_IER] = 2,
361         [UART_FCR] = 4,
362         [UART_LCR] = 5,
363         [UART_MCR] = 6,
364 };
365 
366 static unsigned int au_serial_in(struct uart_port *p, int offset)
367 {
368         offset = au_io_in_map[offset] << p->regshift;
369         return __raw_readl(p->membase + offset);
370 }
371 
372 static void au_serial_out(struct uart_port *p, int offset, int value)
373 {
374         offset = au_io_out_map[offset] << p->regshift;
375         __raw_writel(value, p->membase + offset);
376 }
377 
378 /* Au1x00 haven't got a standard divisor latch */
379 static int au_serial_dl_read(struct uart_8250_port *up)
380 {
381         return __raw_readl(up->port.membase + 0x28);
382 }
383 
384 static void au_serial_dl_write(struct uart_8250_port *up, int value)
385 {
386         __raw_writel(value, up->port.membase + 0x28);
387 }
388 
389 #endif
390 
391 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
392 {
393         offset = offset << p->regshift;
394         outb(p->hub6 - 1 + offset, p->iobase);
395         return inb(p->iobase + 1);
396 }
397 
398 static void hub6_serial_out(struct uart_port *p, int offset, int value)
399 {
400         offset = offset << p->regshift;
401         outb(p->hub6 - 1 + offset, p->iobase);
402         outb(value, p->iobase + 1);
403 }
404 
405 static unsigned int mem_serial_in(struct uart_port *p, int offset)
406 {
407         offset = offset << p->regshift;
408         return readb(p->membase + offset);
409 }
410 
411 static void mem_serial_out(struct uart_port *p, int offset, int value)
412 {
413         offset = offset << p->regshift;
414         writeb(value, p->membase + offset);
415 }
416 
417 static void mem32_serial_out(struct uart_port *p, int offset, int value)
418 {
419         offset = offset << p->regshift;
420         writel(value, p->membase + offset);
421 }
422 
423 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
424 {
425         offset = offset << p->regshift;
426         return readl(p->membase + offset);
427 }
428 
429 static unsigned int io_serial_in(struct uart_port *p, int offset)
430 {
431         offset = offset << p->regshift;
432         return inb(p->iobase + offset);
433 }
434 
435 static void io_serial_out(struct uart_port *p, int offset, int value)
436 {
437         offset = offset << p->regshift;
438         outb(value, p->iobase + offset);
439 }
440 
441 static int serial8250_default_handle_irq(struct uart_port *port);
442 static int exar_handle_irq(struct uart_port *port);
443 
444 static void set_io_from_upio(struct uart_port *p)
445 {
446         struct uart_8250_port *up = up_to_u8250p(p);
447 
448         up->dl_read = default_serial_dl_read;
449         up->dl_write = default_serial_dl_write;
450 
451         switch (p->iotype) {
452         case UPIO_HUB6:
453                 p->serial_in = hub6_serial_in;
454                 p->serial_out = hub6_serial_out;
455                 break;
456 
457         case UPIO_MEM:
458                 p->serial_in = mem_serial_in;
459                 p->serial_out = mem_serial_out;
460                 break;
461 
462         case UPIO_MEM32:
463                 p->serial_in = mem32_serial_in;
464                 p->serial_out = mem32_serial_out;
465                 break;
466 
467 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
468         case UPIO_AU:
469                 p->serial_in = au_serial_in;
470                 p->serial_out = au_serial_out;
471                 up->dl_read = au_serial_dl_read;
472                 up->dl_write = au_serial_dl_write;
473                 break;
474 #endif
475 
476         default:
477                 p->serial_in = io_serial_in;
478                 p->serial_out = io_serial_out;
479                 break;
480         }
481         /* Remember loaded iotype */
482         up->cur_iotype = p->iotype;
483         p->handle_irq = serial8250_default_handle_irq;
484 }
485 
486 static void
487 serial_port_out_sync(struct uart_port *p, int offset, int value)
488 {
489         switch (p->iotype) {
490         case UPIO_MEM:
491         case UPIO_MEM32:
492         case UPIO_AU:
493                 p->serial_out(p, offset, value);
494                 p->serial_in(p, UART_LCR);      /* safe, no side-effects */
495                 break;
496         default:
497                 p->serial_out(p, offset, value);
498         }
499 }
500 
501 /*
502  * For the 16C950
503  */
504 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
505 {
506         serial_out(up, UART_SCR, offset);
507         serial_out(up, UART_ICR, value);
508 }
509 
510 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
511 {
512         unsigned int value;
513 
514         serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
515         serial_out(up, UART_SCR, offset);
516         value = serial_in(up, UART_ICR);
517         serial_icr_write(up, UART_ACR, up->acr);
518 
519         return value;
520 }
521 
522 /*
523  * FIFO support.
524  */
525 static void serial8250_clear_fifos(struct uart_8250_port *p)
526 {
527         if (p->capabilities & UART_CAP_FIFO) {
528                 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
529                 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
530                                UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
531                 serial_out(p, UART_FCR, 0);
532         }
533 }
534 
535 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
536 {
537         serial8250_clear_fifos(p);
538         serial_out(p, UART_FCR, p->fcr);
539 }
540 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
541 
542 /*
543  * IER sleep support.  UARTs which have EFRs need the "extended
544  * capability" bit enabled.  Note that on XR16C850s, we need to
545  * reset LCR to write to IER.
546  */
547 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
548 {
549         /*
550          * Exar UARTs have a SLEEP register that enables or disables
551          * each UART to enter sleep mode separately.  On the XR17V35x the
552          * register is accessible to each UART at the UART_EXAR_SLEEP
553          * offset but the UART channel may only write to the corresponding
554          * bit.
555          */
556         if ((p->port.type == PORT_XR17V35X) ||
557            (p->port.type == PORT_XR17D15X)) {
558                 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
559                 return;
560         }
561 
562         if (p->capabilities & UART_CAP_SLEEP) {
563                 if (p->capabilities & UART_CAP_EFR) {
564                         serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
565                         serial_out(p, UART_EFR, UART_EFR_ECB);
566                         serial_out(p, UART_LCR, 0);
567                 }
568                 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
569                 if (p->capabilities & UART_CAP_EFR) {
570                         serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
571                         serial_out(p, UART_EFR, 0);
572                         serial_out(p, UART_LCR, 0);
573                 }
574         }
575 }
576 
577 #ifdef CONFIG_SERIAL_8250_RSA
578 /*
579  * Attempts to turn on the RSA FIFO.  Returns zero on failure.
580  * We set the port uart clock rate if we succeed.
581  */
582 static int __enable_rsa(struct uart_8250_port *up)
583 {
584         unsigned char mode;
585         int result;
586 
587         mode = serial_in(up, UART_RSA_MSR);
588         result = mode & UART_RSA_MSR_FIFO;
589 
590         if (!result) {
591                 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
592                 mode = serial_in(up, UART_RSA_MSR);
593                 result = mode & UART_RSA_MSR_FIFO;
594         }
595 
596         if (result)
597                 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
598 
599         return result;
600 }
601 
602 static void enable_rsa(struct uart_8250_port *up)
603 {
604         if (up->port.type == PORT_RSA) {
605                 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
606                         spin_lock_irq(&up->port.lock);
607                         __enable_rsa(up);
608                         spin_unlock_irq(&up->port.lock);
609                 }
610                 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
611                         serial_out(up, UART_RSA_FRR, 0);
612         }
613 }
614 
615 /*
616  * Attempts to turn off the RSA FIFO.  Returns zero on failure.
617  * It is unknown why interrupts were disabled in here.  However,
618  * the caller is expected to preserve this behaviour by grabbing
619  * the spinlock before calling this function.
620  */
621 static void disable_rsa(struct uart_8250_port *up)
622 {
623         unsigned char mode;
624         int result;
625 
626         if (up->port.type == PORT_RSA &&
627             up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
628                 spin_lock_irq(&up->port.lock);
629 
630                 mode = serial_in(up, UART_RSA_MSR);
631                 result = !(mode & UART_RSA_MSR_FIFO);
632 
633                 if (!result) {
634                         serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
635                         mode = serial_in(up, UART_RSA_MSR);
636                         result = !(mode & UART_RSA_MSR_FIFO);
637                 }
638 
639                 if (result)
640                         up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
641                 spin_unlock_irq(&up->port.lock);
642         }
643 }
644 #endif /* CONFIG_SERIAL_8250_RSA */
645 
646 /*
647  * This is a quickie test to see how big the FIFO is.
648  * It doesn't work at all the time, more's the pity.
649  */
650 static int size_fifo(struct uart_8250_port *up)
651 {
652         unsigned char old_fcr, old_mcr, old_lcr;
653         unsigned short old_dl;
654         int count;
655 
656         old_lcr = serial_in(up, UART_LCR);
657         serial_out(up, UART_LCR, 0);
658         old_fcr = serial_in(up, UART_FCR);
659         old_mcr = serial_in(up, UART_MCR);
660         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
661                     UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
662         serial_out(up, UART_MCR, UART_MCR_LOOP);
663         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
664         old_dl = serial_dl_read(up);
665         serial_dl_write(up, 0x0001);
666         serial_out(up, UART_LCR, 0x03);
667         for (count = 0; count < 256; count++)
668                 serial_out(up, UART_TX, count);
669         mdelay(20);/* FIXME - schedule_timeout */
670         for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
671              (count < 256); count++)
672                 serial_in(up, UART_RX);
673         serial_out(up, UART_FCR, old_fcr);
674         serial_out(up, UART_MCR, old_mcr);
675         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
676         serial_dl_write(up, old_dl);
677         serial_out(up, UART_LCR, old_lcr);
678 
679         return count;
680 }
681 
682 /*
683  * Read UART ID using the divisor method - set DLL and DLM to zero
684  * and the revision will be in DLL and device type in DLM.  We
685  * preserve the device state across this.
686  */
687 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
688 {
689         unsigned char old_dll, old_dlm, old_lcr;
690         unsigned int id;
691 
692         old_lcr = serial_in(p, UART_LCR);
693         serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
694 
695         old_dll = serial_in(p, UART_DLL);
696         old_dlm = serial_in(p, UART_DLM);
697 
698         serial_out(p, UART_DLL, 0);
699         serial_out(p, UART_DLM, 0);
700 
701         id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
702 
703         serial_out(p, UART_DLL, old_dll);
704         serial_out(p, UART_DLM, old_dlm);
705         serial_out(p, UART_LCR, old_lcr);
706 
707         return id;
708 }
709 
710 /*
711  * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
712  * When this function is called we know it is at least a StarTech
713  * 16650 V2, but it might be one of several StarTech UARTs, or one of
714  * its clones.  (We treat the broken original StarTech 16650 V1 as a
715  * 16550, and why not?  Startech doesn't seem to even acknowledge its
716  * existence.)
717  *
718  * What evil have men's minds wrought...
719  */
720 static void autoconfig_has_efr(struct uart_8250_port *up)
721 {
722         unsigned int id1, id2, id3, rev;
723 
724         /*
725          * Everything with an EFR has SLEEP
726          */
727         up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
728 
729         /*
730          * First we check to see if it's an Oxford Semiconductor UART.
731          *
732          * If we have to do this here because some non-National
733          * Semiconductor clone chips lock up if you try writing to the
734          * LSR register (which serial_icr_read does)
735          */
736 
737         /*
738          * Check for Oxford Semiconductor 16C950.
739          *
740          * EFR [4] must be set else this test fails.
741          *
742          * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
743          * claims that it's needed for 952 dual UART's (which are not
744          * recommended for new designs).
745          */
746         up->acr = 0;
747         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
748         serial_out(up, UART_EFR, UART_EFR_ECB);
749         serial_out(up, UART_LCR, 0x00);
750         id1 = serial_icr_read(up, UART_ID1);
751         id2 = serial_icr_read(up, UART_ID2);
752         id3 = serial_icr_read(up, UART_ID3);
753         rev = serial_icr_read(up, UART_REV);
754 
755         DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
756 
757         if (id1 == 0x16 && id2 == 0xC9 &&
758             (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
759                 up->port.type = PORT_16C950;
760 
761                 /*
762                  * Enable work around for the Oxford Semiconductor 952 rev B
763                  * chip which causes it to seriously miscalculate baud rates
764                  * when DLL is 0.
765                  */
766                 if (id3 == 0x52 && rev == 0x01)
767                         up->bugs |= UART_BUG_QUOT;
768                 return;
769         }
770 
771         /*
772          * We check for a XR16C850 by setting DLL and DLM to 0, and then
773          * reading back DLL and DLM.  The chip type depends on the DLM
774          * value read back:
775          *  0x10 - XR16C850 and the DLL contains the chip revision.
776          *  0x12 - XR16C2850.
777          *  0x14 - XR16C854.
778          */
779         id1 = autoconfig_read_divisor_id(up);
780         DEBUG_AUTOCONF("850id=%04x ", id1);
781 
782         id2 = id1 >> 8;
783         if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
784                 up->port.type = PORT_16850;
785                 return;
786         }
787 
788         /*
789          * It wasn't an XR16C850.
790          *
791          * We distinguish between the '654 and the '650 by counting
792          * how many bytes are in the FIFO.  I'm using this for now,
793          * since that's the technique that was sent to me in the
794          * serial driver update, but I'm not convinced this works.
795          * I've had problems doing this in the past.  -TYT
796          */
797         if (size_fifo(up) == 64)
798                 up->port.type = PORT_16654;
799         else
800                 up->port.type = PORT_16650V2;
801 }
802 
803 /*
804  * We detected a chip without a FIFO.  Only two fall into
805  * this category - the original 8250 and the 16450.  The
806  * 16450 has a scratch register (accessible with LCR=0)
807  */
808 static void autoconfig_8250(struct uart_8250_port *up)
809 {
810         unsigned char scratch, status1, status2;
811 
812         up->port.type = PORT_8250;
813 
814         scratch = serial_in(up, UART_SCR);
815         serial_out(up, UART_SCR, 0xa5);
816         status1 = serial_in(up, UART_SCR);
817         serial_out(up, UART_SCR, 0x5a);
818         status2 = serial_in(up, UART_SCR);
819         serial_out(up, UART_SCR, scratch);
820 
821         if (status1 == 0xa5 && status2 == 0x5a)
822                 up->port.type = PORT_16450;
823 }
824 
825 static int broken_efr(struct uart_8250_port *up)
826 {
827         /*
828          * Exar ST16C2550 "A2" devices incorrectly detect as
829          * having an EFR, and report an ID of 0x0201.  See
830          * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html 
831          */
832         if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
833                 return 1;
834 
835         return 0;
836 }
837 
838 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
839 {
840         unsigned char status;
841 
842         status = serial_in(up, 0x04); /* EXCR2 */
843 #define PRESL(x) ((x) & 0x30)
844         if (PRESL(status) == 0x10) {
845                 /* already in high speed mode */
846                 return 0;
847         } else {
848                 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
849                 status |= 0x10;  /* 1.625 divisor for baud_base --> 921600 */
850                 serial_out(up, 0x04, status);
851         }
852         return 1;
853 }
854 
855 /*
856  * We know that the chip has FIFOs.  Does it have an EFR?  The
857  * EFR is located in the same register position as the IIR and
858  * we know the top two bits of the IIR are currently set.  The
859  * EFR should contain zero.  Try to read the EFR.
860  */
861 static void autoconfig_16550a(struct uart_8250_port *up)
862 {
863         unsigned char status1, status2;
864         unsigned int iersave;
865 
866         up->port.type = PORT_16550A;
867         up->capabilities |= UART_CAP_FIFO;
868 
869         /*
870          * XR17V35x UARTs have an extra divisor register, DLD
871          * that gets enabled with when DLAB is set which will
872          * cause the device to incorrectly match and assign
873          * port type to PORT_16650.  The EFR for this UART is
874          * found at offset 0x09. Instead check the Deice ID (DVID)
875          * register for a 2, 4 or 8 port UART.
876          */
877         if (up->port.flags & UPF_EXAR_EFR) {
878                 status1 = serial_in(up, UART_EXAR_DVID);
879                 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
880                         DEBUG_AUTOCONF("Exar XR17V35x ");
881                         up->port.type = PORT_XR17V35X;
882                         up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
883                                                 UART_CAP_SLEEP;
884 
885                         return;
886                 }
887 
888         }
889 
890         /*
891          * Check for presence of the EFR when DLAB is set.
892          * Only ST16C650V1 UARTs pass this test.
893          */
894         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
895         if (serial_in(up, UART_EFR) == 0) {
896                 serial_out(up, UART_EFR, 0xA8);
897                 if (serial_in(up, UART_EFR) != 0) {
898                         DEBUG_AUTOCONF("EFRv1 ");
899                         up->port.type = PORT_16650;
900                         up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
901                 } else {
902                         DEBUG_AUTOCONF("Motorola 8xxx DUART ");
903                 }
904                 serial_out(up, UART_EFR, 0);
905                 return;
906         }
907 
908         /*
909          * Maybe it requires 0xbf to be written to the LCR.
910          * (other ST16C650V2 UARTs, TI16C752A, etc)
911          */
912         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
913         if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
914                 DEBUG_AUTOCONF("EFRv2 ");
915                 autoconfig_has_efr(up);
916                 return;
917         }
918 
919         /*
920          * Check for a National Semiconductor SuperIO chip.
921          * Attempt to switch to bank 2, read the value of the LOOP bit
922          * from EXCR1. Switch back to bank 0, change it in MCR. Then
923          * switch back to bank 2, read it from EXCR1 again and check
924          * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
925          */
926         serial_out(up, UART_LCR, 0);
927         status1 = serial_in(up, UART_MCR);
928         serial_out(up, UART_LCR, 0xE0);
929         status2 = serial_in(up, 0x02); /* EXCR1 */
930 
931         if (!((status2 ^ status1) & UART_MCR_LOOP)) {
932                 serial_out(up, UART_LCR, 0);
933                 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
934                 serial_out(up, UART_LCR, 0xE0);
935                 status2 = serial_in(up, 0x02); /* EXCR1 */
936                 serial_out(up, UART_LCR, 0);
937                 serial_out(up, UART_MCR, status1);
938 
939                 if ((status2 ^ status1) & UART_MCR_LOOP) {
940                         unsigned short quot;
941 
942                         serial_out(up, UART_LCR, 0xE0);
943 
944                         quot = serial_dl_read(up);
945                         quot <<= 3;
946 
947                         if (ns16550a_goto_highspeed(up))
948                                 serial_dl_write(up, quot);
949 
950                         serial_out(up, UART_LCR, 0);
951 
952                         up->port.uartclk = 921600*16;
953                         up->port.type = PORT_NS16550A;
954                         up->capabilities |= UART_NATSEMI;
955                         return;
956                 }
957         }
958 
959         /*
960          * No EFR.  Try to detect a TI16750, which only sets bit 5 of
961          * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
962          * Try setting it with and without DLAB set.  Cheap clones
963          * set bit 5 without DLAB set.
964          */
965         serial_out(up, UART_LCR, 0);
966         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
967         status1 = serial_in(up, UART_IIR) >> 5;
968         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
969         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
970         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
971         status2 = serial_in(up, UART_IIR) >> 5;
972         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
973         serial_out(up, UART_LCR, 0);
974 
975         DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
976 
977         if (status1 == 6 && status2 == 7) {
978                 up->port.type = PORT_16750;
979                 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
980                 return;
981         }
982 
983         /*
984          * Try writing and reading the UART_IER_UUE bit (b6).
985          * If it works, this is probably one of the Xscale platform's
986          * internal UARTs.
987          * We're going to explicitly set the UUE bit to 0 before
988          * trying to write and read a 1 just to make sure it's not
989          * already a 1 and maybe locked there before we even start start.
990          */
991         iersave = serial_in(up, UART_IER);
992         serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
993         if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
994                 /*
995                  * OK it's in a known zero state, try writing and reading
996                  * without disturbing the current state of the other bits.
997                  */
998                 serial_out(up, UART_IER, iersave | UART_IER_UUE);
999                 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1000                         /*
1001                          * It's an Xscale.
1002                          * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1003                          */
1004                         DEBUG_AUTOCONF("Xscale ");
1005                         up->port.type = PORT_XSCALE;
1006                         up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1007                         return;
1008                 }
1009         } else {
1010                 /*
1011                  * If we got here we couldn't force the IER_UUE bit to 0.
1012                  * Log it and continue.
1013                  */
1014                 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1015         }
1016         serial_out(up, UART_IER, iersave);
1017 
1018         /*
1019          * Exar uarts have EFR in a weird location
1020          */
1021         if (up->port.flags & UPF_EXAR_EFR) {
1022                 DEBUG_AUTOCONF("Exar XR17D15x ");
1023                 up->port.type = PORT_XR17D15X;
1024                 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1025                                     UART_CAP_SLEEP;
1026 
1027                 return;
1028         }
1029 
1030         /*
1031          * We distinguish between 16550A and U6 16550A by counting
1032          * how many bytes are in the FIFO.
1033          */
1034         if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1035                 up->port.type = PORT_U6_16550A;
1036                 up->capabilities |= UART_CAP_AFE;
1037         }
1038 }
1039 
1040 /*
1041  * This routine is called by rs_init() to initialize a specific serial
1042  * port.  It determines what type of UART chip this serial port is
1043  * using: 8250, 16450, 16550, 16550A.  The important question is
1044  * whether or not this UART is a 16550A or not, since this will
1045  * determine whether or not we can use its FIFO features or not.
1046  */
1047 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1048 {
1049         unsigned char status1, scratch, scratch2, scratch3;
1050         unsigned char save_lcr, save_mcr;
1051         struct uart_port *port = &up->port;
1052         unsigned long flags;
1053         unsigned int old_capabilities;
1054 
1055         if (!port->iobase && !port->mapbase && !port->membase)
1056                 return;
1057 
1058         DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1059                        serial_index(port), port->iobase, port->membase);
1060 
1061         /*
1062          * We really do need global IRQs disabled here - we're going to
1063          * be frobbing the chips IRQ enable register to see if it exists.
1064          */
1065         spin_lock_irqsave(&port->lock, flags);
1066 
1067         up->capabilities = 0;
1068         up->bugs = 0;
1069 
1070         if (!(port->flags & UPF_BUGGY_UART)) {
1071                 /*
1072                  * Do a simple existence test first; if we fail this,
1073                  * there's no point trying anything else.
1074                  *
1075                  * 0x80 is used as a nonsense port to prevent against
1076                  * false positives due to ISA bus float.  The
1077                  * assumption is that 0x80 is a non-existent port;
1078                  * which should be safe since include/asm/io.h also
1079                  * makes this assumption.
1080                  *
1081                  * Note: this is safe as long as MCR bit 4 is clear
1082                  * and the device is in "PC" mode.
1083                  */
1084                 scratch = serial_in(up, UART_IER);
1085                 serial_out(up, UART_IER, 0);
1086 #ifdef __i386__
1087                 outb(0xff, 0x080);
1088 #endif
1089                 /*
1090                  * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1091                  * 16C754B) allow only to modify them if an EFR bit is set.
1092                  */
1093                 scratch2 = serial_in(up, UART_IER) & 0x0f;
1094                 serial_out(up, UART_IER, 0x0F);
1095 #ifdef __i386__
1096                 outb(0, 0x080);
1097 #endif
1098                 scratch3 = serial_in(up, UART_IER) & 0x0f;
1099                 serial_out(up, UART_IER, scratch);
1100                 if (scratch2 != 0 || scratch3 != 0x0F) {
1101                         /*
1102                          * We failed; there's nothing here
1103                          */
1104                         spin_unlock_irqrestore(&port->lock, flags);
1105                         DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1106                                        scratch2, scratch3);
1107                         goto out;
1108                 }
1109         }
1110 
1111         save_mcr = serial_in(up, UART_MCR);
1112         save_lcr = serial_in(up, UART_LCR);
1113 
1114         /*
1115          * Check to see if a UART is really there.  Certain broken
1116          * internal modems based on the Rockwell chipset fail this
1117          * test, because they apparently don't implement the loopback
1118          * test mode.  So this test is skipped on the COM 1 through
1119          * COM 4 ports.  This *should* be safe, since no board
1120          * manufacturer would be stupid enough to design a board
1121          * that conflicts with COM 1-4 --- we hope!
1122          */
1123         if (!(port->flags & UPF_SKIP_TEST)) {
1124                 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1125                 status1 = serial_in(up, UART_MSR) & 0xF0;
1126                 serial_out(up, UART_MCR, save_mcr);
1127                 if (status1 != 0x90) {
1128                         spin_unlock_irqrestore(&port->lock, flags);
1129                         DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1130                                        status1);
1131                         goto out;
1132                 }
1133         }
1134 
1135         /*
1136          * We're pretty sure there's a port here.  Lets find out what
1137          * type of port it is.  The IIR top two bits allows us to find
1138          * out if it's 8250 or 16450, 16550, 16550A or later.  This
1139          * determines what we test for next.
1140          *
1141          * We also initialise the EFR (if any) to zero for later.  The
1142          * EFR occupies the same register location as the FCR and IIR.
1143          */
1144         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1145         serial_out(up, UART_EFR, 0);
1146         serial_out(up, UART_LCR, 0);
1147 
1148         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1149         scratch = serial_in(up, UART_IIR) >> 6;
1150 
1151         switch (scratch) {
1152         case 0:
1153                 autoconfig_8250(up);
1154                 break;
1155         case 1:
1156                 port->type = PORT_UNKNOWN;
1157                 break;
1158         case 2:
1159                 port->type = PORT_16550;
1160                 break;
1161         case 3:
1162                 autoconfig_16550a(up);
1163                 break;
1164         }
1165 
1166 #ifdef CONFIG_SERIAL_8250_RSA
1167         /*
1168          * Only probe for RSA ports if we got the region.
1169          */
1170         if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1171                 int i;
1172 
1173                 for (i = 0 ; i < probe_rsa_count; ++i) {
1174                         if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1175                                 port->type = PORT_RSA;
1176                                 break;
1177                         }
1178                 }
1179         }
1180 #endif
1181 
1182         serial_out(up, UART_LCR, save_lcr);
1183 
1184         port->fifosize = uart_config[up->port.type].fifo_size;
1185         old_capabilities = up->capabilities; 
1186         up->capabilities = uart_config[port->type].flags;
1187         up->tx_loadsz = uart_config[port->type].tx_loadsz;
1188 
1189         if (port->type == PORT_UNKNOWN)
1190                 goto out_lock;
1191 
1192         /*
1193          * Reset the UART.
1194          */
1195 #ifdef CONFIG_SERIAL_8250_RSA
1196         if (port->type == PORT_RSA)
1197                 serial_out(up, UART_RSA_FRR, 0);
1198 #endif
1199         serial_out(up, UART_MCR, save_mcr);
1200         serial8250_clear_fifos(up);
1201         serial_in(up, UART_RX);
1202         if (up->capabilities & UART_CAP_UUE)
1203                 serial_out(up, UART_IER, UART_IER_UUE);
1204         else
1205                 serial_out(up, UART_IER, 0);
1206 
1207 out_lock:
1208         spin_unlock_irqrestore(&port->lock, flags);
1209         if (up->capabilities != old_capabilities) {
1210                 printk(KERN_WARNING
1211                        "ttyS%d: detected caps %08x should be %08x\n",
1212                        serial_index(port), old_capabilities,
1213                        up->capabilities);
1214         }
1215 out:
1216         DEBUG_AUTOCONF("iir=%d ", scratch);
1217         DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1218 }
1219 
1220 static void autoconfig_irq(struct uart_8250_port *up)
1221 {
1222         struct uart_port *port = &up->port;
1223         unsigned char save_mcr, save_ier;
1224         unsigned char save_ICP = 0;
1225         unsigned int ICP = 0;
1226         unsigned long irqs;
1227         int irq;
1228 
1229         if (port->flags & UPF_FOURPORT) {
1230                 ICP = (port->iobase & 0xfe0) | 0x1f;
1231                 save_ICP = inb_p(ICP);
1232                 outb_p(0x80, ICP);
1233                 inb_p(ICP);
1234         }
1235 
1236         /* forget possible initially masked and pending IRQ */
1237         probe_irq_off(probe_irq_on());
1238         save_mcr = serial_in(up, UART_MCR);
1239         save_ier = serial_in(up, UART_IER);
1240         serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1241 
1242         irqs = probe_irq_on();
1243         serial_out(up, UART_MCR, 0);
1244         udelay(10);
1245         if (port->flags & UPF_FOURPORT) {
1246                 serial_out(up, UART_MCR,
1247                             UART_MCR_DTR | UART_MCR_RTS);
1248         } else {
1249                 serial_out(up, UART_MCR,
1250                             UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1251         }
1252         serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1253         serial_in(up, UART_LSR);
1254         serial_in(up, UART_RX);
1255         serial_in(up, UART_IIR);
1256         serial_in(up, UART_MSR);
1257         serial_out(up, UART_TX, 0xFF);
1258         udelay(20);
1259         irq = probe_irq_off(irqs);
1260 
1261         serial_out(up, UART_MCR, save_mcr);
1262         serial_out(up, UART_IER, save_ier);
1263 
1264         if (port->flags & UPF_FOURPORT)
1265                 outb_p(save_ICP, ICP);
1266 
1267         port->irq = (irq > 0) ? irq : 0;
1268 }
1269 
1270 static inline void __stop_tx(struct uart_8250_port *p)
1271 {
1272         if (p->ier & UART_IER_THRI) {
1273                 p->ier &= ~UART_IER_THRI;
1274                 serial_out(p, UART_IER, p->ier);
1275         }
1276 }
1277 
1278 static void serial8250_stop_tx(struct uart_port *port)
1279 {
1280         struct uart_8250_port *up = up_to_u8250p(port);
1281 
1282         __stop_tx(up);
1283 
1284         /*
1285          * We really want to stop the transmitter from sending.
1286          */
1287         if (port->type == PORT_16C950) {
1288                 up->acr |= UART_ACR_TXDIS;
1289                 serial_icr_write(up, UART_ACR, up->acr);
1290         }
1291 }
1292 
1293 static void serial8250_start_tx(struct uart_port *port)
1294 {
1295         struct uart_8250_port *up = up_to_u8250p(port);
1296 
1297         if (up->dma && !serial8250_tx_dma(up)) {
1298                 return;
1299         } else if (!(up->ier & UART_IER_THRI)) {
1300                 up->ier |= UART_IER_THRI;
1301                 serial_port_out(port, UART_IER, up->ier);
1302 
1303                 if (up->bugs & UART_BUG_TXEN) {
1304                         unsigned char lsr;
1305                         lsr = serial_in(up, UART_LSR);
1306                         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1307                         if (lsr & UART_LSR_TEMT)
1308                                 serial8250_tx_chars(up);
1309                 }
1310         }
1311 
1312         /*
1313          * Re-enable the transmitter if we disabled it.
1314          */
1315         if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1316                 up->acr &= ~UART_ACR_TXDIS;
1317                 serial_icr_write(up, UART_ACR, up->acr);
1318         }
1319 }
1320 
1321 static void serial8250_stop_rx(struct uart_port *port)
1322 {
1323         struct uart_8250_port *up = up_to_u8250p(port);
1324 
1325         up->ier &= ~UART_IER_RLSI;
1326         up->port.read_status_mask &= ~UART_LSR_DR;
1327         serial_port_out(port, UART_IER, up->ier);
1328 }
1329 
1330 static void serial8250_enable_ms(struct uart_port *port)
1331 {
1332         struct uart_8250_port *up = up_to_u8250p(port);
1333 
1334         /* no MSR capabilities */
1335         if (up->bugs & UART_BUG_NOMSR)
1336                 return;
1337 
1338         up->ier |= UART_IER_MSI;
1339         serial_port_out(port, UART_IER, up->ier);
1340 }
1341 
1342 /*
1343  * serial8250_rx_chars: processes according to the passed in LSR
1344  * value, and returns the remaining LSR bits not handled
1345  * by this Rx routine.
1346  */
1347 unsigned char
1348 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1349 {
1350         struct uart_port *port = &up->port;
1351         unsigned char ch;
1352         int max_count = 256;
1353         char flag;
1354 
1355         do {
1356                 if (likely(lsr & UART_LSR_DR))
1357                         ch = serial_in(up, UART_RX);
1358                 else
1359                         /*
1360                          * Intel 82571 has a Serial Over Lan device that will
1361                          * set UART_LSR_BI without setting UART_LSR_DR when
1362                          * it receives a break. To avoid reading from the
1363                          * receive buffer without UART_LSR_DR bit set, we
1364                          * just force the read character to be 0
1365                          */
1366                         ch = 0;
1367 
1368                 flag = TTY_NORMAL;
1369                 port->icount.rx++;
1370 
1371                 lsr |= up->lsr_saved_flags;
1372                 up->lsr_saved_flags = 0;
1373 
1374                 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1375                         if (lsr & UART_LSR_BI) {
1376                                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1377                                 port->icount.brk++;
1378                                 /*
1379                                  * We do the SysRQ and SAK checking
1380                                  * here because otherwise the break
1381                                  * may get masked by ignore_status_mask
1382                                  * or read_status_mask.
1383                                  */
1384                                 if (uart_handle_break(port))
1385                                         goto ignore_char;
1386                         } else if (lsr & UART_LSR_PE)
1387                                 port->icount.parity++;
1388                         else if (lsr & UART_LSR_FE)
1389                                 port->icount.frame++;
1390                         if (lsr & UART_LSR_OE)
1391                                 port->icount.overrun++;
1392 
1393                         /*
1394                          * Mask off conditions which should be ignored.
1395                          */
1396                         lsr &= port->read_status_mask;
1397 
1398                         if (lsr & UART_LSR_BI) {
1399                                 DEBUG_INTR("handling break....");
1400                                 flag = TTY_BREAK;
1401                         } else if (lsr & UART_LSR_PE)
1402                                 flag = TTY_PARITY;
1403                         else if (lsr & UART_LSR_FE)
1404                                 flag = TTY_FRAME;
1405                 }
1406                 if (uart_handle_sysrq_char(port, ch))
1407                         goto ignore_char;
1408 
1409                 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1410 
1411 ignore_char:
1412                 lsr = serial_in(up, UART_LSR);
1413         } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1414         spin_unlock(&port->lock);
1415         tty_flip_buffer_push(&port->state->port);
1416         spin_lock(&port->lock);
1417         return lsr;
1418 }
1419 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1420 
1421 void serial8250_tx_chars(struct uart_8250_port *up)
1422 {
1423         struct uart_port *port = &up->port;
1424         struct circ_buf *xmit = &port->state->xmit;
1425         int count;
1426 
1427         if (port->x_char) {
1428                 serial_out(up, UART_TX, port->x_char);
1429                 port->icount.tx++;
1430                 port->x_char = 0;
1431                 return;
1432         }
1433         if (uart_tx_stopped(port)) {
1434                 serial8250_stop_tx(port);
1435                 return;
1436         }
1437         if (uart_circ_empty(xmit)) {
1438                 __stop_tx(up);
1439                 return;
1440         }
1441 
1442         count = up->tx_loadsz;
1443         do {
1444                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1445                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1446                 port->icount.tx++;
1447                 if (uart_circ_empty(xmit))
1448                         break;
1449                 if (up->capabilities & UART_CAP_HFIFO) {
1450                         if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1451                             BOTH_EMPTY)
1452                                 break;
1453                 }
1454         } while (--count > 0);
1455 
1456         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1457                 uart_write_wakeup(port);
1458 
1459         DEBUG_INTR("THRE...");
1460 
1461         if (uart_circ_empty(xmit))
1462                 __stop_tx(up);
1463 }
1464 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1465 
1466 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1467 {
1468         struct uart_port *port = &up->port;
1469         unsigned int status = serial_in(up, UART_MSR);
1470 
1471         status |= up->msr_saved_flags;
1472         up->msr_saved_flags = 0;
1473         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1474             port->state != NULL) {
1475                 if (status & UART_MSR_TERI)
1476                         port->icount.rng++;
1477                 if (status & UART_MSR_DDSR)
1478                         port->icount.dsr++;
1479                 if (status & UART_MSR_DDCD)
1480                         uart_handle_dcd_change(port, status & UART_MSR_DCD);
1481                 if (status & UART_MSR_DCTS)
1482                         uart_handle_cts_change(port, status & UART_MSR_CTS);
1483 
1484                 wake_up_interruptible(&port->state->port.delta_msr_wait);
1485         }
1486 
1487         return status;
1488 }
1489 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1490 
1491 /*
1492  * This handles the interrupt from one port.
1493  */
1494 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1495 {
1496         unsigned char status;
1497         unsigned long flags;
1498         struct uart_8250_port *up = up_to_u8250p(port);
1499         int dma_err = 0;
1500 
1501         if (iir & UART_IIR_NO_INT)
1502                 return 0;
1503 
1504         spin_lock_irqsave(&port->lock, flags);
1505 
1506         status = serial_port_in(port, UART_LSR);
1507 
1508         DEBUG_INTR("status = %x...", status);
1509 
1510         if (status & (UART_LSR_DR | UART_LSR_BI)) {
1511                 if (up->dma)
1512                         dma_err = serial8250_rx_dma(up, iir);
1513 
1514                 if (!up->dma || dma_err)
1515                         status = serial8250_rx_chars(up, status);
1516         }
1517         serial8250_modem_status(up);
1518         if (!up->dma && (status & UART_LSR_THRE))
1519                 serial8250_tx_chars(up);
1520 
1521         spin_unlock_irqrestore(&port->lock, flags);
1522         return 1;
1523 }
1524 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1525 
1526 static int serial8250_default_handle_irq(struct uart_port *port)
1527 {
1528         unsigned int iir = serial_port_in(port, UART_IIR);
1529 
1530         return serial8250_handle_irq(port, iir);
1531 }
1532 
1533 /*
1534  * These Exar UARTs have an extra interrupt indicator that could
1535  * fire for a few unimplemented interrupts.  One of which is a
1536  * wakeup event when coming out of sleep.  Put this here just
1537  * to be on the safe side that these interrupts don't go unhandled.
1538  */
1539 static int exar_handle_irq(struct uart_port *port)
1540 {
1541         unsigned char int0, int1, int2, int3;
1542         unsigned int iir = serial_port_in(port, UART_IIR);
1543         int ret;
1544 
1545         ret = serial8250_handle_irq(port, iir);
1546 
1547         if ((port->type == PORT_XR17V35X) ||
1548            (port->type == PORT_XR17D15X)) {
1549                 int0 = serial_port_in(port, 0x80);
1550                 int1 = serial_port_in(port, 0x81);
1551                 int2 = serial_port_in(port, 0x82);
1552                 int3 = serial_port_in(port, 0x83);
1553         }
1554 
1555         return ret;
1556 }
1557 
1558 /*
1559  * This is the serial driver's interrupt routine.
1560  *
1561  * Arjan thinks the old way was overly complex, so it got simplified.
1562  * Alan disagrees, saying that need the complexity to handle the weird
1563  * nature of ISA shared interrupts.  (This is a special exception.)
1564  *
1565  * In order to handle ISA shared interrupts properly, we need to check
1566  * that all ports have been serviced, and therefore the ISA interrupt
1567  * line has been de-asserted.
1568  *
1569  * This means we need to loop through all ports. checking that they
1570  * don't have an interrupt pending.
1571  */
1572 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1573 {
1574         struct irq_info *i = dev_id;
1575         struct list_head *l, *end = NULL;
1576         int pass_counter = 0, handled = 0;
1577 
1578         DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1579 
1580         spin_lock(&i->lock);
1581 
1582         l = i->head;
1583         do {
1584                 struct uart_8250_port *up;
1585                 struct uart_port *port;
1586 
1587                 up = list_entry(l, struct uart_8250_port, list);
1588                 port = &up->port;
1589 
1590                 if (port->handle_irq(port)) {
1591                         handled = 1;
1592                         end = NULL;
1593                 } else if (end == NULL)
1594                         end = l;
1595 
1596                 l = l->next;
1597 
1598                 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1599                         /* If we hit this, we're dead. */
1600                         printk_ratelimited(KERN_ERR
1601                                 "serial8250: too much work for irq%d\n", irq);
1602                         break;
1603                 }
1604         } while (l != end);
1605 
1606         spin_unlock(&i->lock);
1607 
1608         DEBUG_INTR("end.\n");
1609 
1610         return IRQ_RETVAL(handled);
1611 }
1612 
1613 /*
1614  * To support ISA shared interrupts, we need to have one interrupt
1615  * handler that ensures that the IRQ line has been deasserted
1616  * before returning.  Failing to do this will result in the IRQ
1617  * line being stuck active, and, since ISA irqs are edge triggered,
1618  * no more IRQs will be seen.
1619  */
1620 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1621 {
1622         spin_lock_irq(&i->lock);
1623 
1624         if (!list_empty(i->head)) {
1625                 if (i->head == &up->list)
1626                         i->head = i->head->next;
1627                 list_del(&up->list);
1628         } else {
1629                 BUG_ON(i->head != &up->list);
1630                 i->head = NULL;
1631         }
1632         spin_unlock_irq(&i->lock);
1633         /* List empty so throw away the hash node */
1634         if (i->head == NULL) {
1635                 hlist_del(&i->node);
1636                 kfree(i);
1637         }
1638 }
1639 
1640 static int serial_link_irq_chain(struct uart_8250_port *up)
1641 {
1642         struct hlist_head *h;
1643         struct hlist_node *n;
1644         struct irq_info *i;
1645         int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1646 
1647         mutex_lock(&hash_mutex);
1648 
1649         h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1650 
1651         hlist_for_each(n, h) {
1652                 i = hlist_entry(n, struct irq_info, node);
1653                 if (i->irq == up->port.irq)
1654                         break;
1655         }
1656 
1657         if (n == NULL) {
1658                 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1659                 if (i == NULL) {
1660                         mutex_unlock(&hash_mutex);
1661                         return -ENOMEM;
1662                 }
1663                 spin_lock_init(&i->lock);
1664                 i->irq = up->port.irq;
1665                 hlist_add_head(&i->node, h);
1666         }
1667         mutex_unlock(&hash_mutex);
1668 
1669         spin_lock_irq(&i->lock);
1670 
1671         if (i->head) {
1672                 list_add(&up->list, i->head);
1673                 spin_unlock_irq(&i->lock);
1674 
1675                 ret = 0;
1676         } else {
1677                 INIT_LIST_HEAD(&up->list);
1678                 i->head = &up->list;
1679                 spin_unlock_irq(&i->lock);
1680                 irq_flags |= up->port.irqflags;
1681                 ret = request_irq(up->port.irq, serial8250_interrupt,
1682                                   irq_flags, "serial", i);
1683                 if (ret < 0)
1684                         serial_do_unlink(i, up);
1685         }
1686 
1687         return ret;
1688 }
1689 
1690 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1691 {
1692         /*
1693          * yes, some broken gcc emit "warning: 'i' may be used uninitialized"
1694          * but no, we are not going to take a patch that assigns NULL below.
1695          */
1696         struct irq_info *i;
1697         struct hlist_node *n;
1698         struct hlist_head *h;
1699 
1700         mutex_lock(&hash_mutex);
1701 
1702         h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1703 
1704         hlist_for_each(n, h) {
1705                 i = hlist_entry(n, struct irq_info, node);
1706                 if (i->irq == up->port.irq)
1707                         break;
1708         }
1709 
1710         BUG_ON(n == NULL);
1711         BUG_ON(i->head == NULL);
1712 
1713         if (list_empty(i->head))
1714                 free_irq(up->port.irq, i);
1715 
1716         serial_do_unlink(i, up);
1717         mutex_unlock(&hash_mutex);
1718 }
1719 
1720 /*
1721  * This function is used to handle ports that do not have an
1722  * interrupt.  This doesn't work very well for 16450's, but gives
1723  * barely passable results for a 16550A.  (Although at the expense
1724  * of much CPU overhead).
1725  */
1726 static void serial8250_timeout(unsigned long data)
1727 {
1728         struct uart_8250_port *up = (struct uart_8250_port *)data;
1729 
1730         up->port.handle_irq(&up->port);
1731         mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1732 }
1733 
1734 static void serial8250_backup_timeout(unsigned long data)
1735 {
1736         struct uart_8250_port *up = (struct uart_8250_port *)data;
1737         unsigned int iir, ier = 0, lsr;
1738         unsigned long flags;
1739 
1740         spin_lock_irqsave(&up->port.lock, flags);
1741 
1742         /*
1743          * Must disable interrupts or else we risk racing with the interrupt
1744          * based handler.
1745          */
1746         if (up->port.irq) {
1747                 ier = serial_in(up, UART_IER);
1748                 serial_out(up, UART_IER, 0);
1749         }
1750 
1751         iir = serial_in(up, UART_IIR);
1752 
1753         /*
1754          * This should be a safe test for anyone who doesn't trust the
1755          * IIR bits on their UART, but it's specifically designed for
1756          * the "Diva" UART used on the management processor on many HP
1757          * ia64 and parisc boxes.
1758          */
1759         lsr = serial_in(up, UART_LSR);
1760         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1761         if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1762             (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1763             (lsr & UART_LSR_THRE)) {
1764                 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1765                 iir |= UART_IIR_THRI;
1766         }
1767 
1768         if (!(iir & UART_IIR_NO_INT))
1769                 serial8250_tx_chars(up);
1770 
1771         if (up->port.irq)
1772                 serial_out(up, UART_IER, ier);
1773 
1774         spin_unlock_irqrestore(&up->port.lock, flags);
1775 
1776         /* Standard timer interval plus 0.2s to keep the port running */
1777         mod_timer(&up->timer,
1778                 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1779 }
1780 
1781 static unsigned int serial8250_tx_empty(struct uart_port *port)
1782 {
1783         struct uart_8250_port *up = up_to_u8250p(port);
1784         unsigned long flags;
1785         unsigned int lsr;
1786 
1787         spin_lock_irqsave(&port->lock, flags);
1788         lsr = serial_port_in(port, UART_LSR);
1789         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1790         spin_unlock_irqrestore(&port->lock, flags);
1791 
1792         return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1793 }
1794 
1795 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1796 {
1797         struct uart_8250_port *up = up_to_u8250p(port);
1798         unsigned int status;
1799         unsigned int ret;
1800 
1801         status = serial8250_modem_status(up);
1802 
1803         ret = 0;
1804         if (status & UART_MSR_DCD)
1805                 ret |= TIOCM_CAR;
1806         if (status & UART_MSR_RI)
1807                 ret |= TIOCM_RNG;
1808         if (status & UART_MSR_DSR)
1809                 ret |= TIOCM_DSR;
1810         if (status & UART_MSR_CTS)
1811                 ret |= TIOCM_CTS;
1812         return ret;
1813 }
1814 
1815 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1816 {
1817         struct uart_8250_port *up = up_to_u8250p(port);
1818         unsigned char mcr = 0;
1819 
1820         if (mctrl & TIOCM_RTS)
1821                 mcr |= UART_MCR_RTS;
1822         if (mctrl & TIOCM_DTR)
1823                 mcr |= UART_MCR_DTR;
1824         if (mctrl & TIOCM_OUT1)
1825                 mcr |= UART_MCR_OUT1;
1826         if (mctrl & TIOCM_OUT2)
1827                 mcr |= UART_MCR_OUT2;
1828         if (mctrl & TIOCM_LOOP)
1829                 mcr |= UART_MCR_LOOP;
1830 
1831         mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1832 
1833         serial_port_out(port, UART_MCR, mcr);
1834 }
1835 
1836 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1837 {
1838         struct uart_8250_port *up = up_to_u8250p(port);
1839         unsigned long flags;
1840 
1841         spin_lock_irqsave(&port->lock, flags);
1842         if (break_state == -1)
1843                 up->lcr |= UART_LCR_SBC;
1844         else
1845                 up->lcr &= ~UART_LCR_SBC;
1846         serial_port_out(port, UART_LCR, up->lcr);
1847         spin_unlock_irqrestore(&port->lock, flags);
1848 }
1849 
1850 /*
1851  *      Wait for transmitter & holding register to empty
1852  */
1853 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1854 {
1855         unsigned int status, tmout = 10000;
1856 
1857         /* Wait up to 10ms for the character(s) to be sent. */
1858         for (;;) {
1859                 status = serial_in(up, UART_LSR);
1860 
1861                 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1862 
1863                 if ((status & bits) == bits)
1864                         break;
1865                 if (--tmout == 0)
1866                         break;
1867                 udelay(1);
1868         }
1869 
1870         /* Wait up to 1s for flow control if necessary */
1871         if (up->port.flags & UPF_CONS_FLOW) {
1872                 unsigned int tmout;
1873                 for (tmout = 1000000; tmout; tmout--) {
1874                         unsigned int msr = serial_in(up, UART_MSR);
1875                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1876                         if (msr & UART_MSR_CTS)
1877                                 break;
1878                         udelay(1);
1879                         touch_nmi_watchdog();
1880                 }
1881         }
1882 }
1883 
1884 #ifdef CONFIG_CONSOLE_POLL
1885 /*
1886  * Console polling routines for writing and reading from the uart while
1887  * in an interrupt or debug context.
1888  */
1889 
1890 static int serial8250_get_poll_char(struct uart_port *port)
1891 {
1892         unsigned char lsr = serial_port_in(port, UART_LSR);
1893 
1894         if (!(lsr & UART_LSR_DR))
1895                 return NO_POLL_CHAR;
1896 
1897         return serial_port_in(port, UART_RX);
1898 }
1899 
1900 
1901 static void serial8250_put_poll_char(struct uart_port *port,
1902                          unsigned char c)
1903 {
1904         unsigned int ier;
1905         struct uart_8250_port *up = up_to_u8250p(port);
1906 
1907         /*
1908          *      First save the IER then disable the interrupts
1909          */
1910         ier = serial_port_in(port, UART_IER);
1911         if (up->capabilities & UART_CAP_UUE)
1912                 serial_port_out(port, UART_IER, UART_IER_UUE);
1913         else
1914                 serial_port_out(port, UART_IER, 0);
1915 
1916         wait_for_xmitr(up, BOTH_EMPTY);
1917         /*
1918          *      Send the character out.
1919          */
1920         serial_port_out(port, UART_TX, c);
1921 
1922         /*
1923          *      Finally, wait for transmitter to become empty
1924          *      and restore the IER
1925          */
1926         wait_for_xmitr(up, BOTH_EMPTY);
1927         serial_port_out(port, UART_IER, ier);
1928 }
1929 
1930 #endif /* CONFIG_CONSOLE_POLL */
1931 
1932 static int serial8250_startup(struct uart_port *port)
1933 {
1934         struct uart_8250_port *up = up_to_u8250p(port);
1935         unsigned long flags;
1936         unsigned char lsr, iir;
1937         int retval;
1938 
1939         if (port->type == PORT_8250_CIR)
1940                 return -ENODEV;
1941 
1942         if (!port->fifosize)
1943                 port->fifosize = uart_config[port->type].fifo_size;
1944         if (!up->tx_loadsz)
1945                 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1946         if (!up->capabilities)
1947                 up->capabilities = uart_config[port->type].flags;
1948         up->mcr = 0;
1949 
1950         if (port->iotype != up->cur_iotype)
1951                 set_io_from_upio(port);
1952 
1953         if (port->type == PORT_16C950) {
1954                 /* Wake up and initialize UART */
1955                 up->acr = 0;
1956                 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1957                 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1958                 serial_port_out(port, UART_IER, 0);
1959                 serial_port_out(port, UART_LCR, 0);
1960                 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1961                 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1962                 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1963                 serial_port_out(port, UART_LCR, 0);
1964         }
1965 
1966 #ifdef CONFIG_SERIAL_8250_RSA
1967         /*
1968          * If this is an RSA port, see if we can kick it up to the
1969          * higher speed clock.
1970          */
1971         enable_rsa(up);
1972 #endif
1973 
1974         /*
1975          * Clear the FIFO buffers and disable them.
1976          * (they will be reenabled in set_termios())
1977          */
1978         serial8250_clear_fifos(up);
1979 
1980         /*
1981          * Clear the interrupt registers.
1982          */
1983         serial_port_in(port, UART_LSR);
1984         serial_port_in(port, UART_RX);
1985         serial_port_in(port, UART_IIR);
1986         serial_port_in(port, UART_MSR);
1987 
1988         /*
1989          * At this point, there's no way the LSR could still be 0xff;
1990          * if it is, then bail out, because there's likely no UART
1991          * here.
1992          */
1993         if (!(port->flags & UPF_BUGGY_UART) &&
1994             (serial_port_in(port, UART_LSR) == 0xff)) {
1995                 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1996                                    serial_index(port));
1997                 return -ENODEV;
1998         }
1999 
2000         /*
2001          * For a XR16C850, we need to set the trigger levels
2002          */
2003         if (port->type == PORT_16850) {
2004                 unsigned char fctr;
2005 
2006                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2007 
2008                 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2009                 serial_port_out(port, UART_FCTR,
2010                                 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2011                 serial_port_out(port, UART_TRG, UART_TRG_96);
2012                 serial_port_out(port, UART_FCTR,
2013                                 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2014                 serial_port_out(port, UART_TRG, UART_TRG_96);
2015 
2016                 serial_port_out(port, UART_LCR, 0);
2017         }
2018 
2019         if (port->irq) {
2020                 unsigned char iir1;
2021                 /*
2022                  * Test for UARTs that do not reassert THRE when the
2023                  * transmitter is idle and the interrupt has already
2024                  * been cleared.  Real 16550s should always reassert
2025                  * this interrupt whenever the transmitter is idle and
2026                  * the interrupt is enabled.  Delays are necessary to
2027                  * allow register changes to become visible.
2028                  */
2029                 spin_lock_irqsave(&port->lock, flags);
2030                 if (up->port.irqflags & IRQF_SHARED)
2031                         disable_irq_nosync(port->irq);
2032 
2033                 wait_for_xmitr(up, UART_LSR_THRE);
2034                 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2035                 udelay(1); /* allow THRE to set */
2036                 iir1 = serial_port_in(port, UART_IIR);
2037                 serial_port_out(port, UART_IER, 0);
2038                 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2039                 udelay(1); /* allow a working UART time to re-assert THRE */
2040                 iir = serial_port_in(port, UART_IIR);
2041                 serial_port_out(port, UART_IER, 0);
2042 
2043                 if (port->irqflags & IRQF_SHARED)
2044                         enable_irq(port->irq);
2045                 spin_unlock_irqrestore(&port->lock, flags);
2046 
2047                 /*
2048                  * If the interrupt is not reasserted, or we otherwise
2049                  * don't trust the iir, setup a timer to kick the UART
2050                  * on a regular basis.
2051                  */
2052                 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2053                     up->port.flags & UPF_BUG_THRE) {
2054                         up->bugs |= UART_BUG_THRE;
2055                         pr_debug("ttyS%d - using backup timer\n",
2056                                  serial_index(port));
2057                 }
2058         }
2059 
2060         /*
2061          * The above check will only give an accurate result the first time
2062          * the port is opened so this value needs to be preserved.
2063          */
2064         if (up->bugs & UART_BUG_THRE) {
2065                 up->timer.function = serial8250_backup_timeout;
2066                 up->timer.data = (unsigned long)up;
2067                 mod_timer(&up->timer, jiffies +
2068                         uart_poll_timeout(port) + HZ / 5);
2069         }
2070 
2071         /*
2072          * If the "interrupt" for this port doesn't correspond with any
2073          * hardware interrupt, we use a timer-based system.  The original
2074          * driver used to do this with IRQ0.
2075          */
2076         if (!port->irq) {
2077                 up->timer.data = (unsigned long)up;
2078                 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2079         } else {
2080                 retval = serial_link_irq_chain(up);
2081                 if (retval)
2082                         return retval;
2083         }
2084 
2085         /*
2086          * Now, initialize the UART
2087          */
2088         serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2089 
2090         spin_lock_irqsave(&port->lock, flags);
2091         if (up->port.flags & UPF_FOURPORT) {
2092                 if (!up->port.irq)
2093                         up->port.mctrl |= TIOCM_OUT1;
2094         } else
2095                 /*
2096                  * Most PC uarts need OUT2 raised to enable interrupts.
2097                  */
2098                 if (port->irq)
2099                         up->port.mctrl |= TIOCM_OUT2;
2100 
2101         serial8250_set_mctrl(port, port->mctrl);
2102 
2103         /* Serial over Lan (SoL) hack:
2104            Intel 8257x Gigabit ethernet chips have a
2105            16550 emulation, to be used for Serial Over Lan.
2106            Those chips take a longer time than a normal
2107            serial device to signalize that a transmission
2108            data was queued. Due to that, the above test generally
2109            fails. One solution would be to delay the reading of
2110            iir. However, this is not reliable, since the timeout
2111            is variable. So, let's just don't test if we receive
2112            TX irq. This way, we'll never enable UART_BUG_TXEN.
2113          */
2114         if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2115                 goto dont_test_tx_en;
2116 
2117         /*
2118          * Do a quick test to see if we receive an
2119          * interrupt when we enable the TX irq.
2120          */
2121         serial_port_out(port, UART_IER, UART_IER_THRI);
2122         lsr = serial_port_in(port, UART_LSR);
2123         iir = serial_port_in(port, UART_IIR);
2124         serial_port_out(port, UART_IER, 0);
2125 
2126         if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2127                 if (!(up->bugs & UART_BUG_TXEN)) {
2128                         up->bugs |= UART_BUG_TXEN;
2129                         pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2130                                  serial_index(port));
2131                 }
2132         } else {
2133                 up->bugs &= ~UART_BUG_TXEN;
2134         }
2135 
2136 dont_test_tx_en:
2137         spin_unlock_irqrestore(&port->lock, flags);
2138 
2139         /*
2140          * Clear the interrupt registers again for luck, and clear the
2141          * saved flags to avoid getting false values from polling
2142          * routines or the previous session.
2143          */
2144         serial_port_in(port, UART_LSR);
2145         serial_port_in(port, UART_RX);
2146         serial_port_in(port, UART_IIR);
2147         serial_port_in(port, UART_MSR);
2148         up->lsr_saved_flags = 0;
2149         up->msr_saved_flags = 0;
2150 
2151         /*
2152          * Request DMA channels for both RX and TX.
2153          */
2154         if (up->dma) {
2155                 retval = serial8250_request_dma(up);
2156                 if (retval) {
2157                         pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2158                                             serial_index(port));
2159                         up->dma = NULL;
2160                 }
2161         }
2162 
2163         /*
2164          * Finally, enable interrupts.  Note: Modem status interrupts
2165          * are set via set_termios(), which will be occurring imminently
2166          * anyway, so we don't enable them here.
2167          */
2168         up->ier = UART_IER_RLSI | UART_IER_RDI;
2169         serial_port_out(port, UART_IER, up->ier);
2170 
2171         if (port->flags & UPF_FOURPORT) {
2172                 unsigned int icp;
2173                 /*
2174                  * Enable interrupts on the AST Fourport board
2175                  */
2176                 icp = (port->iobase & 0xfe0) | 0x01f;
2177                 outb_p(0x80, icp);
2178                 inb_p(icp);
2179         }
2180 
2181         return 0;
2182 }
2183 
2184 static void serial8250_shutdown(struct uart_port *port)
2185 {
2186         struct uart_8250_port *up = up_to_u8250p(port);
2187         unsigned long flags;
2188 
2189         /*
2190          * Disable interrupts from this port
2191          */
2192         up->ier = 0;
2193         serial_port_out(port, UART_IER, 0);
2194 
2195         if (up->dma)
2196                 serial8250_release_dma(up);
2197 
2198         spin_lock_irqsave(&port->lock, flags);
2199         if (port->flags & UPF_FOURPORT) {
2200                 /* reset interrupts on the AST Fourport board */
2201                 inb((port->iobase & 0xfe0) | 0x1f);
2202                 port->mctrl |= TIOCM_OUT1;
2203         } else
2204                 port->mctrl &= ~TIOCM_OUT2;
2205 
2206         serial8250_set_mctrl(port, port->mctrl);
2207         spin_unlock_irqrestore(&port->lock, flags);
2208 
2209         /*
2210          * Disable break condition and FIFOs
2211          */
2212         serial_port_out(port, UART_LCR,
2213                         serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2214         serial8250_clear_fifos(up);
2215 
2216 #ifdef CONFIG_SERIAL_8250_RSA
2217         /*
2218          * Reset the RSA board back to 115kbps compat mode.
2219          */
2220         disable_rsa(up);
2221 #endif
2222 
2223         /*
2224          * Read data port to reset things, and then unlink from
2225          * the IRQ chain.
2226          */
2227         serial_port_in(port, UART_RX);
2228 
2229         del_timer_sync(&up->timer);
2230         up->timer.function = serial8250_timeout;
2231         if (port->irq)
2232                 serial_unlink_irq_chain(up);
2233 }
2234 
2235 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2236 {
2237         unsigned int quot;
2238 
2239         /*
2240          * Handle magic divisors for baud rates above baud_base on
2241          * SMSC SuperIO chips.
2242          */
2243         if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2244             baud == (port->uartclk/4))
2245                 quot = 0x8001;
2246         else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2247                  baud == (port->uartclk/8))
2248                 quot = 0x8002;
2249         else
2250                 quot = uart_get_divisor(port, baud);
2251 
2252         return quot;
2253 }
2254 
2255 void
2256 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2257                           struct ktermios *old)
2258 {
2259         struct uart_8250_port *up = up_to_u8250p(port);
2260         unsigned char cval;
2261         unsigned long flags;
2262         unsigned int baud, quot;
2263 
2264         switch (termios->c_cflag & CSIZE) {
2265         case CS5:
2266                 cval = UART_LCR_WLEN5;
2267                 break;
2268         case CS6:
2269                 cval = UART_LCR_WLEN6;
2270                 break;
2271         case CS7:
2272                 cval = UART_LCR_WLEN7;
2273                 break;
2274         default:
2275         case CS8:
2276                 cval = UART_LCR_WLEN8;
2277                 break;
2278         }
2279 
2280         if (termios->c_cflag & CSTOPB)
2281                 cval |= UART_LCR_STOP;
2282         if (termios->c_cflag & PARENB) {
2283                 cval |= UART_LCR_PARITY;
2284                 if (up->bugs & UART_BUG_PARITY)
2285                         up->fifo_bug = true;
2286         }
2287         if (!(termios->c_cflag & PARODD))
2288                 cval |= UART_LCR_EPAR;
2289 #ifdef CMSPAR
2290         if (termios->c_cflag & CMSPAR)
2291                 cval |= UART_LCR_SPAR;
2292 #endif
2293 
2294         /*
2295          * Ask the core to calculate the divisor for us.
2296          */
2297         baud = uart_get_baud_rate(port, termios, old,
2298                                   port->uartclk / 16 / 0xffff,
2299                                   port->uartclk / 16);
2300         quot = serial8250_get_divisor(port, baud);
2301 
2302         /*
2303          * Oxford Semi 952 rev B workaround
2304          */
2305         if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2306                 quot++;
2307 
2308         if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2309                 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2310                 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2311                         up->fcr &= ~UART_FCR_TRIGGER_MASK;
2312                         up->fcr |= UART_FCR_TRIGGER_1;
2313                 }
2314         }
2315 
2316         /*
2317          * MCR-based auto flow control.  When AFE is enabled, RTS will be
2318          * deasserted when the receive FIFO contains more characters than
2319          * the trigger, or the MCR RTS bit is cleared.  In the case where
2320          * the remote UART is not using CTS auto flow control, we must
2321          * have sufficient FIFO entries for the latency of the remote
2322          * UART to respond.  IOW, at least 32 bytes of FIFO. Also enable
2323          * AFE if hw flow control is supported
2324          */
2325         if ((up->capabilities & UART_CAP_AFE && (port->fifosize >= 32)) ||
2326             (port->flags & UPF_HARD_FLOW)) {
2327                 up->mcr &= ~UART_MCR_AFE;
2328                 if (termios->c_cflag & CRTSCTS)
2329                         up->mcr |= UART_MCR_AFE;
2330         }
2331 
2332         /*
2333          * Ok, we're now changing the port state.  Do it with
2334          * interrupts disabled.
2335          */
2336         spin_lock_irqsave(&port->lock, flags);
2337 
2338         /*
2339          * Update the per-port timeout.
2340          */
2341         uart_update_timeout(port, termios->c_cflag, baud);
2342 
2343         port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2344         if (termios->c_iflag & INPCK)
2345                 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2346         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2347                 port->read_status_mask |= UART_LSR_BI;
2348 
2349         /*
2350          * Characteres to ignore
2351          */
2352         port->ignore_status_mask = 0;
2353         if (termios->c_iflag & IGNPAR)
2354                 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2355         if (termios->c_iflag & IGNBRK) {
2356                 port->ignore_status_mask |= UART_LSR_BI;
2357                 /*
2358                  * If we're ignoring parity and break indicators,
2359                  * ignore overruns too (for real raw support).
2360                  */
2361                 if (termios->c_iflag & IGNPAR)
2362                         port->ignore_status_mask |= UART_LSR_OE;
2363         }
2364 
2365         /*
2366          * ignore all characters if CREAD is not set
2367          */
2368         if ((termios->c_cflag & CREAD) == 0)
2369                 port->ignore_status_mask |= UART_LSR_DR;
2370 
2371         /*
2372          * CTS flow control flag and modem status interrupts
2373          */
2374         up->ier &= ~UART_IER_MSI;
2375         if (!(up->bugs & UART_BUG_NOMSR) &&
2376                         UART_ENABLE_MS(&up->port, termios->c_cflag))
2377                 up->ier |= UART_IER_MSI;
2378         if (up->capabilities & UART_CAP_UUE)
2379                 up->ier |= UART_IER_UUE;
2380         if (up->capabilities & UART_CAP_RTOIE)
2381                 up->ier |= UART_IER_RTOIE;
2382 
2383         serial_port_out(port, UART_IER, up->ier);
2384 
2385         if (up->capabilities & UART_CAP_EFR) {
2386                 unsigned char efr = 0;
2387                 /*
2388                  * TI16C752/Startech hardware flow control.  FIXME:
2389                  * - TI16C752 requires control thresholds to be set.
2390                  * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2391                  */
2392                 if (termios->c_cflag & CRTSCTS)
2393                         efr |= UART_EFR_CTS;
2394 
2395                 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2396                 if (port->flags & UPF_EXAR_EFR)
2397                         serial_port_out(port, UART_XR_EFR, efr);
2398                 else
2399                         serial_port_out(port, UART_EFR, efr);
2400         }
2401 
2402         /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2403         if (is_omap1510_8250(up)) {
2404                 if (baud == 115200) {
2405                         quot = 1;
2406                         serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2407                 } else
2408                         serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2409         }
2410 
2411         /*
2412          * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2413          * otherwise just set DLAB
2414          */
2415         if (up->capabilities & UART_NATSEMI)
2416                 serial_port_out(port, UART_LCR, 0xe0);
2417         else
2418                 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
2419 
2420         serial_dl_write(up, quot);
2421 
2422         /*
2423          * XR17V35x UARTs have an extra fractional divisor register (DLD)
2424          *
2425          * We need to recalculate all of the registers, because DLM and DLL
2426          * are already rounded to a whole integer.
2427          *
2428          * When recalculating we use a 32x clock instead of a 16x clock to
2429          * allow 1-bit for rounding in the fractional part.
2430          */
2431         if (up->port.type == PORT_XR17V35X) {
2432                 unsigned int baud_x32 = (port->uartclk * 2) / baud;
2433                 u16 quot = baud_x32 / 32;
2434                 u8 quot_frac = DIV_ROUND_CLOSEST(baud_x32 % 32, 2);
2435 
2436                 serial_dl_write(up, quot);
2437                 serial_port_out(port, 0x2, quot_frac & 0xf);
2438         }
2439 
2440         /*
2441          * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2442          * is written without DLAB set, this mode will be disabled.
2443          */
2444         if (port->type == PORT_16750)
2445                 serial_port_out(port, UART_FCR, up->fcr);
2446 
2447         serial_port_out(port, UART_LCR, cval);          /* reset DLAB */
2448         up->lcr = cval;                                 /* Save LCR */
2449         if (port->type != PORT_16750) {
2450                 /* emulated UARTs (Lucent Venus 167x) need two steps */
2451                 if (up->fcr & UART_FCR_ENABLE_FIFO)
2452                         serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2453                 serial_port_out(port, UART_FCR, up->fcr);       /* set fcr */
2454         }
2455         serial8250_set_mctrl(port, port->mctrl);
2456         spin_unlock_irqrestore(&port->lock, flags);
2457         /* Don't rewrite B0 */
2458         if (tty_termios_baud_rate(termios))
2459                 tty_termios_encode_baud_rate(termios, baud, baud);
2460 }
2461 EXPORT_SYMBOL(serial8250_do_set_termios);
2462 
2463 static void
2464 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2465                        struct ktermios *old)
2466 {
2467         if (port->set_termios)
2468                 port->set_termios(port, termios, old);
2469         else
2470                 serial8250_do_set_termios(port, termios, old);
2471 }
2472 
2473 static void
2474 serial8250_set_ldisc(struct uart_port *port, int new)
2475 {
2476         if (new == N_PPS) {
2477                 port->flags |= UPF_HARDPPS_CD;
2478                 serial8250_enable_ms(port);
2479         } else
2480                 port->flags &= ~UPF_HARDPPS_CD;
2481 }
2482 
2483 
2484 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2485                       unsigned int oldstate)
2486 {
2487         struct uart_8250_port *p = up_to_u8250p(port);
2488 
2489         serial8250_set_sleep(p, state != 0);
2490 }
2491 EXPORT_SYMBOL(serial8250_do_pm);
2492 
2493 static void
2494 serial8250_pm(struct uart_port *port, unsigned int state,
2495               unsigned int oldstate)
2496 {
2497         if (port->pm)
2498                 port->pm(port, state, oldstate);
2499         else
2500                 serial8250_do_pm(port, state, oldstate);
2501 }
2502 
2503 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2504 {
2505         if (pt->port.iotype == UPIO_AU)
2506                 return 0x1000;
2507         if (is_omap1_8250(pt))
2508                 return 0x16 << pt->port.regshift;
2509 
2510         return 8 << pt->port.regshift;
2511 }
2512 
2513 /*
2514  * Resource handling.
2515  */
2516 static int serial8250_request_std_resource(struct uart_8250_port *up)
2517 {
2518         unsigned int size = serial8250_port_size(up);
2519         struct uart_port *port = &up->port;
2520         int ret = 0;
2521 
2522         switch (port->iotype) {
2523         case UPIO_AU:
2524         case UPIO_TSI:
2525         case UPIO_MEM32:
2526         case UPIO_MEM:
2527                 if (!port->mapbase)
2528                         break;
2529 
2530                 if (!request_mem_region(port->mapbase, size, "serial")) {
2531                         ret = -EBUSY;
2532                         break;
2533                 }
2534 
2535                 if (port->flags & UPF_IOREMAP) {
2536                         port->membase = ioremap_nocache(port->mapbase, size);
2537                         if (!port->membase) {
2538                                 release_mem_region(port->mapbase, size);
2539                                 ret = -ENOMEM;
2540                         }
2541                 }
2542                 break;
2543 
2544         case UPIO_HUB6:
2545         case UPIO_PORT:
2546                 if (!request_region(port->iobase, size, "serial"))
2547                         ret = -EBUSY;
2548                 break;
2549         }
2550         return ret;
2551 }
2552 
2553 static void serial8250_release_std_resource(struct uart_8250_port *up)
2554 {
2555         unsigned int size = serial8250_port_size(up);
2556         struct uart_port *port = &up->port;
2557 
2558         switch (port->iotype) {
2559         case UPIO_AU:
2560         case UPIO_TSI:
2561         case UPIO_MEM32:
2562         case UPIO_MEM:
2563                 if (!port->mapbase)
2564                         break;
2565 
2566                 if (port->flags & UPF_IOREMAP) {
2567                         iounmap(port->membase);
2568                         port->membase = NULL;
2569                 }
2570 
2571                 release_mem_region(port->mapbase, size);
2572                 break;
2573 
2574         case UPIO_HUB6:
2575         case UPIO_PORT:
2576                 release_region(port->iobase, size);
2577                 break;
2578         }
2579 }
2580 
2581 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2582 {
2583         unsigned long start = UART_RSA_BASE << up->port.regshift;
2584         unsigned int size = 8 << up->port.regshift;
2585         struct uart_port *port = &up->port;
2586         int ret = -EINVAL;
2587 
2588         switch (port->iotype) {
2589         case UPIO_HUB6:
2590         case UPIO_PORT:
2591                 start += port->iobase;
2592                 if (request_region(start, size, "serial-rsa"))
2593                         ret = 0;
2594                 else
2595                         ret = -EBUSY;
2596                 break;
2597         }
2598 
2599         return ret;
2600 }
2601 
2602 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2603 {
2604         unsigned long offset = UART_RSA_BASE << up->port.regshift;
2605         unsigned int size = 8 << up->port.regshift;
2606         struct uart_port *port = &up->port;
2607 
2608         switch (port->iotype) {
2609         case UPIO_HUB6:
2610         case UPIO_PORT:
2611                 release_region(port->iobase + offset, size);
2612                 break;
2613         }
2614 }
2615 
2616 static void serial8250_release_port(struct uart_port *port)
2617 {
2618         struct uart_8250_port *up = up_to_u8250p(port);
2619 
2620         serial8250_release_std_resource(up);
2621         if (port->type == PORT_RSA)
2622                 serial8250_release_rsa_resource(up);
2623 }
2624 
2625 static int serial8250_request_port(struct uart_port *port)
2626 {
2627         struct uart_8250_port *up = up_to_u8250p(port);
2628         int ret;
2629 
2630         if (port->type == PORT_8250_CIR)
2631                 return -ENODEV;
2632 
2633         ret = serial8250_request_std_resource(up);
2634         if (ret == 0 && port->type == PORT_RSA) {
2635                 ret = serial8250_request_rsa_resource(up);
2636                 if (ret < 0)
2637                         serial8250_release_std_resource(up);
2638         }
2639 
2640         return ret;
2641 }
2642 
2643 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2644 {
2645         const struct serial8250_config *conf_type = &uart_config[up->port.type];
2646         unsigned char bytes;
2647 
2648         bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2649 
2650         return bytes ? bytes : -EOPNOTSUPP;
2651 }
2652 
2653 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2654 {
2655         const struct serial8250_config *conf_type = &uart_config[up->port.type];
2656         int i;
2657 
2658         if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2659                 return -EOPNOTSUPP;
2660 
2661         for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2662                 if (bytes < conf_type->rxtrig_bytes[i])
2663                         /* Use the nearest lower value */
2664                         return (--i) << UART_FCR_R_TRIG_SHIFT;
2665         }
2666 
2667         return UART_FCR_R_TRIG_11;
2668 }
2669 
2670 static int do_get_rxtrig(struct tty_port *port)
2671 {
2672         struct uart_state *state = container_of(port, struct uart_state, port);
2673         struct uart_port *uport = state->uart_port;
2674         struct uart_8250_port *up =
2675                 container_of(uport, struct uart_8250_port, port);
2676 
2677         if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2678                 return -EINVAL;
2679 
2680         return fcr_get_rxtrig_bytes(up);
2681 }
2682 
2683 static int do_serial8250_get_rxtrig(struct tty_port *port)
2684 {
2685         int rxtrig_bytes;
2686 
2687         mutex_lock(&port->mutex);
2688         rxtrig_bytes = do_get_rxtrig(port);
2689         mutex_unlock(&port->mutex);
2690 
2691         return rxtrig_bytes;
2692 }
2693 
2694 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2695         struct device_attribute *attr, char *buf)
2696 {
2697         struct tty_port *port = dev_get_drvdata(dev);
2698         int rxtrig_bytes;
2699 
2700         rxtrig_bytes = do_serial8250_get_rxtrig(port);
2701         if (rxtrig_bytes < 0)
2702                 return rxtrig_bytes;
2703 
2704         return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2705 }
2706 
2707 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2708 {
2709         struct uart_state *state = container_of(port, struct uart_state, port);
2710         struct uart_port *uport = state->uart_port;
2711         struct uart_8250_port *up =
2712                 container_of(uport, struct uart_8250_port, port);
2713         int rxtrig;
2714 
2715         if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2716             up->fifo_bug)
2717                 return -EINVAL;
2718 
2719         rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2720         if (rxtrig < 0)
2721                 return rxtrig;
2722 
2723         serial8250_clear_fifos(up);
2724         up->fcr &= ~UART_FCR_TRIGGER_MASK;
2725         up->fcr |= (unsigned char)rxtrig;
2726         serial_out(up, UART_FCR, up->fcr);
2727         return 0;
2728 }
2729 
2730 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2731 {
2732         int ret;
2733 
2734         mutex_lock(&port->mutex);
2735         ret = do_set_rxtrig(port, bytes);
2736         mutex_unlock(&port->mutex);
2737 
2738         return ret;
2739 }
2740 
2741 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2742         struct device_attribute *attr, const char *buf, size_t count)
2743 {
2744         struct tty_port *port = dev_get_drvdata(dev);
2745         unsigned char bytes;
2746         int ret;
2747 
2748         if (!count)
2749                 return -EINVAL;
2750 
2751         ret = kstrtou8(buf, 10, &bytes);
2752         if (ret < 0)
2753                 return ret;
2754 
2755         ret = do_serial8250_set_rxtrig(port, bytes);
2756         if (ret < 0)
2757                 return ret;
2758 
2759         return count;
2760 }
2761 
2762 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2763                    serial8250_get_attr_rx_trig_bytes,
2764                    serial8250_set_attr_rx_trig_bytes);
2765 
2766 static struct attribute *serial8250_dev_attrs[] = {
2767         &dev_attr_rx_trig_bytes.attr,
2768         NULL,
2769         };
2770 
2771 static struct attribute_group serial8250_dev_attr_group = {
2772         .attrs = serial8250_dev_attrs,
2773         };
2774 
2775 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2776 {
2777         const struct serial8250_config *conf_type = &uart_config[up->port.type];
2778 
2779         if (conf_type->rxtrig_bytes[0])
2780                 up->port.attr_group = &serial8250_dev_attr_group;
2781 }
2782 
2783 static void serial8250_config_port(struct uart_port *port, int flags)
2784 {
2785         struct uart_8250_port *up = up_to_u8250p(port);
2786         int probeflags = PROBE_ANY;
2787         int ret;
2788 
2789         if (port->type == PORT_8250_CIR)
2790                 return;
2791 
2792         /*
2793          * Find the region that we can probe for.  This in turn
2794          * tells us whether we can probe for the type of port.
2795          */
2796         ret = serial8250_request_std_resource(up);
2797         if (ret < 0)
2798                 return;
2799 
2800         ret = serial8250_request_rsa_resource(up);
2801         if (ret < 0)
2802                 probeflags &= ~PROBE_RSA;
2803 
2804         if (port->iotype != up->cur_iotype)
2805                 set_io_from_upio(port);
2806 
2807         if (flags & UART_CONFIG_TYPE)
2808                 autoconfig(up, probeflags);
2809 
2810         /* if access method is AU, it is a 16550 with a quirk */
2811         if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2812                 up->bugs |= UART_BUG_NOMSR;
2813 
2814         /* HW bugs may trigger IRQ while IIR == NO_INT */
2815         if (port->type == PORT_TEGRA)
2816                 up->bugs |= UART_BUG_NOMSR;
2817 
2818         if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2819                 autoconfig_irq(up);
2820 
2821         if (port->type != PORT_RSA && probeflags & PROBE_RSA)
2822                 serial8250_release_rsa_resource(up);
2823         if (port->type == PORT_UNKNOWN)
2824                 serial8250_release_std_resource(up);
2825 
2826         /* Fixme: probably not the best place for this */
2827         if ((port->type == PORT_XR17V35X) ||
2828            (port->type == PORT_XR17D15X))
2829                 port->handle_irq = exar_handle_irq;
2830 
2831         register_dev_spec_attr_grp(up);
2832         up->fcr = uart_config[up->port.type].fcr;
2833 }
2834 
2835 static int
2836 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2837 {
2838         if (ser->irq >= nr_irqs || ser->irq < 0 ||
2839             ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2840             ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2841             ser->type == PORT_STARTECH)
2842                 return -EINVAL;
2843         return 0;
2844 }
2845 
2846 static const char *
2847 serial8250_type(struct uart_port *port)
2848 {
2849         int type = port->type;
2850 
2851         if (type >= ARRAY_SIZE(uart_config))
2852                 type = 0;
2853         return uart_config[type].name;
2854 }
2855 
2856 static struct uart_ops serial8250_pops = {
2857         .tx_empty       = serial8250_tx_empty,
2858         .set_mctrl      = serial8250_set_mctrl,
2859         .get_mctrl      = serial8250_get_mctrl,
2860         .stop_tx        = serial8250_stop_tx,
2861         .start_tx       = serial8250_start_tx,
2862         .stop_rx        = serial8250_stop_rx,
2863         .enable_ms      = serial8250_enable_ms,
2864         .break_ctl      = serial8250_break_ctl,
2865         .startup        = serial8250_startup,
2866         .shutdown       = serial8250_shutdown,
2867         .set_termios    = serial8250_set_termios,
2868         .set_ldisc      = serial8250_set_ldisc,
2869         .pm             = serial8250_pm,
2870         .type           = serial8250_type,
2871         .release_port   = serial8250_release_port,
2872         .request_port   = serial8250_request_port,
2873         .config_port    = serial8250_config_port,
2874         .verify_port    = serial8250_verify_port,
2875 #ifdef CONFIG_CONSOLE_POLL
2876         .poll_get_char = serial8250_get_poll_char,
2877         .poll_put_char = serial8250_put_poll_char,
2878 #endif
2879 };
2880 
2881 static struct uart_8250_port serial8250_ports[UART_NR];
2882 
2883 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2884         unsigned short *capabilities);
2885 
2886 void serial8250_set_isa_configurator(
2887         void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2888 {
2889         serial8250_isa_config = v;
2890 }
2891 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2892 
2893 static void __init serial8250_isa_init_ports(void)
2894 {
2895         struct uart_8250_port *up;
2896         static int first = 1;
2897         int i, irqflag = 0;
2898 
2899         if (!first)
2900                 return;
2901         first = 0;
2902 
2903         if (nr_uarts > UART_NR)
2904                 nr_uarts = UART_NR;
2905 
2906         for (i = 0; i < nr_uarts; i++) {
2907                 struct uart_8250_port *up = &serial8250_ports[i];
2908                 struct uart_port *port = &up->port;
2909 
2910                 port->line = i;
2911                 spin_lock_init(&port->lock);
2912 
2913                 init_timer(&up->timer);
2914                 up->timer.function = serial8250_timeout;
2915                 up->cur_iotype = 0xFF;
2916 
2917                 /*
2918                  * ALPHA_KLUDGE_MCR needs to be killed.
2919                  */
2920                 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2921                 up->mcr_force = ALPHA_KLUDGE_MCR;
2922 
2923                 port->ops = &serial8250_pops;
2924         }
2925 
2926         if (share_irqs)
2927                 irqflag = IRQF_SHARED;
2928 
2929         for (i = 0, up = serial8250_ports;
2930              i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2931              i++, up++) {
2932                 struct uart_port *port = &up->port;
2933 
2934                 port->iobase   = old_serial_port[i].port;
2935                 port->irq      = irq_canonicalize(old_serial_port[i].irq);
2936                 port->irqflags = old_serial_port[i].irqflags;
2937                 port->uartclk  = old_serial_port[i].baud_base * 16;
2938                 port->flags    = old_serial_port[i].flags;
2939                 port->hub6     = old_serial_port[i].hub6;
2940                 port->membase  = old_serial_port[i].iomem_base;
2941                 port->iotype   = old_serial_port[i].io_type;
2942                 port->regshift = old_serial_port[i].iomem_reg_shift;
2943                 set_io_from_upio(port);
2944                 port->irqflags |= irqflag;
2945                 if (serial8250_isa_config != NULL)
2946                         serial8250_isa_config(i, &up->port, &up->capabilities);
2947 
2948         }
2949 }
2950 
2951 static void
2952 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2953 {
2954         up->port.type = type;
2955         if (!up->port.fifosize)
2956                 up->port.fifosize = uart_config[type].fifo_size;
2957         if (!up->tx_loadsz)
2958                 up->tx_loadsz = uart_config[type].tx_loadsz;
2959         if (!up->capabilities)
2960                 up->capabilities = uart_config[type].flags;
2961 }
2962 
2963 static void __init
2964 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2965 {
2966         int i;
2967 
2968         for (i = 0; i < nr_uarts; i++) {
2969                 struct uart_8250_port *up = &serial8250_ports[i];
2970 
2971                 if (up->port.dev)
2972                         continue;
2973 
2974                 up->port.dev = dev;
2975 
2976                 if (up->port.flags & UPF_FIXED_TYPE)
2977                         serial8250_init_fixed_type_port(up, up->port.type);
2978 
2979                 uart_add_one_port(drv, &up->port);
2980         }
2981 }
2982 
2983 #ifdef CONFIG_SERIAL_8250_CONSOLE
2984 
2985 static void serial8250_console_putchar(struct uart_port *port, int ch)
2986 {
2987         struct uart_8250_port *up = up_to_u8250p(port);
2988 
2989         wait_for_xmitr(up, UART_LSR_THRE);
2990         serial_port_out(port, UART_TX, ch);
2991 }
2992 
2993 /*
2994  *      Print a string to the serial port trying not to disturb
2995  *      any possible real use of the port...
2996  *
2997  *      The console_lock must be held when we get here.
2998  */
2999 static void
3000 serial8250_console_write(struct console *co, const char *s, unsigned int count)
3001 {
3002         struct uart_8250_port *up = &serial8250_ports[co->index];
3003         struct uart_port *port = &up->port;
3004         unsigned long flags;
3005         unsigned int ier;
3006         int locked = 1;
3007 
3008         touch_nmi_watchdog();
3009 
3010         if (port->sysrq || oops_in_progress)
3011                 locked = spin_trylock_irqsave(&port->lock, flags);
3012         else
3013                 spin_lock_irqsave(&port->lock, flags);
3014 
3015         /*
3016          *      First save the IER then disable the interrupts
3017          */
3018         ier = serial_port_in(port, UART_IER);
3019 
3020         if (up->capabilities & UART_CAP_UUE)
3021                 serial_port_out(port, UART_IER, UART_IER_UUE);
3022         else
3023                 serial_port_out(port, UART_IER, 0);
3024 
3025         uart_console_write(port, s, count, serial8250_console_putchar);
3026 
3027         /*
3028          *      Finally, wait for transmitter to become empty
3029          *      and restore the IER
3030          */
3031         wait_for_xmitr(up, BOTH_EMPTY);
3032         serial_port_out(port, UART_IER, ier);
3033 
3034         /*
3035          *      The receive handling will happen properly because the
3036          *      receive ready bit will still be set; it is not cleared
3037          *      on read.  However, modem control will not, we must
3038          *      call it if we have saved something in the saved flags
3039          *      while processing with interrupts off.
3040          */
3041         if (up->msr_saved_flags)
3042                 serial8250_modem_status(up);
3043 
3044         if (locked)
3045                 spin_unlock_irqrestore(&port->lock, flags);
3046 }
3047 
3048 static int __init serial8250_console_setup(struct console *co, char *options)
3049 {
3050         struct uart_port *port;
3051         int baud = 9600;
3052         int bits = 8;
3053         int parity = 'n';
3054         int flow = 'n';
3055 
3056         /*
3057          * Check whether an invalid uart number has been specified, and
3058          * if so, search for the first available port that does have
3059          * console support.
3060          */
3061         if (co->index >= nr_uarts)
3062                 co->index = 0;
3063         port = &serial8250_ports[co->index].port;
3064         if (!port->iobase && !port->membase)
3065                 return -ENODEV;
3066 
3067         if (options)
3068                 uart_parse_options(options, &baud, &parity, &bits, &flow);
3069 
3070         return uart_set_options(port, co, baud, parity, bits, flow);
3071 }
3072 
3073 static int serial8250_console_early_setup(void)
3074 {
3075         return serial8250_find_port_for_earlycon();
3076 }
3077 
3078 static struct console serial8250_console = {
3079         .name           = "ttyS",
3080         .write          = serial8250_console_write,
3081         .device         = uart_console_device,
3082         .setup          = serial8250_console_setup,
3083         .early_setup    = serial8250_console_early_setup,
3084         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
3085         .index          = -1,
3086         .data           = &serial8250_reg,
3087 };
3088 
3089 static int __init serial8250_console_init(void)
3090 {
3091         serial8250_isa_init_ports();
3092         register_console(&serial8250_console);
3093         return 0;
3094 }
3095 console_initcall(serial8250_console_init);
3096 
3097 int serial8250_find_port(struct uart_port *p)
3098 {
3099         int line;
3100         struct uart_port *port;
3101 
3102         for (line = 0; line < nr_uarts; line++) {
3103                 port = &serial8250_ports[line].port;
3104                 if (uart_match_port(p, port))
3105                         return line;
3106         }
3107         return -ENODEV;
3108 }
3109 
3110 #define SERIAL8250_CONSOLE      &serial8250_console
3111 #else
3112 #define SERIAL8250_CONSOLE      NULL
3113 #endif
3114 
3115 static struct uart_driver serial8250_reg = {
3116         .owner                  = THIS_MODULE,
3117         .driver_name            = "serial",
3118         .dev_name               = "ttyS",
3119         .major                  = TTY_MAJOR,
3120         .minor                  = 64,
3121         .cons                   = SERIAL8250_CONSOLE,
3122 };
3123 
3124 /*
3125  * early_serial_setup - early registration for 8250 ports
3126  *
3127  * Setup an 8250 port structure prior to console initialisation.  Use
3128  * after console initialisation will cause undefined behaviour.
3129  */
3130 int __init early_serial_setup(struct uart_port *port)
3131 {
3132         struct uart_port *p;
3133 
3134         if (port->line >= ARRAY_SIZE(serial8250_ports))
3135                 return -ENODEV;
3136 
3137         serial8250_isa_init_ports();
3138         p = &serial8250_ports[port->line].port;
3139         p->iobase       = port->iobase;
3140         p->membase      = port->membase;
3141         p->irq          = port->irq;
3142         p->irqflags     = port->irqflags;
3143         p->uartclk      = port->uartclk;
3144         p->fifosize     = port->fifosize;
3145         p->regshift     = port->regshift;
3146         p->iotype       = port->iotype;
3147         p->flags        = port->flags;
3148         p->mapbase      = port->mapbase;
3149         p->private_data = port->private_data;
3150         p->type         = port->type;
3151         p->line         = port->line;
3152 
3153         set_io_from_upio(p);
3154         if (port->serial_in)
3155                 p->serial_in = port->serial_in;
3156         if (port->serial_out)
3157                 p->serial_out = port->serial_out;
3158         if (port->handle_irq)
3159                 p->handle_irq = port->handle_irq;
3160         else
3161                 p->handle_irq = serial8250_default_handle_irq;
3162 
3163         return 0;
3164 }
3165 
3166 /**
3167  *      serial8250_suspend_port - suspend one serial port
3168  *      @line:  serial line number
3169  *
3170  *      Suspend one serial port.
3171  */
3172 void serial8250_suspend_port(int line)
3173 {
3174         uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3175 }
3176 
3177 /**
3178  *      serial8250_resume_port - resume one serial port
3179  *      @line:  serial line number
3180  *
3181  *      Resume one serial port.
3182  */
3183 void serial8250_resume_port(int line)
3184 {
3185         struct uart_8250_port *up = &serial8250_ports[line];
3186         struct uart_port *port = &up->port;
3187 
3188         if (up->capabilities & UART_NATSEMI) {
3189                 /* Ensure it's still in high speed mode */
3190                 serial_port_out(port, UART_LCR, 0xE0);
3191 
3192                 ns16550a_goto_highspeed(up);
3193 
3194                 serial_port_out(port, UART_LCR, 0);
3195                 port->uartclk = 921600*16;
3196         }
3197         uart_resume_port(&serial8250_reg, port);
3198 }
3199 
3200 /*
3201  * Register a set of serial devices attached to a platform device.  The
3202  * list is terminated with a zero flags entry, which means we expect
3203  * all entries to have at least UPF_BOOT_AUTOCONF set.
3204  */
3205 static int serial8250_probe(struct platform_device *dev)
3206 {
3207         struct plat_serial8250_port *p = dev_get_platdata(&dev->dev);
3208         struct uart_8250_port uart;
3209         int ret, i, irqflag = 0;
3210 
3211         memset(&uart, 0, sizeof(uart));
3212 
3213         if (share_irqs)
3214                 irqflag = IRQF_SHARED;
3215 
3216         for (i = 0; p && p->flags != 0; p++, i++) {
3217                 uart.port.iobase        = p->iobase;
3218                 uart.port.membase       = p->membase;
3219                 uart.port.irq           = p->irq;
3220                 uart.port.irqflags      = p->irqflags;
3221                 uart.port.uartclk       = p->uartclk;
3222                 uart.port.regshift      = p->regshift;
3223                 uart.port.iotype        = p->iotype;
3224                 uart.port.flags         = p->flags;
3225                 uart.port.mapbase       = p->mapbase;
3226                 uart.port.hub6          = p->hub6;
3227                 uart.port.private_data  = p->private_data;
3228                 uart.port.type          = p->type;
3229                 uart.port.serial_in     = p->serial_in;
3230                 uart.port.serial_out    = p->serial_out;
3231                 uart.port.handle_irq    = p->handle_irq;
3232                 uart.port.handle_break  = p->handle_break;
3233                 uart.port.set_termios   = p->set_termios;
3234                 uart.port.pm            = p->pm;
3235                 uart.port.dev           = &dev->dev;
3236                 uart.port.irqflags      |= irqflag;
3237                 ret = serial8250_register_8250_port(&uart);
3238                 if (ret < 0) {
3239                         dev_err(&dev->dev, "unable to register port at index %d "
3240                                 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3241                                 p->iobase, (unsigned long long)p->mapbase,
3242                                 p->irq, ret);
3243                 }
3244         }
3245         return 0;
3246 }
3247 
3248 /*
3249  * Remove serial ports registered against a platform device.
3250  */
3251 static int serial8250_remove(struct platform_device *dev)
3252 {
3253         int i;
3254 
3255         for (i = 0; i < nr_uarts; i++) {
3256                 struct uart_8250_port *up = &serial8250_ports[i];
3257 
3258                 if (up->port.dev == &dev->dev)
3259                         serial8250_unregister_port(i);
3260         }
3261         return 0;
3262 }
3263 
3264 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3265 {
3266         int i;
3267 
3268         for (i = 0; i < UART_NR; i++) {
3269                 struct uart_8250_port *up = &serial8250_ports[i];
3270 
3271                 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3272                         uart_suspend_port(&serial8250_reg, &up->port);
3273         }
3274 
3275         return 0;
3276 }
3277 
3278 static int serial8250_resume(struct platform_device *dev)
3279 {
3280         int i;
3281 
3282         for (i = 0; i < UART_NR; i++) {
3283                 struct uart_8250_port *up = &serial8250_ports[i];
3284 
3285                 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3286                         serial8250_resume_port(i);
3287         }
3288 
3289         return 0;
3290 }
3291 
3292 static struct platform_driver serial8250_isa_driver = {
3293         .probe          = serial8250_probe,
3294         .remove         = serial8250_remove,
3295         .suspend        = serial8250_suspend,
3296         .resume         = serial8250_resume,
3297         .driver         = {
3298                 .name   = "serial8250",
3299                 .owner  = THIS_MODULE,
3300         },
3301 };
3302 
3303 /*
3304  * This "device" covers _all_ ISA 8250-compatible serial devices listed
3305  * in the table in include/asm/serial.h
3306  */
3307 static struct platform_device *serial8250_isa_devs;
3308 
3309 /*
3310  * serial8250_register_8250_port and serial8250_unregister_port allows for
3311  * 16x50 serial ports to be configured at run-time, to support PCMCIA
3312  * modems and PCI multiport cards.
3313  */
3314 static DEFINE_MUTEX(serial_mutex);
3315 
3316 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3317 {
3318         int i;
3319 
3320         /*
3321          * First, find a port entry which matches.
3322          */
3323         for (i = 0; i < nr_uarts; i++)
3324                 if (uart_match_port(&serial8250_ports[i].port, port))
3325                         return &serial8250_ports[i];
3326 
3327         /*
3328          * We didn't find a matching entry, so look for the first
3329          * free entry.  We look for one which hasn't been previously
3330          * used (indicated by zero iobase).
3331          */
3332         for (i = 0; i < nr_uarts; i++)
3333                 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3334                     serial8250_ports[i].port.iobase == 0)
3335                         return &serial8250_ports[i];
3336 
3337         /*
3338          * That also failed.  Last resort is to find any entry which
3339          * doesn't have a real port associated with it.
3340          */
3341         for (i = 0; i < nr_uarts; i++)
3342                 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3343                         return &serial8250_ports[i];
3344 
3345         return NULL;
3346 }
3347 
3348 /**
3349  *      serial8250_register_8250_port - register a serial port
3350  *      @up: serial port template
3351  *
3352  *      Configure the serial port specified by the request. If the
3353  *      port exists and is in use, it is hung up and unregistered
3354  *      first.
3355  *
3356  *      The port is then probed and if necessary the IRQ is autodetected
3357  *      If this fails an error is returned.
3358  *
3359  *      On success the port is ready to use and the line number is returned.
3360  */
3361 int serial8250_register_8250_port(struct uart_8250_port *up)
3362 {
3363         struct uart_8250_port *uart;
3364         int ret = -ENOSPC;
3365 
3366         if (up->port.uartclk == 0)
3367                 return -EINVAL;
3368 
3369         mutex_lock(&serial_mutex);
3370 
3371         uart = serial8250_find_match_or_unused(&up->port);
3372         if (uart && uart->port.type != PORT_8250_CIR) {
3373                 if (uart->port.dev)
3374                         uart_remove_one_port(&serial8250_reg, &uart->port);
3375 
3376                 uart->port.iobase       = up->port.iobase;
3377                 uart->port.membase      = up->port.membase;
3378                 uart->port.irq          = up->port.irq;
3379                 uart->port.irqflags     = up->port.irqflags;
3380                 uart->port.uartclk      = up->port.uartclk;
3381                 uart->port.fifosize     = up->port.fifosize;
3382                 uart->port.regshift     = up->port.regshift;
3383                 uart->port.iotype       = up->port.iotype;
3384                 uart->port.flags        = up->port.flags | UPF_BOOT_AUTOCONF;
3385                 uart->bugs              = up->bugs;
3386                 uart->port.mapbase      = up->port.mapbase;
3387                 uart->port.private_data = up->port.private_data;
3388                 uart->port.fifosize     = up->port.fifosize;
3389                 uart->tx_loadsz         = up->tx_loadsz;
3390                 uart->capabilities      = up->capabilities;
3391 
3392                 /* Take tx_loadsz from fifosize if it wasn't set separately */
3393                 if (uart->port.fifosize && !uart->tx_loadsz)
3394                         uart->tx_loadsz = uart->port.fifosize;
3395 
3396                 if (up->port.dev)
3397                         uart->port.dev = up->port.dev;
3398 
3399                 if (up->port.flags & UPF_FIXED_TYPE)
3400                         serial8250_init_fixed_type_port(uart, up->port.type);
3401 
3402                 set_io_from_upio(&uart->port);
3403                 /* Possibly override default I/O functions.  */
3404                 if (up->port.serial_in)
3405                         uart->port.serial_in = up->port.serial_in;
3406                 if (up->port.serial_out)
3407                         uart->port.serial_out = up->port.serial_out;
3408                 if (up->port.handle_irq)
3409                         uart->port.handle_irq = up->port.handle_irq;
3410                 /*  Possibly override set_termios call */
3411                 if (up->port.set_termios)
3412                         uart->port.set_termios = up->port.set_termios;
3413                 if (up->port.pm)
3414                         uart->port.pm = up->port.pm;
3415                 if (up->port.handle_break)
3416                         uart->port.handle_break = up->port.handle_break;
3417                 if (up->dl_read)
3418                         uart->dl_read = up->dl_read;
3419                 if (up->dl_write)
3420                         uart->dl_write = up->dl_write;
3421                 if (up->dma)
3422                         uart->dma = up->dma;
3423 
3424                 if (serial8250_isa_config != NULL)
3425                         serial8250_isa_config(0, &uart->port,
3426                                         &uart->capabilities);
3427 
3428                 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3429                 if (ret == 0)
3430                         ret = uart->port.line;
3431         }
3432         mutex_unlock(&serial_mutex);
3433 
3434         return ret;
3435 }
3436 EXPORT_SYMBOL(serial8250_register_8250_port);
3437 
3438 /**
3439  *      serial8250_unregister_port - remove a 16x50 serial port at runtime
3440  *      @line: serial line number
3441  *
3442  *      Remove one serial port.  This may not be called from interrupt
3443  *      context.  We hand the port back to the our control.
3444  */
3445 void serial8250_unregister_port(int line)
3446 {
3447         struct uart_8250_port *uart = &serial8250_ports[line];
3448 
3449         mutex_lock(&serial_mutex);
3450         uart_remove_one_port(&serial8250_reg, &uart->port);
3451         if (serial8250_isa_devs) {
3452                 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3453                 uart->port.type = PORT_UNKNOWN;
3454                 uart->port.dev = &serial8250_isa_devs->dev;
3455                 uart->capabilities = uart_config[uart->port.type].flags;
3456                 uart_add_one_port(&serial8250_reg, &uart->port);
3457         } else {
3458                 uart->port.dev = NULL;
3459         }
3460         mutex_unlock(&serial_mutex);
3461 }
3462 EXPORT_SYMBOL(serial8250_unregister_port);
3463 
3464 static int __init serial8250_init(void)
3465 {
3466         int ret;
3467 
3468         serial8250_isa_init_ports();
3469 
3470         printk(KERN_INFO "Serial: 8250/16550 driver, "
3471                 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3472                 share_irqs ? "en" : "dis");
3473 
3474 #ifdef CONFIG_SPARC
3475         ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3476 #else
3477         serial8250_reg.nr = UART_NR;
3478         ret = uart_register_driver(&serial8250_reg);
3479 #endif
3480         if (ret)
3481                 goto out;
3482 
3483         ret = serial8250_pnp_init();
3484         if (ret)
3485                 goto unreg_uart_drv;
3486 
3487         serial8250_isa_devs = platform_device_alloc("serial8250",
3488                                                     PLAT8250_DEV_LEGACY);
3489         if (!serial8250_isa_devs) {
3490                 ret = -ENOMEM;
3491                 goto unreg_pnp;
3492         }
3493 
3494         ret = platform_device_add(serial8250_isa_devs);
3495         if (ret)
3496                 goto put_dev;
3497 
3498         serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3499 
3500         ret = platform_driver_register(&serial8250_isa_driver);
3501         if (ret == 0)
3502                 goto out;
3503 
3504         platform_device_del(serial8250_isa_devs);
3505 put_dev:
3506         platform_device_put(serial8250_isa_devs);
3507 unreg_pnp:
3508         serial8250_pnp_exit();
3509 unreg_uart_drv:
3510 #ifdef CONFIG_SPARC
3511         sunserial_unregister_minors(&serial8250_reg, UART_NR);
3512 #else
3513         uart_unregister_driver(&serial8250_reg);
3514 #endif
3515 out:
3516         return ret;
3517 }
3518 
3519 static void __exit serial8250_exit(void)
3520 {
3521         struct platform_device *isa_dev = serial8250_isa_devs;
3522 
3523         /*
3524          * This tells serial8250_unregister_port() not to re-register
3525          * the ports (thereby making serial8250_isa_driver permanently
3526          * in use.)
3527          */
3528         serial8250_isa_devs = NULL;
3529 
3530         platform_driver_unregister(&serial8250_isa_driver);
3531         platform_device_unregister(isa_dev);
3532 
3533         serial8250_pnp_exit();
3534 
3535 #ifdef CONFIG_SPARC
3536         sunserial_unregister_minors(&serial8250_reg, UART_NR);
3537 #else
3538         uart_unregister_driver(&serial8250_reg);
3539 #endif
3540 }
3541 
3542 module_init(serial8250_init);
3543 module_exit(serial8250_exit);
3544 
3545 EXPORT_SYMBOL(serial8250_suspend_port);
3546 EXPORT_SYMBOL(serial8250_resume_port);
3547 
3548 MODULE_LICENSE("GPL");
3549 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3550 
3551 module_param(share_irqs, uint, 0644);
3552 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3553         " (unsafe)");
3554 
3555 module_param(nr_uarts, uint, 0644);
3556 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3557 
3558 module_param(skip_txen_test, uint, 0644);
3559 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3560 
3561 #ifdef CONFIG_SERIAL_8250_RSA
3562 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3563 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3564 #endif
3565 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
3566 
3567 #ifdef CONFIG_SERIAL_8250_DEPRECATED_OPTIONS
3568 #ifndef MODULE
3569 /* This module was renamed to 8250_core in 3.7.  Keep the old "8250" name
3570  * working as well for the module options so we don't break people.  We
3571  * need to keep the names identical and the convenient macros will happily
3572  * refuse to let us do that by failing the build with redefinition errors
3573  * of global variables.  So we stick them inside a dummy function to avoid
3574  * those conflicts.  The options still get parsed, and the redefined
3575  * MODULE_PARAM_PREFIX lets us keep the "8250." syntax alive.
3576  *
3577  * This is hacky.  I'm sorry.
3578  */
3579 static void __used s8250_options(void)
3580 {
3581 #undef MODULE_PARAM_PREFIX
3582 #define MODULE_PARAM_PREFIX "8250_core."
3583 
3584         module_param_cb(share_irqs, &param_ops_uint, &share_irqs, 0644);
3585         module_param_cb(nr_uarts, &param_ops_uint, &nr_uarts, 0644);
3586         module_param_cb(skip_txen_test, &param_ops_uint, &skip_txen_test, 0644);
3587 #ifdef CONFIG_SERIAL_8250_RSA
3588         __module_param_call(MODULE_PARAM_PREFIX, probe_rsa,
3589                 &param_array_ops, .arr = &__param_arr_probe_rsa,
3590                 0444, -1);
3591 #endif
3592 }
3593 #else
3594 MODULE_ALIAS("8250_core");
3595 #endif
3596 #endif
3597 

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