Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/tty/serial/8250/8250_core.c

  1 /*
  2  *  Driver for 8250/16550-type serial ports
  3  *
  4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  5  *
  6  *  Copyright (C) 2001 Russell King.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * A note about mapbase / membase
 14  *
 15  *  mapbase is the physical address of the IO port.
 16  *  membase is an 'ioremapped' cookie.
 17  */
 18 
 19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 20 #define SUPPORT_SYSRQ
 21 #endif
 22 
 23 #include <linux/module.h>
 24 #include <linux/moduleparam.h>
 25 #include <linux/ioport.h>
 26 #include <linux/init.h>
 27 #include <linux/console.h>
 28 #include <linux/sysrq.h>
 29 #include <linux/delay.h>
 30 #include <linux/platform_device.h>
 31 #include <linux/tty.h>
 32 #include <linux/ratelimit.h>
 33 #include <linux/tty_flip.h>
 34 #include <linux/serial_reg.h>
 35 #include <linux/serial_core.h>
 36 #include <linux/serial.h>
 37 #include <linux/serial_8250.h>
 38 #include <linux/nmi.h>
 39 #include <linux/mutex.h>
 40 #include <linux/slab.h>
 41 #ifdef CONFIG_SPARC
 42 #include <linux/sunserialcore.h>
 43 #endif
 44 
 45 #include <asm/io.h>
 46 #include <asm/irq.h>
 47 
 48 #include "8250.h"
 49 
 50 /*
 51  * Configuration:
 52  *   share_irqs - whether we pass IRQF_SHARED to request_irq().  This option
 53  *                is unsafe when used on edge-triggered interrupts.
 54  */
 55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
 56 
 57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
 58 
 59 static struct uart_driver serial8250_reg;
 60 
 61 static int serial_index(struct uart_port *port)
 62 {
 63         return (serial8250_reg.minor - 64) + port->line;
 64 }
 65 
 66 static unsigned int skip_txen_test; /* force skip of txen test at init time */
 67 
 68 /*
 69  * Debugging.
 70  */
 71 #if 0
 72 #define DEBUG_AUTOCONF(fmt...)  printk(fmt)
 73 #else
 74 #define DEBUG_AUTOCONF(fmt...)  do { } while (0)
 75 #endif
 76 
 77 #if 0
 78 #define DEBUG_INTR(fmt...)      printk(fmt)
 79 #else
 80 #define DEBUG_INTR(fmt...)      do { } while (0)
 81 #endif
 82 
 83 #define PASS_LIMIT      512
 84 
 85 #define BOTH_EMPTY      (UART_LSR_TEMT | UART_LSR_THRE)
 86 
 87 
 88 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
 89 #define CONFIG_SERIAL_DETECT_IRQ 1
 90 #endif
 91 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
 92 #define CONFIG_SERIAL_MANY_PORTS 1
 93 #endif
 94 
 95 /*
 96  * HUB6 is always on.  This will be removed once the header
 97  * files have been cleaned.
 98  */
 99 #define CONFIG_HUB6 1
100 
101 #include <asm/serial.h>
102 /*
103  * SERIAL_PORT_DFNS tells us about built-in ports that have no
104  * standard enumeration mechanism.   Platforms that can find all
105  * serial ports via mechanisms like ACPI or PCI need not supply it.
106  */
107 #ifndef SERIAL_PORT_DFNS
108 #define SERIAL_PORT_DFNS
109 #endif
110 
111 static const struct old_serial_port old_serial_port[] = {
112         SERIAL_PORT_DFNS /* defined in asm/serial.h */
113 };
114 
115 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
116 
117 #ifdef CONFIG_SERIAL_8250_RSA
118 
119 #define PORT_RSA_MAX 4
120 static unsigned long probe_rsa[PORT_RSA_MAX];
121 static unsigned int probe_rsa_count;
122 #endif /* CONFIG_SERIAL_8250_RSA  */
123 
124 struct irq_info {
125         struct                  hlist_node node;
126         int                     irq;
127         spinlock_t              lock;   /* Protects list not the hash */
128         struct list_head        *head;
129 };
130 
131 #define NR_IRQ_HASH             32      /* Can be adjusted later */
132 static struct hlist_head irq_lists[NR_IRQ_HASH];
133 static DEFINE_MUTEX(hash_mutex);        /* Used to walk the hash */
134 
135 /*
136  * Here we define the default xmit fifo size used for each type of UART.
137  */
138 static const struct serial8250_config uart_config[] = {
139         [PORT_UNKNOWN] = {
140                 .name           = "unknown",
141                 .fifo_size      = 1,
142                 .tx_loadsz      = 1,
143         },
144         [PORT_8250] = {
145                 .name           = "8250",
146                 .fifo_size      = 1,
147                 .tx_loadsz      = 1,
148         },
149         [PORT_16450] = {
150                 .name           = "16450",
151                 .fifo_size      = 1,
152                 .tx_loadsz      = 1,
153         },
154         [PORT_16550] = {
155                 .name           = "16550",
156                 .fifo_size      = 1,
157                 .tx_loadsz      = 1,
158         },
159         [PORT_16550A] = {
160                 .name           = "16550A",
161                 .fifo_size      = 16,
162                 .tx_loadsz      = 16,
163                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164                 .flags          = UART_CAP_FIFO,
165         },
166         [PORT_CIRRUS] = {
167                 .name           = "Cirrus",
168                 .fifo_size      = 1,
169                 .tx_loadsz      = 1,
170         },
171         [PORT_16650] = {
172                 .name           = "ST16650",
173                 .fifo_size      = 1,
174                 .tx_loadsz      = 1,
175                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
176         },
177         [PORT_16650V2] = {
178                 .name           = "ST16650V2",
179                 .fifo_size      = 32,
180                 .tx_loadsz      = 16,
181                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
182                                   UART_FCR_T_TRIG_00,
183                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184         },
185         [PORT_16750] = {
186                 .name           = "TI16750",
187                 .fifo_size      = 64,
188                 .tx_loadsz      = 64,
189                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
190                                   UART_FCR7_64BYTE,
191                 .flags          = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
192         },
193         [PORT_STARTECH] = {
194                 .name           = "Startech",
195                 .fifo_size      = 1,
196                 .tx_loadsz      = 1,
197         },
198         [PORT_16C950] = {
199                 .name           = "16C950/954",
200                 .fifo_size      = 128,
201                 .tx_loadsz      = 128,
202                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203                 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204                 .flags          = UART_CAP_FIFO | UART_CAP_SLEEP,
205         },
206         [PORT_16654] = {
207                 .name           = "ST16654",
208                 .fifo_size      = 64,
209                 .tx_loadsz      = 32,
210                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
211                                   UART_FCR_T_TRIG_10,
212                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
213         },
214         [PORT_16850] = {
215                 .name           = "XR16850",
216                 .fifo_size      = 128,
217                 .tx_loadsz      = 128,
218                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220         },
221         [PORT_RSA] = {
222                 .name           = "RSA",
223                 .fifo_size      = 2048,
224                 .tx_loadsz      = 2048,
225                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226                 .flags          = UART_CAP_FIFO,
227         },
228         [PORT_NS16550A] = {
229                 .name           = "NS16550A",
230                 .fifo_size      = 16,
231                 .tx_loadsz      = 16,
232                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233                 .flags          = UART_CAP_FIFO | UART_NATSEMI,
234         },
235         [PORT_XSCALE] = {
236                 .name           = "XScale",
237                 .fifo_size      = 32,
238                 .tx_loadsz      = 32,
239                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240                 .flags          = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
241         },
242         [PORT_OCTEON] = {
243                 .name           = "OCTEON",
244                 .fifo_size      = 64,
245                 .tx_loadsz      = 64,
246                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
247                 .flags          = UART_CAP_FIFO,
248         },
249         [PORT_AR7] = {
250                 .name           = "AR7",
251                 .fifo_size      = 16,
252                 .tx_loadsz      = 16,
253                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
254                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
255         },
256         [PORT_U6_16550A] = {
257                 .name           = "U6_16550A",
258                 .fifo_size      = 64,
259                 .tx_loadsz      = 64,
260                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
261                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
262         },
263         [PORT_TEGRA] = {
264                 .name           = "Tegra",
265                 .fifo_size      = 32,
266                 .tx_loadsz      = 8,
267                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
268                                   UART_FCR_T_TRIG_01,
269                 .flags          = UART_CAP_FIFO | UART_CAP_RTOIE,
270         },
271         [PORT_XR17D15X] = {
272                 .name           = "XR17D15X",
273                 .fifo_size      = 64,
274                 .tx_loadsz      = 64,
275                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
276                 .flags          = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
277                                   UART_CAP_SLEEP,
278         },
279         [PORT_XR17V35X] = {
280                 .name           = "XR17V35X",
281                 .fifo_size      = 256,
282                 .tx_loadsz      = 256,
283                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
284                                   UART_FCR_T_TRIG_11,
285                 .flags          = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
286                                   UART_CAP_SLEEP,
287         },
288         [PORT_LPC3220] = {
289                 .name           = "LPC3220",
290                 .fifo_size      = 64,
291                 .tx_loadsz      = 32,
292                 .fcr            = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
293                                   UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
294                 .flags          = UART_CAP_FIFO,
295         },
296         [PORT_BRCM_TRUMANAGE] = {
297                 .name           = "TruManage",
298                 .fifo_size      = 1,
299                 .tx_loadsz      = 1024,
300                 .flags          = UART_CAP_HFIFO,
301         },
302         [PORT_8250_CIR] = {
303                 .name           = "CIR port"
304         },
305         [PORT_ALTR_16550_F32] = {
306                 .name           = "Altera 16550 FIFO32",
307                 .fifo_size      = 32,
308                 .tx_loadsz      = 32,
309                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
310                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
311         },
312         [PORT_ALTR_16550_F64] = {
313                 .name           = "Altera 16550 FIFO64",
314                 .fifo_size      = 64,
315                 .tx_loadsz      = 64,
316                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
317                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
318         },
319         [PORT_ALTR_16550_F128] = {
320                 .name           = "Altera 16550 FIFO128",
321                 .fifo_size      = 128,
322                 .tx_loadsz      = 128,
323                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
324                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
325         },
326 };
327 
328 /* Uart divisor latch read */
329 static int default_serial_dl_read(struct uart_8250_port *up)
330 {
331         return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
332 }
333 
334 /* Uart divisor latch write */
335 static void default_serial_dl_write(struct uart_8250_port *up, int value)
336 {
337         serial_out(up, UART_DLL, value & 0xff);
338         serial_out(up, UART_DLM, value >> 8 & 0xff);
339 }
340 
341 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
342 
343 /* Au1x00/RT288x UART hardware has a weird register layout */
344 static const u8 au_io_in_map[] = {
345         [UART_RX]  = 0,
346         [UART_IER] = 2,
347         [UART_IIR] = 3,
348         [UART_LCR] = 5,
349         [UART_MCR] = 6,
350         [UART_LSR] = 7,
351         [UART_MSR] = 8,
352 };
353 
354 static const u8 au_io_out_map[] = {
355         [UART_TX]  = 1,
356         [UART_IER] = 2,
357         [UART_FCR] = 4,
358         [UART_LCR] = 5,
359         [UART_MCR] = 6,
360 };
361 
362 static unsigned int au_serial_in(struct uart_port *p, int offset)
363 {
364         offset = au_io_in_map[offset] << p->regshift;
365         return __raw_readl(p->membase + offset);
366 }
367 
368 static void au_serial_out(struct uart_port *p, int offset, int value)
369 {
370         offset = au_io_out_map[offset] << p->regshift;
371         __raw_writel(value, p->membase + offset);
372 }
373 
374 /* Au1x00 haven't got a standard divisor latch */
375 static int au_serial_dl_read(struct uart_8250_port *up)
376 {
377         return __raw_readl(up->port.membase + 0x28);
378 }
379 
380 static void au_serial_dl_write(struct uart_8250_port *up, int value)
381 {
382         __raw_writel(value, up->port.membase + 0x28);
383 }
384 
385 #endif
386 
387 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
388 {
389         offset = offset << p->regshift;
390         outb(p->hub6 - 1 + offset, p->iobase);
391         return inb(p->iobase + 1);
392 }
393 
394 static void hub6_serial_out(struct uart_port *p, int offset, int value)
395 {
396         offset = offset << p->regshift;
397         outb(p->hub6 - 1 + offset, p->iobase);
398         outb(value, p->iobase + 1);
399 }
400 
401 static unsigned int mem_serial_in(struct uart_port *p, int offset)
402 {
403         offset = offset << p->regshift;
404         return readb(p->membase + offset);
405 }
406 
407 static void mem_serial_out(struct uart_port *p, int offset, int value)
408 {
409         offset = offset << p->regshift;
410         writeb(value, p->membase + offset);
411 }
412 
413 static void mem32_serial_out(struct uart_port *p, int offset, int value)
414 {
415         offset = offset << p->regshift;
416         writel(value, p->membase + offset);
417 }
418 
419 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
420 {
421         offset = offset << p->regshift;
422         return readl(p->membase + offset);
423 }
424 
425 static unsigned int io_serial_in(struct uart_port *p, int offset)
426 {
427         offset = offset << p->regshift;
428         return inb(p->iobase + offset);
429 }
430 
431 static void io_serial_out(struct uart_port *p, int offset, int value)
432 {
433         offset = offset << p->regshift;
434         outb(value, p->iobase + offset);
435 }
436 
437 static int serial8250_default_handle_irq(struct uart_port *port);
438 static int exar_handle_irq(struct uart_port *port);
439 
440 static void set_io_from_upio(struct uart_port *p)
441 {
442         struct uart_8250_port *up =
443                 container_of(p, struct uart_8250_port, port);
444 
445         up->dl_read = default_serial_dl_read;
446         up->dl_write = default_serial_dl_write;
447 
448         switch (p->iotype) {
449         case UPIO_HUB6:
450                 p->serial_in = hub6_serial_in;
451                 p->serial_out = hub6_serial_out;
452                 break;
453 
454         case UPIO_MEM:
455                 p->serial_in = mem_serial_in;
456                 p->serial_out = mem_serial_out;
457                 break;
458 
459         case UPIO_MEM32:
460                 p->serial_in = mem32_serial_in;
461                 p->serial_out = mem32_serial_out;
462                 break;
463 
464 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
465         case UPIO_AU:
466                 p->serial_in = au_serial_in;
467                 p->serial_out = au_serial_out;
468                 up->dl_read = au_serial_dl_read;
469                 up->dl_write = au_serial_dl_write;
470                 break;
471 #endif
472 
473         default:
474                 p->serial_in = io_serial_in;
475                 p->serial_out = io_serial_out;
476                 break;
477         }
478         /* Remember loaded iotype */
479         up->cur_iotype = p->iotype;
480         p->handle_irq = serial8250_default_handle_irq;
481 }
482 
483 static void
484 serial_port_out_sync(struct uart_port *p, int offset, int value)
485 {
486         switch (p->iotype) {
487         case UPIO_MEM:
488         case UPIO_MEM32:
489         case UPIO_AU:
490                 p->serial_out(p, offset, value);
491                 p->serial_in(p, UART_LCR);      /* safe, no side-effects */
492                 break;
493         default:
494                 p->serial_out(p, offset, value);
495         }
496 }
497 
498 /*
499  * For the 16C950
500  */
501 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
502 {
503         serial_out(up, UART_SCR, offset);
504         serial_out(up, UART_ICR, value);
505 }
506 
507 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
508 {
509         unsigned int value;
510 
511         serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
512         serial_out(up, UART_SCR, offset);
513         value = serial_in(up, UART_ICR);
514         serial_icr_write(up, UART_ACR, up->acr);
515 
516         return value;
517 }
518 
519 /*
520  * FIFO support.
521  */
522 static void serial8250_clear_fifos(struct uart_8250_port *p)
523 {
524         if (p->capabilities & UART_CAP_FIFO) {
525                 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
526                 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
527                                UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
528                 serial_out(p, UART_FCR, 0);
529         }
530 }
531 
532 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
533 {
534         unsigned char fcr;
535 
536         serial8250_clear_fifos(p);
537         fcr = uart_config[p->port.type].fcr;
538         serial_out(p, UART_FCR, fcr);
539 }
540 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
541 
542 /*
543  * IER sleep support.  UARTs which have EFRs need the "extended
544  * capability" bit enabled.  Note that on XR16C850s, we need to
545  * reset LCR to write to IER.
546  */
547 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
548 {
549         /*
550          * Exar UARTs have a SLEEP register that enables or disables
551          * each UART to enter sleep mode separately.  On the XR17V35x the
552          * register is accessible to each UART at the UART_EXAR_SLEEP
553          * offset but the UART channel may only write to the corresponding
554          * bit.
555          */
556         if ((p->port.type == PORT_XR17V35X) ||
557            (p->port.type == PORT_XR17D15X)) {
558                 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
559                 return;
560         }
561 
562         if (p->capabilities & UART_CAP_SLEEP) {
563                 if (p->capabilities & UART_CAP_EFR) {
564                         serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
565                         serial_out(p, UART_EFR, UART_EFR_ECB);
566                         serial_out(p, UART_LCR, 0);
567                 }
568                 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
569                 if (p->capabilities & UART_CAP_EFR) {
570                         serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
571                         serial_out(p, UART_EFR, 0);
572                         serial_out(p, UART_LCR, 0);
573                 }
574         }
575 }
576 
577 #ifdef CONFIG_SERIAL_8250_RSA
578 /*
579  * Attempts to turn on the RSA FIFO.  Returns zero on failure.
580  * We set the port uart clock rate if we succeed.
581  */
582 static int __enable_rsa(struct uart_8250_port *up)
583 {
584         unsigned char mode;
585         int result;
586 
587         mode = serial_in(up, UART_RSA_MSR);
588         result = mode & UART_RSA_MSR_FIFO;
589 
590         if (!result) {
591                 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
592                 mode = serial_in(up, UART_RSA_MSR);
593                 result = mode & UART_RSA_MSR_FIFO;
594         }
595 
596         if (result)
597                 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
598 
599         return result;
600 }
601 
602 static void enable_rsa(struct uart_8250_port *up)
603 {
604         if (up->port.type == PORT_RSA) {
605                 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
606                         spin_lock_irq(&up->port.lock);
607                         __enable_rsa(up);
608                         spin_unlock_irq(&up->port.lock);
609                 }
610                 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
611                         serial_out(up, UART_RSA_FRR, 0);
612         }
613 }
614 
615 /*
616  * Attempts to turn off the RSA FIFO.  Returns zero on failure.
617  * It is unknown why interrupts were disabled in here.  However,
618  * the caller is expected to preserve this behaviour by grabbing
619  * the spinlock before calling this function.
620  */
621 static void disable_rsa(struct uart_8250_port *up)
622 {
623         unsigned char mode;
624         int result;
625 
626         if (up->port.type == PORT_RSA &&
627             up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
628                 spin_lock_irq(&up->port.lock);
629 
630                 mode = serial_in(up, UART_RSA_MSR);
631                 result = !(mode & UART_RSA_MSR_FIFO);
632 
633                 if (!result) {
634                         serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
635                         mode = serial_in(up, UART_RSA_MSR);
636                         result = !(mode & UART_RSA_MSR_FIFO);
637                 }
638 
639                 if (result)
640                         up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
641                 spin_unlock_irq(&up->port.lock);
642         }
643 }
644 #endif /* CONFIG_SERIAL_8250_RSA */
645 
646 /*
647  * This is a quickie test to see how big the FIFO is.
648  * It doesn't work at all the time, more's the pity.
649  */
650 static int size_fifo(struct uart_8250_port *up)
651 {
652         unsigned char old_fcr, old_mcr, old_lcr;
653         unsigned short old_dl;
654         int count;
655 
656         old_lcr = serial_in(up, UART_LCR);
657         serial_out(up, UART_LCR, 0);
658         old_fcr = serial_in(up, UART_FCR);
659         old_mcr = serial_in(up, UART_MCR);
660         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
661                     UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
662         serial_out(up, UART_MCR, UART_MCR_LOOP);
663         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
664         old_dl = serial_dl_read(up);
665         serial_dl_write(up, 0x0001);
666         serial_out(up, UART_LCR, 0x03);
667         for (count = 0; count < 256; count++)
668                 serial_out(up, UART_TX, count);
669         mdelay(20);/* FIXME - schedule_timeout */
670         for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
671              (count < 256); count++)
672                 serial_in(up, UART_RX);
673         serial_out(up, UART_FCR, old_fcr);
674         serial_out(up, UART_MCR, old_mcr);
675         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
676         serial_dl_write(up, old_dl);
677         serial_out(up, UART_LCR, old_lcr);
678 
679         return count;
680 }
681 
682 /*
683  * Read UART ID using the divisor method - set DLL and DLM to zero
684  * and the revision will be in DLL and device type in DLM.  We
685  * preserve the device state across this.
686  */
687 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
688 {
689         unsigned char old_dll, old_dlm, old_lcr;
690         unsigned int id;
691 
692         old_lcr = serial_in(p, UART_LCR);
693         serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
694 
695         old_dll = serial_in(p, UART_DLL);
696         old_dlm = serial_in(p, UART_DLM);
697 
698         serial_out(p, UART_DLL, 0);
699         serial_out(p, UART_DLM, 0);
700 
701         id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
702 
703         serial_out(p, UART_DLL, old_dll);
704         serial_out(p, UART_DLM, old_dlm);
705         serial_out(p, UART_LCR, old_lcr);
706 
707         return id;
708 }
709 
710 /*
711  * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
712  * When this function is called we know it is at least a StarTech
713  * 16650 V2, but it might be one of several StarTech UARTs, or one of
714  * its clones.  (We treat the broken original StarTech 16650 V1 as a
715  * 16550, and why not?  Startech doesn't seem to even acknowledge its
716  * existence.)
717  *
718  * What evil have men's minds wrought...
719  */
720 static void autoconfig_has_efr(struct uart_8250_port *up)
721 {
722         unsigned int id1, id2, id3, rev;
723 
724         /*
725          * Everything with an EFR has SLEEP
726          */
727         up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
728 
729         /*
730          * First we check to see if it's an Oxford Semiconductor UART.
731          *
732          * If we have to do this here because some non-National
733          * Semiconductor clone chips lock up if you try writing to the
734          * LSR register (which serial_icr_read does)
735          */
736 
737         /*
738          * Check for Oxford Semiconductor 16C950.
739          *
740          * EFR [4] must be set else this test fails.
741          *
742          * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
743          * claims that it's needed for 952 dual UART's (which are not
744          * recommended for new designs).
745          */
746         up->acr = 0;
747         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
748         serial_out(up, UART_EFR, UART_EFR_ECB);
749         serial_out(up, UART_LCR, 0x00);
750         id1 = serial_icr_read(up, UART_ID1);
751         id2 = serial_icr_read(up, UART_ID2);
752         id3 = serial_icr_read(up, UART_ID3);
753         rev = serial_icr_read(up, UART_REV);
754 
755         DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
756 
757         if (id1 == 0x16 && id2 == 0xC9 &&
758             (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
759                 up->port.type = PORT_16C950;
760 
761                 /*
762                  * Enable work around for the Oxford Semiconductor 952 rev B
763                  * chip which causes it to seriously miscalculate baud rates
764                  * when DLL is 0.
765                  */
766                 if (id3 == 0x52 && rev == 0x01)
767                         up->bugs |= UART_BUG_QUOT;
768                 return;
769         }
770 
771         /*
772          * We check for a XR16C850 by setting DLL and DLM to 0, and then
773          * reading back DLL and DLM.  The chip type depends on the DLM
774          * value read back:
775          *  0x10 - XR16C850 and the DLL contains the chip revision.
776          *  0x12 - XR16C2850.
777          *  0x14 - XR16C854.
778          */
779         id1 = autoconfig_read_divisor_id(up);
780         DEBUG_AUTOCONF("850id=%04x ", id1);
781 
782         id2 = id1 >> 8;
783         if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
784                 up->port.type = PORT_16850;
785                 return;
786         }
787 
788         /*
789          * It wasn't an XR16C850.
790          *
791          * We distinguish between the '654 and the '650 by counting
792          * how many bytes are in the FIFO.  I'm using this for now,
793          * since that's the technique that was sent to me in the
794          * serial driver update, but I'm not convinced this works.
795          * I've had problems doing this in the past.  -TYT
796          */
797         if (size_fifo(up) == 64)
798                 up->port.type = PORT_16654;
799         else
800                 up->port.type = PORT_16650V2;
801 }
802 
803 /*
804  * We detected a chip without a FIFO.  Only two fall into
805  * this category - the original 8250 and the 16450.  The
806  * 16450 has a scratch register (accessible with LCR=0)
807  */
808 static void autoconfig_8250(struct uart_8250_port *up)
809 {
810         unsigned char scratch, status1, status2;
811 
812         up->port.type = PORT_8250;
813 
814         scratch = serial_in(up, UART_SCR);
815         serial_out(up, UART_SCR, 0xa5);
816         status1 = serial_in(up, UART_SCR);
817         serial_out(up, UART_SCR, 0x5a);
818         status2 = serial_in(up, UART_SCR);
819         serial_out(up, UART_SCR, scratch);
820 
821         if (status1 == 0xa5 && status2 == 0x5a)
822                 up->port.type = PORT_16450;
823 }
824 
825 static int broken_efr(struct uart_8250_port *up)
826 {
827         /*
828          * Exar ST16C2550 "A2" devices incorrectly detect as
829          * having an EFR, and report an ID of 0x0201.  See
830          * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html 
831          */
832         if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
833                 return 1;
834 
835         return 0;
836 }
837 
838 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
839 {
840         unsigned char status;
841 
842         status = serial_in(up, 0x04); /* EXCR2 */
843 #define PRESL(x) ((x) & 0x30)
844         if (PRESL(status) == 0x10) {
845                 /* already in high speed mode */
846                 return 0;
847         } else {
848                 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
849                 status |= 0x10;  /* 1.625 divisor for baud_base --> 921600 */
850                 serial_out(up, 0x04, status);
851         }
852         return 1;
853 }
854 
855 /*
856  * We know that the chip has FIFOs.  Does it have an EFR?  The
857  * EFR is located in the same register position as the IIR and
858  * we know the top two bits of the IIR are currently set.  The
859  * EFR should contain zero.  Try to read the EFR.
860  */
861 static void autoconfig_16550a(struct uart_8250_port *up)
862 {
863         unsigned char status1, status2;
864         unsigned int iersave;
865 
866         up->port.type = PORT_16550A;
867         up->capabilities |= UART_CAP_FIFO;
868 
869         /*
870          * XR17V35x UARTs have an extra divisor register, DLD
871          * that gets enabled with when DLAB is set which will
872          * cause the device to incorrectly match and assign
873          * port type to PORT_16650.  The EFR for this UART is
874          * found at offset 0x09. Instead check the Deice ID (DVID)
875          * register for a 2, 4 or 8 port UART.
876          */
877         if (up->port.flags & UPF_EXAR_EFR) {
878                 status1 = serial_in(up, UART_EXAR_DVID);
879                 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
880                         DEBUG_AUTOCONF("Exar XR17V35x ");
881                         up->port.type = PORT_XR17V35X;
882                         up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
883                                                 UART_CAP_SLEEP;
884 
885                         return;
886                 }
887 
888         }
889 
890         /*
891          * Check for presence of the EFR when DLAB is set.
892          * Only ST16C650V1 UARTs pass this test.
893          */
894         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
895         if (serial_in(up, UART_EFR) == 0) {
896                 serial_out(up, UART_EFR, 0xA8);
897                 if (serial_in(up, UART_EFR) != 0) {
898                         DEBUG_AUTOCONF("EFRv1 ");
899                         up->port.type = PORT_16650;
900                         up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
901                 } else {
902                         DEBUG_AUTOCONF("Motorola 8xxx DUART ");
903                 }
904                 serial_out(up, UART_EFR, 0);
905                 return;
906         }
907 
908         /*
909          * Maybe it requires 0xbf to be written to the LCR.
910          * (other ST16C650V2 UARTs, TI16C752A, etc)
911          */
912         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
913         if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
914                 DEBUG_AUTOCONF("EFRv2 ");
915                 autoconfig_has_efr(up);
916                 return;
917         }
918 
919         /*
920          * Check for a National Semiconductor SuperIO chip.
921          * Attempt to switch to bank 2, read the value of the LOOP bit
922          * from EXCR1. Switch back to bank 0, change it in MCR. Then
923          * switch back to bank 2, read it from EXCR1 again and check
924          * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
925          */
926         serial_out(up, UART_LCR, 0);
927         status1 = serial_in(up, UART_MCR);
928         serial_out(up, UART_LCR, 0xE0);
929         status2 = serial_in(up, 0x02); /* EXCR1 */
930 
931         if (!((status2 ^ status1) & UART_MCR_LOOP)) {
932                 serial_out(up, UART_LCR, 0);
933                 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
934                 serial_out(up, UART_LCR, 0xE0);
935                 status2 = serial_in(up, 0x02); /* EXCR1 */
936                 serial_out(up, UART_LCR, 0);
937                 serial_out(up, UART_MCR, status1);
938 
939                 if ((status2 ^ status1) & UART_MCR_LOOP) {
940                         unsigned short quot;
941 
942                         serial_out(up, UART_LCR, 0xE0);
943 
944                         quot = serial_dl_read(up);
945                         quot <<= 3;
946 
947                         if (ns16550a_goto_highspeed(up))
948                                 serial_dl_write(up, quot);
949 
950                         serial_out(up, UART_LCR, 0);
951 
952                         up->port.uartclk = 921600*16;
953                         up->port.type = PORT_NS16550A;
954                         up->capabilities |= UART_NATSEMI;
955                         return;
956                 }
957         }
958 
959         /*
960          * No EFR.  Try to detect a TI16750, which only sets bit 5 of
961          * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
962          * Try setting it with and without DLAB set.  Cheap clones
963          * set bit 5 without DLAB set.
964          */
965         serial_out(up, UART_LCR, 0);
966         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
967         status1 = serial_in(up, UART_IIR) >> 5;
968         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
969         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
970         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
971         status2 = serial_in(up, UART_IIR) >> 5;
972         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
973         serial_out(up, UART_LCR, 0);
974 
975         DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
976 
977         if (status1 == 6 && status2 == 7) {
978                 up->port.type = PORT_16750;
979                 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
980                 return;
981         }
982 
983         /*
984          * Try writing and reading the UART_IER_UUE bit (b6).
985          * If it works, this is probably one of the Xscale platform's
986          * internal UARTs.
987          * We're going to explicitly set the UUE bit to 0 before
988          * trying to write and read a 1 just to make sure it's not
989          * already a 1 and maybe locked there before we even start start.
990          */
991         iersave = serial_in(up, UART_IER);
992         serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
993         if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
994                 /*
995                  * OK it's in a known zero state, try writing and reading
996                  * without disturbing the current state of the other bits.
997                  */
998                 serial_out(up, UART_IER, iersave | UART_IER_UUE);
999                 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1000                         /*
1001                          * It's an Xscale.
1002                          * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1003                          */
1004                         DEBUG_AUTOCONF("Xscale ");
1005                         up->port.type = PORT_XSCALE;
1006                         up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1007                         return;
1008                 }
1009         } else {
1010                 /*
1011                  * If we got here we couldn't force the IER_UUE bit to 0.
1012                  * Log it and continue.
1013                  */
1014                 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1015         }
1016         serial_out(up, UART_IER, iersave);
1017 
1018         /*
1019          * Exar uarts have EFR in a weird location
1020          */
1021         if (up->port.flags & UPF_EXAR_EFR) {
1022                 DEBUG_AUTOCONF("Exar XR17D15x ");
1023                 up->port.type = PORT_XR17D15X;
1024                 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1025                                     UART_CAP_SLEEP;
1026 
1027                 return;
1028         }
1029 
1030         /*
1031          * We distinguish between 16550A and U6 16550A by counting
1032          * how many bytes are in the FIFO.
1033          */
1034         if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1035                 up->port.type = PORT_U6_16550A;
1036                 up->capabilities |= UART_CAP_AFE;
1037         }
1038 }
1039 
1040 /*
1041  * This routine is called by rs_init() to initialize a specific serial
1042  * port.  It determines what type of UART chip this serial port is
1043  * using: 8250, 16450, 16550, 16550A.  The important question is
1044  * whether or not this UART is a 16550A or not, since this will
1045  * determine whether or not we can use its FIFO features or not.
1046  */
1047 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1048 {
1049         unsigned char status1, scratch, scratch2, scratch3;
1050         unsigned char save_lcr, save_mcr;
1051         struct uart_port *port = &up->port;
1052         unsigned long flags;
1053         unsigned int old_capabilities;
1054 
1055         if (!port->iobase && !port->mapbase && !port->membase)
1056                 return;
1057 
1058         DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1059                        serial_index(port), port->iobase, port->membase);
1060 
1061         /*
1062          * We really do need global IRQs disabled here - we're going to
1063          * be frobbing the chips IRQ enable register to see if it exists.
1064          */
1065         spin_lock_irqsave(&port->lock, flags);
1066 
1067         up->capabilities = 0;
1068         up->bugs = 0;
1069 
1070         if (!(port->flags & UPF_BUGGY_UART)) {
1071                 /*
1072                  * Do a simple existence test first; if we fail this,
1073                  * there's no point trying anything else.
1074                  *
1075                  * 0x80 is used as a nonsense port to prevent against
1076                  * false positives due to ISA bus float.  The
1077                  * assumption is that 0x80 is a non-existent port;
1078                  * which should be safe since include/asm/io.h also
1079                  * makes this assumption.
1080                  *
1081                  * Note: this is safe as long as MCR bit 4 is clear
1082                  * and the device is in "PC" mode.
1083                  */
1084                 scratch = serial_in(up, UART_IER);
1085                 serial_out(up, UART_IER, 0);
1086 #ifdef __i386__
1087                 outb(0xff, 0x080);
1088 #endif
1089                 /*
1090                  * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1091                  * 16C754B) allow only to modify them if an EFR bit is set.
1092                  */
1093                 scratch2 = serial_in(up, UART_IER) & 0x0f;
1094                 serial_out(up, UART_IER, 0x0F);
1095 #ifdef __i386__
1096                 outb(0, 0x080);
1097 #endif
1098                 scratch3 = serial_in(up, UART_IER) & 0x0f;
1099                 serial_out(up, UART_IER, scratch);
1100                 if (scratch2 != 0 || scratch3 != 0x0F) {
1101                         /*
1102                          * We failed; there's nothing here
1103                          */
1104                         spin_unlock_irqrestore(&port->lock, flags);
1105                         DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1106                                        scratch2, scratch3);
1107                         goto out;
1108                 }
1109         }
1110 
1111         save_mcr = serial_in(up, UART_MCR);
1112         save_lcr = serial_in(up, UART_LCR);
1113 
1114         /*
1115          * Check to see if a UART is really there.  Certain broken
1116          * internal modems based on the Rockwell chipset fail this
1117          * test, because they apparently don't implement the loopback
1118          * test mode.  So this test is skipped on the COM 1 through
1119          * COM 4 ports.  This *should* be safe, since no board
1120          * manufacturer would be stupid enough to design a board
1121          * that conflicts with COM 1-4 --- we hope!
1122          */
1123         if (!(port->flags & UPF_SKIP_TEST)) {
1124                 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1125                 status1 = serial_in(up, UART_MSR) & 0xF0;
1126                 serial_out(up, UART_MCR, save_mcr);
1127                 if (status1 != 0x90) {
1128                         spin_unlock_irqrestore(&port->lock, flags);
1129                         DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1130                                        status1);
1131                         goto out;
1132                 }
1133         }
1134 
1135         /*
1136          * We're pretty sure there's a port here.  Lets find out what
1137          * type of port it is.  The IIR top two bits allows us to find
1138          * out if it's 8250 or 16450, 16550, 16550A or later.  This
1139          * determines what we test for next.
1140          *
1141          * We also initialise the EFR (if any) to zero for later.  The
1142          * EFR occupies the same register location as the FCR and IIR.
1143          */
1144         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1145         serial_out(up, UART_EFR, 0);
1146         serial_out(up, UART_LCR, 0);
1147 
1148         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1149         scratch = serial_in(up, UART_IIR) >> 6;
1150 
1151         switch (scratch) {
1152         case 0:
1153                 autoconfig_8250(up);
1154                 break;
1155         case 1:
1156                 port->type = PORT_UNKNOWN;
1157                 break;
1158         case 2:
1159                 port->type = PORT_16550;
1160                 break;
1161         case 3:
1162                 autoconfig_16550a(up);
1163                 break;
1164         }
1165 
1166 #ifdef CONFIG_SERIAL_8250_RSA
1167         /*
1168          * Only probe for RSA ports if we got the region.
1169          */
1170         if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1171                 int i;
1172 
1173                 for (i = 0 ; i < probe_rsa_count; ++i) {
1174                         if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1175                                 port->type = PORT_RSA;
1176                                 break;
1177                         }
1178                 }
1179         }
1180 #endif
1181 
1182         serial_out(up, UART_LCR, save_lcr);
1183 
1184         port->fifosize = uart_config[up->port.type].fifo_size;
1185         old_capabilities = up->capabilities; 
1186         up->capabilities = uart_config[port->type].flags;
1187         up->tx_loadsz = uart_config[port->type].tx_loadsz;
1188 
1189         if (port->type == PORT_UNKNOWN)
1190                 goto out_lock;
1191 
1192         /*
1193          * Reset the UART.
1194          */
1195 #ifdef CONFIG_SERIAL_8250_RSA
1196         if (port->type == PORT_RSA)
1197                 serial_out(up, UART_RSA_FRR, 0);
1198 #endif
1199         serial_out(up, UART_MCR, save_mcr);
1200         serial8250_clear_fifos(up);
1201         serial_in(up, UART_RX);
1202         if (up->capabilities & UART_CAP_UUE)
1203                 serial_out(up, UART_IER, UART_IER_UUE);
1204         else
1205                 serial_out(up, UART_IER, 0);
1206 
1207 out_lock:
1208         spin_unlock_irqrestore(&port->lock, flags);
1209         if (up->capabilities != old_capabilities) {
1210                 printk(KERN_WARNING
1211                        "ttyS%d: detected caps %08x should be %08x\n",
1212                        serial_index(port), old_capabilities,
1213                        up->capabilities);
1214         }
1215 out:
1216         DEBUG_AUTOCONF("iir=%d ", scratch);
1217         DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1218 }
1219 
1220 static void autoconfig_irq(struct uart_8250_port *up)
1221 {
1222         struct uart_port *port = &up->port;
1223         unsigned char save_mcr, save_ier;
1224         unsigned char save_ICP = 0;
1225         unsigned int ICP = 0;
1226         unsigned long irqs;
1227         int irq;
1228 
1229         if (port->flags & UPF_FOURPORT) {
1230                 ICP = (port->iobase & 0xfe0) | 0x1f;
1231                 save_ICP = inb_p(ICP);
1232                 outb_p(0x80, ICP);
1233                 inb_p(ICP);
1234         }
1235 
1236         /* forget possible initially masked and pending IRQ */
1237         probe_irq_off(probe_irq_on());
1238         save_mcr = serial_in(up, UART_MCR);
1239         save_ier = serial_in(up, UART_IER);
1240         serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1241 
1242         irqs = probe_irq_on();
1243         serial_out(up, UART_MCR, 0);
1244         udelay(10);
1245         if (port->flags & UPF_FOURPORT) {
1246                 serial_out(up, UART_MCR,
1247                             UART_MCR_DTR | UART_MCR_RTS);
1248         } else {
1249                 serial_out(up, UART_MCR,
1250                             UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1251         }
1252         serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1253         serial_in(up, UART_LSR);
1254         serial_in(up, UART_RX);
1255         serial_in(up, UART_IIR);
1256         serial_in(up, UART_MSR);
1257         serial_out(up, UART_TX, 0xFF);
1258         udelay(20);
1259         irq = probe_irq_off(irqs);
1260 
1261         serial_out(up, UART_MCR, save_mcr);
1262         serial_out(up, UART_IER, save_ier);
1263 
1264         if (port->flags & UPF_FOURPORT)
1265                 outb_p(save_ICP, ICP);
1266 
1267         port->irq = (irq > 0) ? irq : 0;
1268 }
1269 
1270 static inline void __stop_tx(struct uart_8250_port *p)
1271 {
1272         if (p->ier & UART_IER_THRI) {
1273                 p->ier &= ~UART_IER_THRI;
1274                 serial_out(p, UART_IER, p->ier);
1275         }
1276 }
1277 
1278 static void serial8250_stop_tx(struct uart_port *port)
1279 {
1280         struct uart_8250_port *up =
1281                 container_of(port, struct uart_8250_port, port);
1282 
1283         __stop_tx(up);
1284 
1285         /*
1286          * We really want to stop the transmitter from sending.
1287          */
1288         if (port->type == PORT_16C950) {
1289                 up->acr |= UART_ACR_TXDIS;
1290                 serial_icr_write(up, UART_ACR, up->acr);
1291         }
1292 }
1293 
1294 static void serial8250_start_tx(struct uart_port *port)
1295 {
1296         struct uart_8250_port *up =
1297                 container_of(port, struct uart_8250_port, port);
1298 
1299         if (up->dma && !serial8250_tx_dma(up)) {
1300                 return;
1301         } else if (!(up->ier & UART_IER_THRI)) {
1302                 up->ier |= UART_IER_THRI;
1303                 serial_port_out(port, UART_IER, up->ier);
1304 
1305                 if (up->bugs & UART_BUG_TXEN) {
1306                         unsigned char lsr;
1307                         lsr = serial_in(up, UART_LSR);
1308                         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1309                         if (lsr & UART_LSR_TEMT)
1310                                 serial8250_tx_chars(up);
1311                 }
1312         }
1313 
1314         /*
1315          * Re-enable the transmitter if we disabled it.
1316          */
1317         if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1318                 up->acr &= ~UART_ACR_TXDIS;
1319                 serial_icr_write(up, UART_ACR, up->acr);
1320         }
1321 }
1322 
1323 static void serial8250_stop_rx(struct uart_port *port)
1324 {
1325         struct uart_8250_port *up =
1326                 container_of(port, struct uart_8250_port, port);
1327 
1328         up->ier &= ~UART_IER_RLSI;
1329         up->port.read_status_mask &= ~UART_LSR_DR;
1330         serial_port_out(port, UART_IER, up->ier);
1331 }
1332 
1333 static void serial8250_enable_ms(struct uart_port *port)
1334 {
1335         struct uart_8250_port *up =
1336                 container_of(port, struct uart_8250_port, port);
1337 
1338         /* no MSR capabilities */
1339         if (up->bugs & UART_BUG_NOMSR)
1340                 return;
1341 
1342         up->ier |= UART_IER_MSI;
1343         serial_port_out(port, UART_IER, up->ier);
1344 }
1345 
1346 /*
1347  * serial8250_rx_chars: processes according to the passed in LSR
1348  * value, and returns the remaining LSR bits not handled
1349  * by this Rx routine.
1350  */
1351 unsigned char
1352 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1353 {
1354         struct uart_port *port = &up->port;
1355         unsigned char ch;
1356         int max_count = 256;
1357         char flag;
1358 
1359         do {
1360                 if (likely(lsr & UART_LSR_DR))
1361                         ch = serial_in(up, UART_RX);
1362                 else
1363                         /*
1364                          * Intel 82571 has a Serial Over Lan device that will
1365                          * set UART_LSR_BI without setting UART_LSR_DR when
1366                          * it receives a break. To avoid reading from the
1367                          * receive buffer without UART_LSR_DR bit set, we
1368                          * just force the read character to be 0
1369                          */
1370                         ch = 0;
1371 
1372                 flag = TTY_NORMAL;
1373                 port->icount.rx++;
1374 
1375                 lsr |= up->lsr_saved_flags;
1376                 up->lsr_saved_flags = 0;
1377 
1378                 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1379                         if (lsr & UART_LSR_BI) {
1380                                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1381                                 port->icount.brk++;
1382                                 /*
1383                                  * We do the SysRQ and SAK checking
1384                                  * here because otherwise the break
1385                                  * may get masked by ignore_status_mask
1386                                  * or read_status_mask.
1387                                  */
1388                                 if (uart_handle_break(port))
1389                                         goto ignore_char;
1390                         } else if (lsr & UART_LSR_PE)
1391                                 port->icount.parity++;
1392                         else if (lsr & UART_LSR_FE)
1393                                 port->icount.frame++;
1394                         if (lsr & UART_LSR_OE)
1395                                 port->icount.overrun++;
1396 
1397                         /*
1398                          * Mask off conditions which should be ignored.
1399                          */
1400                         lsr &= port->read_status_mask;
1401 
1402                         if (lsr & UART_LSR_BI) {
1403                                 DEBUG_INTR("handling break....");
1404                                 flag = TTY_BREAK;
1405                         } else if (lsr & UART_LSR_PE)
1406                                 flag = TTY_PARITY;
1407                         else if (lsr & UART_LSR_FE)
1408                                 flag = TTY_FRAME;
1409                 }
1410                 if (uart_handle_sysrq_char(port, ch))
1411                         goto ignore_char;
1412 
1413                 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1414 
1415 ignore_char:
1416                 lsr = serial_in(up, UART_LSR);
1417         } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1418         spin_unlock(&port->lock);
1419         tty_flip_buffer_push(&port->state->port);
1420         spin_lock(&port->lock);
1421         return lsr;
1422 }
1423 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1424 
1425 void serial8250_tx_chars(struct uart_8250_port *up)
1426 {
1427         struct uart_port *port = &up->port;
1428         struct circ_buf *xmit = &port->state->xmit;
1429         int count;
1430 
1431         if (port->x_char) {
1432                 serial_out(up, UART_TX, port->x_char);
1433                 port->icount.tx++;
1434                 port->x_char = 0;
1435                 return;
1436         }
1437         if (uart_tx_stopped(port)) {
1438                 serial8250_stop_tx(port);
1439                 return;
1440         }
1441         if (uart_circ_empty(xmit)) {
1442                 __stop_tx(up);
1443                 return;
1444         }
1445 
1446         count = up->tx_loadsz;
1447         do {
1448                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1449                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1450                 port->icount.tx++;
1451                 if (uart_circ_empty(xmit))
1452                         break;
1453                 if (up->capabilities & UART_CAP_HFIFO) {
1454                         if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1455                             BOTH_EMPTY)
1456                                 break;
1457                 }
1458         } while (--count > 0);
1459 
1460         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1461                 uart_write_wakeup(port);
1462 
1463         DEBUG_INTR("THRE...");
1464 
1465         if (uart_circ_empty(xmit))
1466                 __stop_tx(up);
1467 }
1468 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1469 
1470 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1471 {
1472         struct uart_port *port = &up->port;
1473         unsigned int status = serial_in(up, UART_MSR);
1474 
1475         status |= up->msr_saved_flags;
1476         up->msr_saved_flags = 0;
1477         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1478             port->state != NULL) {
1479                 if (status & UART_MSR_TERI)
1480                         port->icount.rng++;
1481                 if (status & UART_MSR_DDSR)
1482                         port->icount.dsr++;
1483                 if (status & UART_MSR_DDCD)
1484                         uart_handle_dcd_change(port, status & UART_MSR_DCD);
1485                 if (status & UART_MSR_DCTS)
1486                         uart_handle_cts_change(port, status & UART_MSR_CTS);
1487 
1488                 wake_up_interruptible(&port->state->port.delta_msr_wait);
1489         }
1490 
1491         return status;
1492 }
1493 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1494 
1495 /*
1496  * This handles the interrupt from one port.
1497  */
1498 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1499 {
1500         unsigned char status;
1501         unsigned long flags;
1502         struct uart_8250_port *up =
1503                 container_of(port, struct uart_8250_port, port);
1504         int dma_err = 0;
1505 
1506         if (iir & UART_IIR_NO_INT)
1507                 return 0;
1508 
1509         spin_lock_irqsave(&port->lock, flags);
1510 
1511         status = serial_port_in(port, UART_LSR);
1512 
1513         DEBUG_INTR("status = %x...", status);
1514 
1515         if (status & (UART_LSR_DR | UART_LSR_BI)) {
1516                 if (up->dma)
1517                         dma_err = serial8250_rx_dma(up, iir);
1518 
1519                 if (!up->dma || dma_err)
1520                         status = serial8250_rx_chars(up, status);
1521         }
1522         serial8250_modem_status(up);
1523         if (!up->dma && (status & UART_LSR_THRE))
1524                 serial8250_tx_chars(up);
1525 
1526         spin_unlock_irqrestore(&port->lock, flags);
1527         return 1;
1528 }
1529 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1530 
1531 static int serial8250_default_handle_irq(struct uart_port *port)
1532 {
1533         unsigned int iir = serial_port_in(port, UART_IIR);
1534 
1535         return serial8250_handle_irq(port, iir);
1536 }
1537 
1538 /*
1539  * These Exar UARTs have an extra interrupt indicator that could
1540  * fire for a few unimplemented interrupts.  One of which is a
1541  * wakeup event when coming out of sleep.  Put this here just
1542  * to be on the safe side that these interrupts don't go unhandled.
1543  */
1544 static int exar_handle_irq(struct uart_port *port)
1545 {
1546         unsigned char int0, int1, int2, int3;
1547         unsigned int iir = serial_port_in(port, UART_IIR);
1548         int ret;
1549 
1550         ret = serial8250_handle_irq(port, iir);
1551 
1552         if ((port->type == PORT_XR17V35X) ||
1553            (port->type == PORT_XR17D15X)) {
1554                 int0 = serial_port_in(port, 0x80);
1555                 int1 = serial_port_in(port, 0x81);
1556                 int2 = serial_port_in(port, 0x82);
1557                 int3 = serial_port_in(port, 0x83);
1558         }
1559 
1560         return ret;
1561 }
1562 
1563 /*
1564  * This is the serial driver's interrupt routine.
1565  *
1566  * Arjan thinks the old way was overly complex, so it got simplified.
1567  * Alan disagrees, saying that need the complexity to handle the weird
1568  * nature of ISA shared interrupts.  (This is a special exception.)
1569  *
1570  * In order to handle ISA shared interrupts properly, we need to check
1571  * that all ports have been serviced, and therefore the ISA interrupt
1572  * line has been de-asserted.
1573  *
1574  * This means we need to loop through all ports. checking that they
1575  * don't have an interrupt pending.
1576  */
1577 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1578 {
1579         struct irq_info *i = dev_id;
1580         struct list_head *l, *end = NULL;
1581         int pass_counter = 0, handled = 0;
1582 
1583         DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1584 
1585         spin_lock(&i->lock);
1586 
1587         l = i->head;
1588         do {
1589                 struct uart_8250_port *up;
1590                 struct uart_port *port;
1591 
1592                 up = list_entry(l, struct uart_8250_port, list);
1593                 port = &up->port;
1594 
1595                 if (port->handle_irq(port)) {
1596                         handled = 1;
1597                         end = NULL;
1598                 } else if (end == NULL)
1599                         end = l;
1600 
1601                 l = l->next;
1602 
1603                 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1604                         /* If we hit this, we're dead. */
1605                         printk_ratelimited(KERN_ERR
1606                                 "serial8250: too much work for irq%d\n", irq);
1607                         break;
1608                 }
1609         } while (l != end);
1610 
1611         spin_unlock(&i->lock);
1612 
1613         DEBUG_INTR("end.\n");
1614 
1615         return IRQ_RETVAL(handled);
1616 }
1617 
1618 /*
1619  * To support ISA shared interrupts, we need to have one interrupt
1620  * handler that ensures that the IRQ line has been deasserted
1621  * before returning.  Failing to do this will result in the IRQ
1622  * line being stuck active, and, since ISA irqs are edge triggered,
1623  * no more IRQs will be seen.
1624  */
1625 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1626 {
1627         spin_lock_irq(&i->lock);
1628 
1629         if (!list_empty(i->head)) {
1630                 if (i->head == &up->list)
1631                         i->head = i->head->next;
1632                 list_del(&up->list);
1633         } else {
1634                 BUG_ON(i->head != &up->list);
1635                 i->head = NULL;
1636         }
1637         spin_unlock_irq(&i->lock);
1638         /* List empty so throw away the hash node */
1639         if (i->head == NULL) {
1640                 hlist_del(&i->node);
1641                 kfree(i);
1642         }
1643 }
1644 
1645 static int serial_link_irq_chain(struct uart_8250_port *up)
1646 {
1647         struct hlist_head *h;
1648         struct hlist_node *n;
1649         struct irq_info *i;
1650         int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1651 
1652         mutex_lock(&hash_mutex);
1653 
1654         h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1655 
1656         hlist_for_each(n, h) {
1657                 i = hlist_entry(n, struct irq_info, node);
1658                 if (i->irq == up->port.irq)
1659                         break;
1660         }
1661 
1662         if (n == NULL) {
1663                 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1664                 if (i == NULL) {
1665                         mutex_unlock(&hash_mutex);
1666                         return -ENOMEM;
1667                 }
1668                 spin_lock_init(&i->lock);
1669                 i->irq = up->port.irq;
1670                 hlist_add_head(&i->node, h);
1671         }
1672         mutex_unlock(&hash_mutex);
1673 
1674         spin_lock_irq(&i->lock);
1675 
1676         if (i->head) {
1677                 list_add(&up->list, i->head);
1678                 spin_unlock_irq(&i->lock);
1679 
1680                 ret = 0;
1681         } else {
1682                 INIT_LIST_HEAD(&up->list);
1683                 i->head = &up->list;
1684                 spin_unlock_irq(&i->lock);
1685                 irq_flags |= up->port.irqflags;
1686                 ret = request_irq(up->port.irq, serial8250_interrupt,
1687                                   irq_flags, "serial", i);
1688                 if (ret < 0)
1689                         serial_do_unlink(i, up);
1690         }
1691 
1692         return ret;
1693 }
1694 
1695 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1696 {
1697         /*
1698          * yes, some broken gcc emit "warning: 'i' may be used uninitialized"
1699          * but no, we are not going to take a patch that assigns NULL below.
1700          */
1701         struct irq_info *i;
1702         struct hlist_node *n;
1703         struct hlist_head *h;
1704 
1705         mutex_lock(&hash_mutex);
1706 
1707         h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1708 
1709         hlist_for_each(n, h) {
1710                 i = hlist_entry(n, struct irq_info, node);
1711                 if (i->irq == up->port.irq)
1712                         break;
1713         }
1714 
1715         BUG_ON(n == NULL);
1716         BUG_ON(i->head == NULL);
1717 
1718         if (list_empty(i->head))
1719                 free_irq(up->port.irq, i);
1720 
1721         serial_do_unlink(i, up);
1722         mutex_unlock(&hash_mutex);
1723 }
1724 
1725 /*
1726  * This function is used to handle ports that do not have an
1727  * interrupt.  This doesn't work very well for 16450's, but gives
1728  * barely passable results for a 16550A.  (Although at the expense
1729  * of much CPU overhead).
1730  */
1731 static void serial8250_timeout(unsigned long data)
1732 {
1733         struct uart_8250_port *up = (struct uart_8250_port *)data;
1734 
1735         up->port.handle_irq(&up->port);
1736         mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1737 }
1738 
1739 static void serial8250_backup_timeout(unsigned long data)
1740 {
1741         struct uart_8250_port *up = (struct uart_8250_port *)data;
1742         unsigned int iir, ier = 0, lsr;
1743         unsigned long flags;
1744 
1745         spin_lock_irqsave(&up->port.lock, flags);
1746 
1747         /*
1748          * Must disable interrupts or else we risk racing with the interrupt
1749          * based handler.
1750          */
1751         if (up->port.irq) {
1752                 ier = serial_in(up, UART_IER);
1753                 serial_out(up, UART_IER, 0);
1754         }
1755 
1756         iir = serial_in(up, UART_IIR);
1757 
1758         /*
1759          * This should be a safe test for anyone who doesn't trust the
1760          * IIR bits on their UART, but it's specifically designed for
1761          * the "Diva" UART used on the management processor on many HP
1762          * ia64 and parisc boxes.
1763          */
1764         lsr = serial_in(up, UART_LSR);
1765         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1766         if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1767             (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1768             (lsr & UART_LSR_THRE)) {
1769                 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1770                 iir |= UART_IIR_THRI;
1771         }
1772 
1773         if (!(iir & UART_IIR_NO_INT))
1774                 serial8250_tx_chars(up);
1775 
1776         if (up->port.irq)
1777                 serial_out(up, UART_IER, ier);
1778 
1779         spin_unlock_irqrestore(&up->port.lock, flags);
1780 
1781         /* Standard timer interval plus 0.2s to keep the port running */
1782         mod_timer(&up->timer,
1783                 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1784 }
1785 
1786 static unsigned int serial8250_tx_empty(struct uart_port *port)
1787 {
1788         struct uart_8250_port *up =
1789                 container_of(port, struct uart_8250_port, port);
1790         unsigned long flags;
1791         unsigned int lsr;
1792 
1793         spin_lock_irqsave(&port->lock, flags);
1794         lsr = serial_port_in(port, UART_LSR);
1795         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1796         spin_unlock_irqrestore(&port->lock, flags);
1797 
1798         return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1799 }
1800 
1801 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1802 {
1803         struct uart_8250_port *up =
1804                 container_of(port, struct uart_8250_port, port);
1805         unsigned int status;
1806         unsigned int ret;
1807 
1808         status = serial8250_modem_status(up);
1809 
1810         ret = 0;
1811         if (status & UART_MSR_DCD)
1812                 ret |= TIOCM_CAR;
1813         if (status & UART_MSR_RI)
1814                 ret |= TIOCM_RNG;
1815         if (status & UART_MSR_DSR)
1816                 ret |= TIOCM_DSR;
1817         if (status & UART_MSR_CTS)
1818                 ret |= TIOCM_CTS;
1819         return ret;
1820 }
1821 
1822 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1823 {
1824         struct uart_8250_port *up =
1825                 container_of(port, struct uart_8250_port, port);
1826         unsigned char mcr = 0;
1827 
1828         if (mctrl & TIOCM_RTS)
1829                 mcr |= UART_MCR_RTS;
1830         if (mctrl & TIOCM_DTR)
1831                 mcr |= UART_MCR_DTR;
1832         if (mctrl & TIOCM_OUT1)
1833                 mcr |= UART_MCR_OUT1;
1834         if (mctrl & TIOCM_OUT2)
1835                 mcr |= UART_MCR_OUT2;
1836         if (mctrl & TIOCM_LOOP)
1837                 mcr |= UART_MCR_LOOP;
1838 
1839         mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1840 
1841         serial_port_out(port, UART_MCR, mcr);
1842 }
1843 
1844 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1845 {
1846         struct uart_8250_port *up =
1847                 container_of(port, struct uart_8250_port, port);
1848         unsigned long flags;
1849 
1850         spin_lock_irqsave(&port->lock, flags);
1851         if (break_state == -1)
1852                 up->lcr |= UART_LCR_SBC;
1853         else
1854                 up->lcr &= ~UART_LCR_SBC;
1855         serial_port_out(port, UART_LCR, up->lcr);
1856         spin_unlock_irqrestore(&port->lock, flags);
1857 }
1858 
1859 /*
1860  *      Wait for transmitter & holding register to empty
1861  */
1862 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1863 {
1864         unsigned int status, tmout = 10000;
1865 
1866         /* Wait up to 10ms for the character(s) to be sent. */
1867         for (;;) {
1868                 status = serial_in(up, UART_LSR);
1869 
1870                 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1871 
1872                 if ((status & bits) == bits)
1873                         break;
1874                 if (--tmout == 0)
1875                         break;
1876                 udelay(1);
1877         }
1878 
1879         /* Wait up to 1s for flow control if necessary */
1880         if (up->port.flags & UPF_CONS_FLOW) {
1881                 unsigned int tmout;
1882                 for (tmout = 1000000; tmout; tmout--) {
1883                         unsigned int msr = serial_in(up, UART_MSR);
1884                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1885                         if (msr & UART_MSR_CTS)
1886                                 break;
1887                         udelay(1);
1888                         touch_nmi_watchdog();
1889                 }
1890         }
1891 }
1892 
1893 #ifdef CONFIG_CONSOLE_POLL
1894 /*
1895  * Console polling routines for writing and reading from the uart while
1896  * in an interrupt or debug context.
1897  */
1898 
1899 static int serial8250_get_poll_char(struct uart_port *port)
1900 {
1901         unsigned char lsr = serial_port_in(port, UART_LSR);
1902 
1903         if (!(lsr & UART_LSR_DR))
1904                 return NO_POLL_CHAR;
1905 
1906         return serial_port_in(port, UART_RX);
1907 }
1908 
1909 
1910 static void serial8250_put_poll_char(struct uart_port *port,
1911                          unsigned char c)
1912 {
1913         unsigned int ier;
1914         struct uart_8250_port *up =
1915                 container_of(port, struct uart_8250_port, port);
1916 
1917         /*
1918          *      First save the IER then disable the interrupts
1919          */
1920         ier = serial_port_in(port, UART_IER);
1921         if (up->capabilities & UART_CAP_UUE)
1922                 serial_port_out(port, UART_IER, UART_IER_UUE);
1923         else
1924                 serial_port_out(port, UART_IER, 0);
1925 
1926         wait_for_xmitr(up, BOTH_EMPTY);
1927         /*
1928          *      Send the character out.
1929          */
1930         serial_port_out(port, UART_TX, c);
1931 
1932         /*
1933          *      Finally, wait for transmitter to become empty
1934          *      and restore the IER
1935          */
1936         wait_for_xmitr(up, BOTH_EMPTY);
1937         serial_port_out(port, UART_IER, ier);
1938 }
1939 
1940 #endif /* CONFIG_CONSOLE_POLL */
1941 
1942 static int serial8250_startup(struct uart_port *port)
1943 {
1944         struct uart_8250_port *up =
1945                 container_of(port, struct uart_8250_port, port);
1946         unsigned long flags;
1947         unsigned char lsr, iir;
1948         int retval;
1949 
1950         if (port->type == PORT_8250_CIR)
1951                 return -ENODEV;
1952 
1953         if (!port->fifosize)
1954                 port->fifosize = uart_config[port->type].fifo_size;
1955         if (!up->tx_loadsz)
1956                 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1957         if (!up->capabilities)
1958                 up->capabilities = uart_config[port->type].flags;
1959         up->mcr = 0;
1960 
1961         if (port->iotype != up->cur_iotype)
1962                 set_io_from_upio(port);
1963 
1964         if (port->type == PORT_16C950) {
1965                 /* Wake up and initialize UART */
1966                 up->acr = 0;
1967                 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1968                 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1969                 serial_port_out(port, UART_IER, 0);
1970                 serial_port_out(port, UART_LCR, 0);
1971                 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1972                 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1973                 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1974                 serial_port_out(port, UART_LCR, 0);
1975         }
1976 
1977 #ifdef CONFIG_SERIAL_8250_RSA
1978         /*
1979          * If this is an RSA port, see if we can kick it up to the
1980          * higher speed clock.
1981          */
1982         enable_rsa(up);
1983 #endif
1984 
1985         /*
1986          * Clear the FIFO buffers and disable them.
1987          * (they will be reenabled in set_termios())
1988          */
1989         serial8250_clear_fifos(up);
1990 
1991         /*
1992          * Clear the interrupt registers.
1993          */
1994         serial_port_in(port, UART_LSR);
1995         serial_port_in(port, UART_RX);
1996         serial_port_in(port, UART_IIR);
1997         serial_port_in(port, UART_MSR);
1998 
1999         /*
2000          * At this point, there's no way the LSR could still be 0xff;
2001          * if it is, then bail out, because there's likely no UART
2002          * here.
2003          */
2004         if (!(port->flags & UPF_BUGGY_UART) &&
2005             (serial_port_in(port, UART_LSR) == 0xff)) {
2006                 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2007                                    serial_index(port));
2008                 return -ENODEV;
2009         }
2010 
2011         /*
2012          * For a XR16C850, we need to set the trigger levels
2013          */
2014         if (port->type == PORT_16850) {
2015                 unsigned char fctr;
2016 
2017                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2018 
2019                 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2020                 serial_port_out(port, UART_FCTR,
2021                                 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2022                 serial_port_out(port, UART_TRG, UART_TRG_96);
2023                 serial_port_out(port, UART_FCTR,
2024                                 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2025                 serial_port_out(port, UART_TRG, UART_TRG_96);
2026 
2027                 serial_port_out(port, UART_LCR, 0);
2028         }
2029 
2030         if (port->irq) {
2031                 unsigned char iir1;
2032                 /*
2033                  * Test for UARTs that do not reassert THRE when the
2034                  * transmitter is idle and the interrupt has already
2035                  * been cleared.  Real 16550s should always reassert
2036                  * this interrupt whenever the transmitter is idle and
2037                  * the interrupt is enabled.  Delays are necessary to
2038                  * allow register changes to become visible.
2039                  */
2040                 spin_lock_irqsave(&port->lock, flags);
2041                 if (up->port.irqflags & IRQF_SHARED)
2042                         disable_irq_nosync(port->irq);
2043 
2044                 wait_for_xmitr(up, UART_LSR_THRE);
2045                 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2046                 udelay(1); /* allow THRE to set */
2047                 iir1 = serial_port_in(port, UART_IIR);
2048                 serial_port_out(port, UART_IER, 0);
2049                 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2050                 udelay(1); /* allow a working UART time to re-assert THRE */
2051                 iir = serial_port_in(port, UART_IIR);
2052                 serial_port_out(port, UART_IER, 0);
2053 
2054                 if (port->irqflags & IRQF_SHARED)
2055                         enable_irq(port->irq);
2056                 spin_unlock_irqrestore(&port->lock, flags);
2057 
2058                 /*
2059                  * If the interrupt is not reasserted, or we otherwise
2060                  * don't trust the iir, setup a timer to kick the UART
2061                  * on a regular basis.
2062                  */
2063                 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2064                     up->port.flags & UPF_BUG_THRE) {
2065                         up->bugs |= UART_BUG_THRE;
2066                         pr_debug("ttyS%d - using backup timer\n",
2067                                  serial_index(port));
2068                 }
2069         }
2070 
2071         /*
2072          * The above check will only give an accurate result the first time
2073          * the port is opened so this value needs to be preserved.
2074          */
2075         if (up->bugs & UART_BUG_THRE) {
2076                 up->timer.function = serial8250_backup_timeout;
2077                 up->timer.data = (unsigned long)up;
2078                 mod_timer(&up->timer, jiffies +
2079                         uart_poll_timeout(port) + HZ / 5);
2080         }
2081 
2082         /*
2083          * If the "interrupt" for this port doesn't correspond with any
2084          * hardware interrupt, we use a timer-based system.  The original
2085          * driver used to do this with IRQ0.
2086          */
2087         if (!port->irq) {
2088                 up->timer.data = (unsigned long)up;
2089                 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2090         } else {
2091                 retval = serial_link_irq_chain(up);
2092                 if (retval)
2093                         return retval;
2094         }
2095 
2096         /*
2097          * Now, initialize the UART
2098          */
2099         serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2100 
2101         spin_lock_irqsave(&port->lock, flags);
2102         if (up->port.flags & UPF_FOURPORT) {
2103                 if (!up->port.irq)
2104                         up->port.mctrl |= TIOCM_OUT1;
2105         } else
2106                 /*
2107                  * Most PC uarts need OUT2 raised to enable interrupts.
2108                  */
2109                 if (port->irq)
2110                         up->port.mctrl |= TIOCM_OUT2;
2111 
2112         serial8250_set_mctrl(port, port->mctrl);
2113 
2114         /* Serial over Lan (SoL) hack:
2115            Intel 8257x Gigabit ethernet chips have a
2116            16550 emulation, to be used for Serial Over Lan.
2117            Those chips take a longer time than a normal
2118            serial device to signalize that a transmission
2119            data was queued. Due to that, the above test generally
2120            fails. One solution would be to delay the reading of
2121            iir. However, this is not reliable, since the timeout
2122            is variable. So, let's just don't test if we receive
2123            TX irq. This way, we'll never enable UART_BUG_TXEN.
2124          */
2125         if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2126                 goto dont_test_tx_en;
2127 
2128         /*
2129          * Do a quick test to see if we receive an
2130          * interrupt when we enable the TX irq.
2131          */
2132         serial_port_out(port, UART_IER, UART_IER_THRI);
2133         lsr = serial_port_in(port, UART_LSR);
2134         iir = serial_port_in(port, UART_IIR);
2135         serial_port_out(port, UART_IER, 0);
2136 
2137         if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2138                 if (!(up->bugs & UART_BUG_TXEN)) {
2139                         up->bugs |= UART_BUG_TXEN;
2140                         pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2141                                  serial_index(port));
2142                 }
2143         } else {
2144                 up->bugs &= ~UART_BUG_TXEN;
2145         }
2146 
2147 dont_test_tx_en:
2148         spin_unlock_irqrestore(&port->lock, flags);
2149 
2150         /*
2151          * Clear the interrupt registers again for luck, and clear the
2152          * saved flags to avoid getting false values from polling
2153          * routines or the previous session.
2154          */
2155         serial_port_in(port, UART_LSR);
2156         serial_port_in(port, UART_RX);
2157         serial_port_in(port, UART_IIR);
2158         serial_port_in(port, UART_MSR);
2159         up->lsr_saved_flags = 0;
2160         up->msr_saved_flags = 0;
2161 
2162         /*
2163          * Request DMA channels for both RX and TX.
2164          */
2165         if (up->dma) {
2166                 retval = serial8250_request_dma(up);
2167                 if (retval) {
2168                         pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2169                                             serial_index(port));
2170                         up->dma = NULL;
2171                 }
2172         }
2173 
2174         /*
2175          * Finally, enable interrupts.  Note: Modem status interrupts
2176          * are set via set_termios(), which will be occurring imminently
2177          * anyway, so we don't enable them here.
2178          */
2179         up->ier = UART_IER_RLSI | UART_IER_RDI;
2180         serial_port_out(port, UART_IER, up->ier);
2181 
2182         if (port->flags & UPF_FOURPORT) {
2183                 unsigned int icp;
2184                 /*
2185                  * Enable interrupts on the AST Fourport board
2186                  */
2187                 icp = (port->iobase & 0xfe0) | 0x01f;
2188                 outb_p(0x80, icp);
2189                 inb_p(icp);
2190         }
2191 
2192         return 0;
2193 }
2194 
2195 static void serial8250_shutdown(struct uart_port *port)
2196 {
2197         struct uart_8250_port *up =
2198                 container_of(port, struct uart_8250_port, port);
2199         unsigned long flags;
2200 
2201         /*
2202          * Disable interrupts from this port
2203          */
2204         up->ier = 0;
2205         serial_port_out(port, UART_IER, 0);
2206 
2207         if (up->dma)
2208                 serial8250_release_dma(up);
2209 
2210         spin_lock_irqsave(&port->lock, flags);
2211         if (port->flags & UPF_FOURPORT) {
2212                 /* reset interrupts on the AST Fourport board */
2213                 inb((port->iobase & 0xfe0) | 0x1f);
2214                 port->mctrl |= TIOCM_OUT1;
2215         } else
2216                 port->mctrl &= ~TIOCM_OUT2;
2217 
2218         serial8250_set_mctrl(port, port->mctrl);
2219         spin_unlock_irqrestore(&port->lock, flags);
2220 
2221         /*
2222          * Disable break condition and FIFOs
2223          */
2224         serial_port_out(port, UART_LCR,
2225                         serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2226         serial8250_clear_fifos(up);
2227 
2228 #ifdef CONFIG_SERIAL_8250_RSA
2229         /*
2230          * Reset the RSA board back to 115kbps compat mode.
2231          */
2232         disable_rsa(up);
2233 #endif
2234 
2235         /*
2236          * Read data port to reset things, and then unlink from
2237          * the IRQ chain.
2238          */
2239         serial_port_in(port, UART_RX);
2240 
2241         del_timer_sync(&up->timer);
2242         up->timer.function = serial8250_timeout;
2243         if (port->irq)
2244                 serial_unlink_irq_chain(up);
2245 }
2246 
2247 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2248 {
2249         unsigned int quot;
2250 
2251         /*
2252          * Handle magic divisors for baud rates above baud_base on
2253          * SMSC SuperIO chips.
2254          */
2255         if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2256             baud == (port->uartclk/4))
2257                 quot = 0x8001;
2258         else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2259                  baud == (port->uartclk/8))
2260                 quot = 0x8002;
2261         else
2262                 quot = uart_get_divisor(port, baud);
2263 
2264         return quot;
2265 }
2266 
2267 void
2268 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2269                           struct ktermios *old)
2270 {
2271         struct uart_8250_port *up =
2272                 container_of(port, struct uart_8250_port, port);
2273         unsigned char cval, fcr = 0;
2274         unsigned long flags;
2275         unsigned int baud, quot;
2276         int fifo_bug = 0;
2277 
2278         switch (termios->c_cflag & CSIZE) {
2279         case CS5:
2280                 cval = UART_LCR_WLEN5;
2281                 break;
2282         case CS6:
2283                 cval = UART_LCR_WLEN6;
2284                 break;
2285         case CS7:
2286                 cval = UART_LCR_WLEN7;
2287                 break;
2288         default:
2289         case CS8:
2290                 cval = UART_LCR_WLEN8;
2291                 break;
2292         }
2293 
2294         if (termios->c_cflag & CSTOPB)
2295                 cval |= UART_LCR_STOP;
2296         if (termios->c_cflag & PARENB) {
2297                 cval |= UART_LCR_PARITY;
2298                 if (up->bugs & UART_BUG_PARITY)
2299                         fifo_bug = 1;
2300         }
2301         if (!(termios->c_cflag & PARODD))
2302                 cval |= UART_LCR_EPAR;
2303 #ifdef CMSPAR
2304         if (termios->c_cflag & CMSPAR)
2305                 cval |= UART_LCR_SPAR;
2306 #endif
2307 
2308         /*
2309          * Ask the core to calculate the divisor for us.
2310          */
2311         baud = uart_get_baud_rate(port, termios, old,
2312                                   port->uartclk / 16 / 0xffff,
2313                                   port->uartclk / 16);
2314         quot = serial8250_get_divisor(port, baud);
2315 
2316         /*
2317          * Oxford Semi 952 rev B workaround
2318          */
2319         if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2320                 quot++;
2321 
2322         if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2323                 fcr = uart_config[port->type].fcr;
2324                 if ((baud < 2400 && !up->dma) || fifo_bug) {
2325                         fcr &= ~UART_FCR_TRIGGER_MASK;
2326                         fcr |= UART_FCR_TRIGGER_1;
2327                 }
2328         }
2329 
2330         /*
2331          * MCR-based auto flow control.  When AFE is enabled, RTS will be
2332          * deasserted when the receive FIFO contains more characters than
2333          * the trigger, or the MCR RTS bit is cleared.  In the case where
2334          * the remote UART is not using CTS auto flow control, we must
2335          * have sufficient FIFO entries for the latency of the remote
2336          * UART to respond.  IOW, at least 32 bytes of FIFO. Also enable
2337          * AFE if hw flow control is supported
2338          */
2339         if ((up->capabilities & UART_CAP_AFE && (port->fifosize >= 32)) ||
2340             (port->flags & UPF_HARD_FLOW)) {
2341                 up->mcr &= ~UART_MCR_AFE;
2342                 if (termios->c_cflag & CRTSCTS)
2343                         up->mcr |= UART_MCR_AFE;
2344         }
2345 
2346         /*
2347          * Ok, we're now changing the port state.  Do it with
2348          * interrupts disabled.
2349          */
2350         spin_lock_irqsave(&port->lock, flags);
2351 
2352         /*
2353          * Update the per-port timeout.
2354          */
2355         uart_update_timeout(port, termios->c_cflag, baud);
2356 
2357         port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2358         if (termios->c_iflag & INPCK)
2359                 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2360         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2361                 port->read_status_mask |= UART_LSR_BI;
2362 
2363         /*
2364          * Characteres to ignore
2365          */
2366         port->ignore_status_mask = 0;
2367         if (termios->c_iflag & IGNPAR)
2368                 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2369         if (termios->c_iflag & IGNBRK) {
2370                 port->ignore_status_mask |= UART_LSR_BI;
2371                 /*
2372                  * If we're ignoring parity and break indicators,
2373                  * ignore overruns too (for real raw support).
2374                  */
2375                 if (termios->c_iflag & IGNPAR)
2376                         port->ignore_status_mask |= UART_LSR_OE;
2377         }
2378 
2379         /*
2380          * ignore all characters if CREAD is not set
2381          */
2382         if ((termios->c_cflag & CREAD) == 0)
2383                 port->ignore_status_mask |= UART_LSR_DR;
2384 
2385         /*
2386          * CTS flow control flag and modem status interrupts
2387          */
2388         up->ier &= ~UART_IER_MSI;
2389         if (!(up->bugs & UART_BUG_NOMSR) &&
2390                         UART_ENABLE_MS(&up->port, termios->c_cflag))
2391                 up->ier |= UART_IER_MSI;
2392         if (up->capabilities & UART_CAP_UUE)
2393                 up->ier |= UART_IER_UUE;
2394         if (up->capabilities & UART_CAP_RTOIE)
2395                 up->ier |= UART_IER_RTOIE;
2396 
2397         serial_port_out(port, UART_IER, up->ier);
2398 
2399         if (up->capabilities & UART_CAP_EFR) {
2400                 unsigned char efr = 0;
2401                 /*
2402                  * TI16C752/Startech hardware flow control.  FIXME:
2403                  * - TI16C752 requires control thresholds to be set.
2404                  * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2405                  */
2406                 if (termios->c_cflag & CRTSCTS)
2407                         efr |= UART_EFR_CTS;
2408 
2409                 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2410                 if (port->flags & UPF_EXAR_EFR)
2411                         serial_port_out(port, UART_XR_EFR, efr);
2412                 else
2413                         serial_port_out(port, UART_EFR, efr);
2414         }
2415 
2416         /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2417         if (is_omap1510_8250(up)) {
2418                 if (baud == 115200) {
2419                         quot = 1;
2420                         serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2421                 } else
2422                         serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2423         }
2424 
2425         /*
2426          * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2427          * otherwise just set DLAB
2428          */
2429         if (up->capabilities & UART_NATSEMI)
2430                 serial_port_out(port, UART_LCR, 0xe0);
2431         else
2432                 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
2433 
2434         serial_dl_write(up, quot);
2435 
2436         /*
2437          * XR17V35x UARTs have an extra fractional divisor register (DLD)
2438          *
2439          * We need to recalculate all of the registers, because DLM and DLL
2440          * are already rounded to a whole integer.
2441          *
2442          * When recalculating we use a 32x clock instead of a 16x clock to
2443          * allow 1-bit for rounding in the fractional part.
2444          */
2445         if (up->port.type == PORT_XR17V35X) {
2446                 unsigned int baud_x32 = (port->uartclk * 2) / baud;
2447                 u16 quot = baud_x32 / 32;
2448                 u8 quot_frac = DIV_ROUND_CLOSEST(baud_x32 % 32, 2);
2449 
2450                 serial_dl_write(up, quot);
2451                 serial_port_out(port, 0x2, quot_frac & 0xf);
2452         }
2453 
2454         /*
2455          * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2456          * is written without DLAB set, this mode will be disabled.
2457          */
2458         if (port->type == PORT_16750)
2459                 serial_port_out(port, UART_FCR, fcr);
2460 
2461         serial_port_out(port, UART_LCR, cval);          /* reset DLAB */
2462         up->lcr = cval;                                 /* Save LCR */
2463         if (port->type != PORT_16750) {
2464                 /* emulated UARTs (Lucent Venus 167x) need two steps */
2465                 if (fcr & UART_FCR_ENABLE_FIFO)
2466                         serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2467                 serial_port_out(port, UART_FCR, fcr);           /* set fcr */
2468         }
2469         serial8250_set_mctrl(port, port->mctrl);
2470         spin_unlock_irqrestore(&port->lock, flags);
2471         /* Don't rewrite B0 */
2472         if (tty_termios_baud_rate(termios))
2473                 tty_termios_encode_baud_rate(termios, baud, baud);
2474 }
2475 EXPORT_SYMBOL(serial8250_do_set_termios);
2476 
2477 static void
2478 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2479                        struct ktermios *old)
2480 {
2481         if (port->set_termios)
2482                 port->set_termios(port, termios, old);
2483         else
2484                 serial8250_do_set_termios(port, termios, old);
2485 }
2486 
2487 static void
2488 serial8250_set_ldisc(struct uart_port *port, int new)
2489 {
2490         if (new == N_PPS) {
2491                 port->flags |= UPF_HARDPPS_CD;
2492                 serial8250_enable_ms(port);
2493         } else
2494                 port->flags &= ~UPF_HARDPPS_CD;
2495 }
2496 
2497 
2498 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2499                       unsigned int oldstate)
2500 {
2501         struct uart_8250_port *p =
2502                 container_of(port, struct uart_8250_port, port);
2503 
2504         serial8250_set_sleep(p, state != 0);
2505 }
2506 EXPORT_SYMBOL(serial8250_do_pm);
2507 
2508 static void
2509 serial8250_pm(struct uart_port *port, unsigned int state,
2510               unsigned int oldstate)
2511 {
2512         if (port->pm)
2513                 port->pm(port, state, oldstate);
2514         else
2515                 serial8250_do_pm(port, state, oldstate);
2516 }
2517 
2518 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2519 {
2520         if (pt->port.iotype == UPIO_AU)
2521                 return 0x1000;
2522         if (is_omap1_8250(pt))
2523                 return 0x16 << pt->port.regshift;
2524 
2525         return 8 << pt->port.regshift;
2526 }
2527 
2528 /*
2529  * Resource handling.
2530  */
2531 static int serial8250_request_std_resource(struct uart_8250_port *up)
2532 {
2533         unsigned int size = serial8250_port_size(up);
2534         struct uart_port *port = &up->port;
2535         int ret = 0;
2536 
2537         switch (port->iotype) {
2538         case UPIO_AU:
2539         case UPIO_TSI:
2540         case UPIO_MEM32:
2541         case UPIO_MEM:
2542                 if (!port->mapbase)
2543                         break;
2544 
2545                 if (!request_mem_region(port->mapbase, size, "serial")) {
2546                         ret = -EBUSY;
2547                         break;
2548                 }
2549 
2550                 if (port->flags & UPF_IOREMAP) {
2551                         port->membase = ioremap_nocache(port->mapbase, size);
2552                         if (!port->membase) {
2553                                 release_mem_region(port->mapbase, size);
2554                                 ret = -ENOMEM;
2555                         }
2556                 }
2557                 break;
2558 
2559         case UPIO_HUB6:
2560         case UPIO_PORT:
2561                 if (!request_region(port->iobase, size, "serial"))
2562                         ret = -EBUSY;
2563                 break;
2564         }
2565         return ret;
2566 }
2567 
2568 static void serial8250_release_std_resource(struct uart_8250_port *up)
2569 {
2570         unsigned int size = serial8250_port_size(up);
2571         struct uart_port *port = &up->port;
2572 
2573         switch (port->iotype) {
2574         case UPIO_AU:
2575         case UPIO_TSI:
2576         case UPIO_MEM32:
2577         case UPIO_MEM:
2578                 if (!port->mapbase)
2579                         break;
2580 
2581                 if (port->flags & UPF_IOREMAP) {
2582                         iounmap(port->membase);
2583                         port->membase = NULL;
2584                 }
2585 
2586                 release_mem_region(port->mapbase, size);
2587                 break;
2588 
2589         case UPIO_HUB6:
2590         case UPIO_PORT:
2591                 release_region(port->iobase, size);
2592                 break;
2593         }
2594 }
2595 
2596 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2597 {
2598         unsigned long start = UART_RSA_BASE << up->port.regshift;
2599         unsigned int size = 8 << up->port.regshift;
2600         struct uart_port *port = &up->port;
2601         int ret = -EINVAL;
2602 
2603         switch (port->iotype) {
2604         case UPIO_HUB6:
2605         case UPIO_PORT:
2606                 start += port->iobase;
2607                 if (request_region(start, size, "serial-rsa"))
2608                         ret = 0;
2609                 else
2610                         ret = -EBUSY;
2611                 break;
2612         }
2613 
2614         return ret;
2615 }
2616 
2617 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2618 {
2619         unsigned long offset = UART_RSA_BASE << up->port.regshift;
2620         unsigned int size = 8 << up->port.regshift;
2621         struct uart_port *port = &up->port;
2622 
2623         switch (port->iotype) {
2624         case UPIO_HUB6:
2625         case UPIO_PORT:
2626                 release_region(port->iobase + offset, size);
2627                 break;
2628         }
2629 }
2630 
2631 static void serial8250_release_port(struct uart_port *port)
2632 {
2633         struct uart_8250_port *up =
2634                 container_of(port, struct uart_8250_port, port);
2635 
2636         serial8250_release_std_resource(up);
2637         if (port->type == PORT_RSA)
2638                 serial8250_release_rsa_resource(up);
2639 }
2640 
2641 static int serial8250_request_port(struct uart_port *port)
2642 {
2643         struct uart_8250_port *up =
2644                 container_of(port, struct uart_8250_port, port);
2645         int ret;
2646 
2647         if (port->type == PORT_8250_CIR)
2648                 return -ENODEV;
2649 
2650         ret = serial8250_request_std_resource(up);
2651         if (ret == 0 && port->type == PORT_RSA) {
2652                 ret = serial8250_request_rsa_resource(up);
2653                 if (ret < 0)
2654                         serial8250_release_std_resource(up);
2655         }
2656 
2657         return ret;
2658 }
2659 
2660 static void serial8250_config_port(struct uart_port *port, int flags)
2661 {
2662         struct uart_8250_port *up =
2663                 container_of(port, struct uart_8250_port, port);
2664         int probeflags = PROBE_ANY;
2665         int ret;
2666 
2667         if (port->type == PORT_8250_CIR)
2668                 return;
2669 
2670         /*
2671          * Find the region that we can probe for.  This in turn
2672          * tells us whether we can probe for the type of port.
2673          */
2674         ret = serial8250_request_std_resource(up);
2675         if (ret < 0)
2676                 return;
2677 
2678         ret = serial8250_request_rsa_resource(up);
2679         if (ret < 0)
2680                 probeflags &= ~PROBE_RSA;
2681 
2682         if (port->iotype != up->cur_iotype)
2683                 set_io_from_upio(port);
2684 
2685         if (flags & UART_CONFIG_TYPE)
2686                 autoconfig(up, probeflags);
2687 
2688         /* if access method is AU, it is a 16550 with a quirk */
2689         if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2690                 up->bugs |= UART_BUG_NOMSR;
2691 
2692         /* HW bugs may trigger IRQ while IIR == NO_INT */
2693         if (port->type == PORT_TEGRA)
2694                 up->bugs |= UART_BUG_NOMSR;
2695 
2696         if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2697                 autoconfig_irq(up);
2698 
2699         if (port->type != PORT_RSA && probeflags & PROBE_RSA)
2700                 serial8250_release_rsa_resource(up);
2701         if (port->type == PORT_UNKNOWN)
2702                 serial8250_release_std_resource(up);
2703 
2704         /* Fixme: probably not the best place for this */
2705         if ((port->type == PORT_XR17V35X) ||
2706            (port->type == PORT_XR17D15X))
2707                 port->handle_irq = exar_handle_irq;
2708 }
2709 
2710 static int
2711 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2712 {
2713         if (ser->irq >= nr_irqs || ser->irq < 0 ||
2714             ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2715             ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2716             ser->type == PORT_STARTECH)
2717                 return -EINVAL;
2718         return 0;
2719 }
2720 
2721 static const char *
2722 serial8250_type(struct uart_port *port)
2723 {
2724         int type = port->type;
2725 
2726         if (type >= ARRAY_SIZE(uart_config))
2727                 type = 0;
2728         return uart_config[type].name;
2729 }
2730 
2731 static struct uart_ops serial8250_pops = {
2732         .tx_empty       = serial8250_tx_empty,
2733         .set_mctrl      = serial8250_set_mctrl,
2734         .get_mctrl      = serial8250_get_mctrl,
2735         .stop_tx        = serial8250_stop_tx,
2736         .start_tx       = serial8250_start_tx,
2737         .stop_rx        = serial8250_stop_rx,
2738         .enable_ms      = serial8250_enable_ms,
2739         .break_ctl      = serial8250_break_ctl,
2740         .startup        = serial8250_startup,
2741         .shutdown       = serial8250_shutdown,
2742         .set_termios    = serial8250_set_termios,
2743         .set_ldisc      = serial8250_set_ldisc,
2744         .pm             = serial8250_pm,
2745         .type           = serial8250_type,
2746         .release_port   = serial8250_release_port,
2747         .request_port   = serial8250_request_port,
2748         .config_port    = serial8250_config_port,
2749         .verify_port    = serial8250_verify_port,
2750 #ifdef CONFIG_CONSOLE_POLL
2751         .poll_get_char = serial8250_get_poll_char,
2752         .poll_put_char = serial8250_put_poll_char,
2753 #endif
2754 };
2755 
2756 static struct uart_8250_port serial8250_ports[UART_NR];
2757 
2758 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2759         unsigned short *capabilities);
2760 
2761 void serial8250_set_isa_configurator(
2762         void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2763 {
2764         serial8250_isa_config = v;
2765 }
2766 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2767 
2768 static void __init serial8250_isa_init_ports(void)
2769 {
2770         struct uart_8250_port *up;
2771         static int first = 1;
2772         int i, irqflag = 0;
2773 
2774         if (!first)
2775                 return;
2776         first = 0;
2777 
2778         if (nr_uarts > UART_NR)
2779                 nr_uarts = UART_NR;
2780 
2781         for (i = 0; i < nr_uarts; i++) {
2782                 struct uart_8250_port *up = &serial8250_ports[i];
2783                 struct uart_port *port = &up->port;
2784 
2785                 port->line = i;
2786                 spin_lock_init(&port->lock);
2787 
2788                 init_timer(&up->timer);
2789                 up->timer.function = serial8250_timeout;
2790                 up->cur_iotype = 0xFF;
2791 
2792                 /*
2793                  * ALPHA_KLUDGE_MCR needs to be killed.
2794                  */
2795                 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2796                 up->mcr_force = ALPHA_KLUDGE_MCR;
2797 
2798                 port->ops = &serial8250_pops;
2799         }
2800 
2801         if (share_irqs)
2802                 irqflag = IRQF_SHARED;
2803 
2804         for (i = 0, up = serial8250_ports;
2805              i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2806              i++, up++) {
2807                 struct uart_port *port = &up->port;
2808 
2809                 port->iobase   = old_serial_port[i].port;
2810                 port->irq      = irq_canonicalize(old_serial_port[i].irq);
2811                 port->irqflags = old_serial_port[i].irqflags;
2812                 port->uartclk  = old_serial_port[i].baud_base * 16;
2813                 port->flags    = old_serial_port[i].flags;
2814                 port->hub6     = old_serial_port[i].hub6;
2815                 port->membase  = old_serial_port[i].iomem_base;
2816                 port->iotype   = old_serial_port[i].io_type;
2817                 port->regshift = old_serial_port[i].iomem_reg_shift;
2818                 set_io_from_upio(port);
2819                 port->irqflags |= irqflag;
2820                 if (serial8250_isa_config != NULL)
2821                         serial8250_isa_config(i, &up->port, &up->capabilities);
2822 
2823         }
2824 }
2825 
2826 static void
2827 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2828 {
2829         up->port.type = type;
2830         if (!up->port.fifosize)
2831                 up->port.fifosize = uart_config[type].fifo_size;
2832         if (!up->tx_loadsz)
2833                 up->tx_loadsz = uart_config[type].tx_loadsz;
2834         if (!up->capabilities)
2835                 up->capabilities = uart_config[type].flags;
2836 }
2837 
2838 static void __init
2839 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2840 {
2841         int i;
2842 
2843         for (i = 0; i < nr_uarts; i++) {
2844                 struct uart_8250_port *up = &serial8250_ports[i];
2845 
2846                 if (up->port.dev)
2847                         continue;
2848 
2849                 up->port.dev = dev;
2850 
2851                 if (up->port.flags & UPF_FIXED_TYPE)
2852                         serial8250_init_fixed_type_port(up, up->port.type);
2853 
2854                 uart_add_one_port(drv, &up->port);
2855         }
2856 }
2857 
2858 #ifdef CONFIG_SERIAL_8250_CONSOLE
2859 
2860 static void serial8250_console_putchar(struct uart_port *port, int ch)
2861 {
2862         struct uart_8250_port *up =
2863                 container_of(port, struct uart_8250_port, port);
2864 
2865         wait_for_xmitr(up, UART_LSR_THRE);
2866         serial_port_out(port, UART_TX, ch);
2867 }
2868 
2869 /*
2870  *      Print a string to the serial port trying not to disturb
2871  *      any possible real use of the port...
2872  *
2873  *      The console_lock must be held when we get here.
2874  */
2875 static void
2876 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2877 {
2878         struct uart_8250_port *up = &serial8250_ports[co->index];
2879         struct uart_port *port = &up->port;
2880         unsigned long flags;
2881         unsigned int ier;
2882         int locked = 1;
2883 
2884         touch_nmi_watchdog();
2885 
2886         if (port->sysrq || oops_in_progress)
2887                 locked = spin_trylock_irqsave(&port->lock, flags);
2888         else
2889                 spin_lock_irqsave(&port->lock, flags);
2890 
2891         /*
2892          *      First save the IER then disable the interrupts
2893          */
2894         ier = serial_port_in(port, UART_IER);
2895 
2896         if (up->capabilities & UART_CAP_UUE)
2897                 serial_port_out(port, UART_IER, UART_IER_UUE);
2898         else
2899                 serial_port_out(port, UART_IER, 0);
2900 
2901         uart_console_write(port, s, count, serial8250_console_putchar);
2902 
2903         /*
2904          *      Finally, wait for transmitter to become empty
2905          *      and restore the IER
2906          */
2907         wait_for_xmitr(up, BOTH_EMPTY);
2908         serial_port_out(port, UART_IER, ier);
2909 
2910         /*
2911          *      The receive handling will happen properly because the
2912          *      receive ready bit will still be set; it is not cleared
2913          *      on read.  However, modem control will not, we must
2914          *      call it if we have saved something in the saved flags
2915          *      while processing with interrupts off.
2916          */
2917         if (up->msr_saved_flags)
2918                 serial8250_modem_status(up);
2919 
2920         if (locked)
2921                 spin_unlock_irqrestore(&port->lock, flags);
2922 }
2923 
2924 static int __init serial8250_console_setup(struct console *co, char *options)
2925 {
2926         struct uart_port *port;
2927         int baud = 9600;
2928         int bits = 8;
2929         int parity = 'n';
2930         int flow = 'n';
2931 
2932         /*
2933          * Check whether an invalid uart number has been specified, and
2934          * if so, search for the first available port that does have
2935          * console support.
2936          */
2937         if (co->index >= nr_uarts)
2938                 co->index = 0;
2939         port = &serial8250_ports[co->index].port;
2940         if (!port->iobase && !port->membase)
2941                 return -ENODEV;
2942 
2943         if (options)
2944                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2945 
2946         return uart_set_options(port, co, baud, parity, bits, flow);
2947 }
2948 
2949 static int serial8250_console_early_setup(void)
2950 {
2951         return serial8250_find_port_for_earlycon();
2952 }
2953 
2954 static struct console serial8250_console = {
2955         .name           = "ttyS",
2956         .write          = serial8250_console_write,
2957         .device         = uart_console_device,
2958         .setup          = serial8250_console_setup,
2959         .early_setup    = serial8250_console_early_setup,
2960         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
2961         .index          = -1,
2962         .data           = &serial8250_reg,
2963 };
2964 
2965 static int __init serial8250_console_init(void)
2966 {
2967         serial8250_isa_init_ports();
2968         register_console(&serial8250_console);
2969         return 0;
2970 }
2971 console_initcall(serial8250_console_init);
2972 
2973 int serial8250_find_port(struct uart_port *p)
2974 {
2975         int line;
2976         struct uart_port *port;
2977 
2978         for (line = 0; line < nr_uarts; line++) {
2979                 port = &serial8250_ports[line].port;
2980                 if (uart_match_port(p, port))
2981                         return line;
2982         }
2983         return -ENODEV;
2984 }
2985 
2986 #define SERIAL8250_CONSOLE      &serial8250_console
2987 #else
2988 #define SERIAL8250_CONSOLE      NULL
2989 #endif
2990 
2991 static struct uart_driver serial8250_reg = {
2992         .owner                  = THIS_MODULE,
2993         .driver_name            = "serial",
2994         .dev_name               = "ttyS",
2995         .major                  = TTY_MAJOR,
2996         .minor                  = 64,
2997         .cons                   = SERIAL8250_CONSOLE,
2998 };
2999 
3000 /*
3001  * early_serial_setup - early registration for 8250 ports
3002  *
3003  * Setup an 8250 port structure prior to console initialisation.  Use
3004  * after console initialisation will cause undefined behaviour.
3005  */
3006 int __init early_serial_setup(struct uart_port *port)
3007 {
3008         struct uart_port *p;
3009 
3010         if (port->line >= ARRAY_SIZE(serial8250_ports))
3011                 return -ENODEV;
3012 
3013         serial8250_isa_init_ports();
3014         p = &serial8250_ports[port->line].port;
3015         p->iobase       = port->iobase;
3016         p->membase      = port->membase;
3017         p->irq          = port->irq;
3018         p->irqflags     = port->irqflags;
3019         p->uartclk      = port->uartclk;
3020         p->fifosize     = port->fifosize;
3021         p->regshift     = port->regshift;
3022         p->iotype       = port->iotype;
3023         p->flags        = port->flags;
3024         p->mapbase      = port->mapbase;
3025         p->private_data = port->private_data;
3026         p->type         = port->type;
3027         p->line         = port->line;
3028 
3029         set_io_from_upio(p);
3030         if (port->serial_in)
3031                 p->serial_in = port->serial_in;
3032         if (port->serial_out)
3033                 p->serial_out = port->serial_out;
3034         if (port->handle_irq)
3035                 p->handle_irq = port->handle_irq;
3036         else
3037                 p->handle_irq = serial8250_default_handle_irq;
3038 
3039         return 0;
3040 }
3041 
3042 /**
3043  *      serial8250_suspend_port - suspend one serial port
3044  *      @line:  serial line number
3045  *
3046  *      Suspend one serial port.
3047  */
3048 void serial8250_suspend_port(int line)
3049 {
3050         uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3051 }
3052 
3053 /**
3054  *      serial8250_resume_port - resume one serial port
3055  *      @line:  serial line number
3056  *
3057  *      Resume one serial port.
3058  */
3059 void serial8250_resume_port(int line)
3060 {
3061         struct uart_8250_port *up = &serial8250_ports[line];
3062         struct uart_port *port = &up->port;
3063 
3064         if (up->capabilities & UART_NATSEMI) {
3065                 /* Ensure it's still in high speed mode */
3066                 serial_port_out(port, UART_LCR, 0xE0);
3067 
3068                 ns16550a_goto_highspeed(up);
3069 
3070                 serial_port_out(port, UART_LCR, 0);
3071                 port->uartclk = 921600*16;
3072         }
3073         uart_resume_port(&serial8250_reg, port);
3074 }
3075 
3076 /*
3077  * Register a set of serial devices attached to a platform device.  The
3078  * list is terminated with a zero flags entry, which means we expect
3079  * all entries to have at least UPF_BOOT_AUTOCONF set.
3080  */
3081 static int serial8250_probe(struct platform_device *dev)
3082 {
3083         struct plat_serial8250_port *p = dev_get_platdata(&dev->dev);
3084         struct uart_8250_port uart;
3085         int ret, i, irqflag = 0;
3086 
3087         memset(&uart, 0, sizeof(uart));
3088 
3089         if (share_irqs)
3090                 irqflag = IRQF_SHARED;
3091 
3092         for (i = 0; p && p->flags != 0; p++, i++) {
3093                 uart.port.iobase        = p->iobase;
3094                 uart.port.membase       = p->membase;
3095                 uart.port.irq           = p->irq;
3096                 uart.port.irqflags      = p->irqflags;
3097                 uart.port.uartclk       = p->uartclk;
3098                 uart.port.regshift      = p->regshift;
3099                 uart.port.iotype        = p->iotype;
3100                 uart.port.flags         = p->flags;
3101                 uart.port.mapbase       = p->mapbase;
3102                 uart.port.hub6          = p->hub6;
3103                 uart.port.private_data  = p->private_data;
3104                 uart.port.type          = p->type;
3105                 uart.port.serial_in     = p->serial_in;
3106                 uart.port.serial_out    = p->serial_out;
3107                 uart.port.handle_irq    = p->handle_irq;
3108                 uart.port.handle_break  = p->handle_break;
3109                 uart.port.set_termios   = p->set_termios;
3110                 uart.port.pm            = p->pm;
3111                 uart.port.dev           = &dev->dev;
3112                 uart.port.irqflags      |= irqflag;
3113                 ret = serial8250_register_8250_port(&uart);
3114                 if (ret < 0) {
3115                         dev_err(&dev->dev, "unable to register port at index %d "
3116                                 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3117                                 p->iobase, (unsigned long long)p->mapbase,
3118                                 p->irq, ret);
3119                 }
3120         }
3121         return 0;
3122 }
3123 
3124 /*
3125  * Remove serial ports registered against a platform device.
3126  */
3127 static int serial8250_remove(struct platform_device *dev)
3128 {
3129         int i;
3130 
3131         for (i = 0; i < nr_uarts; i++) {
3132                 struct uart_8250_port *up = &serial8250_ports[i];
3133 
3134                 if (up->port.dev == &dev->dev)
3135                         serial8250_unregister_port(i);
3136         }
3137         return 0;
3138 }
3139 
3140 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3141 {
3142         int i;
3143 
3144         for (i = 0; i < UART_NR; i++) {
3145                 struct uart_8250_port *up = &serial8250_ports[i];
3146 
3147                 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3148                         uart_suspend_port(&serial8250_reg, &up->port);
3149         }
3150 
3151         return 0;
3152 }
3153 
3154 static int serial8250_resume(struct platform_device *dev)
3155 {
3156         int i;
3157 
3158         for (i = 0; i < UART_NR; i++) {
3159                 struct uart_8250_port *up = &serial8250_ports[i];
3160 
3161                 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3162                         serial8250_resume_port(i);
3163         }
3164 
3165         return 0;
3166 }
3167 
3168 static struct platform_driver serial8250_isa_driver = {
3169         .probe          = serial8250_probe,
3170         .remove         = serial8250_remove,
3171         .suspend        = serial8250_suspend,
3172         .resume         = serial8250_resume,
3173         .driver         = {
3174                 .name   = "serial8250",
3175                 .owner  = THIS_MODULE,
3176         },
3177 };
3178 
3179 /*
3180  * This "device" covers _all_ ISA 8250-compatible serial devices listed
3181  * in the table in include/asm/serial.h
3182  */
3183 static struct platform_device *serial8250_isa_devs;
3184 
3185 /*
3186  * serial8250_register_8250_port and serial8250_unregister_port allows for
3187  * 16x50 serial ports to be configured at run-time, to support PCMCIA
3188  * modems and PCI multiport cards.
3189  */
3190 static DEFINE_MUTEX(serial_mutex);
3191 
3192 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3193 {
3194         int i;
3195 
3196         /*
3197          * First, find a port entry which matches.
3198          */
3199         for (i = 0; i < nr_uarts; i++)
3200                 if (uart_match_port(&serial8250_ports[i].port, port))
3201                         return &serial8250_ports[i];
3202 
3203         /*
3204          * We didn't find a matching entry, so look for the first
3205          * free entry.  We look for one which hasn't been previously
3206          * used (indicated by zero iobase).
3207          */
3208         for (i = 0; i < nr_uarts; i++)
3209                 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3210                     serial8250_ports[i].port.iobase == 0)
3211                         return &serial8250_ports[i];
3212 
3213         /*
3214          * That also failed.  Last resort is to find any entry which
3215          * doesn't have a real port associated with it.
3216          */
3217         for (i = 0; i < nr_uarts; i++)
3218                 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3219                         return &serial8250_ports[i];
3220 
3221         return NULL;
3222 }
3223 
3224 /**
3225  *      serial8250_register_8250_port - register a serial port
3226  *      @up: serial port template
3227  *
3228  *      Configure the serial port specified by the request. If the
3229  *      port exists and is in use, it is hung up and unregistered
3230  *      first.
3231  *
3232  *      The port is then probed and if necessary the IRQ is autodetected
3233  *      If this fails an error is returned.
3234  *
3235  *      On success the port is ready to use and the line number is returned.
3236  */
3237 int serial8250_register_8250_port(struct uart_8250_port *up)
3238 {
3239         struct uart_8250_port *uart;
3240         int ret = -ENOSPC;
3241 
3242         if (up->port.uartclk == 0)
3243                 return -EINVAL;
3244 
3245         mutex_lock(&serial_mutex);
3246 
3247         uart = serial8250_find_match_or_unused(&up->port);
3248         if (uart && uart->port.type != PORT_8250_CIR) {
3249                 if (uart->port.dev)
3250                         uart_remove_one_port(&serial8250_reg, &uart->port);
3251 
3252                 uart->port.iobase       = up->port.iobase;
3253                 uart->port.membase      = up->port.membase;
3254                 uart->port.irq          = up->port.irq;
3255                 uart->port.irqflags     = up->port.irqflags;
3256                 uart->port.uartclk      = up->port.uartclk;
3257                 uart->port.fifosize     = up->port.fifosize;
3258                 uart->port.regshift     = up->port.regshift;
3259                 uart->port.iotype       = up->port.iotype;
3260                 uart->port.flags        = up->port.flags | UPF_BOOT_AUTOCONF;
3261                 uart->bugs              = up->bugs;
3262                 uart->port.mapbase      = up->port.mapbase;
3263                 uart->port.private_data = up->port.private_data;
3264                 uart->port.fifosize     = up->port.fifosize;
3265                 uart->tx_loadsz         = up->tx_loadsz;
3266                 uart->capabilities      = up->capabilities;
3267 
3268                 /* Take tx_loadsz from fifosize if it wasn't set separately */
3269                 if (uart->port.fifosize && !uart->tx_loadsz)
3270                         uart->tx_loadsz = uart->port.fifosize;
3271 
3272                 if (up->port.dev)
3273                         uart->port.dev = up->port.dev;
3274 
3275                 if (up->port.flags & UPF_FIXED_TYPE)
3276                         serial8250_init_fixed_type_port(uart, up->port.type);
3277 
3278                 set_io_from_upio(&uart->port);
3279                 /* Possibly override default I/O functions.  */
3280                 if (up->port.serial_in)
3281                         uart->port.serial_in = up->port.serial_in;
3282                 if (up->port.serial_out)
3283                         uart->port.serial_out = up->port.serial_out;
3284                 if (up->port.handle_irq)
3285                         uart->port.handle_irq = up->port.handle_irq;
3286                 /*  Possibly override set_termios call */
3287                 if (up->port.set_termios)
3288                         uart->port.set_termios = up->port.set_termios;
3289                 if (up->port.pm)
3290                         uart->port.pm = up->port.pm;
3291                 if (up->port.handle_break)
3292                         uart->port.handle_break = up->port.handle_break;
3293                 if (up->dl_read)
3294                         uart->dl_read = up->dl_read;
3295                 if (up->dl_write)
3296                         uart->dl_write = up->dl_write;
3297                 if (up->dma)
3298                         uart->dma = up->dma;
3299 
3300                 if (serial8250_isa_config != NULL)
3301                         serial8250_isa_config(0, &uart->port,
3302                                         &uart->capabilities);
3303 
3304                 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3305                 if (ret == 0)
3306                         ret = uart->port.line;
3307         }
3308         mutex_unlock(&serial_mutex);
3309 
3310         return ret;
3311 }
3312 EXPORT_SYMBOL(serial8250_register_8250_port);
3313 
3314 /**
3315  *      serial8250_unregister_port - remove a 16x50 serial port at runtime
3316  *      @line: serial line number
3317  *
3318  *      Remove one serial port.  This may not be called from interrupt
3319  *      context.  We hand the port back to the our control.
3320  */
3321 void serial8250_unregister_port(int line)
3322 {
3323         struct uart_8250_port *uart = &serial8250_ports[line];
3324 
3325         mutex_lock(&serial_mutex);
3326         uart_remove_one_port(&serial8250_reg, &uart->port);
3327         if (serial8250_isa_devs) {
3328                 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3329                 uart->port.type = PORT_UNKNOWN;
3330                 uart->port.dev = &serial8250_isa_devs->dev;
3331                 uart->capabilities = uart_config[uart->port.type].flags;
3332                 uart_add_one_port(&serial8250_reg, &uart->port);
3333         } else {
3334                 uart->port.dev = NULL;
3335         }
3336         mutex_unlock(&serial_mutex);
3337 }
3338 EXPORT_SYMBOL(serial8250_unregister_port);
3339 
3340 static int __init serial8250_init(void)
3341 {
3342         int ret;
3343 
3344         serial8250_isa_init_ports();
3345 
3346         printk(KERN_INFO "Serial: 8250/16550 driver, "
3347                 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3348                 share_irqs ? "en" : "dis");
3349 
3350 #ifdef CONFIG_SPARC
3351         ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3352 #else
3353         serial8250_reg.nr = UART_NR;
3354         ret = uart_register_driver(&serial8250_reg);
3355 #endif
3356         if (ret)
3357                 goto out;
3358 
3359         ret = serial8250_pnp_init();
3360         if (ret)
3361                 goto unreg_uart_drv;
3362 
3363         serial8250_isa_devs = platform_device_alloc("serial8250",
3364                                                     PLAT8250_DEV_LEGACY);
3365         if (!serial8250_isa_devs) {
3366                 ret = -ENOMEM;
3367                 goto unreg_pnp;
3368         }
3369 
3370         ret = platform_device_add(serial8250_isa_devs);
3371         if (ret)
3372                 goto put_dev;
3373 
3374         serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3375 
3376         ret = platform_driver_register(&serial8250_isa_driver);
3377         if (ret == 0)
3378                 goto out;
3379 
3380         platform_device_del(serial8250_isa_devs);
3381 put_dev:
3382         platform_device_put(serial8250_isa_devs);
3383 unreg_pnp:
3384         serial8250_pnp_exit();
3385 unreg_uart_drv:
3386 #ifdef CONFIG_SPARC
3387         sunserial_unregister_minors(&serial8250_reg, UART_NR);
3388 #else
3389         uart_unregister_driver(&serial8250_reg);
3390 #endif
3391 out:
3392         return ret;
3393 }
3394 
3395 static void __exit serial8250_exit(void)
3396 {
3397         struct platform_device *isa_dev = serial8250_isa_devs;
3398 
3399         /*
3400          * This tells serial8250_unregister_port() not to re-register
3401          * the ports (thereby making serial8250_isa_driver permanently
3402          * in use.)
3403          */
3404         serial8250_isa_devs = NULL;
3405 
3406         platform_driver_unregister(&serial8250_isa_driver);
3407         platform_device_unregister(isa_dev);
3408 
3409         serial8250_pnp_exit();
3410 
3411 #ifdef CONFIG_SPARC
3412         sunserial_unregister_minors(&serial8250_reg, UART_NR);
3413 #else
3414         uart_unregister_driver(&serial8250_reg);
3415 #endif
3416 }
3417 
3418 module_init(serial8250_init);
3419 module_exit(serial8250_exit);
3420 
3421 EXPORT_SYMBOL(serial8250_suspend_port);
3422 EXPORT_SYMBOL(serial8250_resume_port);
3423 
3424 MODULE_LICENSE("GPL");
3425 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3426 
3427 module_param(share_irqs, uint, 0644);
3428 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3429         " (unsafe)");
3430 
3431 module_param(nr_uarts, uint, 0644);
3432 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3433 
3434 module_param(skip_txen_test, uint, 0644);
3435 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3436 
3437 #ifdef CONFIG_SERIAL_8250_RSA
3438 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3439 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3440 #endif
3441 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
3442 
3443 #ifdef CONFIG_SERIAL_8250_DEPRECATED_OPTIONS
3444 #ifndef MODULE
3445 /* This module was renamed to 8250_core in 3.7.  Keep the old "8250" name
3446  * working as well for the module options so we don't break people.  We
3447  * need to keep the names identical and the convenient macros will happily
3448  * refuse to let us do that by failing the build with redefinition errors
3449  * of global variables.  So we stick them inside a dummy function to avoid
3450  * those conflicts.  The options still get parsed, and the redefined
3451  * MODULE_PARAM_PREFIX lets us keep the "8250." syntax alive.
3452  *
3453  * This is hacky.  I'm sorry.
3454  */
3455 static void __used s8250_options(void)
3456 {
3457 #undef MODULE_PARAM_PREFIX
3458 #define MODULE_PARAM_PREFIX "8250_core."
3459 
3460         module_param_cb(share_irqs, &param_ops_uint, &share_irqs, 0644);
3461         module_param_cb(nr_uarts, &param_ops_uint, &nr_uarts, 0644);
3462         module_param_cb(skip_txen_test, &param_ops_uint, &skip_txen_test, 0644);
3463 #ifdef CONFIG_SERIAL_8250_RSA
3464         __module_param_call(MODULE_PARAM_PREFIX, probe_rsa,
3465                 &param_array_ops, .arr = &__param_arr_probe_rsa,
3466                 0444, -1);
3467 #endif
3468 }
3469 #else
3470 MODULE_ALIAS("8250_core");
3471 #endif
3472 #endif
3473 

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