Version:  2.0.40 2.2.26 2.4.37 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6

Linux/drivers/tty/rocket.c

  1 /*
  2  * RocketPort device driver for Linux
  3  *
  4  * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
  5  * 
  6  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
  7  * 
  8  * This program is free software; you can redistribute it and/or
  9  * modify it under the terms of the GNU General Public License as
 10  * published by the Free Software Foundation; either version 2 of the
 11  * License, or (at your option) any later version.
 12  * 
 13  * This program is distributed in the hope that it will be useful, but
 14  * WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 16  * General Public License for more details.
 17  * 
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program; if not, write to the Free Software
 20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 21  */
 22 
 23 /*
 24  * Kernel Synchronization:
 25  *
 26  * This driver has 2 kernel control paths - exception handlers (calls into the driver
 27  * from user mode) and the timer bottom half (tasklet).  This is a polled driver, interrupts
 28  * are not used.
 29  *
 30  * Critical data: 
 31  * -  rp_table[], accessed through passed "info" pointers, is a global (static) array of 
 32  *    serial port state information and the xmit_buf circular buffer.  Protected by 
 33  *    a per port spinlock.
 34  * -  xmit_flags[], an array of ints indexed by line (port) number, indicating that there
 35  *    is data to be transmitted.  Protected by atomic bit operations.
 36  * -  rp_num_ports, int indicating number of open ports, protected by atomic operations.
 37  * 
 38  * rp_write() and rp_write_char() functions use a per port semaphore to protect against
 39  * simultaneous access to the same port by more than one process.
 40  */
 41 
 42 /****** Defines ******/
 43 #define ROCKET_PARANOIA_CHECK
 44 #define ROCKET_DISABLE_SIMUSAGE
 45 
 46 #undef ROCKET_SOFT_FLOW
 47 #undef ROCKET_DEBUG_OPEN
 48 #undef ROCKET_DEBUG_INTR
 49 #undef ROCKET_DEBUG_WRITE
 50 #undef ROCKET_DEBUG_FLOW
 51 #undef ROCKET_DEBUG_THROTTLE
 52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
 53 #undef ROCKET_DEBUG_RECEIVE
 54 #undef ROCKET_DEBUG_HANGUP
 55 #undef REV_PCI_ORDER
 56 #undef ROCKET_DEBUG_IO
 57 
 58 #define POLL_PERIOD (HZ/100)    /*  Polling period .01 seconds (10ms) */
 59 
 60 /****** Kernel includes ******/
 61 
 62 #include <linux/module.h>
 63 #include <linux/errno.h>
 64 #include <linux/major.h>
 65 #include <linux/kernel.h>
 66 #include <linux/signal.h>
 67 #include <linux/slab.h>
 68 #include <linux/mm.h>
 69 #include <linux/sched.h>
 70 #include <linux/timer.h>
 71 #include <linux/interrupt.h>
 72 #include <linux/tty.h>
 73 #include <linux/tty_driver.h>
 74 #include <linux/tty_flip.h>
 75 #include <linux/serial.h>
 76 #include <linux/string.h>
 77 #include <linux/fcntl.h>
 78 #include <linux/ptrace.h>
 79 #include <linux/mutex.h>
 80 #include <linux/ioport.h>
 81 #include <linux/delay.h>
 82 #include <linux/completion.h>
 83 #include <linux/wait.h>
 84 #include <linux/pci.h>
 85 #include <linux/uaccess.h>
 86 #include <linux/atomic.h>
 87 #include <asm/unaligned.h>
 88 #include <linux/bitops.h>
 89 #include <linux/spinlock.h>
 90 #include <linux/init.h>
 91 
 92 /****** RocketPort includes ******/
 93 
 94 #include "rocket_int.h"
 95 #include "rocket.h"
 96 
 97 #define ROCKET_VERSION "2.09"
 98 #define ROCKET_DATE "12-June-2003"
 99 
100 /****** RocketPort Local Variables ******/
101 
102 static void rp_do_poll(unsigned long dummy);
103 
104 static struct tty_driver *rocket_driver;
105 
106 static struct rocket_version driver_version = { 
107         ROCKET_VERSION, ROCKET_DATE
108 };
109 
110 static struct r_port *rp_table[MAX_RP_PORTS];          /*  The main repository of serial port state information. */
111 static unsigned int xmit_flags[NUM_BOARDS];            /*  Bit significant, indicates port had data to transmit. */
112                                                        /*  eg.  Bit 0 indicates port 0 has xmit data, ...        */
113 static atomic_t rp_num_ports_open;                     /*  Number of serial ports open                           */
114 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
115 
116 static unsigned long board1;                           /* ISA addresses, retrieved from rocketport.conf          */
117 static unsigned long board2;
118 static unsigned long board3;
119 static unsigned long board4;
120 static unsigned long controller;
121 static bool support_low_speed;
122 static unsigned long modem1;
123 static unsigned long modem2;
124 static unsigned long modem3;
125 static unsigned long modem4;
126 static unsigned long pc104_1[8];
127 static unsigned long pc104_2[8];
128 static unsigned long pc104_3[8];
129 static unsigned long pc104_4[8];
130 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
131 
132 static int rp_baud_base[NUM_BOARDS];                   /*  Board config info (Someday make a per-board structure)  */
133 static unsigned long rcktpt_io_addr[NUM_BOARDS];
134 static int rcktpt_type[NUM_BOARDS];
135 static int is_PCI[NUM_BOARDS];
136 static rocketModel_t rocketModel[NUM_BOARDS];
137 static int max_board;
138 static const struct tty_port_operations rocket_port_ops;
139 
140 /*
141  * The following arrays define the interrupt bits corresponding to each AIOP.
142  * These bits are different between the ISA and regular PCI boards and the
143  * Universal PCI boards.
144  */
145 
146 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
147         AIOP_INTR_BIT_0,
148         AIOP_INTR_BIT_1,
149         AIOP_INTR_BIT_2,
150         AIOP_INTR_BIT_3
151 };
152 
153 #ifdef CONFIG_PCI
154 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
155         UPCI_AIOP_INTR_BIT_0,
156         UPCI_AIOP_INTR_BIT_1,
157         UPCI_AIOP_INTR_BIT_2,
158         UPCI_AIOP_INTR_BIT_3
159 };
160 #endif
161 
162 static Byte_t RData[RDATASIZE] = {
163         0x00, 0x09, 0xf6, 0x82,
164         0x02, 0x09, 0x86, 0xfb,
165         0x04, 0x09, 0x00, 0x0a,
166         0x06, 0x09, 0x01, 0x0a,
167         0x08, 0x09, 0x8a, 0x13,
168         0x0a, 0x09, 0xc5, 0x11,
169         0x0c, 0x09, 0x86, 0x85,
170         0x0e, 0x09, 0x20, 0x0a,
171         0x10, 0x09, 0x21, 0x0a,
172         0x12, 0x09, 0x41, 0xff,
173         0x14, 0x09, 0x82, 0x00,
174         0x16, 0x09, 0x82, 0x7b,
175         0x18, 0x09, 0x8a, 0x7d,
176         0x1a, 0x09, 0x88, 0x81,
177         0x1c, 0x09, 0x86, 0x7a,
178         0x1e, 0x09, 0x84, 0x81,
179         0x20, 0x09, 0x82, 0x7c,
180         0x22, 0x09, 0x0a, 0x0a
181 };
182 
183 static Byte_t RRegData[RREGDATASIZE] = {
184         0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
185         0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
186         0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
187         0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
188         0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
189         0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
190         0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
191         0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
192         0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
193         0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
194         0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
195         0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
196         0x22, 0x09, 0x0a, 0x0a  /* 30: Rx FIFO Enable */
197 };
198 
199 static CONTROLLER_T sController[CTL_SIZE] = {
200         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
206         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
207          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
208 };
209 
210 static Byte_t sBitMapClrTbl[8] = {
211         0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
212 };
213 
214 static Byte_t sBitMapSetTbl[8] = {
215         0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
216 };
217 
218 static int sClockPrescale = 0x14;
219 
220 /*
221  *  Line number is the ttySIx number (x), the Minor number.  We 
222  *  assign them sequentially, starting at zero.  The following 
223  *  array keeps track of the line number assigned to a given board/aiop/channel.
224  */
225 static unsigned char lineNumbers[MAX_RP_PORTS];
226 static unsigned long nextLineNumber;
227 
228 /*****  RocketPort Static Prototypes   *********/
229 static int __init init_ISA(int i);
230 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
231 static void rp_flush_buffer(struct tty_struct *tty);
232 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
233 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
234 static void rp_start(struct tty_struct *tty);
235 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
236                      int ChanNum);
237 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
238 static void sFlushRxFIFO(CHANNEL_T * ChP);
239 static void sFlushTxFIFO(CHANNEL_T * ChP);
240 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
241 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
242 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
243 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
244 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
245 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
246                            ByteIO_t * AiopIOList, int AiopIOListSize,
247                            int IRQNum, Byte_t Frequency, int PeriodicOnly);
248 static int sReadAiopID(ByteIO_t io);
249 static int sReadAiopNumChan(WordIO_t io);
250 
251 MODULE_AUTHOR("Theodore Ts'o");
252 MODULE_DESCRIPTION("Comtrol RocketPort driver");
253 module_param(board1, ulong, 0);
254 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
255 module_param(board2, ulong, 0);
256 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
257 module_param(board3, ulong, 0);
258 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
259 module_param(board4, ulong, 0);
260 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
261 module_param(controller, ulong, 0);
262 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
263 module_param(support_low_speed, bool, 0);
264 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
265 module_param(modem1, ulong, 0);
266 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
267 module_param(modem2, ulong, 0);
268 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
269 module_param(modem3, ulong, 0);
270 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
271 module_param(modem4, ulong, 0);
272 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
273 module_param_array(pc104_1, ulong, NULL, 0);
274 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
275 module_param_array(pc104_2, ulong, NULL, 0);
276 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
277 module_param_array(pc104_3, ulong, NULL, 0);
278 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
279 module_param_array(pc104_4, ulong, NULL, 0);
280 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
281 
282 static int rp_init(void);
283 static void rp_cleanup_module(void);
284 
285 module_init(rp_init);
286 module_exit(rp_cleanup_module);
287 
288 
289 MODULE_LICENSE("Dual BSD/GPL");
290 
291 /*************************************************************************/
292 /*                     Module code starts here                           */
293 
294 static inline int rocket_paranoia_check(struct r_port *info,
295                                         const char *routine)
296 {
297 #ifdef ROCKET_PARANOIA_CHECK
298         if (!info)
299                 return 1;
300         if (info->magic != RPORT_MAGIC) {
301                 printk(KERN_WARNING "Warning: bad magic number for rocketport "
302                                 "struct in %s\n", routine);
303                 return 1;
304         }
305 #endif
306         return 0;
307 }
308 
309 
310 /*  Serial port receive data function.  Called (from timer poll) when an AIOPIC signals 
311  *  that receive data is present on a serial port.  Pulls data from FIFO, moves it into the 
312  *  tty layer.  
313  */
314 static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
315                 unsigned int ChanStatus)
316 {
317         unsigned int CharNStat;
318         int ToRecv, wRecv, space;
319         unsigned char *cbuf;
320 
321         ToRecv = sGetRxCnt(cp);
322 #ifdef ROCKET_DEBUG_INTR
323         printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
324 #endif
325         if (ToRecv == 0)
326                 return;
327 
328         /*
329          * if status indicates there are errored characters in the
330          * FIFO, then enter status mode (a word in FIFO holds
331          * character and status).
332          */
333         if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
334                 if (!(ChanStatus & STATMODE)) {
335 #ifdef ROCKET_DEBUG_RECEIVE
336                         printk(KERN_INFO "Entering STATMODE...\n");
337 #endif
338                         ChanStatus |= STATMODE;
339                         sEnRxStatusMode(cp);
340                 }
341         }
342 
343         /* 
344          * if we previously entered status mode, then read down the
345          * FIFO one word at a time, pulling apart the character and
346          * the status.  Update error counters depending on status
347          */
348         if (ChanStatus & STATMODE) {
349 #ifdef ROCKET_DEBUG_RECEIVE
350                 printk(KERN_INFO "Ignore %x, read %x...\n",
351                         info->ignore_status_mask, info->read_status_mask);
352 #endif
353                 while (ToRecv) {
354                         char flag;
355 
356                         CharNStat = sInW(sGetTxRxDataIO(cp));
357 #ifdef ROCKET_DEBUG_RECEIVE
358                         printk(KERN_INFO "%x...\n", CharNStat);
359 #endif
360                         if (CharNStat & STMBREAKH)
361                                 CharNStat &= ~(STMFRAMEH | STMPARITYH);
362                         if (CharNStat & info->ignore_status_mask) {
363                                 ToRecv--;
364                                 continue;
365                         }
366                         CharNStat &= info->read_status_mask;
367                         if (CharNStat & STMBREAKH)
368                                 flag = TTY_BREAK;
369                         else if (CharNStat & STMPARITYH)
370                                 flag = TTY_PARITY;
371                         else if (CharNStat & STMFRAMEH)
372                                 flag = TTY_FRAME;
373                         else if (CharNStat & STMRCVROVRH)
374                                 flag = TTY_OVERRUN;
375                         else
376                                 flag = TTY_NORMAL;
377                         tty_insert_flip_char(&info->port, CharNStat & 0xff,
378                                         flag);
379                         ToRecv--;
380                 }
381 
382                 /*
383                  * after we've emptied the FIFO in status mode, turn
384                  * status mode back off
385                  */
386                 if (sGetRxCnt(cp) == 0) {
387 #ifdef ROCKET_DEBUG_RECEIVE
388                         printk(KERN_INFO "Status mode off.\n");
389 #endif
390                         sDisRxStatusMode(cp);
391                 }
392         } else {
393                 /*
394                  * we aren't in status mode, so read down the FIFO two
395                  * characters at time by doing repeated word IO
396                  * transfer.
397                  */
398                 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
399                 if (space < ToRecv) {
400 #ifdef ROCKET_DEBUG_RECEIVE
401                         printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
402 #endif
403                         if (space <= 0)
404                                 return;
405                         ToRecv = space;
406                 }
407                 wRecv = ToRecv >> 1;
408                 if (wRecv)
409                         sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
410                 if (ToRecv & 1)
411                         cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
412         }
413         /*  Push the data up to the tty layer */
414         tty_flip_buffer_push(&info->port);
415 }
416 
417 /*
418  *  Serial port transmit data function.  Called from the timer polling loop as a 
419  *  result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
420  *  to be sent out the serial port.  Data is buffered in rp_table[line].xmit_buf, it is 
421  *  moved to the port's xmit FIFO.  *info is critical data, protected by spinlocks.
422  */
423 static void rp_do_transmit(struct r_port *info)
424 {
425         int c;
426         CHANNEL_t *cp = &info->channel;
427         struct tty_struct *tty;
428         unsigned long flags;
429 
430 #ifdef ROCKET_DEBUG_INTR
431         printk(KERN_DEBUG "%s\n", __func__);
432 #endif
433         if (!info)
434                 return;
435         tty = tty_port_tty_get(&info->port);
436 
437         if (tty == NULL) {
438                 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
439                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
440                 return;
441         }
442 
443         spin_lock_irqsave(&info->slock, flags);
444         info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
445 
446         /*  Loop sending data to FIFO until done or FIFO full */
447         while (1) {
448                 if (tty->stopped)
449                         break;
450                 c = min(info->xmit_fifo_room, info->xmit_cnt);
451                 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
452                 if (c <= 0 || info->xmit_fifo_room <= 0)
453                         break;
454                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
455                 if (c & 1)
456                         sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
457                 info->xmit_tail += c;
458                 info->xmit_tail &= XMIT_BUF_SIZE - 1;
459                 info->xmit_cnt -= c;
460                 info->xmit_fifo_room -= c;
461 #ifdef ROCKET_DEBUG_INTR
462                 printk(KERN_INFO "tx %d chars...\n", c);
463 #endif
464         }
465 
466         if (info->xmit_cnt == 0)
467                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
468 
469         if (info->xmit_cnt < WAKEUP_CHARS) {
470                 tty_wakeup(tty);
471 #ifdef ROCKETPORT_HAVE_POLL_WAIT
472                 wake_up_interruptible(&tty->poll_wait);
473 #endif
474         }
475 
476         spin_unlock_irqrestore(&info->slock, flags);
477         tty_kref_put(tty);
478 
479 #ifdef ROCKET_DEBUG_INTR
480         printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
481                info->xmit_tail, info->xmit_fifo_room);
482 #endif
483 }
484 
485 /*
486  *  Called when a serial port signals it has read data in it's RX FIFO.
487  *  It checks what interrupts are pending and services them, including
488  *  receiving serial data.  
489  */
490 static void rp_handle_port(struct r_port *info)
491 {
492         CHANNEL_t *cp;
493         unsigned int IntMask, ChanStatus;
494 
495         if (!info)
496                 return;
497 
498         if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
499                 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
500                                 "info->flags & NOT_INIT\n");
501                 return;
502         }
503 
504         cp = &info->channel;
505 
506         IntMask = sGetChanIntID(cp) & info->intmask;
507 #ifdef ROCKET_DEBUG_INTR
508         printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
509 #endif
510         ChanStatus = sGetChanStatus(cp);
511         if (IntMask & RXF_TRIG) {       /* Rx FIFO trigger level */
512                 rp_do_receive(info, cp, ChanStatus);
513         }
514         if (IntMask & DELTA_CD) {       /* CD change  */
515 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
516                 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
517                        (ChanStatus & CD_ACT) ? "on" : "off");
518 #endif
519                 if (!(ChanStatus & CD_ACT) && info->cd_status) {
520 #ifdef ROCKET_DEBUG_HANGUP
521                         printk(KERN_INFO "CD drop, calling hangup.\n");
522 #endif
523                         tty_port_tty_hangup(&info->port, false);
524                 }
525                 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
526                 wake_up_interruptible(&info->port.open_wait);
527         }
528 #ifdef ROCKET_DEBUG_INTR
529         if (IntMask & DELTA_CTS) {      /* CTS change */
530                 printk(KERN_INFO "CTS change...\n");
531         }
532         if (IntMask & DELTA_DSR) {      /* DSR change */
533                 printk(KERN_INFO "DSR change...\n");
534         }
535 #endif
536 }
537 
538 /*
539  *  The top level polling routine.  Repeats every 1/100 HZ (10ms).
540  */
541 static void rp_do_poll(unsigned long dummy)
542 {
543         CONTROLLER_t *ctlp;
544         int ctrl, aiop, ch, line;
545         unsigned int xmitmask, i;
546         unsigned int CtlMask;
547         unsigned char AiopMask;
548         Word_t bit;
549 
550         /*  Walk through all the boards (ctrl's) */
551         for (ctrl = 0; ctrl < max_board; ctrl++) {
552                 if (rcktpt_io_addr[ctrl] <= 0)
553                         continue;
554 
555                 /*  Get a ptr to the board's control struct */
556                 ctlp = sCtlNumToCtlPtr(ctrl);
557 
558                 /*  Get the interrupt status from the board */
559 #ifdef CONFIG_PCI
560                 if (ctlp->BusType == isPCI)
561                         CtlMask = sPCIGetControllerIntStatus(ctlp);
562                 else
563 #endif
564                         CtlMask = sGetControllerIntStatus(ctlp);
565 
566                 /*  Check if any AIOP read bits are set */
567                 for (aiop = 0; CtlMask; aiop++) {
568                         bit = ctlp->AiopIntrBits[aiop];
569                         if (CtlMask & bit) {
570                                 CtlMask &= ~bit;
571                                 AiopMask = sGetAiopIntStatus(ctlp, aiop);
572 
573                                 /*  Check if any port read bits are set */
574                                 for (ch = 0; AiopMask;  AiopMask >>= 1, ch++) {
575                                         if (AiopMask & 1) {
576 
577                                                 /*  Get the line number (/dev/ttyRx number). */
578                                                 /*  Read the data from the port. */
579                                                 line = GetLineNumber(ctrl, aiop, ch);
580                                                 rp_handle_port(rp_table[line]);
581                                         }
582                                 }
583                         }
584                 }
585 
586                 xmitmask = xmit_flags[ctrl];
587 
588                 /*
589                  *  xmit_flags contains bit-significant flags, indicating there is data
590                  *  to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port 
591                  *  1, ... (32 total possible).  The variable i has the aiop and ch 
592                  *  numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
593                  */
594                 if (xmitmask) {
595                         for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
596                                 if (xmitmask & (1 << i)) {
597                                         aiop = (i & 0x18) >> 3;
598                                         ch = i & 0x07;
599                                         line = GetLineNumber(ctrl, aiop, ch);
600                                         rp_do_transmit(rp_table[line]);
601                                 }
602                         }
603                 }
604         }
605 
606         /*
607          * Reset the timer so we get called at the next clock tick (10ms).
608          */
609         if (atomic_read(&rp_num_ports_open))
610                 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
611 }
612 
613 /*
614  *  Initializes the r_port structure for a port, as well as enabling the port on 
615  *  the board.  
616  *  Inputs:  board, aiop, chan numbers
617  */
618 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
619 {
620         unsigned rocketMode;
621         struct r_port *info;
622         int line;
623         CONTROLLER_T *ctlp;
624 
625         /*  Get the next available line number */
626         line = SetLineNumber(board, aiop, chan);
627 
628         ctlp = sCtlNumToCtlPtr(board);
629 
630         /*  Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
631         info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
632         if (!info) {
633                 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
634                                 line);
635                 return;
636         }
637 
638         info->magic = RPORT_MAGIC;
639         info->line = line;
640         info->ctlp = ctlp;
641         info->board = board;
642         info->aiop = aiop;
643         info->chan = chan;
644         tty_port_init(&info->port);
645         info->port.ops = &rocket_port_ops;
646         info->flags &= ~ROCKET_MODE_MASK;
647         switch (pc104[board][line]) {
648         case 422:
649                 info->flags |= ROCKET_MODE_RS422;
650                 break;
651         case 485:
652                 info->flags |= ROCKET_MODE_RS485;
653                 break;
654         case 232:
655         default:
656                 info->flags |= ROCKET_MODE_RS232;
657                 break;
658         }
659 
660         info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
661         if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
662                 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
663                                 board, aiop, chan);
664                 tty_port_destroy(&info->port);
665                 kfree(info);
666                 return;
667         }
668 
669         rocketMode = info->flags & ROCKET_MODE_MASK;
670 
671         if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
672                 sEnRTSToggle(&info->channel);
673         else
674                 sDisRTSToggle(&info->channel);
675 
676         if (ctlp->boardType == ROCKET_TYPE_PC104) {
677                 switch (rocketMode) {
678                 case ROCKET_MODE_RS485:
679                         sSetInterfaceMode(&info->channel, InterfaceModeRS485);
680                         break;
681                 case ROCKET_MODE_RS422:
682                         sSetInterfaceMode(&info->channel, InterfaceModeRS422);
683                         break;
684                 case ROCKET_MODE_RS232:
685                 default:
686                         if (info->flags & ROCKET_RTS_TOGGLE)
687                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
688                         else
689                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
690                         break;
691                 }
692         }
693         spin_lock_init(&info->slock);
694         mutex_init(&info->write_mtx);
695         rp_table[line] = info;
696         tty_port_register_device(&info->port, rocket_driver, line,
697                         pci_dev ? &pci_dev->dev : NULL);
698 }
699 
700 /*
701  *  Configures a rocketport port according to its termio settings.  Called from 
702  *  user mode into the driver (exception handler).  *info CD manipulation is spinlock protected.
703  */
704 static void configure_r_port(struct tty_struct *tty, struct r_port *info,
705                              struct ktermios *old_termios)
706 {
707         unsigned cflag;
708         unsigned long flags;
709         unsigned rocketMode;
710         int bits, baud, divisor;
711         CHANNEL_t *cp;
712         struct ktermios *t = &tty->termios;
713 
714         cp = &info->channel;
715         cflag = t->c_cflag;
716 
717         /* Byte size and parity */
718         if ((cflag & CSIZE) == CS8) {
719                 sSetData8(cp);
720                 bits = 10;
721         } else {
722                 sSetData7(cp);
723                 bits = 9;
724         }
725         if (cflag & CSTOPB) {
726                 sSetStop2(cp);
727                 bits++;
728         } else {
729                 sSetStop1(cp);
730         }
731 
732         if (cflag & PARENB) {
733                 sEnParity(cp);
734                 bits++;
735                 if (cflag & PARODD) {
736                         sSetOddParity(cp);
737                 } else {
738                         sSetEvenParity(cp);
739                 }
740         } else {
741                 sDisParity(cp);
742         }
743 
744         /* baud rate */
745         baud = tty_get_baud_rate(tty);
746         if (!baud)
747                 baud = 9600;
748         divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
749         if ((divisor >= 8192 || divisor < 0) && old_termios) {
750                 baud = tty_termios_baud_rate(old_termios);
751                 if (!baud)
752                         baud = 9600;
753                 divisor = (rp_baud_base[info->board] / baud) - 1;
754         }
755         if (divisor >= 8192 || divisor < 0) {
756                 baud = 9600;
757                 divisor = (rp_baud_base[info->board] / baud) - 1;
758         }
759         info->cps = baud / bits;
760         sSetBaud(cp, divisor);
761 
762         /* FIXME: Should really back compute a baud rate from the divisor */
763         tty_encode_baud_rate(tty, baud, baud);
764 
765         if (cflag & CRTSCTS) {
766                 info->intmask |= DELTA_CTS;
767                 sEnCTSFlowCtl(cp);
768         } else {
769                 info->intmask &= ~DELTA_CTS;
770                 sDisCTSFlowCtl(cp);
771         }
772         if (cflag & CLOCAL) {
773                 info->intmask &= ~DELTA_CD;
774         } else {
775                 spin_lock_irqsave(&info->slock, flags);
776                 if (sGetChanStatus(cp) & CD_ACT)
777                         info->cd_status = 1;
778                 else
779                         info->cd_status = 0;
780                 info->intmask |= DELTA_CD;
781                 spin_unlock_irqrestore(&info->slock, flags);
782         }
783 
784         /*
785          * Handle software flow control in the board
786          */
787 #ifdef ROCKET_SOFT_FLOW
788         if (I_IXON(tty)) {
789                 sEnTxSoftFlowCtl(cp);
790                 if (I_IXANY(tty)) {
791                         sEnIXANY(cp);
792                 } else {
793                         sDisIXANY(cp);
794                 }
795                 sSetTxXONChar(cp, START_CHAR(tty));
796                 sSetTxXOFFChar(cp, STOP_CHAR(tty));
797         } else {
798                 sDisTxSoftFlowCtl(cp);
799                 sDisIXANY(cp);
800                 sClrTxXOFF(cp);
801         }
802 #endif
803 
804         /*
805          * Set up ignore/read mask words
806          */
807         info->read_status_mask = STMRCVROVRH | 0xFF;
808         if (I_INPCK(tty))
809                 info->read_status_mask |= STMFRAMEH | STMPARITYH;
810         if (I_BRKINT(tty) || I_PARMRK(tty))
811                 info->read_status_mask |= STMBREAKH;
812 
813         /*
814          * Characters to ignore
815          */
816         info->ignore_status_mask = 0;
817         if (I_IGNPAR(tty))
818                 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
819         if (I_IGNBRK(tty)) {
820                 info->ignore_status_mask |= STMBREAKH;
821                 /*
822                  * If we're ignoring parity and break indicators,
823                  * ignore overruns too.  (For real raw support).
824                  */
825                 if (I_IGNPAR(tty))
826                         info->ignore_status_mask |= STMRCVROVRH;
827         }
828 
829         rocketMode = info->flags & ROCKET_MODE_MASK;
830 
831         if ((info->flags & ROCKET_RTS_TOGGLE)
832             || (rocketMode == ROCKET_MODE_RS485))
833                 sEnRTSToggle(cp);
834         else
835                 sDisRTSToggle(cp);
836 
837         sSetRTS(&info->channel);
838 
839         if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
840                 switch (rocketMode) {
841                 case ROCKET_MODE_RS485:
842                         sSetInterfaceMode(cp, InterfaceModeRS485);
843                         break;
844                 case ROCKET_MODE_RS422:
845                         sSetInterfaceMode(cp, InterfaceModeRS422);
846                         break;
847                 case ROCKET_MODE_RS232:
848                 default:
849                         if (info->flags & ROCKET_RTS_TOGGLE)
850                                 sSetInterfaceMode(cp, InterfaceModeRS232T);
851                         else
852                                 sSetInterfaceMode(cp, InterfaceModeRS232);
853                         break;
854                 }
855         }
856 }
857 
858 static int carrier_raised(struct tty_port *port)
859 {
860         struct r_port *info = container_of(port, struct r_port, port);
861         return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
862 }
863 
864 static void dtr_rts(struct tty_port *port, int on)
865 {
866         struct r_port *info = container_of(port, struct r_port, port);
867         if (on) {
868                 sSetDTR(&info->channel);
869                 sSetRTS(&info->channel);
870         } else {
871                 sClrDTR(&info->channel);
872                 sClrRTS(&info->channel);
873         }
874 }
875 
876 /*
877  *  Exception handler that opens a serial port.  Creates xmit_buf storage, fills in 
878  *  port's r_port struct.  Initializes the port hardware.  
879  */
880 static int rp_open(struct tty_struct *tty, struct file *filp)
881 {
882         struct r_port *info;
883         struct tty_port *port;
884         int retval;
885         CHANNEL_t *cp;
886         unsigned long page;
887 
888         info = rp_table[tty->index];
889         if (info == NULL)
890                 return -ENXIO;
891         port = &info->port;
892         
893         page = __get_free_page(GFP_KERNEL);
894         if (!page)
895                 return -ENOMEM;
896 
897         /*
898          * We must not sleep from here until the port is marked fully in use.
899          */
900         if (info->xmit_buf)
901                 free_page(page);
902         else
903                 info->xmit_buf = (unsigned char *) page;
904 
905         tty->driver_data = info;
906         tty_port_tty_set(port, tty);
907 
908         if (port->count++ == 0) {
909                 atomic_inc(&rp_num_ports_open);
910 
911 #ifdef ROCKET_DEBUG_OPEN
912                 printk(KERN_INFO "rocket mod++ = %d...\n",
913                                 atomic_read(&rp_num_ports_open));
914 #endif
915         }
916 #ifdef ROCKET_DEBUG_OPEN
917         printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
918 #endif
919 
920         /*
921          * Info->count is now 1; so it's safe to sleep now.
922          */
923         if (!test_bit(ASYNCB_INITIALIZED, &port->flags)) {
924                 cp = &info->channel;
925                 sSetRxTrigger(cp, TRIG_1);
926                 if (sGetChanStatus(cp) & CD_ACT)
927                         info->cd_status = 1;
928                 else
929                         info->cd_status = 0;
930                 sDisRxStatusMode(cp);
931                 sFlushRxFIFO(cp);
932                 sFlushTxFIFO(cp);
933 
934                 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
935                 sSetRxTrigger(cp, TRIG_1);
936 
937                 sGetChanStatus(cp);
938                 sDisRxStatusMode(cp);
939                 sClrTxXOFF(cp);
940 
941                 sDisCTSFlowCtl(cp);
942                 sDisTxSoftFlowCtl(cp);
943 
944                 sEnRxFIFO(cp);
945                 sEnTransmit(cp);
946 
947                 set_bit(ASYNCB_INITIALIZED, &info->port.flags);
948 
949                 /*
950                  * Set up the tty->alt_speed kludge
951                  */
952                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
953                         tty->alt_speed = 57600;
954                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
955                         tty->alt_speed = 115200;
956                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
957                         tty->alt_speed = 230400;
958                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
959                         tty->alt_speed = 460800;
960 
961                 configure_r_port(tty, info, NULL);
962                 if (C_BAUD(tty)) {
963                         sSetDTR(cp);
964                         sSetRTS(cp);
965                 }
966         }
967         /*  Starts (or resets) the maint polling loop */
968         mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
969 
970         retval = tty_port_block_til_ready(port, tty, filp);
971         if (retval) {
972 #ifdef ROCKET_DEBUG_OPEN
973                 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
974 #endif
975                 return retval;
976         }
977         return 0;
978 }
979 
980 /*
981  *  Exception handler that closes a serial port. info->port.count is considered critical.
982  */
983 static void rp_close(struct tty_struct *tty, struct file *filp)
984 {
985         struct r_port *info = tty->driver_data;
986         struct tty_port *port = &info->port;
987         int timeout;
988         CHANNEL_t *cp;
989         
990         if (rocket_paranoia_check(info, "rp_close"))
991                 return;
992 
993 #ifdef ROCKET_DEBUG_OPEN
994         printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
995 #endif
996 
997         if (tty_port_close_start(port, tty, filp) == 0)
998                 return;
999 
1000         mutex_lock(&port->mutex);
1001         cp = &info->channel;
1002         /*
1003          * Before we drop DTR, make sure the UART transmitter
1004          * has completely drained; this is especially
1005          * important if there is a transmit FIFO!
1006          */
1007         timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1008         if (timeout == 0)
1009                 timeout = 1;
1010         rp_wait_until_sent(tty, timeout);
1011         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1012 
1013         sDisTransmit(cp);
1014         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1015         sDisCTSFlowCtl(cp);
1016         sDisTxSoftFlowCtl(cp);
1017         sClrTxXOFF(cp);
1018         sFlushRxFIFO(cp);
1019         sFlushTxFIFO(cp);
1020         sClrRTS(cp);
1021         if (C_HUPCL(tty))
1022                 sClrDTR(cp);
1023 
1024         rp_flush_buffer(tty);
1025                 
1026         tty_ldisc_flush(tty);
1027 
1028         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1029 
1030         /* We can't yet use tty_port_close_end as the buffer handling in this
1031            driver is a bit different to the usual */
1032 
1033         if (port->blocked_open) {
1034                 if (port->close_delay) {
1035                         msleep_interruptible(jiffies_to_msecs(port->close_delay));
1036                 }
1037                 wake_up_interruptible(&port->open_wait);
1038         } else {
1039                 if (info->xmit_buf) {
1040                         free_page((unsigned long) info->xmit_buf);
1041                         info->xmit_buf = NULL;
1042                 }
1043         }
1044         spin_lock_irq(&port->lock);
1045         info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_NORMAL_ACTIVE);
1046         tty->closing = 0;
1047         spin_unlock_irq(&port->lock);
1048         mutex_unlock(&port->mutex);
1049         tty_port_tty_set(port, NULL);
1050 
1051         atomic_dec(&rp_num_ports_open);
1052 
1053 #ifdef ROCKET_DEBUG_OPEN
1054         printk(KERN_INFO "rocket mod-- = %d...\n",
1055                         atomic_read(&rp_num_ports_open));
1056         printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1057 #endif
1058 
1059 }
1060 
1061 static void rp_set_termios(struct tty_struct *tty,
1062                            struct ktermios *old_termios)
1063 {
1064         struct r_port *info = tty->driver_data;
1065         CHANNEL_t *cp;
1066         unsigned cflag;
1067 
1068         if (rocket_paranoia_check(info, "rp_set_termios"))
1069                 return;
1070 
1071         cflag = tty->termios.c_cflag;
1072 
1073         /*
1074          * This driver doesn't support CS5 or CS6
1075          */
1076         if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1077                 tty->termios.c_cflag =
1078                     ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1079         /* Or CMSPAR */
1080         tty->termios.c_cflag &= ~CMSPAR;
1081 
1082         configure_r_port(tty, info, old_termios);
1083 
1084         cp = &info->channel;
1085 
1086         /* Handle transition to B0 status */
1087         if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
1088                 sClrDTR(cp);
1089                 sClrRTS(cp);
1090         }
1091 
1092         /* Handle transition away from B0 status */
1093         if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
1094                 sSetRTS(cp);
1095                 sSetDTR(cp);
1096         }
1097 
1098         if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty))
1099                 rp_start(tty);
1100 }
1101 
1102 static int rp_break(struct tty_struct *tty, int break_state)
1103 {
1104         struct r_port *info = tty->driver_data;
1105         unsigned long flags;
1106 
1107         if (rocket_paranoia_check(info, "rp_break"))
1108                 return -EINVAL;
1109 
1110         spin_lock_irqsave(&info->slock, flags);
1111         if (break_state == -1)
1112                 sSendBreak(&info->channel);
1113         else
1114                 sClrBreak(&info->channel);
1115         spin_unlock_irqrestore(&info->slock, flags);
1116         return 0;
1117 }
1118 
1119 /*
1120  * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1121  * the UPCI boards was added, it was decided to make this a function because
1122  * the macro was getting too complicated. All cases except the first one
1123  * (UPCIRingInd) are taken directly from the original macro.
1124  */
1125 static int sGetChanRI(CHANNEL_T * ChP)
1126 {
1127         CONTROLLER_t *CtlP = ChP->CtlP;
1128         int ChanNum = ChP->ChanNum;
1129         int RingInd = 0;
1130 
1131         if (CtlP->UPCIRingInd)
1132                 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1133         else if (CtlP->AltChanRingIndicator)
1134                 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1135         else if (CtlP->boardType == ROCKET_TYPE_PC104)
1136                 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1137 
1138         return RingInd;
1139 }
1140 
1141 /********************************************************************************************/
1142 /*  Here are the routines used by rp_ioctl.  These are all called from exception handlers.  */
1143 
1144 /*
1145  *  Returns the state of the serial modem control lines.  These next 2 functions 
1146  *  are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1147  */
1148 static int rp_tiocmget(struct tty_struct *tty)
1149 {
1150         struct r_port *info = tty->driver_data;
1151         unsigned int control, result, ChanStatus;
1152 
1153         ChanStatus = sGetChanStatusLo(&info->channel);
1154         control = info->channel.TxControl[3];
1155         result = ((control & SET_RTS) ? TIOCM_RTS : 0) | 
1156                 ((control & SET_DTR) ?  TIOCM_DTR : 0) |
1157                 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1158                 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1159                 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1160                 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1161 
1162         return result;
1163 }
1164 
1165 /* 
1166  *  Sets the modem control lines
1167  */
1168 static int rp_tiocmset(struct tty_struct *tty,
1169                                 unsigned int set, unsigned int clear)
1170 {
1171         struct r_port *info = tty->driver_data;
1172 
1173         if (set & TIOCM_RTS)
1174                 info->channel.TxControl[3] |= SET_RTS;
1175         if (set & TIOCM_DTR)
1176                 info->channel.TxControl[3] |= SET_DTR;
1177         if (clear & TIOCM_RTS)
1178                 info->channel.TxControl[3] &= ~SET_RTS;
1179         if (clear & TIOCM_DTR)
1180                 info->channel.TxControl[3] &= ~SET_DTR;
1181 
1182         out32(info->channel.IndexAddr, info->channel.TxControl);
1183         return 0;
1184 }
1185 
1186 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1187 {
1188         struct rocket_config tmp;
1189 
1190         if (!retinfo)
1191                 return -EFAULT;
1192         memset(&tmp, 0, sizeof (tmp));
1193         mutex_lock(&info->port.mutex);
1194         tmp.line = info->line;
1195         tmp.flags = info->flags;
1196         tmp.close_delay = info->port.close_delay;
1197         tmp.closing_wait = info->port.closing_wait;
1198         tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1199         mutex_unlock(&info->port.mutex);
1200 
1201         if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1202                 return -EFAULT;
1203         return 0;
1204 }
1205 
1206 static int set_config(struct tty_struct *tty, struct r_port *info,
1207                                         struct rocket_config __user *new_info)
1208 {
1209         struct rocket_config new_serial;
1210 
1211         if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1212                 return -EFAULT;
1213 
1214         mutex_lock(&info->port.mutex);
1215         if (!capable(CAP_SYS_ADMIN))
1216         {
1217                 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1218                         mutex_unlock(&info->port.mutex);
1219                         return -EPERM;
1220                 }
1221                 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1222                 configure_r_port(tty, info, NULL);
1223                 mutex_unlock(&info->port.mutex);
1224                 return 0;
1225         }
1226 
1227         info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1228         info->port.close_delay = new_serial.close_delay;
1229         info->port.closing_wait = new_serial.closing_wait;
1230 
1231         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1232                 tty->alt_speed = 57600;
1233         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1234                 tty->alt_speed = 115200;
1235         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1236                 tty->alt_speed = 230400;
1237         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1238                 tty->alt_speed = 460800;
1239         mutex_unlock(&info->port.mutex);
1240 
1241         configure_r_port(tty, info, NULL);
1242         return 0;
1243 }
1244 
1245 /*
1246  *  This function fills in a rocket_ports struct with information
1247  *  about what boards/ports are in the system.  This info is passed
1248  *  to user space.  See setrocket.c where the info is used to create
1249  *  the /dev/ttyRx ports.
1250  */
1251 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1252 {
1253         struct rocket_ports tmp;
1254         int board;
1255 
1256         if (!retports)
1257                 return -EFAULT;
1258         memset(&tmp, 0, sizeof (tmp));
1259         tmp.tty_major = rocket_driver->major;
1260 
1261         for (board = 0; board < 4; board++) {
1262                 tmp.rocketModel[board].model = rocketModel[board].model;
1263                 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1264                 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1265                 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1266                 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1267         }
1268         if (copy_to_user(retports, &tmp, sizeof (*retports)))
1269                 return -EFAULT;
1270         return 0;
1271 }
1272 
1273 static int reset_rm2(struct r_port *info, void __user *arg)
1274 {
1275         int reset;
1276 
1277         if (!capable(CAP_SYS_ADMIN))
1278                 return -EPERM;
1279 
1280         if (copy_from_user(&reset, arg, sizeof (int)))
1281                 return -EFAULT;
1282         if (reset)
1283                 reset = 1;
1284 
1285         if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1286             rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1287                 return -EINVAL;
1288 
1289         if (info->ctlp->BusType == isISA)
1290                 sModemReset(info->ctlp, info->chan, reset);
1291         else
1292                 sPCIModemReset(info->ctlp, info->chan, reset);
1293 
1294         return 0;
1295 }
1296 
1297 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1298 {
1299         if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1300                 return -EFAULT;
1301         return 0;
1302 }
1303 
1304 /*  IOCTL call handler into the driver */
1305 static int rp_ioctl(struct tty_struct *tty,
1306                     unsigned int cmd, unsigned long arg)
1307 {
1308         struct r_port *info = tty->driver_data;
1309         void __user *argp = (void __user *)arg;
1310         int ret = 0;
1311 
1312         if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1313                 return -ENXIO;
1314 
1315         switch (cmd) {
1316         case RCKP_GET_STRUCT:
1317                 if (copy_to_user(argp, info, sizeof (struct r_port)))
1318                         ret = -EFAULT;
1319                 break;
1320         case RCKP_GET_CONFIG:
1321                 ret = get_config(info, argp);
1322                 break;
1323         case RCKP_SET_CONFIG:
1324                 ret = set_config(tty, info, argp);
1325                 break;
1326         case RCKP_GET_PORTS:
1327                 ret = get_ports(info, argp);
1328                 break;
1329         case RCKP_RESET_RM2:
1330                 ret = reset_rm2(info, argp);
1331                 break;
1332         case RCKP_GET_VERSION:
1333                 ret = get_version(info, argp);
1334                 break;
1335         default:
1336                 ret = -ENOIOCTLCMD;
1337         }
1338         return ret;
1339 }
1340 
1341 static void rp_send_xchar(struct tty_struct *tty, char ch)
1342 {
1343         struct r_port *info = tty->driver_data;
1344         CHANNEL_t *cp;
1345 
1346         if (rocket_paranoia_check(info, "rp_send_xchar"))
1347                 return;
1348 
1349         cp = &info->channel;
1350         if (sGetTxCnt(cp))
1351                 sWriteTxPrioByte(cp, ch);
1352         else
1353                 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1354 }
1355 
1356 static void rp_throttle(struct tty_struct *tty)
1357 {
1358         struct r_port *info = tty->driver_data;
1359 
1360 #ifdef ROCKET_DEBUG_THROTTLE
1361         printk(KERN_INFO "throttle %s ....\n", tty->name);
1362 #endif
1363 
1364         if (rocket_paranoia_check(info, "rp_throttle"))
1365                 return;
1366 
1367         if (I_IXOFF(tty))
1368                 rp_send_xchar(tty, STOP_CHAR(tty));
1369 
1370         sClrRTS(&info->channel);
1371 }
1372 
1373 static void rp_unthrottle(struct tty_struct *tty)
1374 {
1375         struct r_port *info = tty->driver_data;
1376 #ifdef ROCKET_DEBUG_THROTTLE
1377         printk(KERN_INFO "unthrottle %s ....\n", tty->name);
1378 #endif
1379 
1380         if (rocket_paranoia_check(info, "rp_unthrottle"))
1381                 return;
1382 
1383         if (I_IXOFF(tty))
1384                 rp_send_xchar(tty, START_CHAR(tty));
1385 
1386         sSetRTS(&info->channel);
1387 }
1388 
1389 /*
1390  * ------------------------------------------------------------
1391  * rp_stop() and rp_start()
1392  *
1393  * This routines are called before setting or resetting tty->stopped.
1394  * They enable or disable transmitter interrupts, as necessary.
1395  * ------------------------------------------------------------
1396  */
1397 static void rp_stop(struct tty_struct *tty)
1398 {
1399         struct r_port *info = tty->driver_data;
1400 
1401 #ifdef ROCKET_DEBUG_FLOW
1402         printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1403                info->xmit_cnt, info->xmit_fifo_room);
1404 #endif
1405 
1406         if (rocket_paranoia_check(info, "rp_stop"))
1407                 return;
1408 
1409         if (sGetTxCnt(&info->channel))
1410                 sDisTransmit(&info->channel);
1411 }
1412 
1413 static void rp_start(struct tty_struct *tty)
1414 {
1415         struct r_port *info = tty->driver_data;
1416 
1417 #ifdef ROCKET_DEBUG_FLOW
1418         printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1419                info->xmit_cnt, info->xmit_fifo_room);
1420 #endif
1421 
1422         if (rocket_paranoia_check(info, "rp_stop"))
1423                 return;
1424 
1425         sEnTransmit(&info->channel);
1426         set_bit((info->aiop * 8) + info->chan,
1427                 (void *) &xmit_flags[info->board]);
1428 }
1429 
1430 /*
1431  * rp_wait_until_sent() --- wait until the transmitter is empty
1432  */
1433 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1434 {
1435         struct r_port *info = tty->driver_data;
1436         CHANNEL_t *cp;
1437         unsigned long orig_jiffies;
1438         int check_time, exit_time;
1439         int txcnt;
1440 
1441         if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1442                 return;
1443 
1444         cp = &info->channel;
1445 
1446         orig_jiffies = jiffies;
1447 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1448         printk(KERN_INFO "In %s(%d) (jiff=%lu)...\n", __func__, timeout,
1449                jiffies);
1450         printk(KERN_INFO "cps=%d...\n", info->cps);
1451 #endif
1452         while (1) {
1453                 txcnt = sGetTxCnt(cp);
1454                 if (!txcnt) {
1455                         if (sGetChanStatusLo(cp) & TXSHRMT)
1456                                 break;
1457                         check_time = (HZ / info->cps) / 5;
1458                 } else {
1459                         check_time = HZ * txcnt / info->cps;
1460                 }
1461                 if (timeout) {
1462                         exit_time = orig_jiffies + timeout - jiffies;
1463                         if (exit_time <= 0)
1464                                 break;
1465                         if (exit_time < check_time)
1466                                 check_time = exit_time;
1467                 }
1468                 if (check_time == 0)
1469                         check_time = 1;
1470 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1471                 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1472                                 jiffies, check_time);
1473 #endif
1474                 msleep_interruptible(jiffies_to_msecs(check_time));
1475                 if (signal_pending(current))
1476                         break;
1477         }
1478         __set_current_state(TASK_RUNNING);
1479 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1480         printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1481 #endif
1482 }
1483 
1484 /*
1485  * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1486  */
1487 static void rp_hangup(struct tty_struct *tty)
1488 {
1489         CHANNEL_t *cp;
1490         struct r_port *info = tty->driver_data;
1491         unsigned long flags;
1492 
1493         if (rocket_paranoia_check(info, "rp_hangup"))
1494                 return;
1495 
1496 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1497         printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1498 #endif
1499         rp_flush_buffer(tty);
1500         spin_lock_irqsave(&info->port.lock, flags);
1501         if (info->port.count)
1502                 atomic_dec(&rp_num_ports_open);
1503         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1504         spin_unlock_irqrestore(&info->port.lock, flags);
1505 
1506         tty_port_hangup(&info->port);
1507 
1508         cp = &info->channel;
1509         sDisRxFIFO(cp);
1510         sDisTransmit(cp);
1511         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1512         sDisCTSFlowCtl(cp);
1513         sDisTxSoftFlowCtl(cp);
1514         sClrTxXOFF(cp);
1515         clear_bit(ASYNCB_INITIALIZED, &info->port.flags);
1516 
1517         wake_up_interruptible(&info->port.open_wait);
1518 }
1519 
1520 /*
1521  *  Exception handler - write char routine.  The RocketPort driver uses a
1522  *  double-buffering strategy, with the twist that if the in-memory CPU
1523  *  buffer is empty, and there's space in the transmit FIFO, the
1524  *  writing routines will write directly to transmit FIFO.
1525  *  Write buffer and counters protected by spinlocks
1526  */
1527 static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1528 {
1529         struct r_port *info = tty->driver_data;
1530         CHANNEL_t *cp;
1531         unsigned long flags;
1532 
1533         if (rocket_paranoia_check(info, "rp_put_char"))
1534                 return 0;
1535 
1536         /*
1537          * Grab the port write mutex, locking out other processes that try to
1538          * write to this port
1539          */
1540         mutex_lock(&info->write_mtx);
1541 
1542 #ifdef ROCKET_DEBUG_WRITE
1543         printk(KERN_INFO "rp_put_char %c...\n", ch);
1544 #endif
1545 
1546         spin_lock_irqsave(&info->slock, flags);
1547         cp = &info->channel;
1548 
1549         if (!tty->stopped && info->xmit_fifo_room == 0)
1550                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1551 
1552         if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1553                 info->xmit_buf[info->xmit_head++] = ch;
1554                 info->xmit_head &= XMIT_BUF_SIZE - 1;
1555                 info->xmit_cnt++;
1556                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1557         } else {
1558                 sOutB(sGetTxRxDataIO(cp), ch);
1559                 info->xmit_fifo_room--;
1560         }
1561         spin_unlock_irqrestore(&info->slock, flags);
1562         mutex_unlock(&info->write_mtx);
1563         return 1;
1564 }
1565 
1566 /*
1567  *  Exception handler - write routine, called when user app writes to the device.
1568  *  A per port write mutex is used to protect from another process writing to
1569  *  this port at the same time.  This other process could be running on the other CPU
1570  *  or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out). 
1571  *  Spinlocks protect the info xmit members.
1572  */
1573 static int rp_write(struct tty_struct *tty,
1574                     const unsigned char *buf, int count)
1575 {
1576         struct r_port *info = tty->driver_data;
1577         CHANNEL_t *cp;
1578         const unsigned char *b;
1579         int c, retval = 0;
1580         unsigned long flags;
1581 
1582         if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1583                 return 0;
1584 
1585         if (mutex_lock_interruptible(&info->write_mtx))
1586                 return -ERESTARTSYS;
1587 
1588 #ifdef ROCKET_DEBUG_WRITE
1589         printk(KERN_INFO "rp_write %d chars...\n", count);
1590 #endif
1591         cp = &info->channel;
1592 
1593         if (!tty->stopped && info->xmit_fifo_room < count)
1594                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1595 
1596         /*
1597          *  If the write queue for the port is empty, and there is FIFO space, stuff bytes 
1598          *  into FIFO.  Use the write queue for temp storage.
1599          */
1600         if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1601                 c = min(count, info->xmit_fifo_room);
1602                 b = buf;
1603 
1604                 /*  Push data into FIFO, 2 bytes at a time */
1605                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1606 
1607                 /*  If there is a byte remaining, write it */
1608                 if (c & 1)
1609                         sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1610 
1611                 retval += c;
1612                 buf += c;
1613                 count -= c;
1614 
1615                 spin_lock_irqsave(&info->slock, flags);
1616                 info->xmit_fifo_room -= c;
1617                 spin_unlock_irqrestore(&info->slock, flags);
1618         }
1619 
1620         /* If count is zero, we wrote it all and are done */
1621         if (!count)
1622                 goto end;
1623 
1624         /*  Write remaining data into the port's xmit_buf */
1625         while (1) {
1626                 /* Hung up ? */
1627                 if (!test_bit(ASYNCB_NORMAL_ACTIVE, &info->port.flags))
1628                         goto end;
1629                 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1630                 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1631                 if (c <= 0)
1632                         break;
1633 
1634                 b = buf;
1635                 memcpy(info->xmit_buf + info->xmit_head, b, c);
1636 
1637                 spin_lock_irqsave(&info->slock, flags);
1638                 info->xmit_head =
1639                     (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1640                 info->xmit_cnt += c;
1641                 spin_unlock_irqrestore(&info->slock, flags);
1642 
1643                 buf += c;
1644                 count -= c;
1645                 retval += c;
1646         }
1647 
1648         if ((retval > 0) && !tty->stopped)
1649                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1650         
1651 end:
1652         if (info->xmit_cnt < WAKEUP_CHARS) {
1653                 tty_wakeup(tty);
1654 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1655                 wake_up_interruptible(&tty->poll_wait);
1656 #endif
1657         }
1658         mutex_unlock(&info->write_mtx);
1659         return retval;
1660 }
1661 
1662 /*
1663  * Return the number of characters that can be sent.  We estimate
1664  * only using the in-memory transmit buffer only, and ignore the
1665  * potential space in the transmit FIFO.
1666  */
1667 static int rp_write_room(struct tty_struct *tty)
1668 {
1669         struct r_port *info = tty->driver_data;
1670         int ret;
1671 
1672         if (rocket_paranoia_check(info, "rp_write_room"))
1673                 return 0;
1674 
1675         ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1676         if (ret < 0)
1677                 ret = 0;
1678 #ifdef ROCKET_DEBUG_WRITE
1679         printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1680 #endif
1681         return ret;
1682 }
1683 
1684 /*
1685  * Return the number of characters in the buffer.  Again, this only
1686  * counts those characters in the in-memory transmit buffer.
1687  */
1688 static int rp_chars_in_buffer(struct tty_struct *tty)
1689 {
1690         struct r_port *info = tty->driver_data;
1691 
1692         if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1693                 return 0;
1694 
1695 #ifdef ROCKET_DEBUG_WRITE
1696         printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1697 #endif
1698         return info->xmit_cnt;
1699 }
1700 
1701 /*
1702  *  Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1703  *  r_port struct for the port.  Note that spinlock are used to protect info members,
1704  *  do not call this function if the spinlock is already held.
1705  */
1706 static void rp_flush_buffer(struct tty_struct *tty)
1707 {
1708         struct r_port *info = tty->driver_data;
1709         CHANNEL_t *cp;
1710         unsigned long flags;
1711 
1712         if (rocket_paranoia_check(info, "rp_flush_buffer"))
1713                 return;
1714 
1715         spin_lock_irqsave(&info->slock, flags);
1716         info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1717         spin_unlock_irqrestore(&info->slock, flags);
1718 
1719 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1720         wake_up_interruptible(&tty->poll_wait);
1721 #endif
1722         tty_wakeup(tty);
1723 
1724         cp = &info->channel;
1725         sFlushTxFIFO(cp);
1726 }
1727 
1728 #ifdef CONFIG_PCI
1729 
1730 static const struct pci_device_id rocket_pci_ids[] = {
1731         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
1732         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
1733         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
1734         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
1735         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
1736         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
1737         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
1738         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
1739         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
1740         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
1741         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
1742         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
1743         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
1744         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
1745         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
1746         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
1747         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
1748         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
1749         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
1750         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
1751         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
1752         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
1753         { }
1754 };
1755 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1756 
1757 /*  Resets the speaker controller on RocketModem II and III devices */
1758 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
1759 {
1760         ByteIO_t addr;
1761 
1762         /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
1763         if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
1764                 addr = CtlP->AiopIO[0] + 0x4F;
1765                 sOutB(addr, 0);
1766         }
1767 
1768         /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
1769         if ((model == MODEL_UPCI_RM3_8PORT)
1770             || (model == MODEL_UPCI_RM3_4PORT)) {
1771                 addr = CtlP->AiopIO[0] + 0x88;
1772                 sOutB(addr, 0);
1773         }
1774 }
1775 
1776 /***************************************************************************
1777 Function: sPCIInitController
1778 Purpose:  Initialization of controller global registers and controller
1779           structure.
1780 Call:     sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
1781                           IRQNum,Frequency,PeriodicOnly)
1782           CONTROLLER_T *CtlP; Ptr to controller structure
1783           int CtlNum; Controller number
1784           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
1785              This list must be in the order the AIOPs will be found on the
1786              controller.  Once an AIOP in the list is not found, it is
1787              assumed that there are no more AIOPs on the controller.
1788           int AiopIOListSize; Number of addresses in AiopIOList
1789           int IRQNum; Interrupt Request number.  Can be any of the following:
1790                          0: Disable global interrupts
1791                          3: IRQ 3
1792                          4: IRQ 4
1793                          5: IRQ 5
1794                          9: IRQ 9
1795                          10: IRQ 10
1796                          11: IRQ 11
1797                          12: IRQ 12
1798                          15: IRQ 15
1799           Byte_t Frequency: A flag identifying the frequency
1800                    of the periodic interrupt, can be any one of the following:
1801                       FREQ_DIS - periodic interrupt disabled
1802                       FREQ_137HZ - 137 Hertz
1803                       FREQ_69HZ - 69 Hertz
1804                       FREQ_34HZ - 34 Hertz
1805                       FREQ_17HZ - 17 Hertz
1806                       FREQ_9HZ - 9 Hertz
1807                       FREQ_4HZ - 4 Hertz
1808                    If IRQNum is set to 0 the Frequency parameter is
1809                    overidden, it is forced to a value of FREQ_DIS.
1810           int PeriodicOnly: 1 if all interrupts except the periodic
1811                                interrupt are to be blocked.
1812                             0 is both the periodic interrupt and
1813                                other channel interrupts are allowed.
1814                             If IRQNum is set to 0 the PeriodicOnly parameter is
1815                                overidden, it is forced to a value of 0.
1816 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
1817                initialization failed.
1818 
1819 Comments:
1820           If periodic interrupts are to be disabled but AIOP interrupts
1821           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1822 
1823           If interrupts are to be completely disabled set IRQNum to 0.
1824 
1825           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1826           invalid combination.
1827 
1828           This function performs initialization of global interrupt modes,
1829           but it does not actually enable global interrupts.  To enable
1830           and disable global interrupts use functions sEnGlobalInt() and
1831           sDisGlobalInt().  Enabling of global interrupts is normally not
1832           done until all other initializations are complete.
1833 
1834           Even if interrupts are globally enabled, they must also be
1835           individually enabled for each channel that is to generate
1836           interrupts.
1837 
1838 Warnings: No range checking on any of the parameters is done.
1839 
1840           No context switches are allowed while executing this function.
1841 
1842           After this function all AIOPs on the controller are disabled,
1843           they can be enabled with sEnAiop().
1844 */
1845 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
1846                               ByteIO_t * AiopIOList, int AiopIOListSize,
1847                               WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
1848                               int PeriodicOnly, int altChanRingIndicator,
1849                               int UPCIRingInd)
1850 {
1851         int i;
1852         ByteIO_t io;
1853 
1854         CtlP->AltChanRingIndicator = altChanRingIndicator;
1855         CtlP->UPCIRingInd = UPCIRingInd;
1856         CtlP->CtlNum = CtlNum;
1857         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
1858         CtlP->BusType = isPCI;  /* controller release 1 */
1859 
1860         if (ConfigIO) {
1861                 CtlP->isUPCI = 1;
1862                 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
1863                 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
1864                 CtlP->AiopIntrBits = upci_aiop_intr_bits;
1865         } else {
1866                 CtlP->isUPCI = 0;
1867                 CtlP->PCIIO =
1868                     (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
1869                 CtlP->AiopIntrBits = aiop_intr_bits;
1870         }
1871 
1872         sPCIControllerEOI(CtlP);        /* clear EOI if warm init */
1873         /* Init AIOPs */
1874         CtlP->NumAiop = 0;
1875         for (i = 0; i < AiopIOListSize; i++) {
1876                 io = AiopIOList[i];
1877                 CtlP->AiopIO[i] = (WordIO_t) io;
1878                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
1879 
1880                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
1881                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
1882                         break;  /* done looking for AIOPs */
1883 
1884                 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
1885                 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
1886                 sOutB(io + _INDX_DATA, sClockPrescale);
1887                 CtlP->NumAiop++;        /* bump count of AIOPs */
1888         }
1889 
1890         if (CtlP->NumAiop == 0)
1891                 return (-1);
1892         else
1893                 return (CtlP->NumAiop);
1894 }
1895 
1896 /*
1897  *  Called when a PCI card is found.  Retrieves and stores model information,
1898  *  init's aiopic and serial port hardware.
1899  *  Inputs:  i is the board number (0-n)
1900  */
1901 static __init int register_PCI(int i, struct pci_dev *dev)
1902 {
1903         int num_aiops, aiop, max_num_aiops, num_chan, chan;
1904         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1905         CONTROLLER_t *ctlp;
1906 
1907         int fast_clock = 0;
1908         int altChanRingIndicator = 0;
1909         int ports_per_aiop = 8;
1910         WordIO_t ConfigIO = 0;
1911         ByteIO_t UPCIRingInd = 0;
1912 
1913         if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
1914             pci_enable_device(dev))
1915                 return 0;
1916 
1917         rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1918 
1919         rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1920         rocketModel[i].loadrm2 = 0;
1921         rocketModel[i].startingPortNumber = nextLineNumber;
1922 
1923         /*  Depending on the model, set up some config variables */
1924         switch (dev->device) {
1925         case PCI_DEVICE_ID_RP4QUAD:
1926                 max_num_aiops = 1;
1927                 ports_per_aiop = 4;
1928                 rocketModel[i].model = MODEL_RP4QUAD;
1929                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1930                 rocketModel[i].numPorts = 4;
1931                 break;
1932         case PCI_DEVICE_ID_RP8OCTA:
1933                 max_num_aiops = 1;
1934                 rocketModel[i].model = MODEL_RP8OCTA;
1935                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1936                 rocketModel[i].numPorts = 8;
1937                 break;
1938         case PCI_DEVICE_ID_URP8OCTA:
1939                 max_num_aiops = 1;
1940                 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1941                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1942                 rocketModel[i].numPorts = 8;
1943                 break;
1944         case PCI_DEVICE_ID_RP8INTF:
1945                 max_num_aiops = 1;
1946                 rocketModel[i].model = MODEL_RP8INTF;
1947                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1948                 rocketModel[i].numPorts = 8;
1949                 break;
1950         case PCI_DEVICE_ID_URP8INTF:
1951                 max_num_aiops = 1;
1952                 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1953                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1954                 rocketModel[i].numPorts = 8;
1955                 break;
1956         case PCI_DEVICE_ID_RP8J:
1957                 max_num_aiops = 1;
1958                 rocketModel[i].model = MODEL_RP8J;
1959                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1960                 rocketModel[i].numPorts = 8;
1961                 break;
1962         case PCI_DEVICE_ID_RP4J:
1963                 max_num_aiops = 1;
1964                 ports_per_aiop = 4;
1965                 rocketModel[i].model = MODEL_RP4J;
1966                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1967                 rocketModel[i].numPorts = 4;
1968                 break;
1969         case PCI_DEVICE_ID_RP8SNI:
1970                 max_num_aiops = 1;
1971                 rocketModel[i].model = MODEL_RP8SNI;
1972                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1973                 rocketModel[i].numPorts = 8;
1974                 break;
1975         case PCI_DEVICE_ID_RP16SNI:
1976                 max_num_aiops = 2;
1977                 rocketModel[i].model = MODEL_RP16SNI;
1978                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1979                 rocketModel[i].numPorts = 16;
1980                 break;
1981         case PCI_DEVICE_ID_RP16INTF:
1982                 max_num_aiops = 2;
1983                 rocketModel[i].model = MODEL_RP16INTF;
1984                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1985                 rocketModel[i].numPorts = 16;
1986                 break;
1987         case PCI_DEVICE_ID_URP16INTF:
1988                 max_num_aiops = 2;
1989                 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1990                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1991                 rocketModel[i].numPorts = 16;
1992                 break;
1993         case PCI_DEVICE_ID_CRP16INTF:
1994                 max_num_aiops = 2;
1995                 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1996                 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1997                 rocketModel[i].numPorts = 16;
1998                 break;
1999         case PCI_DEVICE_ID_RP32INTF:
2000                 max_num_aiops = 4;
2001                 rocketModel[i].model = MODEL_RP32INTF;
2002                 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
2003                 rocketModel[i].numPorts = 32;
2004                 break;
2005         case PCI_DEVICE_ID_URP32INTF:
2006                 max_num_aiops = 4;
2007                 rocketModel[i].model = MODEL_UPCI_RP32INTF;
2008                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
2009                 rocketModel[i].numPorts = 32;
2010                 break;
2011         case PCI_DEVICE_ID_RPP4:
2012                 max_num_aiops = 1;
2013                 ports_per_aiop = 4;
2014                 altChanRingIndicator++;
2015                 fast_clock++;
2016                 rocketModel[i].model = MODEL_RPP4;
2017                 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2018                 rocketModel[i].numPorts = 4;
2019                 break;
2020         case PCI_DEVICE_ID_RPP8:
2021                 max_num_aiops = 2;
2022                 ports_per_aiop = 4;
2023                 altChanRingIndicator++;
2024                 fast_clock++;
2025                 rocketModel[i].model = MODEL_RPP8;
2026                 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2027                 rocketModel[i].numPorts = 8;
2028                 break;
2029         case PCI_DEVICE_ID_RP2_232:
2030                 max_num_aiops = 1;
2031                 ports_per_aiop = 2;
2032                 altChanRingIndicator++;
2033                 fast_clock++;
2034                 rocketModel[i].model = MODEL_RP2_232;
2035                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2036                 rocketModel[i].numPorts = 2;
2037                 break;
2038         case PCI_DEVICE_ID_RP2_422:
2039                 max_num_aiops = 1;
2040                 ports_per_aiop = 2;
2041                 altChanRingIndicator++;
2042                 fast_clock++;
2043                 rocketModel[i].model = MODEL_RP2_422;
2044                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2045                 rocketModel[i].numPorts = 2;
2046                 break;
2047         case PCI_DEVICE_ID_RP6M:
2048 
2049                 max_num_aiops = 1;
2050                 ports_per_aiop = 6;
2051 
2052                 /*  If revision is 1, the rocketmodem flash must be loaded.
2053                  *  If it is 2 it is a "socketed" version. */
2054                 if (dev->revision == 1) {
2055                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2056                         rocketModel[i].loadrm2 = 1;
2057                 } else {
2058                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
2059                 }
2060 
2061                 rocketModel[i].model = MODEL_RP6M;
2062                 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2063                 rocketModel[i].numPorts = 6;
2064                 break;
2065         case PCI_DEVICE_ID_RP4M:
2066                 max_num_aiops = 1;
2067                 ports_per_aiop = 4;
2068                 if (dev->revision == 1) {
2069                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2070                         rocketModel[i].loadrm2 = 1;
2071                 } else {
2072                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
2073                 }
2074 
2075                 rocketModel[i].model = MODEL_RP4M;
2076                 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2077                 rocketModel[i].numPorts = 4;
2078                 break;
2079         default:
2080                 max_num_aiops = 0;
2081                 break;
2082         }
2083 
2084         /*
2085          * Check for UPCI boards.
2086          */
2087 
2088         switch (dev->device) {
2089         case PCI_DEVICE_ID_URP32INTF:
2090         case PCI_DEVICE_ID_URP8INTF:
2091         case PCI_DEVICE_ID_URP16INTF:
2092         case PCI_DEVICE_ID_CRP16INTF:
2093         case PCI_DEVICE_ID_URP8OCTA:
2094                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2095                 ConfigIO = pci_resource_start(dev, 1);
2096                 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2097                         UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2098 
2099                         /*
2100                          * Check for octa or quad cable.
2101                          */
2102                         if (!
2103                             (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2104                              PCI_GPIO_CTRL_8PORT)) {
2105                                 ports_per_aiop = 4;
2106                                 rocketModel[i].numPorts = 4;
2107                         }
2108                 }
2109                 break;
2110         case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2111                 max_num_aiops = 1;
2112                 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2113                 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2114                 rocketModel[i].numPorts = 8;
2115                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2116                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2117                 ConfigIO = pci_resource_start(dev, 1);
2118                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2119                 break;
2120         case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2121                 max_num_aiops = 1;
2122                 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2123                 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2124                 rocketModel[i].numPorts = 4;
2125                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2126                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2127                 ConfigIO = pci_resource_start(dev, 1);
2128                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2129                 break;
2130         default:
2131                 break;
2132         }
2133 
2134         if (fast_clock) {
2135                 sClockPrescale = 0x12;  /* mod 2 (divide by 3) */
2136                 rp_baud_base[i] = 921600;
2137         } else {
2138                 /*
2139                  * If support_low_speed is set, use the slow clock
2140                  * prescale, which supports 50 bps
2141                  */
2142                 if (support_low_speed) {
2143                         /* mod 9 (divide by 10) prescale */
2144                         sClockPrescale = 0x19;
2145                         rp_baud_base[i] = 230400;
2146                 } else {
2147                         /* mod 4 (divide by 5) prescale */
2148                         sClockPrescale = 0x14;
2149                         rp_baud_base[i] = 460800;
2150                 }
2151         }
2152 
2153         for (aiop = 0; aiop < max_num_aiops; aiop++)
2154                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2155         ctlp = sCtlNumToCtlPtr(i);
2156         num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2157         for (aiop = 0; aiop < max_num_aiops; aiop++)
2158                 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2159 
2160         dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2161                 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2162                 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2163                 rocketModel[i].startingPortNumber,
2164                 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2165 
2166         if (num_aiops <= 0) {
2167                 rcktpt_io_addr[i] = 0;
2168                 return (0);
2169         }
2170         is_PCI[i] = 1;
2171 
2172         /*  Reset the AIOPIC, init the serial ports */
2173         for (aiop = 0; aiop < num_aiops; aiop++) {
2174                 sResetAiopByNum(ctlp, aiop);
2175                 num_chan = ports_per_aiop;
2176                 for (chan = 0; chan < num_chan; chan++)
2177                         init_r_port(i, aiop, chan, dev);
2178         }
2179 
2180         /*  Rocket modems must be reset */
2181         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2182             (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2183             (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2184                 num_chan = ports_per_aiop;
2185                 for (chan = 0; chan < num_chan; chan++)
2186                         sPCIModemReset(ctlp, chan, 1);
2187                 msleep(500);
2188                 for (chan = 0; chan < num_chan; chan++)
2189                         sPCIModemReset(ctlp, chan, 0);
2190                 msleep(500);
2191                 rmSpeakerReset(ctlp, rocketModel[i].model);
2192         }
2193         return (1);
2194 }
2195 
2196 /*
2197  *  Probes for PCI cards, inits them if found
2198  *  Input:   board_found = number of ISA boards already found, or the
2199  *           starting board number
2200  *  Returns: Number of PCI boards found
2201  */
2202 static int __init init_PCI(int boards_found)
2203 {
2204         struct pci_dev *dev = NULL;
2205         int count = 0;
2206 
2207         /*  Work through the PCI device list, pulling out ours */
2208         while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2209                 if (register_PCI(count + boards_found, dev))
2210                         count++;
2211         }
2212         return (count);
2213 }
2214 
2215 #endif                          /* CONFIG_PCI */
2216 
2217 /*
2218  *  Probes for ISA cards
2219  *  Input:   i = the board number to look for
2220  *  Returns: 1 if board found, 0 else
2221  */
2222 static int __init init_ISA(int i)
2223 {
2224         int num_aiops, num_chan = 0, total_num_chan = 0;
2225         int aiop, chan;
2226         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2227         CONTROLLER_t *ctlp;
2228         char *type_string;
2229 
2230         /*  If io_addr is zero, no board configured */
2231         if (rcktpt_io_addr[i] == 0)
2232                 return (0);
2233 
2234         /*  Reserve the IO region */
2235         if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2236                 printk(KERN_ERR "Unable to reserve IO region for configured "
2237                                 "ISA RocketPort at address 0x%lx, board not "
2238                                 "installed...\n", rcktpt_io_addr[i]);
2239                 rcktpt_io_addr[i] = 0;
2240                 return (0);
2241         }
2242 
2243         ctlp = sCtlNumToCtlPtr(i);
2244 
2245         ctlp->boardType = rcktpt_type[i];
2246 
2247         switch (rcktpt_type[i]) {
2248         case ROCKET_TYPE_PC104:
2249                 type_string = "(PC104)";
2250                 break;
2251         case ROCKET_TYPE_MODEM:
2252                 type_string = "(RocketModem)";
2253                 break;
2254         case ROCKET_TYPE_MODEMII:
2255                 type_string = "(RocketModem II)";
2256                 break;
2257         default:
2258                 type_string = "";
2259                 break;
2260         }
2261 
2262         /*
2263          * If support_low_speed is set, use the slow clock prescale,
2264          * which supports 50 bps
2265          */
2266         if (support_low_speed) {
2267                 sClockPrescale = 0x19;  /* mod 9 (divide by 10) prescale */
2268                 rp_baud_base[i] = 230400;
2269         } else {
2270                 sClockPrescale = 0x14;  /* mod 4 (divide by 5) prescale */
2271                 rp_baud_base[i] = 460800;
2272         }
2273 
2274         for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2275                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2276 
2277         num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio,  MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2278 
2279         if (ctlp->boardType == ROCKET_TYPE_PC104) {
2280                 sEnAiop(ctlp, 2);       /* only one AIOPIC, but these */
2281                 sEnAiop(ctlp, 3);       /* CSels used for other stuff */
2282         }
2283 
2284         /*  If something went wrong initing the AIOP's release the ISA IO memory */
2285         if (num_aiops <= 0) {
2286                 release_region(rcktpt_io_addr[i], 64);
2287                 rcktpt_io_addr[i] = 0;
2288                 return (0);
2289         }
2290   
2291         rocketModel[i].startingPortNumber = nextLineNumber;
2292 
2293         for (aiop = 0; aiop < num_aiops; aiop++) {
2294                 sResetAiopByNum(ctlp, aiop);
2295                 sEnAiop(ctlp, aiop);
2296                 num_chan = sGetAiopNumChan(ctlp, aiop);
2297                 total_num_chan += num_chan;
2298                 for (chan = 0; chan < num_chan; chan++)
2299                         init_r_port(i, aiop, chan, NULL);
2300         }
2301         is_PCI[i] = 0;
2302         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2303                 num_chan = sGetAiopNumChan(ctlp, 0);
2304                 total_num_chan = num_chan;
2305                 for (chan = 0; chan < num_chan; chan++)
2306                         sModemReset(ctlp, chan, 1);
2307                 msleep(500);
2308                 for (chan = 0; chan < num_chan; chan++)
2309                         sModemReset(ctlp, chan, 0);
2310                 msleep(500);
2311                 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2312         } else {
2313                 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2314         }
2315         rocketModel[i].numPorts = total_num_chan;
2316         rocketModel[i].model = MODEL_ISA;
2317 
2318         printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n", 
2319                i, rcktpt_io_addr[i], num_aiops, type_string);
2320 
2321         printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2322                rocketModel[i].modelString,
2323                rocketModel[i].startingPortNumber,
2324                rocketModel[i].startingPortNumber +
2325                rocketModel[i].numPorts - 1);
2326 
2327         return (1);
2328 }
2329 
2330 static const struct tty_operations rocket_ops = {
2331         .open = rp_open,
2332         .close = rp_close,
2333         .write = rp_write,
2334         .put_char = rp_put_char,
2335         .write_room = rp_write_room,
2336         .chars_in_buffer = rp_chars_in_buffer,
2337         .flush_buffer = rp_flush_buffer,
2338         .ioctl = rp_ioctl,
2339         .throttle = rp_throttle,
2340         .unthrottle = rp_unthrottle,
2341         .set_termios = rp_set_termios,
2342         .stop = rp_stop,
2343         .start = rp_start,
2344         .hangup = rp_hangup,
2345         .break_ctl = rp_break,
2346         .send_xchar = rp_send_xchar,
2347         .wait_until_sent = rp_wait_until_sent,
2348         .tiocmget = rp_tiocmget,
2349         .tiocmset = rp_tiocmset,
2350 };
2351 
2352 static const struct tty_port_operations rocket_port_ops = {
2353         .carrier_raised = carrier_raised,
2354         .dtr_rts = dtr_rts,
2355 };
2356 
2357 /*
2358  * The module "startup" routine; it's run when the module is loaded.
2359  */
2360 static int __init rp_init(void)
2361 {
2362         int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2363 
2364         printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2365                ROCKET_VERSION, ROCKET_DATE);
2366 
2367         rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2368         if (!rocket_driver)
2369                 goto err;
2370 
2371         /*
2372          *  If board 1 is non-zero, there is at least one ISA configured.  If controller is 
2373          *  zero, use the default controller IO address of board1 + 0x40.
2374          */
2375         if (board1) {
2376                 if (controller == 0)
2377                         controller = board1 + 0x40;
2378         } else {
2379                 controller = 0;  /*  Used as a flag, meaning no ISA boards */
2380         }
2381 
2382         /*  If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2383         if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2384                 printk(KERN_ERR "Unable to reserve IO region for first "
2385                         "configured ISA RocketPort controller 0x%lx.  "
2386                         "Driver exiting\n", controller);
2387                 ret = -EBUSY;
2388                 goto err_tty;
2389         }
2390 
2391         /*  Store ISA variable retrieved from command line or .conf file. */
2392         rcktpt_io_addr[0] = board1;
2393         rcktpt_io_addr[1] = board2;
2394         rcktpt_io_addr[2] = board3;
2395         rcktpt_io_addr[3] = board4;
2396 
2397         rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2398         rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2399         rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2400         rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2401         rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2402         rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2403         rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2404         rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2405 
2406         /*
2407          * Set up the tty driver structure and then register this
2408          * driver with the tty layer.
2409          */
2410 
2411         rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2412         rocket_driver->name = "ttyR";
2413         rocket_driver->driver_name = "Comtrol RocketPort";
2414         rocket_driver->major = TTY_ROCKET_MAJOR;
2415         rocket_driver->minor_start = 0;
2416         rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2417         rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2418         rocket_driver->init_termios = tty_std_termios;
2419         rocket_driver->init_termios.c_cflag =
2420             B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2421         rocket_driver->init_termios.c_ispeed = 9600;
2422         rocket_driver->init_termios.c_ospeed = 9600;
2423 #ifdef ROCKET_SOFT_FLOW
2424         rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2425 #endif
2426         tty_set_operations(rocket_driver, &rocket_ops);
2427 
2428         ret = tty_register_driver(rocket_driver);
2429         if (ret < 0) {
2430                 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2431                 goto err_controller;
2432         }
2433 
2434 #ifdef ROCKET_DEBUG_OPEN
2435         printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2436 #endif
2437 
2438         /*
2439          *  OK, let's probe each of the controllers looking for boards.  Any boards found
2440          *  will be initialized here.
2441          */
2442         isa_boards_found = 0;
2443         pci_boards_found = 0;
2444 
2445         for (i = 0; i < NUM_BOARDS; i++) {
2446                 if (init_ISA(i))
2447                         isa_boards_found++;
2448         }
2449 
2450 #ifdef CONFIG_PCI
2451         if (isa_boards_found < NUM_BOARDS)
2452                 pci_boards_found = init_PCI(isa_boards_found);
2453 #endif
2454 
2455         max_board = pci_boards_found + isa_boards_found;
2456 
2457         if (max_board == 0) {
2458                 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2459                 ret = -ENXIO;
2460                 goto err_ttyu;
2461         }
2462 
2463         return 0;
2464 err_ttyu:
2465         tty_unregister_driver(rocket_driver);
2466 err_controller:
2467         if (controller)
2468                 release_region(controller, 4);
2469 err_tty:
2470         put_tty_driver(rocket_driver);
2471 err:
2472         return ret;
2473 }
2474 
2475 
2476 static void rp_cleanup_module(void)
2477 {
2478         int retval;
2479         int i;
2480 
2481         del_timer_sync(&rocket_timer);
2482 
2483         retval = tty_unregister_driver(rocket_driver);
2484         if (retval)
2485                 printk(KERN_ERR "Error %d while trying to unregister "
2486                        "rocketport driver\n", -retval);
2487 
2488         for (i = 0; i < MAX_RP_PORTS; i++)
2489                 if (rp_table[i]) {
2490                         tty_unregister_device(rocket_driver, i);
2491                         tty_port_destroy(&rp_table[i]->port);
2492                         kfree(rp_table[i]);
2493                 }
2494 
2495         put_tty_driver(rocket_driver);
2496 
2497         for (i = 0; i < NUM_BOARDS; i++) {
2498                 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2499                         continue;
2500                 release_region(rcktpt_io_addr[i], 64);
2501         }
2502         if (controller)
2503                 release_region(controller, 4);
2504 }
2505 
2506 /***************************************************************************
2507 Function: sInitController
2508 Purpose:  Initialization of controller global registers and controller
2509           structure.
2510 Call:     sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2511                           IRQNum,Frequency,PeriodicOnly)
2512           CONTROLLER_T *CtlP; Ptr to controller structure
2513           int CtlNum; Controller number
2514           ByteIO_t MudbacIO; Mudbac base I/O address.
2515           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2516              This list must be in the order the AIOPs will be found on the
2517              controller.  Once an AIOP in the list is not found, it is
2518              assumed that there are no more AIOPs on the controller.
2519           int AiopIOListSize; Number of addresses in AiopIOList
2520           int IRQNum; Interrupt Request number.  Can be any of the following:
2521                          0: Disable global interrupts
2522                          3: IRQ 3
2523                          4: IRQ 4
2524                          5: IRQ 5
2525                          9: IRQ 9
2526                          10: IRQ 10
2527                          11: IRQ 11
2528                          12: IRQ 12
2529                          15: IRQ 15
2530           Byte_t Frequency: A flag identifying the frequency
2531                    of the periodic interrupt, can be any one of the following:
2532                       FREQ_DIS - periodic interrupt disabled
2533                       FREQ_137HZ - 137 Hertz
2534                       FREQ_69HZ - 69 Hertz
2535                       FREQ_34HZ - 34 Hertz
2536                       FREQ_17HZ - 17 Hertz
2537                       FREQ_9HZ - 9 Hertz
2538                       FREQ_4HZ - 4 Hertz
2539                    If IRQNum is set to 0 the Frequency parameter is
2540                    overidden, it is forced to a value of FREQ_DIS.
2541           int PeriodicOnly: 1 if all interrupts except the periodic
2542                                interrupt are to be blocked.
2543                             0 is both the periodic interrupt and
2544                                other channel interrupts are allowed.
2545                             If IRQNum is set to 0 the PeriodicOnly parameter is
2546                                overidden, it is forced to a value of 0.
2547 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
2548                initialization failed.
2549 
2550 Comments:
2551           If periodic interrupts are to be disabled but AIOP interrupts
2552           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2553 
2554           If interrupts are to be completely disabled set IRQNum to 0.
2555 
2556           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2557           invalid combination.
2558 
2559           This function performs initialization of global interrupt modes,
2560           but it does not actually enable global interrupts.  To enable
2561           and disable global interrupts use functions sEnGlobalInt() and
2562           sDisGlobalInt().  Enabling of global interrupts is normally not
2563           done until all other initializations are complete.
2564 
2565           Even if interrupts are globally enabled, they must also be
2566           individually enabled for each channel that is to generate
2567           interrupts.
2568 
2569 Warnings: No range checking on any of the parameters is done.
2570 
2571           No context switches are allowed while executing this function.
2572 
2573           After this function all AIOPs on the controller are disabled,
2574           they can be enabled with sEnAiop().
2575 */
2576 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2577                            ByteIO_t * AiopIOList, int AiopIOListSize,
2578                            int IRQNum, Byte_t Frequency, int PeriodicOnly)
2579 {
2580         int i;
2581         ByteIO_t io;
2582         int done;
2583 
2584         CtlP->AiopIntrBits = aiop_intr_bits;
2585         CtlP->AltChanRingIndicator = 0;
2586         CtlP->CtlNum = CtlNum;
2587         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
2588         CtlP->BusType = isISA;
2589         CtlP->MBaseIO = MudbacIO;
2590         CtlP->MReg1IO = MudbacIO + 1;
2591         CtlP->MReg2IO = MudbacIO + 2;
2592         CtlP->MReg3IO = MudbacIO + 3;
2593 #if 1
2594         CtlP->MReg2 = 0;        /* interrupt disable */
2595         CtlP->MReg3 = 0;        /* no periodic interrupts */
2596 #else
2597         if (sIRQMap[IRQNum] == 0) {     /* interrupts globally disabled */
2598                 CtlP->MReg2 = 0;        /* interrupt disable */
2599                 CtlP->MReg3 = 0;        /* no periodic interrupts */
2600         } else {
2601                 CtlP->MReg2 = sIRQMap[IRQNum];  /* set IRQ number */
2602                 CtlP->MReg3 = Frequency;        /* set frequency */
2603                 if (PeriodicOnly) {     /* periodic interrupt only */
2604                         CtlP->MReg3 |= PERIODIC_ONLY;
2605                 }
2606         }
2607 #endif
2608         sOutB(CtlP->MReg2IO, CtlP->MReg2);
2609         sOutB(CtlP->MReg3IO, CtlP->MReg3);
2610         sControllerEOI(CtlP);   /* clear EOI if warm init */
2611         /* Init AIOPs */
2612         CtlP->NumAiop = 0;
2613         for (i = done = 0; i < AiopIOListSize; i++) {
2614                 io = AiopIOList[i];
2615                 CtlP->AiopIO[i] = (WordIO_t) io;
2616                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2617                 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2618                 sOutB(MudbacIO, (Byte_t) (io >> 6));    /* set up AIOP I/O in MUDBAC */
2619                 if (done)
2620                         continue;
2621                 sEnAiop(CtlP, i);       /* enable the AIOP */
2622                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
2623                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
2624                         done = 1;       /* done looking for AIOPs */
2625                 else {
2626                         CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2627                         sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
2628                         sOutB(io + _INDX_DATA, sClockPrescale);
2629                         CtlP->NumAiop++;        /* bump count of AIOPs */
2630                 }
2631                 sDisAiop(CtlP, i);      /* disable AIOP */
2632         }
2633 
2634         if (CtlP->NumAiop == 0)
2635                 return (-1);
2636         else
2637                 return (CtlP->NumAiop);
2638 }
2639 
2640 /***************************************************************************
2641 Function: sReadAiopID
2642 Purpose:  Read the AIOP idenfication number directly from an AIOP.
2643 Call:     sReadAiopID(io)
2644           ByteIO_t io: AIOP base I/O address
2645 Return:   int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2646                  is replace by an identifying number.
2647           Flag AIOPID_NULL if no valid AIOP is found
2648 Warnings: No context switches are allowed while executing this function.
2649 
2650 */
2651 static int sReadAiopID(ByteIO_t io)
2652 {
2653         Byte_t AiopID;          /* ID byte from AIOP */
2654 
2655         sOutB(io + _CMD_REG, RESET_ALL);        /* reset AIOP */
2656         sOutB(io + _CMD_REG, 0x0);
2657         AiopID = sInW(io + _CHN_STAT0) & 0x07;
2658         if (AiopID == 0x06)
2659                 return (1);
2660         else                    /* AIOP does not exist */
2661                 return (-1);
2662 }
2663 
2664 /***************************************************************************
2665 Function: sReadAiopNumChan
2666 Purpose:  Read the number of channels available in an AIOP directly from
2667           an AIOP.
2668 Call:     sReadAiopNumChan(io)
2669           WordIO_t io: AIOP base I/O address
2670 Return:   int: The number of channels available
2671 Comments: The number of channels is determined by write/reads from identical
2672           offsets within the SRAM address spaces for channels 0 and 4.
2673           If the channel 4 space is mirrored to channel 0 it is a 4 channel
2674           AIOP, otherwise it is an 8 channel.
2675 Warnings: No context switches are allowed while executing this function.
2676 */
2677 static int sReadAiopNumChan(WordIO_t io)
2678 {
2679         Word_t x;
2680         static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2681 
2682         /* write to chan 0 SRAM */
2683         out32((DWordIO_t) io + _INDX_ADDR, R);
2684         sOutW(io + _INDX_ADDR, 0);      /* read from SRAM, chan 0 */
2685         x = sInW(io + _INDX_DATA);
2686         sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2687         if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2688                 return (8);
2689         else
2690                 return (4);
2691 }
2692 
2693 /***************************************************************************
2694 Function: sInitChan
2695 Purpose:  Initialization of a channel and channel structure
2696 Call:     sInitChan(CtlP,ChP,AiopNum,ChanNum)
2697           CONTROLLER_T *CtlP; Ptr to controller structure
2698           CHANNEL_T *ChP; Ptr to channel structure
2699           int AiopNum; AIOP number within controller
2700           int ChanNum; Channel number within AIOP
2701 Return:   int: 1 if initialization succeeded, 0 if it fails because channel
2702                number exceeds number of channels available in AIOP.
2703 Comments: This function must be called before a channel can be used.
2704 Warnings: No range checking on any of the parameters is done.
2705 
2706           No context switches are allowed while executing this function.
2707 */
2708 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2709                      int ChanNum)
2710 {
2711         int i;
2712         WordIO_t AiopIO;
2713         WordIO_t ChIOOff;
2714         Byte_t *ChR;
2715         Word_t ChOff;
2716         static Byte_t R[4];
2717         int brd9600;
2718 
2719         if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2720                 return 0;       /* exceeds num chans in AIOP */
2721 
2722         /* Channel, AIOP, and controller identifiers */
2723         ChP->CtlP = CtlP;
2724         ChP->ChanID = CtlP->AiopID[AiopNum];
2725         ChP->AiopNum = AiopNum;
2726         ChP->ChanNum = ChanNum;
2727 
2728         /* Global direct addresses */
2729         AiopIO = CtlP->AiopIO[AiopNum];
2730         ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2731         ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2732         ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2733         ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2734         ChP->IndexData = AiopIO + _INDX_DATA;
2735 
2736         /* Channel direct addresses */
2737         ChIOOff = AiopIO + ChP->ChanNum * 2;
2738         ChP->TxRxData = ChIOOff + _TD0;
2739         ChP->ChanStat = ChIOOff + _CHN_STAT0;
2740         ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2741         ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2742 
2743         /* Initialize the channel from the RData array */
2744         for (i = 0; i < RDATASIZE; i += 4) {
2745                 R[0] = RData[i];
2746                 R[1] = RData[i + 1] + 0x10 * ChanNum;
2747                 R[2] = RData[i + 2];
2748                 R[3] = RData[i + 3];
2749                 out32(ChP->IndexAddr, R);
2750         }
2751 
2752         ChR = ChP->R;
2753         for (i = 0; i < RREGDATASIZE; i += 4) {
2754                 ChR[i] = RRegData[i];
2755                 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2756                 ChR[i + 2] = RRegData[i + 2];
2757                 ChR[i + 3] = RRegData[i + 3];
2758         }
2759 
2760         /* Indexed registers */
2761         ChOff = (Word_t) ChanNum *0x1000;
2762 
2763         if (sClockPrescale == 0x14)
2764                 brd9600 = 47;
2765         else
2766                 brd9600 = 23;
2767 
2768         ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2769         ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2770         ChP->BaudDiv[2] = (Byte_t) brd9600;
2771         ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2772         out32(ChP->IndexAddr, ChP->BaudDiv);
2773 
2774         ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2775         ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2776         ChP->TxControl[2] = 0;
2777         ChP->TxControl[3] = 0;
2778         out32(ChP->IndexAddr, ChP->TxControl);
2779 
2780         ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2781         ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2782         ChP->RxControl[2] = 0;
2783         ChP->RxControl[3] = 0;
2784         out32(ChP->IndexAddr, ChP->RxControl);
2785 
2786         ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2787         ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2788         ChP->TxEnables[2] = 0;
2789         ChP->TxEnables[3] = 0;
2790         out32(ChP->IndexAddr, ChP->TxEnables);
2791 
2792         ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2793         ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2794         ChP->TxCompare[2] = 0;
2795         ChP->TxCompare[3] = 0;
2796         out32(ChP->IndexAddr, ChP->TxCompare);
2797 
2798         ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2799         ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2800         ChP->TxReplace1[2] = 0;
2801         ChP->TxReplace1[3] = 0;
2802         out32(ChP->IndexAddr, ChP->TxReplace1);
2803 
2804         ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2805         ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2806         ChP->TxReplace2[2] = 0;
2807         ChP->TxReplace2[3] = 0;
2808         out32(ChP->IndexAddr, ChP->TxReplace2);
2809 
2810         ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2811         ChP->TxFIFO = ChOff + _TX_FIFO;
2812 
2813         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT);  /* apply reset Tx FIFO count */
2814         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Tx FIFO count */
2815         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
2816         sOutW(ChP->IndexData, 0);
2817         ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2818         ChP->RxFIFO = ChOff + _RX_FIFO;
2819 
2820         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT);  /* apply reset Rx FIFO count */
2821         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Rx FIFO count */
2822         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
2823         sOutW(ChP->IndexData, 0);
2824         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
2825         sOutW(ChP->IndexData, 0);
2826         ChP->TxPrioCnt = ChOff + _TXP_CNT;
2827         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2828         sOutB(ChP->IndexData, 0);
2829         ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2830         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2831         sOutB(ChP->IndexData, 0);
2832         ChP->TxPrioBuf = ChOff + _TXP_BUF;
2833         sEnRxProcessor(ChP);    /* start the Rx processor */
2834 
2835         return 1;
2836 }
2837 
2838 /***************************************************************************
2839 Function: sStopRxProcessor
2840 Purpose:  Stop the receive processor from processing a channel.
2841 Call:     sStopRxProcessor(ChP)
2842           CHANNEL_T *ChP; Ptr to channel structure
2843 
2844 Comments: The receive processor can be started again with sStartRxProcessor().
2845           This function causes the receive processor to skip over the
2846           stopped channel.  It does not stop it from processing other channels.
2847 
2848 Warnings: No context switches are allowed while executing this function.
2849 
2850           Do not leave the receive processor stopped for more than one
2851           character time.
2852 
2853           After calling this function a delay of 4 uS is required to ensure
2854           that the receive processor is no longer processing this channel.
2855 */
2856 static void sStopRxProcessor(CHANNEL_T * ChP)
2857 {
2858         Byte_t R[4];
2859 
2860         R[0] = ChP->R[0];
2861         R[1] = ChP->R[1];
2862         R[2] = 0x0a;
2863         R[3] = ChP->R[3];
2864         out32(ChP->IndexAddr, R);
2865 }
2866 
2867 /***************************************************************************
2868 Function: sFlushRxFIFO
2869 Purpose:  Flush the Rx FIFO
2870 Call:     sFlushRxFIFO(ChP)
2871           CHANNEL_T *ChP; Ptr to channel structure
2872 Return:   void
2873 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2874           while it is being flushed the receive processor is stopped
2875           and the transmitter is disabled.  After these operations a
2876           4 uS delay is done before clearing the pointers to allow
2877           the receive processor to stop.  These items are handled inside
2878           this function.
2879 Warnings: No context switches are allowed while executing this function.
2880 */
2881 static void sFlushRxFIFO(CHANNEL_T * ChP)
2882 {
2883         int i;
2884         Byte_t Ch;              /* channel number within AIOP */
2885         int RxFIFOEnabled;      /* 1 if Rx FIFO enabled */
2886 
2887         if (sGetRxCnt(ChP) == 0)        /* Rx FIFO empty */
2888                 return;         /* don't need to flush */
2889 
2890         RxFIFOEnabled = 0;
2891         if (ChP->R[0x32] == 0x08) {     /* Rx FIFO is enabled */
2892                 RxFIFOEnabled = 1;
2893                 sDisRxFIFO(ChP);        /* disable it */
2894                 for (i = 0; i < 2000 / 200; i++)        /* delay 2 uS to allow proc to disable FIFO */
2895                         sInB(ChP->IntChan);     /* depends on bus i/o timing */
2896         }
2897         sGetChanStatus(ChP);    /* clear any pending Rx errors in chan stat */
2898         Ch = (Byte_t) sGetChanNum(ChP);
2899         sOutB(ChP->Cmd, Ch | RESRXFCNT);        /* apply reset Rx FIFO count */
2900         sOutB(ChP->Cmd, Ch);    /* remove reset Rx FIFO count */
2901         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
2902         sOutW(ChP->IndexData, 0);
2903         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
2904         sOutW(ChP->IndexData, 0);
2905         if (RxFIFOEnabled)
2906                 sEnRxFIFO(ChP); /* enable Rx FIFO */
2907 }
2908 
2909 /***************************************************************************
2910 Function: sFlushTxFIFO
2911 Purpose:  Flush the Tx FIFO
2912 Call:     sFlushTxFIFO(ChP)
2913           CHANNEL_T *ChP; Ptr to channel structure
2914 Return:   void
2915 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2916           while it is being flushed the receive processor is stopped
2917           and the transmitter is disabled.  After these operations a
2918           4 uS delay is done before clearing the pointers to allow
2919           the receive processor to stop.  These items are handled inside
2920           this function.
2921 Warnings: No context switches are allowed while executing this function.
2922 */
2923 static void sFlushTxFIFO(CHANNEL_T * ChP)
2924 {
2925         int i;
2926         Byte_t Ch;              /* channel number within AIOP */
2927         int TxEnabled;          /* 1 if transmitter enabled */
2928 
2929         if (sGetTxCnt(ChP) == 0)        /* Tx FIFO empty */
2930                 return;         /* don't need to flush */
2931 
2932         TxEnabled = 0;
2933         if (ChP->TxControl[3] & TX_ENABLE) {
2934                 TxEnabled = 1;
2935                 sDisTransmit(ChP);      /* disable transmitter */
2936         }
2937         sStopRxProcessor(ChP);  /* stop Rx processor */
2938         for (i = 0; i < 4000 / 200; i++)        /* delay 4 uS to allow proc to stop */
2939                 sInB(ChP->IntChan);     /* depends on bus i/o timing */
2940         Ch = (Byte_t) sGetChanNum(ChP);
2941         sOutB(ChP->Cmd, Ch | RESTXFCNT);        /* apply reset Tx FIFO count */
2942         sOutB(ChP->Cmd, Ch);    /* remove reset Tx FIFO count */
2943         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
2944         sOutW(ChP->IndexData, 0);
2945         if (TxEnabled)
2946                 sEnTransmit(ChP);       /* enable transmitter */
2947         sStartRxProcessor(ChP); /* restart Rx processor */
2948 }
2949 
2950 /***************************************************************************
2951 Function: sWriteTxPrioByte
2952 Purpose:  Write a byte of priority transmit data to a channel
2953 Call:     sWriteTxPrioByte(ChP,Data)
2954           CHANNEL_T *ChP; Ptr to channel structure
2955           Byte_t Data; The transmit data byte
2956 
2957 Return:   int: 1 if the bytes is successfully written, otherwise 0.
2958 
2959 Comments: The priority byte is transmitted before any data in the Tx FIFO.
2960 
2961 Warnings: No context switches are allowed while executing this function.
2962 */
2963 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2964 {
2965         Byte_t DWBuf[4];        /* buffer for double word writes */
2966         Word_t *WordPtr;        /* must be far because Win SS != DS */
2967         register DWordIO_t IndexAddr;
2968 
2969         if (sGetTxCnt(ChP) > 1) {       /* write it to Tx priority buffer */
2970                 IndexAddr = ChP->IndexAddr;
2971                 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt);    /* get priority buffer status */
2972                 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2973                         return (0);     /* nothing sent */
2974 
2975                 WordPtr = (Word_t *) (&DWBuf[0]);
2976                 *WordPtr = ChP->TxPrioBuf;      /* data byte address */
2977 
2978                 DWBuf[2] = Data;        /* data byte value */
2979                 out32(IndexAddr, DWBuf);        /* write it out */
2980 
2981                 *WordPtr = ChP->TxPrioCnt;      /* Tx priority count address */
2982 
2983                 DWBuf[2] = PRI_PEND + 1;        /* indicate 1 byte pending */
2984                 DWBuf[3] = 0;   /* priority buffer pointer */
2985                 out32(IndexAddr, DWBuf);        /* write it out */
2986         } else {                /* write it to Tx FIFO */
2987 
2988                 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2989         }
2990         return (1);             /* 1 byte sent */
2991 }
2992 
2993 /***************************************************************************
2994 Function: sEnInterrupts
2995 Purpose:  Enable one or more interrupts for a channel
2996 Call:     sEnInterrupts(ChP,Flags)
2997           CHANNEL_T *ChP; Ptr to channel structure
2998           Word_t Flags: Interrupt enable flags, can be any combination
2999              of the following flags:
3000                 TXINT_EN:   Interrupt on Tx FIFO empty
3001                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3002                             sSetRxTrigger())
3003                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3004                 MCINT_EN:   Interrupt on modem input change
3005                 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3006                             Interrupt Channel Register.
3007 Return:   void
3008 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3009           enabled.  If an interrupt enable flag is not set in Flags, that
3010           interrupt will not be changed.  Interrupts can be disabled with
3011           function sDisInterrupts().
3012 
3013           This function sets the appropriate bit for the channel in the AIOP's
3014           Interrupt Mask Register if the CHANINT_EN flag is set.  This allows
3015           this channel's bit to be set in the AIOP's Interrupt Channel Register.
3016 
3017           Interrupts must also be globally enabled before channel interrupts
3018           will be passed on to the host.  This is done with function
3019           sEnGlobalInt().
3020 
3021           In some cases it may be desirable to disable interrupts globally but
3022           enable channel interrupts.  This would allow the global interrupt
3023           status register to be used to determine which AIOPs need service.
3024 */
3025 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3026 {
3027         Byte_t Mask;            /* Interrupt Mask Register */
3028 
3029         ChP->RxControl[2] |=
3030             ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3031 
3032         out32(ChP->IndexAddr, ChP->RxControl);
3033 
3034         ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3035 
3036         out32(ChP->IndexAddr, ChP->TxControl);
3037 
3038         if (Flags & CHANINT_EN) {
3039                 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3040                 sOutB(ChP->IntMask, Mask);
3041         }
3042 }
3043 
3044 /***************************************************************************
3045 Function: sDisInterrupts
3046 Purpose:  Disable one or more interrupts for a channel
3047 Call:     sDisInterrupts(ChP,Flags)
3048           CHANNEL_T *ChP; Ptr to channel structure
3049           Word_t Flags: Interrupt flags, can be any combination
3050              of the following flags:
3051                 TXINT_EN:   Interrupt on Tx FIFO empty
3052                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3053                             sSetRxTrigger())
3054                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3055                 MCINT_EN:   Interrupt on modem input change
3056                 CHANINT_EN: Disable channel interrupt signal to the
3057                             AIOP's Interrupt Channel Register.
3058 Return:   void
3059 Comments: If an interrupt flag is set in Flags, that interrupt will be
3060           disabled.  If an interrupt flag is not set in Flags, that
3061           interrupt will not be changed.  Interrupts can be enabled with
3062           function sEnInterrupts().
3063 
3064           This function clears the appropriate bit for the channel in the AIOP's
3065           Interrupt Mask Register if the CHANINT_EN flag is set.  This blocks
3066           this channel's bit from being set in the AIOP's Interrupt Channel
3067           Register.
3068 */
3069 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3070 {
3071         Byte_t Mask;            /* Interrupt Mask Register */
3072 
3073         ChP->RxControl[2] &=
3074             ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3075         out32(ChP->IndexAddr, ChP->RxControl);
3076         ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3077         out32(ChP->IndexAddr, ChP->TxControl);
3078 
3079         if (Flags & CHANINT_EN) {
3080                 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3081                 sOutB(ChP->IntMask, Mask);
3082         }
3083 }
3084 
3085 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3086 {
3087         sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3088 }
3089 
3090 /*
3091  *  Not an official SSCI function, but how to reset RocketModems.
3092  *  ISA bus version
3093  */
3094 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3095 {
3096         ByteIO_t addr;
3097         Byte_t val;
3098 
3099         addr = CtlP->AiopIO[0] + 0x400;
3100         val = sInB(CtlP->MReg3IO);
3101         /* if AIOP[1] is not enabled, enable it */
3102         if ((val & 2) == 0) {
3103                 val = sInB(CtlP->MReg2IO);
3104                 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3105                 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3106         }
3107 
3108         sEnAiop(CtlP, 1);
3109         if (!on)
3110                 addr += 8;
3111         sOutB(addr + chan, 0);  /* apply or remove reset */
3112         sDisAiop(CtlP, 1);
3113 }
3114 
3115 /*
3116  *  Not an official SSCI function, but how to reset RocketModems.
3117  *  PCI bus version
3118  */
3119 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3120 {
3121         ByteIO_t addr;
3122 
3123         addr = CtlP->AiopIO[0] + 0x40;  /* 2nd AIOP */
3124         if (!on)
3125                 addr += 8;
3126         sOutB(addr + chan, 0);  /* apply or remove reset */
3127 }
3128 
3129 /*  Returns the line number given the controller (board), aiop and channel number */
3130 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3131 {
3132         return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3133 }
3134 
3135 /*
3136  *  Stores the line number associated with a given controller (board), aiop
3137  *  and channel number.  
3138  *  Returns:  The line number assigned 
3139  */
3140 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3141 {
3142         lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3143         return (nextLineNumber - 1);
3144 }
3145 

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