Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5

Linux/drivers/tty/rocket.c

  1 /*
  2  * RocketPort device driver for Linux
  3  *
  4  * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
  5  * 
  6  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
  7  * 
  8  * This program is free software; you can redistribute it and/or
  9  * modify it under the terms of the GNU General Public License as
 10  * published by the Free Software Foundation; either version 2 of the
 11  * License, or (at your option) any later version.
 12  * 
 13  * This program is distributed in the hope that it will be useful, but
 14  * WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 16  * General Public License for more details.
 17  * 
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program; if not, write to the Free Software
 20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 21  */
 22 
 23 /*
 24  * Kernel Synchronization:
 25  *
 26  * This driver has 2 kernel control paths - exception handlers (calls into the driver
 27  * from user mode) and the timer bottom half (tasklet).  This is a polled driver, interrupts
 28  * are not used.
 29  *
 30  * Critical data: 
 31  * -  rp_table[], accessed through passed "info" pointers, is a global (static) array of 
 32  *    serial port state information and the xmit_buf circular buffer.  Protected by 
 33  *    a per port spinlock.
 34  * -  xmit_flags[], an array of ints indexed by line (port) number, indicating that there
 35  *    is data to be transmitted.  Protected by atomic bit operations.
 36  * -  rp_num_ports, int indicating number of open ports, protected by atomic operations.
 37  * 
 38  * rp_write() and rp_write_char() functions use a per port semaphore to protect against
 39  * simultaneous access to the same port by more than one process.
 40  */
 41 
 42 /****** Defines ******/
 43 #define ROCKET_PARANOIA_CHECK
 44 #define ROCKET_DISABLE_SIMUSAGE
 45 
 46 #undef ROCKET_SOFT_FLOW
 47 #undef ROCKET_DEBUG_OPEN
 48 #undef ROCKET_DEBUG_INTR
 49 #undef ROCKET_DEBUG_WRITE
 50 #undef ROCKET_DEBUG_FLOW
 51 #undef ROCKET_DEBUG_THROTTLE
 52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
 53 #undef ROCKET_DEBUG_RECEIVE
 54 #undef ROCKET_DEBUG_HANGUP
 55 #undef REV_PCI_ORDER
 56 #undef ROCKET_DEBUG_IO
 57 
 58 #define POLL_PERIOD (HZ/100)    /*  Polling period .01 seconds (10ms) */
 59 
 60 /****** Kernel includes ******/
 61 
 62 #include <linux/module.h>
 63 #include <linux/errno.h>
 64 #include <linux/major.h>
 65 #include <linux/kernel.h>
 66 #include <linux/signal.h>
 67 #include <linux/slab.h>
 68 #include <linux/mm.h>
 69 #include <linux/sched.h>
 70 #include <linux/timer.h>
 71 #include <linux/interrupt.h>
 72 #include <linux/tty.h>
 73 #include <linux/tty_driver.h>
 74 #include <linux/tty_flip.h>
 75 #include <linux/serial.h>
 76 #include <linux/string.h>
 77 #include <linux/fcntl.h>
 78 #include <linux/ptrace.h>
 79 #include <linux/mutex.h>
 80 #include <linux/ioport.h>
 81 #include <linux/delay.h>
 82 #include <linux/completion.h>
 83 #include <linux/wait.h>
 84 #include <linux/pci.h>
 85 #include <linux/uaccess.h>
 86 #include <linux/atomic.h>
 87 #include <asm/unaligned.h>
 88 #include <linux/bitops.h>
 89 #include <linux/spinlock.h>
 90 #include <linux/init.h>
 91 
 92 /****** RocketPort includes ******/
 93 
 94 #include "rocket_int.h"
 95 #include "rocket.h"
 96 
 97 #define ROCKET_VERSION "2.09"
 98 #define ROCKET_DATE "12-June-2003"
 99 
100 /****** RocketPort Local Variables ******/
101 
102 static void rp_do_poll(unsigned long dummy);
103 
104 static struct tty_driver *rocket_driver;
105 
106 static struct rocket_version driver_version = { 
107         ROCKET_VERSION, ROCKET_DATE
108 };
109 
110 static struct r_port *rp_table[MAX_RP_PORTS];          /*  The main repository of serial port state information. */
111 static unsigned int xmit_flags[NUM_BOARDS];            /*  Bit significant, indicates port had data to transmit. */
112                                                        /*  eg.  Bit 0 indicates port 0 has xmit data, ...        */
113 static atomic_t rp_num_ports_open;                     /*  Number of serial ports open                           */
114 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
115 
116 static unsigned long board1;                           /* ISA addresses, retrieved from rocketport.conf          */
117 static unsigned long board2;
118 static unsigned long board3;
119 static unsigned long board4;
120 static unsigned long controller;
121 static bool support_low_speed;
122 static unsigned long modem1;
123 static unsigned long modem2;
124 static unsigned long modem3;
125 static unsigned long modem4;
126 static unsigned long pc104_1[8];
127 static unsigned long pc104_2[8];
128 static unsigned long pc104_3[8];
129 static unsigned long pc104_4[8];
130 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
131 
132 static int rp_baud_base[NUM_BOARDS];                   /*  Board config info (Someday make a per-board structure)  */
133 static unsigned long rcktpt_io_addr[NUM_BOARDS];
134 static int rcktpt_type[NUM_BOARDS];
135 static int is_PCI[NUM_BOARDS];
136 static rocketModel_t rocketModel[NUM_BOARDS];
137 static int max_board;
138 static const struct tty_port_operations rocket_port_ops;
139 
140 /*
141  * The following arrays define the interrupt bits corresponding to each AIOP.
142  * These bits are different between the ISA and regular PCI boards and the
143  * Universal PCI boards.
144  */
145 
146 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
147         AIOP_INTR_BIT_0,
148         AIOP_INTR_BIT_1,
149         AIOP_INTR_BIT_2,
150         AIOP_INTR_BIT_3
151 };
152 
153 #ifdef CONFIG_PCI
154 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
155         UPCI_AIOP_INTR_BIT_0,
156         UPCI_AIOP_INTR_BIT_1,
157         UPCI_AIOP_INTR_BIT_2,
158         UPCI_AIOP_INTR_BIT_3
159 };
160 #endif
161 
162 static Byte_t RData[RDATASIZE] = {
163         0x00, 0x09, 0xf6, 0x82,
164         0x02, 0x09, 0x86, 0xfb,
165         0x04, 0x09, 0x00, 0x0a,
166         0x06, 0x09, 0x01, 0x0a,
167         0x08, 0x09, 0x8a, 0x13,
168         0x0a, 0x09, 0xc5, 0x11,
169         0x0c, 0x09, 0x86, 0x85,
170         0x0e, 0x09, 0x20, 0x0a,
171         0x10, 0x09, 0x21, 0x0a,
172         0x12, 0x09, 0x41, 0xff,
173         0x14, 0x09, 0x82, 0x00,
174         0x16, 0x09, 0x82, 0x7b,
175         0x18, 0x09, 0x8a, 0x7d,
176         0x1a, 0x09, 0x88, 0x81,
177         0x1c, 0x09, 0x86, 0x7a,
178         0x1e, 0x09, 0x84, 0x81,
179         0x20, 0x09, 0x82, 0x7c,
180         0x22, 0x09, 0x0a, 0x0a
181 };
182 
183 static Byte_t RRegData[RREGDATASIZE] = {
184         0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
185         0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
186         0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
187         0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
188         0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
189         0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
190         0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
191         0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
192         0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
193         0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
194         0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
195         0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
196         0x22, 0x09, 0x0a, 0x0a  /* 30: Rx FIFO Enable */
197 };
198 
199 static CONTROLLER_T sController[CTL_SIZE] = {
200         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
206         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
207          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
208 };
209 
210 static Byte_t sBitMapClrTbl[8] = {
211         0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
212 };
213 
214 static Byte_t sBitMapSetTbl[8] = {
215         0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
216 };
217 
218 static int sClockPrescale = 0x14;
219 
220 /*
221  *  Line number is the ttySIx number (x), the Minor number.  We 
222  *  assign them sequentially, starting at zero.  The following 
223  *  array keeps track of the line number assigned to a given board/aiop/channel.
224  */
225 static unsigned char lineNumbers[MAX_RP_PORTS];
226 static unsigned long nextLineNumber;
227 
228 /*****  RocketPort Static Prototypes   *********/
229 static int __init init_ISA(int i);
230 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
231 static void rp_flush_buffer(struct tty_struct *tty);
232 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
233 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
234 static void rp_start(struct tty_struct *tty);
235 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
236                      int ChanNum);
237 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
238 static void sFlushRxFIFO(CHANNEL_T * ChP);
239 static void sFlushTxFIFO(CHANNEL_T * ChP);
240 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
241 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
242 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
243 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
244 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
245 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
246                            ByteIO_t * AiopIOList, int AiopIOListSize,
247                            int IRQNum, Byte_t Frequency, int PeriodicOnly);
248 static int sReadAiopID(ByteIO_t io);
249 static int sReadAiopNumChan(WordIO_t io);
250 
251 MODULE_AUTHOR("Theodore Ts'o");
252 MODULE_DESCRIPTION("Comtrol RocketPort driver");
253 module_param(board1, ulong, 0);
254 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
255 module_param(board2, ulong, 0);
256 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
257 module_param(board3, ulong, 0);
258 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
259 module_param(board4, ulong, 0);
260 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
261 module_param(controller, ulong, 0);
262 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
263 module_param(support_low_speed, bool, 0);
264 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
265 module_param(modem1, ulong, 0);
266 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
267 module_param(modem2, ulong, 0);
268 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
269 module_param(modem3, ulong, 0);
270 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
271 module_param(modem4, ulong, 0);
272 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
273 module_param_array(pc104_1, ulong, NULL, 0);
274 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
275 module_param_array(pc104_2, ulong, NULL, 0);
276 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
277 module_param_array(pc104_3, ulong, NULL, 0);
278 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
279 module_param_array(pc104_4, ulong, NULL, 0);
280 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
281 
282 static int rp_init(void);
283 static void rp_cleanup_module(void);
284 
285 module_init(rp_init);
286 module_exit(rp_cleanup_module);
287 
288 
289 MODULE_LICENSE("Dual BSD/GPL");
290 
291 /*************************************************************************/
292 /*                     Module code starts here                           */
293 
294 static inline int rocket_paranoia_check(struct r_port *info,
295                                         const char *routine)
296 {
297 #ifdef ROCKET_PARANOIA_CHECK
298         if (!info)
299                 return 1;
300         if (info->magic != RPORT_MAGIC) {
301                 printk(KERN_WARNING "Warning: bad magic number for rocketport "
302                                 "struct in %s\n", routine);
303                 return 1;
304         }
305 #endif
306         return 0;
307 }
308 
309 
310 /*  Serial port receive data function.  Called (from timer poll) when an AIOPIC signals 
311  *  that receive data is present on a serial port.  Pulls data from FIFO, moves it into the 
312  *  tty layer.  
313  */
314 static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
315                 unsigned int ChanStatus)
316 {
317         unsigned int CharNStat;
318         int ToRecv, wRecv, space;
319         unsigned char *cbuf;
320 
321         ToRecv = sGetRxCnt(cp);
322 #ifdef ROCKET_DEBUG_INTR
323         printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
324 #endif
325         if (ToRecv == 0)
326                 return;
327 
328         /*
329          * if status indicates there are errored characters in the
330          * FIFO, then enter status mode (a word in FIFO holds
331          * character and status).
332          */
333         if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
334                 if (!(ChanStatus & STATMODE)) {
335 #ifdef ROCKET_DEBUG_RECEIVE
336                         printk(KERN_INFO "Entering STATMODE...\n");
337 #endif
338                         ChanStatus |= STATMODE;
339                         sEnRxStatusMode(cp);
340                 }
341         }
342 
343         /* 
344          * if we previously entered status mode, then read down the
345          * FIFO one word at a time, pulling apart the character and
346          * the status.  Update error counters depending on status
347          */
348         if (ChanStatus & STATMODE) {
349 #ifdef ROCKET_DEBUG_RECEIVE
350                 printk(KERN_INFO "Ignore %x, read %x...\n",
351                         info->ignore_status_mask, info->read_status_mask);
352 #endif
353                 while (ToRecv) {
354                         char flag;
355 
356                         CharNStat = sInW(sGetTxRxDataIO(cp));
357 #ifdef ROCKET_DEBUG_RECEIVE
358                         printk(KERN_INFO "%x...\n", CharNStat);
359 #endif
360                         if (CharNStat & STMBREAKH)
361                                 CharNStat &= ~(STMFRAMEH | STMPARITYH);
362                         if (CharNStat & info->ignore_status_mask) {
363                                 ToRecv--;
364                                 continue;
365                         }
366                         CharNStat &= info->read_status_mask;
367                         if (CharNStat & STMBREAKH)
368                                 flag = TTY_BREAK;
369                         else if (CharNStat & STMPARITYH)
370                                 flag = TTY_PARITY;
371                         else if (CharNStat & STMFRAMEH)
372                                 flag = TTY_FRAME;
373                         else if (CharNStat & STMRCVROVRH)
374                                 flag = TTY_OVERRUN;
375                         else
376                                 flag = TTY_NORMAL;
377                         tty_insert_flip_char(&info->port, CharNStat & 0xff,
378                                         flag);
379                         ToRecv--;
380                 }
381 
382                 /*
383                  * after we've emptied the FIFO in status mode, turn
384                  * status mode back off
385                  */
386                 if (sGetRxCnt(cp) == 0) {
387 #ifdef ROCKET_DEBUG_RECEIVE
388                         printk(KERN_INFO "Status mode off.\n");
389 #endif
390                         sDisRxStatusMode(cp);
391                 }
392         } else {
393                 /*
394                  * we aren't in status mode, so read down the FIFO two
395                  * characters at time by doing repeated word IO
396                  * transfer.
397                  */
398                 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
399                 if (space < ToRecv) {
400 #ifdef ROCKET_DEBUG_RECEIVE
401                         printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
402 #endif
403                         if (space <= 0)
404                                 return;
405                         ToRecv = space;
406                 }
407                 wRecv = ToRecv >> 1;
408                 if (wRecv)
409                         sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
410                 if (ToRecv & 1)
411                         cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
412         }
413         /*  Push the data up to the tty layer */
414         tty_flip_buffer_push(&info->port);
415 }
416 
417 /*
418  *  Serial port transmit data function.  Called from the timer polling loop as a 
419  *  result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
420  *  to be sent out the serial port.  Data is buffered in rp_table[line].xmit_buf, it is 
421  *  moved to the port's xmit FIFO.  *info is critical data, protected by spinlocks.
422  */
423 static void rp_do_transmit(struct r_port *info)
424 {
425         int c;
426         CHANNEL_t *cp = &info->channel;
427         struct tty_struct *tty;
428         unsigned long flags;
429 
430 #ifdef ROCKET_DEBUG_INTR
431         printk(KERN_DEBUG "%s\n", __func__);
432 #endif
433         if (!info)
434                 return;
435         tty = tty_port_tty_get(&info->port);
436 
437         if (tty == NULL) {
438                 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
439                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
440                 return;
441         }
442 
443         spin_lock_irqsave(&info->slock, flags);
444         info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
445 
446         /*  Loop sending data to FIFO until done or FIFO full */
447         while (1) {
448                 if (tty->stopped)
449                         break;
450                 c = min(info->xmit_fifo_room, info->xmit_cnt);
451                 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
452                 if (c <= 0 || info->xmit_fifo_room <= 0)
453                         break;
454                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
455                 if (c & 1)
456                         sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
457                 info->xmit_tail += c;
458                 info->xmit_tail &= XMIT_BUF_SIZE - 1;
459                 info->xmit_cnt -= c;
460                 info->xmit_fifo_room -= c;
461 #ifdef ROCKET_DEBUG_INTR
462                 printk(KERN_INFO "tx %d chars...\n", c);
463 #endif
464         }
465 
466         if (info->xmit_cnt == 0)
467                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
468 
469         if (info->xmit_cnt < WAKEUP_CHARS) {
470                 tty_wakeup(tty);
471 #ifdef ROCKETPORT_HAVE_POLL_WAIT
472                 wake_up_interruptible(&tty->poll_wait);
473 #endif
474         }
475 
476         spin_unlock_irqrestore(&info->slock, flags);
477         tty_kref_put(tty);
478 
479 #ifdef ROCKET_DEBUG_INTR
480         printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
481                info->xmit_tail, info->xmit_fifo_room);
482 #endif
483 }
484 
485 /*
486  *  Called when a serial port signals it has read data in it's RX FIFO.
487  *  It checks what interrupts are pending and services them, including
488  *  receiving serial data.  
489  */
490 static void rp_handle_port(struct r_port *info)
491 {
492         CHANNEL_t *cp;
493         unsigned int IntMask, ChanStatus;
494 
495         if (!info)
496                 return;
497 
498         if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
499                 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
500                                 "info->flags & NOT_INIT\n");
501                 return;
502         }
503 
504         cp = &info->channel;
505 
506         IntMask = sGetChanIntID(cp) & info->intmask;
507 #ifdef ROCKET_DEBUG_INTR
508         printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
509 #endif
510         ChanStatus = sGetChanStatus(cp);
511         if (IntMask & RXF_TRIG) {       /* Rx FIFO trigger level */
512                 rp_do_receive(info, cp, ChanStatus);
513         }
514         if (IntMask & DELTA_CD) {       /* CD change  */
515 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
516                 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
517                        (ChanStatus & CD_ACT) ? "on" : "off");
518 #endif
519                 if (!(ChanStatus & CD_ACT) && info->cd_status) {
520 #ifdef ROCKET_DEBUG_HANGUP
521                         printk(KERN_INFO "CD drop, calling hangup.\n");
522 #endif
523                         tty_port_tty_hangup(&info->port, false);
524                 }
525                 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
526                 wake_up_interruptible(&info->port.open_wait);
527         }
528 #ifdef ROCKET_DEBUG_INTR
529         if (IntMask & DELTA_CTS) {      /* CTS change */
530                 printk(KERN_INFO "CTS change...\n");
531         }
532         if (IntMask & DELTA_DSR) {      /* DSR change */
533                 printk(KERN_INFO "DSR change...\n");
534         }
535 #endif
536 }
537 
538 /*
539  *  The top level polling routine.  Repeats every 1/100 HZ (10ms).
540  */
541 static void rp_do_poll(unsigned long dummy)
542 {
543         CONTROLLER_t *ctlp;
544         int ctrl, aiop, ch, line;
545         unsigned int xmitmask, i;
546         unsigned int CtlMask;
547         unsigned char AiopMask;
548         Word_t bit;
549 
550         /*  Walk through all the boards (ctrl's) */
551         for (ctrl = 0; ctrl < max_board; ctrl++) {
552                 if (rcktpt_io_addr[ctrl] <= 0)
553                         continue;
554 
555                 /*  Get a ptr to the board's control struct */
556                 ctlp = sCtlNumToCtlPtr(ctrl);
557 
558                 /*  Get the interrupt status from the board */
559 #ifdef CONFIG_PCI
560                 if (ctlp->BusType == isPCI)
561                         CtlMask = sPCIGetControllerIntStatus(ctlp);
562                 else
563 #endif
564                         CtlMask = sGetControllerIntStatus(ctlp);
565 
566                 /*  Check if any AIOP read bits are set */
567                 for (aiop = 0; CtlMask; aiop++) {
568                         bit = ctlp->AiopIntrBits[aiop];
569                         if (CtlMask & bit) {
570                                 CtlMask &= ~bit;
571                                 AiopMask = sGetAiopIntStatus(ctlp, aiop);
572 
573                                 /*  Check if any port read bits are set */
574                                 for (ch = 0; AiopMask;  AiopMask >>= 1, ch++) {
575                                         if (AiopMask & 1) {
576 
577                                                 /*  Get the line number (/dev/ttyRx number). */
578                                                 /*  Read the data from the port. */
579                                                 line = GetLineNumber(ctrl, aiop, ch);
580                                                 rp_handle_port(rp_table[line]);
581                                         }
582                                 }
583                         }
584                 }
585 
586                 xmitmask = xmit_flags[ctrl];
587 
588                 /*
589                  *  xmit_flags contains bit-significant flags, indicating there is data
590                  *  to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port 
591                  *  1, ... (32 total possible).  The variable i has the aiop and ch 
592                  *  numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
593                  */
594                 if (xmitmask) {
595                         for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
596                                 if (xmitmask & (1 << i)) {
597                                         aiop = (i & 0x18) >> 3;
598                                         ch = i & 0x07;
599                                         line = GetLineNumber(ctrl, aiop, ch);
600                                         rp_do_transmit(rp_table[line]);
601                                 }
602                         }
603                 }
604         }
605 
606         /*
607          * Reset the timer so we get called at the next clock tick (10ms).
608          */
609         if (atomic_read(&rp_num_ports_open))
610                 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
611 }
612 
613 /*
614  *  Initializes the r_port structure for a port, as well as enabling the port on 
615  *  the board.  
616  *  Inputs:  board, aiop, chan numbers
617  */
618 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
619 {
620         unsigned rocketMode;
621         struct r_port *info;
622         int line;
623         CONTROLLER_T *ctlp;
624 
625         /*  Get the next available line number */
626         line = SetLineNumber(board, aiop, chan);
627 
628         ctlp = sCtlNumToCtlPtr(board);
629 
630         /*  Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
631         info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
632         if (!info) {
633                 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
634                                 line);
635                 return;
636         }
637 
638         info->magic = RPORT_MAGIC;
639         info->line = line;
640         info->ctlp = ctlp;
641         info->board = board;
642         info->aiop = aiop;
643         info->chan = chan;
644         tty_port_init(&info->port);
645         info->port.ops = &rocket_port_ops;
646         init_completion(&info->close_wait);
647         info->flags &= ~ROCKET_MODE_MASK;
648         switch (pc104[board][line]) {
649         case 422:
650                 info->flags |= ROCKET_MODE_RS422;
651                 break;
652         case 485:
653                 info->flags |= ROCKET_MODE_RS485;
654                 break;
655         case 232:
656         default:
657                 info->flags |= ROCKET_MODE_RS232;
658                 break;
659         }
660 
661         info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
662         if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
663                 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
664                                 board, aiop, chan);
665                 tty_port_destroy(&info->port);
666                 kfree(info);
667                 return;
668         }
669 
670         rocketMode = info->flags & ROCKET_MODE_MASK;
671 
672         if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
673                 sEnRTSToggle(&info->channel);
674         else
675                 sDisRTSToggle(&info->channel);
676 
677         if (ctlp->boardType == ROCKET_TYPE_PC104) {
678                 switch (rocketMode) {
679                 case ROCKET_MODE_RS485:
680                         sSetInterfaceMode(&info->channel, InterfaceModeRS485);
681                         break;
682                 case ROCKET_MODE_RS422:
683                         sSetInterfaceMode(&info->channel, InterfaceModeRS422);
684                         break;
685                 case ROCKET_MODE_RS232:
686                 default:
687                         if (info->flags & ROCKET_RTS_TOGGLE)
688                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
689                         else
690                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
691                         break;
692                 }
693         }
694         spin_lock_init(&info->slock);
695         mutex_init(&info->write_mtx);
696         rp_table[line] = info;
697         tty_port_register_device(&info->port, rocket_driver, line,
698                         pci_dev ? &pci_dev->dev : NULL);
699 }
700 
701 /*
702  *  Configures a rocketport port according to its termio settings.  Called from 
703  *  user mode into the driver (exception handler).  *info CD manipulation is spinlock protected.
704  */
705 static void configure_r_port(struct tty_struct *tty, struct r_port *info,
706                              struct ktermios *old_termios)
707 {
708         unsigned cflag;
709         unsigned long flags;
710         unsigned rocketMode;
711         int bits, baud, divisor;
712         CHANNEL_t *cp;
713         struct ktermios *t = &tty->termios;
714 
715         cp = &info->channel;
716         cflag = t->c_cflag;
717 
718         /* Byte size and parity */
719         if ((cflag & CSIZE) == CS8) {
720                 sSetData8(cp);
721                 bits = 10;
722         } else {
723                 sSetData7(cp);
724                 bits = 9;
725         }
726         if (cflag & CSTOPB) {
727                 sSetStop2(cp);
728                 bits++;
729         } else {
730                 sSetStop1(cp);
731         }
732 
733         if (cflag & PARENB) {
734                 sEnParity(cp);
735                 bits++;
736                 if (cflag & PARODD) {
737                         sSetOddParity(cp);
738                 } else {
739                         sSetEvenParity(cp);
740                 }
741         } else {
742                 sDisParity(cp);
743         }
744 
745         /* baud rate */
746         baud = tty_get_baud_rate(tty);
747         if (!baud)
748                 baud = 9600;
749         divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
750         if ((divisor >= 8192 || divisor < 0) && old_termios) {
751                 baud = tty_termios_baud_rate(old_termios);
752                 if (!baud)
753                         baud = 9600;
754                 divisor = (rp_baud_base[info->board] / baud) - 1;
755         }
756         if (divisor >= 8192 || divisor < 0) {
757                 baud = 9600;
758                 divisor = (rp_baud_base[info->board] / baud) - 1;
759         }
760         info->cps = baud / bits;
761         sSetBaud(cp, divisor);
762 
763         /* FIXME: Should really back compute a baud rate from the divisor */
764         tty_encode_baud_rate(tty, baud, baud);
765 
766         if (cflag & CRTSCTS) {
767                 info->intmask |= DELTA_CTS;
768                 sEnCTSFlowCtl(cp);
769         } else {
770                 info->intmask &= ~DELTA_CTS;
771                 sDisCTSFlowCtl(cp);
772         }
773         if (cflag & CLOCAL) {
774                 info->intmask &= ~DELTA_CD;
775         } else {
776                 spin_lock_irqsave(&info->slock, flags);
777                 if (sGetChanStatus(cp) & CD_ACT)
778                         info->cd_status = 1;
779                 else
780                         info->cd_status = 0;
781                 info->intmask |= DELTA_CD;
782                 spin_unlock_irqrestore(&info->slock, flags);
783         }
784 
785         /*
786          * Handle software flow control in the board
787          */
788 #ifdef ROCKET_SOFT_FLOW
789         if (I_IXON(tty)) {
790                 sEnTxSoftFlowCtl(cp);
791                 if (I_IXANY(tty)) {
792                         sEnIXANY(cp);
793                 } else {
794                         sDisIXANY(cp);
795                 }
796                 sSetTxXONChar(cp, START_CHAR(tty));
797                 sSetTxXOFFChar(cp, STOP_CHAR(tty));
798         } else {
799                 sDisTxSoftFlowCtl(cp);
800                 sDisIXANY(cp);
801                 sClrTxXOFF(cp);
802         }
803 #endif
804 
805         /*
806          * Set up ignore/read mask words
807          */
808         info->read_status_mask = STMRCVROVRH | 0xFF;
809         if (I_INPCK(tty))
810                 info->read_status_mask |= STMFRAMEH | STMPARITYH;
811         if (I_BRKINT(tty) || I_PARMRK(tty))
812                 info->read_status_mask |= STMBREAKH;
813 
814         /*
815          * Characters to ignore
816          */
817         info->ignore_status_mask = 0;
818         if (I_IGNPAR(tty))
819                 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
820         if (I_IGNBRK(tty)) {
821                 info->ignore_status_mask |= STMBREAKH;
822                 /*
823                  * If we're ignoring parity and break indicators,
824                  * ignore overruns too.  (For real raw support).
825                  */
826                 if (I_IGNPAR(tty))
827                         info->ignore_status_mask |= STMRCVROVRH;
828         }
829 
830         rocketMode = info->flags & ROCKET_MODE_MASK;
831 
832         if ((info->flags & ROCKET_RTS_TOGGLE)
833             || (rocketMode == ROCKET_MODE_RS485))
834                 sEnRTSToggle(cp);
835         else
836                 sDisRTSToggle(cp);
837 
838         sSetRTS(&info->channel);
839 
840         if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
841                 switch (rocketMode) {
842                 case ROCKET_MODE_RS485:
843                         sSetInterfaceMode(cp, InterfaceModeRS485);
844                         break;
845                 case ROCKET_MODE_RS422:
846                         sSetInterfaceMode(cp, InterfaceModeRS422);
847                         break;
848                 case ROCKET_MODE_RS232:
849                 default:
850                         if (info->flags & ROCKET_RTS_TOGGLE)
851                                 sSetInterfaceMode(cp, InterfaceModeRS232T);
852                         else
853                                 sSetInterfaceMode(cp, InterfaceModeRS232);
854                         break;
855                 }
856         }
857 }
858 
859 static int carrier_raised(struct tty_port *port)
860 {
861         struct r_port *info = container_of(port, struct r_port, port);
862         return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
863 }
864 
865 static void dtr_rts(struct tty_port *port, int on)
866 {
867         struct r_port *info = container_of(port, struct r_port, port);
868         if (on) {
869                 sSetDTR(&info->channel);
870                 sSetRTS(&info->channel);
871         } else {
872                 sClrDTR(&info->channel);
873                 sClrRTS(&info->channel);
874         }
875 }
876 
877 /*
878  *  Exception handler that opens a serial port.  Creates xmit_buf storage, fills in 
879  *  port's r_port struct.  Initializes the port hardware.  
880  */
881 static int rp_open(struct tty_struct *tty, struct file *filp)
882 {
883         struct r_port *info;
884         struct tty_port *port;
885         int retval;
886         CHANNEL_t *cp;
887         unsigned long page;
888 
889         info = rp_table[tty->index];
890         if (info == NULL)
891                 return -ENXIO;
892         port = &info->port;
893         
894         page = __get_free_page(GFP_KERNEL);
895         if (!page)
896                 return -ENOMEM;
897 
898         /*
899          * We must not sleep from here until the port is marked fully in use.
900          */
901         if (info->xmit_buf)
902                 free_page(page);
903         else
904                 info->xmit_buf = (unsigned char *) page;
905 
906         tty->driver_data = info;
907         tty_port_tty_set(port, tty);
908 
909         if (port->count++ == 0) {
910                 atomic_inc(&rp_num_ports_open);
911 
912 #ifdef ROCKET_DEBUG_OPEN
913                 printk(KERN_INFO "rocket mod++ = %d...\n",
914                                 atomic_read(&rp_num_ports_open));
915 #endif
916         }
917 #ifdef ROCKET_DEBUG_OPEN
918         printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
919 #endif
920 
921         /*
922          * Info->count is now 1; so it's safe to sleep now.
923          */
924         if (!test_bit(ASYNCB_INITIALIZED, &port->flags)) {
925                 cp = &info->channel;
926                 sSetRxTrigger(cp, TRIG_1);
927                 if (sGetChanStatus(cp) & CD_ACT)
928                         info->cd_status = 1;
929                 else
930                         info->cd_status = 0;
931                 sDisRxStatusMode(cp);
932                 sFlushRxFIFO(cp);
933                 sFlushTxFIFO(cp);
934 
935                 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
936                 sSetRxTrigger(cp, TRIG_1);
937 
938                 sGetChanStatus(cp);
939                 sDisRxStatusMode(cp);
940                 sClrTxXOFF(cp);
941 
942                 sDisCTSFlowCtl(cp);
943                 sDisTxSoftFlowCtl(cp);
944 
945                 sEnRxFIFO(cp);
946                 sEnTransmit(cp);
947 
948                 set_bit(ASYNCB_INITIALIZED, &info->port.flags);
949 
950                 /*
951                  * Set up the tty->alt_speed kludge
952                  */
953                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
954                         tty->alt_speed = 57600;
955                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
956                         tty->alt_speed = 115200;
957                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
958                         tty->alt_speed = 230400;
959                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
960                         tty->alt_speed = 460800;
961 
962                 configure_r_port(tty, info, NULL);
963                 if (tty->termios.c_cflag & CBAUD) {
964                         sSetDTR(cp);
965                         sSetRTS(cp);
966                 }
967         }
968         /*  Starts (or resets) the maint polling loop */
969         mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
970 
971         retval = tty_port_block_til_ready(port, tty, filp);
972         if (retval) {
973 #ifdef ROCKET_DEBUG_OPEN
974                 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
975 #endif
976                 return retval;
977         }
978         return 0;
979 }
980 
981 /*
982  *  Exception handler that closes a serial port. info->port.count is considered critical.
983  */
984 static void rp_close(struct tty_struct *tty, struct file *filp)
985 {
986         struct r_port *info = tty->driver_data;
987         struct tty_port *port = &info->port;
988         int timeout;
989         CHANNEL_t *cp;
990         
991         if (rocket_paranoia_check(info, "rp_close"))
992                 return;
993 
994 #ifdef ROCKET_DEBUG_OPEN
995         printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
996 #endif
997 
998         if (tty_port_close_start(port, tty, filp) == 0)
999                 return;
1000 
1001         mutex_lock(&port->mutex);
1002         cp = &info->channel;
1003         /*
1004          * Before we drop DTR, make sure the UART transmitter
1005          * has completely drained; this is especially
1006          * important if there is a transmit FIFO!
1007          */
1008         timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1009         if (timeout == 0)
1010                 timeout = 1;
1011         rp_wait_until_sent(tty, timeout);
1012         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1013 
1014         sDisTransmit(cp);
1015         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1016         sDisCTSFlowCtl(cp);
1017         sDisTxSoftFlowCtl(cp);
1018         sClrTxXOFF(cp);
1019         sFlushRxFIFO(cp);
1020         sFlushTxFIFO(cp);
1021         sClrRTS(cp);
1022         if (C_HUPCL(tty))
1023                 sClrDTR(cp);
1024 
1025         rp_flush_buffer(tty);
1026                 
1027         tty_ldisc_flush(tty);
1028 
1029         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1030 
1031         /* We can't yet use tty_port_close_end as the buffer handling in this
1032            driver is a bit different to the usual */
1033 
1034         if (port->blocked_open) {
1035                 if (port->close_delay) {
1036                         msleep_interruptible(jiffies_to_msecs(port->close_delay));
1037                 }
1038                 wake_up_interruptible(&port->open_wait);
1039         } else {
1040                 if (info->xmit_buf) {
1041                         free_page((unsigned long) info->xmit_buf);
1042                         info->xmit_buf = NULL;
1043                 }
1044         }
1045         spin_lock_irq(&port->lock);
1046         info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_CLOSING | ASYNC_NORMAL_ACTIVE);
1047         tty->closing = 0;
1048         spin_unlock_irq(&port->lock);
1049         mutex_unlock(&port->mutex);
1050         tty_port_tty_set(port, NULL);
1051 
1052         complete_all(&info->close_wait);
1053         atomic_dec(&rp_num_ports_open);
1054 
1055 #ifdef ROCKET_DEBUG_OPEN
1056         printk(KERN_INFO "rocket mod-- = %d...\n",
1057                         atomic_read(&rp_num_ports_open));
1058         printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1059 #endif
1060 
1061 }
1062 
1063 static void rp_set_termios(struct tty_struct *tty,
1064                            struct ktermios *old_termios)
1065 {
1066         struct r_port *info = tty->driver_data;
1067         CHANNEL_t *cp;
1068         unsigned cflag;
1069 
1070         if (rocket_paranoia_check(info, "rp_set_termios"))
1071                 return;
1072 
1073         cflag = tty->termios.c_cflag;
1074 
1075         /*
1076          * This driver doesn't support CS5 or CS6
1077          */
1078         if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1079                 tty->termios.c_cflag =
1080                     ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1081         /* Or CMSPAR */
1082         tty->termios.c_cflag &= ~CMSPAR;
1083 
1084         configure_r_port(tty, info, old_termios);
1085 
1086         cp = &info->channel;
1087 
1088         /* Handle transition to B0 status */
1089         if ((old_termios->c_cflag & CBAUD) && !(tty->termios.c_cflag & CBAUD)) {
1090                 sClrDTR(cp);
1091                 sClrRTS(cp);
1092         }
1093 
1094         /* Handle transition away from B0 status */
1095         if (!(old_termios->c_cflag & CBAUD) && (tty->termios.c_cflag & CBAUD)) {
1096                 sSetRTS(cp);
1097                 sSetDTR(cp);
1098         }
1099 
1100         if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios.c_cflag & CRTSCTS))
1101                 rp_start(tty);
1102 }
1103 
1104 static int rp_break(struct tty_struct *tty, int break_state)
1105 {
1106         struct r_port *info = tty->driver_data;
1107         unsigned long flags;
1108 
1109         if (rocket_paranoia_check(info, "rp_break"))
1110                 return -EINVAL;
1111 
1112         spin_lock_irqsave(&info->slock, flags);
1113         if (break_state == -1)
1114                 sSendBreak(&info->channel);
1115         else
1116                 sClrBreak(&info->channel);
1117         spin_unlock_irqrestore(&info->slock, flags);
1118         return 0;
1119 }
1120 
1121 /*
1122  * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1123  * the UPCI boards was added, it was decided to make this a function because
1124  * the macro was getting too complicated. All cases except the first one
1125  * (UPCIRingInd) are taken directly from the original macro.
1126  */
1127 static int sGetChanRI(CHANNEL_T * ChP)
1128 {
1129         CONTROLLER_t *CtlP = ChP->CtlP;
1130         int ChanNum = ChP->ChanNum;
1131         int RingInd = 0;
1132 
1133         if (CtlP->UPCIRingInd)
1134                 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1135         else if (CtlP->AltChanRingIndicator)
1136                 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1137         else if (CtlP->boardType == ROCKET_TYPE_PC104)
1138                 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1139 
1140         return RingInd;
1141 }
1142 
1143 /********************************************************************************************/
1144 /*  Here are the routines used by rp_ioctl.  These are all called from exception handlers.  */
1145 
1146 /*
1147  *  Returns the state of the serial modem control lines.  These next 2 functions 
1148  *  are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1149  */
1150 static int rp_tiocmget(struct tty_struct *tty)
1151 {
1152         struct r_port *info = tty->driver_data;
1153         unsigned int control, result, ChanStatus;
1154 
1155         ChanStatus = sGetChanStatusLo(&info->channel);
1156         control = info->channel.TxControl[3];
1157         result = ((control & SET_RTS) ? TIOCM_RTS : 0) | 
1158                 ((control & SET_DTR) ?  TIOCM_DTR : 0) |
1159                 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1160                 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1161                 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1162                 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1163 
1164         return result;
1165 }
1166 
1167 /* 
1168  *  Sets the modem control lines
1169  */
1170 static int rp_tiocmset(struct tty_struct *tty,
1171                                 unsigned int set, unsigned int clear)
1172 {
1173         struct r_port *info = tty->driver_data;
1174 
1175         if (set & TIOCM_RTS)
1176                 info->channel.TxControl[3] |= SET_RTS;
1177         if (set & TIOCM_DTR)
1178                 info->channel.TxControl[3] |= SET_DTR;
1179         if (clear & TIOCM_RTS)
1180                 info->channel.TxControl[3] &= ~SET_RTS;
1181         if (clear & TIOCM_DTR)
1182                 info->channel.TxControl[3] &= ~SET_DTR;
1183 
1184         out32(info->channel.IndexAddr, info->channel.TxControl);
1185         return 0;
1186 }
1187 
1188 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1189 {
1190         struct rocket_config tmp;
1191 
1192         if (!retinfo)
1193                 return -EFAULT;
1194         memset(&tmp, 0, sizeof (tmp));
1195         mutex_lock(&info->port.mutex);
1196         tmp.line = info->line;
1197         tmp.flags = info->flags;
1198         tmp.close_delay = info->port.close_delay;
1199         tmp.closing_wait = info->port.closing_wait;
1200         tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1201         mutex_unlock(&info->port.mutex);
1202 
1203         if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1204                 return -EFAULT;
1205         return 0;
1206 }
1207 
1208 static int set_config(struct tty_struct *tty, struct r_port *info,
1209                                         struct rocket_config __user *new_info)
1210 {
1211         struct rocket_config new_serial;
1212 
1213         if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1214                 return -EFAULT;
1215 
1216         mutex_lock(&info->port.mutex);
1217         if (!capable(CAP_SYS_ADMIN))
1218         {
1219                 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1220                         mutex_unlock(&info->port.mutex);
1221                         return -EPERM;
1222                 }
1223                 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1224                 configure_r_port(tty, info, NULL);
1225                 mutex_unlock(&info->port.mutex);
1226                 return 0;
1227         }
1228 
1229         info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1230         info->port.close_delay = new_serial.close_delay;
1231         info->port.closing_wait = new_serial.closing_wait;
1232 
1233         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1234                 tty->alt_speed = 57600;
1235         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1236                 tty->alt_speed = 115200;
1237         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1238                 tty->alt_speed = 230400;
1239         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1240                 tty->alt_speed = 460800;
1241         mutex_unlock(&info->port.mutex);
1242 
1243         configure_r_port(tty, info, NULL);
1244         return 0;
1245 }
1246 
1247 /*
1248  *  This function fills in a rocket_ports struct with information
1249  *  about what boards/ports are in the system.  This info is passed
1250  *  to user space.  See setrocket.c where the info is used to create
1251  *  the /dev/ttyRx ports.
1252  */
1253 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1254 {
1255         struct rocket_ports tmp;
1256         int board;
1257 
1258         if (!retports)
1259                 return -EFAULT;
1260         memset(&tmp, 0, sizeof (tmp));
1261         tmp.tty_major = rocket_driver->major;
1262 
1263         for (board = 0; board < 4; board++) {
1264                 tmp.rocketModel[board].model = rocketModel[board].model;
1265                 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1266                 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1267                 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1268                 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1269         }
1270         if (copy_to_user(retports, &tmp, sizeof (*retports)))
1271                 return -EFAULT;
1272         return 0;
1273 }
1274 
1275 static int reset_rm2(struct r_port *info, void __user *arg)
1276 {
1277         int reset;
1278 
1279         if (!capable(CAP_SYS_ADMIN))
1280                 return -EPERM;
1281 
1282         if (copy_from_user(&reset, arg, sizeof (int)))
1283                 return -EFAULT;
1284         if (reset)
1285                 reset = 1;
1286 
1287         if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1288             rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1289                 return -EINVAL;
1290 
1291         if (info->ctlp->BusType == isISA)
1292                 sModemReset(info->ctlp, info->chan, reset);
1293         else
1294                 sPCIModemReset(info->ctlp, info->chan, reset);
1295 
1296         return 0;
1297 }
1298 
1299 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1300 {
1301         if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1302                 return -EFAULT;
1303         return 0;
1304 }
1305 
1306 /*  IOCTL call handler into the driver */
1307 static int rp_ioctl(struct tty_struct *tty,
1308                     unsigned int cmd, unsigned long arg)
1309 {
1310         struct r_port *info = tty->driver_data;
1311         void __user *argp = (void __user *)arg;
1312         int ret = 0;
1313 
1314         if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1315                 return -ENXIO;
1316 
1317         switch (cmd) {
1318         case RCKP_GET_STRUCT:
1319                 if (copy_to_user(argp, info, sizeof (struct r_port)))
1320                         ret = -EFAULT;
1321                 break;
1322         case RCKP_GET_CONFIG:
1323                 ret = get_config(info, argp);
1324                 break;
1325         case RCKP_SET_CONFIG:
1326                 ret = set_config(tty, info, argp);
1327                 break;
1328         case RCKP_GET_PORTS:
1329                 ret = get_ports(info, argp);
1330                 break;
1331         case RCKP_RESET_RM2:
1332                 ret = reset_rm2(info, argp);
1333                 break;
1334         case RCKP_GET_VERSION:
1335                 ret = get_version(info, argp);
1336                 break;
1337         default:
1338                 ret = -ENOIOCTLCMD;
1339         }
1340         return ret;
1341 }
1342 
1343 static void rp_send_xchar(struct tty_struct *tty, char ch)
1344 {
1345         struct r_port *info = tty->driver_data;
1346         CHANNEL_t *cp;
1347 
1348         if (rocket_paranoia_check(info, "rp_send_xchar"))
1349                 return;
1350 
1351         cp = &info->channel;
1352         if (sGetTxCnt(cp))
1353                 sWriteTxPrioByte(cp, ch);
1354         else
1355                 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1356 }
1357 
1358 static void rp_throttle(struct tty_struct *tty)
1359 {
1360         struct r_port *info = tty->driver_data;
1361 
1362 #ifdef ROCKET_DEBUG_THROTTLE
1363         printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1364                tty->ldisc.chars_in_buffer(tty));
1365 #endif
1366 
1367         if (rocket_paranoia_check(info, "rp_throttle"))
1368                 return;
1369 
1370         if (I_IXOFF(tty))
1371                 rp_send_xchar(tty, STOP_CHAR(tty));
1372 
1373         sClrRTS(&info->channel);
1374 }
1375 
1376 static void rp_unthrottle(struct tty_struct *tty)
1377 {
1378         struct r_port *info = tty->driver_data;
1379 #ifdef ROCKET_DEBUG_THROTTLE
1380         printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1381                tty->ldisc.chars_in_buffer(tty));
1382 #endif
1383 
1384         if (rocket_paranoia_check(info, "rp_unthrottle"))
1385                 return;
1386 
1387         if (I_IXOFF(tty))
1388                 rp_send_xchar(tty, START_CHAR(tty));
1389 
1390         sSetRTS(&info->channel);
1391 }
1392 
1393 /*
1394  * ------------------------------------------------------------
1395  * rp_stop() and rp_start()
1396  *
1397  * This routines are called before setting or resetting tty->stopped.
1398  * They enable or disable transmitter interrupts, as necessary.
1399  * ------------------------------------------------------------
1400  */
1401 static void rp_stop(struct tty_struct *tty)
1402 {
1403         struct r_port *info = tty->driver_data;
1404 
1405 #ifdef ROCKET_DEBUG_FLOW
1406         printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1407                info->xmit_cnt, info->xmit_fifo_room);
1408 #endif
1409 
1410         if (rocket_paranoia_check(info, "rp_stop"))
1411                 return;
1412 
1413         if (sGetTxCnt(&info->channel))
1414                 sDisTransmit(&info->channel);
1415 }
1416 
1417 static void rp_start(struct tty_struct *tty)
1418 {
1419         struct r_port *info = tty->driver_data;
1420 
1421 #ifdef ROCKET_DEBUG_FLOW
1422         printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1423                info->xmit_cnt, info->xmit_fifo_room);
1424 #endif
1425 
1426         if (rocket_paranoia_check(info, "rp_stop"))
1427                 return;
1428 
1429         sEnTransmit(&info->channel);
1430         set_bit((info->aiop * 8) + info->chan,
1431                 (void *) &xmit_flags[info->board]);
1432 }
1433 
1434 /*
1435  * rp_wait_until_sent() --- wait until the transmitter is empty
1436  */
1437 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1438 {
1439         struct r_port *info = tty->driver_data;
1440         CHANNEL_t *cp;
1441         unsigned long orig_jiffies;
1442         int check_time, exit_time;
1443         int txcnt;
1444 
1445         if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1446                 return;
1447 
1448         cp = &info->channel;
1449 
1450         orig_jiffies = jiffies;
1451 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1452         printk(KERN_INFO "In %s(%d) (jiff=%lu)...\n", __func__, timeout,
1453                jiffies);
1454         printk(KERN_INFO "cps=%d...\n", info->cps);
1455 #endif
1456         while (1) {
1457                 txcnt = sGetTxCnt(cp);
1458                 if (!txcnt) {
1459                         if (sGetChanStatusLo(cp) & TXSHRMT)
1460                                 break;
1461                         check_time = (HZ / info->cps) / 5;
1462                 } else {
1463                         check_time = HZ * txcnt / info->cps;
1464                 }
1465                 if (timeout) {
1466                         exit_time = orig_jiffies + timeout - jiffies;
1467                         if (exit_time <= 0)
1468                                 break;
1469                         if (exit_time < check_time)
1470                                 check_time = exit_time;
1471                 }
1472                 if (check_time == 0)
1473                         check_time = 1;
1474 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1475                 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1476                                 jiffies, check_time);
1477 #endif
1478                 msleep_interruptible(jiffies_to_msecs(check_time));
1479                 if (signal_pending(current))
1480                         break;
1481         }
1482         __set_current_state(TASK_RUNNING);
1483 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1484         printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1485 #endif
1486 }
1487 
1488 /*
1489  * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1490  */
1491 static void rp_hangup(struct tty_struct *tty)
1492 {
1493         CHANNEL_t *cp;
1494         struct r_port *info = tty->driver_data;
1495         unsigned long flags;
1496 
1497         if (rocket_paranoia_check(info, "rp_hangup"))
1498                 return;
1499 
1500 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1501         printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1502 #endif
1503         rp_flush_buffer(tty);
1504         spin_lock_irqsave(&info->port.lock, flags);
1505         if (info->port.count)
1506                 atomic_dec(&rp_num_ports_open);
1507         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1508         spin_unlock_irqrestore(&info->port.lock, flags);
1509 
1510         tty_port_hangup(&info->port);
1511 
1512         cp = &info->channel;
1513         sDisRxFIFO(cp);
1514         sDisTransmit(cp);
1515         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1516         sDisCTSFlowCtl(cp);
1517         sDisTxSoftFlowCtl(cp);
1518         sClrTxXOFF(cp);
1519         clear_bit(ASYNCB_INITIALIZED, &info->port.flags);
1520 
1521         wake_up_interruptible(&info->port.open_wait);
1522 }
1523 
1524 /*
1525  *  Exception handler - write char routine.  The RocketPort driver uses a
1526  *  double-buffering strategy, with the twist that if the in-memory CPU
1527  *  buffer is empty, and there's space in the transmit FIFO, the
1528  *  writing routines will write directly to transmit FIFO.
1529  *  Write buffer and counters protected by spinlocks
1530  */
1531 static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1532 {
1533         struct r_port *info = tty->driver_data;
1534         CHANNEL_t *cp;
1535         unsigned long flags;
1536 
1537         if (rocket_paranoia_check(info, "rp_put_char"))
1538                 return 0;
1539 
1540         /*
1541          * Grab the port write mutex, locking out other processes that try to
1542          * write to this port
1543          */
1544         mutex_lock(&info->write_mtx);
1545 
1546 #ifdef ROCKET_DEBUG_WRITE
1547         printk(KERN_INFO "rp_put_char %c...\n", ch);
1548 #endif
1549 
1550         spin_lock_irqsave(&info->slock, flags);
1551         cp = &info->channel;
1552 
1553         if (!tty->stopped && info->xmit_fifo_room == 0)
1554                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1555 
1556         if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1557                 info->xmit_buf[info->xmit_head++] = ch;
1558                 info->xmit_head &= XMIT_BUF_SIZE - 1;
1559                 info->xmit_cnt++;
1560                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1561         } else {
1562                 sOutB(sGetTxRxDataIO(cp), ch);
1563                 info->xmit_fifo_room--;
1564         }
1565         spin_unlock_irqrestore(&info->slock, flags);
1566         mutex_unlock(&info->write_mtx);
1567         return 1;
1568 }
1569 
1570 /*
1571  *  Exception handler - write routine, called when user app writes to the device.
1572  *  A per port write mutex is used to protect from another process writing to
1573  *  this port at the same time.  This other process could be running on the other CPU
1574  *  or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out). 
1575  *  Spinlocks protect the info xmit members.
1576  */
1577 static int rp_write(struct tty_struct *tty,
1578                     const unsigned char *buf, int count)
1579 {
1580         struct r_port *info = tty->driver_data;
1581         CHANNEL_t *cp;
1582         const unsigned char *b;
1583         int c, retval = 0;
1584         unsigned long flags;
1585 
1586         if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1587                 return 0;
1588 
1589         if (mutex_lock_interruptible(&info->write_mtx))
1590                 return -ERESTARTSYS;
1591 
1592 #ifdef ROCKET_DEBUG_WRITE
1593         printk(KERN_INFO "rp_write %d chars...\n", count);
1594 #endif
1595         cp = &info->channel;
1596 
1597         if (!tty->stopped && info->xmit_fifo_room < count)
1598                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1599 
1600         /*
1601          *  If the write queue for the port is empty, and there is FIFO space, stuff bytes 
1602          *  into FIFO.  Use the write queue for temp storage.
1603          */
1604         if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1605                 c = min(count, info->xmit_fifo_room);
1606                 b = buf;
1607 
1608                 /*  Push data into FIFO, 2 bytes at a time */
1609                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1610 
1611                 /*  If there is a byte remaining, write it */
1612                 if (c & 1)
1613                         sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1614 
1615                 retval += c;
1616                 buf += c;
1617                 count -= c;
1618 
1619                 spin_lock_irqsave(&info->slock, flags);
1620                 info->xmit_fifo_room -= c;
1621                 spin_unlock_irqrestore(&info->slock, flags);
1622         }
1623 
1624         /* If count is zero, we wrote it all and are done */
1625         if (!count)
1626                 goto end;
1627 
1628         /*  Write remaining data into the port's xmit_buf */
1629         while (1) {
1630                 /* Hung up ? */
1631                 if (!test_bit(ASYNCB_NORMAL_ACTIVE, &info->port.flags))
1632                         goto end;
1633                 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1634                 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1635                 if (c <= 0)
1636                         break;
1637 
1638                 b = buf;
1639                 memcpy(info->xmit_buf + info->xmit_head, b, c);
1640 
1641                 spin_lock_irqsave(&info->slock, flags);
1642                 info->xmit_head =
1643                     (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1644                 info->xmit_cnt += c;
1645                 spin_unlock_irqrestore(&info->slock, flags);
1646 
1647                 buf += c;
1648                 count -= c;
1649                 retval += c;
1650         }
1651 
1652         if ((retval > 0) && !tty->stopped)
1653                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1654         
1655 end:
1656         if (info->xmit_cnt < WAKEUP_CHARS) {
1657                 tty_wakeup(tty);
1658 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1659                 wake_up_interruptible(&tty->poll_wait);
1660 #endif
1661         }
1662         mutex_unlock(&info->write_mtx);
1663         return retval;
1664 }
1665 
1666 /*
1667  * Return the number of characters that can be sent.  We estimate
1668  * only using the in-memory transmit buffer only, and ignore the
1669  * potential space in the transmit FIFO.
1670  */
1671 static int rp_write_room(struct tty_struct *tty)
1672 {
1673         struct r_port *info = tty->driver_data;
1674         int ret;
1675 
1676         if (rocket_paranoia_check(info, "rp_write_room"))
1677                 return 0;
1678 
1679         ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1680         if (ret < 0)
1681                 ret = 0;
1682 #ifdef ROCKET_DEBUG_WRITE
1683         printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1684 #endif
1685         return ret;
1686 }
1687 
1688 /*
1689  * Return the number of characters in the buffer.  Again, this only
1690  * counts those characters in the in-memory transmit buffer.
1691  */
1692 static int rp_chars_in_buffer(struct tty_struct *tty)
1693 {
1694         struct r_port *info = tty->driver_data;
1695 
1696         if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1697                 return 0;
1698 
1699 #ifdef ROCKET_DEBUG_WRITE
1700         printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1701 #endif
1702         return info->xmit_cnt;
1703 }
1704 
1705 /*
1706  *  Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1707  *  r_port struct for the port.  Note that spinlock are used to protect info members,
1708  *  do not call this function if the spinlock is already held.
1709  */
1710 static void rp_flush_buffer(struct tty_struct *tty)
1711 {
1712         struct r_port *info = tty->driver_data;
1713         CHANNEL_t *cp;
1714         unsigned long flags;
1715 
1716         if (rocket_paranoia_check(info, "rp_flush_buffer"))
1717                 return;
1718 
1719         spin_lock_irqsave(&info->slock, flags);
1720         info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1721         spin_unlock_irqrestore(&info->slock, flags);
1722 
1723 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1724         wake_up_interruptible(&tty->poll_wait);
1725 #endif
1726         tty_wakeup(tty);
1727 
1728         cp = &info->channel;
1729         sFlushTxFIFO(cp);
1730 }
1731 
1732 #ifdef CONFIG_PCI
1733 
1734 static const struct pci_device_id rocket_pci_ids[] = {
1735         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
1736         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
1737         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
1738         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
1739         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
1740         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
1741         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
1742         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
1743         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
1744         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
1745         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
1746         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
1747         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
1748         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
1749         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
1750         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
1751         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
1752         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
1753         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
1754         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
1755         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
1756         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
1757         { }
1758 };
1759 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1760 
1761 /*  Resets the speaker controller on RocketModem II and III devices */
1762 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
1763 {
1764         ByteIO_t addr;
1765 
1766         /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
1767         if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
1768                 addr = CtlP->AiopIO[0] + 0x4F;
1769                 sOutB(addr, 0);
1770         }
1771 
1772         /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
1773         if ((model == MODEL_UPCI_RM3_8PORT)
1774             || (model == MODEL_UPCI_RM3_4PORT)) {
1775                 addr = CtlP->AiopIO[0] + 0x88;
1776                 sOutB(addr, 0);
1777         }
1778 }
1779 
1780 /***************************************************************************
1781 Function: sPCIInitController
1782 Purpose:  Initialization of controller global registers and controller
1783           structure.
1784 Call:     sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
1785                           IRQNum,Frequency,PeriodicOnly)
1786           CONTROLLER_T *CtlP; Ptr to controller structure
1787           int CtlNum; Controller number
1788           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
1789              This list must be in the order the AIOPs will be found on the
1790              controller.  Once an AIOP in the list is not found, it is
1791              assumed that there are no more AIOPs on the controller.
1792           int AiopIOListSize; Number of addresses in AiopIOList
1793           int IRQNum; Interrupt Request number.  Can be any of the following:
1794                          0: Disable global interrupts
1795                          3: IRQ 3
1796                          4: IRQ 4
1797                          5: IRQ 5
1798                          9: IRQ 9
1799                          10: IRQ 10
1800                          11: IRQ 11
1801                          12: IRQ 12
1802                          15: IRQ 15
1803           Byte_t Frequency: A flag identifying the frequency
1804                    of the periodic interrupt, can be any one of the following:
1805                       FREQ_DIS - periodic interrupt disabled
1806                       FREQ_137HZ - 137 Hertz
1807                       FREQ_69HZ - 69 Hertz
1808                       FREQ_34HZ - 34 Hertz
1809                       FREQ_17HZ - 17 Hertz
1810                       FREQ_9HZ - 9 Hertz
1811                       FREQ_4HZ - 4 Hertz
1812                    If IRQNum is set to 0 the Frequency parameter is
1813                    overidden, it is forced to a value of FREQ_DIS.
1814           int PeriodicOnly: 1 if all interrupts except the periodic
1815                                interrupt are to be blocked.
1816                             0 is both the periodic interrupt and
1817                                other channel interrupts are allowed.
1818                             If IRQNum is set to 0 the PeriodicOnly parameter is
1819                                overidden, it is forced to a value of 0.
1820 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
1821                initialization failed.
1822 
1823 Comments:
1824           If periodic interrupts are to be disabled but AIOP interrupts
1825           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1826 
1827           If interrupts are to be completely disabled set IRQNum to 0.
1828 
1829           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1830           invalid combination.
1831 
1832           This function performs initialization of global interrupt modes,
1833           but it does not actually enable global interrupts.  To enable
1834           and disable global interrupts use functions sEnGlobalInt() and
1835           sDisGlobalInt().  Enabling of global interrupts is normally not
1836           done until all other initializations are complete.
1837 
1838           Even if interrupts are globally enabled, they must also be
1839           individually enabled for each channel that is to generate
1840           interrupts.
1841 
1842 Warnings: No range checking on any of the parameters is done.
1843 
1844           No context switches are allowed while executing this function.
1845 
1846           After this function all AIOPs on the controller are disabled,
1847           they can be enabled with sEnAiop().
1848 */
1849 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
1850                               ByteIO_t * AiopIOList, int AiopIOListSize,
1851                               WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
1852                               int PeriodicOnly, int altChanRingIndicator,
1853                               int UPCIRingInd)
1854 {
1855         int i;
1856         ByteIO_t io;
1857 
1858         CtlP->AltChanRingIndicator = altChanRingIndicator;
1859         CtlP->UPCIRingInd = UPCIRingInd;
1860         CtlP->CtlNum = CtlNum;
1861         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
1862         CtlP->BusType = isPCI;  /* controller release 1 */
1863 
1864         if (ConfigIO) {
1865                 CtlP->isUPCI = 1;
1866                 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
1867                 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
1868                 CtlP->AiopIntrBits = upci_aiop_intr_bits;
1869         } else {
1870                 CtlP->isUPCI = 0;
1871                 CtlP->PCIIO =
1872                     (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
1873                 CtlP->AiopIntrBits = aiop_intr_bits;
1874         }
1875 
1876         sPCIControllerEOI(CtlP);        /* clear EOI if warm init */
1877         /* Init AIOPs */
1878         CtlP->NumAiop = 0;
1879         for (i = 0; i < AiopIOListSize; i++) {
1880                 io = AiopIOList[i];
1881                 CtlP->AiopIO[i] = (WordIO_t) io;
1882                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
1883 
1884                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
1885                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
1886                         break;  /* done looking for AIOPs */
1887 
1888                 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
1889                 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
1890                 sOutB(io + _INDX_DATA, sClockPrescale);
1891                 CtlP->NumAiop++;        /* bump count of AIOPs */
1892         }
1893 
1894         if (CtlP->NumAiop == 0)
1895                 return (-1);
1896         else
1897                 return (CtlP->NumAiop);
1898 }
1899 
1900 /*
1901  *  Called when a PCI card is found.  Retrieves and stores model information,
1902  *  init's aiopic and serial port hardware.
1903  *  Inputs:  i is the board number (0-n)
1904  */
1905 static __init int register_PCI(int i, struct pci_dev *dev)
1906 {
1907         int num_aiops, aiop, max_num_aiops, num_chan, chan;
1908         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1909         CONTROLLER_t *ctlp;
1910 
1911         int fast_clock = 0;
1912         int altChanRingIndicator = 0;
1913         int ports_per_aiop = 8;
1914         WordIO_t ConfigIO = 0;
1915         ByteIO_t UPCIRingInd = 0;
1916 
1917         if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
1918             pci_enable_device(dev))
1919                 return 0;
1920 
1921         rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1922 
1923         rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1924         rocketModel[i].loadrm2 = 0;
1925         rocketModel[i].startingPortNumber = nextLineNumber;
1926 
1927         /*  Depending on the model, set up some config variables */
1928         switch (dev->device) {
1929         case PCI_DEVICE_ID_RP4QUAD:
1930                 max_num_aiops = 1;
1931                 ports_per_aiop = 4;
1932                 rocketModel[i].model = MODEL_RP4QUAD;
1933                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1934                 rocketModel[i].numPorts = 4;
1935                 break;
1936         case PCI_DEVICE_ID_RP8OCTA:
1937                 max_num_aiops = 1;
1938                 rocketModel[i].model = MODEL_RP8OCTA;
1939                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1940                 rocketModel[i].numPorts = 8;
1941                 break;
1942         case PCI_DEVICE_ID_URP8OCTA:
1943                 max_num_aiops = 1;
1944                 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1945                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1946                 rocketModel[i].numPorts = 8;
1947                 break;
1948         case PCI_DEVICE_ID_RP8INTF:
1949                 max_num_aiops = 1;
1950                 rocketModel[i].model = MODEL_RP8INTF;
1951                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1952                 rocketModel[i].numPorts = 8;
1953                 break;
1954         case PCI_DEVICE_ID_URP8INTF:
1955                 max_num_aiops = 1;
1956                 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1957                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1958                 rocketModel[i].numPorts = 8;
1959                 break;
1960         case PCI_DEVICE_ID_RP8J:
1961                 max_num_aiops = 1;
1962                 rocketModel[i].model = MODEL_RP8J;
1963                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1964                 rocketModel[i].numPorts = 8;
1965                 break;
1966         case PCI_DEVICE_ID_RP4J:
1967                 max_num_aiops = 1;
1968                 ports_per_aiop = 4;
1969                 rocketModel[i].model = MODEL_RP4J;
1970                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1971                 rocketModel[i].numPorts = 4;
1972                 break;
1973         case PCI_DEVICE_ID_RP8SNI:
1974                 max_num_aiops = 1;
1975                 rocketModel[i].model = MODEL_RP8SNI;
1976                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1977                 rocketModel[i].numPorts = 8;
1978                 break;
1979         case PCI_DEVICE_ID_RP16SNI:
1980                 max_num_aiops = 2;
1981                 rocketModel[i].model = MODEL_RP16SNI;
1982                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1983                 rocketModel[i].numPorts = 16;
1984                 break;
1985         case PCI_DEVICE_ID_RP16INTF:
1986                 max_num_aiops = 2;
1987                 rocketModel[i].model = MODEL_RP16INTF;
1988                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1989                 rocketModel[i].numPorts = 16;
1990                 break;
1991         case PCI_DEVICE_ID_URP16INTF:
1992                 max_num_aiops = 2;
1993                 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1994                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1995                 rocketModel[i].numPorts = 16;
1996                 break;
1997         case PCI_DEVICE_ID_CRP16INTF:
1998                 max_num_aiops = 2;
1999                 rocketModel[i].model = MODEL_CPCI_RP16INTF;
2000                 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
2001                 rocketModel[i].numPorts = 16;
2002                 break;
2003         case PCI_DEVICE_ID_RP32INTF:
2004                 max_num_aiops = 4;
2005                 rocketModel[i].model = MODEL_RP32INTF;
2006                 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
2007                 rocketModel[i].numPorts = 32;
2008                 break;
2009         case PCI_DEVICE_ID_URP32INTF:
2010                 max_num_aiops = 4;
2011                 rocketModel[i].model = MODEL_UPCI_RP32INTF;
2012                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
2013                 rocketModel[i].numPorts = 32;
2014                 break;
2015         case PCI_DEVICE_ID_RPP4:
2016                 max_num_aiops = 1;
2017                 ports_per_aiop = 4;
2018                 altChanRingIndicator++;
2019                 fast_clock++;
2020                 rocketModel[i].model = MODEL_RPP4;
2021                 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2022                 rocketModel[i].numPorts = 4;
2023                 break;
2024         case PCI_DEVICE_ID_RPP8:
2025                 max_num_aiops = 2;
2026                 ports_per_aiop = 4;
2027                 altChanRingIndicator++;
2028                 fast_clock++;
2029                 rocketModel[i].model = MODEL_RPP8;
2030                 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2031                 rocketModel[i].numPorts = 8;
2032                 break;
2033         case PCI_DEVICE_ID_RP2_232:
2034                 max_num_aiops = 1;
2035                 ports_per_aiop = 2;
2036                 altChanRingIndicator++;
2037                 fast_clock++;
2038                 rocketModel[i].model = MODEL_RP2_232;
2039                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2040                 rocketModel[i].numPorts = 2;
2041                 break;
2042         case PCI_DEVICE_ID_RP2_422:
2043                 max_num_aiops = 1;
2044                 ports_per_aiop = 2;
2045                 altChanRingIndicator++;
2046                 fast_clock++;
2047                 rocketModel[i].model = MODEL_RP2_422;
2048                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2049                 rocketModel[i].numPorts = 2;
2050                 break;
2051         case PCI_DEVICE_ID_RP6M:
2052 
2053                 max_num_aiops = 1;
2054                 ports_per_aiop = 6;
2055 
2056                 /*  If revision is 1, the rocketmodem flash must be loaded.
2057                  *  If it is 2 it is a "socketed" version. */
2058                 if (dev->revision == 1) {
2059                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2060                         rocketModel[i].loadrm2 = 1;
2061                 } else {
2062                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
2063                 }
2064 
2065                 rocketModel[i].model = MODEL_RP6M;
2066                 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2067                 rocketModel[i].numPorts = 6;
2068                 break;
2069         case PCI_DEVICE_ID_RP4M:
2070                 max_num_aiops = 1;
2071                 ports_per_aiop = 4;
2072                 if (dev->revision == 1) {
2073                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2074                         rocketModel[i].loadrm2 = 1;
2075                 } else {
2076                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
2077                 }
2078 
2079                 rocketModel[i].model = MODEL_RP4M;
2080                 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2081                 rocketModel[i].numPorts = 4;
2082                 break;
2083         default:
2084                 max_num_aiops = 0;
2085                 break;
2086         }
2087 
2088         /*
2089          * Check for UPCI boards.
2090          */
2091 
2092         switch (dev->device) {
2093         case PCI_DEVICE_ID_URP32INTF:
2094         case PCI_DEVICE_ID_URP8INTF:
2095         case PCI_DEVICE_ID_URP16INTF:
2096         case PCI_DEVICE_ID_CRP16INTF:
2097         case PCI_DEVICE_ID_URP8OCTA:
2098                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2099                 ConfigIO = pci_resource_start(dev, 1);
2100                 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2101                         UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2102 
2103                         /*
2104                          * Check for octa or quad cable.
2105                          */
2106                         if (!
2107                             (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2108                              PCI_GPIO_CTRL_8PORT)) {
2109                                 ports_per_aiop = 4;
2110                                 rocketModel[i].numPorts = 4;
2111                         }
2112                 }
2113                 break;
2114         case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2115                 max_num_aiops = 1;
2116                 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2117                 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2118                 rocketModel[i].numPorts = 8;
2119                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2120                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2121                 ConfigIO = pci_resource_start(dev, 1);
2122                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2123                 break;
2124         case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2125                 max_num_aiops = 1;
2126                 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2127                 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2128                 rocketModel[i].numPorts = 4;
2129                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2130                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2131                 ConfigIO = pci_resource_start(dev, 1);
2132                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2133                 break;
2134         default:
2135                 break;
2136         }
2137 
2138         if (fast_clock) {
2139                 sClockPrescale = 0x12;  /* mod 2 (divide by 3) */
2140                 rp_baud_base[i] = 921600;
2141         } else {
2142                 /*
2143                  * If support_low_speed is set, use the slow clock
2144                  * prescale, which supports 50 bps
2145                  */
2146                 if (support_low_speed) {
2147                         /* mod 9 (divide by 10) prescale */
2148                         sClockPrescale = 0x19;
2149                         rp_baud_base[i] = 230400;
2150                 } else {
2151                         /* mod 4 (divide by 5) prescale */
2152                         sClockPrescale = 0x14;
2153                         rp_baud_base[i] = 460800;
2154                 }
2155         }
2156 
2157         for (aiop = 0; aiop < max_num_aiops; aiop++)
2158                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2159         ctlp = sCtlNumToCtlPtr(i);
2160         num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2161         for (aiop = 0; aiop < max_num_aiops; aiop++)
2162                 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2163 
2164         dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2165                 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2166                 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2167                 rocketModel[i].startingPortNumber,
2168                 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2169 
2170         if (num_aiops <= 0) {
2171                 rcktpt_io_addr[i] = 0;
2172                 return (0);
2173         }
2174         is_PCI[i] = 1;
2175 
2176         /*  Reset the AIOPIC, init the serial ports */
2177         for (aiop = 0; aiop < num_aiops; aiop++) {
2178                 sResetAiopByNum(ctlp, aiop);
2179                 num_chan = ports_per_aiop;
2180                 for (chan = 0; chan < num_chan; chan++)
2181                         init_r_port(i, aiop, chan, dev);
2182         }
2183 
2184         /*  Rocket modems must be reset */
2185         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2186             (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2187             (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2188                 num_chan = ports_per_aiop;
2189                 for (chan = 0; chan < num_chan; chan++)
2190                         sPCIModemReset(ctlp, chan, 1);
2191                 msleep(500);
2192                 for (chan = 0; chan < num_chan; chan++)
2193                         sPCIModemReset(ctlp, chan, 0);
2194                 msleep(500);
2195                 rmSpeakerReset(ctlp, rocketModel[i].model);
2196         }
2197         return (1);
2198 }
2199 
2200 /*
2201  *  Probes for PCI cards, inits them if found
2202  *  Input:   board_found = number of ISA boards already found, or the
2203  *           starting board number
2204  *  Returns: Number of PCI boards found
2205  */
2206 static int __init init_PCI(int boards_found)
2207 {
2208         struct pci_dev *dev = NULL;
2209         int count = 0;
2210 
2211         /*  Work through the PCI device list, pulling out ours */
2212         while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2213                 if (register_PCI(count + boards_found, dev))
2214                         count++;
2215         }
2216         return (count);
2217 }
2218 
2219 #endif                          /* CONFIG_PCI */
2220 
2221 /*
2222  *  Probes for ISA cards
2223  *  Input:   i = the board number to look for
2224  *  Returns: 1 if board found, 0 else
2225  */
2226 static int __init init_ISA(int i)
2227 {
2228         int num_aiops, num_chan = 0, total_num_chan = 0;
2229         int aiop, chan;
2230         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2231         CONTROLLER_t *ctlp;
2232         char *type_string;
2233 
2234         /*  If io_addr is zero, no board configured */
2235         if (rcktpt_io_addr[i] == 0)
2236                 return (0);
2237 
2238         /*  Reserve the IO region */
2239         if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2240                 printk(KERN_ERR "Unable to reserve IO region for configured "
2241                                 "ISA RocketPort at address 0x%lx, board not "
2242                                 "installed...\n", rcktpt_io_addr[i]);
2243                 rcktpt_io_addr[i] = 0;
2244                 return (0);
2245         }
2246 
2247         ctlp = sCtlNumToCtlPtr(i);
2248 
2249         ctlp->boardType = rcktpt_type[i];
2250 
2251         switch (rcktpt_type[i]) {
2252         case ROCKET_TYPE_PC104:
2253                 type_string = "(PC104)";
2254                 break;
2255         case ROCKET_TYPE_MODEM:
2256                 type_string = "(RocketModem)";
2257                 break;
2258         case ROCKET_TYPE_MODEMII:
2259                 type_string = "(RocketModem II)";
2260                 break;
2261         default:
2262                 type_string = "";
2263                 break;
2264         }
2265 
2266         /*
2267          * If support_low_speed is set, use the slow clock prescale,
2268          * which supports 50 bps
2269          */
2270         if (support_low_speed) {
2271                 sClockPrescale = 0x19;  /* mod 9 (divide by 10) prescale */
2272                 rp_baud_base[i] = 230400;
2273         } else {
2274                 sClockPrescale = 0x14;  /* mod 4 (divide by 5) prescale */
2275                 rp_baud_base[i] = 460800;
2276         }
2277 
2278         for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2279                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2280 
2281         num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio,  MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2282 
2283         if (ctlp->boardType == ROCKET_TYPE_PC104) {
2284                 sEnAiop(ctlp, 2);       /* only one AIOPIC, but these */
2285                 sEnAiop(ctlp, 3);       /* CSels used for other stuff */
2286         }
2287 
2288         /*  If something went wrong initing the AIOP's release the ISA IO memory */
2289         if (num_aiops <= 0) {
2290                 release_region(rcktpt_io_addr[i], 64);
2291                 rcktpt_io_addr[i] = 0;
2292                 return (0);
2293         }
2294   
2295         rocketModel[i].startingPortNumber = nextLineNumber;
2296 
2297         for (aiop = 0; aiop < num_aiops; aiop++) {
2298                 sResetAiopByNum(ctlp, aiop);
2299                 sEnAiop(ctlp, aiop);
2300                 num_chan = sGetAiopNumChan(ctlp, aiop);
2301                 total_num_chan += num_chan;
2302                 for (chan = 0; chan < num_chan; chan++)
2303                         init_r_port(i, aiop, chan, NULL);
2304         }
2305         is_PCI[i] = 0;
2306         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2307                 num_chan = sGetAiopNumChan(ctlp, 0);
2308                 total_num_chan = num_chan;
2309                 for (chan = 0; chan < num_chan; chan++)
2310                         sModemReset(ctlp, chan, 1);
2311                 msleep(500);
2312                 for (chan = 0; chan < num_chan; chan++)
2313                         sModemReset(ctlp, chan, 0);
2314                 msleep(500);
2315                 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2316         } else {
2317                 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2318         }
2319         rocketModel[i].numPorts = total_num_chan;
2320         rocketModel[i].model = MODEL_ISA;
2321 
2322         printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n", 
2323                i, rcktpt_io_addr[i], num_aiops, type_string);
2324 
2325         printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2326                rocketModel[i].modelString,
2327                rocketModel[i].startingPortNumber,
2328                rocketModel[i].startingPortNumber +
2329                rocketModel[i].numPorts - 1);
2330 
2331         return (1);
2332 }
2333 
2334 static const struct tty_operations rocket_ops = {
2335         .open = rp_open,
2336         .close = rp_close,
2337         .write = rp_write,
2338         .put_char = rp_put_char,
2339         .write_room = rp_write_room,
2340         .chars_in_buffer = rp_chars_in_buffer,
2341         .flush_buffer = rp_flush_buffer,
2342         .ioctl = rp_ioctl,
2343         .throttle = rp_throttle,
2344         .unthrottle = rp_unthrottle,
2345         .set_termios = rp_set_termios,
2346         .stop = rp_stop,
2347         .start = rp_start,
2348         .hangup = rp_hangup,
2349         .break_ctl = rp_break,
2350         .send_xchar = rp_send_xchar,
2351         .wait_until_sent = rp_wait_until_sent,
2352         .tiocmget = rp_tiocmget,
2353         .tiocmset = rp_tiocmset,
2354 };
2355 
2356 static const struct tty_port_operations rocket_port_ops = {
2357         .carrier_raised = carrier_raised,
2358         .dtr_rts = dtr_rts,
2359 };
2360 
2361 /*
2362  * The module "startup" routine; it's run when the module is loaded.
2363  */
2364 static int __init rp_init(void)
2365 {
2366         int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2367 
2368         printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2369                ROCKET_VERSION, ROCKET_DATE);
2370 
2371         rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2372         if (!rocket_driver)
2373                 goto err;
2374 
2375         /*
2376          *  If board 1 is non-zero, there is at least one ISA configured.  If controller is 
2377          *  zero, use the default controller IO address of board1 + 0x40.
2378          */
2379         if (board1) {
2380                 if (controller == 0)
2381                         controller = board1 + 0x40;
2382         } else {
2383                 controller = 0;  /*  Used as a flag, meaning no ISA boards */
2384         }
2385 
2386         /*  If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2387         if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2388                 printk(KERN_ERR "Unable to reserve IO region for first "
2389                         "configured ISA RocketPort controller 0x%lx.  "
2390                         "Driver exiting\n", controller);
2391                 ret = -EBUSY;
2392                 goto err_tty;
2393         }
2394 
2395         /*  Store ISA variable retrieved from command line or .conf file. */
2396         rcktpt_io_addr[0] = board1;
2397         rcktpt_io_addr[1] = board2;
2398         rcktpt_io_addr[2] = board3;
2399         rcktpt_io_addr[3] = board4;
2400 
2401         rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2402         rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2403         rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2404         rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2405         rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2406         rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2407         rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2408         rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2409 
2410         /*
2411          * Set up the tty driver structure and then register this
2412          * driver with the tty layer.
2413          */
2414 
2415         rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2416         rocket_driver->name = "ttyR";
2417         rocket_driver->driver_name = "Comtrol RocketPort";
2418         rocket_driver->major = TTY_ROCKET_MAJOR;
2419         rocket_driver->minor_start = 0;
2420         rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2421         rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2422         rocket_driver->init_termios = tty_std_termios;
2423         rocket_driver->init_termios.c_cflag =
2424             B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2425         rocket_driver->init_termios.c_ispeed = 9600;
2426         rocket_driver->init_termios.c_ospeed = 9600;
2427 #ifdef ROCKET_SOFT_FLOW
2428         rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2429 #endif
2430         tty_set_operations(rocket_driver, &rocket_ops);
2431 
2432         ret = tty_register_driver(rocket_driver);
2433         if (ret < 0) {
2434                 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2435                 goto err_controller;
2436         }
2437 
2438 #ifdef ROCKET_DEBUG_OPEN
2439         printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2440 #endif
2441 
2442         /*
2443          *  OK, let's probe each of the controllers looking for boards.  Any boards found
2444          *  will be initialized here.
2445          */
2446         isa_boards_found = 0;
2447         pci_boards_found = 0;
2448 
2449         for (i = 0; i < NUM_BOARDS; i++) {
2450                 if (init_ISA(i))
2451                         isa_boards_found++;
2452         }
2453 
2454 #ifdef CONFIG_PCI
2455         if (isa_boards_found < NUM_BOARDS)
2456                 pci_boards_found = init_PCI(isa_boards_found);
2457 #endif
2458 
2459         max_board = pci_boards_found + isa_boards_found;
2460 
2461         if (max_board == 0) {
2462                 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2463                 ret = -ENXIO;
2464                 goto err_ttyu;
2465         }
2466 
2467         return 0;
2468 err_ttyu:
2469         tty_unregister_driver(rocket_driver);
2470 err_controller:
2471         if (controller)
2472                 release_region(controller, 4);
2473 err_tty:
2474         put_tty_driver(rocket_driver);
2475 err:
2476         return ret;
2477 }
2478 
2479 
2480 static void rp_cleanup_module(void)
2481 {
2482         int retval;
2483         int i;
2484 
2485         del_timer_sync(&rocket_timer);
2486 
2487         retval = tty_unregister_driver(rocket_driver);
2488         if (retval)
2489                 printk(KERN_ERR "Error %d while trying to unregister "
2490                        "rocketport driver\n", -retval);
2491 
2492         for (i = 0; i < MAX_RP_PORTS; i++)
2493                 if (rp_table[i]) {
2494                         tty_unregister_device(rocket_driver, i);
2495                         tty_port_destroy(&rp_table[i]->port);
2496                         kfree(rp_table[i]);
2497                 }
2498 
2499         put_tty_driver(rocket_driver);
2500 
2501         for (i = 0; i < NUM_BOARDS; i++) {
2502                 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2503                         continue;
2504                 release_region(rcktpt_io_addr[i], 64);
2505         }
2506         if (controller)
2507                 release_region(controller, 4);
2508 }
2509 
2510 /***************************************************************************
2511 Function: sInitController
2512 Purpose:  Initialization of controller global registers and controller
2513           structure.
2514 Call:     sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2515                           IRQNum,Frequency,PeriodicOnly)
2516           CONTROLLER_T *CtlP; Ptr to controller structure
2517           int CtlNum; Controller number
2518           ByteIO_t MudbacIO; Mudbac base I/O address.
2519           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2520              This list must be in the order the AIOPs will be found on the
2521              controller.  Once an AIOP in the list is not found, it is
2522              assumed that there are no more AIOPs on the controller.
2523           int AiopIOListSize; Number of addresses in AiopIOList
2524           int IRQNum; Interrupt Request number.  Can be any of the following:
2525                          0: Disable global interrupts
2526                          3: IRQ 3
2527                          4: IRQ 4
2528                          5: IRQ 5
2529                          9: IRQ 9
2530                          10: IRQ 10
2531                          11: IRQ 11
2532                          12: IRQ 12
2533                          15: IRQ 15
2534           Byte_t Frequency: A flag identifying the frequency
2535                    of the periodic interrupt, can be any one of the following:
2536                       FREQ_DIS - periodic interrupt disabled
2537                       FREQ_137HZ - 137 Hertz
2538                       FREQ_69HZ - 69 Hertz
2539                       FREQ_34HZ - 34 Hertz
2540                       FREQ_17HZ - 17 Hertz
2541                       FREQ_9HZ - 9 Hertz
2542                       FREQ_4HZ - 4 Hertz
2543                    If IRQNum is set to 0 the Frequency parameter is
2544                    overidden, it is forced to a value of FREQ_DIS.
2545           int PeriodicOnly: 1 if all interrupts except the periodic
2546                                interrupt are to be blocked.
2547                             0 is both the periodic interrupt and
2548                                other channel interrupts are allowed.
2549                             If IRQNum is set to 0 the PeriodicOnly parameter is
2550                                overidden, it is forced to a value of 0.
2551 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
2552                initialization failed.
2553 
2554 Comments:
2555           If periodic interrupts are to be disabled but AIOP interrupts
2556           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2557 
2558           If interrupts are to be completely disabled set IRQNum to 0.
2559 
2560           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2561           invalid combination.
2562 
2563           This function performs initialization of global interrupt modes,
2564           but it does not actually enable global interrupts.  To enable
2565           and disable global interrupts use functions sEnGlobalInt() and
2566           sDisGlobalInt().  Enabling of global interrupts is normally not
2567           done until all other initializations are complete.
2568 
2569           Even if interrupts are globally enabled, they must also be
2570           individually enabled for each channel that is to generate
2571           interrupts.
2572 
2573 Warnings: No range checking on any of the parameters is done.
2574 
2575           No context switches are allowed while executing this function.
2576 
2577           After this function all AIOPs on the controller are disabled,
2578           they can be enabled with sEnAiop().
2579 */
2580 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2581                            ByteIO_t * AiopIOList, int AiopIOListSize,
2582                            int IRQNum, Byte_t Frequency, int PeriodicOnly)
2583 {
2584         int i;
2585         ByteIO_t io;
2586         int done;
2587 
2588         CtlP->AiopIntrBits = aiop_intr_bits;
2589         CtlP->AltChanRingIndicator = 0;
2590         CtlP->CtlNum = CtlNum;
2591         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
2592         CtlP->BusType = isISA;
2593         CtlP->MBaseIO = MudbacIO;
2594         CtlP->MReg1IO = MudbacIO + 1;
2595         CtlP->MReg2IO = MudbacIO + 2;
2596         CtlP->MReg3IO = MudbacIO + 3;
2597 #if 1
2598         CtlP->MReg2 = 0;        /* interrupt disable */
2599         CtlP->MReg3 = 0;        /* no periodic interrupts */
2600 #else
2601         if (sIRQMap[IRQNum] == 0) {     /* interrupts globally disabled */
2602                 CtlP->MReg2 = 0;        /* interrupt disable */
2603                 CtlP->MReg3 = 0;        /* no periodic interrupts */
2604         } else {
2605                 CtlP->MReg2 = sIRQMap[IRQNum];  /* set IRQ number */
2606                 CtlP->MReg3 = Frequency;        /* set frequency */
2607                 if (PeriodicOnly) {     /* periodic interrupt only */
2608                         CtlP->MReg3 |= PERIODIC_ONLY;
2609                 }
2610         }
2611 #endif
2612         sOutB(CtlP->MReg2IO, CtlP->MReg2);
2613         sOutB(CtlP->MReg3IO, CtlP->MReg3);
2614         sControllerEOI(CtlP);   /* clear EOI if warm init */
2615         /* Init AIOPs */
2616         CtlP->NumAiop = 0;
2617         for (i = done = 0; i < AiopIOListSize; i++) {
2618                 io = AiopIOList[i];
2619                 CtlP->AiopIO[i] = (WordIO_t) io;
2620                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2621                 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2622                 sOutB(MudbacIO, (Byte_t) (io >> 6));    /* set up AIOP I/O in MUDBAC */
2623                 if (done)
2624                         continue;
2625                 sEnAiop(CtlP, i);       /* enable the AIOP */
2626                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
2627                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
2628                         done = 1;       /* done looking for AIOPs */
2629                 else {
2630                         CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2631                         sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
2632                         sOutB(io + _INDX_DATA, sClockPrescale);
2633                         CtlP->NumAiop++;        /* bump count of AIOPs */
2634                 }
2635                 sDisAiop(CtlP, i);      /* disable AIOP */
2636         }
2637 
2638         if (CtlP->NumAiop == 0)
2639                 return (-1);
2640         else
2641                 return (CtlP->NumAiop);
2642 }
2643 
2644 /***************************************************************************
2645 Function: sReadAiopID
2646 Purpose:  Read the AIOP idenfication number directly from an AIOP.
2647 Call:     sReadAiopID(io)
2648           ByteIO_t io: AIOP base I/O address
2649 Return:   int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2650                  is replace by an identifying number.
2651           Flag AIOPID_NULL if no valid AIOP is found
2652 Warnings: No context switches are allowed while executing this function.
2653 
2654 */
2655 static int sReadAiopID(ByteIO_t io)
2656 {
2657         Byte_t AiopID;          /* ID byte from AIOP */
2658 
2659         sOutB(io + _CMD_REG, RESET_ALL);        /* reset AIOP */
2660         sOutB(io + _CMD_REG, 0x0);
2661         AiopID = sInW(io + _CHN_STAT0) & 0x07;
2662         if (AiopID == 0x06)
2663                 return (1);
2664         else                    /* AIOP does not exist */
2665                 return (-1);
2666 }
2667 
2668 /***************************************************************************
2669 Function: sReadAiopNumChan
2670 Purpose:  Read the number of channels available in an AIOP directly from
2671           an AIOP.
2672 Call:     sReadAiopNumChan(io)
2673           WordIO_t io: AIOP base I/O address
2674 Return:   int: The number of channels available
2675 Comments: The number of channels is determined by write/reads from identical
2676           offsets within the SRAM address spaces for channels 0 and 4.
2677           If the channel 4 space is mirrored to channel 0 it is a 4 channel
2678           AIOP, otherwise it is an 8 channel.
2679 Warnings: No context switches are allowed while executing this function.
2680 */
2681 static int sReadAiopNumChan(WordIO_t io)
2682 {
2683         Word_t x;
2684         static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2685 
2686         /* write to chan 0 SRAM */
2687         out32((DWordIO_t) io + _INDX_ADDR, R);
2688         sOutW(io + _INDX_ADDR, 0);      /* read from SRAM, chan 0 */
2689         x = sInW(io + _INDX_DATA);
2690         sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2691         if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2692                 return (8);
2693         else
2694                 return (4);
2695 }
2696 
2697 /***************************************************************************
2698 Function: sInitChan
2699 Purpose:  Initialization of a channel and channel structure
2700 Call:     sInitChan(CtlP,ChP,AiopNum,ChanNum)
2701           CONTROLLER_T *CtlP; Ptr to controller structure
2702           CHANNEL_T *ChP; Ptr to channel structure
2703           int AiopNum; AIOP number within controller
2704           int ChanNum; Channel number within AIOP
2705 Return:   int: 1 if initialization succeeded, 0 if it fails because channel
2706                number exceeds number of channels available in AIOP.
2707 Comments: This function must be called before a channel can be used.
2708 Warnings: No range checking on any of the parameters is done.
2709 
2710           No context switches are allowed while executing this function.
2711 */
2712 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2713                      int ChanNum)
2714 {
2715         int i;
2716         WordIO_t AiopIO;
2717         WordIO_t ChIOOff;
2718         Byte_t *ChR;
2719         Word_t ChOff;
2720         static Byte_t R[4];
2721         int brd9600;
2722 
2723         if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2724                 return 0;       /* exceeds num chans in AIOP */
2725 
2726         /* Channel, AIOP, and controller identifiers */
2727         ChP->CtlP = CtlP;
2728         ChP->ChanID = CtlP->AiopID[AiopNum];
2729         ChP->AiopNum = AiopNum;
2730         ChP->ChanNum = ChanNum;
2731 
2732         /* Global direct addresses */
2733         AiopIO = CtlP->AiopIO[AiopNum];
2734         ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2735         ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2736         ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2737         ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2738         ChP->IndexData = AiopIO + _INDX_DATA;
2739 
2740         /* Channel direct addresses */
2741         ChIOOff = AiopIO + ChP->ChanNum * 2;
2742         ChP->TxRxData = ChIOOff + _TD0;
2743         ChP->ChanStat = ChIOOff + _CHN_STAT0;
2744         ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2745         ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2746 
2747         /* Initialize the channel from the RData array */
2748         for (i = 0; i < RDATASIZE; i += 4) {
2749                 R[0] = RData[i];
2750                 R[1] = RData[i + 1] + 0x10 * ChanNum;
2751                 R[2] = RData[i + 2];
2752                 R[3] = RData[i + 3];
2753                 out32(ChP->IndexAddr, R);
2754         }
2755 
2756         ChR = ChP->R;
2757         for (i = 0; i < RREGDATASIZE; i += 4) {
2758                 ChR[i] = RRegData[i];
2759                 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2760                 ChR[i + 2] = RRegData[i + 2];
2761                 ChR[i + 3] = RRegData[i + 3];
2762         }
2763 
2764         /* Indexed registers */
2765         ChOff = (Word_t) ChanNum *0x1000;
2766 
2767         if (sClockPrescale == 0x14)
2768                 brd9600 = 47;
2769         else
2770                 brd9600 = 23;
2771 
2772         ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2773         ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2774         ChP->BaudDiv[2] = (Byte_t) brd9600;
2775         ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2776         out32(ChP->IndexAddr, ChP->BaudDiv);
2777 
2778         ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2779         ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2780         ChP->TxControl[2] = 0;
2781         ChP->TxControl[3] = 0;
2782         out32(ChP->IndexAddr, ChP->TxControl);
2783 
2784         ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2785         ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2786         ChP->RxControl[2] = 0;
2787         ChP->RxControl[3] = 0;
2788         out32(ChP->IndexAddr, ChP->RxControl);
2789 
2790         ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2791         ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2792         ChP->TxEnables[2] = 0;
2793         ChP->TxEnables[3] = 0;
2794         out32(ChP->IndexAddr, ChP->TxEnables);
2795 
2796         ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2797         ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2798         ChP->TxCompare[2] = 0;
2799         ChP->TxCompare[3] = 0;
2800         out32(ChP->IndexAddr, ChP->TxCompare);
2801 
2802         ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2803         ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2804         ChP->TxReplace1[2] = 0;
2805         ChP->TxReplace1[3] = 0;
2806         out32(ChP->IndexAddr, ChP->TxReplace1);
2807 
2808         ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2809         ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2810         ChP->TxReplace2[2] = 0;
2811         ChP->TxReplace2[3] = 0;
2812         out32(ChP->IndexAddr, ChP->TxReplace2);
2813 
2814         ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2815         ChP->TxFIFO = ChOff + _TX_FIFO;
2816 
2817         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT);  /* apply reset Tx FIFO count */
2818         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Tx FIFO count */
2819         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
2820         sOutW(ChP->IndexData, 0);
2821         ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2822         ChP->RxFIFO = ChOff + _RX_FIFO;
2823 
2824         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT);  /* apply reset Rx FIFO count */
2825         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Rx FIFO count */
2826         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
2827         sOutW(ChP->IndexData, 0);
2828         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
2829         sOutW(ChP->IndexData, 0);
2830         ChP->TxPrioCnt = ChOff + _TXP_CNT;
2831         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2832         sOutB(ChP->IndexData, 0);
2833         ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2834         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2835         sOutB(ChP->IndexData, 0);
2836         ChP->TxPrioBuf = ChOff + _TXP_BUF;
2837         sEnRxProcessor(ChP);    /* start the Rx processor */
2838 
2839         return 1;
2840 }
2841 
2842 /***************************************************************************
2843 Function: sStopRxProcessor
2844 Purpose:  Stop the receive processor from processing a channel.
2845 Call:     sStopRxProcessor(ChP)
2846           CHANNEL_T *ChP; Ptr to channel structure
2847 
2848 Comments: The receive processor can be started again with sStartRxProcessor().
2849           This function causes the receive processor to skip over the
2850           stopped channel.  It does not stop it from processing other channels.
2851 
2852 Warnings: No context switches are allowed while executing this function.
2853 
2854           Do not leave the receive processor stopped for more than one
2855           character time.
2856 
2857           After calling this function a delay of 4 uS is required to ensure
2858           that the receive processor is no longer processing this channel.
2859 */
2860 static void sStopRxProcessor(CHANNEL_T * ChP)
2861 {
2862         Byte_t R[4];
2863 
2864         R[0] = ChP->R[0];
2865         R[1] = ChP->R[1];
2866         R[2] = 0x0a;
2867         R[3] = ChP->R[3];
2868         out32(ChP->IndexAddr, R);
2869 }
2870 
2871 /***************************************************************************
2872 Function: sFlushRxFIFO
2873 Purpose:  Flush the Rx FIFO
2874 Call:     sFlushRxFIFO(ChP)
2875           CHANNEL_T *ChP; Ptr to channel structure
2876 Return:   void
2877 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2878           while it is being flushed the receive processor is stopped
2879           and the transmitter is disabled.  After these operations a
2880           4 uS delay is done before clearing the pointers to allow
2881           the receive processor to stop.  These items are handled inside
2882           this function.
2883 Warnings: No context switches are allowed while executing this function.
2884 */
2885 static void sFlushRxFIFO(CHANNEL_T * ChP)
2886 {
2887         int i;
2888         Byte_t Ch;              /* channel number within AIOP */
2889         int RxFIFOEnabled;      /* 1 if Rx FIFO enabled */
2890 
2891         if (sGetRxCnt(ChP) == 0)        /* Rx FIFO empty */
2892                 return;         /* don't need to flush */
2893 
2894         RxFIFOEnabled = 0;
2895         if (ChP->R[0x32] == 0x08) {     /* Rx FIFO is enabled */
2896                 RxFIFOEnabled = 1;
2897                 sDisRxFIFO(ChP);        /* disable it */
2898                 for (i = 0; i < 2000 / 200; i++)        /* delay 2 uS to allow proc to disable FIFO */
2899                         sInB(ChP->IntChan);     /* depends on bus i/o timing */
2900         }
2901         sGetChanStatus(ChP);    /* clear any pending Rx errors in chan stat */
2902         Ch = (Byte_t) sGetChanNum(ChP);
2903         sOutB(ChP->Cmd, Ch | RESRXFCNT);        /* apply reset Rx FIFO count */
2904         sOutB(ChP->Cmd, Ch);    /* remove reset Rx FIFO count */
2905         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
2906         sOutW(ChP->IndexData, 0);
2907         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
2908         sOutW(ChP->IndexData, 0);
2909         if (RxFIFOEnabled)
2910                 sEnRxFIFO(ChP); /* enable Rx FIFO */
2911 }
2912 
2913 /***************************************************************************
2914 Function: sFlushTxFIFO
2915 Purpose:  Flush the Tx FIFO
2916 Call:     sFlushTxFIFO(ChP)
2917           CHANNEL_T *ChP; Ptr to channel structure
2918 Return:   void
2919 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2920           while it is being flushed the receive processor is stopped
2921           and the transmitter is disabled.  After these operations a
2922           4 uS delay is done before clearing the pointers to allow
2923           the receive processor to stop.  These items are handled inside
2924           this function.
2925 Warnings: No context switches are allowed while executing this function.
2926 */
2927 static void sFlushTxFIFO(CHANNEL_T * ChP)
2928 {
2929         int i;
2930         Byte_t Ch;              /* channel number within AIOP */
2931         int TxEnabled;          /* 1 if transmitter enabled */
2932 
2933         if (sGetTxCnt(ChP) == 0)        /* Tx FIFO empty */
2934                 return;         /* don't need to flush */
2935 
2936         TxEnabled = 0;
2937         if (ChP->TxControl[3] & TX_ENABLE) {
2938                 TxEnabled = 1;
2939                 sDisTransmit(ChP);      /* disable transmitter */
2940         }
2941         sStopRxProcessor(ChP);  /* stop Rx processor */
2942         for (i = 0; i < 4000 / 200; i++)        /* delay 4 uS to allow proc to stop */
2943                 sInB(ChP->IntChan);     /* depends on bus i/o timing */
2944         Ch = (Byte_t) sGetChanNum(ChP);
2945         sOutB(ChP->Cmd, Ch | RESTXFCNT);        /* apply reset Tx FIFO count */
2946         sOutB(ChP->Cmd, Ch);    /* remove reset Tx FIFO count */
2947         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
2948         sOutW(ChP->IndexData, 0);
2949         if (TxEnabled)
2950                 sEnTransmit(ChP);       /* enable transmitter */
2951         sStartRxProcessor(ChP); /* restart Rx processor */
2952 }
2953 
2954 /***************************************************************************
2955 Function: sWriteTxPrioByte
2956 Purpose:  Write a byte of priority transmit data to a channel
2957 Call:     sWriteTxPrioByte(ChP,Data)
2958           CHANNEL_T *ChP; Ptr to channel structure
2959           Byte_t Data; The transmit data byte
2960 
2961 Return:   int: 1 if the bytes is successfully written, otherwise 0.
2962 
2963 Comments: The priority byte is transmitted before any data in the Tx FIFO.
2964 
2965 Warnings: No context switches are allowed while executing this function.
2966 */
2967 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2968 {
2969         Byte_t DWBuf[4];        /* buffer for double word writes */
2970         Word_t *WordPtr;        /* must be far because Win SS != DS */
2971         register DWordIO_t IndexAddr;
2972 
2973         if (sGetTxCnt(ChP) > 1) {       /* write it to Tx priority buffer */
2974                 IndexAddr = ChP->IndexAddr;
2975                 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt);    /* get priority buffer status */
2976                 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2977                         return (0);     /* nothing sent */
2978 
2979                 WordPtr = (Word_t *) (&DWBuf[0]);
2980                 *WordPtr = ChP->TxPrioBuf;      /* data byte address */
2981 
2982                 DWBuf[2] = Data;        /* data byte value */
2983                 out32(IndexAddr, DWBuf);        /* write it out */
2984 
2985                 *WordPtr = ChP->TxPrioCnt;      /* Tx priority count address */
2986 
2987                 DWBuf[2] = PRI_PEND + 1;        /* indicate 1 byte pending */
2988                 DWBuf[3] = 0;   /* priority buffer pointer */
2989                 out32(IndexAddr, DWBuf);        /* write it out */
2990         } else {                /* write it to Tx FIFO */
2991 
2992                 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2993         }
2994         return (1);             /* 1 byte sent */
2995 }
2996 
2997 /***************************************************************************
2998 Function: sEnInterrupts
2999 Purpose:  Enable one or more interrupts for a channel
3000 Call:     sEnInterrupts(ChP,Flags)
3001           CHANNEL_T *ChP; Ptr to channel structure
3002           Word_t Flags: Interrupt enable flags, can be any combination
3003              of the following flags:
3004                 TXINT_EN:   Interrupt on Tx FIFO empty
3005                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3006                             sSetRxTrigger())
3007                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3008                 MCINT_EN:   Interrupt on modem input change
3009                 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3010                             Interrupt Channel Register.
3011 Return:   void
3012 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3013           enabled.  If an interrupt enable flag is not set in Flags, that
3014           interrupt will not be changed.  Interrupts can be disabled with
3015           function sDisInterrupts().
3016 
3017           This function sets the appropriate bit for the channel in the AIOP's
3018           Interrupt Mask Register if the CHANINT_EN flag is set.  This allows
3019           this channel's bit to be set in the AIOP's Interrupt Channel Register.
3020 
3021           Interrupts must also be globally enabled before channel interrupts
3022           will be passed on to the host.  This is done with function
3023           sEnGlobalInt().
3024 
3025           In some cases it may be desirable to disable interrupts globally but
3026           enable channel interrupts.  This would allow the global interrupt
3027           status register to be used to determine which AIOPs need service.
3028 */
3029 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3030 {
3031         Byte_t Mask;            /* Interrupt Mask Register */
3032 
3033         ChP->RxControl[2] |=
3034             ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3035 
3036         out32(ChP->IndexAddr, ChP->RxControl);
3037 
3038         ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3039 
3040         out32(ChP->IndexAddr, ChP->TxControl);
3041 
3042         if (Flags & CHANINT_EN) {
3043                 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3044                 sOutB(ChP->IntMask, Mask);
3045         }
3046 }
3047 
3048 /***************************************************************************
3049 Function: sDisInterrupts
3050 Purpose:  Disable one or more interrupts for a channel
3051 Call:     sDisInterrupts(ChP,Flags)
3052           CHANNEL_T *ChP; Ptr to channel structure
3053           Word_t Flags: Interrupt flags, can be any combination
3054              of the following flags:
3055                 TXINT_EN:   Interrupt on Tx FIFO empty
3056                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3057                             sSetRxTrigger())
3058                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3059                 MCINT_EN:   Interrupt on modem input change
3060                 CHANINT_EN: Disable channel interrupt signal to the
3061                             AIOP's Interrupt Channel Register.
3062 Return:   void
3063 Comments: If an interrupt flag is set in Flags, that interrupt will be
3064           disabled.  If an interrupt flag is not set in Flags, that
3065           interrupt will not be changed.  Interrupts can be enabled with
3066           function sEnInterrupts().
3067 
3068           This function clears the appropriate bit for the channel in the AIOP's
3069           Interrupt Mask Register if the CHANINT_EN flag is set.  This blocks
3070           this channel's bit from being set in the AIOP's Interrupt Channel
3071           Register.
3072 */
3073 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3074 {
3075         Byte_t Mask;            /* Interrupt Mask Register */
3076 
3077         ChP->RxControl[2] &=
3078             ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3079         out32(ChP->IndexAddr, ChP->RxControl);
3080         ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3081         out32(ChP->IndexAddr, ChP->TxControl);
3082 
3083         if (Flags & CHANINT_EN) {
3084                 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3085                 sOutB(ChP->IntMask, Mask);
3086         }
3087 }
3088 
3089 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3090 {
3091         sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3092 }
3093 
3094 /*
3095  *  Not an official SSCI function, but how to reset RocketModems.
3096  *  ISA bus version
3097  */
3098 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3099 {
3100         ByteIO_t addr;
3101         Byte_t val;
3102 
3103         addr = CtlP->AiopIO[0] + 0x400;
3104         val = sInB(CtlP->MReg3IO);
3105         /* if AIOP[1] is not enabled, enable it */
3106         if ((val & 2) == 0) {
3107                 val = sInB(CtlP->MReg2IO);
3108                 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3109                 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3110         }
3111 
3112         sEnAiop(CtlP, 1);
3113         if (!on)
3114                 addr += 8;
3115         sOutB(addr + chan, 0);  /* apply or remove reset */
3116         sDisAiop(CtlP, 1);
3117 }
3118 
3119 /*
3120  *  Not an official SSCI function, but how to reset RocketModems.
3121  *  PCI bus version
3122  */
3123 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3124 {
3125         ByteIO_t addr;
3126 
3127         addr = CtlP->AiopIO[0] + 0x40;  /* 2nd AIOP */
3128         if (!on)
3129                 addr += 8;
3130         sOutB(addr + chan, 0);  /* apply or remove reset */
3131 }
3132 
3133 /*  Returns the line number given the controller (board), aiop and channel number */
3134 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3135 {
3136         return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3137 }
3138 
3139 /*
3140  *  Stores the line number associated with a given controller (board), aiop
3141  *  and channel number.  
3142  *  Returns:  The line number assigned 
3143  */
3144 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3145 {
3146         lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3147         return (nextLineNumber - 1);
3148 }
3149 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us