Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/tty/rocket.c

  1 /*
  2  * RocketPort device driver for Linux
  3  *
  4  * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
  5  * 
  6  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
  7  * 
  8  * This program is free software; you can redistribute it and/or
  9  * modify it under the terms of the GNU General Public License as
 10  * published by the Free Software Foundation; either version 2 of the
 11  * License, or (at your option) any later version.
 12  * 
 13  * This program is distributed in the hope that it will be useful, but
 14  * WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 16  * General Public License for more details.
 17  * 
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program; if not, write to the Free Software
 20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 21  */
 22 
 23 /*
 24  * Kernel Synchronization:
 25  *
 26  * This driver has 2 kernel control paths - exception handlers (calls into the driver
 27  * from user mode) and the timer bottom half (tasklet).  This is a polled driver, interrupts
 28  * are not used.
 29  *
 30  * Critical data: 
 31  * -  rp_table[], accessed through passed "info" pointers, is a global (static) array of 
 32  *    serial port state information and the xmit_buf circular buffer.  Protected by 
 33  *    a per port spinlock.
 34  * -  xmit_flags[], an array of ints indexed by line (port) number, indicating that there
 35  *    is data to be transmitted.  Protected by atomic bit operations.
 36  * -  rp_num_ports, int indicating number of open ports, protected by atomic operations.
 37  * 
 38  * rp_write() and rp_write_char() functions use a per port semaphore to protect against
 39  * simultaneous access to the same port by more than one process.
 40  */
 41 
 42 /****** Defines ******/
 43 #define ROCKET_PARANOIA_CHECK
 44 #define ROCKET_DISABLE_SIMUSAGE
 45 
 46 #undef ROCKET_SOFT_FLOW
 47 #undef ROCKET_DEBUG_OPEN
 48 #undef ROCKET_DEBUG_INTR
 49 #undef ROCKET_DEBUG_WRITE
 50 #undef ROCKET_DEBUG_FLOW
 51 #undef ROCKET_DEBUG_THROTTLE
 52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
 53 #undef ROCKET_DEBUG_RECEIVE
 54 #undef ROCKET_DEBUG_HANGUP
 55 #undef REV_PCI_ORDER
 56 #undef ROCKET_DEBUG_IO
 57 
 58 #define POLL_PERIOD (HZ/100)    /*  Polling period .01 seconds (10ms) */
 59 
 60 /****** Kernel includes ******/
 61 
 62 #include <linux/module.h>
 63 #include <linux/errno.h>
 64 #include <linux/major.h>
 65 #include <linux/kernel.h>
 66 #include <linux/signal.h>
 67 #include <linux/slab.h>
 68 #include <linux/mm.h>
 69 #include <linux/sched.h>
 70 #include <linux/timer.h>
 71 #include <linux/interrupt.h>
 72 #include <linux/tty.h>
 73 #include <linux/tty_driver.h>
 74 #include <linux/tty_flip.h>
 75 #include <linux/serial.h>
 76 #include <linux/string.h>
 77 #include <linux/fcntl.h>
 78 #include <linux/ptrace.h>
 79 #include <linux/mutex.h>
 80 #include <linux/ioport.h>
 81 #include <linux/delay.h>
 82 #include <linux/completion.h>
 83 #include <linux/wait.h>
 84 #include <linux/pci.h>
 85 #include <linux/uaccess.h>
 86 #include <linux/atomic.h>
 87 #include <asm/unaligned.h>
 88 #include <linux/bitops.h>
 89 #include <linux/spinlock.h>
 90 #include <linux/init.h>
 91 
 92 /****** RocketPort includes ******/
 93 
 94 #include "rocket_int.h"
 95 #include "rocket.h"
 96 
 97 #define ROCKET_VERSION "2.09"
 98 #define ROCKET_DATE "12-June-2003"
 99 
100 /****** RocketPort Local Variables ******/
101 
102 static void rp_do_poll(unsigned long dummy);
103 
104 static struct tty_driver *rocket_driver;
105 
106 static struct rocket_version driver_version = { 
107         ROCKET_VERSION, ROCKET_DATE
108 };
109 
110 static struct r_port *rp_table[MAX_RP_PORTS];          /*  The main repository of serial port state information. */
111 static unsigned int xmit_flags[NUM_BOARDS];            /*  Bit significant, indicates port had data to transmit. */
112                                                        /*  eg.  Bit 0 indicates port 0 has xmit data, ...        */
113 static atomic_t rp_num_ports_open;                     /*  Number of serial ports open                           */
114 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
115 
116 static unsigned long board1;                           /* ISA addresses, retrieved from rocketport.conf          */
117 static unsigned long board2;
118 static unsigned long board3;
119 static unsigned long board4;
120 static unsigned long controller;
121 static bool support_low_speed;
122 static unsigned long modem1;
123 static unsigned long modem2;
124 static unsigned long modem3;
125 static unsigned long modem4;
126 static unsigned long pc104_1[8];
127 static unsigned long pc104_2[8];
128 static unsigned long pc104_3[8];
129 static unsigned long pc104_4[8];
130 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
131 
132 static int rp_baud_base[NUM_BOARDS];                   /*  Board config info (Someday make a per-board structure)  */
133 static unsigned long rcktpt_io_addr[NUM_BOARDS];
134 static int rcktpt_type[NUM_BOARDS];
135 static int is_PCI[NUM_BOARDS];
136 static rocketModel_t rocketModel[NUM_BOARDS];
137 static int max_board;
138 static const struct tty_port_operations rocket_port_ops;
139 
140 /*
141  * The following arrays define the interrupt bits corresponding to each AIOP.
142  * These bits are different between the ISA and regular PCI boards and the
143  * Universal PCI boards.
144  */
145 
146 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
147         AIOP_INTR_BIT_0,
148         AIOP_INTR_BIT_1,
149         AIOP_INTR_BIT_2,
150         AIOP_INTR_BIT_3
151 };
152 
153 #ifdef CONFIG_PCI
154 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
155         UPCI_AIOP_INTR_BIT_0,
156         UPCI_AIOP_INTR_BIT_1,
157         UPCI_AIOP_INTR_BIT_2,
158         UPCI_AIOP_INTR_BIT_3
159 };
160 #endif
161 
162 static Byte_t RData[RDATASIZE] = {
163         0x00, 0x09, 0xf6, 0x82,
164         0x02, 0x09, 0x86, 0xfb,
165         0x04, 0x09, 0x00, 0x0a,
166         0x06, 0x09, 0x01, 0x0a,
167         0x08, 0x09, 0x8a, 0x13,
168         0x0a, 0x09, 0xc5, 0x11,
169         0x0c, 0x09, 0x86, 0x85,
170         0x0e, 0x09, 0x20, 0x0a,
171         0x10, 0x09, 0x21, 0x0a,
172         0x12, 0x09, 0x41, 0xff,
173         0x14, 0x09, 0x82, 0x00,
174         0x16, 0x09, 0x82, 0x7b,
175         0x18, 0x09, 0x8a, 0x7d,
176         0x1a, 0x09, 0x88, 0x81,
177         0x1c, 0x09, 0x86, 0x7a,
178         0x1e, 0x09, 0x84, 0x81,
179         0x20, 0x09, 0x82, 0x7c,
180         0x22, 0x09, 0x0a, 0x0a
181 };
182 
183 static Byte_t RRegData[RREGDATASIZE] = {
184         0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
185         0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
186         0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
187         0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
188         0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
189         0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
190         0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
191         0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
192         0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
193         0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
194         0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
195         0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
196         0x22, 0x09, 0x0a, 0x0a  /* 30: Rx FIFO Enable */
197 };
198 
199 static CONTROLLER_T sController[CTL_SIZE] = {
200         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
206         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
207          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
208 };
209 
210 static Byte_t sBitMapClrTbl[8] = {
211         0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
212 };
213 
214 static Byte_t sBitMapSetTbl[8] = {
215         0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
216 };
217 
218 static int sClockPrescale = 0x14;
219 
220 /*
221  *  Line number is the ttySIx number (x), the Minor number.  We 
222  *  assign them sequentially, starting at zero.  The following 
223  *  array keeps track of the line number assigned to a given board/aiop/channel.
224  */
225 static unsigned char lineNumbers[MAX_RP_PORTS];
226 static unsigned long nextLineNumber;
227 
228 /*****  RocketPort Static Prototypes   *********/
229 static int __init init_ISA(int i);
230 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
231 static void rp_flush_buffer(struct tty_struct *tty);
232 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
233 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
234 static void rp_start(struct tty_struct *tty);
235 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
236                      int ChanNum);
237 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
238 static void sFlushRxFIFO(CHANNEL_T * ChP);
239 static void sFlushTxFIFO(CHANNEL_T * ChP);
240 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
241 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
242 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
243 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
244 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
245 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
246                            ByteIO_t * AiopIOList, int AiopIOListSize,
247                            int IRQNum, Byte_t Frequency, int PeriodicOnly);
248 static int sReadAiopID(ByteIO_t io);
249 static int sReadAiopNumChan(WordIO_t io);
250 
251 MODULE_AUTHOR("Theodore Ts'o");
252 MODULE_DESCRIPTION("Comtrol RocketPort driver");
253 module_param(board1, ulong, 0);
254 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
255 module_param(board2, ulong, 0);
256 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
257 module_param(board3, ulong, 0);
258 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
259 module_param(board4, ulong, 0);
260 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
261 module_param(controller, ulong, 0);
262 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
263 module_param(support_low_speed, bool, 0);
264 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
265 module_param(modem1, ulong, 0);
266 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
267 module_param(modem2, ulong, 0);
268 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
269 module_param(modem3, ulong, 0);
270 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
271 module_param(modem4, ulong, 0);
272 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
273 module_param_array(pc104_1, ulong, NULL, 0);
274 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
275 module_param_array(pc104_2, ulong, NULL, 0);
276 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
277 module_param_array(pc104_3, ulong, NULL, 0);
278 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
279 module_param_array(pc104_4, ulong, NULL, 0);
280 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
281 
282 static int rp_init(void);
283 static void rp_cleanup_module(void);
284 
285 module_init(rp_init);
286 module_exit(rp_cleanup_module);
287 
288 
289 MODULE_LICENSE("Dual BSD/GPL");
290 
291 /*************************************************************************/
292 /*                     Module code starts here                           */
293 
294 static inline int rocket_paranoia_check(struct r_port *info,
295                                         const char *routine)
296 {
297 #ifdef ROCKET_PARANOIA_CHECK
298         if (!info)
299                 return 1;
300         if (info->magic != RPORT_MAGIC) {
301                 printk(KERN_WARNING "Warning: bad magic number for rocketport "
302                                 "struct in %s\n", routine);
303                 return 1;
304         }
305 #endif
306         return 0;
307 }
308 
309 
310 /*  Serial port receive data function.  Called (from timer poll) when an AIOPIC signals 
311  *  that receive data is present on a serial port.  Pulls data from FIFO, moves it into the 
312  *  tty layer.  
313  */
314 static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
315                 unsigned int ChanStatus)
316 {
317         unsigned int CharNStat;
318         int ToRecv, wRecv, space;
319         unsigned char *cbuf;
320 
321         ToRecv = sGetRxCnt(cp);
322 #ifdef ROCKET_DEBUG_INTR
323         printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
324 #endif
325         if (ToRecv == 0)
326                 return;
327 
328         /*
329          * if status indicates there are errored characters in the
330          * FIFO, then enter status mode (a word in FIFO holds
331          * character and status).
332          */
333         if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
334                 if (!(ChanStatus & STATMODE)) {
335 #ifdef ROCKET_DEBUG_RECEIVE
336                         printk(KERN_INFO "Entering STATMODE...\n");
337 #endif
338                         ChanStatus |= STATMODE;
339                         sEnRxStatusMode(cp);
340                 }
341         }
342 
343         /* 
344          * if we previously entered status mode, then read down the
345          * FIFO one word at a time, pulling apart the character and
346          * the status.  Update error counters depending on status
347          */
348         if (ChanStatus & STATMODE) {
349 #ifdef ROCKET_DEBUG_RECEIVE
350                 printk(KERN_INFO "Ignore %x, read %x...\n",
351                         info->ignore_status_mask, info->read_status_mask);
352 #endif
353                 while (ToRecv) {
354                         char flag;
355 
356                         CharNStat = sInW(sGetTxRxDataIO(cp));
357 #ifdef ROCKET_DEBUG_RECEIVE
358                         printk(KERN_INFO "%x...\n", CharNStat);
359 #endif
360                         if (CharNStat & STMBREAKH)
361                                 CharNStat &= ~(STMFRAMEH | STMPARITYH);
362                         if (CharNStat & info->ignore_status_mask) {
363                                 ToRecv--;
364                                 continue;
365                         }
366                         CharNStat &= info->read_status_mask;
367                         if (CharNStat & STMBREAKH)
368                                 flag = TTY_BREAK;
369                         else if (CharNStat & STMPARITYH)
370                                 flag = TTY_PARITY;
371                         else if (CharNStat & STMFRAMEH)
372                                 flag = TTY_FRAME;
373                         else if (CharNStat & STMRCVROVRH)
374                                 flag = TTY_OVERRUN;
375                         else
376                                 flag = TTY_NORMAL;
377                         tty_insert_flip_char(&info->port, CharNStat & 0xff,
378                                         flag);
379                         ToRecv--;
380                 }
381 
382                 /*
383                  * after we've emptied the FIFO in status mode, turn
384                  * status mode back off
385                  */
386                 if (sGetRxCnt(cp) == 0) {
387 #ifdef ROCKET_DEBUG_RECEIVE
388                         printk(KERN_INFO "Status mode off.\n");
389 #endif
390                         sDisRxStatusMode(cp);
391                 }
392         } else {
393                 /*
394                  * we aren't in status mode, so read down the FIFO two
395                  * characters at time by doing repeated word IO
396                  * transfer.
397                  */
398                 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
399                 if (space < ToRecv) {
400 #ifdef ROCKET_DEBUG_RECEIVE
401                         printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
402 #endif
403                         if (space <= 0)
404                                 return;
405                         ToRecv = space;
406                 }
407                 wRecv = ToRecv >> 1;
408                 if (wRecv)
409                         sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
410                 if (ToRecv & 1)
411                         cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
412         }
413         /*  Push the data up to the tty layer */
414         tty_flip_buffer_push(&info->port);
415 }
416 
417 /*
418  *  Serial port transmit data function.  Called from the timer polling loop as a 
419  *  result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
420  *  to be sent out the serial port.  Data is buffered in rp_table[line].xmit_buf, it is 
421  *  moved to the port's xmit FIFO.  *info is critical data, protected by spinlocks.
422  */
423 static void rp_do_transmit(struct r_port *info)
424 {
425         int c;
426         CHANNEL_t *cp = &info->channel;
427         struct tty_struct *tty;
428         unsigned long flags;
429 
430 #ifdef ROCKET_DEBUG_INTR
431         printk(KERN_DEBUG "%s\n", __func__);
432 #endif
433         if (!info)
434                 return;
435         tty = tty_port_tty_get(&info->port);
436 
437         if (tty == NULL) {
438                 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
439                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
440                 return;
441         }
442 
443         spin_lock_irqsave(&info->slock, flags);
444         info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
445 
446         /*  Loop sending data to FIFO until done or FIFO full */
447         while (1) {
448                 if (tty->stopped)
449                         break;
450                 c = min(info->xmit_fifo_room, info->xmit_cnt);
451                 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
452                 if (c <= 0 || info->xmit_fifo_room <= 0)
453                         break;
454                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
455                 if (c & 1)
456                         sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
457                 info->xmit_tail += c;
458                 info->xmit_tail &= XMIT_BUF_SIZE - 1;
459                 info->xmit_cnt -= c;
460                 info->xmit_fifo_room -= c;
461 #ifdef ROCKET_DEBUG_INTR
462                 printk(KERN_INFO "tx %d chars...\n", c);
463 #endif
464         }
465 
466         if (info->xmit_cnt == 0)
467                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
468 
469         if (info->xmit_cnt < WAKEUP_CHARS) {
470                 tty_wakeup(tty);
471 #ifdef ROCKETPORT_HAVE_POLL_WAIT
472                 wake_up_interruptible(&tty->poll_wait);
473 #endif
474         }
475 
476         spin_unlock_irqrestore(&info->slock, flags);
477         tty_kref_put(tty);
478 
479 #ifdef ROCKET_DEBUG_INTR
480         printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
481                info->xmit_tail, info->xmit_fifo_room);
482 #endif
483 }
484 
485 /*
486  *  Called when a serial port signals it has read data in it's RX FIFO.
487  *  It checks what interrupts are pending and services them, including
488  *  receiving serial data.  
489  */
490 static void rp_handle_port(struct r_port *info)
491 {
492         CHANNEL_t *cp;
493         unsigned int IntMask, ChanStatus;
494 
495         if (!info)
496                 return;
497 
498         if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
499                 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
500                                 "info->flags & NOT_INIT\n");
501                 return;
502         }
503 
504         cp = &info->channel;
505 
506         IntMask = sGetChanIntID(cp) & info->intmask;
507 #ifdef ROCKET_DEBUG_INTR
508         printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
509 #endif
510         ChanStatus = sGetChanStatus(cp);
511         if (IntMask & RXF_TRIG) {       /* Rx FIFO trigger level */
512                 rp_do_receive(info, cp, ChanStatus);
513         }
514         if (IntMask & DELTA_CD) {       /* CD change  */
515 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
516                 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
517                        (ChanStatus & CD_ACT) ? "on" : "off");
518 #endif
519                 if (!(ChanStatus & CD_ACT) && info->cd_status) {
520 #ifdef ROCKET_DEBUG_HANGUP
521                         printk(KERN_INFO "CD drop, calling hangup.\n");
522 #endif
523                         tty_port_tty_hangup(&info->port, false);
524                 }
525                 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
526                 wake_up_interruptible(&info->port.open_wait);
527         }
528 #ifdef ROCKET_DEBUG_INTR
529         if (IntMask & DELTA_CTS) {      /* CTS change */
530                 printk(KERN_INFO "CTS change...\n");
531         }
532         if (IntMask & DELTA_DSR) {      /* DSR change */
533                 printk(KERN_INFO "DSR change...\n");
534         }
535 #endif
536 }
537 
538 /*
539  *  The top level polling routine.  Repeats every 1/100 HZ (10ms).
540  */
541 static void rp_do_poll(unsigned long dummy)
542 {
543         CONTROLLER_t *ctlp;
544         int ctrl, aiop, ch, line;
545         unsigned int xmitmask, i;
546         unsigned int CtlMask;
547         unsigned char AiopMask;
548         Word_t bit;
549 
550         /*  Walk through all the boards (ctrl's) */
551         for (ctrl = 0; ctrl < max_board; ctrl++) {
552                 if (rcktpt_io_addr[ctrl] <= 0)
553                         continue;
554 
555                 /*  Get a ptr to the board's control struct */
556                 ctlp = sCtlNumToCtlPtr(ctrl);
557 
558                 /*  Get the interrupt status from the board */
559 #ifdef CONFIG_PCI
560                 if (ctlp->BusType == isPCI)
561                         CtlMask = sPCIGetControllerIntStatus(ctlp);
562                 else
563 #endif
564                         CtlMask = sGetControllerIntStatus(ctlp);
565 
566                 /*  Check if any AIOP read bits are set */
567                 for (aiop = 0; CtlMask; aiop++) {
568                         bit = ctlp->AiopIntrBits[aiop];
569                         if (CtlMask & bit) {
570                                 CtlMask &= ~bit;
571                                 AiopMask = sGetAiopIntStatus(ctlp, aiop);
572 
573                                 /*  Check if any port read bits are set */
574                                 for (ch = 0; AiopMask;  AiopMask >>= 1, ch++) {
575                                         if (AiopMask & 1) {
576 
577                                                 /*  Get the line number (/dev/ttyRx number). */
578                                                 /*  Read the data from the port. */
579                                                 line = GetLineNumber(ctrl, aiop, ch);
580                                                 rp_handle_port(rp_table[line]);
581                                         }
582                                 }
583                         }
584                 }
585 
586                 xmitmask = xmit_flags[ctrl];
587 
588                 /*
589                  *  xmit_flags contains bit-significant flags, indicating there is data
590                  *  to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port 
591                  *  1, ... (32 total possible).  The variable i has the aiop and ch 
592                  *  numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
593                  */
594                 if (xmitmask) {
595                         for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
596                                 if (xmitmask & (1 << i)) {
597                                         aiop = (i & 0x18) >> 3;
598                                         ch = i & 0x07;
599                                         line = GetLineNumber(ctrl, aiop, ch);
600                                         rp_do_transmit(rp_table[line]);
601                                 }
602                         }
603                 }
604         }
605 
606         /*
607          * Reset the timer so we get called at the next clock tick (10ms).
608          */
609         if (atomic_read(&rp_num_ports_open))
610                 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
611 }
612 
613 /*
614  *  Initializes the r_port structure for a port, as well as enabling the port on 
615  *  the board.  
616  *  Inputs:  board, aiop, chan numbers
617  */
618 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
619 {
620         unsigned rocketMode;
621         struct r_port *info;
622         int line;
623         CONTROLLER_T *ctlp;
624 
625         /*  Get the next available line number */
626         line = SetLineNumber(board, aiop, chan);
627 
628         ctlp = sCtlNumToCtlPtr(board);
629 
630         /*  Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
631         info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
632         if (!info) {
633                 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
634                                 line);
635                 return;
636         }
637 
638         info->magic = RPORT_MAGIC;
639         info->line = line;
640         info->ctlp = ctlp;
641         info->board = board;
642         info->aiop = aiop;
643         info->chan = chan;
644         tty_port_init(&info->port);
645         info->port.ops = &rocket_port_ops;
646         init_completion(&info->close_wait);
647         info->flags &= ~ROCKET_MODE_MASK;
648         switch (pc104[board][line]) {
649         case 422:
650                 info->flags |= ROCKET_MODE_RS422;
651                 break;
652         case 485:
653                 info->flags |= ROCKET_MODE_RS485;
654                 break;
655         case 232:
656         default:
657                 info->flags |= ROCKET_MODE_RS232;
658                 break;
659         }
660 
661         info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
662         if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
663                 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
664                                 board, aiop, chan);
665                 tty_port_destroy(&info->port);
666                 kfree(info);
667                 return;
668         }
669 
670         rocketMode = info->flags & ROCKET_MODE_MASK;
671 
672         if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
673                 sEnRTSToggle(&info->channel);
674         else
675                 sDisRTSToggle(&info->channel);
676 
677         if (ctlp->boardType == ROCKET_TYPE_PC104) {
678                 switch (rocketMode) {
679                 case ROCKET_MODE_RS485:
680                         sSetInterfaceMode(&info->channel, InterfaceModeRS485);
681                         break;
682                 case ROCKET_MODE_RS422:
683                         sSetInterfaceMode(&info->channel, InterfaceModeRS422);
684                         break;
685                 case ROCKET_MODE_RS232:
686                 default:
687                         if (info->flags & ROCKET_RTS_TOGGLE)
688                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
689                         else
690                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
691                         break;
692                 }
693         }
694         spin_lock_init(&info->slock);
695         mutex_init(&info->write_mtx);
696         rp_table[line] = info;
697         tty_port_register_device(&info->port, rocket_driver, line,
698                         pci_dev ? &pci_dev->dev : NULL);
699 }
700 
701 /*
702  *  Configures a rocketport port according to its termio settings.  Called from 
703  *  user mode into the driver (exception handler).  *info CD manipulation is spinlock protected.
704  */
705 static void configure_r_port(struct tty_struct *tty, struct r_port *info,
706                              struct ktermios *old_termios)
707 {
708         unsigned cflag;
709         unsigned long flags;
710         unsigned rocketMode;
711         int bits, baud, divisor;
712         CHANNEL_t *cp;
713         struct ktermios *t = &tty->termios;
714 
715         cp = &info->channel;
716         cflag = t->c_cflag;
717 
718         /* Byte size and parity */
719         if ((cflag & CSIZE) == CS8) {
720                 sSetData8(cp);
721                 bits = 10;
722         } else {
723                 sSetData7(cp);
724                 bits = 9;
725         }
726         if (cflag & CSTOPB) {
727                 sSetStop2(cp);
728                 bits++;
729         } else {
730                 sSetStop1(cp);
731         }
732 
733         if (cflag & PARENB) {
734                 sEnParity(cp);
735                 bits++;
736                 if (cflag & PARODD) {
737                         sSetOddParity(cp);
738                 } else {
739                         sSetEvenParity(cp);
740                 }
741         } else {
742                 sDisParity(cp);
743         }
744 
745         /* baud rate */
746         baud = tty_get_baud_rate(tty);
747         if (!baud)
748                 baud = 9600;
749         divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
750         if ((divisor >= 8192 || divisor < 0) && old_termios) {
751                 baud = tty_termios_baud_rate(old_termios);
752                 if (!baud)
753                         baud = 9600;
754                 divisor = (rp_baud_base[info->board] / baud) - 1;
755         }
756         if (divisor >= 8192 || divisor < 0) {
757                 baud = 9600;
758                 divisor = (rp_baud_base[info->board] / baud) - 1;
759         }
760         info->cps = baud / bits;
761         sSetBaud(cp, divisor);
762 
763         /* FIXME: Should really back compute a baud rate from the divisor */
764         tty_encode_baud_rate(tty, baud, baud);
765 
766         if (cflag & CRTSCTS) {
767                 info->intmask |= DELTA_CTS;
768                 sEnCTSFlowCtl(cp);
769         } else {
770                 info->intmask &= ~DELTA_CTS;
771                 sDisCTSFlowCtl(cp);
772         }
773         if (cflag & CLOCAL) {
774                 info->intmask &= ~DELTA_CD;
775         } else {
776                 spin_lock_irqsave(&info->slock, flags);
777                 if (sGetChanStatus(cp) & CD_ACT)
778                         info->cd_status = 1;
779                 else
780                         info->cd_status = 0;
781                 info->intmask |= DELTA_CD;
782                 spin_unlock_irqrestore(&info->slock, flags);
783         }
784 
785         /*
786          * Handle software flow control in the board
787          */
788 #ifdef ROCKET_SOFT_FLOW
789         if (I_IXON(tty)) {
790                 sEnTxSoftFlowCtl(cp);
791                 if (I_IXANY(tty)) {
792                         sEnIXANY(cp);
793                 } else {
794                         sDisIXANY(cp);
795                 }
796                 sSetTxXONChar(cp, START_CHAR(tty));
797                 sSetTxXOFFChar(cp, STOP_CHAR(tty));
798         } else {
799                 sDisTxSoftFlowCtl(cp);
800                 sDisIXANY(cp);
801                 sClrTxXOFF(cp);
802         }
803 #endif
804 
805         /*
806          * Set up ignore/read mask words
807          */
808         info->read_status_mask = STMRCVROVRH | 0xFF;
809         if (I_INPCK(tty))
810                 info->read_status_mask |= STMFRAMEH | STMPARITYH;
811         if (I_BRKINT(tty) || I_PARMRK(tty))
812                 info->read_status_mask |= STMBREAKH;
813 
814         /*
815          * Characters to ignore
816          */
817         info->ignore_status_mask = 0;
818         if (I_IGNPAR(tty))
819                 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
820         if (I_IGNBRK(tty)) {
821                 info->ignore_status_mask |= STMBREAKH;
822                 /*
823                  * If we're ignoring parity and break indicators,
824                  * ignore overruns too.  (For real raw support).
825                  */
826                 if (I_IGNPAR(tty))
827                         info->ignore_status_mask |= STMRCVROVRH;
828         }
829 
830         rocketMode = info->flags & ROCKET_MODE_MASK;
831 
832         if ((info->flags & ROCKET_RTS_TOGGLE)
833             || (rocketMode == ROCKET_MODE_RS485))
834                 sEnRTSToggle(cp);
835         else
836                 sDisRTSToggle(cp);
837 
838         sSetRTS(&info->channel);
839 
840         if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
841                 switch (rocketMode) {
842                 case ROCKET_MODE_RS485:
843                         sSetInterfaceMode(cp, InterfaceModeRS485);
844                         break;
845                 case ROCKET_MODE_RS422:
846                         sSetInterfaceMode(cp, InterfaceModeRS422);
847                         break;
848                 case ROCKET_MODE_RS232:
849                 default:
850                         if (info->flags & ROCKET_RTS_TOGGLE)
851                                 sSetInterfaceMode(cp, InterfaceModeRS232T);
852                         else
853                                 sSetInterfaceMode(cp, InterfaceModeRS232);
854                         break;
855                 }
856         }
857 }
858 
859 static int carrier_raised(struct tty_port *port)
860 {
861         struct r_port *info = container_of(port, struct r_port, port);
862         return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
863 }
864 
865 static void dtr_rts(struct tty_port *port, int on)
866 {
867         struct r_port *info = container_of(port, struct r_port, port);
868         if (on) {
869                 sSetDTR(&info->channel);
870                 sSetRTS(&info->channel);
871         } else {
872                 sClrDTR(&info->channel);
873                 sClrRTS(&info->channel);
874         }
875 }
876 
877 /*
878  *  Exception handler that opens a serial port.  Creates xmit_buf storage, fills in 
879  *  port's r_port struct.  Initializes the port hardware.  
880  */
881 static int rp_open(struct tty_struct *tty, struct file *filp)
882 {
883         struct r_port *info;
884         struct tty_port *port;
885         int retval;
886         CHANNEL_t *cp;
887         unsigned long page;
888 
889         info = rp_table[tty->index];
890         if (info == NULL)
891                 return -ENXIO;
892         port = &info->port;
893         
894         page = __get_free_page(GFP_KERNEL);
895         if (!page)
896                 return -ENOMEM;
897 
898         if (port->flags & ASYNC_CLOSING) {
899                 retval = wait_for_completion_interruptible(&info->close_wait);
900                 free_page(page);
901                 if (retval)
902                         return retval;
903                 return ((port->flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
904         }
905 
906         /*
907          * We must not sleep from here until the port is marked fully in use.
908          */
909         if (info->xmit_buf)
910                 free_page(page);
911         else
912                 info->xmit_buf = (unsigned char *) page;
913 
914         tty->driver_data = info;
915         tty_port_tty_set(port, tty);
916 
917         if (port->count++ == 0) {
918                 atomic_inc(&rp_num_ports_open);
919 
920 #ifdef ROCKET_DEBUG_OPEN
921                 printk(KERN_INFO "rocket mod++ = %d...\n",
922                                 atomic_read(&rp_num_ports_open));
923 #endif
924         }
925 #ifdef ROCKET_DEBUG_OPEN
926         printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
927 #endif
928 
929         /*
930          * Info->count is now 1; so it's safe to sleep now.
931          */
932         if (!test_bit(ASYNCB_INITIALIZED, &port->flags)) {
933                 cp = &info->channel;
934                 sSetRxTrigger(cp, TRIG_1);
935                 if (sGetChanStatus(cp) & CD_ACT)
936                         info->cd_status = 1;
937                 else
938                         info->cd_status = 0;
939                 sDisRxStatusMode(cp);
940                 sFlushRxFIFO(cp);
941                 sFlushTxFIFO(cp);
942 
943                 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
944                 sSetRxTrigger(cp, TRIG_1);
945 
946                 sGetChanStatus(cp);
947                 sDisRxStatusMode(cp);
948                 sClrTxXOFF(cp);
949 
950                 sDisCTSFlowCtl(cp);
951                 sDisTxSoftFlowCtl(cp);
952 
953                 sEnRxFIFO(cp);
954                 sEnTransmit(cp);
955 
956                 set_bit(ASYNCB_INITIALIZED, &info->port.flags);
957 
958                 /*
959                  * Set up the tty->alt_speed kludge
960                  */
961                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
962                         tty->alt_speed = 57600;
963                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
964                         tty->alt_speed = 115200;
965                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
966                         tty->alt_speed = 230400;
967                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
968                         tty->alt_speed = 460800;
969 
970                 configure_r_port(tty, info, NULL);
971                 if (tty->termios.c_cflag & CBAUD) {
972                         sSetDTR(cp);
973                         sSetRTS(cp);
974                 }
975         }
976         /*  Starts (or resets) the maint polling loop */
977         mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
978 
979         retval = tty_port_block_til_ready(port, tty, filp);
980         if (retval) {
981 #ifdef ROCKET_DEBUG_OPEN
982                 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
983 #endif
984                 return retval;
985         }
986         return 0;
987 }
988 
989 /*
990  *  Exception handler that closes a serial port. info->port.count is considered critical.
991  */
992 static void rp_close(struct tty_struct *tty, struct file *filp)
993 {
994         struct r_port *info = tty->driver_data;
995         struct tty_port *port = &info->port;
996         int timeout;
997         CHANNEL_t *cp;
998         
999         if (rocket_paranoia_check(info, "rp_close"))
1000                 return;
1001 
1002 #ifdef ROCKET_DEBUG_OPEN
1003         printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1004 #endif
1005 
1006         if (tty_port_close_start(port, tty, filp) == 0)
1007                 return;
1008 
1009         mutex_lock(&port->mutex);
1010         cp = &info->channel;
1011         /*
1012          * Before we drop DTR, make sure the UART transmitter
1013          * has completely drained; this is especially
1014          * important if there is a transmit FIFO!
1015          */
1016         timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1017         if (timeout == 0)
1018                 timeout = 1;
1019         rp_wait_until_sent(tty, timeout);
1020         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1021 
1022         sDisTransmit(cp);
1023         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1024         sDisCTSFlowCtl(cp);
1025         sDisTxSoftFlowCtl(cp);
1026         sClrTxXOFF(cp);
1027         sFlushRxFIFO(cp);
1028         sFlushTxFIFO(cp);
1029         sClrRTS(cp);
1030         if (C_HUPCL(tty))
1031                 sClrDTR(cp);
1032 
1033         rp_flush_buffer(tty);
1034                 
1035         tty_ldisc_flush(tty);
1036 
1037         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1038 
1039         /* We can't yet use tty_port_close_end as the buffer handling in this
1040            driver is a bit different to the usual */
1041 
1042         if (port->blocked_open) {
1043                 if (port->close_delay) {
1044                         msleep_interruptible(jiffies_to_msecs(port->close_delay));
1045                 }
1046                 wake_up_interruptible(&port->open_wait);
1047         } else {
1048                 if (info->xmit_buf) {
1049                         free_page((unsigned long) info->xmit_buf);
1050                         info->xmit_buf = NULL;
1051                 }
1052         }
1053         spin_lock_irq(&port->lock);
1054         info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_CLOSING | ASYNC_NORMAL_ACTIVE);
1055         tty->closing = 0;
1056         spin_unlock_irq(&port->lock);
1057         mutex_unlock(&port->mutex);
1058         tty_port_tty_set(port, NULL);
1059 
1060         wake_up_interruptible(&port->close_wait);
1061         complete_all(&info->close_wait);
1062         atomic_dec(&rp_num_ports_open);
1063 
1064 #ifdef ROCKET_DEBUG_OPEN
1065         printk(KERN_INFO "rocket mod-- = %d...\n",
1066                         atomic_read(&rp_num_ports_open));
1067         printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1068 #endif
1069 
1070 }
1071 
1072 static void rp_set_termios(struct tty_struct *tty,
1073                            struct ktermios *old_termios)
1074 {
1075         struct r_port *info = tty->driver_data;
1076         CHANNEL_t *cp;
1077         unsigned cflag;
1078 
1079         if (rocket_paranoia_check(info, "rp_set_termios"))
1080                 return;
1081 
1082         cflag = tty->termios.c_cflag;
1083 
1084         /*
1085          * This driver doesn't support CS5 or CS6
1086          */
1087         if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1088                 tty->termios.c_cflag =
1089                     ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1090         /* Or CMSPAR */
1091         tty->termios.c_cflag &= ~CMSPAR;
1092 
1093         configure_r_port(tty, info, old_termios);
1094 
1095         cp = &info->channel;
1096 
1097         /* Handle transition to B0 status */
1098         if ((old_termios->c_cflag & CBAUD) && !(tty->termios.c_cflag & CBAUD)) {
1099                 sClrDTR(cp);
1100                 sClrRTS(cp);
1101         }
1102 
1103         /* Handle transition away from B0 status */
1104         if (!(old_termios->c_cflag & CBAUD) && (tty->termios.c_cflag & CBAUD)) {
1105                 sSetRTS(cp);
1106                 sSetDTR(cp);
1107         }
1108 
1109         if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios.c_cflag & CRTSCTS))
1110                 rp_start(tty);
1111 }
1112 
1113 static int rp_break(struct tty_struct *tty, int break_state)
1114 {
1115         struct r_port *info = tty->driver_data;
1116         unsigned long flags;
1117 
1118         if (rocket_paranoia_check(info, "rp_break"))
1119                 return -EINVAL;
1120 
1121         spin_lock_irqsave(&info->slock, flags);
1122         if (break_state == -1)
1123                 sSendBreak(&info->channel);
1124         else
1125                 sClrBreak(&info->channel);
1126         spin_unlock_irqrestore(&info->slock, flags);
1127         return 0;
1128 }
1129 
1130 /*
1131  * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1132  * the UPCI boards was added, it was decided to make this a function because
1133  * the macro was getting too complicated. All cases except the first one
1134  * (UPCIRingInd) are taken directly from the original macro.
1135  */
1136 static int sGetChanRI(CHANNEL_T * ChP)
1137 {
1138         CONTROLLER_t *CtlP = ChP->CtlP;
1139         int ChanNum = ChP->ChanNum;
1140         int RingInd = 0;
1141 
1142         if (CtlP->UPCIRingInd)
1143                 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1144         else if (CtlP->AltChanRingIndicator)
1145                 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1146         else if (CtlP->boardType == ROCKET_TYPE_PC104)
1147                 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1148 
1149         return RingInd;
1150 }
1151 
1152 /********************************************************************************************/
1153 /*  Here are the routines used by rp_ioctl.  These are all called from exception handlers.  */
1154 
1155 /*
1156  *  Returns the state of the serial modem control lines.  These next 2 functions 
1157  *  are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1158  */
1159 static int rp_tiocmget(struct tty_struct *tty)
1160 {
1161         struct r_port *info = tty->driver_data;
1162         unsigned int control, result, ChanStatus;
1163 
1164         ChanStatus = sGetChanStatusLo(&info->channel);
1165         control = info->channel.TxControl[3];
1166         result = ((control & SET_RTS) ? TIOCM_RTS : 0) | 
1167                 ((control & SET_DTR) ?  TIOCM_DTR : 0) |
1168                 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1169                 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1170                 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1171                 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1172 
1173         return result;
1174 }
1175 
1176 /* 
1177  *  Sets the modem control lines
1178  */
1179 static int rp_tiocmset(struct tty_struct *tty,
1180                                 unsigned int set, unsigned int clear)
1181 {
1182         struct r_port *info = tty->driver_data;
1183 
1184         if (set & TIOCM_RTS)
1185                 info->channel.TxControl[3] |= SET_RTS;
1186         if (set & TIOCM_DTR)
1187                 info->channel.TxControl[3] |= SET_DTR;
1188         if (clear & TIOCM_RTS)
1189                 info->channel.TxControl[3] &= ~SET_RTS;
1190         if (clear & TIOCM_DTR)
1191                 info->channel.TxControl[3] &= ~SET_DTR;
1192 
1193         out32(info->channel.IndexAddr, info->channel.TxControl);
1194         return 0;
1195 }
1196 
1197 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1198 {
1199         struct rocket_config tmp;
1200 
1201         if (!retinfo)
1202                 return -EFAULT;
1203         memset(&tmp, 0, sizeof (tmp));
1204         mutex_lock(&info->port.mutex);
1205         tmp.line = info->line;
1206         tmp.flags = info->flags;
1207         tmp.close_delay = info->port.close_delay;
1208         tmp.closing_wait = info->port.closing_wait;
1209         tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1210         mutex_unlock(&info->port.mutex);
1211 
1212         if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1213                 return -EFAULT;
1214         return 0;
1215 }
1216 
1217 static int set_config(struct tty_struct *tty, struct r_port *info,
1218                                         struct rocket_config __user *new_info)
1219 {
1220         struct rocket_config new_serial;
1221 
1222         if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1223                 return -EFAULT;
1224 
1225         mutex_lock(&info->port.mutex);
1226         if (!capable(CAP_SYS_ADMIN))
1227         {
1228                 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1229                         mutex_unlock(&info->port.mutex);
1230                         return -EPERM;
1231                 }
1232                 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1233                 configure_r_port(tty, info, NULL);
1234                 mutex_unlock(&info->port.mutex);
1235                 return 0;
1236         }
1237 
1238         info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1239         info->port.close_delay = new_serial.close_delay;
1240         info->port.closing_wait = new_serial.closing_wait;
1241 
1242         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1243                 tty->alt_speed = 57600;
1244         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1245                 tty->alt_speed = 115200;
1246         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1247                 tty->alt_speed = 230400;
1248         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1249                 tty->alt_speed = 460800;
1250         mutex_unlock(&info->port.mutex);
1251 
1252         configure_r_port(tty, info, NULL);
1253         return 0;
1254 }
1255 
1256 /*
1257  *  This function fills in a rocket_ports struct with information
1258  *  about what boards/ports are in the system.  This info is passed
1259  *  to user space.  See setrocket.c where the info is used to create
1260  *  the /dev/ttyRx ports.
1261  */
1262 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1263 {
1264         struct rocket_ports tmp;
1265         int board;
1266 
1267         if (!retports)
1268                 return -EFAULT;
1269         memset(&tmp, 0, sizeof (tmp));
1270         tmp.tty_major = rocket_driver->major;
1271 
1272         for (board = 0; board < 4; board++) {
1273                 tmp.rocketModel[board].model = rocketModel[board].model;
1274                 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1275                 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1276                 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1277                 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1278         }
1279         if (copy_to_user(retports, &tmp, sizeof (*retports)))
1280                 return -EFAULT;
1281         return 0;
1282 }
1283 
1284 static int reset_rm2(struct r_port *info, void __user *arg)
1285 {
1286         int reset;
1287 
1288         if (!capable(CAP_SYS_ADMIN))
1289                 return -EPERM;
1290 
1291         if (copy_from_user(&reset, arg, sizeof (int)))
1292                 return -EFAULT;
1293         if (reset)
1294                 reset = 1;
1295 
1296         if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1297             rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1298                 return -EINVAL;
1299 
1300         if (info->ctlp->BusType == isISA)
1301                 sModemReset(info->ctlp, info->chan, reset);
1302         else
1303                 sPCIModemReset(info->ctlp, info->chan, reset);
1304 
1305         return 0;
1306 }
1307 
1308 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1309 {
1310         if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1311                 return -EFAULT;
1312         return 0;
1313 }
1314 
1315 /*  IOCTL call handler into the driver */
1316 static int rp_ioctl(struct tty_struct *tty,
1317                     unsigned int cmd, unsigned long arg)
1318 {
1319         struct r_port *info = tty->driver_data;
1320         void __user *argp = (void __user *)arg;
1321         int ret = 0;
1322 
1323         if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1324                 return -ENXIO;
1325 
1326         switch (cmd) {
1327         case RCKP_GET_STRUCT:
1328                 if (copy_to_user(argp, info, sizeof (struct r_port)))
1329                         ret = -EFAULT;
1330                 break;
1331         case RCKP_GET_CONFIG:
1332                 ret = get_config(info, argp);
1333                 break;
1334         case RCKP_SET_CONFIG:
1335                 ret = set_config(tty, info, argp);
1336                 break;
1337         case RCKP_GET_PORTS:
1338                 ret = get_ports(info, argp);
1339                 break;
1340         case RCKP_RESET_RM2:
1341                 ret = reset_rm2(info, argp);
1342                 break;
1343         case RCKP_GET_VERSION:
1344                 ret = get_version(info, argp);
1345                 break;
1346         default:
1347                 ret = -ENOIOCTLCMD;
1348         }
1349         return ret;
1350 }
1351 
1352 static void rp_send_xchar(struct tty_struct *tty, char ch)
1353 {
1354         struct r_port *info = tty->driver_data;
1355         CHANNEL_t *cp;
1356 
1357         if (rocket_paranoia_check(info, "rp_send_xchar"))
1358                 return;
1359 
1360         cp = &info->channel;
1361         if (sGetTxCnt(cp))
1362                 sWriteTxPrioByte(cp, ch);
1363         else
1364                 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1365 }
1366 
1367 static void rp_throttle(struct tty_struct *tty)
1368 {
1369         struct r_port *info = tty->driver_data;
1370 
1371 #ifdef ROCKET_DEBUG_THROTTLE
1372         printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1373                tty->ldisc.chars_in_buffer(tty));
1374 #endif
1375 
1376         if (rocket_paranoia_check(info, "rp_throttle"))
1377                 return;
1378 
1379         if (I_IXOFF(tty))
1380                 rp_send_xchar(tty, STOP_CHAR(tty));
1381 
1382         sClrRTS(&info->channel);
1383 }
1384 
1385 static void rp_unthrottle(struct tty_struct *tty)
1386 {
1387         struct r_port *info = tty->driver_data;
1388 #ifdef ROCKET_DEBUG_THROTTLE
1389         printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1390                tty->ldisc.chars_in_buffer(tty));
1391 #endif
1392 
1393         if (rocket_paranoia_check(info, "rp_throttle"))
1394                 return;
1395 
1396         if (I_IXOFF(tty))
1397                 rp_send_xchar(tty, START_CHAR(tty));
1398 
1399         sSetRTS(&info->channel);
1400 }
1401 
1402 /*
1403  * ------------------------------------------------------------
1404  * rp_stop() and rp_start()
1405  *
1406  * This routines are called before setting or resetting tty->stopped.
1407  * They enable or disable transmitter interrupts, as necessary.
1408  * ------------------------------------------------------------
1409  */
1410 static void rp_stop(struct tty_struct *tty)
1411 {
1412         struct r_port *info = tty->driver_data;
1413 
1414 #ifdef ROCKET_DEBUG_FLOW
1415         printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1416                info->xmit_cnt, info->xmit_fifo_room);
1417 #endif
1418 
1419         if (rocket_paranoia_check(info, "rp_stop"))
1420                 return;
1421 
1422         if (sGetTxCnt(&info->channel))
1423                 sDisTransmit(&info->channel);
1424 }
1425 
1426 static void rp_start(struct tty_struct *tty)
1427 {
1428         struct r_port *info = tty->driver_data;
1429 
1430 #ifdef ROCKET_DEBUG_FLOW
1431         printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1432                info->xmit_cnt, info->xmit_fifo_room);
1433 #endif
1434 
1435         if (rocket_paranoia_check(info, "rp_stop"))
1436                 return;
1437 
1438         sEnTransmit(&info->channel);
1439         set_bit((info->aiop * 8) + info->chan,
1440                 (void *) &xmit_flags[info->board]);
1441 }
1442 
1443 /*
1444  * rp_wait_until_sent() --- wait until the transmitter is empty
1445  */
1446 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1447 {
1448         struct r_port *info = tty->driver_data;
1449         CHANNEL_t *cp;
1450         unsigned long orig_jiffies;
1451         int check_time, exit_time;
1452         int txcnt;
1453 
1454         if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1455                 return;
1456 
1457         cp = &info->channel;
1458 
1459         orig_jiffies = jiffies;
1460 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1461         printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1462                jiffies);
1463         printk(KERN_INFO "cps=%d...\n", info->cps);
1464 #endif
1465         while (1) {
1466                 txcnt = sGetTxCnt(cp);
1467                 if (!txcnt) {
1468                         if (sGetChanStatusLo(cp) & TXSHRMT)
1469                                 break;
1470                         check_time = (HZ / info->cps) / 5;
1471                 } else {
1472                         check_time = HZ * txcnt / info->cps;
1473                 }
1474                 if (timeout) {
1475                         exit_time = orig_jiffies + timeout - jiffies;
1476                         if (exit_time <= 0)
1477                                 break;
1478                         if (exit_time < check_time)
1479                                 check_time = exit_time;
1480                 }
1481                 if (check_time == 0)
1482                         check_time = 1;
1483 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1484                 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1485                                 jiffies, check_time);
1486 #endif
1487                 msleep_interruptible(jiffies_to_msecs(check_time));
1488                 if (signal_pending(current))
1489                         break;
1490         }
1491         __set_current_state(TASK_RUNNING);
1492 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1493         printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1494 #endif
1495 }
1496 
1497 /*
1498  * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1499  */
1500 static void rp_hangup(struct tty_struct *tty)
1501 {
1502         CHANNEL_t *cp;
1503         struct r_port *info = tty->driver_data;
1504         unsigned long flags;
1505 
1506         if (rocket_paranoia_check(info, "rp_hangup"))
1507                 return;
1508 
1509 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1510         printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1511 #endif
1512         rp_flush_buffer(tty);
1513         spin_lock_irqsave(&info->port.lock, flags);
1514         if (info->port.flags & ASYNC_CLOSING) {
1515                 spin_unlock_irqrestore(&info->port.lock, flags);
1516                 return;
1517         }
1518         if (info->port.count)
1519                 atomic_dec(&rp_num_ports_open);
1520         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1521         spin_unlock_irqrestore(&info->port.lock, flags);
1522 
1523         tty_port_hangup(&info->port);
1524 
1525         cp = &info->channel;
1526         sDisRxFIFO(cp);
1527         sDisTransmit(cp);
1528         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1529         sDisCTSFlowCtl(cp);
1530         sDisTxSoftFlowCtl(cp);
1531         sClrTxXOFF(cp);
1532         clear_bit(ASYNCB_INITIALIZED, &info->port.flags);
1533 
1534         wake_up_interruptible(&info->port.open_wait);
1535 }
1536 
1537 /*
1538  *  Exception handler - write char routine.  The RocketPort driver uses a
1539  *  double-buffering strategy, with the twist that if the in-memory CPU
1540  *  buffer is empty, and there's space in the transmit FIFO, the
1541  *  writing routines will write directly to transmit FIFO.
1542  *  Write buffer and counters protected by spinlocks
1543  */
1544 static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1545 {
1546         struct r_port *info = tty->driver_data;
1547         CHANNEL_t *cp;
1548         unsigned long flags;
1549 
1550         if (rocket_paranoia_check(info, "rp_put_char"))
1551                 return 0;
1552 
1553         /*
1554          * Grab the port write mutex, locking out other processes that try to
1555          * write to this port
1556          */
1557         mutex_lock(&info->write_mtx);
1558 
1559 #ifdef ROCKET_DEBUG_WRITE
1560         printk(KERN_INFO "rp_put_char %c...\n", ch);
1561 #endif
1562 
1563         spin_lock_irqsave(&info->slock, flags);
1564         cp = &info->channel;
1565 
1566         if (!tty->stopped && info->xmit_fifo_room == 0)
1567                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1568 
1569         if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1570                 info->xmit_buf[info->xmit_head++] = ch;
1571                 info->xmit_head &= XMIT_BUF_SIZE - 1;
1572                 info->xmit_cnt++;
1573                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1574         } else {
1575                 sOutB(sGetTxRxDataIO(cp), ch);
1576                 info->xmit_fifo_room--;
1577         }
1578         spin_unlock_irqrestore(&info->slock, flags);
1579         mutex_unlock(&info->write_mtx);
1580         return 1;
1581 }
1582 
1583 /*
1584  *  Exception handler - write routine, called when user app writes to the device.
1585  *  A per port write mutex is used to protect from another process writing to
1586  *  this port at the same time.  This other process could be running on the other CPU
1587  *  or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out). 
1588  *  Spinlocks protect the info xmit members.
1589  */
1590 static int rp_write(struct tty_struct *tty,
1591                     const unsigned char *buf, int count)
1592 {
1593         struct r_port *info = tty->driver_data;
1594         CHANNEL_t *cp;
1595         const unsigned char *b;
1596         int c, retval = 0;
1597         unsigned long flags;
1598 
1599         if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1600                 return 0;
1601 
1602         if (mutex_lock_interruptible(&info->write_mtx))
1603                 return -ERESTARTSYS;
1604 
1605 #ifdef ROCKET_DEBUG_WRITE
1606         printk(KERN_INFO "rp_write %d chars...\n", count);
1607 #endif
1608         cp = &info->channel;
1609 
1610         if (!tty->stopped && info->xmit_fifo_room < count)
1611                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1612 
1613         /*
1614          *  If the write queue for the port is empty, and there is FIFO space, stuff bytes 
1615          *  into FIFO.  Use the write queue for temp storage.
1616          */
1617         if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1618                 c = min(count, info->xmit_fifo_room);
1619                 b = buf;
1620 
1621                 /*  Push data into FIFO, 2 bytes at a time */
1622                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1623 
1624                 /*  If there is a byte remaining, write it */
1625                 if (c & 1)
1626                         sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1627 
1628                 retval += c;
1629                 buf += c;
1630                 count -= c;
1631 
1632                 spin_lock_irqsave(&info->slock, flags);
1633                 info->xmit_fifo_room -= c;
1634                 spin_unlock_irqrestore(&info->slock, flags);
1635         }
1636 
1637         /* If count is zero, we wrote it all and are done */
1638         if (!count)
1639                 goto end;
1640 
1641         /*  Write remaining data into the port's xmit_buf */
1642         while (1) {
1643                 /* Hung up ? */
1644                 if (!test_bit(ASYNCB_NORMAL_ACTIVE, &info->port.flags))
1645                         goto end;
1646                 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1647                 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1648                 if (c <= 0)
1649                         break;
1650 
1651                 b = buf;
1652                 memcpy(info->xmit_buf + info->xmit_head, b, c);
1653 
1654                 spin_lock_irqsave(&info->slock, flags);
1655                 info->xmit_head =
1656                     (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1657                 info->xmit_cnt += c;
1658                 spin_unlock_irqrestore(&info->slock, flags);
1659 
1660                 buf += c;
1661                 count -= c;
1662                 retval += c;
1663         }
1664 
1665         if ((retval > 0) && !tty->stopped)
1666                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1667         
1668 end:
1669         if (info->xmit_cnt < WAKEUP_CHARS) {
1670                 tty_wakeup(tty);
1671 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1672                 wake_up_interruptible(&tty->poll_wait);
1673 #endif
1674         }
1675         mutex_unlock(&info->write_mtx);
1676         return retval;
1677 }
1678 
1679 /*
1680  * Return the number of characters that can be sent.  We estimate
1681  * only using the in-memory transmit buffer only, and ignore the
1682  * potential space in the transmit FIFO.
1683  */
1684 static int rp_write_room(struct tty_struct *tty)
1685 {
1686         struct r_port *info = tty->driver_data;
1687         int ret;
1688 
1689         if (rocket_paranoia_check(info, "rp_write_room"))
1690                 return 0;
1691 
1692         ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1693         if (ret < 0)
1694                 ret = 0;
1695 #ifdef ROCKET_DEBUG_WRITE
1696         printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1697 #endif
1698         return ret;
1699 }
1700 
1701 /*
1702  * Return the number of characters in the buffer.  Again, this only
1703  * counts those characters in the in-memory transmit buffer.
1704  */
1705 static int rp_chars_in_buffer(struct tty_struct *tty)
1706 {
1707         struct r_port *info = tty->driver_data;
1708 
1709         if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1710                 return 0;
1711 
1712 #ifdef ROCKET_DEBUG_WRITE
1713         printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1714 #endif
1715         return info->xmit_cnt;
1716 }
1717 
1718 /*
1719  *  Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1720  *  r_port struct for the port.  Note that spinlock are used to protect info members,
1721  *  do not call this function if the spinlock is already held.
1722  */
1723 static void rp_flush_buffer(struct tty_struct *tty)
1724 {
1725         struct r_port *info = tty->driver_data;
1726         CHANNEL_t *cp;
1727         unsigned long flags;
1728 
1729         if (rocket_paranoia_check(info, "rp_flush_buffer"))
1730                 return;
1731 
1732         spin_lock_irqsave(&info->slock, flags);
1733         info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1734         spin_unlock_irqrestore(&info->slock, flags);
1735 
1736 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1737         wake_up_interruptible(&tty->poll_wait);
1738 #endif
1739         tty_wakeup(tty);
1740 
1741         cp = &info->channel;
1742         sFlushTxFIFO(cp);
1743 }
1744 
1745 #ifdef CONFIG_PCI
1746 
1747 static const struct pci_device_id rocket_pci_ids[] = {
1748         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
1749         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
1750         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
1751         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
1752         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
1753         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
1754         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
1755         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
1756         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
1757         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
1758         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
1759         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
1760         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
1761         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
1762         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
1763         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
1764         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
1765         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
1766         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
1767         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
1768         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
1769         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
1770         { }
1771 };
1772 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1773 
1774 /*  Resets the speaker controller on RocketModem II and III devices */
1775 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
1776 {
1777         ByteIO_t addr;
1778 
1779         /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
1780         if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
1781                 addr = CtlP->AiopIO[0] + 0x4F;
1782                 sOutB(addr, 0);
1783         }
1784 
1785         /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
1786         if ((model == MODEL_UPCI_RM3_8PORT)
1787             || (model == MODEL_UPCI_RM3_4PORT)) {
1788                 addr = CtlP->AiopIO[0] + 0x88;
1789                 sOutB(addr, 0);
1790         }
1791 }
1792 
1793 /***************************************************************************
1794 Function: sPCIInitController
1795 Purpose:  Initialization of controller global registers and controller
1796           structure.
1797 Call:     sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
1798                           IRQNum,Frequency,PeriodicOnly)
1799           CONTROLLER_T *CtlP; Ptr to controller structure
1800           int CtlNum; Controller number
1801           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
1802              This list must be in the order the AIOPs will be found on the
1803              controller.  Once an AIOP in the list is not found, it is
1804              assumed that there are no more AIOPs on the controller.
1805           int AiopIOListSize; Number of addresses in AiopIOList
1806           int IRQNum; Interrupt Request number.  Can be any of the following:
1807                          0: Disable global interrupts
1808                          3: IRQ 3
1809                          4: IRQ 4
1810                          5: IRQ 5
1811                          9: IRQ 9
1812                          10: IRQ 10
1813                          11: IRQ 11
1814                          12: IRQ 12
1815                          15: IRQ 15
1816           Byte_t Frequency: A flag identifying the frequency
1817                    of the periodic interrupt, can be any one of the following:
1818                       FREQ_DIS - periodic interrupt disabled
1819                       FREQ_137HZ - 137 Hertz
1820                       FREQ_69HZ - 69 Hertz
1821                       FREQ_34HZ - 34 Hertz
1822                       FREQ_17HZ - 17 Hertz
1823                       FREQ_9HZ - 9 Hertz
1824                       FREQ_4HZ - 4 Hertz
1825                    If IRQNum is set to 0 the Frequency parameter is
1826                    overidden, it is forced to a value of FREQ_DIS.
1827           int PeriodicOnly: 1 if all interrupts except the periodic
1828                                interrupt are to be blocked.
1829                             0 is both the periodic interrupt and
1830                                other channel interrupts are allowed.
1831                             If IRQNum is set to 0 the PeriodicOnly parameter is
1832                                overidden, it is forced to a value of 0.
1833 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
1834                initialization failed.
1835 
1836 Comments:
1837           If periodic interrupts are to be disabled but AIOP interrupts
1838           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1839 
1840           If interrupts are to be completely disabled set IRQNum to 0.
1841 
1842           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1843           invalid combination.
1844 
1845           This function performs initialization of global interrupt modes,
1846           but it does not actually enable global interrupts.  To enable
1847           and disable global interrupts use functions sEnGlobalInt() and
1848           sDisGlobalInt().  Enabling of global interrupts is normally not
1849           done until all other initializations are complete.
1850 
1851           Even if interrupts are globally enabled, they must also be
1852           individually enabled for each channel that is to generate
1853           interrupts.
1854 
1855 Warnings: No range checking on any of the parameters is done.
1856 
1857           No context switches are allowed while executing this function.
1858 
1859           After this function all AIOPs on the controller are disabled,
1860           they can be enabled with sEnAiop().
1861 */
1862 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
1863                               ByteIO_t * AiopIOList, int AiopIOListSize,
1864                               WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
1865                               int PeriodicOnly, int altChanRingIndicator,
1866                               int UPCIRingInd)
1867 {
1868         int i;
1869         ByteIO_t io;
1870 
1871         CtlP->AltChanRingIndicator = altChanRingIndicator;
1872         CtlP->UPCIRingInd = UPCIRingInd;
1873         CtlP->CtlNum = CtlNum;
1874         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
1875         CtlP->BusType = isPCI;  /* controller release 1 */
1876 
1877         if (ConfigIO) {
1878                 CtlP->isUPCI = 1;
1879                 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
1880                 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
1881                 CtlP->AiopIntrBits = upci_aiop_intr_bits;
1882         } else {
1883                 CtlP->isUPCI = 0;
1884                 CtlP->PCIIO =
1885                     (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
1886                 CtlP->AiopIntrBits = aiop_intr_bits;
1887         }
1888 
1889         sPCIControllerEOI(CtlP);        /* clear EOI if warm init */
1890         /* Init AIOPs */
1891         CtlP->NumAiop = 0;
1892         for (i = 0; i < AiopIOListSize; i++) {
1893                 io = AiopIOList[i];
1894                 CtlP->AiopIO[i] = (WordIO_t) io;
1895                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
1896 
1897                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
1898                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
1899                         break;  /* done looking for AIOPs */
1900 
1901                 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
1902                 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
1903                 sOutB(io + _INDX_DATA, sClockPrescale);
1904                 CtlP->NumAiop++;        /* bump count of AIOPs */
1905         }
1906 
1907         if (CtlP->NumAiop == 0)
1908                 return (-1);
1909         else
1910                 return (CtlP->NumAiop);
1911 }
1912 
1913 /*
1914  *  Called when a PCI card is found.  Retrieves and stores model information,
1915  *  init's aiopic and serial port hardware.
1916  *  Inputs:  i is the board number (0-n)
1917  */
1918 static __init int register_PCI(int i, struct pci_dev *dev)
1919 {
1920         int num_aiops, aiop, max_num_aiops, num_chan, chan;
1921         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1922         CONTROLLER_t *ctlp;
1923 
1924         int fast_clock = 0;
1925         int altChanRingIndicator = 0;
1926         int ports_per_aiop = 8;
1927         WordIO_t ConfigIO = 0;
1928         ByteIO_t UPCIRingInd = 0;
1929 
1930         if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
1931             pci_enable_device(dev))
1932                 return 0;
1933 
1934         rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1935 
1936         rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1937         rocketModel[i].loadrm2 = 0;
1938         rocketModel[i].startingPortNumber = nextLineNumber;
1939 
1940         /*  Depending on the model, set up some config variables */
1941         switch (dev->device) {
1942         case PCI_DEVICE_ID_RP4QUAD:
1943                 max_num_aiops = 1;
1944                 ports_per_aiop = 4;
1945                 rocketModel[i].model = MODEL_RP4QUAD;
1946                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1947                 rocketModel[i].numPorts = 4;
1948                 break;
1949         case PCI_DEVICE_ID_RP8OCTA:
1950                 max_num_aiops = 1;
1951                 rocketModel[i].model = MODEL_RP8OCTA;
1952                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1953                 rocketModel[i].numPorts = 8;
1954                 break;
1955         case PCI_DEVICE_ID_URP8OCTA:
1956                 max_num_aiops = 1;
1957                 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1958                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1959                 rocketModel[i].numPorts = 8;
1960                 break;
1961         case PCI_DEVICE_ID_RP8INTF:
1962                 max_num_aiops = 1;
1963                 rocketModel[i].model = MODEL_RP8INTF;
1964                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1965                 rocketModel[i].numPorts = 8;
1966                 break;
1967         case PCI_DEVICE_ID_URP8INTF:
1968                 max_num_aiops = 1;
1969                 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1970                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1971                 rocketModel[i].numPorts = 8;
1972                 break;
1973         case PCI_DEVICE_ID_RP8J:
1974                 max_num_aiops = 1;
1975                 rocketModel[i].model = MODEL_RP8J;
1976                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1977                 rocketModel[i].numPorts = 8;
1978                 break;
1979         case PCI_DEVICE_ID_RP4J:
1980                 max_num_aiops = 1;
1981                 ports_per_aiop = 4;
1982                 rocketModel[i].model = MODEL_RP4J;
1983                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1984                 rocketModel[i].numPorts = 4;
1985                 break;
1986         case PCI_DEVICE_ID_RP8SNI:
1987                 max_num_aiops = 1;
1988                 rocketModel[i].model = MODEL_RP8SNI;
1989                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1990                 rocketModel[i].numPorts = 8;
1991                 break;
1992         case PCI_DEVICE_ID_RP16SNI:
1993                 max_num_aiops = 2;
1994                 rocketModel[i].model = MODEL_RP16SNI;
1995                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1996                 rocketModel[i].numPorts = 16;
1997                 break;
1998         case PCI_DEVICE_ID_RP16INTF:
1999                 max_num_aiops = 2;
2000                 rocketModel[i].model = MODEL_RP16INTF;
2001                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
2002                 rocketModel[i].numPorts = 16;
2003                 break;
2004         case PCI_DEVICE_ID_URP16INTF:
2005                 max_num_aiops = 2;
2006                 rocketModel[i].model = MODEL_UPCI_RP16INTF;
2007                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
2008                 rocketModel[i].numPorts = 16;
2009                 break;
2010         case PCI_DEVICE_ID_CRP16INTF:
2011                 max_num_aiops = 2;
2012                 rocketModel[i].model = MODEL_CPCI_RP16INTF;
2013                 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
2014                 rocketModel[i].numPorts = 16;
2015                 break;
2016         case PCI_DEVICE_ID_RP32INTF:
2017                 max_num_aiops = 4;
2018                 rocketModel[i].model = MODEL_RP32INTF;
2019                 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
2020                 rocketModel[i].numPorts = 32;
2021                 break;
2022         case PCI_DEVICE_ID_URP32INTF:
2023                 max_num_aiops = 4;
2024                 rocketModel[i].model = MODEL_UPCI_RP32INTF;
2025                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
2026                 rocketModel[i].numPorts = 32;
2027                 break;
2028         case PCI_DEVICE_ID_RPP4:
2029                 max_num_aiops = 1;
2030                 ports_per_aiop = 4;
2031                 altChanRingIndicator++;
2032                 fast_clock++;
2033                 rocketModel[i].model = MODEL_RPP4;
2034                 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2035                 rocketModel[i].numPorts = 4;
2036                 break;
2037         case PCI_DEVICE_ID_RPP8:
2038                 max_num_aiops = 2;
2039                 ports_per_aiop = 4;
2040                 altChanRingIndicator++;
2041                 fast_clock++;
2042                 rocketModel[i].model = MODEL_RPP8;
2043                 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2044                 rocketModel[i].numPorts = 8;
2045                 break;
2046         case PCI_DEVICE_ID_RP2_232:
2047                 max_num_aiops = 1;
2048                 ports_per_aiop = 2;
2049                 altChanRingIndicator++;
2050                 fast_clock++;
2051                 rocketModel[i].model = MODEL_RP2_232;
2052                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2053                 rocketModel[i].numPorts = 2;
2054                 break;
2055         case PCI_DEVICE_ID_RP2_422:
2056                 max_num_aiops = 1;
2057                 ports_per_aiop = 2;
2058                 altChanRingIndicator++;
2059                 fast_clock++;
2060                 rocketModel[i].model = MODEL_RP2_422;
2061                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2062                 rocketModel[i].numPorts = 2;
2063                 break;
2064         case PCI_DEVICE_ID_RP6M:
2065 
2066                 max_num_aiops = 1;
2067                 ports_per_aiop = 6;
2068 
2069                 /*  If revision is 1, the rocketmodem flash must be loaded.
2070                  *  If it is 2 it is a "socketed" version. */
2071                 if (dev->revision == 1) {
2072                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2073                         rocketModel[i].loadrm2 = 1;
2074                 } else {
2075                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
2076                 }
2077 
2078                 rocketModel[i].model = MODEL_RP6M;
2079                 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2080                 rocketModel[i].numPorts = 6;
2081                 break;
2082         case PCI_DEVICE_ID_RP4M:
2083                 max_num_aiops = 1;
2084                 ports_per_aiop = 4;
2085                 if (dev->revision == 1) {
2086                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2087                         rocketModel[i].loadrm2 = 1;
2088                 } else {
2089                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
2090                 }
2091 
2092                 rocketModel[i].model = MODEL_RP4M;
2093                 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2094                 rocketModel[i].numPorts = 4;
2095                 break;
2096         default:
2097                 max_num_aiops = 0;
2098                 break;
2099         }
2100 
2101         /*
2102          * Check for UPCI boards.
2103          */
2104 
2105         switch (dev->device) {
2106         case PCI_DEVICE_ID_URP32INTF:
2107         case PCI_DEVICE_ID_URP8INTF:
2108         case PCI_DEVICE_ID_URP16INTF:
2109         case PCI_DEVICE_ID_CRP16INTF:
2110         case PCI_DEVICE_ID_URP8OCTA:
2111                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2112                 ConfigIO = pci_resource_start(dev, 1);
2113                 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2114                         UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2115 
2116                         /*
2117                          * Check for octa or quad cable.
2118                          */
2119                         if (!
2120                             (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2121                              PCI_GPIO_CTRL_8PORT)) {
2122                                 ports_per_aiop = 4;
2123                                 rocketModel[i].numPorts = 4;
2124                         }
2125                 }
2126                 break;
2127         case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2128                 max_num_aiops = 1;
2129                 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2130                 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2131                 rocketModel[i].numPorts = 8;
2132                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2133                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2134                 ConfigIO = pci_resource_start(dev, 1);
2135                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2136                 break;
2137         case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2138                 max_num_aiops = 1;
2139                 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2140                 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2141                 rocketModel[i].numPorts = 4;
2142                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2143                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2144                 ConfigIO = pci_resource_start(dev, 1);
2145                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2146                 break;
2147         default:
2148                 break;
2149         }
2150 
2151         if (fast_clock) {
2152                 sClockPrescale = 0x12;  /* mod 2 (divide by 3) */
2153                 rp_baud_base[i] = 921600;
2154         } else {
2155                 /*
2156                  * If support_low_speed is set, use the slow clock
2157                  * prescale, which supports 50 bps
2158                  */
2159                 if (support_low_speed) {
2160                         /* mod 9 (divide by 10) prescale */
2161                         sClockPrescale = 0x19;
2162                         rp_baud_base[i] = 230400;
2163                 } else {
2164                         /* mod 4 (divide by 5) prescale */
2165                         sClockPrescale = 0x14;
2166                         rp_baud_base[i] = 460800;
2167                 }
2168         }
2169 
2170         for (aiop = 0; aiop < max_num_aiops; aiop++)
2171                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2172         ctlp = sCtlNumToCtlPtr(i);
2173         num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2174         for (aiop = 0; aiop < max_num_aiops; aiop++)
2175                 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2176 
2177         dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2178                 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2179                 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2180                 rocketModel[i].startingPortNumber,
2181                 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2182 
2183         if (num_aiops <= 0) {
2184                 rcktpt_io_addr[i] = 0;
2185                 return (0);
2186         }
2187         is_PCI[i] = 1;
2188 
2189         /*  Reset the AIOPIC, init the serial ports */
2190         for (aiop = 0; aiop < num_aiops; aiop++) {
2191                 sResetAiopByNum(ctlp, aiop);
2192                 num_chan = ports_per_aiop;
2193                 for (chan = 0; chan < num_chan; chan++)
2194                         init_r_port(i, aiop, chan, dev);
2195         }
2196 
2197         /*  Rocket modems must be reset */
2198         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2199             (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2200             (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2201                 num_chan = ports_per_aiop;
2202                 for (chan = 0; chan < num_chan; chan++)
2203                         sPCIModemReset(ctlp, chan, 1);
2204                 msleep(500);
2205                 for (chan = 0; chan < num_chan; chan++)
2206                         sPCIModemReset(ctlp, chan, 0);
2207                 msleep(500);
2208                 rmSpeakerReset(ctlp, rocketModel[i].model);
2209         }
2210         return (1);
2211 }
2212 
2213 /*
2214  *  Probes for PCI cards, inits them if found
2215  *  Input:   board_found = number of ISA boards already found, or the
2216  *           starting board number
2217  *  Returns: Number of PCI boards found
2218  */
2219 static int __init init_PCI(int boards_found)
2220 {
2221         struct pci_dev *dev = NULL;
2222         int count = 0;
2223 
2224         /*  Work through the PCI device list, pulling out ours */
2225         while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2226                 if (register_PCI(count + boards_found, dev))
2227                         count++;
2228         }
2229         return (count);
2230 }
2231 
2232 #endif                          /* CONFIG_PCI */
2233 
2234 /*
2235  *  Probes for ISA cards
2236  *  Input:   i = the board number to look for
2237  *  Returns: 1 if board found, 0 else
2238  */
2239 static int __init init_ISA(int i)
2240 {
2241         int num_aiops, num_chan = 0, total_num_chan = 0;
2242         int aiop, chan;
2243         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2244         CONTROLLER_t *ctlp;
2245         char *type_string;
2246 
2247         /*  If io_addr is zero, no board configured */
2248         if (rcktpt_io_addr[i] == 0)
2249                 return (0);
2250 
2251         /*  Reserve the IO region */
2252         if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2253                 printk(KERN_ERR "Unable to reserve IO region for configured "
2254                                 "ISA RocketPort at address 0x%lx, board not "
2255                                 "installed...\n", rcktpt_io_addr[i]);
2256                 rcktpt_io_addr[i] = 0;
2257                 return (0);
2258         }
2259 
2260         ctlp = sCtlNumToCtlPtr(i);
2261 
2262         ctlp->boardType = rcktpt_type[i];
2263 
2264         switch (rcktpt_type[i]) {
2265         case ROCKET_TYPE_PC104:
2266                 type_string = "(PC104)";
2267                 break;
2268         case ROCKET_TYPE_MODEM:
2269                 type_string = "(RocketModem)";
2270                 break;
2271         case ROCKET_TYPE_MODEMII:
2272                 type_string = "(RocketModem II)";
2273                 break;
2274         default:
2275                 type_string = "";
2276                 break;
2277         }
2278 
2279         /*
2280          * If support_low_speed is set, use the slow clock prescale,
2281          * which supports 50 bps
2282          */
2283         if (support_low_speed) {
2284                 sClockPrescale = 0x19;  /* mod 9 (divide by 10) prescale */
2285                 rp_baud_base[i] = 230400;
2286         } else {
2287                 sClockPrescale = 0x14;  /* mod 4 (divide by 5) prescale */
2288                 rp_baud_base[i] = 460800;
2289         }
2290 
2291         for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2292                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2293 
2294         num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio,  MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2295 
2296         if (ctlp->boardType == ROCKET_TYPE_PC104) {
2297                 sEnAiop(ctlp, 2);       /* only one AIOPIC, but these */
2298                 sEnAiop(ctlp, 3);       /* CSels used for other stuff */
2299         }
2300 
2301         /*  If something went wrong initing the AIOP's release the ISA IO memory */
2302         if (num_aiops <= 0) {
2303                 release_region(rcktpt_io_addr[i], 64);
2304                 rcktpt_io_addr[i] = 0;
2305                 return (0);
2306         }
2307   
2308         rocketModel[i].startingPortNumber = nextLineNumber;
2309 
2310         for (aiop = 0; aiop < num_aiops; aiop++) {
2311                 sResetAiopByNum(ctlp, aiop);
2312                 sEnAiop(ctlp, aiop);
2313                 num_chan = sGetAiopNumChan(ctlp, aiop);
2314                 total_num_chan += num_chan;
2315                 for (chan = 0; chan < num_chan; chan++)
2316                         init_r_port(i, aiop, chan, NULL);
2317         }
2318         is_PCI[i] = 0;
2319         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2320                 num_chan = sGetAiopNumChan(ctlp, 0);
2321                 total_num_chan = num_chan;
2322                 for (chan = 0; chan < num_chan; chan++)
2323                         sModemReset(ctlp, chan, 1);
2324                 msleep(500);
2325                 for (chan = 0; chan < num_chan; chan++)
2326                         sModemReset(ctlp, chan, 0);
2327                 msleep(500);
2328                 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2329         } else {
2330                 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2331         }
2332         rocketModel[i].numPorts = total_num_chan;
2333         rocketModel[i].model = MODEL_ISA;
2334 
2335         printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n", 
2336                i, rcktpt_io_addr[i], num_aiops, type_string);
2337 
2338         printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2339                rocketModel[i].modelString,
2340                rocketModel[i].startingPortNumber,
2341                rocketModel[i].startingPortNumber +
2342                rocketModel[i].numPorts - 1);
2343 
2344         return (1);
2345 }
2346 
2347 static const struct tty_operations rocket_ops = {
2348         .open = rp_open,
2349         .close = rp_close,
2350         .write = rp_write,
2351         .put_char = rp_put_char,
2352         .write_room = rp_write_room,
2353         .chars_in_buffer = rp_chars_in_buffer,
2354         .flush_buffer = rp_flush_buffer,
2355         .ioctl = rp_ioctl,
2356         .throttle = rp_throttle,
2357         .unthrottle = rp_unthrottle,
2358         .set_termios = rp_set_termios,
2359         .stop = rp_stop,
2360         .start = rp_start,
2361         .hangup = rp_hangup,
2362         .break_ctl = rp_break,
2363         .send_xchar = rp_send_xchar,
2364         .wait_until_sent = rp_wait_until_sent,
2365         .tiocmget = rp_tiocmget,
2366         .tiocmset = rp_tiocmset,
2367 };
2368 
2369 static const struct tty_port_operations rocket_port_ops = {
2370         .carrier_raised = carrier_raised,
2371         .dtr_rts = dtr_rts,
2372 };
2373 
2374 /*
2375  * The module "startup" routine; it's run when the module is loaded.
2376  */
2377 static int __init rp_init(void)
2378 {
2379         int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2380 
2381         printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2382                ROCKET_VERSION, ROCKET_DATE);
2383 
2384         rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2385         if (!rocket_driver)
2386                 goto err;
2387 
2388         /*
2389          *  If board 1 is non-zero, there is at least one ISA configured.  If controller is 
2390          *  zero, use the default controller IO address of board1 + 0x40.
2391          */
2392         if (board1) {
2393                 if (controller == 0)
2394                         controller = board1 + 0x40;
2395         } else {
2396                 controller = 0;  /*  Used as a flag, meaning no ISA boards */
2397         }
2398 
2399         /*  If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2400         if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2401                 printk(KERN_ERR "Unable to reserve IO region for first "
2402                         "configured ISA RocketPort controller 0x%lx.  "
2403                         "Driver exiting\n", controller);
2404                 ret = -EBUSY;
2405                 goto err_tty;
2406         }
2407 
2408         /*  Store ISA variable retrieved from command line or .conf file. */
2409         rcktpt_io_addr[0] = board1;
2410         rcktpt_io_addr[1] = board2;
2411         rcktpt_io_addr[2] = board3;
2412         rcktpt_io_addr[3] = board4;
2413 
2414         rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2415         rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2416         rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2417         rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2418         rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2419         rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2420         rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2421         rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2422 
2423         /*
2424          * Set up the tty driver structure and then register this
2425          * driver with the tty layer.
2426          */
2427 
2428         rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2429         rocket_driver->name = "ttyR";
2430         rocket_driver->driver_name = "Comtrol RocketPort";
2431         rocket_driver->major = TTY_ROCKET_MAJOR;
2432         rocket_driver->minor_start = 0;
2433         rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2434         rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2435         rocket_driver->init_termios = tty_std_termios;
2436         rocket_driver->init_termios.c_cflag =
2437             B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2438         rocket_driver->init_termios.c_ispeed = 9600;
2439         rocket_driver->init_termios.c_ospeed = 9600;
2440 #ifdef ROCKET_SOFT_FLOW
2441         rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2442 #endif
2443         tty_set_operations(rocket_driver, &rocket_ops);
2444 
2445         ret = tty_register_driver(rocket_driver);
2446         if (ret < 0) {
2447                 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2448                 goto err_controller;
2449         }
2450 
2451 #ifdef ROCKET_DEBUG_OPEN
2452         printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2453 #endif
2454 
2455         /*
2456          *  OK, let's probe each of the controllers looking for boards.  Any boards found
2457          *  will be initialized here.
2458          */
2459         isa_boards_found = 0;
2460         pci_boards_found = 0;
2461 
2462         for (i = 0; i < NUM_BOARDS; i++) {
2463                 if (init_ISA(i))
2464                         isa_boards_found++;
2465         }
2466 
2467 #ifdef CONFIG_PCI
2468         if (isa_boards_found < NUM_BOARDS)
2469                 pci_boards_found = init_PCI(isa_boards_found);
2470 #endif
2471 
2472         max_board = pci_boards_found + isa_boards_found;
2473 
2474         if (max_board == 0) {
2475                 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2476                 ret = -ENXIO;
2477                 goto err_ttyu;
2478         }
2479 
2480         return 0;
2481 err_ttyu:
2482         tty_unregister_driver(rocket_driver);
2483 err_controller:
2484         if (controller)
2485                 release_region(controller, 4);
2486 err_tty:
2487         put_tty_driver(rocket_driver);
2488 err:
2489         return ret;
2490 }
2491 
2492 
2493 static void rp_cleanup_module(void)
2494 {
2495         int retval;
2496         int i;
2497 
2498         del_timer_sync(&rocket_timer);
2499 
2500         retval = tty_unregister_driver(rocket_driver);
2501         if (retval)
2502                 printk(KERN_ERR "Error %d while trying to unregister "
2503                        "rocketport driver\n", -retval);
2504 
2505         for (i = 0; i < MAX_RP_PORTS; i++)
2506                 if (rp_table[i]) {
2507                         tty_unregister_device(rocket_driver, i);
2508                         tty_port_destroy(&rp_table[i]->port);
2509                         kfree(rp_table[i]);
2510                 }
2511 
2512         put_tty_driver(rocket_driver);
2513 
2514         for (i = 0; i < NUM_BOARDS; i++) {
2515                 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2516                         continue;
2517                 release_region(rcktpt_io_addr[i], 64);
2518         }
2519         if (controller)
2520                 release_region(controller, 4);
2521 }
2522 
2523 /***************************************************************************
2524 Function: sInitController
2525 Purpose:  Initialization of controller global registers and controller
2526           structure.
2527 Call:     sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2528                           IRQNum,Frequency,PeriodicOnly)
2529           CONTROLLER_T *CtlP; Ptr to controller structure
2530           int CtlNum; Controller number
2531           ByteIO_t MudbacIO; Mudbac base I/O address.
2532           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2533              This list must be in the order the AIOPs will be found on the
2534              controller.  Once an AIOP in the list is not found, it is
2535              assumed that there are no more AIOPs on the controller.
2536           int AiopIOListSize; Number of addresses in AiopIOList
2537           int IRQNum; Interrupt Request number.  Can be any of the following:
2538                          0: Disable global interrupts
2539                          3: IRQ 3
2540                          4: IRQ 4
2541                          5: IRQ 5
2542                          9: IRQ 9
2543                          10: IRQ 10
2544                          11: IRQ 11
2545                          12: IRQ 12
2546                          15: IRQ 15
2547           Byte_t Frequency: A flag identifying the frequency
2548                    of the periodic interrupt, can be any one of the following:
2549                       FREQ_DIS - periodic interrupt disabled
2550                       FREQ_137HZ - 137 Hertz
2551                       FREQ_69HZ - 69 Hertz
2552                       FREQ_34HZ - 34 Hertz
2553                       FREQ_17HZ - 17 Hertz
2554                       FREQ_9HZ - 9 Hertz
2555                       FREQ_4HZ - 4 Hertz
2556                    If IRQNum is set to 0 the Frequency parameter is
2557                    overidden, it is forced to a value of FREQ_DIS.
2558           int PeriodicOnly: 1 if all interrupts except the periodic
2559                                interrupt are to be blocked.
2560                             0 is both the periodic interrupt and
2561                                other channel interrupts are allowed.
2562                             If IRQNum is set to 0 the PeriodicOnly parameter is
2563                                overidden, it is forced to a value of 0.
2564 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
2565                initialization failed.
2566 
2567 Comments:
2568           If periodic interrupts are to be disabled but AIOP interrupts
2569           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2570 
2571           If interrupts are to be completely disabled set IRQNum to 0.
2572 
2573           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2574           invalid combination.
2575 
2576           This function performs initialization of global interrupt modes,
2577           but it does not actually enable global interrupts.  To enable
2578           and disable global interrupts use functions sEnGlobalInt() and
2579           sDisGlobalInt().  Enabling of global interrupts is normally not
2580           done until all other initializations are complete.
2581 
2582           Even if interrupts are globally enabled, they must also be
2583           individually enabled for each channel that is to generate
2584           interrupts.
2585 
2586 Warnings: No range checking on any of the parameters is done.
2587 
2588           No context switches are allowed while executing this function.
2589 
2590           After this function all AIOPs on the controller are disabled,
2591           they can be enabled with sEnAiop().
2592 */
2593 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2594                            ByteIO_t * AiopIOList, int AiopIOListSize,
2595                            int IRQNum, Byte_t Frequency, int PeriodicOnly)
2596 {
2597         int i;
2598         ByteIO_t io;
2599         int done;
2600 
2601         CtlP->AiopIntrBits = aiop_intr_bits;
2602         CtlP->AltChanRingIndicator = 0;
2603         CtlP->CtlNum = CtlNum;
2604         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
2605         CtlP->BusType = isISA;
2606         CtlP->MBaseIO = MudbacIO;
2607         CtlP->MReg1IO = MudbacIO + 1;
2608         CtlP->MReg2IO = MudbacIO + 2;
2609         CtlP->MReg3IO = MudbacIO + 3;
2610 #if 1
2611         CtlP->MReg2 = 0;        /* interrupt disable */
2612         CtlP->MReg3 = 0;        /* no periodic interrupts */
2613 #else
2614         if (sIRQMap[IRQNum] == 0) {     /* interrupts globally disabled */
2615                 CtlP->MReg2 = 0;        /* interrupt disable */
2616                 CtlP->MReg3 = 0;        /* no periodic interrupts */
2617         } else {
2618                 CtlP->MReg2 = sIRQMap[IRQNum];  /* set IRQ number */
2619                 CtlP->MReg3 = Frequency;        /* set frequency */
2620                 if (PeriodicOnly) {     /* periodic interrupt only */
2621                         CtlP->MReg3 |= PERIODIC_ONLY;
2622                 }
2623         }
2624 #endif
2625         sOutB(CtlP->MReg2IO, CtlP->MReg2);
2626         sOutB(CtlP->MReg3IO, CtlP->MReg3);
2627         sControllerEOI(CtlP);   /* clear EOI if warm init */
2628         /* Init AIOPs */
2629         CtlP->NumAiop = 0;
2630         for (i = done = 0; i < AiopIOListSize; i++) {
2631                 io = AiopIOList[i];
2632                 CtlP->AiopIO[i] = (WordIO_t) io;
2633                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2634                 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2635                 sOutB(MudbacIO, (Byte_t) (io >> 6));    /* set up AIOP I/O in MUDBAC */
2636                 if (done)
2637                         continue;
2638                 sEnAiop(CtlP, i);       /* enable the AIOP */
2639                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
2640                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
2641                         done = 1;       /* done looking for AIOPs */
2642                 else {
2643                         CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2644                         sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
2645                         sOutB(io + _INDX_DATA, sClockPrescale);
2646                         CtlP->NumAiop++;        /* bump count of AIOPs */
2647                 }
2648                 sDisAiop(CtlP, i);      /* disable AIOP */
2649         }
2650 
2651         if (CtlP->NumAiop == 0)
2652                 return (-1);
2653         else
2654                 return (CtlP->NumAiop);
2655 }
2656 
2657 /***************************************************************************
2658 Function: sReadAiopID
2659 Purpose:  Read the AIOP idenfication number directly from an AIOP.
2660 Call:     sReadAiopID(io)
2661           ByteIO_t io: AIOP base I/O address
2662 Return:   int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2663                  is replace by an identifying number.
2664           Flag AIOPID_NULL if no valid AIOP is found
2665 Warnings: No context switches are allowed while executing this function.
2666 
2667 */
2668 static int sReadAiopID(ByteIO_t io)
2669 {
2670         Byte_t AiopID;          /* ID byte from AIOP */
2671 
2672         sOutB(io + _CMD_REG, RESET_ALL);        /* reset AIOP */
2673         sOutB(io + _CMD_REG, 0x0);
2674         AiopID = sInW(io + _CHN_STAT0) & 0x07;
2675         if (AiopID == 0x06)
2676                 return (1);
2677         else                    /* AIOP does not exist */
2678                 return (-1);
2679 }
2680 
2681 /***************************************************************************
2682 Function: sReadAiopNumChan
2683 Purpose:  Read the number of channels available in an AIOP directly from
2684           an AIOP.
2685 Call:     sReadAiopNumChan(io)
2686           WordIO_t io: AIOP base I/O address
2687 Return:   int: The number of channels available
2688 Comments: The number of channels is determined by write/reads from identical
2689           offsets within the SRAM address spaces for channels 0 and 4.
2690           If the channel 4 space is mirrored to channel 0 it is a 4 channel
2691           AIOP, otherwise it is an 8 channel.
2692 Warnings: No context switches are allowed while executing this function.
2693 */
2694 static int sReadAiopNumChan(WordIO_t io)
2695 {
2696         Word_t x;
2697         static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2698 
2699         /* write to chan 0 SRAM */
2700         out32((DWordIO_t) io + _INDX_ADDR, R);
2701         sOutW(io + _INDX_ADDR, 0);      /* read from SRAM, chan 0 */
2702         x = sInW(io + _INDX_DATA);
2703         sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2704         if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2705                 return (8);
2706         else
2707                 return (4);
2708 }
2709 
2710 /***************************************************************************
2711 Function: sInitChan
2712 Purpose:  Initialization of a channel and channel structure
2713 Call:     sInitChan(CtlP,ChP,AiopNum,ChanNum)
2714           CONTROLLER_T *CtlP; Ptr to controller structure
2715           CHANNEL_T *ChP; Ptr to channel structure
2716           int AiopNum; AIOP number within controller
2717           int ChanNum; Channel number within AIOP
2718 Return:   int: 1 if initialization succeeded, 0 if it fails because channel
2719                number exceeds number of channels available in AIOP.
2720 Comments: This function must be called before a channel can be used.
2721 Warnings: No range checking on any of the parameters is done.
2722 
2723           No context switches are allowed while executing this function.
2724 */
2725 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2726                      int ChanNum)
2727 {
2728         int i;
2729         WordIO_t AiopIO;
2730         WordIO_t ChIOOff;
2731         Byte_t *ChR;
2732         Word_t ChOff;
2733         static Byte_t R[4];
2734         int brd9600;
2735 
2736         if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2737                 return 0;       /* exceeds num chans in AIOP */
2738 
2739         /* Channel, AIOP, and controller identifiers */
2740         ChP->CtlP = CtlP;
2741         ChP->ChanID = CtlP->AiopID[AiopNum];
2742         ChP->AiopNum = AiopNum;
2743         ChP->ChanNum = ChanNum;
2744 
2745         /* Global direct addresses */
2746         AiopIO = CtlP->AiopIO[AiopNum];
2747         ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2748         ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2749         ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2750         ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2751         ChP->IndexData = AiopIO + _INDX_DATA;
2752 
2753         /* Channel direct addresses */
2754         ChIOOff = AiopIO + ChP->ChanNum * 2;
2755         ChP->TxRxData = ChIOOff + _TD0;
2756         ChP->ChanStat = ChIOOff + _CHN_STAT0;
2757         ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2758         ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2759 
2760         /* Initialize the channel from the RData array */
2761         for (i = 0; i < RDATASIZE; i += 4) {
2762                 R[0] = RData[i];
2763                 R[1] = RData[i + 1] + 0x10 * ChanNum;
2764                 R[2] = RData[i + 2];
2765                 R[3] = RData[i + 3];
2766                 out32(ChP->IndexAddr, R);
2767         }
2768 
2769         ChR = ChP->R;
2770         for (i = 0; i < RREGDATASIZE; i += 4) {
2771                 ChR[i] = RRegData[i];
2772                 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2773                 ChR[i + 2] = RRegData[i + 2];
2774                 ChR[i + 3] = RRegData[i + 3];
2775         }
2776 
2777         /* Indexed registers */
2778         ChOff = (Word_t) ChanNum *0x1000;
2779 
2780         if (sClockPrescale == 0x14)
2781                 brd9600 = 47;
2782         else
2783                 brd9600 = 23;
2784 
2785         ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2786         ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2787         ChP->BaudDiv[2] = (Byte_t) brd9600;
2788         ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2789         out32(ChP->IndexAddr, ChP->BaudDiv);
2790 
2791         ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2792         ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2793         ChP->TxControl[2] = 0;
2794         ChP->TxControl[3] = 0;
2795         out32(ChP->IndexAddr, ChP->TxControl);
2796 
2797         ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2798         ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2799         ChP->RxControl[2] = 0;
2800         ChP->RxControl[3] = 0;
2801         out32(ChP->IndexAddr, ChP->RxControl);
2802 
2803         ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2804         ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2805         ChP->TxEnables[2] = 0;
2806         ChP->TxEnables[3] = 0;
2807         out32(ChP->IndexAddr, ChP->TxEnables);
2808 
2809         ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2810         ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2811         ChP->TxCompare[2] = 0;
2812         ChP->TxCompare[3] = 0;
2813         out32(ChP->IndexAddr, ChP->TxCompare);
2814 
2815         ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2816         ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2817         ChP->TxReplace1[2] = 0;
2818         ChP->TxReplace1[3] = 0;
2819         out32(ChP->IndexAddr, ChP->TxReplace1);
2820 
2821         ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2822         ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2823         ChP->TxReplace2[2] = 0;
2824         ChP->TxReplace2[3] = 0;
2825         out32(ChP->IndexAddr, ChP->TxReplace2);
2826 
2827         ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2828         ChP->TxFIFO = ChOff + _TX_FIFO;
2829 
2830         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT);  /* apply reset Tx FIFO count */
2831         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Tx FIFO count */
2832         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
2833         sOutW(ChP->IndexData, 0);
2834         ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2835         ChP->RxFIFO = ChOff + _RX_FIFO;
2836 
2837         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT);  /* apply reset Rx FIFO count */
2838         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Rx FIFO count */
2839         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
2840         sOutW(ChP->IndexData, 0);
2841         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
2842         sOutW(ChP->IndexData, 0);
2843         ChP->TxPrioCnt = ChOff + _TXP_CNT;
2844         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2845         sOutB(ChP->IndexData, 0);
2846         ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2847         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2848         sOutB(ChP->IndexData, 0);
2849         ChP->TxPrioBuf = ChOff + _TXP_BUF;
2850         sEnRxProcessor(ChP);    /* start the Rx processor */
2851 
2852         return 1;
2853 }
2854 
2855 /***************************************************************************
2856 Function: sStopRxProcessor
2857 Purpose:  Stop the receive processor from processing a channel.
2858 Call:     sStopRxProcessor(ChP)
2859           CHANNEL_T *ChP; Ptr to channel structure
2860 
2861 Comments: The receive processor can be started again with sStartRxProcessor().
2862           This function causes the receive processor to skip over the
2863           stopped channel.  It does not stop it from processing other channels.
2864 
2865 Warnings: No context switches are allowed while executing this function.
2866 
2867           Do not leave the receive processor stopped for more than one
2868           character time.
2869 
2870           After calling this function a delay of 4 uS is required to ensure
2871           that the receive processor is no longer processing this channel.
2872 */
2873 static void sStopRxProcessor(CHANNEL_T * ChP)
2874 {
2875         Byte_t R[4];
2876 
2877         R[0] = ChP->R[0];
2878         R[1] = ChP->R[1];
2879         R[2] = 0x0a;
2880         R[3] = ChP->R[3];
2881         out32(ChP->IndexAddr, R);
2882 }
2883 
2884 /***************************************************************************
2885 Function: sFlushRxFIFO
2886 Purpose:  Flush the Rx FIFO
2887 Call:     sFlushRxFIFO(ChP)
2888           CHANNEL_T *ChP; Ptr to channel structure
2889 Return:   void
2890 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2891           while it is being flushed the receive processor is stopped
2892           and the transmitter is disabled.  After these operations a
2893           4 uS delay is done before clearing the pointers to allow
2894           the receive processor to stop.  These items are handled inside
2895           this function.
2896 Warnings: No context switches are allowed while executing this function.
2897 */
2898 static void sFlushRxFIFO(CHANNEL_T * ChP)
2899 {
2900         int i;
2901         Byte_t Ch;              /* channel number within AIOP */
2902         int RxFIFOEnabled;      /* 1 if Rx FIFO enabled */
2903 
2904         if (sGetRxCnt(ChP) == 0)        /* Rx FIFO empty */
2905                 return;         /* don't need to flush */
2906 
2907         RxFIFOEnabled = 0;
2908         if (ChP->R[0x32] == 0x08) {     /* Rx FIFO is enabled */
2909                 RxFIFOEnabled = 1;
2910                 sDisRxFIFO(ChP);        /* disable it */
2911                 for (i = 0; i < 2000 / 200; i++)        /* delay 2 uS to allow proc to disable FIFO */
2912                         sInB(ChP->IntChan);     /* depends on bus i/o timing */
2913         }
2914         sGetChanStatus(ChP);    /* clear any pending Rx errors in chan stat */
2915         Ch = (Byte_t) sGetChanNum(ChP);
2916         sOutB(ChP->Cmd, Ch | RESRXFCNT);        /* apply reset Rx FIFO count */
2917         sOutB(ChP->Cmd, Ch);    /* remove reset Rx FIFO count */
2918         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
2919         sOutW(ChP->IndexData, 0);
2920         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
2921         sOutW(ChP->IndexData, 0);
2922         if (RxFIFOEnabled)
2923                 sEnRxFIFO(ChP); /* enable Rx FIFO */
2924 }
2925 
2926 /***************************************************************************
2927 Function: sFlushTxFIFO
2928 Purpose:  Flush the Tx FIFO
2929 Call:     sFlushTxFIFO(ChP)
2930           CHANNEL_T *ChP; Ptr to channel structure
2931 Return:   void
2932 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2933           while it is being flushed the receive processor is stopped
2934           and the transmitter is disabled.  After these operations a
2935           4 uS delay is done before clearing the pointers to allow
2936           the receive processor to stop.  These items are handled inside
2937           this function.
2938 Warnings: No context switches are allowed while executing this function.
2939 */
2940 static void sFlushTxFIFO(CHANNEL_T * ChP)
2941 {
2942         int i;
2943         Byte_t Ch;              /* channel number within AIOP */
2944         int TxEnabled;          /* 1 if transmitter enabled */
2945 
2946         if (sGetTxCnt(ChP) == 0)        /* Tx FIFO empty */
2947                 return;         /* don't need to flush */
2948 
2949         TxEnabled = 0;
2950         if (ChP->TxControl[3] & TX_ENABLE) {
2951                 TxEnabled = 1;
2952                 sDisTransmit(ChP);      /* disable transmitter */
2953         }
2954         sStopRxProcessor(ChP);  /* stop Rx processor */
2955         for (i = 0; i < 4000 / 200; i++)        /* delay 4 uS to allow proc to stop */
2956                 sInB(ChP->IntChan);     /* depends on bus i/o timing */
2957         Ch = (Byte_t) sGetChanNum(ChP);
2958         sOutB(ChP->Cmd, Ch | RESTXFCNT);        /* apply reset Tx FIFO count */
2959         sOutB(ChP->Cmd, Ch);    /* remove reset Tx FIFO count */
2960         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
2961         sOutW(ChP->IndexData, 0);
2962         if (TxEnabled)
2963                 sEnTransmit(ChP);       /* enable transmitter */
2964         sStartRxProcessor(ChP); /* restart Rx processor */
2965 }
2966 
2967 /***************************************************************************
2968 Function: sWriteTxPrioByte
2969 Purpose:  Write a byte of priority transmit data to a channel
2970 Call:     sWriteTxPrioByte(ChP,Data)
2971           CHANNEL_T *ChP; Ptr to channel structure
2972           Byte_t Data; The transmit data byte
2973 
2974 Return:   int: 1 if the bytes is successfully written, otherwise 0.
2975 
2976 Comments: The priority byte is transmitted before any data in the Tx FIFO.
2977 
2978 Warnings: No context switches are allowed while executing this function.
2979 */
2980 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2981 {
2982         Byte_t DWBuf[4];        /* buffer for double word writes */
2983         Word_t *WordPtr;        /* must be far because Win SS != DS */
2984         register DWordIO_t IndexAddr;
2985 
2986         if (sGetTxCnt(ChP) > 1) {       /* write it to Tx priority buffer */
2987                 IndexAddr = ChP->IndexAddr;
2988                 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt);    /* get priority buffer status */
2989                 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2990                         return (0);     /* nothing sent */
2991 
2992                 WordPtr = (Word_t *) (&DWBuf[0]);
2993                 *WordPtr = ChP->TxPrioBuf;      /* data byte address */
2994 
2995                 DWBuf[2] = Data;        /* data byte value */
2996                 out32(IndexAddr, DWBuf);        /* write it out */
2997 
2998                 *WordPtr = ChP->TxPrioCnt;      /* Tx priority count address */
2999 
3000                 DWBuf[2] = PRI_PEND + 1;        /* indicate 1 byte pending */
3001                 DWBuf[3] = 0;   /* priority buffer pointer */
3002                 out32(IndexAddr, DWBuf);        /* write it out */
3003         } else {                /* write it to Tx FIFO */
3004 
3005                 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3006         }
3007         return (1);             /* 1 byte sent */
3008 }
3009 
3010 /***************************************************************************
3011 Function: sEnInterrupts
3012 Purpose:  Enable one or more interrupts for a channel
3013 Call:     sEnInterrupts(ChP,Flags)
3014           CHANNEL_T *ChP; Ptr to channel structure
3015           Word_t Flags: Interrupt enable flags, can be any combination
3016              of the following flags:
3017                 TXINT_EN:   Interrupt on Tx FIFO empty
3018                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3019                             sSetRxTrigger())
3020                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3021                 MCINT_EN:   Interrupt on modem input change
3022                 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3023                             Interrupt Channel Register.
3024 Return:   void
3025 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3026           enabled.  If an interrupt enable flag is not set in Flags, that
3027           interrupt will not be changed.  Interrupts can be disabled with
3028           function sDisInterrupts().
3029 
3030           This function sets the appropriate bit for the channel in the AIOP's
3031           Interrupt Mask Register if the CHANINT_EN flag is set.  This allows
3032           this channel's bit to be set in the AIOP's Interrupt Channel Register.
3033 
3034           Interrupts must also be globally enabled before channel interrupts
3035           will be passed on to the host.  This is done with function
3036           sEnGlobalInt().
3037 
3038           In some cases it may be desirable to disable interrupts globally but
3039           enable channel interrupts.  This would allow the global interrupt
3040           status register to be used to determine which AIOPs need service.
3041 */
3042 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3043 {
3044         Byte_t Mask;            /* Interrupt Mask Register */
3045 
3046         ChP->RxControl[2] |=
3047             ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3048 
3049         out32(ChP->IndexAddr, ChP->RxControl);
3050 
3051         ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3052 
3053         out32(ChP->IndexAddr, ChP->TxControl);
3054 
3055         if (Flags & CHANINT_EN) {
3056                 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3057                 sOutB(ChP->IntMask, Mask);
3058         }
3059 }
3060 
3061 /***************************************************************************
3062 Function: sDisInterrupts
3063 Purpose:  Disable one or more interrupts for a channel
3064 Call:     sDisInterrupts(ChP,Flags)
3065           CHANNEL_T *ChP; Ptr to channel structure
3066           Word_t Flags: Interrupt flags, can be any combination
3067              of the following flags:
3068                 TXINT_EN:   Interrupt on Tx FIFO empty
3069                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3070                             sSetRxTrigger())
3071                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3072                 MCINT_EN:   Interrupt on modem input change
3073                 CHANINT_EN: Disable channel interrupt signal to the
3074                             AIOP's Interrupt Channel Register.
3075 Return:   void
3076 Comments: If an interrupt flag is set in Flags, that interrupt will be
3077           disabled.  If an interrupt flag is not set in Flags, that
3078           interrupt will not be changed.  Interrupts can be enabled with
3079           function sEnInterrupts().
3080 
3081           This function clears the appropriate bit for the channel in the AIOP's
3082           Interrupt Mask Register if the CHANINT_EN flag is set.  This blocks
3083           this channel's bit from being set in the AIOP's Interrupt Channel
3084           Register.
3085 */
3086 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3087 {
3088         Byte_t Mask;            /* Interrupt Mask Register */
3089 
3090         ChP->RxControl[2] &=
3091             ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3092         out32(ChP->IndexAddr, ChP->RxControl);
3093         ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3094         out32(ChP->IndexAddr, ChP->TxControl);
3095 
3096         if (Flags & CHANINT_EN) {
3097                 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3098                 sOutB(ChP->IntMask, Mask);
3099         }
3100 }
3101 
3102 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3103 {
3104         sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3105 }
3106 
3107 /*
3108  *  Not an official SSCI function, but how to reset RocketModems.
3109  *  ISA bus version
3110  */
3111 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3112 {
3113         ByteIO_t addr;
3114         Byte_t val;
3115 
3116         addr = CtlP->AiopIO[0] + 0x400;
3117         val = sInB(CtlP->MReg3IO);
3118         /* if AIOP[1] is not enabled, enable it */
3119         if ((val & 2) == 0) {
3120                 val = sInB(CtlP->MReg2IO);
3121                 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3122                 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3123         }
3124 
3125         sEnAiop(CtlP, 1);
3126         if (!on)
3127                 addr += 8;
3128         sOutB(addr + chan, 0);  /* apply or remove reset */
3129         sDisAiop(CtlP, 1);
3130 }
3131 
3132 /*
3133  *  Not an official SSCI function, but how to reset RocketModems.
3134  *  PCI bus version
3135  */
3136 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3137 {
3138         ByteIO_t addr;
3139 
3140         addr = CtlP->AiopIO[0] + 0x40;  /* 2nd AIOP */
3141         if (!on)
3142                 addr += 8;
3143         sOutB(addr + chan, 0);  /* apply or remove reset */
3144 }
3145 
3146 /*  Returns the line number given the controller (board), aiop and channel number */
3147 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3148 {
3149         return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3150 }
3151 
3152 /*
3153  *  Stores the line number associated with a given controller (board), aiop
3154  *  and channel number.  
3155  *  Returns:  The line number assigned 
3156  */
3157 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3158 {
3159         lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3160         return (nextLineNumber - 1);
3161 }
3162 

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