Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/thermal/samsung/exynos_tmu.c

  1 /*
  2  * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
  3  *
  4  *  Copyright (C) 2011 Samsung Electronics
  5  *  Donggeun Kim <dg77.kim@samsung.com>
  6  *  Amit Daniel Kachhap <amit.kachhap@linaro.org>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  *
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program; if not, write to the Free Software
 20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 21  *
 22  */
 23 
 24 #include <linux/clk.h>
 25 #include <linux/io.h>
 26 #include <linux/interrupt.h>
 27 #include <linux/module.h>
 28 #include <linux/of.h>
 29 #include <linux/of_address.h>
 30 #include <linux/of_irq.h>
 31 #include <linux/platform_device.h>
 32 #include <linux/regulator/consumer.h>
 33 
 34 #include "exynos_thermal_common.h"
 35 #include "exynos_tmu.h"
 36 #include "exynos_tmu_data.h"
 37 
 38 /**
 39  * struct exynos_tmu_data : A structure to hold the private data of the TMU
 40         driver
 41  * @id: identifier of the one instance of the TMU controller.
 42  * @pdata: pointer to the tmu platform/configuration data
 43  * @base: base address of the single instance of the TMU controller.
 44  * @base_second: base address of the common registers of the TMU controller.
 45  * @irq: irq number of the TMU controller.
 46  * @soc: id of the SOC type.
 47  * @irq_work: pointer to the irq work structure.
 48  * @lock: lock to implement synchronization.
 49  * @clk: pointer to the clock structure.
 50  * @clk_sec: pointer to the clock structure for accessing the base_second.
 51  * @temp_error1: fused value of the first point trim.
 52  * @temp_error2: fused value of the second point trim.
 53  * @regulator: pointer to the TMU regulator structure.
 54  * @reg_conf: pointer to structure to register with core thermal.
 55  */
 56 struct exynos_tmu_data {
 57         int id;
 58         struct exynos_tmu_platform_data *pdata;
 59         void __iomem *base;
 60         void __iomem *base_second;
 61         int irq;
 62         enum soc_type soc;
 63         struct work_struct irq_work;
 64         struct mutex lock;
 65         struct clk *clk, *clk_sec;
 66         u8 temp_error1, temp_error2;
 67         struct regulator *regulator;
 68         struct thermal_sensor_conf *reg_conf;
 69 };
 70 
 71 /*
 72  * TMU treats temperature as a mapped temperature code.
 73  * The temperature is converted differently depending on the calibration type.
 74  */
 75 static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
 76 {
 77         struct exynos_tmu_platform_data *pdata = data->pdata;
 78         int temp_code;
 79 
 80         switch (pdata->cal_type) {
 81         case TYPE_TWO_POINT_TRIMMING:
 82                 temp_code = (temp - pdata->first_point_trim) *
 83                         (data->temp_error2 - data->temp_error1) /
 84                         (pdata->second_point_trim - pdata->first_point_trim) +
 85                         data->temp_error1;
 86                 break;
 87         case TYPE_ONE_POINT_TRIMMING:
 88                 temp_code = temp + data->temp_error1 - pdata->first_point_trim;
 89                 break;
 90         default:
 91                 temp_code = temp + pdata->default_temp_offset;
 92                 break;
 93         }
 94 
 95         return temp_code;
 96 }
 97 
 98 /*
 99  * Calculate a temperature value from a temperature code.
100  * The unit of the temperature is degree Celsius.
101  */
102 static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
103 {
104         struct exynos_tmu_platform_data *pdata = data->pdata;
105         int temp;
106 
107         switch (pdata->cal_type) {
108         case TYPE_TWO_POINT_TRIMMING:
109                 temp = (temp_code - data->temp_error1) *
110                         (pdata->second_point_trim - pdata->first_point_trim) /
111                         (data->temp_error2 - data->temp_error1) +
112                         pdata->first_point_trim;
113                 break;
114         case TYPE_ONE_POINT_TRIMMING:
115                 temp = temp_code - data->temp_error1 + pdata->first_point_trim;
116                 break;
117         default:
118                 temp = temp_code - pdata->default_temp_offset;
119                 break;
120         }
121 
122         return temp;
123 }
124 
125 static void exynos_tmu_clear_irqs(struct exynos_tmu_data *data)
126 {
127         const struct exynos_tmu_registers *reg = data->pdata->registers;
128         unsigned int val_irq;
129 
130         val_irq = readl(data->base + reg->tmu_intstat);
131         /*
132          * Clear the interrupts.  Please note that the documentation for
133          * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly
134          * states that INTCLEAR register has a different placing of bits
135          * responsible for FALL IRQs than INTSTAT register.  Exynos5420
136          * and Exynos5440 documentation is correct (Exynos4210 doesn't
137          * support FALL IRQs at all).
138          */
139         writel(val_irq, data->base + reg->tmu_intclear);
140 }
141 
142 static int exynos_tmu_initialize(struct platform_device *pdev)
143 {
144         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
145         struct exynos_tmu_platform_data *pdata = data->pdata;
146         const struct exynos_tmu_registers *reg = pdata->registers;
147         unsigned int status, trim_info = 0, con, ctrl;
148         unsigned int rising_threshold = 0, falling_threshold = 0;
149         int ret = 0, threshold_code, i;
150 
151         mutex_lock(&data->lock);
152         clk_enable(data->clk);
153         if (!IS_ERR(data->clk_sec))
154                 clk_enable(data->clk_sec);
155 
156         if (TMU_SUPPORTS(pdata, READY_STATUS)) {
157                 status = readb(data->base + reg->tmu_status);
158                 if (!status) {
159                         ret = -EBUSY;
160                         goto out;
161                 }
162         }
163 
164         if (TMU_SUPPORTS(pdata, TRIM_RELOAD)) {
165                 for (i = 0; i < reg->triminfo_ctrl_count; i++) {
166                         if (pdata->triminfo_reload[i]) {
167                                 ctrl = readl(data->base +
168                                                 reg->triminfo_ctrl[i]);
169                                 ctrl |= pdata->triminfo_reload[i];
170                                 writel(ctrl, data->base +
171                                                 reg->triminfo_ctrl[i]);
172                         }
173                 }
174         }
175 
176         /* Save trimming info in order to perform calibration */
177         if (data->soc == SOC_ARCH_EXYNOS5440) {
178                 /*
179                  * For exynos5440 soc triminfo value is swapped between TMU0 and
180                  * TMU2, so the below logic is needed.
181                  */
182                 switch (data->id) {
183                 case 0:
184                         trim_info = readl(data->base +
185                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
186                         break;
187                 case 1:
188                         trim_info = readl(data->base + reg->triminfo_data);
189                         break;
190                 case 2:
191                         trim_info = readl(data->base -
192                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
193                 }
194         } else {
195                 /* On exynos5420 the triminfo register is in the shared space */
196                 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
197                         trim_info = readl(data->base_second +
198                                                         reg->triminfo_data);
199                 else
200                         trim_info = readl(data->base + reg->triminfo_data);
201         }
202         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
203         data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
204                                 EXYNOS_TMU_TEMP_MASK);
205 
206         if (!data->temp_error1 ||
207                 (pdata->min_efuse_value > data->temp_error1) ||
208                 (data->temp_error1 > pdata->max_efuse_value))
209                 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
210 
211         if (!data->temp_error2)
212                 data->temp_error2 =
213                         (pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
214                         EXYNOS_TMU_TEMP_MASK;
215 
216         rising_threshold = readl(data->base + reg->threshold_th0);
217 
218         if (data->soc == SOC_ARCH_EXYNOS4210) {
219                 /* Write temperature code for threshold */
220                 threshold_code = temp_to_code(data, pdata->threshold);
221                 writeb(threshold_code,
222                         data->base + reg->threshold_temp);
223                 for (i = 0; i < pdata->non_hw_trigger_levels; i++)
224                         writeb(pdata->trigger_levels[i], data->base +
225                         reg->threshold_th0 + i * sizeof(reg->threshold_th0));
226 
227                 exynos_tmu_clear_irqs(data);
228         } else {
229                 /* Write temperature code for rising and falling threshold */
230                 for (i = 0; i < pdata->non_hw_trigger_levels; i++) {
231                         threshold_code = temp_to_code(data,
232                                                 pdata->trigger_levels[i]);
233                         rising_threshold &= ~(0xff << 8 * i);
234                         rising_threshold |= threshold_code << 8 * i;
235                         if (pdata->threshold_falling) {
236                                 threshold_code = temp_to_code(data,
237                                                 pdata->trigger_levels[i] -
238                                                 pdata->threshold_falling);
239                                 falling_threshold |= threshold_code << 8 * i;
240                         }
241                 }
242 
243                 writel(rising_threshold,
244                                 data->base + reg->threshold_th0);
245                 writel(falling_threshold,
246                                 data->base + reg->threshold_th1);
247 
248                 exynos_tmu_clear_irqs(data);
249 
250                 /* if last threshold limit is also present */
251                 i = pdata->max_trigger_level - 1;
252                 if (pdata->trigger_levels[i] &&
253                                 (pdata->trigger_type[i] == HW_TRIP)) {
254                         threshold_code = temp_to_code(data,
255                                                 pdata->trigger_levels[i]);
256                         if (i == EXYNOS_MAX_TRIGGER_PER_REG - 1) {
257                                 /* 1-4 level to be assigned in th0 reg */
258                                 rising_threshold &= ~(0xff << 8 * i);
259                                 rising_threshold |= threshold_code << 8 * i;
260                                 writel(rising_threshold,
261                                         data->base + reg->threshold_th0);
262                         } else if (i == EXYNOS_MAX_TRIGGER_PER_REG) {
263                                 /* 5th level to be assigned in th2 reg */
264                                 rising_threshold =
265                                 threshold_code << reg->threshold_th3_l0_shift;
266                                 writel(rising_threshold,
267                                         data->base + reg->threshold_th2);
268                         }
269                         con = readl(data->base + reg->tmu_ctrl);
270                         con |= (1 << reg->therm_trip_en_shift);
271                         writel(con, data->base + reg->tmu_ctrl);
272                 }
273         }
274         /*Clear the PMIN in the common TMU register*/
275         if (reg->tmu_pmin && !data->id)
276                 writel(0, data->base_second + reg->tmu_pmin);
277 out:
278         clk_disable(data->clk);
279         mutex_unlock(&data->lock);
280         if (!IS_ERR(data->clk_sec))
281                 clk_disable(data->clk_sec);
282 
283         return ret;
284 }
285 
286 static void exynos_tmu_control(struct platform_device *pdev, bool on)
287 {
288         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
289         struct exynos_tmu_platform_data *pdata = data->pdata;
290         const struct exynos_tmu_registers *reg = pdata->registers;
291         unsigned int con, interrupt_en;
292 
293         mutex_lock(&data->lock);
294         clk_enable(data->clk);
295 
296         con = readl(data->base + reg->tmu_ctrl);
297 
298         if (pdata->test_mux)
299                 con |= (pdata->test_mux << reg->test_mux_addr_shift);
300 
301         con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT);
302         con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
303 
304         con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
305         con |= (pdata->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
306 
307         if (pdata->noise_cancel_mode) {
308                 con &= ~(reg->therm_trip_mode_mask <<
309                                         reg->therm_trip_mode_shift);
310                 con |= (pdata->noise_cancel_mode << reg->therm_trip_mode_shift);
311         }
312 
313         if (on) {
314                 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
315                 interrupt_en =
316                         pdata->trigger_enable[3] << reg->inten_rise3_shift |
317                         pdata->trigger_enable[2] << reg->inten_rise2_shift |
318                         pdata->trigger_enable[1] << reg->inten_rise1_shift |
319                         pdata->trigger_enable[0] << reg->inten_rise0_shift;
320                 if (TMU_SUPPORTS(pdata, FALLING_TRIP))
321                         interrupt_en |=
322                                 interrupt_en << reg->inten_fall0_shift;
323         } else {
324                 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
325                 interrupt_en = 0; /* Disable all interrupts */
326         }
327         writel(interrupt_en, data->base + reg->tmu_inten);
328         writel(con, data->base + reg->tmu_ctrl);
329 
330         clk_disable(data->clk);
331         mutex_unlock(&data->lock);
332 }
333 
334 static int exynos_tmu_read(struct exynos_tmu_data *data)
335 {
336         struct exynos_tmu_platform_data *pdata = data->pdata;
337         const struct exynos_tmu_registers *reg = pdata->registers;
338         u8 temp_code;
339         int temp;
340 
341         mutex_lock(&data->lock);
342         clk_enable(data->clk);
343 
344         temp_code = readb(data->base + reg->tmu_cur_temp);
345 
346         if (data->soc == SOC_ARCH_EXYNOS4210)
347                 /* temp_code should range between 75 and 175 */
348                 if (temp_code < 75 || temp_code > 175) {
349                         temp = -ENODATA;
350                         goto out;
351                 }
352 
353         temp = code_to_temp(data, temp_code);
354 out:
355         clk_disable(data->clk);
356         mutex_unlock(&data->lock);
357 
358         return temp;
359 }
360 
361 #ifdef CONFIG_THERMAL_EMULATION
362 static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
363 {
364         struct exynos_tmu_data *data = drv_data;
365         struct exynos_tmu_platform_data *pdata = data->pdata;
366         const struct exynos_tmu_registers *reg = pdata->registers;
367         unsigned int val;
368         int ret = -EINVAL;
369 
370         if (!TMU_SUPPORTS(pdata, EMULATION))
371                 goto out;
372 
373         if (temp && temp < MCELSIUS)
374                 goto out;
375 
376         mutex_lock(&data->lock);
377         clk_enable(data->clk);
378 
379         val = readl(data->base + reg->emul_con);
380 
381         if (temp) {
382                 temp /= MCELSIUS;
383 
384                 if (TMU_SUPPORTS(pdata, EMUL_TIME)) {
385                         val &= ~(EXYNOS_EMUL_TIME_MASK << reg->emul_time_shift);
386                         val |= (EXYNOS_EMUL_TIME << reg->emul_time_shift);
387                 }
388                 val &= ~(EXYNOS_EMUL_DATA_MASK << reg->emul_temp_shift);
389                 val |= (temp_to_code(data, temp) << reg->emul_temp_shift) |
390                         EXYNOS_EMUL_ENABLE;
391         } else {
392                 val &= ~EXYNOS_EMUL_ENABLE;
393         }
394 
395         writel(val, data->base + reg->emul_con);
396 
397         clk_disable(data->clk);
398         mutex_unlock(&data->lock);
399         return 0;
400 out:
401         return ret;
402 }
403 #else
404 static int exynos_tmu_set_emulation(void *drv_data,     unsigned long temp)
405         { return -EINVAL; }
406 #endif/*CONFIG_THERMAL_EMULATION*/
407 
408 static void exynos_tmu_work(struct work_struct *work)
409 {
410         struct exynos_tmu_data *data = container_of(work,
411                         struct exynos_tmu_data, irq_work);
412         struct exynos_tmu_platform_data *pdata = data->pdata;
413         const struct exynos_tmu_registers *reg = pdata->registers;
414         unsigned int val_type;
415 
416         if (!IS_ERR(data->clk_sec))
417                 clk_enable(data->clk_sec);
418         /* Find which sensor generated this interrupt */
419         if (reg->tmu_irqstatus) {
420                 val_type = readl(data->base_second + reg->tmu_irqstatus);
421                 if (!((val_type >> data->id) & 0x1))
422                         goto out;
423         }
424         if (!IS_ERR(data->clk_sec))
425                 clk_disable(data->clk_sec);
426 
427         exynos_report_trigger(data->reg_conf);
428         mutex_lock(&data->lock);
429         clk_enable(data->clk);
430 
431         /* TODO: take action based on particular interrupt */
432         exynos_tmu_clear_irqs(data);
433 
434         clk_disable(data->clk);
435         mutex_unlock(&data->lock);
436 out:
437         enable_irq(data->irq);
438 }
439 
440 static irqreturn_t exynos_tmu_irq(int irq, void *id)
441 {
442         struct exynos_tmu_data *data = id;
443 
444         disable_irq_nosync(irq);
445         schedule_work(&data->irq_work);
446 
447         return IRQ_HANDLED;
448 }
449 
450 static const struct of_device_id exynos_tmu_match[] = {
451         {
452                 .compatible = "samsung,exynos3250-tmu",
453                 .data = (void *)EXYNOS3250_TMU_DRV_DATA,
454         },
455         {
456                 .compatible = "samsung,exynos4210-tmu",
457                 .data = (void *)EXYNOS4210_TMU_DRV_DATA,
458         },
459         {
460                 .compatible = "samsung,exynos4412-tmu",
461                 .data = (void *)EXYNOS4412_TMU_DRV_DATA,
462         },
463         {
464                 .compatible = "samsung,exynos5250-tmu",
465                 .data = (void *)EXYNOS5250_TMU_DRV_DATA,
466         },
467         {
468                 .compatible = "samsung,exynos5260-tmu",
469                 .data = (void *)EXYNOS5260_TMU_DRV_DATA,
470         },
471         {
472                 .compatible = "samsung,exynos5420-tmu",
473                 .data = (void *)EXYNOS5420_TMU_DRV_DATA,
474         },
475         {
476                 .compatible = "samsung,exynos5420-tmu-ext-triminfo",
477                 .data = (void *)EXYNOS5420_TMU_DRV_DATA,
478         },
479         {
480                 .compatible = "samsung,exynos5440-tmu",
481                 .data = (void *)EXYNOS5440_TMU_DRV_DATA,
482         },
483         {},
484 };
485 MODULE_DEVICE_TABLE(of, exynos_tmu_match);
486 
487 static inline struct  exynos_tmu_platform_data *exynos_get_driver_data(
488                         struct platform_device *pdev, int id)
489 {
490         struct  exynos_tmu_init_data *data_table;
491         struct exynos_tmu_platform_data *tmu_data;
492         const struct of_device_id *match;
493 
494         match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
495         if (!match)
496                 return NULL;
497         data_table = (struct exynos_tmu_init_data *) match->data;
498         if (!data_table || id >= data_table->tmu_count)
499                 return NULL;
500         tmu_data = data_table->tmu_data;
501         return (struct exynos_tmu_platform_data *) (tmu_data + id);
502 }
503 
504 static int exynos_map_dt_data(struct platform_device *pdev)
505 {
506         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
507         struct exynos_tmu_platform_data *pdata;
508         struct resource res;
509         int ret;
510 
511         if (!data || !pdev->dev.of_node)
512                 return -ENODEV;
513 
514         /*
515          * Try enabling the regulator if found
516          * TODO: Add regulator as an SOC feature, so that regulator enable
517          * is a compulsory call.
518          */
519         data->regulator = devm_regulator_get(&pdev->dev, "vtmu");
520         if (!IS_ERR(data->regulator)) {
521                 ret = regulator_enable(data->regulator);
522                 if (ret) {
523                         dev_err(&pdev->dev, "failed to enable vtmu\n");
524                         return ret;
525                 }
526         } else {
527                 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n");
528         }
529 
530         data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl");
531         if (data->id < 0)
532                 data->id = 0;
533 
534         data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
535         if (data->irq <= 0) {
536                 dev_err(&pdev->dev, "failed to get IRQ\n");
537                 return -ENODEV;
538         }
539 
540         if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
541                 dev_err(&pdev->dev, "failed to get Resource 0\n");
542                 return -ENODEV;
543         }
544 
545         data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
546         if (!data->base) {
547                 dev_err(&pdev->dev, "Failed to ioremap memory\n");
548                 return -EADDRNOTAVAIL;
549         }
550 
551         pdata = exynos_get_driver_data(pdev, data->id);
552         if (!pdata) {
553                 dev_err(&pdev->dev, "No platform init data supplied.\n");
554                 return -ENODEV;
555         }
556         data->pdata = pdata;
557         /*
558          * Check if the TMU shares some registers and then try to map the
559          * memory of common registers.
560          */
561         if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
562                 return 0;
563 
564         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
565                 dev_err(&pdev->dev, "failed to get Resource 1\n");
566                 return -ENODEV;
567         }
568 
569         data->base_second = devm_ioremap(&pdev->dev, res.start,
570                                         resource_size(&res));
571         if (!data->base_second) {
572                 dev_err(&pdev->dev, "Failed to ioremap memory\n");
573                 return -ENOMEM;
574         }
575 
576         return 0;
577 }
578 
579 static int exynos_tmu_probe(struct platform_device *pdev)
580 {
581         struct exynos_tmu_data *data;
582         struct exynos_tmu_platform_data *pdata;
583         struct thermal_sensor_conf *sensor_conf;
584         int ret, i;
585 
586         data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
587                                         GFP_KERNEL);
588         if (!data)
589                 return -ENOMEM;
590 
591         platform_set_drvdata(pdev, data);
592         mutex_init(&data->lock);
593 
594         ret = exynos_map_dt_data(pdev);
595         if (ret)
596                 return ret;
597 
598         pdata = data->pdata;
599 
600         INIT_WORK(&data->irq_work, exynos_tmu_work);
601 
602         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
603         if (IS_ERR(data->clk)) {
604                 dev_err(&pdev->dev, "Failed to get clock\n");
605                 return  PTR_ERR(data->clk);
606         }
607 
608         data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
609         if (IS_ERR(data->clk_sec)) {
610                 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
611                         dev_err(&pdev->dev, "Failed to get triminfo clock\n");
612                         return PTR_ERR(data->clk_sec);
613                 }
614         } else {
615                 ret = clk_prepare(data->clk_sec);
616                 if (ret) {
617                         dev_err(&pdev->dev, "Failed to get clock\n");
618                         return ret;
619                 }
620         }
621 
622         ret = clk_prepare(data->clk);
623         if (ret) {
624                 dev_err(&pdev->dev, "Failed to get clock\n");
625                 goto err_clk_sec;
626         }
627 
628         if (pdata->type == SOC_ARCH_EXYNOS3250 ||
629             pdata->type == SOC_ARCH_EXYNOS4210 ||
630             pdata->type == SOC_ARCH_EXYNOS4412 ||
631             pdata->type == SOC_ARCH_EXYNOS5250 ||
632             pdata->type == SOC_ARCH_EXYNOS5260 ||
633             pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO ||
634             pdata->type == SOC_ARCH_EXYNOS5440)
635                 data->soc = pdata->type;
636         else {
637                 ret = -EINVAL;
638                 dev_err(&pdev->dev, "Platform not supported\n");
639                 goto err_clk;
640         }
641 
642         ret = exynos_tmu_initialize(pdev);
643         if (ret) {
644                 dev_err(&pdev->dev, "Failed to initialize TMU\n");
645                 goto err_clk;
646         }
647 
648         exynos_tmu_control(pdev, true);
649 
650         /* Allocate a structure to register with the exynos core thermal */
651         sensor_conf = devm_kzalloc(&pdev->dev,
652                                 sizeof(struct thermal_sensor_conf), GFP_KERNEL);
653         if (!sensor_conf) {
654                 ret = -ENOMEM;
655                 goto err_clk;
656         }
657         sprintf(sensor_conf->name, "therm_zone%d", data->id);
658         sensor_conf->read_temperature = (int (*)(void *))exynos_tmu_read;
659         sensor_conf->write_emul_temp =
660                 (int (*)(void *, unsigned long))exynos_tmu_set_emulation;
661         sensor_conf->driver_data = data;
662         sensor_conf->trip_data.trip_count = pdata->trigger_enable[0] +
663                         pdata->trigger_enable[1] + pdata->trigger_enable[2]+
664                         pdata->trigger_enable[3];
665 
666         for (i = 0; i < sensor_conf->trip_data.trip_count; i++) {
667                 sensor_conf->trip_data.trip_val[i] =
668                         pdata->threshold + pdata->trigger_levels[i];
669                 sensor_conf->trip_data.trip_type[i] =
670                                         pdata->trigger_type[i];
671         }
672 
673         sensor_conf->trip_data.trigger_falling = pdata->threshold_falling;
674 
675         sensor_conf->cooling_data.freq_clip_count = pdata->freq_tab_count;
676         for (i = 0; i < pdata->freq_tab_count; i++) {
677                 sensor_conf->cooling_data.freq_data[i].freq_clip_max =
678                                         pdata->freq_tab[i].freq_clip_max;
679                 sensor_conf->cooling_data.freq_data[i].temp_level =
680                                         pdata->freq_tab[i].temp_level;
681         }
682         sensor_conf->dev = &pdev->dev;
683         /* Register the sensor with thermal management interface */
684         ret = exynos_register_thermal(sensor_conf);
685         if (ret) {
686                 dev_err(&pdev->dev, "Failed to register thermal interface\n");
687                 goto err_clk;
688         }
689         data->reg_conf = sensor_conf;
690 
691         ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
692                 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
693         if (ret) {
694                 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
695                 goto err_clk;
696         }
697 
698         return 0;
699 err_clk:
700         clk_unprepare(data->clk);
701 err_clk_sec:
702         if (!IS_ERR(data->clk_sec))
703                 clk_unprepare(data->clk_sec);
704         return ret;
705 }
706 
707 static int exynos_tmu_remove(struct platform_device *pdev)
708 {
709         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
710 
711         exynos_unregister_thermal(data->reg_conf);
712 
713         exynos_tmu_control(pdev, false);
714 
715         clk_unprepare(data->clk);
716         if (!IS_ERR(data->clk_sec))
717                 clk_unprepare(data->clk_sec);
718 
719         if (!IS_ERR(data->regulator))
720                 regulator_disable(data->regulator);
721 
722         return 0;
723 }
724 
725 #ifdef CONFIG_PM_SLEEP
726 static int exynos_tmu_suspend(struct device *dev)
727 {
728         exynos_tmu_control(to_platform_device(dev), false);
729 
730         return 0;
731 }
732 
733 static int exynos_tmu_resume(struct device *dev)
734 {
735         struct platform_device *pdev = to_platform_device(dev);
736 
737         exynos_tmu_initialize(pdev);
738         exynos_tmu_control(pdev, true);
739 
740         return 0;
741 }
742 
743 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
744                          exynos_tmu_suspend, exynos_tmu_resume);
745 #define EXYNOS_TMU_PM   (&exynos_tmu_pm)
746 #else
747 #define EXYNOS_TMU_PM   NULL
748 #endif
749 
750 static struct platform_driver exynos_tmu_driver = {
751         .driver = {
752                 .name   = "exynos-tmu",
753                 .owner  = THIS_MODULE,
754                 .pm     = EXYNOS_TMU_PM,
755                 .of_match_table = exynos_tmu_match,
756         },
757         .probe = exynos_tmu_probe,
758         .remove = exynos_tmu_remove,
759 };
760 
761 module_platform_driver(exynos_tmu_driver);
762 
763 MODULE_DESCRIPTION("EXYNOS TMU Driver");
764 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
765 MODULE_LICENSE("GPL");
766 MODULE_ALIAS("platform:exynos-tmu");
767 

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