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Linux/drivers/staging/netlogic/xlr_net.c

  1 /*
  2  * Copyright (c) 2003-2012 Broadcom Corporation
  3  * All Rights Reserved
  4  *
  5  * This software is available to you under a choice of one of two
  6  * licenses.  You may choose to be licensed under the terms of the GNU
  7  * General Public License (GPL) Version 2, available from the file
  8  * COPYING in the main directory of this source tree, or the Broadcom
  9  * license below:
 10  *
 11  * Redistribution and use in source and binary forms, with or without
 12  * modification, are permitted provided that the following conditions
 13  * are met:
 14  *
 15  * 1. Redistributions of source code must retain the above copyright
 16  *    notice, this list of conditions and the following disclaimer.
 17  * 2. Redistributions in binary form must reproduce the above copyright
 18  *    notice, this list of conditions and the following disclaimer in
 19  *    the documentation and/or other materials provided with the
 20  *    distribution.
 21  *
 22  * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
 23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 25  * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
 26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 33  */
 34 #include <linux/phy.h>
 35 #include <linux/delay.h>
 36 #include <linux/netdevice.h>
 37 #include <linux/smp.h>
 38 #include <linux/ethtool.h>
 39 #include <linux/module.h>
 40 #include <linux/etherdevice.h>
 41 #include <linux/skbuff.h>
 42 #include <linux/jiffies.h>
 43 #include <linux/interrupt.h>
 44 #include <linux/platform_device.h>
 45 
 46 #include <asm/mipsregs.h>
 47 /*
 48  * fmn.h - For FMN credit configuration and registering fmn_handler.
 49  * FMN is communication mechanism that allows processing agents within
 50  * XLR/XLS to communicate each other.
 51  */
 52 #include <asm/netlogic/xlr/fmn.h>
 53 
 54 #include "platform_net.h"
 55 #include "xlr_net.h"
 56 
 57 /*
 58  * The readl/writel implementation byteswaps on XLR/XLS, so
 59  * we need to use __raw_ IO to read the NAE registers
 60  * because they are in the big-endian MMIO area on the SoC.
 61  */
 62 static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val)
 63 {
 64         __raw_writel(val, base + reg);
 65 }
 66 
 67 static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg)
 68 {
 69         return __raw_readl(base + reg);
 70 }
 71 
 72 static inline void xlr_reg_update(u32 *base_addr, u32 off, u32 val, u32 mask)
 73 {
 74         u32 tmp;
 75 
 76         tmp = xlr_nae_rdreg(base_addr, off);
 77         xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask));
 78 }
 79 
 80 #define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES
 81 
 82 static int send_to_rfr_fifo(struct xlr_net_priv *priv, void *addr)
 83 {
 84         struct nlm_fmn_msg msg;
 85         int ret = 0, num_try = 0, stnid;
 86         unsigned long paddr, mflags;
 87 
 88         paddr = virt_to_bus(addr);
 89         msg.msg0 = (u64)paddr & 0xffffffffe0ULL;
 90         msg.msg1 = 0;
 91         msg.msg2 = 0;
 92         msg.msg3 = 0;
 93         stnid = priv->nd->rfr_station;
 94         do {
 95                 mflags = nlm_cop2_enable_irqsave();
 96                 ret = nlm_fmn_send(1, 0, stnid, &msg);
 97                 nlm_cop2_disable_irqrestore(mflags);
 98                 if (ret == 0)
 99                         return 0;
100         } while (++num_try < 10000);
101 
102         netdev_err(priv->ndev, "Send to RFR failed in RX path\n");
103         return ret;
104 }
105 
106 static inline unsigned char *xlr_alloc_skb(void)
107 {
108         struct sk_buff *skb;
109         int buf_len = sizeof(struct sk_buff *);
110         unsigned char *skb_data;
111 
112         /* skb->data is cache aligned */
113         skb = alloc_skb(XLR_RX_BUF_SIZE, GFP_ATOMIC);
114         if (!skb)
115                 return NULL;
116         skb_data = skb->data;
117         skb_put(skb, MAC_SKB_BACK_PTR_SIZE);
118         skb_pull(skb, MAC_SKB_BACK_PTR_SIZE);
119         memcpy(skb_data, &skb, buf_len);
120 
121         return skb->data;
122 }
123 
124 static void xlr_net_fmn_handler(int bkt, int src_stnid, int size, int code,
125                                 struct nlm_fmn_msg *msg, void *arg)
126 {
127         struct sk_buff *skb;
128         void *skb_data = NULL;
129         struct net_device *ndev;
130         struct xlr_net_priv *priv;
131         u32 port, length;
132         unsigned char *addr;
133         struct xlr_adapter *adapter = arg;
134 
135         length = (msg->msg0 >> 40) & 0x3fff;
136         if (length == 0) {
137                 addr = bus_to_virt(msg->msg0 & 0xffffffffffULL);
138                 addr = addr - MAC_SKB_BACK_PTR_SIZE;
139                 skb = (struct sk_buff *)(*(unsigned long *)addr);
140                 dev_kfree_skb_any((struct sk_buff *)addr);
141         } else {
142                 addr = (unsigned char *)
143                         bus_to_virt(msg->msg0 & 0xffffffffe0ULL);
144                 length = length - BYTE_OFFSET - MAC_CRC_LEN;
145                 port = ((int)msg->msg0) & 0x0f;
146                 addr = addr - MAC_SKB_BACK_PTR_SIZE;
147                 skb = (struct sk_buff *)(*(unsigned long *)addr);
148                 skb->dev = adapter->netdev[port];
149                 if (!skb->dev)
150                         return;
151                 ndev = skb->dev;
152                 priv = netdev_priv(ndev);
153 
154                 /* 16 byte IP header align */
155                 skb_reserve(skb, BYTE_OFFSET);
156                 skb_put(skb, length);
157                 skb->protocol = eth_type_trans(skb, skb->dev);
158                 skb->dev->last_rx = jiffies;
159                 netif_rx(skb);
160                 /* Fill rx ring */
161                 skb_data = xlr_alloc_skb();
162                 if (skb_data)
163                         send_to_rfr_fifo(priv, skb_data);
164         }
165 }
166 
167 static struct phy_device *xlr_get_phydev(struct xlr_net_priv *priv)
168 {
169         return mdiobus_get_phy(priv->mii_bus, priv->phy_addr);
170 }
171 
172 /*
173  * Ethtool operation
174  */
175 static int xlr_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
176 {
177         struct xlr_net_priv *priv = netdev_priv(ndev);
178         struct phy_device *phydev = xlr_get_phydev(priv);
179 
180         if (!phydev)
181                 return -ENODEV;
182         return phy_ethtool_gset(phydev, ecmd);
183 }
184 
185 static int xlr_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
186 {
187         struct xlr_net_priv *priv = netdev_priv(ndev);
188         struct phy_device *phydev = xlr_get_phydev(priv);
189 
190         if (!phydev)
191                 return -ENODEV;
192         return phy_ethtool_sset(phydev, ecmd);
193 }
194 
195 static struct ethtool_ops xlr_ethtool_ops = {
196         .get_settings = xlr_get_settings,
197         .set_settings = xlr_set_settings,
198 };
199 
200 /*
201  * Net operations
202  */
203 static int xlr_net_fill_rx_ring(struct net_device *ndev)
204 {
205         void *skb_data;
206         struct xlr_net_priv *priv = netdev_priv(ndev);
207         int i;
208 
209         for (i = 0; i < MAX_FRIN_SPILL / 4; i++) {
210                 skb_data = xlr_alloc_skb();
211                 if (!skb_data) {
212                         netdev_err(ndev, "SKB allocation failed\n");
213                         return -ENOMEM;
214                 }
215                 send_to_rfr_fifo(priv, skb_data);
216         }
217         netdev_info(ndev, "Rx ring setup done\n");
218         return 0;
219 }
220 
221 static int xlr_net_open(struct net_device *ndev)
222 {
223         u32 err;
224         struct xlr_net_priv *priv = netdev_priv(ndev);
225         struct phy_device *phydev = xlr_get_phydev(priv);
226 
227         /* schedule a link state check */
228         phy_start(phydev);
229 
230         err = phy_start_aneg(phydev);
231         if (err) {
232                 pr_err("Autoneg failed\n");
233                 return err;
234         }
235         /* Setup the speed from PHY to internal reg*/
236         xlr_set_gmac_speed(priv);
237 
238         netif_tx_start_all_queues(ndev);
239 
240         return 0;
241 }
242 
243 static int xlr_net_stop(struct net_device *ndev)
244 {
245         struct xlr_net_priv *priv = netdev_priv(ndev);
246         struct phy_device *phydev = xlr_get_phydev(priv);
247 
248         phy_stop(phydev);
249         netif_tx_stop_all_queues(ndev);
250         return 0;
251 }
252 
253 static void xlr_make_tx_desc(struct nlm_fmn_msg *msg, unsigned long addr,
254                              struct sk_buff *skb)
255 {
256         unsigned long physkb = virt_to_phys(skb);
257         int cpu_core = nlm_core_id();
258         int fr_stn_id = cpu_core * 8 + XLR_FB_STN;      /* FB to 6th bucket */
259 
260         msg->msg0 = (((u64)1 << 63)     |       /* End of packet descriptor */
261                 ((u64)127 << 54)        |       /* No Free back */
262                 (u64)skb->len << 40     |       /* Length of data */
263                 ((u64)addr));
264         msg->msg1 = (((u64)1 << 63)     |
265                 ((u64)fr_stn_id << 54)  |       /* Free back id */
266                 (u64)0 << 40            |       /* Set len to 0 */
267                 ((u64)physkb  & 0xffffffff));   /* 32bit address */
268         msg->msg2 = 0;
269         msg->msg3 = 0;
270 }
271 
272 static void __maybe_unused xlr_wakeup_queue(unsigned long dev)
273 {
274         struct net_device *ndev = (struct net_device *)dev;
275         struct xlr_net_priv *priv = netdev_priv(ndev);
276         struct phy_device *phydev = xlr_get_phydev(priv);
277 
278         if (phydev->link)
279                 netif_tx_wake_queue(netdev_get_tx_queue(ndev, priv->wakeup_q));
280 }
281 
282 static netdev_tx_t xlr_net_start_xmit(struct sk_buff *skb,
283                                       struct net_device *ndev)
284 {
285         struct nlm_fmn_msg msg;
286         struct xlr_net_priv *priv = netdev_priv(ndev);
287         int ret;
288         u32 flags;
289 
290         xlr_make_tx_desc(&msg, virt_to_phys(skb->data), skb);
291         flags = nlm_cop2_enable_irqsave();
292         ret = nlm_fmn_send(2, 0, priv->tx_stnid, &msg);
293         nlm_cop2_disable_irqrestore(flags);
294         if (ret)
295                 dev_kfree_skb_any(skb);
296         return NETDEV_TX_OK;
297 }
298 
299 static u16 xlr_net_select_queue(struct net_device *ndev, struct sk_buff *skb,
300                                 void *accel_priv,
301                                 select_queue_fallback_t fallback)
302 {
303         return (u16)smp_processor_id();
304 }
305 
306 static void xlr_hw_set_mac_addr(struct net_device *ndev)
307 {
308         struct xlr_net_priv *priv = netdev_priv(ndev);
309 
310         /* set mac station address */
311         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0,
312                      ((ndev->dev_addr[5] << 24) | (ndev->dev_addr[4] << 16) |
313                      (ndev->dev_addr[3] << 8) | (ndev->dev_addr[2])));
314         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1,
315                      ((ndev->dev_addr[1] << 24) | (ndev->dev_addr[0] << 16)));
316 
317         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff);
318         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
319         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff);
320         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
321 
322         xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG,
323                      (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
324                      (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
325                      (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID));
326 
327         if (priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII ||
328             priv->nd->phy_interface == PHY_INTERFACE_MODE_SGMII)
329                 xlr_reg_update(priv->base_addr, R_IPG_IFG, MAC_B2B_IPG, 0x7f);
330 }
331 
332 static int xlr_net_set_mac_addr(struct net_device *ndev, void *data)
333 {
334         int err;
335 
336         err = eth_mac_addr(ndev, data);
337         if (err)
338                 return err;
339         xlr_hw_set_mac_addr(ndev);
340         return 0;
341 }
342 
343 static void xlr_set_rx_mode(struct net_device *ndev)
344 {
345         struct xlr_net_priv *priv = netdev_priv(ndev);
346         u32 regval;
347 
348         regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG);
349 
350         if (ndev->flags & IFF_PROMISC) {
351                 regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
352                 (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
353                 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
354                 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
355         } else {
356                 regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
357                 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
358         }
359 
360         xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval);
361 }
362 
363 static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats)
364 {
365         struct xlr_net_priv *priv = netdev_priv(ndev);
366 
367         stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER);
368         stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER);
369         stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER);
370         stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER);
371         stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER);
372         stats->rx_dropped = xlr_nae_rdreg(priv->base_addr,
373                         RX_DROP_PACKET_COUNTER);
374         stats->tx_dropped = xlr_nae_rdreg(priv->base_addr,
375                         TX_DROP_FRAME_COUNTER);
376 
377         stats->multicast = xlr_nae_rdreg(priv->base_addr,
378                         RX_MULTICAST_PACKET_COUNTER);
379         stats->collisions = xlr_nae_rdreg(priv->base_addr,
380                         TX_TOTAL_COLLISION_COUNTER);
381 
382         stats->rx_length_errors = xlr_nae_rdreg(priv->base_addr,
383                         RX_FRAME_LENGTH_ERROR_COUNTER);
384         stats->rx_over_errors = xlr_nae_rdreg(priv->base_addr,
385                         RX_DROP_PACKET_COUNTER);
386         stats->rx_crc_errors = xlr_nae_rdreg(priv->base_addr,
387                         RX_FCS_ERROR_COUNTER);
388         stats->rx_frame_errors = xlr_nae_rdreg(priv->base_addr,
389                         RX_ALIGNMENT_ERROR_COUNTER);
390 
391         stats->rx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
392                         RX_DROP_PACKET_COUNTER);
393         stats->rx_missed_errors = xlr_nae_rdreg(priv->base_addr,
394                         RX_CARRIER_SENSE_ERROR_COUNTER);
395 
396         stats->rx_errors = (stats->rx_over_errors + stats->rx_crc_errors +
397                         stats->rx_frame_errors + stats->rx_fifo_errors +
398                         stats->rx_missed_errors);
399 
400         stats->tx_aborted_errors = xlr_nae_rdreg(priv->base_addr,
401                         TX_EXCESSIVE_COLLISION_PACKET_COUNTER);
402         stats->tx_carrier_errors = xlr_nae_rdreg(priv->base_addr,
403                         TX_DROP_FRAME_COUNTER);
404         stats->tx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
405                         TX_DROP_FRAME_COUNTER);
406 }
407 
408 static struct rtnl_link_stats64 *xlr_get_stats64(struct net_device *ndev,
409                                                  struct rtnl_link_stats64 *stats
410                                                  )
411 {
412         xlr_stats(ndev, stats);
413         return stats;
414 }
415 
416 static struct net_device_ops xlr_netdev_ops = {
417         .ndo_open = xlr_net_open,
418         .ndo_stop = xlr_net_stop,
419         .ndo_start_xmit = xlr_net_start_xmit,
420         .ndo_select_queue = xlr_net_select_queue,
421         .ndo_set_mac_address = xlr_net_set_mac_addr,
422         .ndo_set_rx_mode = xlr_set_rx_mode,
423         .ndo_get_stats64 = xlr_get_stats64,
424 };
425 
426 /*
427  * Gmac init
428  */
429 static void *xlr_config_spill(struct xlr_net_priv *priv, int reg_start_0,
430                               int reg_start_1, int reg_size, int size)
431 {
432         void *spill;
433         u32 *base;
434         unsigned long phys_addr;
435         u32 spill_size;
436 
437         base = priv->base_addr;
438         spill_size = size;
439         spill = kmalloc(spill_size + SMP_CACHE_BYTES, GFP_ATOMIC);
440         if (!spill) {
441                 pr_err("Unable to allocate memory for spill area!\n");
442                 return ZERO_SIZE_PTR;
443         }
444 
445         spill = PTR_ALIGN(spill, SMP_CACHE_BYTES);
446         phys_addr = virt_to_phys(spill);
447         dev_dbg(&priv->ndev->dev, "Allocated spill %d bytes at %lx\n",
448                 size, phys_addr);
449         xlr_nae_wreg(base, reg_start_0, (phys_addr >> 5) & 0xffffffff);
450         xlr_nae_wreg(base, reg_start_1, ((u64)phys_addr >> 37) & 0x07);
451         xlr_nae_wreg(base, reg_size, spill_size);
452 
453         return spill;
454 }
455 
456 /*
457  * Configure the 6 FIFO's that are used by the network accelarator to
458  * communicate with the rest of the XLx device. 4 of the FIFO's are for
459  * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding
460  * the NA with free descriptors.
461  */
462 static void xlr_config_fifo_spill_area(struct xlr_net_priv *priv)
463 {
464         priv->frin_spill = xlr_config_spill(priv,
465                         R_REG_FRIN_SPILL_MEM_START_0,
466                         R_REG_FRIN_SPILL_MEM_START_1,
467                         R_REG_FRIN_SPILL_MEM_SIZE,
468                         MAX_FRIN_SPILL *
469                         sizeof(u64));
470         priv->frout_spill = xlr_config_spill(priv,
471                         R_FROUT_SPILL_MEM_START_0,
472                         R_FROUT_SPILL_MEM_START_1,
473                         R_FROUT_SPILL_MEM_SIZE,
474                         MAX_FROUT_SPILL *
475                         sizeof(u64));
476         priv->class_0_spill = xlr_config_spill(priv,
477                         R_CLASS0_SPILL_MEM_START_0,
478                         R_CLASS0_SPILL_MEM_START_1,
479                         R_CLASS0_SPILL_MEM_SIZE,
480                         MAX_CLASS_0_SPILL *
481                         sizeof(u64));
482         priv->class_1_spill = xlr_config_spill(priv,
483                         R_CLASS1_SPILL_MEM_START_0,
484                         R_CLASS1_SPILL_MEM_START_1,
485                         R_CLASS1_SPILL_MEM_SIZE,
486                         MAX_CLASS_1_SPILL *
487                         sizeof(u64));
488         priv->class_2_spill = xlr_config_spill(priv,
489                         R_CLASS2_SPILL_MEM_START_0,
490                         R_CLASS2_SPILL_MEM_START_1,
491                         R_CLASS2_SPILL_MEM_SIZE,
492                         MAX_CLASS_2_SPILL *
493                         sizeof(u64));
494         priv->class_3_spill = xlr_config_spill(priv,
495                         R_CLASS3_SPILL_MEM_START_0,
496                         R_CLASS3_SPILL_MEM_START_1,
497                         R_CLASS3_SPILL_MEM_SIZE,
498                         MAX_CLASS_3_SPILL *
499                         sizeof(u64));
500 }
501 
502 /*
503  * Configure PDE to Round-Robin distribution of packets to the
504  * available cpu
505  */
506 static void xlr_config_pde(struct xlr_net_priv *priv)
507 {
508         int i = 0;
509         u64 bkt_map = 0;
510 
511         /* Each core has 8 buckets(station) */
512         for (i = 0; i < hweight32(priv->nd->cpu_mask); i++)
513                 bkt_map |= (0xff << (i * 8));
514 
515         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0, (bkt_map & 0xffffffff));
516         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0 + 1,
517                      ((bkt_map >> 32) & 0xffffffff));
518 
519         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1, (bkt_map & 0xffffffff));
520         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1 + 1,
521                      ((bkt_map >> 32) & 0xffffffff));
522 
523         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2, (bkt_map & 0xffffffff));
524         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2 + 1,
525                      ((bkt_map >> 32) & 0xffffffff));
526 
527         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3, (bkt_map & 0xffffffff));
528         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3 + 1,
529                      ((bkt_map >> 32) & 0xffffffff));
530 }
531 
532 /*
533  * Setup the Message ring credits, bucket size and other
534  * common configuration
535  */
536 static int xlr_config_common(struct xlr_net_priv *priv)
537 {
538         struct xlr_fmn_info *gmac = priv->nd->gmac_fmn_info;
539         int start_stn_id = gmac->start_stn_id;
540         int end_stn_id = gmac->end_stn_id;
541         int *bucket_size = priv->nd->bucket_size;
542         int i, j, err;
543 
544         /* Setting non-core MsgBktSize(0x321 - 0x325) */
545         for (i = start_stn_id; i <= end_stn_id; i++) {
546                 xlr_nae_wreg(priv->base_addr,
547                              R_GMAC_RFR0_BUCKET_SIZE + i - start_stn_id,
548                              bucket_size[i]);
549         }
550 
551         /*
552          * Setting non-core Credit counter register
553          * Distributing Gmac's credit to CPU's
554          */
555         for (i = 0; i < 8; i++) {
556                 for (j = 0; j < 8; j++)
557                         xlr_nae_wreg(priv->base_addr,
558                                      (R_CC_CPU0_0 + (i * 8)) + j,
559                                      gmac->credit_config[(i * 8) + j]);
560         }
561 
562         xlr_nae_wreg(priv->base_addr, R_MSG_TX_THRESHOLD, 3);
563         xlr_nae_wreg(priv->base_addr, R_DMACR0, 0xffffffff);
564         xlr_nae_wreg(priv->base_addr, R_DMACR1, 0xffffffff);
565         xlr_nae_wreg(priv->base_addr, R_DMACR2, 0xffffffff);
566         xlr_nae_wreg(priv->base_addr, R_DMACR3, 0xffffffff);
567         xlr_nae_wreg(priv->base_addr, R_FREEQCARVE, 0);
568 
569         err = xlr_net_fill_rx_ring(priv->ndev);
570         if (err)
571                 return err;
572         nlm_register_fmn_handler(start_stn_id, end_stn_id, xlr_net_fmn_handler,
573                                  priv->adapter);
574         return 0;
575 }
576 
577 static void xlr_config_translate_table(struct xlr_net_priv *priv)
578 {
579         u32 cpu_mask;
580         u32 val;
581         int bkts[32]; /* one bucket is assumed for each cpu */
582         int b1, b2, c1, c2, i, j, k;
583         int use_bkt;
584 
585         use_bkt = 0;
586         cpu_mask = priv->nd->cpu_mask;
587 
588         pr_info("Using %s-based distribution\n",
589                 (use_bkt) ? "bucket" : "class");
590         j = 0;
591         for (i = 0; i < 32; i++) {
592                 if ((1 << i) & cpu_mask) {
593                         /* for each cpu, mark the 4+threadid bucket */
594                         bkts[j] = ((i / 4) * 8) + (i % 4);
595                         j++;
596                 }
597         }
598 
599         /*configure the 128 * 9 Translation table to send to available buckets*/
600         k = 0;
601         c1 = 3;
602         c2 = 0;
603         for (i = 0; i < 64; i++) {
604                 /*
605                  * On use_bkt set the b0, b1 are used, else
606                  * the 4 classes are used, here implemented
607                  * a logic to distribute the packets to the
608                  * buckets equally or based on the class
609                  */
610                 c1 = (c1 + 1) & 3;
611                 c2 = (c1 + 1) & 3;
612                 b1 = bkts[k];
613                 k = (k + 1) % j;
614                 b2 = bkts[k];
615                 k = (k + 1) % j;
616 
617                 val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
618                                 (c2 << 7) | (b2 << 1) | (use_bkt << 0));
619                 dev_dbg(&priv->ndev->dev, "Table[%d] b1=%d b2=%d c1=%d c2=%d\n",
620                         i, b1, b2, c1, c2);
621                 xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val);
622                 c1 = c2;
623         }
624 }
625 
626 static void xlr_config_parser(struct xlr_net_priv *priv)
627 {
628         u32 val;
629 
630         /* Mark it as ETHERNET type */
631         xlr_nae_wreg(priv->base_addr, R_L2TYPE_0, 0x01);
632 
633         /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
634         xlr_nae_wreg(priv->base_addr, R_PARSERCONFIGREG,
635                      ((0x7f << 8) | (1 << 1)));
636 
637         /* configure the parser : L2 Type is configured in the bootloader */
638         /* extract IP: src, dest protocol */
639         xlr_nae_wreg(priv->base_addr, R_L3CTABLE,
640                      (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
641                      (0x0800 << 0));
642         xlr_nae_wreg(priv->base_addr, R_L3CTABLE + 1,
643                      (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) |
644                      (16 << 4) | 4);
645 
646         /* Configure to extract SRC port and Dest port for TCP and UDP pkts */
647         xlr_nae_wreg(priv->base_addr, R_L4CTABLE, 6);
648         xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 2, 17);
649         val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
650         xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val);
651         xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val);
652 
653         xlr_config_translate_table(priv);
654 }
655 
656 static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val)
657 {
658         unsigned long timeout, stoptime, checktime;
659         int timedout;
660 
661         /* 100ms timeout*/
662         timeout = msecs_to_jiffies(100);
663         stoptime = jiffies + timeout;
664         timedout = 0;
665 
666         xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, (phy_addr << 8) | regnum);
667 
668         /* Write the data which starts the write cycle */
669         xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32)val);
670 
671         /* poll for the read cycle to complete */
672         while (!timedout) {
673                 checktime = jiffies;
674                 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
675                         break;
676                 timedout = time_after(checktime, stoptime);
677         }
678         if (timedout) {
679                 pr_info("Phy device write err: device busy");
680                 return -EBUSY;
681         }
682 
683         return 0;
684 }
685 
686 static int xlr_phy_read(u32 *base_addr, int phy_addr, int regnum)
687 {
688         unsigned long timeout, stoptime, checktime;
689         int timedout;
690 
691         /* 100ms timeout*/
692         timeout = msecs_to_jiffies(100);
693         stoptime = jiffies + timeout;
694         timedout = 0;
695 
696         /* setup the phy reg to be used */
697         xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS,
698                      (phy_addr << 8) | (regnum << 0));
699 
700         /* Issue the read command */
701         xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND,
702                      (1 << O_MII_MGMT_COMMAND__rstat));
703 
704         /* poll for the read cycle to complete */
705         while (!timedout) {
706                 checktime = jiffies;
707                 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
708                         break;
709                 timedout = time_after(checktime, stoptime);
710         }
711         if (timedout) {
712                 pr_info("Phy device read err: device busy");
713                 return -EBUSY;
714         }
715 
716         /* clear the read cycle */
717         xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 0);
718 
719         /* Read the data */
720         return xlr_nae_rdreg(base_addr, R_MII_MGMT_STATUS);
721 }
722 
723 static int xlr_mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 val)
724 {
725         struct xlr_net_priv *priv = bus->priv;
726         int ret;
727 
728         ret = xlr_phy_write(priv->mii_addr, phy_addr, regnum, val);
729         dev_dbg(&priv->ndev->dev, "mii_write phy %d : %d <- %x [%x]\n",
730                 phy_addr, regnum, val, ret);
731         return ret;
732 }
733 
734 static int xlr_mii_read(struct mii_bus *bus, int phy_addr, int regnum)
735 {
736         struct xlr_net_priv *priv = bus->priv;
737         int ret;
738 
739         ret =  xlr_phy_read(priv->mii_addr, phy_addr, regnum);
740         dev_dbg(&priv->ndev->dev, "mii_read phy %d : %d [%x]\n",
741                 phy_addr, regnum, ret);
742         return ret;
743 }
744 
745 /*
746  * XLR ports are RGMII. XLS ports are SGMII mostly except the port0,
747  * which can be configured either SGMII or RGMII, considered SGMII
748  * by default, if board setup to RGMII the port_type need to set
749  * accordingly.Serdes and PCS layer need to configured for SGMII
750  */
751 static void xlr_sgmii_init(struct xlr_net_priv *priv)
752 {
753         int phy;
754 
755         xlr_phy_write(priv->serdes_addr, 26, 0, 0x6DB0);
756         xlr_phy_write(priv->serdes_addr, 26, 1, 0xFFFF);
757         xlr_phy_write(priv->serdes_addr, 26, 2, 0xB6D0);
758         xlr_phy_write(priv->serdes_addr, 26, 3, 0x00FF);
759         xlr_phy_write(priv->serdes_addr, 26, 4, 0x0000);
760         xlr_phy_write(priv->serdes_addr, 26, 5, 0x0000);
761         xlr_phy_write(priv->serdes_addr, 26, 6, 0x0005);
762         xlr_phy_write(priv->serdes_addr, 26, 7, 0x0001);
763         xlr_phy_write(priv->serdes_addr, 26, 8, 0x0000);
764         xlr_phy_write(priv->serdes_addr, 26, 9, 0x0000);
765         xlr_phy_write(priv->serdes_addr, 26, 10, 0x0000);
766 
767         /* program  GPIO values for serdes init parameters */
768         xlr_nae_wreg(priv->gpio_addr, 0x20, 0x7e6802);
769         xlr_nae_wreg(priv->gpio_addr, 0x10, 0x7104);
770 
771         xlr_nae_wreg(priv->gpio_addr, 0x22, 0x7e6802);
772         xlr_nae_wreg(priv->gpio_addr, 0x21, 0x7104);
773 
774         /* enable autoneg - more magic */
775         phy = priv->phy_addr % 4 + 27;
776         xlr_phy_write(priv->pcs_addr, phy, 0, 0x1000);
777         xlr_phy_write(priv->pcs_addr, phy, 0, 0x0200);
778 }
779 
780 void xlr_set_gmac_speed(struct xlr_net_priv *priv)
781 {
782         struct phy_device *phydev = xlr_get_phydev(priv);
783         int speed;
784 
785         if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
786                 xlr_sgmii_init(priv);
787 
788         if (phydev->speed != priv->phy_speed) {
789                 speed = phydev->speed;
790                 if (speed == SPEED_1000) {
791                         /* Set interface to Byte mode */
792                         xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
793                         priv->phy_speed = speed;
794                 } else if (speed == SPEED_100 || speed == SPEED_10) {
795                         /* Set interface to Nibble mode */
796                         xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7117);
797                         priv->phy_speed = speed;
798                 }
799                 /* Set SGMII speed in Interface control reg */
800                 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
801                         if (speed == SPEED_10)
802                                 xlr_nae_wreg(priv->base_addr,
803                                              R_INTERFACE_CONTROL,
804                                              SGMII_SPEED_10);
805                         if (speed == SPEED_100)
806                                 xlr_nae_wreg(priv->base_addr,
807                                              R_INTERFACE_CONTROL,
808                                              SGMII_SPEED_100);
809                         if (speed == SPEED_1000)
810                                 xlr_nae_wreg(priv->base_addr,
811                                              R_INTERFACE_CONTROL,
812                                              SGMII_SPEED_1000);
813                 }
814                 if (speed == SPEED_10)
815                         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x2);
816                 if (speed == SPEED_100)
817                         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x1);
818                 if (speed == SPEED_1000)
819                         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x0);
820         }
821         pr_info("gmac%d : %dMbps\n", priv->port_id, priv->phy_speed);
822 }
823 
824 static void xlr_gmac_link_adjust(struct net_device *ndev)
825 {
826         struct xlr_net_priv *priv = netdev_priv(ndev);
827         struct phy_device *phydev = xlr_get_phydev(priv);
828         u32 intreg;
829 
830         intreg = xlr_nae_rdreg(priv->base_addr, R_INTREG);
831         if (phydev->link) {
832                 if (phydev->speed != priv->phy_speed) {
833                         xlr_set_gmac_speed(priv);
834                         pr_info("gmac%d : Link up\n", priv->port_id);
835                 }
836         } else {
837                 xlr_set_gmac_speed(priv);
838                 pr_info("gmac%d : Link down\n", priv->port_id);
839         }
840 }
841 
842 static int xlr_mii_probe(struct xlr_net_priv *priv)
843 {
844         struct phy_device *phydev = xlr_get_phydev(priv);
845 
846         if (!phydev) {
847                 pr_err("no PHY found on phy_addr %d\n", priv->phy_addr);
848                 return -ENODEV;
849         }
850 
851         /* Attach MAC to PHY */
852         phydev = phy_connect(priv->ndev, phydev_name(phydev),
853                              xlr_gmac_link_adjust, priv->nd->phy_interface);
854 
855         if (IS_ERR(phydev)) {
856                 pr_err("could not attach PHY\n");
857                 return PTR_ERR(phydev);
858         }
859         phydev->supported &= (ADVERTISED_10baseT_Full
860                                 | ADVERTISED_10baseT_Half
861                                 | ADVERTISED_100baseT_Full
862                                 | ADVERTISED_100baseT_Half
863                                 | ADVERTISED_1000baseT_Full
864                                 | ADVERTISED_Autoneg
865                                 | ADVERTISED_MII);
866 
867         phydev->advertising = phydev->supported;
868         phy_attached_info(phydev);
869         return 0;
870 }
871 
872 static int xlr_setup_mdio(struct xlr_net_priv *priv,
873                           struct platform_device *pdev)
874 {
875         int err;
876 
877         priv->mii_bus = mdiobus_alloc();
878         if (!priv->mii_bus) {
879                 pr_err("mdiobus alloc failed\n");
880                 return -ENOMEM;
881         }
882 
883         priv->mii_bus->priv = priv;
884         priv->mii_bus->name = "xlr-mdio";
885         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
886                  priv->mii_bus->name, priv->port_id);
887         priv->mii_bus->read = xlr_mii_read;
888         priv->mii_bus->write = xlr_mii_write;
889         priv->mii_bus->parent = &pdev->dev;
890 
891         /* Scan only the enabled address */
892         priv->mii_bus->phy_mask = ~(1 << priv->phy_addr);
893 
894         /* setting clock divisor to 54 */
895         xlr_nae_wreg(priv->base_addr, R_MII_MGMT_CONFIG, 0x7);
896 
897         err = mdiobus_register(priv->mii_bus);
898         if (err) {
899                 mdiobus_free(priv->mii_bus);
900                 pr_err("mdio bus registration failed\n");
901                 return err;
902         }
903 
904         pr_info("Registered mdio bus id : %s\n", priv->mii_bus->id);
905         err = xlr_mii_probe(priv);
906         if (err) {
907                 mdiobus_free(priv->mii_bus);
908                 return err;
909         }
910         return 0;
911 }
912 
913 static void xlr_port_enable(struct xlr_net_priv *priv)
914 {
915         u32 prid = (read_c0_prid() & 0xf000);
916 
917         /* Setup MAC_CONFIG reg if (xls & rgmii) */
918         if ((prid == 0x8000 || prid == 0x4000 || prid == 0xc000) &&
919             priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII)
920                 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
921                                (1 << O_RX_CONTROL__RGMII),
922                                (1 << O_RX_CONTROL__RGMII));
923 
924         /* Rx Tx enable */
925         xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
926                        ((1 << O_MAC_CONFIG_1__rxen) |
927                         (1 << O_MAC_CONFIG_1__txen) |
928                         (1 << O_MAC_CONFIG_1__rxfc) |
929                         (1 << O_MAC_CONFIG_1__txfc)),
930                        ((1 << O_MAC_CONFIG_1__rxen) |
931                         (1 << O_MAC_CONFIG_1__txen) |
932                         (1 << O_MAC_CONFIG_1__rxfc) |
933                         (1 << O_MAC_CONFIG_1__txfc)));
934 
935         /* Setup tx control reg */
936         xlr_reg_update(priv->base_addr, R_TX_CONTROL,
937                        ((1 << O_TX_CONTROL__TXENABLE) |
938                        (512 << O_TX_CONTROL__TXTHRESHOLD)), 0x3fff);
939 
940         /* Setup rx control reg */
941         xlr_reg_update(priv->base_addr, R_RX_CONTROL,
942                        1 << O_RX_CONTROL__RXENABLE,
943                        1 << O_RX_CONTROL__RXENABLE);
944 }
945 
946 static void xlr_port_disable(struct xlr_net_priv *priv)
947 {
948         /* Setup MAC_CONFIG reg */
949         /* Rx Tx disable*/
950         xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
951                        ((1 << O_MAC_CONFIG_1__rxen) |
952                         (1 << O_MAC_CONFIG_1__txen) |
953                         (1 << O_MAC_CONFIG_1__rxfc) |
954                         (1 << O_MAC_CONFIG_1__txfc)), 0x0);
955 
956         /* Setup tx control reg */
957         xlr_reg_update(priv->base_addr, R_TX_CONTROL,
958                        ((1 << O_TX_CONTROL__TXENABLE) |
959                        (512 << O_TX_CONTROL__TXTHRESHOLD)), 0);
960 
961         /* Setup rx control reg */
962         xlr_reg_update(priv->base_addr, R_RX_CONTROL,
963                        1 << O_RX_CONTROL__RXENABLE, 0);
964 }
965 
966 /*
967  * Initialization of gmac
968  */
969 static int xlr_gmac_init(struct xlr_net_priv *priv,
970                          struct platform_device *pdev)
971 {
972         int ret;
973 
974         pr_info("Initializing the gmac%d\n", priv->port_id);
975 
976         xlr_port_disable(priv);
977 
978         xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL,
979                      (1 << O_DESC_PACK_CTRL__MAXENTRY) |
980                      (BYTE_OFFSET << O_DESC_PACK_CTRL__BYTEOFFSET) |
981                      (1600 << O_DESC_PACK_CTRL__REGULARSIZE));
982 
983         ret = xlr_setup_mdio(priv, pdev);
984         if (ret)
985                 return ret;
986         xlr_port_enable(priv);
987 
988         /* Enable Full-duplex/1000Mbps/CRC */
989         xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
990         /* speed 2.5Mhz */
991         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02);
992         /* Setup Interrupt mask reg */
993         xlr_nae_wreg(priv->base_addr, R_INTMASK, (1 << O_INTMASK__TXILLEGAL) |
994                      (1 << O_INTMASK__MDINT) | (1 << O_INTMASK__TXFETCHERROR) |
995                      (1 << O_INTMASK__P2PSPILLECC) | (1 << O_INTMASK__TAGFULL) |
996                      (1 << O_INTMASK__UNDERRUN) | (1 << O_INTMASK__ABORT));
997 
998         /* Clear all stats */
999         xlr_reg_update(priv->base_addr, R_STATCTRL, 0, 1 << O_STATCTRL__CLRCNT);
1000         xlr_reg_update(priv->base_addr, R_STATCTRL, 1 << 2, 1 << 2);
1001         return 0;
1002 }
1003 
1004 static int xlr_net_probe(struct platform_device *pdev)
1005 {
1006         struct xlr_net_priv *priv = NULL;
1007         struct net_device *ndev;
1008         struct resource *res;
1009         struct xlr_adapter *adapter;
1010         int err, port;
1011 
1012         pr_info("XLR/XLS Ethernet Driver controller %d\n", pdev->id);
1013         /*
1014          * Allocate our adapter data structure and attach it to the device.
1015          */
1016         adapter = (struct xlr_adapter *)
1017                 devm_kzalloc(&pdev->dev, sizeof(*adapter), GFP_KERNEL);
1018         if (!adapter) {
1019                 err = -ENOMEM;
1020                 return err;
1021         }
1022 
1023         /*
1024          * XLR and XLS have 1 and 2 NAE controller respectively
1025          * Each controller has 4 gmac ports, mapping each controller
1026          * under one parent device, 4 gmac ports under one device.
1027          */
1028         for (port = 0; port < pdev->num_resources / 2; port++) {
1029                 ndev = alloc_etherdev_mq(sizeof(struct xlr_net_priv), 32);
1030                 if (!ndev) {
1031                         dev_err(&pdev->dev,
1032                                 "Allocation of Ethernet device failed\n");
1033                         return -ENOMEM;
1034                 }
1035 
1036                 priv = netdev_priv(ndev);
1037                 priv->pdev = pdev;
1038                 priv->ndev = ndev;
1039                 priv->port_id = (pdev->id * 4) + port;
1040                 priv->nd = (struct xlr_net_data *)pdev->dev.platform_data;
1041                 res = platform_get_resource(pdev, IORESOURCE_MEM, port);
1042                 priv->base_addr = devm_ioremap_resource(&pdev->dev, res);
1043                 if (IS_ERR(priv->base_addr)) {
1044                         err = PTR_ERR(priv->base_addr);
1045                         goto err_gmac;
1046                 }
1047                 priv->adapter = adapter;
1048                 adapter->netdev[port] = ndev;
1049 
1050                 res = platform_get_resource(pdev, IORESOURCE_IRQ, port);
1051                 if (!res) {
1052                         dev_err(&pdev->dev, "No irq resource for MAC %d\n",
1053                                 priv->port_id);
1054                         err = -ENODEV;
1055                         goto err_gmac;
1056                 }
1057 
1058                 ndev->irq = res->start;
1059 
1060                 priv->phy_addr = priv->nd->phy_addr[port];
1061                 priv->tx_stnid = priv->nd->tx_stnid[port];
1062                 priv->mii_addr = priv->nd->mii_addr;
1063                 priv->serdes_addr = priv->nd->serdes_addr;
1064                 priv->pcs_addr = priv->nd->pcs_addr;
1065                 priv->gpio_addr = priv->nd->gpio_addr;
1066 
1067                 ndev->netdev_ops = &xlr_netdev_ops;
1068                 ndev->watchdog_timeo = HZ;
1069 
1070                 /* Setup Mac address and Rx mode */
1071                 eth_hw_addr_random(ndev);
1072                 xlr_hw_set_mac_addr(ndev);
1073                 xlr_set_rx_mode(ndev);
1074 
1075                 priv->num_rx_desc += MAX_NUM_DESC_SPILL;
1076                 ndev->ethtool_ops = &xlr_ethtool_ops;
1077                 SET_NETDEV_DEV(ndev, &pdev->dev);
1078 
1079                 xlr_config_fifo_spill_area(priv);
1080                 /* Configure PDE to Round-Robin pkt distribution */
1081                 xlr_config_pde(priv);
1082                 xlr_config_parser(priv);
1083 
1084                 /* Call init with respect to port */
1085                 if (strcmp(res->name, "gmac") == 0) {
1086                         err = xlr_gmac_init(priv, pdev);
1087                         if (err) {
1088                                 dev_err(&pdev->dev, "gmac%d init failed\n",
1089                                         priv->port_id);
1090                                 goto err_gmac;
1091                         }
1092                 }
1093 
1094                 if (priv->port_id == 0 || priv->port_id == 4) {
1095                         err = xlr_config_common(priv);
1096                         if (err)
1097                                 goto err_netdev;
1098                 }
1099 
1100                 err = register_netdev(ndev);
1101                 if (err) {
1102                         dev_err(&pdev->dev,
1103                                 "Registering netdev failed for gmac%d\n",
1104                                 priv->port_id);
1105                         goto err_netdev;
1106                 }
1107                 platform_set_drvdata(pdev, priv);
1108         }
1109 
1110         return 0;
1111 
1112 err_netdev:
1113         mdiobus_free(priv->mii_bus);
1114 err_gmac:
1115         free_netdev(ndev);
1116         return err;
1117 }
1118 
1119 static int xlr_net_remove(struct platform_device *pdev)
1120 {
1121         struct xlr_net_priv *priv = platform_get_drvdata(pdev);
1122 
1123         unregister_netdev(priv->ndev);
1124         mdiobus_unregister(priv->mii_bus);
1125         mdiobus_free(priv->mii_bus);
1126         free_netdev(priv->ndev);
1127         return 0;
1128 }
1129 
1130 static struct platform_driver xlr_net_driver = {
1131         .probe          = xlr_net_probe,
1132         .remove         = xlr_net_remove,
1133         .driver         = {
1134                 .name   = "xlr-net",
1135         },
1136 };
1137 
1138 module_platform_driver(xlr_net_driver);
1139 
1140 MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
1141 MODULE_DESCRIPTION("Ethernet driver for Netlogic XLR/XLS");
1142 MODULE_LICENSE("Dual BSD/GPL");
1143 MODULE_ALIAS("platform:xlr-net");
1144 

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