Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/drivers/staging/netlogic/xlr_net.c

  1 /*
  2  * Copyright (c) 2003-2012 Broadcom Corporation
  3  * All Rights Reserved
  4  *
  5  * This software is available to you under a choice of one of two
  6  * licenses.  You may choose to be licensed under the terms of the GNU
  7  * General Public License (GPL) Version 2, available from the file
  8  * COPYING in the main directory of this source tree, or the Broadcom
  9  * license below:
 10  *
 11  * Redistribution and use in source and binary forms, with or without
 12  * modification, are permitted provided that the following conditions
 13  * are met:
 14  *
 15  * 1. Redistributions of source code must retain the above copyright
 16  *    notice, this list of conditions and the following disclaimer.
 17  * 2. Redistributions in binary form must reproduce the above copyright
 18  *    notice, this list of conditions and the following disclaimer in
 19  *    the documentation and/or other materials provided with the
 20  *    distribution.
 21  *
 22  * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
 23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 25  * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
 26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 33  */
 34 #include <linux/phy.h>
 35 #include <linux/delay.h>
 36 #include <linux/netdevice.h>
 37 #include <linux/smp.h>
 38 #include <linux/ethtool.h>
 39 #include <linux/module.h>
 40 #include <linux/etherdevice.h>
 41 #include <linux/skbuff.h>
 42 #include <linux/jiffies.h>
 43 #include <linux/interrupt.h>
 44 #include <linux/platform_device.h>
 45 
 46 #include <asm/mipsregs.h>
 47 /*
 48  * fmn.h - For FMN credit configuration and registering fmn_handler.
 49  * FMN is communication mechanism that allows processing agents within
 50  * XLR/XLS to communicate each other.
 51  */
 52 #include <asm/netlogic/xlr/fmn.h>
 53 
 54 #include "platform_net.h"
 55 #include "xlr_net.h"
 56 
 57 /*
 58  * The readl/writel implementation byteswaps on XLR/XLS, so
 59  * we need to use __raw_ IO to read the NAE registers
 60  * because they are in the big-endian MMIO area on the SoC.
 61  */
 62 static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val)
 63 {
 64         __raw_writel(val, base + reg);
 65 }
 66 
 67 static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg)
 68 {
 69         return __raw_readl(base + reg);
 70 }
 71 
 72 static inline void xlr_reg_update(u32 *base_addr, u32 off, u32 val, u32 mask)
 73 {
 74         u32 tmp;
 75 
 76         tmp = xlr_nae_rdreg(base_addr, off);
 77         xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask));
 78 }
 79 
 80 #define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES
 81 
 82 static int send_to_rfr_fifo(struct xlr_net_priv *priv, void *addr)
 83 {
 84         struct nlm_fmn_msg msg;
 85         int ret = 0, num_try = 0, stnid;
 86         unsigned long paddr, mflags;
 87 
 88         paddr = virt_to_bus(addr);
 89         msg.msg0 = (u64)paddr & 0xffffffffe0ULL;
 90         msg.msg1 = 0;
 91         msg.msg2 = 0;
 92         msg.msg3 = 0;
 93         stnid = priv->nd->rfr_station;
 94         do {
 95                 mflags = nlm_cop2_enable_irqsave();
 96                 ret = nlm_fmn_send(1, 0, stnid, &msg);
 97                 nlm_cop2_disable_irqrestore(mflags);
 98                 if (ret == 0)
 99                         return 0;
100         } while (++num_try < 10000);
101 
102         netdev_err(priv->ndev, "Send to RFR failed in RX path\n");
103         return ret;
104 }
105 
106 static inline unsigned char *xlr_alloc_skb(void)
107 {
108         struct sk_buff *skb;
109         int buf_len = sizeof(struct sk_buff *);
110         unsigned char *skb_data;
111 
112         /* skb->data is cache aligned */
113         skb = alloc_skb(XLR_RX_BUF_SIZE, GFP_ATOMIC);
114         if (!skb)
115                 return NULL;
116         skb_data = skb->data;
117         skb_put(skb, MAC_SKB_BACK_PTR_SIZE);
118         skb_pull(skb, MAC_SKB_BACK_PTR_SIZE);
119         memcpy(skb_data, &skb, buf_len);
120 
121         return skb->data;
122 }
123 
124 static void xlr_net_fmn_handler(int bkt, int src_stnid, int size, int code,
125                                 struct nlm_fmn_msg *msg, void *arg)
126 {
127         struct sk_buff *skb;
128         void *skb_data = NULL;
129         struct net_device *ndev;
130         struct xlr_net_priv *priv;
131         u32 port, length;
132         unsigned char *addr;
133         struct xlr_adapter *adapter = arg;
134 
135         length = (msg->msg0 >> 40) & 0x3fff;
136         if (length == 0) {
137                 addr = bus_to_virt(msg->msg0 & 0xffffffffffULL);
138                 addr = addr - MAC_SKB_BACK_PTR_SIZE;
139                 skb = (struct sk_buff *)(*(unsigned long *)addr);
140                 dev_kfree_skb_any((struct sk_buff *)addr);
141         } else {
142                 addr = (unsigned char *)
143                         bus_to_virt(msg->msg0 & 0xffffffffe0ULL);
144                 length = length - BYTE_OFFSET - MAC_CRC_LEN;
145                 port = ((int)msg->msg0) & 0x0f;
146                 addr = addr - MAC_SKB_BACK_PTR_SIZE;
147                 skb = (struct sk_buff *)(*(unsigned long *)addr);
148                 skb->dev = adapter->netdev[port];
149                 if (!skb->dev)
150                         return;
151                 ndev = skb->dev;
152                 priv = netdev_priv(ndev);
153 
154                 /* 16 byte IP header align */
155                 skb_reserve(skb, BYTE_OFFSET);
156                 skb_put(skb, length);
157                 skb->protocol = eth_type_trans(skb, skb->dev);
158                 skb->dev->last_rx = jiffies;
159                 netif_rx(skb);
160                 /* Fill rx ring */
161                 skb_data = xlr_alloc_skb();
162                 if (skb_data)
163                         send_to_rfr_fifo(priv, skb_data);
164         }
165 }
166 
167 static struct phy_device *xlr_get_phydev(struct xlr_net_priv *priv)
168 {
169         return mdiobus_get_phy(priv->mii_bus, priv->phy_addr);
170 }
171 
172 /*
173  * Ethtool operation
174  */
175 static int xlr_get_link_ksettings(struct net_device *ndev,
176                                   struct ethtool_link_ksettings *ecmd)
177 {
178         struct xlr_net_priv *priv = netdev_priv(ndev);
179         struct phy_device *phydev = xlr_get_phydev(priv);
180 
181         if (!phydev)
182                 return -ENODEV;
183         return phy_ethtool_ksettings_get(phydev, ecmd);
184 }
185 
186 static int xlr_set_link_ksettings(struct net_device *ndev,
187                                   const struct ethtool_link_ksettings *ecmd)
188 {
189         struct xlr_net_priv *priv = netdev_priv(ndev);
190         struct phy_device *phydev = xlr_get_phydev(priv);
191 
192         if (!phydev)
193                 return -ENODEV;
194         return phy_ethtool_ksettings_set(phydev, ecmd);
195 }
196 
197 static const struct ethtool_ops xlr_ethtool_ops = {
198         .get_link_ksettings = xlr_get_link_ksettings,
199         .set_link_ksettings = xlr_set_link_ksettings,
200 };
201 
202 /*
203  * Net operations
204  */
205 static int xlr_net_fill_rx_ring(struct net_device *ndev)
206 {
207         void *skb_data;
208         struct xlr_net_priv *priv = netdev_priv(ndev);
209         int i;
210 
211         for (i = 0; i < MAX_FRIN_SPILL / 4; i++) {
212                 skb_data = xlr_alloc_skb();
213                 if (!skb_data) {
214                         netdev_err(ndev, "SKB allocation failed\n");
215                         return -ENOMEM;
216                 }
217                 send_to_rfr_fifo(priv, skb_data);
218         }
219         netdev_info(ndev, "Rx ring setup done\n");
220         return 0;
221 }
222 
223 static int xlr_net_open(struct net_device *ndev)
224 {
225         u32 err;
226         struct xlr_net_priv *priv = netdev_priv(ndev);
227         struct phy_device *phydev = xlr_get_phydev(priv);
228 
229         /* schedule a link state check */
230         phy_start(phydev);
231 
232         err = phy_start_aneg(phydev);
233         if (err) {
234                 pr_err("Autoneg failed\n");
235                 return err;
236         }
237         /* Setup the speed from PHY to internal reg*/
238         xlr_set_gmac_speed(priv);
239 
240         netif_tx_start_all_queues(ndev);
241 
242         return 0;
243 }
244 
245 static int xlr_net_stop(struct net_device *ndev)
246 {
247         struct xlr_net_priv *priv = netdev_priv(ndev);
248         struct phy_device *phydev = xlr_get_phydev(priv);
249 
250         phy_stop(phydev);
251         netif_tx_stop_all_queues(ndev);
252         return 0;
253 }
254 
255 static void xlr_make_tx_desc(struct nlm_fmn_msg *msg, unsigned long addr,
256                              struct sk_buff *skb)
257 {
258         unsigned long physkb = virt_to_phys(skb);
259         int cpu_core = nlm_core_id();
260         int fr_stn_id = cpu_core * 8 + XLR_FB_STN;      /* FB to 6th bucket */
261 
262         msg->msg0 = (((u64)1 << 63)     |       /* End of packet descriptor */
263                 ((u64)127 << 54)        |       /* No Free back */
264                 (u64)skb->len << 40     |       /* Length of data */
265                 ((u64)addr));
266         msg->msg1 = (((u64)1 << 63)     |
267                 ((u64)fr_stn_id << 54)  |       /* Free back id */
268                 (u64)0 << 40            |       /* Set len to 0 */
269                 ((u64)physkb  & 0xffffffff));   /* 32bit address */
270         msg->msg2 = 0;
271         msg->msg3 = 0;
272 }
273 
274 static netdev_tx_t xlr_net_start_xmit(struct sk_buff *skb,
275                                       struct net_device *ndev)
276 {
277         struct nlm_fmn_msg msg;
278         struct xlr_net_priv *priv = netdev_priv(ndev);
279         int ret;
280         u32 flags;
281 
282         xlr_make_tx_desc(&msg, virt_to_phys(skb->data), skb);
283         flags = nlm_cop2_enable_irqsave();
284         ret = nlm_fmn_send(2, 0, priv->tx_stnid, &msg);
285         nlm_cop2_disable_irqrestore(flags);
286         if (ret)
287                 dev_kfree_skb_any(skb);
288         return NETDEV_TX_OK;
289 }
290 
291 static u16 xlr_net_select_queue(struct net_device *ndev, struct sk_buff *skb,
292                                 void *accel_priv,
293                                 select_queue_fallback_t fallback)
294 {
295         return (u16)smp_processor_id();
296 }
297 
298 static void xlr_hw_set_mac_addr(struct net_device *ndev)
299 {
300         struct xlr_net_priv *priv = netdev_priv(ndev);
301 
302         /* set mac station address */
303         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0,
304                      ((ndev->dev_addr[5] << 24) | (ndev->dev_addr[4] << 16) |
305                      (ndev->dev_addr[3] << 8) | (ndev->dev_addr[2])));
306         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1,
307                      ((ndev->dev_addr[1] << 24) | (ndev->dev_addr[0] << 16)));
308 
309         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff);
310         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
311         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff);
312         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
313 
314         xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG,
315                      (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
316                      (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
317                      (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID));
318 
319         if (priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII ||
320             priv->nd->phy_interface == PHY_INTERFACE_MODE_SGMII)
321                 xlr_reg_update(priv->base_addr, R_IPG_IFG, MAC_B2B_IPG, 0x7f);
322 }
323 
324 static int xlr_net_set_mac_addr(struct net_device *ndev, void *data)
325 {
326         int err;
327 
328         err = eth_mac_addr(ndev, data);
329         if (err)
330                 return err;
331         xlr_hw_set_mac_addr(ndev);
332         return 0;
333 }
334 
335 static void xlr_set_rx_mode(struct net_device *ndev)
336 {
337         struct xlr_net_priv *priv = netdev_priv(ndev);
338         u32 regval;
339 
340         regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG);
341 
342         if (ndev->flags & IFF_PROMISC) {
343                 regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
344                 (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
345                 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
346                 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
347         } else {
348                 regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
349                 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
350         }
351 
352         xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval);
353 }
354 
355 static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats)
356 {
357         struct xlr_net_priv *priv = netdev_priv(ndev);
358 
359         stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER);
360         stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER);
361         stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER);
362         stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER);
363         stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER);
364         stats->rx_dropped = xlr_nae_rdreg(priv->base_addr,
365                         RX_DROP_PACKET_COUNTER);
366         stats->tx_dropped = xlr_nae_rdreg(priv->base_addr,
367                         TX_DROP_FRAME_COUNTER);
368 
369         stats->multicast = xlr_nae_rdreg(priv->base_addr,
370                         RX_MULTICAST_PACKET_COUNTER);
371         stats->collisions = xlr_nae_rdreg(priv->base_addr,
372                         TX_TOTAL_COLLISION_COUNTER);
373 
374         stats->rx_length_errors = xlr_nae_rdreg(priv->base_addr,
375                         RX_FRAME_LENGTH_ERROR_COUNTER);
376         stats->rx_over_errors = xlr_nae_rdreg(priv->base_addr,
377                         RX_DROP_PACKET_COUNTER);
378         stats->rx_crc_errors = xlr_nae_rdreg(priv->base_addr,
379                         RX_FCS_ERROR_COUNTER);
380         stats->rx_frame_errors = xlr_nae_rdreg(priv->base_addr,
381                         RX_ALIGNMENT_ERROR_COUNTER);
382 
383         stats->rx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
384                         RX_DROP_PACKET_COUNTER);
385         stats->rx_missed_errors = xlr_nae_rdreg(priv->base_addr,
386                         RX_CARRIER_SENSE_ERROR_COUNTER);
387 
388         stats->rx_errors = (stats->rx_over_errors + stats->rx_crc_errors +
389                         stats->rx_frame_errors + stats->rx_fifo_errors +
390                         stats->rx_missed_errors);
391 
392         stats->tx_aborted_errors = xlr_nae_rdreg(priv->base_addr,
393                         TX_EXCESSIVE_COLLISION_PACKET_COUNTER);
394         stats->tx_carrier_errors = xlr_nae_rdreg(priv->base_addr,
395                         TX_DROP_FRAME_COUNTER);
396         stats->tx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
397                         TX_DROP_FRAME_COUNTER);
398 }
399 
400 static struct rtnl_link_stats64 *xlr_get_stats64(struct net_device *ndev,
401                                                  struct rtnl_link_stats64 *stats
402                                                  )
403 {
404         xlr_stats(ndev, stats);
405         return stats;
406 }
407 
408 static const struct net_device_ops xlr_netdev_ops = {
409         .ndo_open = xlr_net_open,
410         .ndo_stop = xlr_net_stop,
411         .ndo_start_xmit = xlr_net_start_xmit,
412         .ndo_select_queue = xlr_net_select_queue,
413         .ndo_set_mac_address = xlr_net_set_mac_addr,
414         .ndo_set_rx_mode = xlr_set_rx_mode,
415         .ndo_get_stats64 = xlr_get_stats64,
416 };
417 
418 /*
419  * Gmac init
420  */
421 static void *xlr_config_spill(struct xlr_net_priv *priv, int reg_start_0,
422                               int reg_start_1, int reg_size, int size)
423 {
424         void *spill;
425         u32 *base;
426         unsigned long phys_addr;
427         u32 spill_size;
428 
429         base = priv->base_addr;
430         spill_size = size;
431         spill = kmalloc(spill_size + SMP_CACHE_BYTES, GFP_ATOMIC);
432         if (!spill) {
433                 pr_err("Unable to allocate memory for spill area!\n");
434                 return ZERO_SIZE_PTR;
435         }
436 
437         spill = PTR_ALIGN(spill, SMP_CACHE_BYTES);
438         phys_addr = virt_to_phys(spill);
439         dev_dbg(&priv->ndev->dev, "Allocated spill %d bytes at %lx\n",
440                 size, phys_addr);
441         xlr_nae_wreg(base, reg_start_0, (phys_addr >> 5) & 0xffffffff);
442         xlr_nae_wreg(base, reg_start_1, ((u64)phys_addr >> 37) & 0x07);
443         xlr_nae_wreg(base, reg_size, spill_size);
444 
445         return spill;
446 }
447 
448 /*
449  * Configure the 6 FIFO's that are used by the network accelarator to
450  * communicate with the rest of the XLx device. 4 of the FIFO's are for
451  * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding
452  * the NA with free descriptors.
453  */
454 static void xlr_config_fifo_spill_area(struct xlr_net_priv *priv)
455 {
456         priv->frin_spill = xlr_config_spill(priv,
457                         R_REG_FRIN_SPILL_MEM_START_0,
458                         R_REG_FRIN_SPILL_MEM_START_1,
459                         R_REG_FRIN_SPILL_MEM_SIZE,
460                         MAX_FRIN_SPILL *
461                         sizeof(u64));
462         priv->frout_spill = xlr_config_spill(priv,
463                         R_FROUT_SPILL_MEM_START_0,
464                         R_FROUT_SPILL_MEM_START_1,
465                         R_FROUT_SPILL_MEM_SIZE,
466                         MAX_FROUT_SPILL *
467                         sizeof(u64));
468         priv->class_0_spill = xlr_config_spill(priv,
469                         R_CLASS0_SPILL_MEM_START_0,
470                         R_CLASS0_SPILL_MEM_START_1,
471                         R_CLASS0_SPILL_MEM_SIZE,
472                         MAX_CLASS_0_SPILL *
473                         sizeof(u64));
474         priv->class_1_spill = xlr_config_spill(priv,
475                         R_CLASS1_SPILL_MEM_START_0,
476                         R_CLASS1_SPILL_MEM_START_1,
477                         R_CLASS1_SPILL_MEM_SIZE,
478                         MAX_CLASS_1_SPILL *
479                         sizeof(u64));
480         priv->class_2_spill = xlr_config_spill(priv,
481                         R_CLASS2_SPILL_MEM_START_0,
482                         R_CLASS2_SPILL_MEM_START_1,
483                         R_CLASS2_SPILL_MEM_SIZE,
484                         MAX_CLASS_2_SPILL *
485                         sizeof(u64));
486         priv->class_3_spill = xlr_config_spill(priv,
487                         R_CLASS3_SPILL_MEM_START_0,
488                         R_CLASS3_SPILL_MEM_START_1,
489                         R_CLASS3_SPILL_MEM_SIZE,
490                         MAX_CLASS_3_SPILL *
491                         sizeof(u64));
492 }
493 
494 /*
495  * Configure PDE to Round-Robin distribution of packets to the
496  * available cpu
497  */
498 static void xlr_config_pde(struct xlr_net_priv *priv)
499 {
500         int i = 0;
501         u64 bkt_map = 0;
502 
503         /* Each core has 8 buckets(station) */
504         for (i = 0; i < hweight32(priv->nd->cpu_mask); i++)
505                 bkt_map |= (0xff << (i * 8));
506 
507         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0, (bkt_map & 0xffffffff));
508         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0 + 1,
509                      ((bkt_map >> 32) & 0xffffffff));
510 
511         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1, (bkt_map & 0xffffffff));
512         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1 + 1,
513                      ((bkt_map >> 32) & 0xffffffff));
514 
515         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2, (bkt_map & 0xffffffff));
516         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2 + 1,
517                      ((bkt_map >> 32) & 0xffffffff));
518 
519         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3, (bkt_map & 0xffffffff));
520         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3 + 1,
521                      ((bkt_map >> 32) & 0xffffffff));
522 }
523 
524 /*
525  * Setup the Message ring credits, bucket size and other
526  * common configuration
527  */
528 static int xlr_config_common(struct xlr_net_priv *priv)
529 {
530         struct xlr_fmn_info *gmac = priv->nd->gmac_fmn_info;
531         int start_stn_id = gmac->start_stn_id;
532         int end_stn_id = gmac->end_stn_id;
533         int *bucket_size = priv->nd->bucket_size;
534         int i, j, err;
535 
536         /* Setting non-core MsgBktSize(0x321 - 0x325) */
537         for (i = start_stn_id; i <= end_stn_id; i++) {
538                 xlr_nae_wreg(priv->base_addr,
539                              R_GMAC_RFR0_BUCKET_SIZE + i - start_stn_id,
540                              bucket_size[i]);
541         }
542 
543         /*
544          * Setting non-core Credit counter register
545          * Distributing Gmac's credit to CPU's
546          */
547         for (i = 0; i < 8; i++) {
548                 for (j = 0; j < 8; j++)
549                         xlr_nae_wreg(priv->base_addr,
550                                      (R_CC_CPU0_0 + (i * 8)) + j,
551                                      gmac->credit_config[(i * 8) + j]);
552         }
553 
554         xlr_nae_wreg(priv->base_addr, R_MSG_TX_THRESHOLD, 3);
555         xlr_nae_wreg(priv->base_addr, R_DMACR0, 0xffffffff);
556         xlr_nae_wreg(priv->base_addr, R_DMACR1, 0xffffffff);
557         xlr_nae_wreg(priv->base_addr, R_DMACR2, 0xffffffff);
558         xlr_nae_wreg(priv->base_addr, R_DMACR3, 0xffffffff);
559         xlr_nae_wreg(priv->base_addr, R_FREEQCARVE, 0);
560 
561         err = xlr_net_fill_rx_ring(priv->ndev);
562         if (err)
563                 return err;
564         nlm_register_fmn_handler(start_stn_id, end_stn_id, xlr_net_fmn_handler,
565                                  priv->adapter);
566         return 0;
567 }
568 
569 static void xlr_config_translate_table(struct xlr_net_priv *priv)
570 {
571         u32 cpu_mask;
572         u32 val;
573         int bkts[32]; /* one bucket is assumed for each cpu */
574         int b1, b2, c1, c2, i, j, k;
575         int use_bkt;
576 
577         use_bkt = 0;
578         cpu_mask = priv->nd->cpu_mask;
579 
580         pr_info("Using %s-based distribution\n",
581                 (use_bkt) ? "bucket" : "class");
582         j = 0;
583         for (i = 0; i < 32; i++) {
584                 if ((1 << i) & cpu_mask) {
585                         /* for each cpu, mark the 4+threadid bucket */
586                         bkts[j] = ((i / 4) * 8) + (i % 4);
587                         j++;
588                 }
589         }
590 
591         /*configure the 128 * 9 Translation table to send to available buckets*/
592         k = 0;
593         c1 = 3;
594         c2 = 0;
595         for (i = 0; i < 64; i++) {
596                 /*
597                  * On use_bkt set the b0, b1 are used, else
598                  * the 4 classes are used, here implemented
599                  * a logic to distribute the packets to the
600                  * buckets equally or based on the class
601                  */
602                 c1 = (c1 + 1) & 3;
603                 c2 = (c1 + 1) & 3;
604                 b1 = bkts[k];
605                 k = (k + 1) % j;
606                 b2 = bkts[k];
607                 k = (k + 1) % j;
608 
609                 val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
610                                 (c2 << 7) | (b2 << 1) | (use_bkt << 0));
611                 dev_dbg(&priv->ndev->dev, "Table[%d] b1=%d b2=%d c1=%d c2=%d\n",
612                         i, b1, b2, c1, c2);
613                 xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val);
614                 c1 = c2;
615         }
616 }
617 
618 static void xlr_config_parser(struct xlr_net_priv *priv)
619 {
620         u32 val;
621 
622         /* Mark it as ETHERNET type */
623         xlr_nae_wreg(priv->base_addr, R_L2TYPE_0, 0x01);
624 
625         /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
626         xlr_nae_wreg(priv->base_addr, R_PARSERCONFIGREG,
627                      ((0x7f << 8) | (1 << 1)));
628 
629         /* configure the parser : L2 Type is configured in the bootloader */
630         /* extract IP: src, dest protocol */
631         xlr_nae_wreg(priv->base_addr, R_L3CTABLE,
632                      (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
633                      (0x0800 << 0));
634         xlr_nae_wreg(priv->base_addr, R_L3CTABLE + 1,
635                      (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) |
636                      (16 << 4) | 4);
637 
638         /* Configure to extract SRC port and Dest port for TCP and UDP pkts */
639         xlr_nae_wreg(priv->base_addr, R_L4CTABLE, 6);
640         xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 2, 17);
641         val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
642         xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val);
643         xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val);
644 
645         xlr_config_translate_table(priv);
646 }
647 
648 static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val)
649 {
650         unsigned long timeout, stoptime, checktime;
651         int timedout;
652 
653         /* 100ms timeout*/
654         timeout = msecs_to_jiffies(100);
655         stoptime = jiffies + timeout;
656         timedout = 0;
657 
658         xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, (phy_addr << 8) | regnum);
659 
660         /* Write the data which starts the write cycle */
661         xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32)val);
662 
663         /* poll for the read cycle to complete */
664         while (!timedout) {
665                 checktime = jiffies;
666                 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
667                         break;
668                 timedout = time_after(checktime, stoptime);
669         }
670         if (timedout) {
671                 pr_info("Phy device write err: device busy");
672                 return -EBUSY;
673         }
674 
675         return 0;
676 }
677 
678 static int xlr_phy_read(u32 *base_addr, int phy_addr, int regnum)
679 {
680         unsigned long timeout, stoptime, checktime;
681         int timedout;
682 
683         /* 100ms timeout*/
684         timeout = msecs_to_jiffies(100);
685         stoptime = jiffies + timeout;
686         timedout = 0;
687 
688         /* setup the phy reg to be used */
689         xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS,
690                      (phy_addr << 8) | (regnum << 0));
691 
692         /* Issue the read command */
693         xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND,
694                      (1 << O_MII_MGMT_COMMAND__rstat));
695 
696         /* poll for the read cycle to complete */
697         while (!timedout) {
698                 checktime = jiffies;
699                 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
700                         break;
701                 timedout = time_after(checktime, stoptime);
702         }
703         if (timedout) {
704                 pr_info("Phy device read err: device busy");
705                 return -EBUSY;
706         }
707 
708         /* clear the read cycle */
709         xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 0);
710 
711         /* Read the data */
712         return xlr_nae_rdreg(base_addr, R_MII_MGMT_STATUS);
713 }
714 
715 static int xlr_mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 val)
716 {
717         struct xlr_net_priv *priv = bus->priv;
718         int ret;
719 
720         ret = xlr_phy_write(priv->mii_addr, phy_addr, regnum, val);
721         dev_dbg(&priv->ndev->dev, "mii_write phy %d : %d <- %x [%x]\n",
722                 phy_addr, regnum, val, ret);
723         return ret;
724 }
725 
726 static int xlr_mii_read(struct mii_bus *bus, int phy_addr, int regnum)
727 {
728         struct xlr_net_priv *priv = bus->priv;
729         int ret;
730 
731         ret =  xlr_phy_read(priv->mii_addr, phy_addr, regnum);
732         dev_dbg(&priv->ndev->dev, "mii_read phy %d : %d [%x]\n",
733                 phy_addr, regnum, ret);
734         return ret;
735 }
736 
737 /*
738  * XLR ports are RGMII. XLS ports are SGMII mostly except the port0,
739  * which can be configured either SGMII or RGMII, considered SGMII
740  * by default, if board setup to RGMII the port_type need to set
741  * accordingly.Serdes and PCS layer need to configured for SGMII
742  */
743 static void xlr_sgmii_init(struct xlr_net_priv *priv)
744 {
745         int phy;
746 
747         xlr_phy_write(priv->serdes_addr, 26, 0, 0x6DB0);
748         xlr_phy_write(priv->serdes_addr, 26, 1, 0xFFFF);
749         xlr_phy_write(priv->serdes_addr, 26, 2, 0xB6D0);
750         xlr_phy_write(priv->serdes_addr, 26, 3, 0x00FF);
751         xlr_phy_write(priv->serdes_addr, 26, 4, 0x0000);
752         xlr_phy_write(priv->serdes_addr, 26, 5, 0x0000);
753         xlr_phy_write(priv->serdes_addr, 26, 6, 0x0005);
754         xlr_phy_write(priv->serdes_addr, 26, 7, 0x0001);
755         xlr_phy_write(priv->serdes_addr, 26, 8, 0x0000);
756         xlr_phy_write(priv->serdes_addr, 26, 9, 0x0000);
757         xlr_phy_write(priv->serdes_addr, 26, 10, 0x0000);
758 
759         /* program  GPIO values for serdes init parameters */
760         xlr_nae_wreg(priv->gpio_addr, 0x20, 0x7e6802);
761         xlr_nae_wreg(priv->gpio_addr, 0x10, 0x7104);
762 
763         xlr_nae_wreg(priv->gpio_addr, 0x22, 0x7e6802);
764         xlr_nae_wreg(priv->gpio_addr, 0x21, 0x7104);
765 
766         /* enable autoneg - more magic */
767         phy = priv->phy_addr % 4 + 27;
768         xlr_phy_write(priv->pcs_addr, phy, 0, 0x1000);
769         xlr_phy_write(priv->pcs_addr, phy, 0, 0x0200);
770 }
771 
772 void xlr_set_gmac_speed(struct xlr_net_priv *priv)
773 {
774         struct phy_device *phydev = xlr_get_phydev(priv);
775         int speed;
776 
777         if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
778                 xlr_sgmii_init(priv);
779 
780         if (phydev->speed != priv->phy_speed) {
781                 speed = phydev->speed;
782                 if (speed == SPEED_1000) {
783                         /* Set interface to Byte mode */
784                         xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
785                         priv->phy_speed = speed;
786                 } else if (speed == SPEED_100 || speed == SPEED_10) {
787                         /* Set interface to Nibble mode */
788                         xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7117);
789                         priv->phy_speed = speed;
790                 }
791                 /* Set SGMII speed in Interface control reg */
792                 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
793                         if (speed == SPEED_10)
794                                 xlr_nae_wreg(priv->base_addr,
795                                              R_INTERFACE_CONTROL,
796                                              SGMII_SPEED_10);
797                         if (speed == SPEED_100)
798                                 xlr_nae_wreg(priv->base_addr,
799                                              R_INTERFACE_CONTROL,
800                                              SGMII_SPEED_100);
801                         if (speed == SPEED_1000)
802                                 xlr_nae_wreg(priv->base_addr,
803                                              R_INTERFACE_CONTROL,
804                                              SGMII_SPEED_1000);
805                 }
806                 if (speed == SPEED_10)
807                         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x2);
808                 if (speed == SPEED_100)
809                         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x1);
810                 if (speed == SPEED_1000)
811                         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x0);
812         }
813         pr_info("gmac%d : %dMbps\n", priv->port_id, priv->phy_speed);
814 }
815 
816 static void xlr_gmac_link_adjust(struct net_device *ndev)
817 {
818         struct xlr_net_priv *priv = netdev_priv(ndev);
819         struct phy_device *phydev = xlr_get_phydev(priv);
820         u32 intreg;
821 
822         intreg = xlr_nae_rdreg(priv->base_addr, R_INTREG);
823         if (phydev->link) {
824                 if (phydev->speed != priv->phy_speed) {
825                         xlr_set_gmac_speed(priv);
826                         pr_info("gmac%d : Link up\n", priv->port_id);
827                 }
828         } else {
829                 xlr_set_gmac_speed(priv);
830                 pr_info("gmac%d : Link down\n", priv->port_id);
831         }
832 }
833 
834 static int xlr_mii_probe(struct xlr_net_priv *priv)
835 {
836         struct phy_device *phydev = xlr_get_phydev(priv);
837 
838         if (!phydev) {
839                 pr_err("no PHY found on phy_addr %d\n", priv->phy_addr);
840                 return -ENODEV;
841         }
842 
843         /* Attach MAC to PHY */
844         phydev = phy_connect(priv->ndev, phydev_name(phydev),
845                              xlr_gmac_link_adjust, priv->nd->phy_interface);
846 
847         if (IS_ERR(phydev)) {
848                 pr_err("could not attach PHY\n");
849                 return PTR_ERR(phydev);
850         }
851         phydev->supported &= (ADVERTISED_10baseT_Full
852                                 | ADVERTISED_10baseT_Half
853                                 | ADVERTISED_100baseT_Full
854                                 | ADVERTISED_100baseT_Half
855                                 | ADVERTISED_1000baseT_Full
856                                 | ADVERTISED_Autoneg
857                                 | ADVERTISED_MII);
858 
859         phydev->advertising = phydev->supported;
860         phy_attached_info(phydev);
861         return 0;
862 }
863 
864 static int xlr_setup_mdio(struct xlr_net_priv *priv,
865                           struct platform_device *pdev)
866 {
867         int err;
868 
869         priv->mii_bus = mdiobus_alloc();
870         if (!priv->mii_bus) {
871                 pr_err("mdiobus alloc failed\n");
872                 return -ENOMEM;
873         }
874 
875         priv->mii_bus->priv = priv;
876         priv->mii_bus->name = "xlr-mdio";
877         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
878                  priv->mii_bus->name, priv->port_id);
879         priv->mii_bus->read = xlr_mii_read;
880         priv->mii_bus->write = xlr_mii_write;
881         priv->mii_bus->parent = &pdev->dev;
882 
883         /* Scan only the enabled address */
884         priv->mii_bus->phy_mask = ~(1 << priv->phy_addr);
885 
886         /* setting clock divisor to 54 */
887         xlr_nae_wreg(priv->base_addr, R_MII_MGMT_CONFIG, 0x7);
888 
889         err = mdiobus_register(priv->mii_bus);
890         if (err) {
891                 mdiobus_free(priv->mii_bus);
892                 pr_err("mdio bus registration failed\n");
893                 return err;
894         }
895 
896         pr_info("Registered mdio bus id : %s\n", priv->mii_bus->id);
897         err = xlr_mii_probe(priv);
898         if (err) {
899                 mdiobus_free(priv->mii_bus);
900                 return err;
901         }
902         return 0;
903 }
904 
905 static void xlr_port_enable(struct xlr_net_priv *priv)
906 {
907         u32 prid = (read_c0_prid() & 0xf000);
908 
909         /* Setup MAC_CONFIG reg if (xls & rgmii) */
910         if ((prid == 0x8000 || prid == 0x4000 || prid == 0xc000) &&
911             priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII)
912                 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
913                                (1 << O_RX_CONTROL__RGMII),
914                                (1 << O_RX_CONTROL__RGMII));
915 
916         /* Rx Tx enable */
917         xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
918                        ((1 << O_MAC_CONFIG_1__rxen) |
919                         (1 << O_MAC_CONFIG_1__txen) |
920                         (1 << O_MAC_CONFIG_1__rxfc) |
921                         (1 << O_MAC_CONFIG_1__txfc)),
922                        ((1 << O_MAC_CONFIG_1__rxen) |
923                         (1 << O_MAC_CONFIG_1__txen) |
924                         (1 << O_MAC_CONFIG_1__rxfc) |
925                         (1 << O_MAC_CONFIG_1__txfc)));
926 
927         /* Setup tx control reg */
928         xlr_reg_update(priv->base_addr, R_TX_CONTROL,
929                        ((1 << O_TX_CONTROL__TXENABLE) |
930                        (512 << O_TX_CONTROL__TXTHRESHOLD)), 0x3fff);
931 
932         /* Setup rx control reg */
933         xlr_reg_update(priv->base_addr, R_RX_CONTROL,
934                        1 << O_RX_CONTROL__RXENABLE,
935                        1 << O_RX_CONTROL__RXENABLE);
936 }
937 
938 static void xlr_port_disable(struct xlr_net_priv *priv)
939 {
940         /* Setup MAC_CONFIG reg */
941         /* Rx Tx disable*/
942         xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
943                        ((1 << O_MAC_CONFIG_1__rxen) |
944                         (1 << O_MAC_CONFIG_1__txen) |
945                         (1 << O_MAC_CONFIG_1__rxfc) |
946                         (1 << O_MAC_CONFIG_1__txfc)), 0x0);
947 
948         /* Setup tx control reg */
949         xlr_reg_update(priv->base_addr, R_TX_CONTROL,
950                        ((1 << O_TX_CONTROL__TXENABLE) |
951                        (512 << O_TX_CONTROL__TXTHRESHOLD)), 0);
952 
953         /* Setup rx control reg */
954         xlr_reg_update(priv->base_addr, R_RX_CONTROL,
955                        1 << O_RX_CONTROL__RXENABLE, 0);
956 }
957 
958 /*
959  * Initialization of gmac
960  */
961 static int xlr_gmac_init(struct xlr_net_priv *priv,
962                          struct platform_device *pdev)
963 {
964         int ret;
965 
966         pr_info("Initializing the gmac%d\n", priv->port_id);
967 
968         xlr_port_disable(priv);
969 
970         xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL,
971                      (1 << O_DESC_PACK_CTRL__MAXENTRY) |
972                      (BYTE_OFFSET << O_DESC_PACK_CTRL__BYTEOFFSET) |
973                      (1600 << O_DESC_PACK_CTRL__REGULARSIZE));
974 
975         ret = xlr_setup_mdio(priv, pdev);
976         if (ret)
977                 return ret;
978         xlr_port_enable(priv);
979 
980         /* Enable Full-duplex/1000Mbps/CRC */
981         xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
982         /* speed 2.5Mhz */
983         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02);
984         /* Setup Interrupt mask reg */
985         xlr_nae_wreg(priv->base_addr, R_INTMASK, (1 << O_INTMASK__TXILLEGAL) |
986                      (1 << O_INTMASK__MDINT) | (1 << O_INTMASK__TXFETCHERROR) |
987                      (1 << O_INTMASK__P2PSPILLECC) | (1 << O_INTMASK__TAGFULL) |
988                      (1 << O_INTMASK__UNDERRUN) | (1 << O_INTMASK__ABORT));
989 
990         /* Clear all stats */
991         xlr_reg_update(priv->base_addr, R_STATCTRL, 0, 1 << O_STATCTRL__CLRCNT);
992         xlr_reg_update(priv->base_addr, R_STATCTRL, 1 << 2, 1 << 2);
993         return 0;
994 }
995 
996 static int xlr_net_probe(struct platform_device *pdev)
997 {
998         struct xlr_net_priv *priv = NULL;
999         struct net_device *ndev;
1000         struct resource *res;
1001         struct xlr_adapter *adapter;
1002         int err, port;
1003 
1004         pr_info("XLR/XLS Ethernet Driver controller %d\n", pdev->id);
1005         /*
1006          * Allocate our adapter data structure and attach it to the device.
1007          */
1008         adapter = (struct xlr_adapter *)
1009                 devm_kzalloc(&pdev->dev, sizeof(*adapter), GFP_KERNEL);
1010         if (!adapter)
1011                 return -ENOMEM;
1012 
1013         /*
1014          * XLR and XLS have 1 and 2 NAE controller respectively
1015          * Each controller has 4 gmac ports, mapping each controller
1016          * under one parent device, 4 gmac ports under one device.
1017          */
1018         for (port = 0; port < pdev->num_resources / 2; port++) {
1019                 ndev = alloc_etherdev_mq(sizeof(struct xlr_net_priv), 32);
1020                 if (!ndev) {
1021                         dev_err(&pdev->dev,
1022                                 "Allocation of Ethernet device failed\n");
1023                         return -ENOMEM;
1024                 }
1025 
1026                 priv = netdev_priv(ndev);
1027                 priv->pdev = pdev;
1028                 priv->ndev = ndev;
1029                 priv->port_id = (pdev->id * 4) + port;
1030                 priv->nd = (struct xlr_net_data *)pdev->dev.platform_data;
1031                 res = platform_get_resource(pdev, IORESOURCE_MEM, port);
1032                 priv->base_addr = devm_ioremap_resource(&pdev->dev, res);
1033                 if (IS_ERR(priv->base_addr)) {
1034                         err = PTR_ERR(priv->base_addr);
1035                         goto err_gmac;
1036                 }
1037                 priv->adapter = adapter;
1038                 adapter->netdev[port] = ndev;
1039 
1040                 res = platform_get_resource(pdev, IORESOURCE_IRQ, port);
1041                 if (!res) {
1042                         dev_err(&pdev->dev, "No irq resource for MAC %d\n",
1043                                 priv->port_id);
1044                         err = -ENODEV;
1045                         goto err_gmac;
1046                 }
1047 
1048                 ndev->irq = res->start;
1049 
1050                 priv->phy_addr = priv->nd->phy_addr[port];
1051                 priv->tx_stnid = priv->nd->tx_stnid[port];
1052                 priv->mii_addr = priv->nd->mii_addr;
1053                 priv->serdes_addr = priv->nd->serdes_addr;
1054                 priv->pcs_addr = priv->nd->pcs_addr;
1055                 priv->gpio_addr = priv->nd->gpio_addr;
1056 
1057                 ndev->netdev_ops = &xlr_netdev_ops;
1058                 ndev->watchdog_timeo = HZ;
1059 
1060                 /* Setup Mac address and Rx mode */
1061                 eth_hw_addr_random(ndev);
1062                 xlr_hw_set_mac_addr(ndev);
1063                 xlr_set_rx_mode(ndev);
1064 
1065                 priv->num_rx_desc += MAX_NUM_DESC_SPILL;
1066                 ndev->ethtool_ops = &xlr_ethtool_ops;
1067                 SET_NETDEV_DEV(ndev, &pdev->dev);
1068 
1069                 xlr_config_fifo_spill_area(priv);
1070                 /* Configure PDE to Round-Robin pkt distribution */
1071                 xlr_config_pde(priv);
1072                 xlr_config_parser(priv);
1073 
1074                 /* Call init with respect to port */
1075                 if (strcmp(res->name, "gmac") == 0) {
1076                         err = xlr_gmac_init(priv, pdev);
1077                         if (err) {
1078                                 dev_err(&pdev->dev, "gmac%d init failed\n",
1079                                         priv->port_id);
1080                                 goto err_gmac;
1081                         }
1082                 }
1083 
1084                 if (priv->port_id == 0 || priv->port_id == 4) {
1085                         err = xlr_config_common(priv);
1086                         if (err)
1087                                 goto err_netdev;
1088                 }
1089 
1090                 err = register_netdev(ndev);
1091                 if (err) {
1092                         dev_err(&pdev->dev,
1093                                 "Registering netdev failed for gmac%d\n",
1094                                 priv->port_id);
1095                         goto err_netdev;
1096                 }
1097                 platform_set_drvdata(pdev, priv);
1098         }
1099 
1100         return 0;
1101 
1102 err_netdev:
1103         mdiobus_free(priv->mii_bus);
1104 err_gmac:
1105         free_netdev(ndev);
1106         return err;
1107 }
1108 
1109 static int xlr_net_remove(struct platform_device *pdev)
1110 {
1111         struct xlr_net_priv *priv = platform_get_drvdata(pdev);
1112 
1113         unregister_netdev(priv->ndev);
1114         mdiobus_unregister(priv->mii_bus);
1115         mdiobus_free(priv->mii_bus);
1116         free_netdev(priv->ndev);
1117         return 0;
1118 }
1119 
1120 static struct platform_driver xlr_net_driver = {
1121         .probe          = xlr_net_probe,
1122         .remove         = xlr_net_remove,
1123         .driver         = {
1124                 .name   = "xlr-net",
1125         },
1126 };
1127 
1128 module_platform_driver(xlr_net_driver);
1129 
1130 MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
1131 MODULE_DESCRIPTION("Ethernet driver for Netlogic XLR/XLS");
1132 MODULE_LICENSE("Dual BSD/GPL");
1133 MODULE_ALIAS("platform:xlr-net");
1134 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us