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Linux/drivers/staging/netlogic/xlr_net.c

  1 /*
  2  * Copyright (c) 2003-2012 Broadcom Corporation
  3  * All Rights Reserved
  4  *
  5  * This software is available to you under a choice of one of two
  6  * licenses.  You may choose to be licensed under the terms of the GNU
  7  * General Public License (GPL) Version 2, available from the file
  8  * COPYING in the main directory of this source tree, or the Broadcom
  9  * license below:
 10  *
 11  * Redistribution and use in source and binary forms, with or without
 12  * modification, are permitted provided that the following conditions
 13  * are met:
 14  *
 15  * 1. Redistributions of source code must retain the above copyright
 16  *    notice, this list of conditions and the following disclaimer.
 17  * 2. Redistributions in binary form must reproduce the above copyright
 18  *    notice, this list of conditions and the following disclaimer in
 19  *    the documentation and/or other materials provided with the
 20  *    distribution.
 21  *
 22  * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
 23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 25  * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
 26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 33  */
 34 #include <linux/phy.h>
 35 #include <linux/delay.h>
 36 #include <linux/netdevice.h>
 37 #include <linux/smp.h>
 38 #include <linux/ethtool.h>
 39 #include <linux/module.h>
 40 #include <linux/etherdevice.h>
 41 #include <linux/skbuff.h>
 42 #include <linux/jiffies.h>
 43 #include <linux/interrupt.h>
 44 #include <linux/platform_device.h>
 45 
 46 #include <asm/mipsregs.h>
 47 /*
 48  * fmn.h - For FMN credit configuration and registering fmn_handler.
 49  * FMN is communication mechanism that allows processing agents within
 50  * XLR/XLS to communicate each other.
 51  */
 52 #include <asm/netlogic/xlr/fmn.h>
 53 
 54 #include "platform_net.h"
 55 #include "xlr_net.h"
 56 
 57 /*
 58  * The readl/writel implementation byteswaps on XLR/XLS, so
 59  * we need to use __raw_ IO to read the NAE registers
 60  * because they are in the big-endian MMIO area on the SoC.
 61  */
 62 static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val)
 63 {
 64         __raw_writel(val, base + reg);
 65 }
 66 
 67 static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg)
 68 {
 69         return __raw_readl(base + reg);
 70 }
 71 
 72 static inline void xlr_reg_update(u32 *base_addr, u32 off, u32 val, u32 mask)
 73 {
 74         u32 tmp;
 75 
 76         tmp = xlr_nae_rdreg(base_addr, off);
 77         xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask));
 78 }
 79 
 80 #define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES
 81 
 82 static int send_to_rfr_fifo(struct xlr_net_priv *priv, void *addr)
 83 {
 84         struct nlm_fmn_msg msg;
 85         int ret = 0, num_try = 0, stnid;
 86         unsigned long paddr, mflags;
 87 
 88         paddr = virt_to_bus(addr);
 89         msg.msg0 = (u64)paddr & 0xffffffffe0ULL;
 90         msg.msg1 = 0;
 91         msg.msg2 = 0;
 92         msg.msg3 = 0;
 93         stnid = priv->nd->rfr_station;
 94         do {
 95                 mflags = nlm_cop2_enable_irqsave();
 96                 ret = nlm_fmn_send(1, 0, stnid, &msg);
 97                 nlm_cop2_disable_irqrestore(mflags);
 98                 if (ret == 0)
 99                         return 0;
100         } while (++num_try < 10000);
101 
102         netdev_err(priv->ndev, "Send to RFR failed in RX path\n");
103         return ret;
104 }
105 
106 static inline unsigned char *xlr_alloc_skb(void)
107 {
108         struct sk_buff *skb;
109         int buf_len = sizeof(struct sk_buff *);
110         unsigned char *skb_data;
111 
112         /* skb->data is cache aligned */
113         skb = alloc_skb(XLR_RX_BUF_SIZE, GFP_ATOMIC);
114         if (!skb)
115                 return NULL;
116         skb_data = skb->data;
117         skb_put(skb, MAC_SKB_BACK_PTR_SIZE);
118         skb_pull(skb, MAC_SKB_BACK_PTR_SIZE);
119         memcpy(skb_data, &skb, buf_len);
120 
121         return skb->data;
122 }
123 
124 static void xlr_net_fmn_handler(int bkt, int src_stnid, int size, int code,
125                                 struct nlm_fmn_msg *msg, void *arg)
126 {
127         struct sk_buff *skb;
128         void *skb_data = NULL;
129         struct net_device *ndev;
130         struct xlr_net_priv *priv;
131         u32 port, length;
132         unsigned char *addr;
133         struct xlr_adapter *adapter = arg;
134 
135         length = (msg->msg0 >> 40) & 0x3fff;
136         if (length == 0) {
137                 addr = bus_to_virt(msg->msg0 & 0xffffffffffULL);
138                 addr = addr - MAC_SKB_BACK_PTR_SIZE;
139                 skb = (struct sk_buff *)(*(unsigned long *)addr);
140                 dev_kfree_skb_any((struct sk_buff *)addr);
141         } else {
142                 addr = (unsigned char *)
143                         bus_to_virt(msg->msg0 & 0xffffffffe0ULL);
144                 length = length - BYTE_OFFSET - MAC_CRC_LEN;
145                 port = ((int)msg->msg0) & 0x0f;
146                 addr = addr - MAC_SKB_BACK_PTR_SIZE;
147                 skb = (struct sk_buff *)(*(unsigned long *)addr);
148                 skb->dev = adapter->netdev[port];
149                 if (!skb->dev)
150                         return;
151                 ndev = skb->dev;
152                 priv = netdev_priv(ndev);
153 
154                 /* 16 byte IP header align */
155                 skb_reserve(skb, BYTE_OFFSET);
156                 skb_put(skb, length);
157                 skb->protocol = eth_type_trans(skb, skb->dev);
158                 skb->dev->last_rx = jiffies;
159                 netif_rx(skb);
160                 /* Fill rx ring */
161                 skb_data = xlr_alloc_skb();
162                 if (skb_data)
163                         send_to_rfr_fifo(priv, skb_data);
164         }
165 }
166 
167 static struct phy_device *xlr_get_phydev(struct xlr_net_priv *priv)
168 {
169         return mdiobus_get_phy(priv->mii_bus, priv->phy_addr);
170 }
171 
172 /*
173  * Ethtool operation
174  */
175 static int xlr_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
176 {
177         struct xlr_net_priv *priv = netdev_priv(ndev);
178         struct phy_device *phydev = xlr_get_phydev(priv);
179 
180         if (!phydev)
181                 return -ENODEV;
182         return phy_ethtool_gset(phydev, ecmd);
183 }
184 
185 static int xlr_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
186 {
187         struct xlr_net_priv *priv = netdev_priv(ndev);
188         struct phy_device *phydev = xlr_get_phydev(priv);
189 
190         if (!phydev)
191                 return -ENODEV;
192         return phy_ethtool_sset(phydev, ecmd);
193 }
194 
195 static const struct ethtool_ops xlr_ethtool_ops = {
196         .get_settings = xlr_get_settings,
197         .set_settings = xlr_set_settings,
198 };
199 
200 /*
201  * Net operations
202  */
203 static int xlr_net_fill_rx_ring(struct net_device *ndev)
204 {
205         void *skb_data;
206         struct xlr_net_priv *priv = netdev_priv(ndev);
207         int i;
208 
209         for (i = 0; i < MAX_FRIN_SPILL / 4; i++) {
210                 skb_data = xlr_alloc_skb();
211                 if (!skb_data) {
212                         netdev_err(ndev, "SKB allocation failed\n");
213                         return -ENOMEM;
214                 }
215                 send_to_rfr_fifo(priv, skb_data);
216         }
217         netdev_info(ndev, "Rx ring setup done\n");
218         return 0;
219 }
220 
221 static int xlr_net_open(struct net_device *ndev)
222 {
223         u32 err;
224         struct xlr_net_priv *priv = netdev_priv(ndev);
225         struct phy_device *phydev = xlr_get_phydev(priv);
226 
227         /* schedule a link state check */
228         phy_start(phydev);
229 
230         err = phy_start_aneg(phydev);
231         if (err) {
232                 pr_err("Autoneg failed\n");
233                 return err;
234         }
235         /* Setup the speed from PHY to internal reg*/
236         xlr_set_gmac_speed(priv);
237 
238         netif_tx_start_all_queues(ndev);
239 
240         return 0;
241 }
242 
243 static int xlr_net_stop(struct net_device *ndev)
244 {
245         struct xlr_net_priv *priv = netdev_priv(ndev);
246         struct phy_device *phydev = xlr_get_phydev(priv);
247 
248         phy_stop(phydev);
249         netif_tx_stop_all_queues(ndev);
250         return 0;
251 }
252 
253 static void xlr_make_tx_desc(struct nlm_fmn_msg *msg, unsigned long addr,
254                              struct sk_buff *skb)
255 {
256         unsigned long physkb = virt_to_phys(skb);
257         int cpu_core = nlm_core_id();
258         int fr_stn_id = cpu_core * 8 + XLR_FB_STN;      /* FB to 6th bucket */
259 
260         msg->msg0 = (((u64)1 << 63)     |       /* End of packet descriptor */
261                 ((u64)127 << 54)        |       /* No Free back */
262                 (u64)skb->len << 40     |       /* Length of data */
263                 ((u64)addr));
264         msg->msg1 = (((u64)1 << 63)     |
265                 ((u64)fr_stn_id << 54)  |       /* Free back id */
266                 (u64)0 << 40            |       /* Set len to 0 */
267                 ((u64)physkb  & 0xffffffff));   /* 32bit address */
268         msg->msg2 = 0;
269         msg->msg3 = 0;
270 }
271 
272 static netdev_tx_t xlr_net_start_xmit(struct sk_buff *skb,
273                                       struct net_device *ndev)
274 {
275         struct nlm_fmn_msg msg;
276         struct xlr_net_priv *priv = netdev_priv(ndev);
277         int ret;
278         u32 flags;
279 
280         xlr_make_tx_desc(&msg, virt_to_phys(skb->data), skb);
281         flags = nlm_cop2_enable_irqsave();
282         ret = nlm_fmn_send(2, 0, priv->tx_stnid, &msg);
283         nlm_cop2_disable_irqrestore(flags);
284         if (ret)
285                 dev_kfree_skb_any(skb);
286         return NETDEV_TX_OK;
287 }
288 
289 static u16 xlr_net_select_queue(struct net_device *ndev, struct sk_buff *skb,
290                                 void *accel_priv,
291                                 select_queue_fallback_t fallback)
292 {
293         return (u16)smp_processor_id();
294 }
295 
296 static void xlr_hw_set_mac_addr(struct net_device *ndev)
297 {
298         struct xlr_net_priv *priv = netdev_priv(ndev);
299 
300         /* set mac station address */
301         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0,
302                      ((ndev->dev_addr[5] << 24) | (ndev->dev_addr[4] << 16) |
303                      (ndev->dev_addr[3] << 8) | (ndev->dev_addr[2])));
304         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1,
305                      ((ndev->dev_addr[1] << 24) | (ndev->dev_addr[0] << 16)));
306 
307         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff);
308         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
309         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff);
310         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
311 
312         xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG,
313                      (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
314                      (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
315                      (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID));
316 
317         if (priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII ||
318             priv->nd->phy_interface == PHY_INTERFACE_MODE_SGMII)
319                 xlr_reg_update(priv->base_addr, R_IPG_IFG, MAC_B2B_IPG, 0x7f);
320 }
321 
322 static int xlr_net_set_mac_addr(struct net_device *ndev, void *data)
323 {
324         int err;
325 
326         err = eth_mac_addr(ndev, data);
327         if (err)
328                 return err;
329         xlr_hw_set_mac_addr(ndev);
330         return 0;
331 }
332 
333 static void xlr_set_rx_mode(struct net_device *ndev)
334 {
335         struct xlr_net_priv *priv = netdev_priv(ndev);
336         u32 regval;
337 
338         regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG);
339 
340         if (ndev->flags & IFF_PROMISC) {
341                 regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
342                 (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
343                 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
344                 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
345         } else {
346                 regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
347                 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
348         }
349 
350         xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval);
351 }
352 
353 static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats)
354 {
355         struct xlr_net_priv *priv = netdev_priv(ndev);
356 
357         stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER);
358         stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER);
359         stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER);
360         stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER);
361         stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER);
362         stats->rx_dropped = xlr_nae_rdreg(priv->base_addr,
363                         RX_DROP_PACKET_COUNTER);
364         stats->tx_dropped = xlr_nae_rdreg(priv->base_addr,
365                         TX_DROP_FRAME_COUNTER);
366 
367         stats->multicast = xlr_nae_rdreg(priv->base_addr,
368                         RX_MULTICAST_PACKET_COUNTER);
369         stats->collisions = xlr_nae_rdreg(priv->base_addr,
370                         TX_TOTAL_COLLISION_COUNTER);
371 
372         stats->rx_length_errors = xlr_nae_rdreg(priv->base_addr,
373                         RX_FRAME_LENGTH_ERROR_COUNTER);
374         stats->rx_over_errors = xlr_nae_rdreg(priv->base_addr,
375                         RX_DROP_PACKET_COUNTER);
376         stats->rx_crc_errors = xlr_nae_rdreg(priv->base_addr,
377                         RX_FCS_ERROR_COUNTER);
378         stats->rx_frame_errors = xlr_nae_rdreg(priv->base_addr,
379                         RX_ALIGNMENT_ERROR_COUNTER);
380 
381         stats->rx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
382                         RX_DROP_PACKET_COUNTER);
383         stats->rx_missed_errors = xlr_nae_rdreg(priv->base_addr,
384                         RX_CARRIER_SENSE_ERROR_COUNTER);
385 
386         stats->rx_errors = (stats->rx_over_errors + stats->rx_crc_errors +
387                         stats->rx_frame_errors + stats->rx_fifo_errors +
388                         stats->rx_missed_errors);
389 
390         stats->tx_aborted_errors = xlr_nae_rdreg(priv->base_addr,
391                         TX_EXCESSIVE_COLLISION_PACKET_COUNTER);
392         stats->tx_carrier_errors = xlr_nae_rdreg(priv->base_addr,
393                         TX_DROP_FRAME_COUNTER);
394         stats->tx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
395                         TX_DROP_FRAME_COUNTER);
396 }
397 
398 static struct rtnl_link_stats64 *xlr_get_stats64(struct net_device *ndev,
399                                                  struct rtnl_link_stats64 *stats
400                                                  )
401 {
402         xlr_stats(ndev, stats);
403         return stats;
404 }
405 
406 static const struct net_device_ops xlr_netdev_ops = {
407         .ndo_open = xlr_net_open,
408         .ndo_stop = xlr_net_stop,
409         .ndo_start_xmit = xlr_net_start_xmit,
410         .ndo_select_queue = xlr_net_select_queue,
411         .ndo_set_mac_address = xlr_net_set_mac_addr,
412         .ndo_set_rx_mode = xlr_set_rx_mode,
413         .ndo_get_stats64 = xlr_get_stats64,
414 };
415 
416 /*
417  * Gmac init
418  */
419 static void *xlr_config_spill(struct xlr_net_priv *priv, int reg_start_0,
420                               int reg_start_1, int reg_size, int size)
421 {
422         void *spill;
423         u32 *base;
424         unsigned long phys_addr;
425         u32 spill_size;
426 
427         base = priv->base_addr;
428         spill_size = size;
429         spill = kmalloc(spill_size + SMP_CACHE_BYTES, GFP_ATOMIC);
430         if (!spill) {
431                 pr_err("Unable to allocate memory for spill area!\n");
432                 return ZERO_SIZE_PTR;
433         }
434 
435         spill = PTR_ALIGN(spill, SMP_CACHE_BYTES);
436         phys_addr = virt_to_phys(spill);
437         dev_dbg(&priv->ndev->dev, "Allocated spill %d bytes at %lx\n",
438                 size, phys_addr);
439         xlr_nae_wreg(base, reg_start_0, (phys_addr >> 5) & 0xffffffff);
440         xlr_nae_wreg(base, reg_start_1, ((u64)phys_addr >> 37) & 0x07);
441         xlr_nae_wreg(base, reg_size, spill_size);
442 
443         return spill;
444 }
445 
446 /*
447  * Configure the 6 FIFO's that are used by the network accelarator to
448  * communicate with the rest of the XLx device. 4 of the FIFO's are for
449  * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding
450  * the NA with free descriptors.
451  */
452 static void xlr_config_fifo_spill_area(struct xlr_net_priv *priv)
453 {
454         priv->frin_spill = xlr_config_spill(priv,
455                         R_REG_FRIN_SPILL_MEM_START_0,
456                         R_REG_FRIN_SPILL_MEM_START_1,
457                         R_REG_FRIN_SPILL_MEM_SIZE,
458                         MAX_FRIN_SPILL *
459                         sizeof(u64));
460         priv->frout_spill = xlr_config_spill(priv,
461                         R_FROUT_SPILL_MEM_START_0,
462                         R_FROUT_SPILL_MEM_START_1,
463                         R_FROUT_SPILL_MEM_SIZE,
464                         MAX_FROUT_SPILL *
465                         sizeof(u64));
466         priv->class_0_spill = xlr_config_spill(priv,
467                         R_CLASS0_SPILL_MEM_START_0,
468                         R_CLASS0_SPILL_MEM_START_1,
469                         R_CLASS0_SPILL_MEM_SIZE,
470                         MAX_CLASS_0_SPILL *
471                         sizeof(u64));
472         priv->class_1_spill = xlr_config_spill(priv,
473                         R_CLASS1_SPILL_MEM_START_0,
474                         R_CLASS1_SPILL_MEM_START_1,
475                         R_CLASS1_SPILL_MEM_SIZE,
476                         MAX_CLASS_1_SPILL *
477                         sizeof(u64));
478         priv->class_2_spill = xlr_config_spill(priv,
479                         R_CLASS2_SPILL_MEM_START_0,
480                         R_CLASS2_SPILL_MEM_START_1,
481                         R_CLASS2_SPILL_MEM_SIZE,
482                         MAX_CLASS_2_SPILL *
483                         sizeof(u64));
484         priv->class_3_spill = xlr_config_spill(priv,
485                         R_CLASS3_SPILL_MEM_START_0,
486                         R_CLASS3_SPILL_MEM_START_1,
487                         R_CLASS3_SPILL_MEM_SIZE,
488                         MAX_CLASS_3_SPILL *
489                         sizeof(u64));
490 }
491 
492 /*
493  * Configure PDE to Round-Robin distribution of packets to the
494  * available cpu
495  */
496 static void xlr_config_pde(struct xlr_net_priv *priv)
497 {
498         int i = 0;
499         u64 bkt_map = 0;
500 
501         /* Each core has 8 buckets(station) */
502         for (i = 0; i < hweight32(priv->nd->cpu_mask); i++)
503                 bkt_map |= (0xff << (i * 8));
504 
505         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0, (bkt_map & 0xffffffff));
506         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0 + 1,
507                      ((bkt_map >> 32) & 0xffffffff));
508 
509         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1, (bkt_map & 0xffffffff));
510         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1 + 1,
511                      ((bkt_map >> 32) & 0xffffffff));
512 
513         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2, (bkt_map & 0xffffffff));
514         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2 + 1,
515                      ((bkt_map >> 32) & 0xffffffff));
516 
517         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3, (bkt_map & 0xffffffff));
518         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3 + 1,
519                      ((bkt_map >> 32) & 0xffffffff));
520 }
521 
522 /*
523  * Setup the Message ring credits, bucket size and other
524  * common configuration
525  */
526 static int xlr_config_common(struct xlr_net_priv *priv)
527 {
528         struct xlr_fmn_info *gmac = priv->nd->gmac_fmn_info;
529         int start_stn_id = gmac->start_stn_id;
530         int end_stn_id = gmac->end_stn_id;
531         int *bucket_size = priv->nd->bucket_size;
532         int i, j, err;
533 
534         /* Setting non-core MsgBktSize(0x321 - 0x325) */
535         for (i = start_stn_id; i <= end_stn_id; i++) {
536                 xlr_nae_wreg(priv->base_addr,
537                              R_GMAC_RFR0_BUCKET_SIZE + i - start_stn_id,
538                              bucket_size[i]);
539         }
540 
541         /*
542          * Setting non-core Credit counter register
543          * Distributing Gmac's credit to CPU's
544          */
545         for (i = 0; i < 8; i++) {
546                 for (j = 0; j < 8; j++)
547                         xlr_nae_wreg(priv->base_addr,
548                                      (R_CC_CPU0_0 + (i * 8)) + j,
549                                      gmac->credit_config[(i * 8) + j]);
550         }
551 
552         xlr_nae_wreg(priv->base_addr, R_MSG_TX_THRESHOLD, 3);
553         xlr_nae_wreg(priv->base_addr, R_DMACR0, 0xffffffff);
554         xlr_nae_wreg(priv->base_addr, R_DMACR1, 0xffffffff);
555         xlr_nae_wreg(priv->base_addr, R_DMACR2, 0xffffffff);
556         xlr_nae_wreg(priv->base_addr, R_DMACR3, 0xffffffff);
557         xlr_nae_wreg(priv->base_addr, R_FREEQCARVE, 0);
558 
559         err = xlr_net_fill_rx_ring(priv->ndev);
560         if (err)
561                 return err;
562         nlm_register_fmn_handler(start_stn_id, end_stn_id, xlr_net_fmn_handler,
563                                  priv->adapter);
564         return 0;
565 }
566 
567 static void xlr_config_translate_table(struct xlr_net_priv *priv)
568 {
569         u32 cpu_mask;
570         u32 val;
571         int bkts[32]; /* one bucket is assumed for each cpu */
572         int b1, b2, c1, c2, i, j, k;
573         int use_bkt;
574 
575         use_bkt = 0;
576         cpu_mask = priv->nd->cpu_mask;
577 
578         pr_info("Using %s-based distribution\n",
579                 (use_bkt) ? "bucket" : "class");
580         j = 0;
581         for (i = 0; i < 32; i++) {
582                 if ((1 << i) & cpu_mask) {
583                         /* for each cpu, mark the 4+threadid bucket */
584                         bkts[j] = ((i / 4) * 8) + (i % 4);
585                         j++;
586                 }
587         }
588 
589         /*configure the 128 * 9 Translation table to send to available buckets*/
590         k = 0;
591         c1 = 3;
592         c2 = 0;
593         for (i = 0; i < 64; i++) {
594                 /*
595                  * On use_bkt set the b0, b1 are used, else
596                  * the 4 classes are used, here implemented
597                  * a logic to distribute the packets to the
598                  * buckets equally or based on the class
599                  */
600                 c1 = (c1 + 1) & 3;
601                 c2 = (c1 + 1) & 3;
602                 b1 = bkts[k];
603                 k = (k + 1) % j;
604                 b2 = bkts[k];
605                 k = (k + 1) % j;
606 
607                 val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
608                                 (c2 << 7) | (b2 << 1) | (use_bkt << 0));
609                 dev_dbg(&priv->ndev->dev, "Table[%d] b1=%d b2=%d c1=%d c2=%d\n",
610                         i, b1, b2, c1, c2);
611                 xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val);
612                 c1 = c2;
613         }
614 }
615 
616 static void xlr_config_parser(struct xlr_net_priv *priv)
617 {
618         u32 val;
619 
620         /* Mark it as ETHERNET type */
621         xlr_nae_wreg(priv->base_addr, R_L2TYPE_0, 0x01);
622 
623         /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
624         xlr_nae_wreg(priv->base_addr, R_PARSERCONFIGREG,
625                      ((0x7f << 8) | (1 << 1)));
626 
627         /* configure the parser : L2 Type is configured in the bootloader */
628         /* extract IP: src, dest protocol */
629         xlr_nae_wreg(priv->base_addr, R_L3CTABLE,
630                      (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
631                      (0x0800 << 0));
632         xlr_nae_wreg(priv->base_addr, R_L3CTABLE + 1,
633                      (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) |
634                      (16 << 4) | 4);
635 
636         /* Configure to extract SRC port and Dest port for TCP and UDP pkts */
637         xlr_nae_wreg(priv->base_addr, R_L4CTABLE, 6);
638         xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 2, 17);
639         val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
640         xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val);
641         xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val);
642 
643         xlr_config_translate_table(priv);
644 }
645 
646 static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val)
647 {
648         unsigned long timeout, stoptime, checktime;
649         int timedout;
650 
651         /* 100ms timeout*/
652         timeout = msecs_to_jiffies(100);
653         stoptime = jiffies + timeout;
654         timedout = 0;
655 
656         xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, (phy_addr << 8) | regnum);
657 
658         /* Write the data which starts the write cycle */
659         xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32)val);
660 
661         /* poll for the read cycle to complete */
662         while (!timedout) {
663                 checktime = jiffies;
664                 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
665                         break;
666                 timedout = time_after(checktime, stoptime);
667         }
668         if (timedout) {
669                 pr_info("Phy device write err: device busy");
670                 return -EBUSY;
671         }
672 
673         return 0;
674 }
675 
676 static int xlr_phy_read(u32 *base_addr, int phy_addr, int regnum)
677 {
678         unsigned long timeout, stoptime, checktime;
679         int timedout;
680 
681         /* 100ms timeout*/
682         timeout = msecs_to_jiffies(100);
683         stoptime = jiffies + timeout;
684         timedout = 0;
685 
686         /* setup the phy reg to be used */
687         xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS,
688                      (phy_addr << 8) | (regnum << 0));
689 
690         /* Issue the read command */
691         xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND,
692                      (1 << O_MII_MGMT_COMMAND__rstat));
693 
694         /* poll for the read cycle to complete */
695         while (!timedout) {
696                 checktime = jiffies;
697                 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
698                         break;
699                 timedout = time_after(checktime, stoptime);
700         }
701         if (timedout) {
702                 pr_info("Phy device read err: device busy");
703                 return -EBUSY;
704         }
705 
706         /* clear the read cycle */
707         xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 0);
708 
709         /* Read the data */
710         return xlr_nae_rdreg(base_addr, R_MII_MGMT_STATUS);
711 }
712 
713 static int xlr_mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 val)
714 {
715         struct xlr_net_priv *priv = bus->priv;
716         int ret;
717 
718         ret = xlr_phy_write(priv->mii_addr, phy_addr, regnum, val);
719         dev_dbg(&priv->ndev->dev, "mii_write phy %d : %d <- %x [%x]\n",
720                 phy_addr, regnum, val, ret);
721         return ret;
722 }
723 
724 static int xlr_mii_read(struct mii_bus *bus, int phy_addr, int regnum)
725 {
726         struct xlr_net_priv *priv = bus->priv;
727         int ret;
728 
729         ret =  xlr_phy_read(priv->mii_addr, phy_addr, regnum);
730         dev_dbg(&priv->ndev->dev, "mii_read phy %d : %d [%x]\n",
731                 phy_addr, regnum, ret);
732         return ret;
733 }
734 
735 /*
736  * XLR ports are RGMII. XLS ports are SGMII mostly except the port0,
737  * which can be configured either SGMII or RGMII, considered SGMII
738  * by default, if board setup to RGMII the port_type need to set
739  * accordingly.Serdes and PCS layer need to configured for SGMII
740  */
741 static void xlr_sgmii_init(struct xlr_net_priv *priv)
742 {
743         int phy;
744 
745         xlr_phy_write(priv->serdes_addr, 26, 0, 0x6DB0);
746         xlr_phy_write(priv->serdes_addr, 26, 1, 0xFFFF);
747         xlr_phy_write(priv->serdes_addr, 26, 2, 0xB6D0);
748         xlr_phy_write(priv->serdes_addr, 26, 3, 0x00FF);
749         xlr_phy_write(priv->serdes_addr, 26, 4, 0x0000);
750         xlr_phy_write(priv->serdes_addr, 26, 5, 0x0000);
751         xlr_phy_write(priv->serdes_addr, 26, 6, 0x0005);
752         xlr_phy_write(priv->serdes_addr, 26, 7, 0x0001);
753         xlr_phy_write(priv->serdes_addr, 26, 8, 0x0000);
754         xlr_phy_write(priv->serdes_addr, 26, 9, 0x0000);
755         xlr_phy_write(priv->serdes_addr, 26, 10, 0x0000);
756 
757         /* program  GPIO values for serdes init parameters */
758         xlr_nae_wreg(priv->gpio_addr, 0x20, 0x7e6802);
759         xlr_nae_wreg(priv->gpio_addr, 0x10, 0x7104);
760 
761         xlr_nae_wreg(priv->gpio_addr, 0x22, 0x7e6802);
762         xlr_nae_wreg(priv->gpio_addr, 0x21, 0x7104);
763 
764         /* enable autoneg - more magic */
765         phy = priv->phy_addr % 4 + 27;
766         xlr_phy_write(priv->pcs_addr, phy, 0, 0x1000);
767         xlr_phy_write(priv->pcs_addr, phy, 0, 0x0200);
768 }
769 
770 void xlr_set_gmac_speed(struct xlr_net_priv *priv)
771 {
772         struct phy_device *phydev = xlr_get_phydev(priv);
773         int speed;
774 
775         if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
776                 xlr_sgmii_init(priv);
777 
778         if (phydev->speed != priv->phy_speed) {
779                 speed = phydev->speed;
780                 if (speed == SPEED_1000) {
781                         /* Set interface to Byte mode */
782                         xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
783                         priv->phy_speed = speed;
784                 } else if (speed == SPEED_100 || speed == SPEED_10) {
785                         /* Set interface to Nibble mode */
786                         xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7117);
787                         priv->phy_speed = speed;
788                 }
789                 /* Set SGMII speed in Interface control reg */
790                 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
791                         if (speed == SPEED_10)
792                                 xlr_nae_wreg(priv->base_addr,
793                                              R_INTERFACE_CONTROL,
794                                              SGMII_SPEED_10);
795                         if (speed == SPEED_100)
796                                 xlr_nae_wreg(priv->base_addr,
797                                              R_INTERFACE_CONTROL,
798                                              SGMII_SPEED_100);
799                         if (speed == SPEED_1000)
800                                 xlr_nae_wreg(priv->base_addr,
801                                              R_INTERFACE_CONTROL,
802                                              SGMII_SPEED_1000);
803                 }
804                 if (speed == SPEED_10)
805                         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x2);
806                 if (speed == SPEED_100)
807                         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x1);
808                 if (speed == SPEED_1000)
809                         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x0);
810         }
811         pr_info("gmac%d : %dMbps\n", priv->port_id, priv->phy_speed);
812 }
813 
814 static void xlr_gmac_link_adjust(struct net_device *ndev)
815 {
816         struct xlr_net_priv *priv = netdev_priv(ndev);
817         struct phy_device *phydev = xlr_get_phydev(priv);
818         u32 intreg;
819 
820         intreg = xlr_nae_rdreg(priv->base_addr, R_INTREG);
821         if (phydev->link) {
822                 if (phydev->speed != priv->phy_speed) {
823                         xlr_set_gmac_speed(priv);
824                         pr_info("gmac%d : Link up\n", priv->port_id);
825                 }
826         } else {
827                 xlr_set_gmac_speed(priv);
828                 pr_info("gmac%d : Link down\n", priv->port_id);
829         }
830 }
831 
832 static int xlr_mii_probe(struct xlr_net_priv *priv)
833 {
834         struct phy_device *phydev = xlr_get_phydev(priv);
835 
836         if (!phydev) {
837                 pr_err("no PHY found on phy_addr %d\n", priv->phy_addr);
838                 return -ENODEV;
839         }
840 
841         /* Attach MAC to PHY */
842         phydev = phy_connect(priv->ndev, phydev_name(phydev),
843                              xlr_gmac_link_adjust, priv->nd->phy_interface);
844 
845         if (IS_ERR(phydev)) {
846                 pr_err("could not attach PHY\n");
847                 return PTR_ERR(phydev);
848         }
849         phydev->supported &= (ADVERTISED_10baseT_Full
850                                 | ADVERTISED_10baseT_Half
851                                 | ADVERTISED_100baseT_Full
852                                 | ADVERTISED_100baseT_Half
853                                 | ADVERTISED_1000baseT_Full
854                                 | ADVERTISED_Autoneg
855                                 | ADVERTISED_MII);
856 
857         phydev->advertising = phydev->supported;
858         phy_attached_info(phydev);
859         return 0;
860 }
861 
862 static int xlr_setup_mdio(struct xlr_net_priv *priv,
863                           struct platform_device *pdev)
864 {
865         int err;
866 
867         priv->mii_bus = mdiobus_alloc();
868         if (!priv->mii_bus) {
869                 pr_err("mdiobus alloc failed\n");
870                 return -ENOMEM;
871         }
872 
873         priv->mii_bus->priv = priv;
874         priv->mii_bus->name = "xlr-mdio";
875         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
876                  priv->mii_bus->name, priv->port_id);
877         priv->mii_bus->read = xlr_mii_read;
878         priv->mii_bus->write = xlr_mii_write;
879         priv->mii_bus->parent = &pdev->dev;
880 
881         /* Scan only the enabled address */
882         priv->mii_bus->phy_mask = ~(1 << priv->phy_addr);
883 
884         /* setting clock divisor to 54 */
885         xlr_nae_wreg(priv->base_addr, R_MII_MGMT_CONFIG, 0x7);
886 
887         err = mdiobus_register(priv->mii_bus);
888         if (err) {
889                 mdiobus_free(priv->mii_bus);
890                 pr_err("mdio bus registration failed\n");
891                 return err;
892         }
893 
894         pr_info("Registered mdio bus id : %s\n", priv->mii_bus->id);
895         err = xlr_mii_probe(priv);
896         if (err) {
897                 mdiobus_free(priv->mii_bus);
898                 return err;
899         }
900         return 0;
901 }
902 
903 static void xlr_port_enable(struct xlr_net_priv *priv)
904 {
905         u32 prid = (read_c0_prid() & 0xf000);
906 
907         /* Setup MAC_CONFIG reg if (xls & rgmii) */
908         if ((prid == 0x8000 || prid == 0x4000 || prid == 0xc000) &&
909             priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII)
910                 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
911                                (1 << O_RX_CONTROL__RGMII),
912                                (1 << O_RX_CONTROL__RGMII));
913 
914         /* Rx Tx enable */
915         xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
916                        ((1 << O_MAC_CONFIG_1__rxen) |
917                         (1 << O_MAC_CONFIG_1__txen) |
918                         (1 << O_MAC_CONFIG_1__rxfc) |
919                         (1 << O_MAC_CONFIG_1__txfc)),
920                        ((1 << O_MAC_CONFIG_1__rxen) |
921                         (1 << O_MAC_CONFIG_1__txen) |
922                         (1 << O_MAC_CONFIG_1__rxfc) |
923                         (1 << O_MAC_CONFIG_1__txfc)));
924 
925         /* Setup tx control reg */
926         xlr_reg_update(priv->base_addr, R_TX_CONTROL,
927                        ((1 << O_TX_CONTROL__TXENABLE) |
928                        (512 << O_TX_CONTROL__TXTHRESHOLD)), 0x3fff);
929 
930         /* Setup rx control reg */
931         xlr_reg_update(priv->base_addr, R_RX_CONTROL,
932                        1 << O_RX_CONTROL__RXENABLE,
933                        1 << O_RX_CONTROL__RXENABLE);
934 }
935 
936 static void xlr_port_disable(struct xlr_net_priv *priv)
937 {
938         /* Setup MAC_CONFIG reg */
939         /* Rx Tx disable*/
940         xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
941                        ((1 << O_MAC_CONFIG_1__rxen) |
942                         (1 << O_MAC_CONFIG_1__txen) |
943                         (1 << O_MAC_CONFIG_1__rxfc) |
944                         (1 << O_MAC_CONFIG_1__txfc)), 0x0);
945 
946         /* Setup tx control reg */
947         xlr_reg_update(priv->base_addr, R_TX_CONTROL,
948                        ((1 << O_TX_CONTROL__TXENABLE) |
949                        (512 << O_TX_CONTROL__TXTHRESHOLD)), 0);
950 
951         /* Setup rx control reg */
952         xlr_reg_update(priv->base_addr, R_RX_CONTROL,
953                        1 << O_RX_CONTROL__RXENABLE, 0);
954 }
955 
956 /*
957  * Initialization of gmac
958  */
959 static int xlr_gmac_init(struct xlr_net_priv *priv,
960                          struct platform_device *pdev)
961 {
962         int ret;
963 
964         pr_info("Initializing the gmac%d\n", priv->port_id);
965 
966         xlr_port_disable(priv);
967 
968         xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL,
969                      (1 << O_DESC_PACK_CTRL__MAXENTRY) |
970                      (BYTE_OFFSET << O_DESC_PACK_CTRL__BYTEOFFSET) |
971                      (1600 << O_DESC_PACK_CTRL__REGULARSIZE));
972 
973         ret = xlr_setup_mdio(priv, pdev);
974         if (ret)
975                 return ret;
976         xlr_port_enable(priv);
977 
978         /* Enable Full-duplex/1000Mbps/CRC */
979         xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
980         /* speed 2.5Mhz */
981         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02);
982         /* Setup Interrupt mask reg */
983         xlr_nae_wreg(priv->base_addr, R_INTMASK, (1 << O_INTMASK__TXILLEGAL) |
984                      (1 << O_INTMASK__MDINT) | (1 << O_INTMASK__TXFETCHERROR) |
985                      (1 << O_INTMASK__P2PSPILLECC) | (1 << O_INTMASK__TAGFULL) |
986                      (1 << O_INTMASK__UNDERRUN) | (1 << O_INTMASK__ABORT));
987 
988         /* Clear all stats */
989         xlr_reg_update(priv->base_addr, R_STATCTRL, 0, 1 << O_STATCTRL__CLRCNT);
990         xlr_reg_update(priv->base_addr, R_STATCTRL, 1 << 2, 1 << 2);
991         return 0;
992 }
993 
994 static int xlr_net_probe(struct platform_device *pdev)
995 {
996         struct xlr_net_priv *priv = NULL;
997         struct net_device *ndev;
998         struct resource *res;
999         struct xlr_adapter *adapter;
1000         int err, port;
1001 
1002         pr_info("XLR/XLS Ethernet Driver controller %d\n", pdev->id);
1003         /*
1004          * Allocate our adapter data structure and attach it to the device.
1005          */
1006         adapter = (struct xlr_adapter *)
1007                 devm_kzalloc(&pdev->dev, sizeof(*adapter), GFP_KERNEL);
1008         if (!adapter) {
1009                 err = -ENOMEM;
1010                 return err;
1011         }
1012 
1013         /*
1014          * XLR and XLS have 1 and 2 NAE controller respectively
1015          * Each controller has 4 gmac ports, mapping each controller
1016          * under one parent device, 4 gmac ports under one device.
1017          */
1018         for (port = 0; port < pdev->num_resources / 2; port++) {
1019                 ndev = alloc_etherdev_mq(sizeof(struct xlr_net_priv), 32);
1020                 if (!ndev) {
1021                         dev_err(&pdev->dev,
1022                                 "Allocation of Ethernet device failed\n");
1023                         return -ENOMEM;
1024                 }
1025 
1026                 priv = netdev_priv(ndev);
1027                 priv->pdev = pdev;
1028                 priv->ndev = ndev;
1029                 priv->port_id = (pdev->id * 4) + port;
1030                 priv->nd = (struct xlr_net_data *)pdev->dev.platform_data;
1031                 res = platform_get_resource(pdev, IORESOURCE_MEM, port);
1032                 priv->base_addr = devm_ioremap_resource(&pdev->dev, res);
1033                 if (IS_ERR(priv->base_addr)) {
1034                         err = PTR_ERR(priv->base_addr);
1035                         goto err_gmac;
1036                 }
1037                 priv->adapter = adapter;
1038                 adapter->netdev[port] = ndev;
1039 
1040                 res = platform_get_resource(pdev, IORESOURCE_IRQ, port);
1041                 if (!res) {
1042                         dev_err(&pdev->dev, "No irq resource for MAC %d\n",
1043                                 priv->port_id);
1044                         err = -ENODEV;
1045                         goto err_gmac;
1046                 }
1047 
1048                 ndev->irq = res->start;
1049 
1050                 priv->phy_addr = priv->nd->phy_addr[port];
1051                 priv->tx_stnid = priv->nd->tx_stnid[port];
1052                 priv->mii_addr = priv->nd->mii_addr;
1053                 priv->serdes_addr = priv->nd->serdes_addr;
1054                 priv->pcs_addr = priv->nd->pcs_addr;
1055                 priv->gpio_addr = priv->nd->gpio_addr;
1056 
1057                 ndev->netdev_ops = &xlr_netdev_ops;
1058                 ndev->watchdog_timeo = HZ;
1059 
1060                 /* Setup Mac address and Rx mode */
1061                 eth_hw_addr_random(ndev);
1062                 xlr_hw_set_mac_addr(ndev);
1063                 xlr_set_rx_mode(ndev);
1064 
1065                 priv->num_rx_desc += MAX_NUM_DESC_SPILL;
1066                 ndev->ethtool_ops = &xlr_ethtool_ops;
1067                 SET_NETDEV_DEV(ndev, &pdev->dev);
1068 
1069                 xlr_config_fifo_spill_area(priv);
1070                 /* Configure PDE to Round-Robin pkt distribution */
1071                 xlr_config_pde(priv);
1072                 xlr_config_parser(priv);
1073 
1074                 /* Call init with respect to port */
1075                 if (strcmp(res->name, "gmac") == 0) {
1076                         err = xlr_gmac_init(priv, pdev);
1077                         if (err) {
1078                                 dev_err(&pdev->dev, "gmac%d init failed\n",
1079                                         priv->port_id);
1080                                 goto err_gmac;
1081                         }
1082                 }
1083 
1084                 if (priv->port_id == 0 || priv->port_id == 4) {
1085                         err = xlr_config_common(priv);
1086                         if (err)
1087                                 goto err_netdev;
1088                 }
1089 
1090                 err = register_netdev(ndev);
1091                 if (err) {
1092                         dev_err(&pdev->dev,
1093                                 "Registering netdev failed for gmac%d\n",
1094                                 priv->port_id);
1095                         goto err_netdev;
1096                 }
1097                 platform_set_drvdata(pdev, priv);
1098         }
1099 
1100         return 0;
1101 
1102 err_netdev:
1103         mdiobus_free(priv->mii_bus);
1104 err_gmac:
1105         free_netdev(ndev);
1106         return err;
1107 }
1108 
1109 static int xlr_net_remove(struct platform_device *pdev)
1110 {
1111         struct xlr_net_priv *priv = platform_get_drvdata(pdev);
1112 
1113         unregister_netdev(priv->ndev);
1114         mdiobus_unregister(priv->mii_bus);
1115         mdiobus_free(priv->mii_bus);
1116         free_netdev(priv->ndev);
1117         return 0;
1118 }
1119 
1120 static struct platform_driver xlr_net_driver = {
1121         .probe          = xlr_net_probe,
1122         .remove         = xlr_net_remove,
1123         .driver         = {
1124                 .name   = "xlr-net",
1125         },
1126 };
1127 
1128 module_platform_driver(xlr_net_driver);
1129 
1130 MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
1131 MODULE_DESCRIPTION("Ethernet driver for Netlogic XLR/XLS");
1132 MODULE_LICENSE("Dual BSD/GPL");
1133 MODULE_ALIAS("platform:xlr-net");
1134 

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