Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5

Linux/drivers/staging/netlogic/xlr_net.c

  1 /*
  2  * Copyright (c) 2003-2012 Broadcom Corporation
  3  * All Rights Reserved
  4  *
  5  * This software is available to you under a choice of one of two
  6  * licenses.  You may choose to be licensed under the terms of the GNU
  7  * General Public License (GPL) Version 2, available from the file
  8  * COPYING in the main directory of this source tree, or the Broadcom
  9  * license below:
 10  *
 11  * Redistribution and use in source and binary forms, with or without
 12  * modification, are permitted provided that the following conditions
 13  * are met:
 14  *
 15  * 1. Redistributions of source code must retain the above copyright
 16  *    notice, this list of conditions and the following disclaimer.
 17  * 2. Redistributions in binary form must reproduce the above copyright
 18  *    notice, this list of conditions and the following disclaimer in
 19  *    the documentation and/or other materials provided with the
 20  *    distribution.
 21  *
 22  * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
 23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 25  * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
 26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 33  */
 34 #include <linux/phy.h>
 35 #include <linux/delay.h>
 36 #include <linux/netdevice.h>
 37 #include <linux/smp.h>
 38 #include <linux/ethtool.h>
 39 #include <linux/module.h>
 40 #include <linux/etherdevice.h>
 41 #include <linux/skbuff.h>
 42 #include <linux/jiffies.h>
 43 #include <linux/interrupt.h>
 44 #include <linux/platform_device.h>
 45 
 46 #include <asm/mipsregs.h>
 47 /*
 48  * fmn.h - For FMN credit configuration and registering fmn_handler.
 49  * FMN is communication mechanism that allows processing agents within
 50  * XLR/XLS to communicate each other.
 51  */
 52 #include <asm/netlogic/xlr/fmn.h>
 53 
 54 #include "platform_net.h"
 55 #include "xlr_net.h"
 56 
 57 /*
 58  * The readl/writel implementation byteswaps on XLR/XLS, so
 59  * we need to use __raw_ IO to read the NAE registers
 60  * because they are in the big-endian MMIO area on the SoC.
 61  */
 62 static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val)
 63 {
 64         __raw_writel(val, base + reg);
 65 }
 66 
 67 static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg)
 68 {
 69         return __raw_readl(base + reg);
 70 }
 71 
 72 static inline void xlr_reg_update(u32 *base_addr,
 73                 u32 off, u32 val, u32 mask)
 74 {
 75         u32 tmp;
 76 
 77         tmp = xlr_nae_rdreg(base_addr, off);
 78         xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask));
 79 }
 80 
 81 #define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES
 82 
 83 static int send_to_rfr_fifo(struct xlr_net_priv *priv, void *addr)
 84 {
 85         struct nlm_fmn_msg msg;
 86         int ret = 0, num_try = 0, stnid;
 87         unsigned long paddr, mflags;
 88 
 89         paddr = virt_to_bus(addr);
 90         msg.msg0 = (u64)paddr & 0xffffffffe0ULL;
 91         msg.msg1 = 0;
 92         msg.msg2 = 0;
 93         msg.msg3 = 0;
 94         stnid = priv->nd->rfr_station;
 95         do {
 96                 mflags = nlm_cop2_enable_irqsave();
 97                 ret = nlm_fmn_send(1, 0, stnid, &msg);
 98                 nlm_cop2_disable_irqrestore(mflags);
 99                 if (ret == 0)
100                         return 0;
101         } while (++num_try < 10000);
102 
103         pr_err("Send to RFR failed in RX path\n");
104         return ret;
105 }
106 
107 static inline unsigned char *xlr_alloc_skb(void)
108 {
109         struct sk_buff *skb;
110         int buf_len = sizeof(struct sk_buff *);
111         unsigned char *skb_data;
112 
113         /* skb->data is cache aligned */
114         skb = alloc_skb(XLR_RX_BUF_SIZE, GFP_ATOMIC);
115         if (!skb)
116                 return NULL;
117         skb_data = skb->data;
118         skb_put(skb, MAC_SKB_BACK_PTR_SIZE);
119         skb_pull(skb, MAC_SKB_BACK_PTR_SIZE);
120         memcpy(skb_data, &skb, buf_len);
121 
122         return skb->data;
123 }
124 
125 static void xlr_net_fmn_handler(int bkt, int src_stnid, int size,
126                 int code, struct nlm_fmn_msg *msg, void *arg)
127 {
128         struct sk_buff *skb;
129         void *skb_data = NULL;
130         struct net_device *ndev;
131         struct xlr_net_priv *priv;
132         u32 port, length;
133         unsigned char *addr;
134         struct xlr_adapter *adapter = (struct xlr_adapter *) arg;
135 
136         length = (msg->msg0 >> 40) & 0x3fff;
137         if (length == 0) {
138                 addr = bus_to_virt(msg->msg0 & 0xffffffffffULL);
139                 addr = addr - MAC_SKB_BACK_PTR_SIZE;
140                 skb = (struct sk_buff *) *(unsigned long *)addr;
141                 dev_kfree_skb_any((struct sk_buff *)addr);
142         } else {
143                 addr = (unsigned char *)
144                         bus_to_virt(msg->msg0 & 0xffffffffe0ULL);
145                 length = length - BYTE_OFFSET - MAC_CRC_LEN;
146                 port = ((int)msg->msg0) & 0x0f;
147                 addr = addr - MAC_SKB_BACK_PTR_SIZE;
148                 skb = (struct sk_buff *) *(unsigned long *)addr;
149                 skb->dev = adapter->netdev[port];
150                 if (skb->dev == NULL)
151                         return;
152                 ndev = skb->dev;
153                 priv = netdev_priv(ndev);
154 
155                 /* 16 byte IP header align */
156                 skb_reserve(skb, BYTE_OFFSET);
157                 skb_put(skb, length);
158                 skb->protocol = eth_type_trans(skb, skb->dev);
159                 skb->dev->last_rx = jiffies;
160                 netif_rx(skb);
161                 /* Fill rx ring */
162                 skb_data = xlr_alloc_skb();
163                 if (skb_data)
164                         send_to_rfr_fifo(priv, skb_data);
165         }
166 }
167 
168 static struct phy_device *xlr_get_phydev(struct xlr_net_priv *priv)
169 {
170         return mdiobus_get_phy(priv->mii_bus, priv->phy_addr);
171 }
172 
173 /*
174  * Ethtool operation
175  */
176 static int xlr_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
177 {
178         struct xlr_net_priv *priv = netdev_priv(ndev);
179         struct phy_device *phydev = xlr_get_phydev(priv);
180 
181         if (!phydev)
182                 return -ENODEV;
183         return phy_ethtool_gset(phydev, ecmd);
184 }
185 
186 static int xlr_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
187 {
188         struct xlr_net_priv *priv = netdev_priv(ndev);
189         struct phy_device *phydev = xlr_get_phydev(priv);
190 
191         if (!phydev)
192                 return -ENODEV;
193         return phy_ethtool_sset(phydev, ecmd);
194 }
195 
196 static struct ethtool_ops xlr_ethtool_ops = {
197         .get_settings = xlr_get_settings,
198         .set_settings = xlr_set_settings,
199 };
200 
201 /*
202  * Net operations
203  */
204 static int xlr_net_fill_rx_ring(struct net_device *ndev)
205 {
206         void *skb_data;
207         struct xlr_net_priv *priv = netdev_priv(ndev);
208         int i;
209 
210         for (i = 0; i < MAX_FRIN_SPILL/4; i++) {
211                 skb_data = xlr_alloc_skb();
212                 if (!skb_data) {
213                         pr_err("SKB allocation failed\n");
214                         return -ENOMEM;
215                 }
216                 send_to_rfr_fifo(priv, skb_data);
217         }
218         pr_info("Rx ring setup done\n");
219         return 0;
220 }
221 
222 static int xlr_net_open(struct net_device *ndev)
223 {
224         u32 err;
225         struct xlr_net_priv *priv = netdev_priv(ndev);
226         struct phy_device *phydev = xlr_get_phydev(priv);
227 
228         /* schedule a link state check */
229         phy_start(phydev);
230 
231         err = phy_start_aneg(phydev);
232         if (err) {
233                 pr_err("Autoneg failed\n");
234                 return err;
235         }
236         /* Setup the speed from PHY to internal reg*/
237         xlr_set_gmac_speed(priv);
238 
239         netif_tx_start_all_queues(ndev);
240 
241         return 0;
242 }
243 
244 static int xlr_net_stop(struct net_device *ndev)
245 {
246         struct xlr_net_priv *priv = netdev_priv(ndev);
247         struct phy_device *phydev = xlr_get_phydev(priv);
248 
249         phy_stop(phydev);
250         netif_tx_stop_all_queues(ndev);
251         return 0;
252 }
253 
254 static void xlr_make_tx_desc(struct nlm_fmn_msg *msg, unsigned long addr,
255                 struct sk_buff *skb)
256 {
257         unsigned long physkb = virt_to_phys(skb);
258         int cpu_core = nlm_core_id();
259         int fr_stn_id = cpu_core * 8 + XLR_FB_STN;      /* FB to 6th bucket */
260 
261         msg->msg0 = (((u64)1 << 63)     |       /* End of packet descriptor */
262                 ((u64)127 << 54)        |       /* No Free back */
263                 (u64)skb->len << 40     |       /* Length of data */
264                 ((u64)addr));
265         msg->msg1 = (((u64)1 << 63)     |
266                 ((u64)fr_stn_id << 54)  |       /* Free back id */
267                 (u64)0 << 40            |       /* Set len to 0 */
268                 ((u64)physkb  & 0xffffffff));   /* 32bit address */
269         msg->msg2 = msg->msg3 = 0;
270 }
271 
272 static void __maybe_unused xlr_wakeup_queue(unsigned long dev)
273 {
274         struct net_device *ndev = (struct net_device *) dev;
275         struct xlr_net_priv *priv = netdev_priv(ndev);
276         struct phy_device *phydev = xlr_get_phydev(priv);
277 
278         if (phydev->link)
279                 netif_tx_wake_queue(netdev_get_tx_queue(ndev, priv->wakeup_q));
280 }
281 
282 static netdev_tx_t xlr_net_start_xmit(struct sk_buff *skb,
283                 struct net_device *ndev)
284 {
285         struct nlm_fmn_msg msg;
286         struct xlr_net_priv *priv = netdev_priv(ndev);
287         int ret;
288         u32 flags;
289 
290         xlr_make_tx_desc(&msg, virt_to_phys(skb->data), skb);
291         flags = nlm_cop2_enable_irqsave();
292         ret = nlm_fmn_send(2, 0, priv->tx_stnid, &msg);
293         nlm_cop2_disable_irqrestore(flags);
294         if (ret)
295                 dev_kfree_skb_any(skb);
296         return NETDEV_TX_OK;
297 }
298 
299 static u16 xlr_net_select_queue(struct net_device *ndev, struct sk_buff *skb,
300                                 void *accel_priv,
301                                 select_queue_fallback_t fallback)
302 {
303         return (u16)smp_processor_id();
304 }
305 
306 static void xlr_hw_set_mac_addr(struct net_device *ndev)
307 {
308         struct xlr_net_priv *priv = netdev_priv(ndev);
309 
310         /* set mac station address */
311         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0,
312                 ((ndev->dev_addr[5] << 24) | (ndev->dev_addr[4] << 16) |
313                 (ndev->dev_addr[3] << 8) | (ndev->dev_addr[2])));
314         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1,
315                 ((ndev->dev_addr[1] << 24) | (ndev->dev_addr[0] << 16)));
316 
317         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff);
318         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
319         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff);
320         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
321 
322         xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG,
323                 (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
324                 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
325                 (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID));
326 
327         if (priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII ||
328                         priv->nd->phy_interface == PHY_INTERFACE_MODE_SGMII)
329                 xlr_reg_update(priv->base_addr, R_IPG_IFG, MAC_B2B_IPG, 0x7f);
330 }
331 
332 static int xlr_net_set_mac_addr(struct net_device *ndev, void *data)
333 {
334         int err;
335 
336         err = eth_mac_addr(ndev, data);
337         if (err)
338                 return err;
339         xlr_hw_set_mac_addr(ndev);
340         return 0;
341 }
342 
343 static void xlr_set_rx_mode(struct net_device *ndev)
344 {
345         struct xlr_net_priv *priv = netdev_priv(ndev);
346         u32 regval;
347 
348         regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG);
349 
350         if (ndev->flags & IFF_PROMISC) {
351                 regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
352                 (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
353                 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
354                 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
355         } else {
356                 regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
357                 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
358         }
359 
360         xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval);
361 }
362 
363 static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats)
364 {
365         struct xlr_net_priv *priv = netdev_priv(ndev);
366 
367         stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER);
368         stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER);
369         stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER);
370         stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER);
371         stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER);
372         stats->rx_dropped = xlr_nae_rdreg(priv->base_addr,
373                         RX_DROP_PACKET_COUNTER);
374         stats->tx_dropped = xlr_nae_rdreg(priv->base_addr,
375                         TX_DROP_FRAME_COUNTER);
376 
377         stats->multicast = xlr_nae_rdreg(priv->base_addr,
378                         RX_MULTICAST_PACKET_COUNTER);
379         stats->collisions = xlr_nae_rdreg(priv->base_addr,
380                         TX_TOTAL_COLLISION_COUNTER);
381 
382         stats->rx_length_errors = xlr_nae_rdreg(priv->base_addr,
383                         RX_FRAME_LENGTH_ERROR_COUNTER);
384         stats->rx_over_errors = xlr_nae_rdreg(priv->base_addr,
385                         RX_DROP_PACKET_COUNTER);
386         stats->rx_crc_errors = xlr_nae_rdreg(priv->base_addr,
387                         RX_FCS_ERROR_COUNTER);
388         stats->rx_frame_errors = xlr_nae_rdreg(priv->base_addr,
389                         RX_ALIGNMENT_ERROR_COUNTER);
390 
391         stats->rx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
392                         RX_DROP_PACKET_COUNTER);
393         stats->rx_missed_errors = xlr_nae_rdreg(priv->base_addr,
394                         RX_CARRIER_SENSE_ERROR_COUNTER);
395 
396         stats->rx_errors = (stats->rx_over_errors + stats->rx_crc_errors +
397                         stats->rx_frame_errors + stats->rx_fifo_errors +
398                         stats->rx_missed_errors);
399 
400         stats->tx_aborted_errors = xlr_nae_rdreg(priv->base_addr,
401                         TX_EXCESSIVE_COLLISION_PACKET_COUNTER);
402         stats->tx_carrier_errors = xlr_nae_rdreg(priv->base_addr,
403                         TX_DROP_FRAME_COUNTER);
404         stats->tx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
405                         TX_DROP_FRAME_COUNTER);
406 }
407 
408 static struct rtnl_link_stats64 *xlr_get_stats64(struct net_device *ndev,
409                 struct rtnl_link_stats64 *stats)
410 {
411         xlr_stats(ndev, stats);
412         return stats;
413 }
414 
415 static struct net_device_ops xlr_netdev_ops = {
416         .ndo_open = xlr_net_open,
417         .ndo_stop = xlr_net_stop,
418         .ndo_start_xmit = xlr_net_start_xmit,
419         .ndo_select_queue = xlr_net_select_queue,
420         .ndo_set_mac_address = xlr_net_set_mac_addr,
421         .ndo_set_rx_mode = xlr_set_rx_mode,
422         .ndo_get_stats64 = xlr_get_stats64,
423 };
424 
425 /*
426  * Gmac init
427  */
428 static void *xlr_config_spill(struct xlr_net_priv *priv, int reg_start_0,
429                 int reg_start_1, int reg_size, int size)
430 {
431         void *spill;
432         u32 *base;
433         unsigned long phys_addr;
434         u32 spill_size;
435 
436         base = priv->base_addr;
437         spill_size = size;
438         spill = kmalloc(spill_size + SMP_CACHE_BYTES, GFP_ATOMIC);
439         if (!spill)
440                 pr_err("Unable to allocate memory for spill area!\n");
441 
442         spill = PTR_ALIGN(spill, SMP_CACHE_BYTES);
443         phys_addr = virt_to_phys(spill);
444         dev_dbg(&priv->ndev->dev, "Allocated spill %d bytes at %lx\n",
445                         size, phys_addr);
446         xlr_nae_wreg(base, reg_start_0, (phys_addr >> 5) & 0xffffffff);
447         xlr_nae_wreg(base, reg_start_1, ((u64)phys_addr >> 37) & 0x07);
448         xlr_nae_wreg(base, reg_size, spill_size);
449 
450         return spill;
451 }
452 
453 /*
454  * Configure the 6 FIFO's that are used by the network accelarator to
455  * communicate with the rest of the XLx device. 4 of the FIFO's are for
456  * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding
457  * the NA with free descriptors.
458  */
459 static void xlr_config_fifo_spill_area(struct xlr_net_priv *priv)
460 {
461         priv->frin_spill = xlr_config_spill(priv,
462                         R_REG_FRIN_SPILL_MEM_START_0,
463                         R_REG_FRIN_SPILL_MEM_START_1,
464                         R_REG_FRIN_SPILL_MEM_SIZE,
465                         MAX_FRIN_SPILL *
466                         sizeof(u64));
467         priv->frout_spill = xlr_config_spill(priv,
468                         R_FROUT_SPILL_MEM_START_0,
469                         R_FROUT_SPILL_MEM_START_1,
470                         R_FROUT_SPILL_MEM_SIZE,
471                         MAX_FROUT_SPILL *
472                         sizeof(u64));
473         priv->class_0_spill = xlr_config_spill(priv,
474                         R_CLASS0_SPILL_MEM_START_0,
475                         R_CLASS0_SPILL_MEM_START_1,
476                         R_CLASS0_SPILL_MEM_SIZE,
477                         MAX_CLASS_0_SPILL *
478                         sizeof(u64));
479         priv->class_1_spill = xlr_config_spill(priv,
480                         R_CLASS1_SPILL_MEM_START_0,
481                         R_CLASS1_SPILL_MEM_START_1,
482                         R_CLASS1_SPILL_MEM_SIZE,
483                         MAX_CLASS_1_SPILL *
484                         sizeof(u64));
485         priv->class_2_spill = xlr_config_spill(priv,
486                         R_CLASS2_SPILL_MEM_START_0,
487                         R_CLASS2_SPILL_MEM_START_1,
488                         R_CLASS2_SPILL_MEM_SIZE,
489                         MAX_CLASS_2_SPILL *
490                         sizeof(u64));
491         priv->class_3_spill = xlr_config_spill(priv,
492                         R_CLASS3_SPILL_MEM_START_0,
493                         R_CLASS3_SPILL_MEM_START_1,
494                         R_CLASS3_SPILL_MEM_SIZE,
495                         MAX_CLASS_3_SPILL *
496                         sizeof(u64));
497 }
498 
499 /*
500  * Configure PDE to Round-Robin distribution of packets to the
501  * available cpu
502  */
503 static void xlr_config_pde(struct xlr_net_priv *priv)
504 {
505         int i = 0;
506         u64 bkt_map = 0;
507 
508         /* Each core has 8 buckets(station) */
509         for (i = 0; i < hweight32(priv->nd->cpu_mask); i++)
510                 bkt_map |= (0xff << (i * 8));
511 
512         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0, (bkt_map & 0xffffffff));
513         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0 + 1,
514                         ((bkt_map >> 32) & 0xffffffff));
515 
516         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1, (bkt_map & 0xffffffff));
517         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1 + 1,
518                         ((bkt_map >> 32) & 0xffffffff));
519 
520         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2, (bkt_map & 0xffffffff));
521         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2 + 1,
522                         ((bkt_map >> 32) & 0xffffffff));
523 
524         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3, (bkt_map & 0xffffffff));
525         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3 + 1,
526                         ((bkt_map >> 32) & 0xffffffff));
527 }
528 
529 /*
530  * Setup the Message ring credits, bucket size and other
531  * common configuration
532  */
533 static int xlr_config_common(struct xlr_net_priv *priv)
534 {
535         struct xlr_fmn_info *gmac = priv->nd->gmac_fmn_info;
536         int start_stn_id = gmac->start_stn_id;
537         int end_stn_id = gmac->end_stn_id;
538         int *bucket_size = priv->nd->bucket_size;
539         int i, j, err;
540 
541         /* Setting non-core MsgBktSize(0x321 - 0x325) */
542         for (i = start_stn_id; i <= end_stn_id; i++) {
543                 xlr_nae_wreg(priv->base_addr,
544                                 R_GMAC_RFR0_BUCKET_SIZE + i - start_stn_id,
545                                 bucket_size[i]);
546         }
547 
548         /*
549          * Setting non-core Credit counter register
550          * Distributing Gmac's credit to CPU's
551          */
552         for (i = 0; i < 8; i++) {
553                 for (j = 0; j < 8; j++)
554                         xlr_nae_wreg(priv->base_addr,
555                                         (R_CC_CPU0_0 + (i * 8)) + j,
556                                         gmac->credit_config[(i * 8) + j]);
557         }
558 
559         xlr_nae_wreg(priv->base_addr, R_MSG_TX_THRESHOLD, 3);
560         xlr_nae_wreg(priv->base_addr, R_DMACR0, 0xffffffff);
561         xlr_nae_wreg(priv->base_addr, R_DMACR1, 0xffffffff);
562         xlr_nae_wreg(priv->base_addr, R_DMACR2, 0xffffffff);
563         xlr_nae_wreg(priv->base_addr, R_DMACR3, 0xffffffff);
564         xlr_nae_wreg(priv->base_addr, R_FREEQCARVE, 0);
565 
566         err = xlr_net_fill_rx_ring(priv->ndev);
567         if (err)
568                 return err;
569         nlm_register_fmn_handler(start_stn_id, end_stn_id, xlr_net_fmn_handler,
570                         priv->adapter);
571         return 0;
572 }
573 
574 static void xlr_config_translate_table(struct xlr_net_priv *priv)
575 {
576         u32 cpu_mask;
577         u32 val;
578         int bkts[32]; /* one bucket is assumed for each cpu */
579         int b1, b2, c1, c2, i, j, k;
580         int use_bkt;
581 
582         use_bkt = 0;
583         cpu_mask = priv->nd->cpu_mask;
584 
585         pr_info("Using %s-based distribution\n",
586                         (use_bkt) ? "bucket" : "class");
587         j = 0;
588         for (i = 0; i < 32; i++) {
589                 if ((1 << i) & cpu_mask) {
590                         /* for each cpu, mark the 4+threadid bucket */
591                         bkts[j] = ((i / 4) * 8) + (i % 4);
592                         j++;
593                 }
594         }
595 
596         /*configure the 128 * 9 Translation table to send to available buckets*/
597         k = 0;
598         c1 = 3;
599         c2 = 0;
600         for (i = 0; i < 64; i++) {
601                 /*
602                  * On use_bkt set the b0, b1 are used, else
603                  * the 4 classes are used, here implemented
604                  * a logic to distribute the packets to the
605                  * buckets equally or based on the class
606                  */
607                 c1 = (c1 + 1) & 3;
608                 c2 = (c1 + 1) & 3;
609                 b1 = bkts[k];
610                 k = (k + 1) % j;
611                 b2 = bkts[k];
612                 k = (k + 1) % j;
613 
614                 val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
615                                 (c2 << 7) | (b2 << 1) | (use_bkt << 0));
616                 dev_dbg(&priv->ndev->dev, "Table[%d] b1=%d b2=%d c1=%d c2=%d\n",
617                                 i, b1, b2, c1, c2);
618                 xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val);
619                 c1 = c2;
620         }
621 }
622 
623 static void xlr_config_parser(struct xlr_net_priv *priv)
624 {
625         u32 val;
626 
627         /* Mark it as ETHERNET type */
628         xlr_nae_wreg(priv->base_addr, R_L2TYPE_0, 0x01);
629 
630         /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
631         xlr_nae_wreg(priv->base_addr, R_PARSERCONFIGREG,
632                         ((0x7f << 8) | (1 << 1)));
633 
634         /* configure the parser : L2 Type is configured in the bootloader */
635         /* extract IP: src, dest protocol */
636         xlr_nae_wreg(priv->base_addr, R_L3CTABLE,
637                         (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
638                         (0x0800 << 0));
639         xlr_nae_wreg(priv->base_addr, R_L3CTABLE + 1,
640                         (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) |
641                         (16 << 4) | 4);
642 
643         /* Configure to extract SRC port and Dest port for TCP and UDP pkts */
644         xlr_nae_wreg(priv->base_addr, R_L4CTABLE, 6);
645         xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 2, 17);
646         val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
647         xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val);
648         xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val);
649 
650         xlr_config_translate_table(priv);
651 }
652 
653 static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val)
654 {
655         unsigned long timeout, stoptime, checktime;
656         int timedout;
657 
658         /* 100ms timeout*/
659         timeout = msecs_to_jiffies(100);
660         stoptime = jiffies + timeout;
661         timedout = 0;
662 
663         xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, (phy_addr << 8) | regnum);
664 
665         /* Write the data which starts the write cycle */
666         xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32) val);
667 
668         /* poll for the read cycle to complete */
669         while (!timedout) {
670                 checktime = jiffies;
671                 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
672                         break;
673                 timedout = time_after(checktime, stoptime);
674         }
675         if (timedout) {
676                 pr_info("Phy device write err: device busy");
677                 return -EBUSY;
678         }
679 
680         return 0;
681 }
682 
683 static int xlr_phy_read(u32 *base_addr, int phy_addr, int regnum)
684 {
685         unsigned long timeout, stoptime, checktime;
686         int timedout;
687 
688         /* 100ms timeout*/
689         timeout = msecs_to_jiffies(100);
690         stoptime = jiffies + timeout;
691         timedout = 0;
692 
693         /* setup the phy reg to be used */
694         xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS,
695                         (phy_addr << 8) | (regnum << 0));
696 
697         /* Issue the read command */
698         xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND,
699                         (1 << O_MII_MGMT_COMMAND__rstat));
700 
701         /* poll for the read cycle to complete */
702         while (!timedout) {
703                 checktime = jiffies;
704                 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
705                         break;
706                 timedout = time_after(checktime, stoptime);
707         }
708         if (timedout) {
709                 pr_info("Phy device read err: device busy");
710                 return -EBUSY;
711         }
712 
713         /* clear the read cycle */
714         xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 0);
715 
716         /* Read the data */
717         return xlr_nae_rdreg(base_addr, R_MII_MGMT_STATUS);
718 }
719 
720 static int xlr_mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 val)
721 {
722         struct xlr_net_priv *priv = bus->priv;
723         int ret;
724 
725         ret = xlr_phy_write(priv->mii_addr, phy_addr, regnum, val);
726         dev_dbg(&priv->ndev->dev, "mii_write phy %d : %d <- %x [%x]\n",
727                         phy_addr, regnum, val, ret);
728         return ret;
729 }
730 
731 static int xlr_mii_read(struct mii_bus *bus, int phy_addr, int regnum)
732 {
733         struct xlr_net_priv *priv = bus->priv;
734         int ret;
735 
736         ret =  xlr_phy_read(priv->mii_addr, phy_addr, regnum);
737         dev_dbg(&priv->ndev->dev, "mii_read phy %d : %d [%x]\n",
738                         phy_addr, regnum, ret);
739         return ret;
740 }
741 
742 /*
743  * XLR ports are RGMII. XLS ports are SGMII mostly except the port0,
744  * which can be configured either SGMII or RGMII, considered SGMII
745  * by default, if board setup to RGMII the port_type need to set
746  * accordingly.Serdes and PCS layer need to configured for SGMII
747  */
748 static void xlr_sgmii_init(struct xlr_net_priv *priv)
749 {
750         int phy;
751 
752         xlr_phy_write(priv->serdes_addr, 26, 0, 0x6DB0);
753         xlr_phy_write(priv->serdes_addr, 26, 1, 0xFFFF);
754         xlr_phy_write(priv->serdes_addr, 26, 2, 0xB6D0);
755         xlr_phy_write(priv->serdes_addr, 26, 3, 0x00FF);
756         xlr_phy_write(priv->serdes_addr, 26, 4, 0x0000);
757         xlr_phy_write(priv->serdes_addr, 26, 5, 0x0000);
758         xlr_phy_write(priv->serdes_addr, 26, 6, 0x0005);
759         xlr_phy_write(priv->serdes_addr, 26, 7, 0x0001);
760         xlr_phy_write(priv->serdes_addr, 26, 8, 0x0000);
761         xlr_phy_write(priv->serdes_addr, 26, 9, 0x0000);
762         xlr_phy_write(priv->serdes_addr, 26, 10, 0x0000);
763 
764         /* program  GPIO values for serdes init parameters */
765         xlr_nae_wreg(priv->gpio_addr, 0x20, 0x7e6802);
766         xlr_nae_wreg(priv->gpio_addr, 0x10, 0x7104);
767 
768         xlr_nae_wreg(priv->gpio_addr, 0x22, 0x7e6802);
769         xlr_nae_wreg(priv->gpio_addr, 0x21, 0x7104);
770 
771         /* enable autoneg - more magic */
772         phy = priv->phy_addr % 4 + 27;
773         xlr_phy_write(priv->pcs_addr, phy, 0, 0x1000);
774         xlr_phy_write(priv->pcs_addr, phy, 0, 0x0200);
775 }
776 
777 void xlr_set_gmac_speed(struct xlr_net_priv *priv)
778 {
779         struct phy_device *phydev = xlr_get_phydev(priv);
780         int speed;
781 
782         if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
783                 xlr_sgmii_init(priv);
784 
785         if (phydev->speed != priv->phy_speed) {
786                 speed = phydev->speed;
787                 if (speed == SPEED_1000) {
788                         /* Set interface to Byte mode */
789                         xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
790                         priv->phy_speed = speed;
791                 } else if (speed == SPEED_100 || speed == SPEED_10) {
792                         /* Set interface to Nibble mode */
793                         xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7117);
794                         priv->phy_speed = speed;
795                 }
796                 /* Set SGMII speed in Interface control reg */
797                 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
798                         if (speed == SPEED_10)
799                                 xlr_nae_wreg(priv->base_addr,
800                                         R_INTERFACE_CONTROL, SGMII_SPEED_10);
801                         if (speed == SPEED_100)
802                                 xlr_nae_wreg(priv->base_addr,
803                                         R_INTERFACE_CONTROL, SGMII_SPEED_100);
804                         if (speed == SPEED_1000)
805                                 xlr_nae_wreg(priv->base_addr,
806                                         R_INTERFACE_CONTROL, SGMII_SPEED_1000);
807                 }
808                 if (speed == SPEED_10)
809                         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x2);
810                 if (speed == SPEED_100)
811                         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x1);
812                 if (speed == SPEED_1000)
813                         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x0);
814         }
815         pr_info("gmac%d : %dMbps\n", priv->port_id, priv->phy_speed);
816 }
817 
818 static void xlr_gmac_link_adjust(struct net_device *ndev)
819 {
820         struct xlr_net_priv *priv = netdev_priv(ndev);
821         struct phy_device *phydev = xlr_get_phydev(priv);
822         u32 intreg;
823 
824         intreg = xlr_nae_rdreg(priv->base_addr, R_INTREG);
825         if (phydev->link) {
826                 if (phydev->speed != priv->phy_speed) {
827                         xlr_set_gmac_speed(priv);
828                         pr_info("gmac%d : Link up\n", priv->port_id);
829                 }
830         } else {
831                 xlr_set_gmac_speed(priv);
832                 pr_info("gmac%d : Link down\n", priv->port_id);
833         }
834 }
835 
836 static int xlr_mii_probe(struct xlr_net_priv *priv)
837 {
838         struct phy_device *phydev = xlr_get_phydev(priv);
839 
840         if (!phydev) {
841                 pr_err("no PHY found on phy_addr %d\n", priv->phy_addr);
842                 return -ENODEV;
843         }
844 
845         /* Attach MAC to PHY */
846         phydev = phy_connect(priv->ndev, phydev_name(phydev),
847                              &xlr_gmac_link_adjust, priv->nd->phy_interface);
848 
849         if (IS_ERR(phydev)) {
850                 pr_err("could not attach PHY\n");
851                 return PTR_ERR(phydev);
852         }
853         phydev->supported &= (ADVERTISED_10baseT_Full
854                                 | ADVERTISED_10baseT_Half
855                                 | ADVERTISED_100baseT_Full
856                                 | ADVERTISED_100baseT_Half
857                                 | ADVERTISED_1000baseT_Full
858                                 | ADVERTISED_Autoneg
859                                 | ADVERTISED_MII);
860 
861         phydev->advertising = phydev->supported;
862         phy_attached_info(phydev);
863         return 0;
864 }
865 
866 static int xlr_setup_mdio(struct xlr_net_priv *priv,
867                 struct platform_device *pdev)
868 {
869         int err;
870 
871         priv->mii_bus = mdiobus_alloc();
872         if (!priv->mii_bus) {
873                 pr_err("mdiobus alloc failed\n");
874                 return -ENOMEM;
875         }
876 
877         priv->mii_bus->priv = priv;
878         priv->mii_bus->name = "xlr-mdio";
879         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
880                         priv->mii_bus->name, priv->port_id);
881         priv->mii_bus->read = xlr_mii_read;
882         priv->mii_bus->write = xlr_mii_write;
883         priv->mii_bus->parent = &pdev->dev;
884 
885         /* Scan only the enabled address */
886         priv->mii_bus->phy_mask = ~(1 << priv->phy_addr);
887 
888         /* setting clock divisor to 54 */
889         xlr_nae_wreg(priv->base_addr, R_MII_MGMT_CONFIG, 0x7);
890 
891         err = mdiobus_register(priv->mii_bus);
892         if (err) {
893                 mdiobus_free(priv->mii_bus);
894                 pr_err("mdio bus registration failed\n");
895                 return err;
896         }
897 
898         pr_info("Registered mdio bus id : %s\n", priv->mii_bus->id);
899         err = xlr_mii_probe(priv);
900         if (err) {
901                 mdiobus_free(priv->mii_bus);
902                 return err;
903         }
904         return 0;
905 }
906 
907 static void xlr_port_enable(struct xlr_net_priv *priv)
908 {
909         u32 prid = (read_c0_prid() & 0xf000);
910 
911         /* Setup MAC_CONFIG reg if (xls & rgmii) */
912         if ((prid == 0x8000 || prid == 0x4000 || prid == 0xc000) &&
913                         priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII)
914                 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
915                         (1 << O_RX_CONTROL__RGMII), (1 << O_RX_CONTROL__RGMII));
916 
917         /* Rx Tx enable */
918         xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
919                 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) |
920                 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)),
921                 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) |
922                 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)));
923 
924         /* Setup tx control reg */
925         xlr_reg_update(priv->base_addr, R_TX_CONTROL,
926                 ((1 << O_TX_CONTROL__TxEnable) |
927                 (512 << O_TX_CONTROL__TxThreshold)), 0x3fff);
928 
929         /* Setup rx control reg */
930         xlr_reg_update(priv->base_addr, R_RX_CONTROL,
931                 1 << O_RX_CONTROL__RxEnable, 1 << O_RX_CONTROL__RxEnable);
932 }
933 
934 static void xlr_port_disable(struct xlr_net_priv *priv)
935 {
936         /* Setup MAC_CONFIG reg */
937         /* Rx Tx disable*/
938         xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
939                 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) |
940                 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)),
941                 0x0);
942 
943         /* Setup tx control reg */
944         xlr_reg_update(priv->base_addr, R_TX_CONTROL,
945                 ((1 << O_TX_CONTROL__TxEnable) |
946                 (512 << O_TX_CONTROL__TxThreshold)), 0);
947 
948         /* Setup rx control reg */
949         xlr_reg_update(priv->base_addr, R_RX_CONTROL,
950                 1 << O_RX_CONTROL__RxEnable, 0);
951 }
952 
953 /*
954  * Initialization of gmac
955  */
956 static int xlr_gmac_init(struct xlr_net_priv *priv,
957                 struct platform_device *pdev)
958 {
959         int ret;
960 
961         pr_info("Initializing the gmac%d\n", priv->port_id);
962 
963         xlr_port_disable(priv);
964 
965         xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL,
966                         (1 << O_DESC_PACK_CTRL__MaxEntry)
967                         | (BYTE_OFFSET << O_DESC_PACK_CTRL__ByteOffset)
968                         | (1600 << O_DESC_PACK_CTRL__RegularSize));
969 
970         ret = xlr_setup_mdio(priv, pdev);
971         if (ret)
972                 return ret;
973         xlr_port_enable(priv);
974 
975         /* Enable Full-duplex/1000Mbps/CRC */
976         xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
977         /* speed 2.5Mhz */
978         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02);
979         /* Setup Interrupt mask reg */
980         xlr_nae_wreg(priv->base_addr, R_INTMASK,
981                 (1 << O_INTMASK__TxIllegal)     |
982                 (1 << O_INTMASK__MDInt)         |
983                 (1 << O_INTMASK__TxFetchError)  |
984                 (1 << O_INTMASK__P2PSpillEcc)   |
985                 (1 << O_INTMASK__TagFull)       |
986                 (1 << O_INTMASK__Underrun)      |
987                 (1 << O_INTMASK__Abort)
988                 );
989 
990         /* Clear all stats */
991         xlr_reg_update(priv->base_addr, R_STATCTRL,
992                 0, 1 << O_STATCTRL__ClrCnt);
993         xlr_reg_update(priv->base_addr, R_STATCTRL, 1 << 2,
994                 1 << 2);
995         return 0;
996 }
997 
998 static int xlr_net_probe(struct platform_device *pdev)
999 {
1000         struct xlr_net_priv *priv = NULL;
1001         struct net_device *ndev;
1002         struct resource *res;
1003         struct xlr_adapter *adapter;
1004         int err, port;
1005 
1006         pr_info("XLR/XLS Ethernet Driver controller %d\n", pdev->id);
1007         /*
1008          * Allocate our adapter data structure and attach it to the device.
1009          */
1010         adapter = (struct xlr_adapter *)
1011                 devm_kzalloc(&pdev->dev, sizeof(*adapter), GFP_KERNEL);
1012         if (!adapter) {
1013                 err = -ENOMEM;
1014                 return err;
1015         }
1016 
1017         /*
1018          * XLR and XLS have 1 and 2 NAE controller respectively
1019          * Each controller has 4 gmac ports, mapping each controller
1020          * under one parent device, 4 gmac ports under one device.
1021          */
1022         for (port = 0; port < pdev->num_resources/2; port++) {
1023                 ndev = alloc_etherdev_mq(sizeof(struct xlr_net_priv), 32);
1024                 if (!ndev) {
1025                         pr_err("Allocation of Ethernet device failed\n");
1026                         return -ENOMEM;
1027                 }
1028 
1029                 priv = netdev_priv(ndev);
1030                 priv->pdev = pdev;
1031                 priv->ndev = ndev;
1032                 priv->port_id = (pdev->id * 4) + port;
1033                 priv->nd = (struct xlr_net_data *)pdev->dev.platform_data;
1034                 res = platform_get_resource(pdev, IORESOURCE_MEM, port);
1035 
1036                 if (res == NULL) {
1037                         pr_err("No memory resource for MAC %d\n",
1038                                         priv->port_id);
1039                         err = -ENODEV;
1040                         goto err_gmac;
1041                 }
1042                 priv->base_addr = devm_ioremap_resource(&pdev->dev, res);
1043                 if (IS_ERR(priv->base_addr)) {
1044                         err = PTR_ERR(priv->base_addr);
1045                         goto err_gmac;
1046                 }
1047                 priv->adapter = adapter;
1048                 adapter->netdev[port] = ndev;
1049 
1050                 res = platform_get_resource(pdev, IORESOURCE_IRQ, port);
1051                 if (res == NULL) {
1052                         pr_err("No irq resource for MAC %d\n", priv->port_id);
1053                         err = -ENODEV;
1054                         goto err_gmac;
1055                 }
1056 
1057                 ndev->irq = res->start;
1058 
1059                 priv->phy_addr = priv->nd->phy_addr[port];
1060                 priv->tx_stnid = priv->nd->tx_stnid[port];
1061                 priv->mii_addr = priv->nd->mii_addr;
1062                 priv->serdes_addr = priv->nd->serdes_addr;
1063                 priv->pcs_addr = priv->nd->pcs_addr;
1064                 priv->gpio_addr = priv->nd->gpio_addr;
1065 
1066                 ndev->netdev_ops = &xlr_netdev_ops;
1067                 ndev->watchdog_timeo = HZ;
1068 
1069                 /* Setup Mac address and Rx mode */
1070                 eth_hw_addr_random(ndev);
1071                 xlr_hw_set_mac_addr(ndev);
1072                 xlr_set_rx_mode(ndev);
1073 
1074                 priv->num_rx_desc += MAX_NUM_DESC_SPILL;
1075                 ndev->ethtool_ops = &xlr_ethtool_ops;
1076                 SET_NETDEV_DEV(ndev, &pdev->dev);
1077 
1078                 xlr_config_fifo_spill_area(priv);
1079                 /* Configure PDE to Round-Robin pkt distribution */
1080                 xlr_config_pde(priv);
1081                 xlr_config_parser(priv);
1082 
1083                 /* Call init with respect to port */
1084                 if (strcmp(res->name, "gmac") == 0) {
1085                         err = xlr_gmac_init(priv, pdev);
1086                         if (err) {
1087                                 pr_err("gmac%d init failed\n", priv->port_id);
1088                                 goto err_gmac;
1089                         }
1090                 }
1091 
1092                 if (priv->port_id == 0 || priv->port_id == 4) {
1093                         err = xlr_config_common(priv);
1094                         if (err)
1095                                 goto err_netdev;
1096                 }
1097 
1098                 err = register_netdev(ndev);
1099                 if (err) {
1100                         pr_err("Registering netdev failed for gmac%d\n",
1101                                         priv->port_id);
1102                         goto err_netdev;
1103                 }
1104                 platform_set_drvdata(pdev, priv);
1105         }
1106 
1107         return 0;
1108 
1109 err_netdev:
1110         mdiobus_free(priv->mii_bus);
1111 err_gmac:
1112         free_netdev(ndev);
1113         return err;
1114 }
1115 
1116 static int xlr_net_remove(struct platform_device *pdev)
1117 {
1118         struct xlr_net_priv *priv = platform_get_drvdata(pdev);
1119 
1120         unregister_netdev(priv->ndev);
1121         mdiobus_unregister(priv->mii_bus);
1122         mdiobus_free(priv->mii_bus);
1123         free_netdev(priv->ndev);
1124         return 0;
1125 }
1126 
1127 static struct platform_driver xlr_net_driver = {
1128         .probe          = xlr_net_probe,
1129         .remove         = xlr_net_remove,
1130         .driver         = {
1131                 .name   = "xlr-net",
1132         },
1133 };
1134 
1135 module_platform_driver(xlr_net_driver);
1136 
1137 MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
1138 MODULE_DESCRIPTION("Ethernet driver for Netlogic XLR/XLS");
1139 MODULE_LICENSE("Dual BSD/GPL");
1140 MODULE_ALIAS("platform:xlr-net");
1141 

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