Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/staging/mt29f_spinand/mt29f_spinand.c

  1 /*
  2  * Copyright (c) 2003-2013 Broadcom Corporation
  3  *
  4  * Copyright (c) 2009-2010 Micron Technology, Inc.
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License
  8  * as published by the Free Software Foundation; either version 2
  9  * of the License, or (at your option) any later version.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  */
 16 
 17 #include <linux/module.h>
 18 #include <linux/delay.h>
 19 #include <linux/mtd/mtd.h>
 20 #include <linux/mtd/partitions.h>
 21 #include <linux/mtd/nand.h>
 22 #include <linux/spi/spi.h>
 23 
 24 #include "mt29f_spinand.h"
 25 
 26 #define BUFSIZE (10 * 64 * 2048)
 27 #define CACHE_BUF 2112
 28 /*
 29  * OOB area specification layout:  Total 32 available free bytes.
 30  */
 31 
 32 static inline struct spinand_state *mtd_to_state(struct mtd_info *mtd)
 33 {
 34         struct nand_chip *chip = (struct nand_chip *)mtd->priv;
 35         struct spinand_info *info = (struct spinand_info *)chip->priv;
 36         struct spinand_state *state = (struct spinand_state *)info->priv;
 37 
 38         return state;
 39 }
 40 
 41 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 42 static int enable_hw_ecc;
 43 static int enable_read_hw_ecc;
 44 
 45 static struct nand_ecclayout spinand_oob_64 = {
 46         .eccbytes = 24,
 47         .eccpos = {
 48                 1, 2, 3, 4, 5, 6,
 49                 17, 18, 19, 20, 21, 22,
 50                 33, 34, 35, 36, 37, 38,
 51                 49, 50, 51, 52, 53, 54, },
 52         .oobavail = 32,
 53         .oobfree = {
 54                 {.offset = 8,
 55                         .length = 8},
 56                 {.offset = 24,
 57                         .length = 8},
 58                 {.offset = 40,
 59                         .length = 8},
 60                 {.offset = 56,
 61                         .length = 8},
 62         }
 63 };
 64 #endif
 65 
 66 /*
 67  * spinand_cmd - to process a command to send to the SPI Nand
 68  * Description:
 69  *    Set up the command buffer to send to the SPI controller.
 70  *    The command buffer has to initialized to 0.
 71  */
 72 
 73 static int spinand_cmd(struct spi_device *spi, struct spinand_cmd *cmd)
 74 {
 75         struct spi_message message;
 76         struct spi_transfer x[4];
 77         u8 dummy = 0xff;
 78 
 79         spi_message_init(&message);
 80         memset(x, 0, sizeof(x));
 81 
 82         x[0].len = 1;
 83         x[0].tx_buf = &cmd->cmd;
 84         spi_message_add_tail(&x[0], &message);
 85 
 86         if (cmd->n_addr) {
 87                 x[1].len = cmd->n_addr;
 88                 x[1].tx_buf = cmd->addr;
 89                 spi_message_add_tail(&x[1], &message);
 90         }
 91 
 92         if (cmd->n_dummy) {
 93                 x[2].len = cmd->n_dummy;
 94                 x[2].tx_buf = &dummy;
 95                 spi_message_add_tail(&x[2], &message);
 96         }
 97 
 98         if (cmd->n_tx) {
 99                 x[3].len = cmd->n_tx;
100                 x[3].tx_buf = cmd->tx_buf;
101                 spi_message_add_tail(&x[3], &message);
102         }
103 
104         if (cmd->n_rx) {
105                 x[3].len = cmd->n_rx;
106                 x[3].rx_buf = cmd->rx_buf;
107                 spi_message_add_tail(&x[3], &message);
108         }
109 
110         return spi_sync(spi, &message);
111 }
112 
113 /*
114  * spinand_read_id- Read SPI Nand ID
115  * Description:
116  *    Read ID: read two ID bytes from the SPI Nand device
117  */
118 static int spinand_read_id(struct spi_device *spi_nand, u8 *id)
119 {
120         int retval;
121         u8 nand_id[3];
122         struct spinand_cmd cmd = {0};
123 
124         cmd.cmd = CMD_READ_ID;
125         cmd.n_rx = 3;
126         cmd.rx_buf = &nand_id[0];
127 
128         retval = spinand_cmd(spi_nand, &cmd);
129         if (retval < 0) {
130                 dev_err(&spi_nand->dev, "error %d reading id\n", retval);
131                 return retval;
132         }
133         id[0] = nand_id[1];
134         id[1] = nand_id[2];
135         return retval;
136 }
137 
138 /*
139  * spinand_read_status- send command 0xf to the SPI Nand status register
140  * Description:
141  *    After read, write, or erase, the Nand device is expected to set the
142  *    busy status.
143  *    This function is to allow reading the status of the command: read,
144  *    write, and erase.
145  *    Once the status turns to be ready, the other status bits also are
146  *    valid status bits.
147  */
148 static int spinand_read_status(struct spi_device *spi_nand, uint8_t *status)
149 {
150         struct spinand_cmd cmd = {0};
151         int ret;
152 
153         cmd.cmd = CMD_READ_REG;
154         cmd.n_addr = 1;
155         cmd.addr[0] = REG_STATUS;
156         cmd.n_rx = 1;
157         cmd.rx_buf = status;
158 
159         ret = spinand_cmd(spi_nand, &cmd);
160         if (ret < 0)
161                 dev_err(&spi_nand->dev, "err: %d read status register\n", ret);
162 
163         return ret;
164 }
165 
166 #define MAX_WAIT_JIFFIES  (40 * HZ)
167 static int wait_till_ready(struct spi_device *spi_nand)
168 {
169         unsigned long deadline;
170         int retval;
171         u8 stat = 0;
172 
173         deadline = jiffies + MAX_WAIT_JIFFIES;
174         do {
175                 retval = spinand_read_status(spi_nand, &stat);
176                 if (retval < 0)
177                         return -1;
178                 else if (!(stat & 0x1))
179                         break;
180 
181                 cond_resched();
182         } while (!time_after_eq(jiffies, deadline));
183 
184         if ((stat & 0x1) == 0)
185                 return 0;
186 
187         return -1;
188 }
189 /**
190  * spinand_get_otp- send command 0xf to read the SPI Nand OTP register
191  * Description:
192  *   There is one bit( bit 0x10 ) to set or to clear the internal ECC.
193  *   Enable chip internal ECC, set the bit to 1
194  *   Disable chip internal ECC, clear the bit to 0
195  */
196 static int spinand_get_otp(struct spi_device *spi_nand, u8 *otp)
197 {
198         struct spinand_cmd cmd = {0};
199         int retval;
200 
201         cmd.cmd = CMD_READ_REG;
202         cmd.n_addr = 1;
203         cmd.addr[0] = REG_OTP;
204         cmd.n_rx = 1;
205         cmd.rx_buf = otp;
206 
207         retval = spinand_cmd(spi_nand, &cmd);
208         if (retval < 0)
209                 dev_err(&spi_nand->dev, "error %d get otp\n", retval);
210         return retval;
211 }
212 
213 /**
214  * spinand_set_otp- send command 0x1f to write the SPI Nand OTP register
215  * Description:
216  *   There is one bit( bit 0x10 ) to set or to clear the internal ECC.
217  *   Enable chip internal ECC, set the bit to 1
218  *   Disable chip internal ECC, clear the bit to 0
219  */
220 static int spinand_set_otp(struct spi_device *spi_nand, u8 *otp)
221 {
222         int retval;
223         struct spinand_cmd cmd = {0};
224 
225         cmd.cmd = CMD_WRITE_REG,
226         cmd.n_addr = 1,
227         cmd.addr[0] = REG_OTP,
228         cmd.n_tx = 1,
229         cmd.tx_buf = otp,
230 
231         retval = spinand_cmd(spi_nand, &cmd);
232         if (retval < 0)
233                 dev_err(&spi_nand->dev, "error %d set otp\n", retval);
234 
235         return retval;
236 }
237 
238 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
239 /**
240  * spinand_enable_ecc- send command 0x1f to write the SPI Nand OTP register
241  * Description:
242  *   There is one bit( bit 0x10 ) to set or to clear the internal ECC.
243  *   Enable chip internal ECC, set the bit to 1
244  *   Disable chip internal ECC, clear the bit to 0
245  */
246 static int spinand_enable_ecc(struct spi_device *spi_nand)
247 {
248         int retval;
249         u8 otp = 0;
250 
251         retval = spinand_get_otp(spi_nand, &otp);
252         if (retval < 0)
253                 return retval;
254 
255         if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) {
256                 return 0;
257         } else {
258                 otp |= OTP_ECC_MASK;
259                 retval = spinand_set_otp(spi_nand, &otp);
260                 if (retval < 0)
261                         return retval;
262                 return spinand_get_otp(spi_nand, &otp);
263         }
264 }
265 #endif
266 
267 static int spinand_disable_ecc(struct spi_device *spi_nand)
268 {
269         int retval;
270         u8 otp = 0;
271 
272         retval = spinand_get_otp(spi_nand, &otp);
273         if (retval < 0)
274                 return retval;
275 
276         if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) {
277                 otp &= ~OTP_ECC_MASK;
278                 retval = spinand_set_otp(spi_nand, &otp);
279                 if (retval < 0)
280                         return retval;
281                 return spinand_get_otp(spi_nand, &otp);
282         } else
283                 return 0;
284 }
285 
286 /**
287  * spinand_write_enable- send command 0x06 to enable write or erase the
288  * Nand cells
289  * Description:
290  *   Before write and erase the Nand cells, the write enable has to be set.
291  *   After the write or erase, the write enable bit is automatically
292  *   cleared (status register bit 2)
293  *   Set the bit 2 of the status register has the same effect
294  */
295 static int spinand_write_enable(struct spi_device *spi_nand)
296 {
297         struct spinand_cmd cmd = {0};
298 
299         cmd.cmd = CMD_WR_ENABLE;
300         return spinand_cmd(spi_nand, &cmd);
301 }
302 
303 static int spinand_read_page_to_cache(struct spi_device *spi_nand, u16 page_id)
304 {
305         struct spinand_cmd cmd = {0};
306         u16 row;
307 
308         row = page_id;
309         cmd.cmd = CMD_READ;
310         cmd.n_addr = 3;
311         cmd.addr[1] = (u8)((row & 0xff00) >> 8);
312         cmd.addr[2] = (u8)(row & 0x00ff);
313 
314         return spinand_cmd(spi_nand, &cmd);
315 }
316 
317 /*
318  * spinand_read_from_cache- send command 0x03 to read out the data from the
319  * cache register(2112 bytes max)
320  * Description:
321  *   The read can specify 1 to 2112 bytes of data read at the corresponding
322  *   locations.
323  *   No tRd delay.
324  */
325 static int spinand_read_from_cache(struct spi_device *spi_nand, u16 page_id,
326                 u16 byte_id, u16 len, u8 *rbuf)
327 {
328         struct spinand_cmd cmd = {0};
329         u16 column;
330 
331         column = byte_id;
332         cmd.cmd = CMD_READ_RDM;
333         cmd.n_addr = 3;
334         cmd.addr[0] = (u8)((column & 0xff00) >> 8);
335         cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
336         cmd.addr[1] = (u8)(column & 0x00ff);
337         cmd.addr[2] = (u8)(0xff);
338         cmd.n_dummy = 0;
339         cmd.n_rx = len;
340         cmd.rx_buf = rbuf;
341 
342         return spinand_cmd(spi_nand, &cmd);
343 }
344 
345 /*
346  * spinand_read_page-to read a page with:
347  * @page_id: the physical page number
348  * @offset:  the location from 0 to 2111
349  * @len:     number of bytes to read
350  * @rbuf:    read buffer to hold @len bytes
351  *
352  * Description:
353  *   The read includes two commands to the Nand: 0x13 and 0x03 commands
354  *   Poll to read status to wait for tRD time.
355  */
356 static int spinand_read_page(struct spi_device *spi_nand, u16 page_id,
357                 u16 offset, u16 len, u8 *rbuf)
358 {
359         int ret;
360         u8 status = 0;
361 
362 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
363         if (enable_read_hw_ecc) {
364                 if (spinand_enable_ecc(spi_nand) < 0)
365                         dev_err(&spi_nand->dev, "enable HW ECC failed!");
366         }
367 #endif
368         ret = spinand_read_page_to_cache(spi_nand, page_id);
369         if (ret < 0)
370                 return ret;
371 
372         if (wait_till_ready(spi_nand))
373                 dev_err(&spi_nand->dev, "WAIT timedout!!!\n");
374 
375         while (1) {
376                 ret = spinand_read_status(spi_nand, &status);
377                 if (ret < 0) {
378                         dev_err(&spi_nand->dev,
379                                         "err %d read status register\n", ret);
380                         return ret;
381                 }
382 
383                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
384                         if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
385                                 dev_err(&spi_nand->dev, "ecc error, page=%d\n",
386                                                 page_id);
387                                 return 0;
388                         }
389                         break;
390                 }
391         }
392 
393         ret = spinand_read_from_cache(spi_nand, page_id, offset, len, rbuf);
394         if (ret < 0) {
395                 dev_err(&spi_nand->dev, "read from cache failed!!\n");
396                 return ret;
397         }
398 
399 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
400         if (enable_read_hw_ecc) {
401                 ret = spinand_disable_ecc(spi_nand);
402                 if (ret < 0) {
403                         dev_err(&spi_nand->dev, "disable ecc failed!!\n");
404                         return ret;
405                 }
406                 enable_read_hw_ecc = 0;
407         }
408 #endif
409         return ret;
410 }
411 
412 /*
413  * spinand_program_data_to_cache--to write a page to cache with:
414  * @byte_id: the location to write to the cache
415  * @len:     number of bytes to write
416  * @rbuf:    read buffer to hold @len bytes
417  *
418  * Description:
419  *   The write command used here is 0x84--indicating that the cache is
420  *   not cleared first.
421  *   Since it is writing the data to cache, there is no tPROG time.
422  */
423 static int spinand_program_data_to_cache(struct spi_device *spi_nand,
424                 u16 page_id, u16 byte_id, u16 len, u8 *wbuf)
425 {
426         struct spinand_cmd cmd = {0};
427         u16 column;
428 
429         column = byte_id;
430         cmd.cmd = CMD_PROG_PAGE_CLRCACHE;
431         cmd.n_addr = 2;
432         cmd.addr[0] = (u8)((column & 0xff00) >> 8);
433         cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
434         cmd.addr[1] = (u8)(column & 0x00ff);
435         cmd.n_tx = len;
436         cmd.tx_buf = wbuf;
437 
438         return spinand_cmd(spi_nand, &cmd);
439 }
440 
441 /**
442  * spinand_program_execute--to write a page from cache to the Nand array with
443  * @page_id: the physical page location to write the page.
444  *
445  * Description:
446  *   The write command used here is 0x10--indicating the cache is writing to
447  *   the Nand array.
448  *   Need to wait for tPROG time to finish the transaction.
449  */
450 static int spinand_program_execute(struct spi_device *spi_nand, u16 page_id)
451 {
452         struct spinand_cmd cmd = {0};
453         u16 row;
454 
455         row = page_id;
456         cmd.cmd = CMD_PROG_PAGE_EXC;
457         cmd.n_addr = 3;
458         cmd.addr[1] = (u8)((row & 0xff00) >> 8);
459         cmd.addr[2] = (u8)(row & 0x00ff);
460 
461         return spinand_cmd(spi_nand, &cmd);
462 }
463 
464 /**
465  * spinand_program_page--to write a page with:
466  * @page_id: the physical page location to write the page.
467  * @offset:  the location from the cache starting from 0 to 2111
468  * @len:     the number of bytes to write
469  * @wbuf:    the buffer to hold the number of bytes
470  *
471  * Description:
472  *   The commands used here are 0x06, 0x84, and 0x10--indicating that
473  *   the write enable is first sent, the write cache command, and the
474  *   write execute command.
475  *   Poll to wait for the tPROG time to finish the transaction.
476  */
477 static int spinand_program_page(struct spi_device *spi_nand,
478                 u16 page_id, u16 offset, u16 len, u8 *buf)
479 {
480         int retval;
481         u8 status = 0;
482         uint8_t *wbuf;
483 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
484         unsigned int i, j;
485 
486         enable_read_hw_ecc = 0;
487         wbuf = devm_kzalloc(&spi_nand->dev, CACHE_BUF, GFP_KERNEL);
488         spinand_read_page(spi_nand, page_id, 0, CACHE_BUF, wbuf);
489 
490         for (i = offset, j = 0; i < len; i++, j++)
491                 wbuf[i] &= buf[j];
492 
493         if (enable_hw_ecc) {
494                 retval = spinand_enable_ecc(spi_nand);
495                 if (retval < 0) {
496                         dev_err(&spi_nand->dev, "enable ecc failed!!\n");
497                         return retval;
498                 }
499         }
500 #else
501         wbuf = buf;
502 #endif
503         retval = spinand_write_enable(spi_nand);
504         if (retval < 0) {
505                 dev_err(&spi_nand->dev, "write enable failed!!\n");
506                 return retval;
507         }
508         if (wait_till_ready(spi_nand))
509                 dev_err(&spi_nand->dev, "wait timedout!!!\n");
510 
511         retval = spinand_program_data_to_cache(spi_nand, page_id,
512                         offset, len, wbuf);
513         if (retval < 0)
514                 return retval;
515         retval = spinand_program_execute(spi_nand, page_id);
516         if (retval < 0)
517                 return retval;
518         while (1) {
519                 retval = spinand_read_status(spi_nand, &status);
520                 if (retval < 0) {
521                         dev_err(&spi_nand->dev,
522                                         "error %d reading status register\n",
523                                         retval);
524                         return retval;
525                 }
526 
527                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
528                         if ((status & STATUS_P_FAIL_MASK) == STATUS_P_FAIL) {
529                                 dev_err(&spi_nand->dev,
530                                         "program error, page %d\n", page_id);
531                                 return -1;
532                         } else
533                                 break;
534                 }
535         }
536 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
537         if (enable_hw_ecc) {
538                 retval = spinand_disable_ecc(spi_nand);
539                 if (retval < 0) {
540                         dev_err(&spi_nand->dev, "disable ecc failed!!\n");
541                         return retval;
542                 }
543                 enable_hw_ecc = 0;
544         }
545 #endif
546 
547         return 0;
548 }
549 
550 /**
551  * spinand_erase_block_erase--to erase a page with:
552  * @block_id: the physical block location to erase.
553  *
554  * Description:
555  *   The command used here is 0xd8--indicating an erase command to erase
556  *   one block--64 pages
557  *   Need to wait for tERS.
558  */
559 static int spinand_erase_block_erase(struct spi_device *spi_nand, u16 block_id)
560 {
561         struct spinand_cmd cmd = {0};
562         u16 row;
563 
564         row = block_id;
565         cmd.cmd = CMD_ERASE_BLK;
566         cmd.n_addr = 3;
567         cmd.addr[1] = (u8)((row & 0xff00) >> 8);
568         cmd.addr[2] = (u8)(row & 0x00ff);
569 
570         return spinand_cmd(spi_nand, &cmd);
571 }
572 
573 /**
574  * spinand_erase_block--to erase a page with:
575  * @block_id: the physical block location to erase.
576  *
577  * Description:
578  *   The commands used here are 0x06 and 0xd8--indicating an erase
579  *   command to erase one block--64 pages
580  *   It will first to enable the write enable bit (0x06 command),
581  *   and then send the 0xd8 erase command
582  *   Poll to wait for the tERS time to complete the tranaction.
583  */
584 static int spinand_erase_block(struct spi_device *spi_nand, u16 block_id)
585 {
586         int retval;
587         u8 status = 0;
588 
589         retval = spinand_write_enable(spi_nand);
590         if (wait_till_ready(spi_nand))
591                 dev_err(&spi_nand->dev, "wait timedout!!!\n");
592 
593         retval = spinand_erase_block_erase(spi_nand, block_id);
594         while (1) {
595                 retval = spinand_read_status(spi_nand, &status);
596                 if (retval < 0) {
597                         dev_err(&spi_nand->dev,
598                                         "error %d reading status register\n",
599                                         (int) retval);
600                         return retval;
601                 }
602 
603                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
604                         if ((status & STATUS_E_FAIL_MASK) == STATUS_E_FAIL) {
605                                 dev_err(&spi_nand->dev,
606                                         "erase error, block %d\n", block_id);
607                                 return -1;
608                         } else
609                                 break;
610                 }
611         }
612         return 0;
613 }
614 
615 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
616 static int spinand_write_page_hwecc(struct mtd_info *mtd,
617                 struct nand_chip *chip, const uint8_t *buf, int oob_required)
618 {
619         const uint8_t *p = buf;
620         int eccsize = chip->ecc.size;
621         int eccsteps = chip->ecc.steps;
622 
623         enable_hw_ecc = 1;
624         chip->write_buf(mtd, p, eccsize * eccsteps);
625         return 0;
626 }
627 
628 static int spinand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
629                 uint8_t *buf, int oob_required, int page)
630 {
631         u8 retval, status;
632         uint8_t *p = buf;
633         int eccsize = chip->ecc.size;
634         int eccsteps = chip->ecc.steps;
635         struct spinand_info *info = (struct spinand_info *)chip->priv;
636 
637         enable_read_hw_ecc = 1;
638 
639         chip->read_buf(mtd, p, eccsize * eccsteps);
640         if (oob_required)
641                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
642 
643         while (1) {
644                 retval = spinand_read_status(info->spi, &status);
645                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
646                         if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
647                                 pr_info("spinand: ECC error\n");
648                                 mtd->ecc_stats.failed++;
649                         } else if ((status & STATUS_ECC_MASK) ==
650                                         STATUS_ECC_1BIT_CORRECTED)
651                                 mtd->ecc_stats.corrected++;
652                         break;
653                 }
654         }
655         return 0;
656 
657 }
658 #endif
659 
660 static void spinand_select_chip(struct mtd_info *mtd, int dev)
661 {
662 }
663 
664 static uint8_t spinand_read_byte(struct mtd_info *mtd)
665 {
666         struct spinand_state *state = mtd_to_state(mtd);
667         u8 data;
668 
669         data = state->buf[state->buf_ptr];
670         state->buf_ptr++;
671         return data;
672 }
673 
674 
675 static int spinand_wait(struct mtd_info *mtd, struct nand_chip *chip)
676 {
677         struct spinand_info *info = (struct spinand_info *)chip->priv;
678 
679         unsigned long timeo = jiffies;
680         int retval, state = chip->state;
681         u8 status;
682 
683         if (state == FL_ERASING)
684                 timeo += (HZ * 400) / 1000;
685         else
686                 timeo += (HZ * 20) / 1000;
687 
688         while (time_before(jiffies, timeo)) {
689                 retval = spinand_read_status(info->spi, &status);
690                 if ((status & STATUS_OIP_MASK) == STATUS_READY)
691                         return 0;
692 
693                 cond_resched();
694         }
695         return 0;
696 }
697 
698 static void spinand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
699 {
700 
701         struct spinand_state *state = mtd_to_state(mtd);
702         memcpy(state->buf + state->buf_ptr, buf, len);
703         state->buf_ptr += len;
704 }
705 
706 static void spinand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
707 {
708         struct spinand_state *state = mtd_to_state(mtd);
709         memcpy(buf, state->buf + state->buf_ptr, len);
710         state->buf_ptr += len;
711 }
712 
713 /*
714  * spinand_reset- send RESET command "0xff" to the Nand device.
715  */
716 static void spinand_reset(struct spi_device *spi_nand)
717 {
718         struct spinand_cmd cmd = {0};
719 
720         cmd.cmd = CMD_RESET;
721 
722         if (spinand_cmd(spi_nand, &cmd) < 0)
723                 pr_info("spinand reset failed!\n");
724 
725         /* elapse 1ms before issuing any other command */
726         udelay(1000);
727 
728         if (wait_till_ready(spi_nand))
729                 dev_err(&spi_nand->dev, "wait timedout!\n");
730 }
731 
732 static void spinand_cmdfunc(struct mtd_info *mtd, unsigned int command,
733                 int column, int page)
734 {
735         struct nand_chip *chip = (struct nand_chip *)mtd->priv;
736         struct spinand_info *info = (struct spinand_info *)chip->priv;
737         struct spinand_state *state = (struct spinand_state *)info->priv;
738 
739         switch (command) {
740         /*
741          * READ0 - read in first  0x800 bytes
742          */
743         case NAND_CMD_READ1:
744         case NAND_CMD_READ0:
745                 state->buf_ptr = 0;
746                 spinand_read_page(info->spi, page, 0x0, 0x840, state->buf);
747                 break;
748         /* READOOB reads only the OOB because no ECC is performed. */
749         case NAND_CMD_READOOB:
750                 state->buf_ptr = 0;
751                 spinand_read_page(info->spi, page, 0x800, 0x40, state->buf);
752                 break;
753         case NAND_CMD_RNDOUT:
754                 state->buf_ptr = column;
755                 break;
756         case NAND_CMD_READID:
757                 state->buf_ptr = 0;
758                 spinand_read_id(info->spi, (u8 *)state->buf);
759                 break;
760         case NAND_CMD_PARAM:
761                 state->buf_ptr = 0;
762                 break;
763         /* ERASE1 stores the block and page address */
764         case NAND_CMD_ERASE1:
765                 spinand_erase_block(info->spi, page);
766                 break;
767         /* ERASE2 uses the block and page address from ERASE1 */
768         case NAND_CMD_ERASE2:
769                 break;
770         /* SEQIN sets up the addr buffer and all registers except the length */
771         case NAND_CMD_SEQIN:
772                 state->col = column;
773                 state->row = page;
774                 state->buf_ptr = 0;
775                 break;
776         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
777         case NAND_CMD_PAGEPROG:
778                 spinand_program_page(info->spi, state->row, state->col,
779                                 state->buf_ptr, state->buf);
780                 break;
781         case NAND_CMD_STATUS:
782                 spinand_get_otp(info->spi, state->buf);
783                 if (!(state->buf[0] & 0x80))
784                         state->buf[0] = 0x80;
785                 state->buf_ptr = 0;
786                 break;
787         /* RESET command */
788         case NAND_CMD_RESET:
789                 if (wait_till_ready(info->spi))
790                         dev_err(&info->spi->dev, "WAIT timedout!!!\n");
791                 /* a minimum of 250us must elapse before issuing RESET cmd*/
792                 udelay(250);
793                 spinand_reset(info->spi);
794                 break;
795         default:
796                 dev_err(&mtd->dev, "Unknown CMD: 0x%x\n", command);
797         }
798 }
799 
800 /**
801  * spinand_lock_block- send write register 0x1f command to the Nand device
802  *
803  * Description:
804  *    After power up, all the Nand blocks are locked.  This function allows
805  *    one to unlock the blocks, and so it can be written or erased.
806  */
807 static int spinand_lock_block(struct spi_device *spi_nand, u8 lock)
808 {
809         struct spinand_cmd cmd = {0};
810         int ret;
811         u8 otp = 0;
812 
813         ret = spinand_get_otp(spi_nand, &otp);
814 
815         cmd.cmd = CMD_WRITE_REG;
816         cmd.n_addr = 1;
817         cmd.addr[0] = REG_BLOCK_LOCK;
818         cmd.n_tx = 1;
819         cmd.tx_buf = &lock;
820 
821         ret = spinand_cmd(spi_nand, &cmd);
822         if (ret < 0)
823                 dev_err(&spi_nand->dev, "error %d lock block\n", ret);
824 
825         return ret;
826 }
827 /*
828  * spinand_probe - [spinand Interface]
829  * @spi_nand: registered device driver.
830  *
831  * Description:
832  *   To set up the device driver parameters to make the device available.
833  */
834 static int spinand_probe(struct spi_device *spi_nand)
835 {
836         struct mtd_info *mtd;
837         struct nand_chip *chip;
838         struct spinand_info *info;
839         struct spinand_state *state;
840         struct mtd_part_parser_data ppdata;
841 
842         info  = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_info),
843                         GFP_KERNEL);
844         if (!info)
845                 return -ENOMEM;
846 
847         info->spi = spi_nand;
848 
849         spinand_lock_block(spi_nand, BL_ALL_UNLOCKED);
850 
851         state = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_state),
852                         GFP_KERNEL);
853         if (!state)
854                 return -ENOMEM;
855 
856         info->priv      = state;
857         state->buf_ptr  = 0;
858         state->buf      = devm_kzalloc(&spi_nand->dev, BUFSIZE, GFP_KERNEL);
859         if (!state->buf)
860                 return -ENOMEM;
861 
862         chip = devm_kzalloc(&spi_nand->dev, sizeof(struct nand_chip),
863                         GFP_KERNEL);
864         if (!chip)
865                 return -ENOMEM;
866 
867 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
868         chip->ecc.mode  = NAND_ECC_HW;
869         chip->ecc.size  = 0x200;
870         chip->ecc.bytes = 0x6;
871         chip->ecc.steps = 0x4;
872 
873         chip->ecc.strength = 1;
874         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
875         chip->ecc.layout = &spinand_oob_64;
876         chip->ecc.read_page = spinand_read_page_hwecc;
877         chip->ecc.write_page = spinand_write_page_hwecc;
878 #else
879         chip->ecc.mode  = NAND_ECC_SOFT;
880         if (spinand_disable_ecc(spi_nand) < 0)
881                 pr_info("%s: disable ecc failed!\n", __func__);
882 #endif
883 
884         chip->priv      = info;
885         chip->read_buf  = spinand_read_buf;
886         chip->write_buf = spinand_write_buf;
887         chip->read_byte = spinand_read_byte;
888         chip->cmdfunc   = spinand_cmdfunc;
889         chip->waitfunc  = spinand_wait;
890         chip->options   |= NAND_CACHEPRG;
891         chip->select_chip = spinand_select_chip;
892 
893         mtd = devm_kzalloc(&spi_nand->dev, sizeof(struct mtd_info), GFP_KERNEL);
894         if (!mtd)
895                 return -ENOMEM;
896 
897         dev_set_drvdata(&spi_nand->dev, mtd);
898 
899         mtd->priv = chip;
900         mtd->name = dev_name(&spi_nand->dev);
901         mtd->owner = THIS_MODULE;
902         mtd->oobsize = 64;
903 
904         if (nand_scan(mtd, 1))
905                 return -ENXIO;
906 
907         ppdata.of_node = spi_nand->dev.of_node;
908         return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
909 }
910 
911 /*
912  * spinand_remove: Remove the device driver
913  * @spi: the spi device.
914  *
915  * Description:
916  *   To remove the device driver parameters and free up allocated memories.
917  */
918 static int spinand_remove(struct spi_device *spi)
919 {
920         mtd_device_unregister(dev_get_drvdata(&spi->dev));
921 
922         return 0;
923 }
924 
925 static const struct of_device_id spinand_dt[] = {
926         { .compatible = "spinand,mt29f", },
927 };
928 
929 /*
930  * Device name structure description
931  */
932 static struct spi_driver spinand_driver = {
933         .driver = {
934                 .name           = "mt29f",
935                 .bus            = &spi_bus_type,
936                 .owner          = THIS_MODULE,
937                 .of_match_table = spinand_dt,
938         },
939         .probe          = spinand_probe,
940         .remove         = spinand_remove,
941 };
942 
943 module_spi_driver(spinand_driver);
944 
945 MODULE_DESCRIPTION("SPI NAND driver for Micron");
946 MODULE_AUTHOR("Henry Pan <hspan@micron.com>, Kamlakant Patel <kamlakant.patel@broadcom.com>");
947 MODULE_LICENSE("GPL v2");
948 

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