Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4

Linux/drivers/staging/mt29f_spinand/mt29f_spinand.c

  1 /*
  2  * Copyright (c) 2003-2013 Broadcom Corporation
  3  *
  4  * Copyright (c) 2009-2010 Micron Technology, Inc.
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License
  8  * as published by the Free Software Foundation; either version 2
  9  * of the License, or (at your option) any later version.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  */
 16 
 17 #include <linux/module.h>
 18 #include <linux/delay.h>
 19 #include <linux/mtd/mtd.h>
 20 #include <linux/mtd/partitions.h>
 21 #include <linux/mtd/nand.h>
 22 #include <linux/spi/spi.h>
 23 
 24 #include "mt29f_spinand.h"
 25 
 26 #define BUFSIZE (10 * 64 * 2048)
 27 #define CACHE_BUF 2112
 28 /*
 29  * OOB area specification layout:  Total 32 available free bytes.
 30  */
 31 
 32 static inline struct spinand_state *mtd_to_state(struct mtd_info *mtd)
 33 {
 34         struct nand_chip *chip = (struct nand_chip *)mtd->priv;
 35         struct spinand_info *info = (struct spinand_info *)chip->priv;
 36         struct spinand_state *state = (struct spinand_state *)info->priv;
 37 
 38         return state;
 39 }
 40 
 41 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 42 static int enable_hw_ecc;
 43 static int enable_read_hw_ecc;
 44 
 45 static struct nand_ecclayout spinand_oob_64 = {
 46         .eccbytes = 24,
 47         .eccpos = {
 48                 1, 2, 3, 4, 5, 6,
 49                 17, 18, 19, 20, 21, 22,
 50                 33, 34, 35, 36, 37, 38,
 51                 49, 50, 51, 52, 53, 54, },
 52         .oobavail = 32,
 53         .oobfree = {
 54                 {.offset = 8,
 55                         .length = 8},
 56                 {.offset = 24,
 57                         .length = 8},
 58                 {.offset = 40,
 59                         .length = 8},
 60                 {.offset = 56,
 61                         .length = 8},
 62         }
 63 };
 64 #endif
 65 
 66 /*
 67  * spinand_cmd - to process a command to send to the SPI Nand
 68  * Description:
 69  *    Set up the command buffer to send to the SPI controller.
 70  *    The command buffer has to initialized to 0.
 71  */
 72 
 73 static int spinand_cmd(struct spi_device *spi, struct spinand_cmd *cmd)
 74 {
 75         struct spi_message message;
 76         struct spi_transfer x[4];
 77         u8 dummy = 0xff;
 78 
 79         spi_message_init(&message);
 80         memset(x, 0, sizeof(x));
 81 
 82         x[0].len = 1;
 83         x[0].tx_buf = &cmd->cmd;
 84         spi_message_add_tail(&x[0], &message);
 85 
 86         if (cmd->n_addr) {
 87                 x[1].len = cmd->n_addr;
 88                 x[1].tx_buf = cmd->addr;
 89                 spi_message_add_tail(&x[1], &message);
 90         }
 91 
 92         if (cmd->n_dummy) {
 93                 x[2].len = cmd->n_dummy;
 94                 x[2].tx_buf = &dummy;
 95                 spi_message_add_tail(&x[2], &message);
 96         }
 97 
 98         if (cmd->n_tx) {
 99                 x[3].len = cmd->n_tx;
100                 x[3].tx_buf = cmd->tx_buf;
101                 spi_message_add_tail(&x[3], &message);
102         }
103 
104         if (cmd->n_rx) {
105                 x[3].len = cmd->n_rx;
106                 x[3].rx_buf = cmd->rx_buf;
107                 spi_message_add_tail(&x[3], &message);
108         }
109 
110         return spi_sync(spi, &message);
111 }
112 
113 /*
114  * spinand_read_id- Read SPI Nand ID
115  * Description:
116  *    Read ID: read two ID bytes from the SPI Nand device
117  */
118 static int spinand_read_id(struct spi_device *spi_nand, u8 *id)
119 {
120         int retval;
121         u8 nand_id[3];
122         struct spinand_cmd cmd = {0};
123 
124         cmd.cmd = CMD_READ_ID;
125         cmd.n_rx = 3;
126         cmd.rx_buf = &nand_id[0];
127 
128         retval = spinand_cmd(spi_nand, &cmd);
129         if (retval < 0) {
130                 dev_err(&spi_nand->dev, "error %d reading id\n", retval);
131                 return retval;
132         }
133         id[0] = nand_id[1];
134         id[1] = nand_id[2];
135         return retval;
136 }
137 
138 /*
139  * spinand_read_status- send command 0xf to the SPI Nand status register
140  * Description:
141  *    After read, write, or erase, the Nand device is expected to set the
142  *    busy status.
143  *    This function is to allow reading the status of the command: read,
144  *    write, and erase.
145  *    Once the status turns to be ready, the other status bits also are
146  *    valid status bits.
147  */
148 static int spinand_read_status(struct spi_device *spi_nand, u8 *status)
149 {
150         struct spinand_cmd cmd = {0};
151         int ret;
152 
153         cmd.cmd = CMD_READ_REG;
154         cmd.n_addr = 1;
155         cmd.addr[0] = REG_STATUS;
156         cmd.n_rx = 1;
157         cmd.rx_buf = status;
158 
159         ret = spinand_cmd(spi_nand, &cmd);
160         if (ret < 0)
161                 dev_err(&spi_nand->dev, "err: %d read status register\n", ret);
162 
163         return ret;
164 }
165 
166 #define MAX_WAIT_JIFFIES  (40 * HZ)
167 static int wait_till_ready(struct spi_device *spi_nand)
168 {
169         unsigned long deadline;
170         int retval;
171         u8 stat = 0;
172 
173         deadline = jiffies + MAX_WAIT_JIFFIES;
174         do {
175                 retval = spinand_read_status(spi_nand, &stat);
176                 if (retval < 0)
177                         return -1;
178                 else if (!(stat & 0x1))
179                         break;
180 
181                 cond_resched();
182         } while (!time_after_eq(jiffies, deadline));
183 
184         if ((stat & 0x1) == 0)
185                 return 0;
186 
187         return -1;
188 }
189 
190 /**
191  * spinand_get_otp- send command 0xf to read the SPI Nand OTP register
192  * Description:
193  *   There is one bit( bit 0x10 ) to set or to clear the internal ECC.
194  *   Enable chip internal ECC, set the bit to 1
195  *   Disable chip internal ECC, clear the bit to 0
196  */
197 static int spinand_get_otp(struct spi_device *spi_nand, u8 *otp)
198 {
199         struct spinand_cmd cmd = {0};
200         int retval;
201 
202         cmd.cmd = CMD_READ_REG;
203         cmd.n_addr = 1;
204         cmd.addr[0] = REG_OTP;
205         cmd.n_rx = 1;
206         cmd.rx_buf = otp;
207 
208         retval = spinand_cmd(spi_nand, &cmd);
209         if (retval < 0)
210                 dev_err(&spi_nand->dev, "error %d get otp\n", retval);
211         return retval;
212 }
213 
214 /**
215  * spinand_set_otp- send command 0x1f to write the SPI Nand OTP register
216  * Description:
217  *   There is one bit( bit 0x10 ) to set or to clear the internal ECC.
218  *   Enable chip internal ECC, set the bit to 1
219  *   Disable chip internal ECC, clear the bit to 0
220  */
221 static int spinand_set_otp(struct spi_device *spi_nand, u8 *otp)
222 {
223         int retval;
224         struct spinand_cmd cmd = {0};
225 
226         cmd.cmd = CMD_WRITE_REG,
227         cmd.n_addr = 1,
228         cmd.addr[0] = REG_OTP,
229         cmd.n_tx = 1,
230         cmd.tx_buf = otp,
231 
232         retval = spinand_cmd(spi_nand, &cmd);
233         if (retval < 0)
234                 dev_err(&spi_nand->dev, "error %d set otp\n", retval);
235 
236         return retval;
237 }
238 
239 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
240 /**
241  * spinand_enable_ecc- send command 0x1f to write the SPI Nand OTP register
242  * Description:
243  *   There is one bit( bit 0x10 ) to set or to clear the internal ECC.
244  *   Enable chip internal ECC, set the bit to 1
245  *   Disable chip internal ECC, clear the bit to 0
246  */
247 static int spinand_enable_ecc(struct spi_device *spi_nand)
248 {
249         int retval;
250         u8 otp = 0;
251 
252         retval = spinand_get_otp(spi_nand, &otp);
253         if (retval < 0)
254                 return retval;
255 
256         if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK)
257                 return 0;
258         otp |= OTP_ECC_MASK;
259         retval = spinand_set_otp(spi_nand, &otp);
260         if (retval < 0)
261                 return retval;
262         return spinand_get_otp(spi_nand, &otp);
263 }
264 #endif
265 
266 static int spinand_disable_ecc(struct spi_device *spi_nand)
267 {
268         int retval;
269         u8 otp = 0;
270 
271         retval = spinand_get_otp(spi_nand, &otp);
272         if (retval < 0)
273                 return retval;
274 
275         if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) {
276                 otp &= ~OTP_ECC_MASK;
277                 retval = spinand_set_otp(spi_nand, &otp);
278                 if (retval < 0)
279                         return retval;
280                 return spinand_get_otp(spi_nand, &otp);
281         }
282         return 0;
283 }
284 
285 /**
286  * spinand_write_enable- send command 0x06 to enable write or erase the
287  * Nand cells
288  * Description:
289  *   Before write and erase the Nand cells, the write enable has to be set.
290  *   After the write or erase, the write enable bit is automatically
291  *   cleared (status register bit 2)
292  *   Set the bit 2 of the status register has the same effect
293  */
294 static int spinand_write_enable(struct spi_device *spi_nand)
295 {
296         struct spinand_cmd cmd = {0};
297 
298         cmd.cmd = CMD_WR_ENABLE;
299         return spinand_cmd(spi_nand, &cmd);
300 }
301 
302 static int spinand_read_page_to_cache(struct spi_device *spi_nand, u16 page_id)
303 {
304         struct spinand_cmd cmd = {0};
305         u16 row;
306 
307         row = page_id;
308         cmd.cmd = CMD_READ;
309         cmd.n_addr = 3;
310         cmd.addr[1] = (u8)((row & 0xff00) >> 8);
311         cmd.addr[2] = (u8)(row & 0x00ff);
312 
313         return spinand_cmd(spi_nand, &cmd);
314 }
315 
316 /*
317  * spinand_read_from_cache- send command 0x03 to read out the data from the
318  * cache register(2112 bytes max)
319  * Description:
320  *   The read can specify 1 to 2112 bytes of data read at the corresponding
321  *   locations.
322  *   No tRd delay.
323  */
324 static int spinand_read_from_cache(struct spi_device *spi_nand, u16 page_id,
325                                    u16 byte_id, u16 len, u8 *rbuf)
326 {
327         struct spinand_cmd cmd = {0};
328         u16 column;
329 
330         column = byte_id;
331         cmd.cmd = CMD_READ_RDM;
332         cmd.n_addr = 3;
333         cmd.addr[0] = (u8)((column & 0xff00) >> 8);
334         cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
335         cmd.addr[1] = (u8)(column & 0x00ff);
336         cmd.addr[2] = (u8)(0xff);
337         cmd.n_dummy = 0;
338         cmd.n_rx = len;
339         cmd.rx_buf = rbuf;
340 
341         return spinand_cmd(spi_nand, &cmd);
342 }
343 
344 /*
345  * spinand_read_page-to read a page with:
346  * @page_id: the physical page number
347  * @offset:  the location from 0 to 2111
348  * @len:     number of bytes to read
349  * @rbuf:    read buffer to hold @len bytes
350  *
351  * Description:
352  *   The read includes two commands to the Nand: 0x13 and 0x03 commands
353  *   Poll to read status to wait for tRD time.
354  */
355 static int spinand_read_page(struct spi_device *spi_nand, u16 page_id,
356                              u16 offset, u16 len, u8 *rbuf)
357 {
358         int ret;
359         u8 status = 0;
360 
361 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
362         if (enable_read_hw_ecc) {
363                 if (spinand_enable_ecc(spi_nand) < 0)
364                         dev_err(&spi_nand->dev, "enable HW ECC failed!");
365         }
366 #endif
367         ret = spinand_read_page_to_cache(spi_nand, page_id);
368         if (ret < 0)
369                 return ret;
370 
371         if (wait_till_ready(spi_nand))
372                 dev_err(&spi_nand->dev, "WAIT timedout!!!\n");
373 
374         while (1) {
375                 ret = spinand_read_status(spi_nand, &status);
376                 if (ret < 0) {
377                         dev_err(&spi_nand->dev,
378                                 "err %d read status register\n", ret);
379                         return ret;
380                 }
381 
382                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
383                         if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
384                                 dev_err(&spi_nand->dev, "ecc error, page=%d\n",
385                                         page_id);
386                                 return 0;
387                         }
388                         break;
389                 }
390         }
391 
392         ret = spinand_read_from_cache(spi_nand, page_id, offset, len, rbuf);
393         if (ret < 0) {
394                 dev_err(&spi_nand->dev, "read from cache failed!!\n");
395                 return ret;
396         }
397 
398 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
399         if (enable_read_hw_ecc) {
400                 ret = spinand_disable_ecc(spi_nand);
401                 if (ret < 0) {
402                         dev_err(&spi_nand->dev, "disable ecc failed!!\n");
403                         return ret;
404                 }
405                 enable_read_hw_ecc = 0;
406         }
407 #endif
408         return ret;
409 }
410 
411 /*
412  * spinand_program_data_to_cache--to write a page to cache with:
413  * @byte_id: the location to write to the cache
414  * @len:     number of bytes to write
415  * @rbuf:    read buffer to hold @len bytes
416  *
417  * Description:
418  *   The write command used here is 0x84--indicating that the cache is
419  *   not cleared first.
420  *   Since it is writing the data to cache, there is no tPROG time.
421  */
422 static int spinand_program_data_to_cache(struct spi_device *spi_nand,
423                                          u16 page_id, u16 byte_id,
424                                          u16 len, u8 *wbuf)
425 {
426         struct spinand_cmd cmd = {0};
427         u16 column;
428 
429         column = byte_id;
430         cmd.cmd = CMD_PROG_PAGE_CLRCACHE;
431         cmd.n_addr = 2;
432         cmd.addr[0] = (u8)((column & 0xff00) >> 8);
433         cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
434         cmd.addr[1] = (u8)(column & 0x00ff);
435         cmd.n_tx = len;
436         cmd.tx_buf = wbuf;
437 
438         return spinand_cmd(spi_nand, &cmd);
439 }
440 
441 /**
442  * spinand_program_execute--to write a page from cache to the Nand array with
443  * @page_id: the physical page location to write the page.
444  *
445  * Description:
446  *   The write command used here is 0x10--indicating the cache is writing to
447  *   the Nand array.
448  *   Need to wait for tPROG time to finish the transaction.
449  */
450 static int spinand_program_execute(struct spi_device *spi_nand, u16 page_id)
451 {
452         struct spinand_cmd cmd = {0};
453         u16 row;
454 
455         row = page_id;
456         cmd.cmd = CMD_PROG_PAGE_EXC;
457         cmd.n_addr = 3;
458         cmd.addr[1] = (u8)((row & 0xff00) >> 8);
459         cmd.addr[2] = (u8)(row & 0x00ff);
460 
461         return spinand_cmd(spi_nand, &cmd);
462 }
463 
464 /**
465  * spinand_program_page--to write a page with:
466  * @page_id: the physical page location to write the page.
467  * @offset:  the location from the cache starting from 0 to 2111
468  * @len:     the number of bytes to write
469  * @wbuf:    the buffer to hold the number of bytes
470  *
471  * Description:
472  *   The commands used here are 0x06, 0x84, and 0x10--indicating that
473  *   the write enable is first sent, the write cache command, and the
474  *   write execute command.
475  *   Poll to wait for the tPROG time to finish the transaction.
476  */
477 static int spinand_program_page(struct spi_device *spi_nand,
478                                 u16 page_id, u16 offset, u16 len, u8 *buf)
479 {
480         int retval;
481         u8 status = 0;
482         u8 *wbuf;
483 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
484         unsigned int i, j;
485 
486         enable_read_hw_ecc = 0;
487         wbuf = devm_kzalloc(&spi_nand->dev, CACHE_BUF, GFP_KERNEL);
488         spinand_read_page(spi_nand, page_id, 0, CACHE_BUF, wbuf);
489 
490         for (i = offset, j = 0; i < len; i++, j++)
491                 wbuf[i] &= buf[j];
492 
493         if (enable_hw_ecc) {
494                 retval = spinand_enable_ecc(spi_nand);
495                 if (retval < 0) {
496                         dev_err(&spi_nand->dev, "enable ecc failed!!\n");
497                         return retval;
498                 }
499         }
500 #else
501         wbuf = buf;
502 #endif
503         retval = spinand_write_enable(spi_nand);
504         if (retval < 0) {
505                 dev_err(&spi_nand->dev, "write enable failed!!\n");
506                 return retval;
507         }
508         if (wait_till_ready(spi_nand))
509                 dev_err(&spi_nand->dev, "wait timedout!!!\n");
510 
511         retval = spinand_program_data_to_cache(spi_nand, page_id,
512                                                offset, len, wbuf);
513         if (retval < 0)
514                 return retval;
515         retval = spinand_program_execute(spi_nand, page_id);
516         if (retval < 0)
517                 return retval;
518         while (1) {
519                 retval = spinand_read_status(spi_nand, &status);
520                 if (retval < 0) {
521                         dev_err(&spi_nand->dev,
522                                 "error %d reading status register\n", retval);
523                         return retval;
524                 }
525 
526                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
527                         if ((status & STATUS_P_FAIL_MASK) == STATUS_P_FAIL) {
528                                 dev_err(&spi_nand->dev,
529                                         "program error, page %d\n", page_id);
530                                 return -1;
531                         }
532                         break;
533                 }
534         }
535 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
536         if (enable_hw_ecc) {
537                 retval = spinand_disable_ecc(spi_nand);
538                 if (retval < 0) {
539                         dev_err(&spi_nand->dev, "disable ecc failed!!\n");
540                         return retval;
541                 }
542                 enable_hw_ecc = 0;
543         }
544 #endif
545 
546         return 0;
547 }
548 
549 /**
550  * spinand_erase_block_erase--to erase a page with:
551  * @block_id: the physical block location to erase.
552  *
553  * Description:
554  *   The command used here is 0xd8--indicating an erase command to erase
555  *   one block--64 pages
556  *   Need to wait for tERS.
557  */
558 static int spinand_erase_block_erase(struct spi_device *spi_nand, u16 block_id)
559 {
560         struct spinand_cmd cmd = {0};
561         u16 row;
562 
563         row = block_id;
564         cmd.cmd = CMD_ERASE_BLK;
565         cmd.n_addr = 3;
566         cmd.addr[1] = (u8)((row & 0xff00) >> 8);
567         cmd.addr[2] = (u8)(row & 0x00ff);
568 
569         return spinand_cmd(spi_nand, &cmd);
570 }
571 
572 /**
573  * spinand_erase_block--to erase a page with:
574  * @block_id: the physical block location to erase.
575  *
576  * Description:
577  *   The commands used here are 0x06 and 0xd8--indicating an erase
578  *   command to erase one block--64 pages
579  *   It will first to enable the write enable bit (0x06 command),
580  *   and then send the 0xd8 erase command
581  *   Poll to wait for the tERS time to complete the tranaction.
582  */
583 static int spinand_erase_block(struct spi_device *spi_nand, u16 block_id)
584 {
585         int retval;
586         u8 status = 0;
587 
588         retval = spinand_write_enable(spi_nand);
589         if (wait_till_ready(spi_nand))
590                 dev_err(&spi_nand->dev, "wait timedout!!!\n");
591 
592         retval = spinand_erase_block_erase(spi_nand, block_id);
593         while (1) {
594                 retval = spinand_read_status(spi_nand, &status);
595                 if (retval < 0) {
596                         dev_err(&spi_nand->dev,
597                                 "error %d reading status register\n", retval);
598                         return retval;
599                 }
600 
601                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
602                         if ((status & STATUS_E_FAIL_MASK) == STATUS_E_FAIL) {
603                                 dev_err(&spi_nand->dev,
604                                         "erase error, block %d\n", block_id);
605                                 return -1;
606                         }
607                         break;
608                 }
609         }
610         return 0;
611 }
612 
613 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
614 static int spinand_write_page_hwecc(struct mtd_info *mtd,
615                                     struct nand_chip *chip,
616                                     const u8 *buf, int oob_required,
617                                     int page)
618 {
619         const u8 *p = buf;
620         int eccsize = chip->ecc.size;
621         int eccsteps = chip->ecc.steps;
622 
623         enable_hw_ecc = 1;
624         chip->write_buf(mtd, p, eccsize * eccsteps);
625         return 0;
626 }
627 
628 static int spinand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
629                                    u8 *buf, int oob_required, int page)
630 {
631         int retval;
632         u8 status;
633         u8 *p = buf;
634         int eccsize = chip->ecc.size;
635         int eccsteps = chip->ecc.steps;
636         struct spinand_info *info = (struct spinand_info *)chip->priv;
637 
638         enable_read_hw_ecc = 1;
639 
640         chip->read_buf(mtd, p, eccsize * eccsteps);
641         if (oob_required)
642                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
643 
644         while (1) {
645                 retval = spinand_read_status(info->spi, &status);
646                 if (retval < 0) {
647                         dev_err(&mtd->dev,
648                                 "error %d reading status register\n", retval);
649                         return retval;
650                 }
651 
652                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
653                         if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
654                                 pr_info("spinand: ECC error\n");
655                                 mtd->ecc_stats.failed++;
656                         } else if ((status & STATUS_ECC_MASK) ==
657                                         STATUS_ECC_1BIT_CORRECTED)
658                                 mtd->ecc_stats.corrected++;
659                         break;
660                 }
661         }
662         return 0;
663 }
664 #endif
665 
666 static void spinand_select_chip(struct mtd_info *mtd, int dev)
667 {
668 }
669 
670 static u8 spinand_read_byte(struct mtd_info *mtd)
671 {
672         struct spinand_state *state = mtd_to_state(mtd);
673         u8 data;
674 
675         data = state->buf[state->buf_ptr];
676         state->buf_ptr++;
677         return data;
678 }
679 
680 static int spinand_wait(struct mtd_info *mtd, struct nand_chip *chip)
681 {
682         struct spinand_info *info = (struct spinand_info *)chip->priv;
683 
684         unsigned long timeo = jiffies;
685         int retval, state = chip->state;
686         u8 status;
687 
688         if (state == FL_ERASING)
689                 timeo += (HZ * 400) / 1000;
690         else
691                 timeo += (HZ * 20) / 1000;
692 
693         while (time_before(jiffies, timeo)) {
694                 retval = spinand_read_status(info->spi, &status);
695                 if (retval < 0) {
696                         dev_err(&mtd->dev,
697                                 "error %d reading status register\n", retval);
698                         return retval;
699                 }
700 
701                 if ((status & STATUS_OIP_MASK) == STATUS_READY)
702                         return 0;
703 
704                 cond_resched();
705         }
706         return 0;
707 }
708 
709 static void spinand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
710 {
711         struct spinand_state *state = mtd_to_state(mtd);
712 
713         memcpy(state->buf + state->buf_ptr, buf, len);
714         state->buf_ptr += len;
715 }
716 
717 static void spinand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
718 {
719         struct spinand_state *state = mtd_to_state(mtd);
720 
721         memcpy(buf, state->buf + state->buf_ptr, len);
722         state->buf_ptr += len;
723 }
724 
725 /*
726  * spinand_reset- send RESET command "0xff" to the Nand device.
727  */
728 static void spinand_reset(struct spi_device *spi_nand)
729 {
730         struct spinand_cmd cmd = {0};
731 
732         cmd.cmd = CMD_RESET;
733 
734         if (spinand_cmd(spi_nand, &cmd) < 0)
735                 pr_info("spinand reset failed!\n");
736 
737         /* elapse 1ms before issuing any other command */
738         usleep_range(1000, 2000);
739 
740         if (wait_till_ready(spi_nand))
741                 dev_err(&spi_nand->dev, "wait timedout!\n");
742 }
743 
744 static void spinand_cmdfunc(struct mtd_info *mtd, unsigned int command,
745                             int column, int page)
746 {
747         struct nand_chip *chip = (struct nand_chip *)mtd->priv;
748         struct spinand_info *info = (struct spinand_info *)chip->priv;
749         struct spinand_state *state = (struct spinand_state *)info->priv;
750 
751         switch (command) {
752         /*
753          * READ0 - read in first  0x800 bytes
754          */
755         case NAND_CMD_READ1:
756         case NAND_CMD_READ0:
757                 state->buf_ptr = 0;
758                 spinand_read_page(info->spi, page, 0x0, 0x840, state->buf);
759                 break;
760         /* READOOB reads only the OOB because no ECC is performed. */
761         case NAND_CMD_READOOB:
762                 state->buf_ptr = 0;
763                 spinand_read_page(info->spi, page, 0x800, 0x40, state->buf);
764                 break;
765         case NAND_CMD_RNDOUT:
766                 state->buf_ptr = column;
767                 break;
768         case NAND_CMD_READID:
769                 state->buf_ptr = 0;
770                 spinand_read_id(info->spi, state->buf);
771                 break;
772         case NAND_CMD_PARAM:
773                 state->buf_ptr = 0;
774                 break;
775         /* ERASE1 stores the block and page address */
776         case NAND_CMD_ERASE1:
777                 spinand_erase_block(info->spi, page);
778                 break;
779         /* ERASE2 uses the block and page address from ERASE1 */
780         case NAND_CMD_ERASE2:
781                 break;
782         /* SEQIN sets up the addr buffer and all registers except the length */
783         case NAND_CMD_SEQIN:
784                 state->col = column;
785                 state->row = page;
786                 state->buf_ptr = 0;
787                 break;
788         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
789         case NAND_CMD_PAGEPROG:
790                 spinand_program_page(info->spi, state->row, state->col,
791                                      state->buf_ptr, state->buf);
792                 break;
793         case NAND_CMD_STATUS:
794                 spinand_get_otp(info->spi, state->buf);
795                 if (!(state->buf[0] & 0x80))
796                         state->buf[0] = 0x80;
797                 state->buf_ptr = 0;
798                 break;
799         /* RESET command */
800         case NAND_CMD_RESET:
801                 if (wait_till_ready(info->spi))
802                         dev_err(&info->spi->dev, "WAIT timedout!!!\n");
803                 /* a minimum of 250us must elapse before issuing RESET cmd*/
804                 usleep_range(250, 1000);
805                 spinand_reset(info->spi);
806                 break;
807         default:
808                 dev_err(&mtd->dev, "Unknown CMD: 0x%x\n", command);
809         }
810 }
811 
812 /**
813  * spinand_lock_block- send write register 0x1f command to the Nand device
814  *
815  * Description:
816  *    After power up, all the Nand blocks are locked.  This function allows
817  *    one to unlock the blocks, and so it can be written or erased.
818  */
819 static int spinand_lock_block(struct spi_device *spi_nand, u8 lock)
820 {
821         struct spinand_cmd cmd = {0};
822         int ret;
823         u8 otp = 0;
824 
825         ret = spinand_get_otp(spi_nand, &otp);
826 
827         cmd.cmd = CMD_WRITE_REG;
828         cmd.n_addr = 1;
829         cmd.addr[0] = REG_BLOCK_LOCK;
830         cmd.n_tx = 1;
831         cmd.tx_buf = &lock;
832 
833         ret = spinand_cmd(spi_nand, &cmd);
834         if (ret < 0)
835                 dev_err(&spi_nand->dev, "error %d lock block\n", ret);
836 
837         return ret;
838 }
839 
840 /*
841  * spinand_probe - [spinand Interface]
842  * @spi_nand: registered device driver.
843  *
844  * Description:
845  *   To set up the device driver parameters to make the device available.
846  */
847 static int spinand_probe(struct spi_device *spi_nand)
848 {
849         struct mtd_info *mtd;
850         struct nand_chip *chip;
851         struct spinand_info *info;
852         struct spinand_state *state;
853         struct mtd_part_parser_data ppdata;
854 
855         info  = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_info),
856                              GFP_KERNEL);
857         if (!info)
858                 return -ENOMEM;
859 
860         info->spi = spi_nand;
861 
862         spinand_lock_block(spi_nand, BL_ALL_UNLOCKED);
863 
864         state = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_state),
865                              GFP_KERNEL);
866         if (!state)
867                 return -ENOMEM;
868 
869         info->priv      = state;
870         state->buf_ptr  = 0;
871         state->buf      = devm_kzalloc(&spi_nand->dev, BUFSIZE, GFP_KERNEL);
872         if (!state->buf)
873                 return -ENOMEM;
874 
875         chip = devm_kzalloc(&spi_nand->dev, sizeof(struct nand_chip),
876                             GFP_KERNEL);
877         if (!chip)
878                 return -ENOMEM;
879 
880 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
881         chip->ecc.mode  = NAND_ECC_HW;
882         chip->ecc.size  = 0x200;
883         chip->ecc.bytes = 0x6;
884         chip->ecc.steps = 0x4;
885 
886         chip->ecc.strength = 1;
887         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
888         chip->ecc.layout = &spinand_oob_64;
889         chip->ecc.read_page = spinand_read_page_hwecc;
890         chip->ecc.write_page = spinand_write_page_hwecc;
891 #else
892         chip->ecc.mode  = NAND_ECC_SOFT;
893         if (spinand_disable_ecc(spi_nand) < 0)
894                 pr_info("%s: disable ecc failed!\n", __func__);
895 #endif
896 
897         chip->priv      = info;
898         chip->read_buf  = spinand_read_buf;
899         chip->write_buf = spinand_write_buf;
900         chip->read_byte = spinand_read_byte;
901         chip->cmdfunc   = spinand_cmdfunc;
902         chip->waitfunc  = spinand_wait;
903         chip->options   |= NAND_CACHEPRG;
904         chip->select_chip = spinand_select_chip;
905 
906         mtd = devm_kzalloc(&spi_nand->dev, sizeof(struct mtd_info), GFP_KERNEL);
907         if (!mtd)
908                 return -ENOMEM;
909 
910         dev_set_drvdata(&spi_nand->dev, mtd);
911 
912         mtd->priv = chip;
913         mtd->dev.parent = &spi_nand->dev;
914         mtd->oobsize = 64;
915 
916         if (nand_scan(mtd, 1))
917                 return -ENXIO;
918 
919         ppdata.of_node = spi_nand->dev.of_node;
920         return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
921 }
922 
923 /*
924  * spinand_remove: Remove the device driver
925  * @spi: the spi device.
926  *
927  * Description:
928  *   To remove the device driver parameters and free up allocated memories.
929  */
930 static int spinand_remove(struct spi_device *spi)
931 {
932         mtd_device_unregister(dev_get_drvdata(&spi->dev));
933 
934         return 0;
935 }
936 
937 static const struct of_device_id spinand_dt[] = {
938         { .compatible = "spinand,mt29f", },
939         {}
940 };
941 MODULE_DEVICE_TABLE(of, spinand_dt);
942 
943 /*
944  * Device name structure description
945  */
946 static struct spi_driver spinand_driver = {
947         .driver = {
948                 .name           = "mt29f",
949                 .of_match_table = spinand_dt,
950         },
951         .probe          = spinand_probe,
952         .remove         = spinand_remove,
953 };
954 
955 module_spi_driver(spinand_driver);
956 
957 MODULE_DESCRIPTION("SPI NAND driver for Micron");
958 MODULE_AUTHOR("Henry Pan <hspan@micron.com>, Kamlakant Patel <kamlakant.patel@broadcom.com>");
959 MODULE_LICENSE("GPL v2");
960 

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