Version:  2.0.40 2.2.26 2.4.37 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7

Linux/drivers/staging/mt29f_spinand/mt29f_spinand.c

  1 /*
  2  * Copyright (c) 2003-2013 Broadcom Corporation
  3  *
  4  * Copyright (c) 2009-2010 Micron Technology, Inc.
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License
  8  * as published by the Free Software Foundation; either version 2
  9  * of the License, or (at your option) any later version.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  */
 16 
 17 #include <linux/module.h>
 18 #include <linux/delay.h>
 19 #include <linux/mtd/mtd.h>
 20 #include <linux/mtd/partitions.h>
 21 #include <linux/mtd/nand.h>
 22 #include <linux/spi/spi.h>
 23 
 24 #include "mt29f_spinand.h"
 25 
 26 #define BUFSIZE (10 * 64 * 2048)
 27 #define CACHE_BUF 2112
 28 /*
 29  * OOB area specification layout:  Total 32 available free bytes.
 30  */
 31 
 32 static inline struct spinand_state *mtd_to_state(struct mtd_info *mtd)
 33 {
 34         struct nand_chip *chip = mtd_to_nand(mtd);
 35         struct spinand_info *info = nand_get_controller_data(chip);
 36         struct spinand_state *state = info->priv;
 37 
 38         return state;
 39 }
 40 
 41 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 42 static int enable_hw_ecc;
 43 static int enable_read_hw_ecc;
 44 
 45 static int spinand_ooblayout_64_ecc(struct mtd_info *mtd, int section,
 46                                     struct mtd_oob_region *oobregion)
 47 {
 48         if (section > 3)
 49                 return -ERANGE;
 50 
 51         oobregion->offset = (section * 16) + 1;
 52         oobregion->length = 6;
 53 
 54         return 0;
 55 }
 56 
 57 static int spinand_ooblayout_64_free(struct mtd_info *mtd, int section,
 58                                      struct mtd_oob_region *oobregion)
 59 {
 60         if (section > 3)
 61                 return -ERANGE;
 62 
 63         oobregion->offset = (section * 16) + 8;
 64         oobregion->length = 8;
 65 
 66         return 0;
 67 }
 68 
 69 static const struct mtd_ooblayout_ops spinand_oob_64_ops = {
 70         .ecc = spinand_ooblayout_64_ecc,
 71         .free = spinand_ooblayout_64_free,
 72 };
 73 #endif
 74 
 75 /**
 76  * spinand_cmd - process a command to send to the SPI Nand
 77  * Description:
 78  *    Set up the command buffer to send to the SPI controller.
 79  *    The command buffer has to initialized to 0.
 80  */
 81 
 82 static int spinand_cmd(struct spi_device *spi, struct spinand_cmd *cmd)
 83 {
 84         struct spi_message message;
 85         struct spi_transfer x[4];
 86         u8 dummy = 0xff;
 87 
 88         spi_message_init(&message);
 89         memset(x, 0, sizeof(x));
 90 
 91         x[0].len = 1;
 92         x[0].tx_buf = &cmd->cmd;
 93         spi_message_add_tail(&x[0], &message);
 94 
 95         if (cmd->n_addr) {
 96                 x[1].len = cmd->n_addr;
 97                 x[1].tx_buf = cmd->addr;
 98                 spi_message_add_tail(&x[1], &message);
 99         }
100 
101         if (cmd->n_dummy) {
102                 x[2].len = cmd->n_dummy;
103                 x[2].tx_buf = &dummy;
104                 spi_message_add_tail(&x[2], &message);
105         }
106 
107         if (cmd->n_tx) {
108                 x[3].len = cmd->n_tx;
109                 x[3].tx_buf = cmd->tx_buf;
110                 spi_message_add_tail(&x[3], &message);
111         }
112 
113         if (cmd->n_rx) {
114                 x[3].len = cmd->n_rx;
115                 x[3].rx_buf = cmd->rx_buf;
116                 spi_message_add_tail(&x[3], &message);
117         }
118 
119         return spi_sync(spi, &message);
120 }
121 
122 /**
123  * spinand_read_id - Read SPI Nand ID
124  * Description:
125  *    read two ID bytes from the SPI Nand device
126  */
127 static int spinand_read_id(struct spi_device *spi_nand, u8 *id)
128 {
129         int retval;
130         u8 nand_id[3];
131         struct spinand_cmd cmd = {0};
132 
133         cmd.cmd = CMD_READ_ID;
134         cmd.n_rx = 3;
135         cmd.rx_buf = &nand_id[0];
136 
137         retval = spinand_cmd(spi_nand, &cmd);
138         if (retval < 0) {
139                 dev_err(&spi_nand->dev, "error %d reading id\n", retval);
140                 return retval;
141         }
142         id[0] = nand_id[1];
143         id[1] = nand_id[2];
144         return retval;
145 }
146 
147 /**
148  * spinand_read_status - send command 0xf to the SPI Nand status register
149  * Description:
150  *    After read, write, or erase, the Nand device is expected to set the
151  *    busy status.
152  *    This function is to allow reading the status of the command: read,
153  *    write, and erase.
154  *    Once the status turns to be ready, the other status bits also are
155  *    valid status bits.
156  */
157 static int spinand_read_status(struct spi_device *spi_nand, u8 *status)
158 {
159         struct spinand_cmd cmd = {0};
160         int ret;
161 
162         cmd.cmd = CMD_READ_REG;
163         cmd.n_addr = 1;
164         cmd.addr[0] = REG_STATUS;
165         cmd.n_rx = 1;
166         cmd.rx_buf = status;
167 
168         ret = spinand_cmd(spi_nand, &cmd);
169         if (ret < 0)
170                 dev_err(&spi_nand->dev, "err: %d read status register\n", ret);
171 
172         return ret;
173 }
174 
175 #define MAX_WAIT_JIFFIES  (40 * HZ)
176 static int wait_till_ready(struct spi_device *spi_nand)
177 {
178         unsigned long deadline;
179         int retval;
180         u8 stat = 0;
181 
182         deadline = jiffies + MAX_WAIT_JIFFIES;
183         do {
184                 retval = spinand_read_status(spi_nand, &stat);
185                 if (retval < 0)
186                         return -1;
187                 if (!(stat & 0x1))
188                         break;
189 
190                 cond_resched();
191         } while (!time_after_eq(jiffies, deadline));
192 
193         if ((stat & 0x1) == 0)
194                 return 0;
195 
196         return -1;
197 }
198 
199 /**
200  * spinand_get_otp - send command 0xf to read the SPI Nand OTP register
201  * Description:
202  *   There is one bit( bit 0x10 ) to set or to clear the internal ECC.
203  *   Enable chip internal ECC, set the bit to 1
204  *   Disable chip internal ECC, clear the bit to 0
205  */
206 static int spinand_get_otp(struct spi_device *spi_nand, u8 *otp)
207 {
208         struct spinand_cmd cmd = {0};
209         int retval;
210 
211         cmd.cmd = CMD_READ_REG;
212         cmd.n_addr = 1;
213         cmd.addr[0] = REG_OTP;
214         cmd.n_rx = 1;
215         cmd.rx_buf = otp;
216 
217         retval = spinand_cmd(spi_nand, &cmd);
218         if (retval < 0)
219                 dev_err(&spi_nand->dev, "error %d get otp\n", retval);
220         return retval;
221 }
222 
223 /**
224  * spinand_set_otp - send command 0x1f to write the SPI Nand OTP register
225  * Description:
226  *   There is one bit( bit 0x10 ) to set or to clear the internal ECC.
227  *   Enable chip internal ECC, set the bit to 1
228  *   Disable chip internal ECC, clear the bit to 0
229  */
230 static int spinand_set_otp(struct spi_device *spi_nand, u8 *otp)
231 {
232         int retval;
233         struct spinand_cmd cmd = {0};
234 
235         cmd.cmd = CMD_WRITE_REG;
236         cmd.n_addr = 1;
237         cmd.addr[0] = REG_OTP;
238         cmd.n_tx = 1;
239         cmd.tx_buf = otp;
240 
241         retval = spinand_cmd(spi_nand, &cmd);
242         if (retval < 0)
243                 dev_err(&spi_nand->dev, "error %d set otp\n", retval);
244 
245         return retval;
246 }
247 
248 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
249 /**
250  * spinand_enable_ecc - send command 0x1f to write the SPI Nand OTP register
251  * Description:
252  *   There is one bit( bit 0x10 ) to set or to clear the internal ECC.
253  *   Enable chip internal ECC, set the bit to 1
254  *   Disable chip internal ECC, clear the bit to 0
255  */
256 static int spinand_enable_ecc(struct spi_device *spi_nand)
257 {
258         int retval;
259         u8 otp = 0;
260 
261         retval = spinand_get_otp(spi_nand, &otp);
262         if (retval < 0)
263                 return retval;
264 
265         if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK)
266                 return 0;
267         otp |= OTP_ECC_MASK;
268         retval = spinand_set_otp(spi_nand, &otp);
269         if (retval < 0)
270                 return retval;
271         return spinand_get_otp(spi_nand, &otp);
272 }
273 #endif
274 
275 static int spinand_disable_ecc(struct spi_device *spi_nand)
276 {
277         int retval;
278         u8 otp = 0;
279 
280         retval = spinand_get_otp(spi_nand, &otp);
281         if (retval < 0)
282                 return retval;
283 
284         if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) {
285                 otp &= ~OTP_ECC_MASK;
286                 retval = spinand_set_otp(spi_nand, &otp);
287                 if (retval < 0)
288                         return retval;
289                 return spinand_get_otp(spi_nand, &otp);
290         }
291         return 0;
292 }
293 
294 /**
295  * spinand_write_enable - send command 0x06 to enable write or erase the
296  * Nand cells
297  * Description:
298  *   Before write and erase the Nand cells, the write enable has to be set.
299  *   After the write or erase, the write enable bit is automatically
300  *   cleared (status register bit 2)
301  *   Set the bit 2 of the status register has the same effect
302  */
303 static int spinand_write_enable(struct spi_device *spi_nand)
304 {
305         struct spinand_cmd cmd = {0};
306 
307         cmd.cmd = CMD_WR_ENABLE;
308         return spinand_cmd(spi_nand, &cmd);
309 }
310 
311 static int spinand_read_page_to_cache(struct spi_device *spi_nand, u16 page_id)
312 {
313         struct spinand_cmd cmd = {0};
314         u16 row;
315 
316         row = page_id;
317         cmd.cmd = CMD_READ;
318         cmd.n_addr = 3;
319         cmd.addr[1] = (u8)((row & 0xff00) >> 8);
320         cmd.addr[2] = (u8)(row & 0x00ff);
321 
322         return spinand_cmd(spi_nand, &cmd);
323 }
324 
325 /**
326  * spinand_read_from_cache - send command 0x03 to read out the data from the
327  * cache register (2112 bytes max)
328  * Description:
329  *   The read can specify 1 to 2112 bytes of data read at the corresponding
330  *   locations.
331  *   No tRd delay.
332  */
333 static int spinand_read_from_cache(struct spi_device *spi_nand, u16 page_id,
334                                    u16 byte_id, u16 len, u8 *rbuf)
335 {
336         struct spinand_cmd cmd = {0};
337         u16 column;
338 
339         column = byte_id;
340         cmd.cmd = CMD_READ_RDM;
341         cmd.n_addr = 3;
342         cmd.addr[0] = (u8)((column & 0xff00) >> 8);
343         cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
344         cmd.addr[1] = (u8)(column & 0x00ff);
345         cmd.addr[2] = (u8)(0xff);
346         cmd.n_dummy = 0;
347         cmd.n_rx = len;
348         cmd.rx_buf = rbuf;
349 
350         return spinand_cmd(spi_nand, &cmd);
351 }
352 
353 /**
354  * spinand_read_page - read a page
355  * @page_id: the physical page number
356  * @offset:  the location from 0 to 2111
357  * @len:     number of bytes to read
358  * @rbuf:    read buffer to hold @len bytes
359  *
360  * Description:
361  *   The read includes two commands to the Nand - 0x13 and 0x03 commands
362  *   Poll to read status to wait for tRD time.
363  */
364 static int spinand_read_page(struct spi_device *spi_nand, u16 page_id,
365                              u16 offset, u16 len, u8 *rbuf)
366 {
367         int ret;
368         u8 status = 0;
369 
370 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
371         if (enable_read_hw_ecc) {
372                 if (spinand_enable_ecc(spi_nand) < 0)
373                         dev_err(&spi_nand->dev, "enable HW ECC failed!");
374         }
375 #endif
376         ret = spinand_read_page_to_cache(spi_nand, page_id);
377         if (ret < 0)
378                 return ret;
379 
380         if (wait_till_ready(spi_nand))
381                 dev_err(&spi_nand->dev, "WAIT timedout!!!\n");
382 
383         while (1) {
384                 ret = spinand_read_status(spi_nand, &status);
385                 if (ret < 0) {
386                         dev_err(&spi_nand->dev,
387                                 "err %d read status register\n", ret);
388                         return ret;
389                 }
390 
391                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
392                         if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
393                                 dev_err(&spi_nand->dev, "ecc error, page=%d\n",
394                                         page_id);
395                                 return 0;
396                         }
397                         break;
398                 }
399         }
400 
401         ret = spinand_read_from_cache(spi_nand, page_id, offset, len, rbuf);
402         if (ret < 0) {
403                 dev_err(&spi_nand->dev, "read from cache failed!!\n");
404                 return ret;
405         }
406 
407 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
408         if (enable_read_hw_ecc) {
409                 ret = spinand_disable_ecc(spi_nand);
410                 if (ret < 0) {
411                         dev_err(&spi_nand->dev, "disable ecc failed!!\n");
412                         return ret;
413                 }
414                 enable_read_hw_ecc = 0;
415         }
416 #endif
417         return ret;
418 }
419 
420 /**
421  * spinand_program_data_to_cache - write a page to cache
422  * @byte_id: the location to write to the cache
423  * @len:     number of bytes to write
424  * @wbuf:    write buffer holding @len bytes
425  *
426  * Description:
427  *   The write command used here is 0x84--indicating that the cache is
428  *   not cleared first.
429  *   Since it is writing the data to cache, there is no tPROG time.
430  */
431 static int spinand_program_data_to_cache(struct spi_device *spi_nand,
432                                          u16 page_id, u16 byte_id,
433                                          u16 len, u8 *wbuf)
434 {
435         struct spinand_cmd cmd = {0};
436         u16 column;
437 
438         column = byte_id;
439         cmd.cmd = CMD_PROG_PAGE_CLRCACHE;
440         cmd.n_addr = 2;
441         cmd.addr[0] = (u8)((column & 0xff00) >> 8);
442         cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
443         cmd.addr[1] = (u8)(column & 0x00ff);
444         cmd.n_tx = len;
445         cmd.tx_buf = wbuf;
446 
447         return spinand_cmd(spi_nand, &cmd);
448 }
449 
450 /**
451  * spinand_program_execute - write a page from cache to the Nand array
452  * @page_id: the physical page location to write the page.
453  *
454  * Description:
455  *   The write command used here is 0x10--indicating the cache is writing to
456  *   the Nand array.
457  *   Need to wait for tPROG time to finish the transaction.
458  */
459 static int spinand_program_execute(struct spi_device *spi_nand, u16 page_id)
460 {
461         struct spinand_cmd cmd = {0};
462         u16 row;
463 
464         row = page_id;
465         cmd.cmd = CMD_PROG_PAGE_EXC;
466         cmd.n_addr = 3;
467         cmd.addr[1] = (u8)((row & 0xff00) >> 8);
468         cmd.addr[2] = (u8)(row & 0x00ff);
469 
470         return spinand_cmd(spi_nand, &cmd);
471 }
472 
473 /**
474  * spinand_program_page - write a page
475  * @page_id: the physical page location to write the page.
476  * @offset:  the location from the cache starting from 0 to 2111
477  * @len:     the number of bytes to write
478  * @buf:     the buffer holding @len bytes
479  *
480  * Description:
481  *   The commands used here are 0x06, 0x84, and 0x10--indicating that
482  *   the write enable is first sent, the write cache command, and the
483  *   write execute command.
484  *   Poll to wait for the tPROG time to finish the transaction.
485  */
486 static int spinand_program_page(struct spi_device *spi_nand,
487                                 u16 page_id, u16 offset, u16 len, u8 *buf)
488 {
489         int retval;
490         u8 status = 0;
491         u8 *wbuf;
492 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
493         unsigned int i, j;
494 
495         wbuf = devm_kzalloc(&spi_nand->dev, CACHE_BUF, GFP_KERNEL);
496         if (!wbuf)
497                 return -ENOMEM;
498 
499         enable_read_hw_ecc = 0;
500         spinand_read_page(spi_nand, page_id, 0, CACHE_BUF, wbuf);
501 
502         for (i = offset, j = 0; i < len; i++, j++)
503                 wbuf[i] &= buf[j];
504 
505         if (enable_hw_ecc) {
506                 retval = spinand_enable_ecc(spi_nand);
507                 if (retval < 0) {
508                         dev_err(&spi_nand->dev, "enable ecc failed!!\n");
509                         return retval;
510                 }
511         }
512 #else
513         wbuf = buf;
514 #endif
515         retval = spinand_write_enable(spi_nand);
516         if (retval < 0) {
517                 dev_err(&spi_nand->dev, "write enable failed!!\n");
518                 return retval;
519         }
520         if (wait_till_ready(spi_nand))
521                 dev_err(&spi_nand->dev, "wait timedout!!!\n");
522 
523         retval = spinand_program_data_to_cache(spi_nand, page_id,
524                                                offset, len, wbuf);
525         if (retval < 0)
526                 return retval;
527         retval = spinand_program_execute(spi_nand, page_id);
528         if (retval < 0)
529                 return retval;
530         while (1) {
531                 retval = spinand_read_status(spi_nand, &status);
532                 if (retval < 0) {
533                         dev_err(&spi_nand->dev,
534                                 "error %d reading status register\n", retval);
535                         return retval;
536                 }
537 
538                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
539                         if ((status & STATUS_P_FAIL_MASK) == STATUS_P_FAIL) {
540                                 dev_err(&spi_nand->dev,
541                                         "program error, page %d\n", page_id);
542                                 return -1;
543                         }
544                         break;
545                 }
546         }
547 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
548         if (enable_hw_ecc) {
549                 retval = spinand_disable_ecc(spi_nand);
550                 if (retval < 0) {
551                         dev_err(&spi_nand->dev, "disable ecc failed!!\n");
552                         return retval;
553                 }
554                 enable_hw_ecc = 0;
555         }
556 #endif
557 
558         return 0;
559 }
560 
561 /**
562  * spinand_erase_block_erase - erase a page
563  * @block_id: the physical block location to erase.
564  *
565  * Description:
566  *   The command used here is 0xd8--indicating an erase command to erase
567  *   one block--64 pages
568  *   Need to wait for tERS.
569  */
570 static int spinand_erase_block_erase(struct spi_device *spi_nand, u16 block_id)
571 {
572         struct spinand_cmd cmd = {0};
573         u16 row;
574 
575         row = block_id;
576         cmd.cmd = CMD_ERASE_BLK;
577         cmd.n_addr = 3;
578         cmd.addr[1] = (u8)((row & 0xff00) >> 8);
579         cmd.addr[2] = (u8)(row & 0x00ff);
580 
581         return spinand_cmd(spi_nand, &cmd);
582 }
583 
584 /**
585  * spinand_erase_block - erase a page
586  * @block_id: the physical block location to erase.
587  *
588  * Description:
589  *   The commands used here are 0x06 and 0xd8--indicating an erase
590  *   command to erase one block--64 pages
591  *   It will first to enable the write enable bit (0x06 command),
592  *   and then send the 0xd8 erase command
593  *   Poll to wait for the tERS time to complete the tranaction.
594  */
595 static int spinand_erase_block(struct spi_device *spi_nand, u16 block_id)
596 {
597         int retval;
598         u8 status = 0;
599 
600         retval = spinand_write_enable(spi_nand);
601         if (wait_till_ready(spi_nand))
602                 dev_err(&spi_nand->dev, "wait timedout!!!\n");
603 
604         retval = spinand_erase_block_erase(spi_nand, block_id);
605         while (1) {
606                 retval = spinand_read_status(spi_nand, &status);
607                 if (retval < 0) {
608                         dev_err(&spi_nand->dev,
609                                 "error %d reading status register\n", retval);
610                         return retval;
611                 }
612 
613                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
614                         if ((status & STATUS_E_FAIL_MASK) == STATUS_E_FAIL) {
615                                 dev_err(&spi_nand->dev,
616                                         "erase error, block %d\n", block_id);
617                                 return -1;
618                         }
619                         break;
620                 }
621         }
622         return 0;
623 }
624 
625 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
626 static int spinand_write_page_hwecc(struct mtd_info *mtd,
627                                     struct nand_chip *chip,
628                                     const u8 *buf, int oob_required,
629                                     int page)
630 {
631         const u8 *p = buf;
632         int eccsize = chip->ecc.size;
633         int eccsteps = chip->ecc.steps;
634 
635         enable_hw_ecc = 1;
636         chip->write_buf(mtd, p, eccsize * eccsteps);
637         return 0;
638 }
639 
640 static int spinand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
641                                    u8 *buf, int oob_required, int page)
642 {
643         int retval;
644         u8 status;
645         u8 *p = buf;
646         int eccsize = chip->ecc.size;
647         int eccsteps = chip->ecc.steps;
648         struct spinand_info *info = nand_get_controller_data(chip);
649 
650         enable_read_hw_ecc = 1;
651 
652         chip->read_buf(mtd, p, eccsize * eccsteps);
653         if (oob_required)
654                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
655 
656         while (1) {
657                 retval = spinand_read_status(info->spi, &status);
658                 if (retval < 0) {
659                         dev_err(&mtd->dev,
660                                 "error %d reading status register\n", retval);
661                         return retval;
662                 }
663 
664                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
665                         if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
666                                 pr_info("spinand: ECC error\n");
667                                 mtd->ecc_stats.failed++;
668                         } else if ((status & STATUS_ECC_MASK) ==
669                                         STATUS_ECC_1BIT_CORRECTED)
670                                 mtd->ecc_stats.corrected++;
671                         break;
672                 }
673         }
674         return 0;
675 }
676 #endif
677 
678 static void spinand_select_chip(struct mtd_info *mtd, int dev)
679 {
680 }
681 
682 static u8 spinand_read_byte(struct mtd_info *mtd)
683 {
684         struct spinand_state *state = mtd_to_state(mtd);
685         u8 data;
686 
687         data = state->buf[state->buf_ptr];
688         state->buf_ptr++;
689         return data;
690 }
691 
692 static int spinand_wait(struct mtd_info *mtd, struct nand_chip *chip)
693 {
694         struct spinand_info *info = nand_get_controller_data(chip);
695 
696         unsigned long timeo = jiffies;
697         int retval, state = chip->state;
698         u8 status;
699 
700         if (state == FL_ERASING)
701                 timeo += (HZ * 400) / 1000;
702         else
703                 timeo += (HZ * 20) / 1000;
704 
705         while (time_before(jiffies, timeo)) {
706                 retval = spinand_read_status(info->spi, &status);
707                 if (retval < 0) {
708                         dev_err(&mtd->dev,
709                                 "error %d reading status register\n", retval);
710                         return retval;
711                 }
712 
713                 if ((status & STATUS_OIP_MASK) == STATUS_READY)
714                         return 0;
715 
716                 cond_resched();
717         }
718         return 0;
719 }
720 
721 static void spinand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
722 {
723         struct spinand_state *state = mtd_to_state(mtd);
724 
725         memcpy(state->buf + state->buf_ptr, buf, len);
726         state->buf_ptr += len;
727 }
728 
729 static void spinand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
730 {
731         struct spinand_state *state = mtd_to_state(mtd);
732 
733         memcpy(buf, state->buf + state->buf_ptr, len);
734         state->buf_ptr += len;
735 }
736 
737 /*
738  * spinand_reset- send RESET command "0xff" to the Nand device.
739  */
740 static void spinand_reset(struct spi_device *spi_nand)
741 {
742         struct spinand_cmd cmd = {0};
743 
744         cmd.cmd = CMD_RESET;
745 
746         if (spinand_cmd(spi_nand, &cmd) < 0)
747                 pr_info("spinand reset failed!\n");
748 
749         /* elapse 1ms before issuing any other command */
750         usleep_range(1000, 2000);
751 
752         if (wait_till_ready(spi_nand))
753                 dev_err(&spi_nand->dev, "wait timedout!\n");
754 }
755 
756 static void spinand_cmdfunc(struct mtd_info *mtd, unsigned int command,
757                             int column, int page)
758 {
759         struct nand_chip *chip = mtd_to_nand(mtd);
760         struct spinand_info *info = nand_get_controller_data(chip);
761         struct spinand_state *state = info->priv;
762 
763         switch (command) {
764         /*
765          * READ0 - read in first  0x800 bytes
766          */
767         case NAND_CMD_READ1:
768         case NAND_CMD_READ0:
769                 state->buf_ptr = 0;
770                 spinand_read_page(info->spi, page, 0x0, 0x840, state->buf);
771                 break;
772         /* READOOB reads only the OOB because no ECC is performed. */
773         case NAND_CMD_READOOB:
774                 state->buf_ptr = 0;
775                 spinand_read_page(info->spi, page, 0x800, 0x40, state->buf);
776                 break;
777         case NAND_CMD_RNDOUT:
778                 state->buf_ptr = column;
779                 break;
780         case NAND_CMD_READID:
781                 state->buf_ptr = 0;
782                 spinand_read_id(info->spi, state->buf);
783                 break;
784         case NAND_CMD_PARAM:
785                 state->buf_ptr = 0;
786                 break;
787         /* ERASE1 stores the block and page address */
788         case NAND_CMD_ERASE1:
789                 spinand_erase_block(info->spi, page);
790                 break;
791         /* ERASE2 uses the block and page address from ERASE1 */
792         case NAND_CMD_ERASE2:
793                 break;
794         /* SEQIN sets up the addr buffer and all registers except the length */
795         case NAND_CMD_SEQIN:
796                 state->col = column;
797                 state->row = page;
798                 state->buf_ptr = 0;
799                 break;
800         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
801         case NAND_CMD_PAGEPROG:
802                 spinand_program_page(info->spi, state->row, state->col,
803                                      state->buf_ptr, state->buf);
804                 break;
805         case NAND_CMD_STATUS:
806                 spinand_get_otp(info->spi, state->buf);
807                 if (!(state->buf[0] & 0x80))
808                         state->buf[0] = 0x80;
809                 state->buf_ptr = 0;
810                 break;
811         /* RESET command */
812         case NAND_CMD_RESET:
813                 if (wait_till_ready(info->spi))
814                         dev_err(&info->spi->dev, "WAIT timedout!!!\n");
815                 /* a minimum of 250us must elapse before issuing RESET cmd*/
816                 usleep_range(250, 1000);
817                 spinand_reset(info->spi);
818                 break;
819         default:
820                 dev_err(&mtd->dev, "Unknown CMD: 0x%x\n", command);
821         }
822 }
823 
824 /**
825  * spinand_lock_block - send write register 0x1f command to the Nand device
826  *
827  * Description:
828  *    After power up, all the Nand blocks are locked.  This function allows
829  *    one to unlock the blocks, and so it can be written or erased.
830  */
831 static int spinand_lock_block(struct spi_device *spi_nand, u8 lock)
832 {
833         struct spinand_cmd cmd = {0};
834         int ret;
835         u8 otp = 0;
836 
837         ret = spinand_get_otp(spi_nand, &otp);
838 
839         cmd.cmd = CMD_WRITE_REG;
840         cmd.n_addr = 1;
841         cmd.addr[0] = REG_BLOCK_LOCK;
842         cmd.n_tx = 1;
843         cmd.tx_buf = &lock;
844 
845         ret = spinand_cmd(spi_nand, &cmd);
846         if (ret < 0)
847                 dev_err(&spi_nand->dev, "error %d lock block\n", ret);
848 
849         return ret;
850 }
851 
852 /**
853  * spinand_probe - [spinand Interface]
854  * @spi_nand: registered device driver.
855  *
856  * Description:
857  *   Set up the device driver parameters to make the device available.
858  */
859 static int spinand_probe(struct spi_device *spi_nand)
860 {
861         struct mtd_info *mtd;
862         struct nand_chip *chip;
863         struct spinand_info *info;
864         struct spinand_state *state;
865 
866         info  = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_info),
867                              GFP_KERNEL);
868         if (!info)
869                 return -ENOMEM;
870 
871         info->spi = spi_nand;
872 
873         spinand_lock_block(spi_nand, BL_ALL_UNLOCKED);
874 
875         state = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_state),
876                              GFP_KERNEL);
877         if (!state)
878                 return -ENOMEM;
879 
880         info->priv      = state;
881         state->buf_ptr  = 0;
882         state->buf      = devm_kzalloc(&spi_nand->dev, BUFSIZE, GFP_KERNEL);
883         if (!state->buf)
884                 return -ENOMEM;
885 
886         chip = devm_kzalloc(&spi_nand->dev, sizeof(struct nand_chip),
887                             GFP_KERNEL);
888         if (!chip)
889                 return -ENOMEM;
890 
891 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
892         chip->ecc.mode  = NAND_ECC_HW;
893         chip->ecc.size  = 0x200;
894         chip->ecc.bytes = 0x6;
895         chip->ecc.steps = 0x4;
896 
897         chip->ecc.strength = 1;
898         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
899         chip->ecc.read_page = spinand_read_page_hwecc;
900         chip->ecc.write_page = spinand_write_page_hwecc;
901 #else
902         chip->ecc.mode  = NAND_ECC_SOFT;
903         chip->ecc.algo  = NAND_ECC_HAMMING;
904         if (spinand_disable_ecc(spi_nand) < 0)
905                 dev_info(&spi_nand->dev, "%s: disable ecc failed!\n",
906                          __func__);
907 #endif
908 
909         nand_set_flash_node(chip, spi_nand->dev.of_node);
910         nand_set_controller_data(chip, info);
911         chip->read_buf  = spinand_read_buf;
912         chip->write_buf = spinand_write_buf;
913         chip->read_byte = spinand_read_byte;
914         chip->cmdfunc   = spinand_cmdfunc;
915         chip->waitfunc  = spinand_wait;
916         chip->options   |= NAND_CACHEPRG;
917         chip->select_chip = spinand_select_chip;
918 
919         mtd = nand_to_mtd(chip);
920 
921         dev_set_drvdata(&spi_nand->dev, mtd);
922 
923         mtd->dev.parent = &spi_nand->dev;
924         mtd->oobsize = 64;
925 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
926         mtd_set_ooblayout(mtd, &spinand_oob_64_ops);
927 #endif
928 
929         if (nand_scan(mtd, 1))
930                 return -ENXIO;
931 
932         return mtd_device_register(mtd, NULL, 0);
933 }
934 
935 /**
936  * spinand_remove - remove the device driver
937  * @spi: the spi device.
938  *
939  * Description:
940  *   Remove the device driver parameters and free up allocated memories.
941  */
942 static int spinand_remove(struct spi_device *spi)
943 {
944         mtd_device_unregister(dev_get_drvdata(&spi->dev));
945 
946         return 0;
947 }
948 
949 static const struct of_device_id spinand_dt[] = {
950         { .compatible = "spinand,mt29f", },
951         {}
952 };
953 MODULE_DEVICE_TABLE(of, spinand_dt);
954 
955 /*
956  * Device name structure description
957  */
958 static struct spi_driver spinand_driver = {
959         .driver = {
960                 .name           = "mt29f",
961                 .of_match_table = spinand_dt,
962         },
963         .probe          = spinand_probe,
964         .remove         = spinand_remove,
965 };
966 
967 module_spi_driver(spinand_driver);
968 
969 MODULE_DESCRIPTION("SPI NAND driver for Micron");
970 MODULE_AUTHOR("Henry Pan <hspan@micron.com>, Kamlakant Patel <kamlakant.patel@broadcom.com>");
971 MODULE_LICENSE("GPL v2");
972 

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