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Linux/drivers/staging/media/lirc/lirc_sir.c

  1 /*
  2  * LIRC SIR driver, (C) 2000 Milan Pikula <www@fornax.sk>
  3  *
  4  * lirc_sir - Device driver for use with SIR (serial infra red)
  5  * mode of IrDA on many notebooks.
  6  *
  7  *  This program is free software; you can redistribute it and/or modify
  8  *  it under the terms of the GNU General Public License as published by
  9  *  the Free Software Foundation; either version 2 of the License, or
 10  *  (at your option) any later version.
 11  *
 12  *  This program is distributed in the hope that it will be useful,
 13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 15  *  GNU General Public License for more details.
 16  *
 17  *  You should have received a copy of the GNU General Public License
 18  *  along with this program; if not, write to the Free Software
 19  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 20  *
 21  *
 22  * 2000/09/16 Frank Przybylski <mail@frankprzybylski.de> :
 23  *  added timeout and relaxed pulse detection, removed gap bug
 24  *
 25  * 2000/12/15 Christoph Bartelmus <lirc@bartelmus.de> :
 26  *   added support for Tekram Irmate 210 (sending does not work yet,
 27  *   kind of disappointing that nobody was able to implement that
 28  *   before),
 29  *   major clean-up
 30  *
 31  * 2001/02/27 Christoph Bartelmus <lirc@bartelmus.de> :
 32  *   added support for StrongARM SA1100 embedded microprocessor
 33  *   parts cut'n'pasted from sa1100_ir.c (C) 2000 Russell King
 34  */
 35 
 36 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 37 
 38 #include <linux/module.h>
 39 #include <linux/sched.h>
 40 #include <linux/errno.h>
 41 #include <linux/signal.h>
 42 #include <linux/fs.h>
 43 #include <linux/interrupt.h>
 44 #include <linux/ioport.h>
 45 #include <linux/kernel.h>
 46 #include <linux/serial_reg.h>
 47 #include <linux/time.h>
 48 #include <linux/string.h>
 49 #include <linux/types.h>
 50 #include <linux/wait.h>
 51 #include <linux/mm.h>
 52 #include <linux/delay.h>
 53 #include <linux/poll.h>
 54 #include <linux/io.h>
 55 #include <asm/irq.h>
 56 #include <linux/fcntl.h>
 57 #include <linux/platform_device.h>
 58 #ifdef LIRC_ON_SA1100
 59 #include <asm/hardware.h>
 60 #ifdef CONFIG_SA1100_COLLIE
 61 #include <asm/arch/tc35143.h>
 62 #include <asm/ucb1200.h>
 63 #endif
 64 #endif
 65 
 66 #include <linux/timer.h>
 67 
 68 #include <media/lirc.h>
 69 #include <media/lirc_dev.h>
 70 
 71 /* SECTION: Definitions */
 72 
 73 /*** Tekram dongle ***/
 74 #ifdef LIRC_SIR_TEKRAM
 75 /* stolen from kernel source */
 76 /* definitions for Tekram dongle */
 77 #define TEKRAM_115200 0x00
 78 #define TEKRAM_57600  0x01
 79 #define TEKRAM_38400  0x02
 80 #define TEKRAM_19200  0x03
 81 #define TEKRAM_9600   0x04
 82 #define TEKRAM_2400   0x08
 83 
 84 #define TEKRAM_PW 0x10 /* Pulse select bit */
 85 
 86 /* 10bit * 1s/115200bit in milliseconds = 87ms*/
 87 #define TIME_CONST (10000000ul/115200ul)
 88 
 89 #endif
 90 
 91 #ifdef LIRC_SIR_ACTISYS_ACT200L
 92 static void init_act200(void);
 93 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
 94 static void init_act220(void);
 95 #endif
 96 
 97 /*** SA1100 ***/
 98 #ifdef LIRC_ON_SA1100
 99 struct sa1100_ser2_registers {
100         /* HSSP control register */
101         unsigned char hscr0;
102         /* UART registers */
103         unsigned char utcr0;
104         unsigned char utcr1;
105         unsigned char utcr2;
106         unsigned char utcr3;
107         unsigned char utcr4;
108         unsigned char utdr;
109         unsigned char utsr0;
110         unsigned char utsr1;
111 } sr;
112 
113 static int irq = IRQ_Ser2ICP;
114 
115 #define LIRC_ON_SA1100_TRANSMITTER_LATENCY 0
116 
117 /* pulse/space ratio of 50/50 */
118 static unsigned long pulse_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY);
119 /* 1000000/freq-pulse_width */
120 static unsigned long space_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY);
121 static unsigned int freq = 38000;      /* modulation frequency */
122 static unsigned int duty_cycle = 50;   /* duty cycle of 50% */
123 
124 #endif
125 
126 #define RBUF_LEN 1024
127 #define WBUF_LEN 1024
128 
129 #define LIRC_DRIVER_NAME "lirc_sir"
130 
131 #define PULSE '['
132 
133 #ifndef LIRC_SIR_TEKRAM
134 /* 9bit * 1s/115200bit in milli seconds = 78.125ms*/
135 #define TIME_CONST (9000000ul/115200ul)
136 #endif
137 
138 
139 /* timeout for sequences in jiffies (=5/100s), must be longer than TIME_CONST */
140 #define SIR_TIMEOUT     (HZ*5/100)
141 
142 #ifndef LIRC_ON_SA1100
143 #ifndef LIRC_IRQ
144 #define LIRC_IRQ 4
145 #endif
146 #ifndef LIRC_PORT
147 /* for external dongles, default to com1 */
148 #if defined(LIRC_SIR_ACTISYS_ACT200L)         || \
149             defined(LIRC_SIR_ACTISYS_ACT220L) || \
150             defined(LIRC_SIR_TEKRAM)
151 #define LIRC_PORT 0x3f8
152 #else
153 /* onboard sir ports are typically com3 */
154 #define LIRC_PORT 0x3e8
155 #endif
156 #endif
157 
158 static int io = LIRC_PORT;
159 static int irq = LIRC_IRQ;
160 static int threshold = 3;
161 #endif
162 
163 static DEFINE_SPINLOCK(timer_lock);
164 static struct timer_list timerlist;
165 /* time of last signal change detected */
166 static struct timeval last_tv = {0, 0};
167 /* time of last UART data ready interrupt */
168 static struct timeval last_intr_tv = {0, 0};
169 static int last_value;
170 
171 static DECLARE_WAIT_QUEUE_HEAD(lirc_read_queue);
172 
173 static DEFINE_SPINLOCK(hardware_lock);
174 
175 static int rx_buf[RBUF_LEN];
176 static unsigned int rx_tail, rx_head;
177 
178 static bool debug;
179 #define dprintk(fmt, args...)                                           \
180         do {                                                            \
181                 if (debug)                                              \
182                         printk(KERN_DEBUG LIRC_DRIVER_NAME ": "         \
183                                 fmt, ## args);                          \
184         } while (0)
185 
186 /* SECTION: Prototypes */
187 
188 /* Communication with user-space */
189 static unsigned int lirc_poll(struct file *file, poll_table *wait);
190 static ssize_t lirc_read(struct file *file, char __user *buf, size_t count,
191                          loff_t *ppos);
192 static ssize_t lirc_write(struct file *file, const char __user *buf, size_t n,
193                           loff_t *pos);
194 static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
195 static void add_read_queue(int flag, unsigned long val);
196 static int init_chrdev(void);
197 static void drop_chrdev(void);
198 /* Hardware */
199 static irqreturn_t sir_interrupt(int irq, void *dev_id);
200 static void send_space(unsigned long len);
201 static void send_pulse(unsigned long len);
202 static int init_hardware(void);
203 static void drop_hardware(void);
204 /* Initialisation */
205 static int init_port(void);
206 static void drop_port(void);
207 
208 #ifdef LIRC_ON_SA1100
209 static void on(void)
210 {
211         PPSR |= PPC_TXD2;
212 }
213 
214 static void off(void)
215 {
216         PPSR &= ~PPC_TXD2;
217 }
218 #else
219 static inline unsigned int sinp(int offset)
220 {
221         return inb(io + offset);
222 }
223 
224 static inline void soutp(int offset, int value)
225 {
226         outb(value, io + offset);
227 }
228 #endif
229 
230 #ifndef MAX_UDELAY_MS
231 #define MAX_UDELAY_US 5000
232 #else
233 #define MAX_UDELAY_US (MAX_UDELAY_MS*1000)
234 #endif
235 
236 static void safe_udelay(unsigned long usecs)
237 {
238         while (usecs > MAX_UDELAY_US) {
239                 udelay(MAX_UDELAY_US);
240                 usecs -= MAX_UDELAY_US;
241         }
242         udelay(usecs);
243 }
244 
245 /* SECTION: Communication with user-space */
246 
247 static unsigned int lirc_poll(struct file *file, poll_table *wait)
248 {
249         poll_wait(file, &lirc_read_queue, wait);
250         if (rx_head != rx_tail)
251                 return POLLIN | POLLRDNORM;
252         return 0;
253 }
254 
255 static ssize_t lirc_read(struct file *file, char __user *buf, size_t count,
256                          loff_t *ppos)
257 {
258         int n = 0;
259         int retval = 0;
260         DECLARE_WAITQUEUE(wait, current);
261 
262         if (count % sizeof(int))
263                 return -EINVAL;
264 
265         add_wait_queue(&lirc_read_queue, &wait);
266         set_current_state(TASK_INTERRUPTIBLE);
267         while (n < count) {
268                 if (rx_head != rx_tail) {
269                         if (copy_to_user(buf + n,
270                                          rx_buf + rx_head,
271                                          sizeof(int))) {
272                                 retval = -EFAULT;
273                                 break;
274                         }
275                         rx_head = (rx_head + 1) & (RBUF_LEN - 1);
276                         n += sizeof(int);
277                 } else {
278                         if (file->f_flags & O_NONBLOCK) {
279                                 retval = -EAGAIN;
280                                 break;
281                         }
282                         if (signal_pending(current)) {
283                                 retval = -ERESTARTSYS;
284                                 break;
285                         }
286                         schedule();
287                         set_current_state(TASK_INTERRUPTIBLE);
288                 }
289         }
290         remove_wait_queue(&lirc_read_queue, &wait);
291         set_current_state(TASK_RUNNING);
292         return n ? n : retval;
293 }
294 static ssize_t lirc_write(struct file *file, const char __user *buf, size_t n,
295                           loff_t *pos)
296 {
297         unsigned long flags;
298         int i, count;
299         int *tx_buf;
300 
301         count = n / sizeof(int);
302         if (n % sizeof(int) || count % 2 == 0)
303                 return -EINVAL;
304         tx_buf = memdup_user(buf, n);
305         if (IS_ERR(tx_buf))
306                 return PTR_ERR(tx_buf);
307         i = 0;
308 #ifdef LIRC_ON_SA1100
309         /* disable receiver */
310         Ser2UTCR3 = 0;
311 #endif
312         local_irq_save(flags);
313         while (1) {
314                 if (i >= count)
315                         break;
316                 if (tx_buf[i])
317                         send_pulse(tx_buf[i]);
318                 i++;
319                 if (i >= count)
320                         break;
321                 if (tx_buf[i])
322                         send_space(tx_buf[i]);
323                 i++;
324         }
325         local_irq_restore(flags);
326 #ifdef LIRC_ON_SA1100
327         off();
328         udelay(1000); /* wait 1ms for IR diode to recover */
329         Ser2UTCR3 = 0;
330         /* clear status register to prevent unwanted interrupts */
331         Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
332         /* enable receiver */
333         Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE;
334 #endif
335         kfree(tx_buf);
336         return count;
337 }
338 
339 static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
340 {
341         u32 __user *uptr = (u32 __user *)arg;
342         int retval = 0;
343         u32 value = 0;
344 #ifdef LIRC_ON_SA1100
345 
346         if (cmd == LIRC_GET_FEATURES)
347                 value = LIRC_CAN_SEND_PULSE |
348                         LIRC_CAN_SET_SEND_DUTY_CYCLE |
349                         LIRC_CAN_SET_SEND_CARRIER |
350                         LIRC_CAN_REC_MODE2;
351         else if (cmd == LIRC_GET_SEND_MODE)
352                 value = LIRC_MODE_PULSE;
353         else if (cmd == LIRC_GET_REC_MODE)
354                 value = LIRC_MODE_MODE2;
355 #else
356         if (cmd == LIRC_GET_FEATURES)
357                 value = LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2;
358         else if (cmd == LIRC_GET_SEND_MODE)
359                 value = LIRC_MODE_PULSE;
360         else if (cmd == LIRC_GET_REC_MODE)
361                 value = LIRC_MODE_MODE2;
362 #endif
363 
364         switch (cmd) {
365         case LIRC_GET_FEATURES:
366         case LIRC_GET_SEND_MODE:
367         case LIRC_GET_REC_MODE:
368                 retval = put_user(value, uptr);
369                 break;
370 
371         case LIRC_SET_SEND_MODE:
372         case LIRC_SET_REC_MODE:
373                 retval = get_user(value, uptr);
374                 break;
375 #ifdef LIRC_ON_SA1100
376         case LIRC_SET_SEND_DUTY_CYCLE:
377                 retval = get_user(value, uptr);
378                 if (retval)
379                         return retval;
380                 if (value <= 0 || value > 100)
381                         return -EINVAL;
382                 /* (value/100)*(1000000/freq) */
383                 duty_cycle = value;
384                 pulse_width = (unsigned long) duty_cycle*10000/freq;
385                 space_width = (unsigned long) 1000000L/freq-pulse_width;
386                 if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
387                         pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
388                 if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
389                         space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
390                 break;
391         case LIRC_SET_SEND_CARRIER:
392                 retval = get_user(value, uptr);
393                 if (retval)
394                         return retval;
395                 if (value > 500000 || value < 20000)
396                         return -EINVAL;
397                 freq = value;
398                 pulse_width = (unsigned long) duty_cycle*10000/freq;
399                 space_width = (unsigned long) 1000000L/freq-pulse_width;
400                 if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
401                         pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
402                 if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
403                         space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
404                 break;
405 #endif
406         default:
407                 retval = -ENOIOCTLCMD;
408 
409         }
410 
411         if (retval)
412                 return retval;
413         if (cmd == LIRC_SET_REC_MODE) {
414                 if (value != LIRC_MODE_MODE2)
415                         retval = -ENOSYS;
416         } else if (cmd == LIRC_SET_SEND_MODE) {
417                 if (value != LIRC_MODE_PULSE)
418                         retval = -ENOSYS;
419         }
420 
421         return retval;
422 }
423 
424 static void add_read_queue(int flag, unsigned long val)
425 {
426         unsigned int new_rx_tail;
427         int newval;
428 
429         dprintk("add flag %d with val %lu\n", flag, val);
430 
431         newval = val & PULSE_MASK;
432 
433         /*
434          * statistically, pulses are ~TIME_CONST/2 too long. we could
435          * maybe make this more exact, but this is good enough
436          */
437         if (flag) {
438                 /* pulse */
439                 if (newval > TIME_CONST/2)
440                         newval -= TIME_CONST/2;
441                 else /* should not ever happen */
442                         newval = 1;
443                 newval |= PULSE_BIT;
444         } else {
445                 newval += TIME_CONST/2;
446         }
447         new_rx_tail = (rx_tail + 1) & (RBUF_LEN - 1);
448         if (new_rx_tail == rx_head) {
449                 dprintk("Buffer overrun.\n");
450                 return;
451         }
452         rx_buf[rx_tail] = newval;
453         rx_tail = new_rx_tail;
454         wake_up_interruptible(&lirc_read_queue);
455 }
456 
457 static const struct file_operations lirc_fops = {
458         .owner          = THIS_MODULE,
459         .read           = lirc_read,
460         .write          = lirc_write,
461         .poll           = lirc_poll,
462         .unlocked_ioctl = lirc_ioctl,
463 #ifdef CONFIG_COMPAT
464         .compat_ioctl   = lirc_ioctl,
465 #endif
466         .open           = lirc_dev_fop_open,
467         .release        = lirc_dev_fop_close,
468         .llseek         = no_llseek,
469 };
470 
471 static int set_use_inc(void *data)
472 {
473         return 0;
474 }
475 
476 static void set_use_dec(void *data)
477 {
478 }
479 
480 static struct lirc_driver driver = {
481         .name           = LIRC_DRIVER_NAME,
482         .minor          = -1,
483         .code_length    = 1,
484         .sample_rate    = 0,
485         .data           = NULL,
486         .add_to_buf     = NULL,
487         .set_use_inc    = set_use_inc,
488         .set_use_dec    = set_use_dec,
489         .fops           = &lirc_fops,
490         .dev            = NULL,
491         .owner          = THIS_MODULE,
492 };
493 
494 static struct platform_device *lirc_sir_dev;
495 
496 static int init_chrdev(void)
497 {
498         driver.dev = &lirc_sir_dev->dev;
499         driver.minor = lirc_register_driver(&driver);
500         if (driver.minor < 0) {
501                 pr_err("init_chrdev() failed.\n");
502                 return -EIO;
503         }
504         return 0;
505 }
506 
507 static void drop_chrdev(void)
508 {
509         lirc_unregister_driver(driver.minor);
510 }
511 
512 /* SECTION: Hardware */
513 static long delta(struct timeval *tv1, struct timeval *tv2)
514 {
515         unsigned long deltv;
516 
517         deltv = tv2->tv_sec - tv1->tv_sec;
518         if (deltv > 15)
519                 deltv = 0xFFFFFF;
520         else
521                 deltv = deltv*1000000 +
522                         tv2->tv_usec -
523                         tv1->tv_usec;
524         return deltv;
525 }
526 
527 static void sir_timeout(unsigned long data)
528 {
529         /*
530          * if last received signal was a pulse, but receiving stopped
531          * within the 9 bit frame, we need to finish this pulse and
532          * simulate a signal change to from pulse to space. Otherwise
533          * upper layers will receive two sequences next time.
534          */
535 
536         unsigned long flags;
537         unsigned long pulse_end;
538 
539         /* avoid interference with interrupt */
540         spin_lock_irqsave(&timer_lock, flags);
541         if (last_value) {
542 #ifndef LIRC_ON_SA1100
543                 /* clear unread bits in UART and restart */
544                 outb(UART_FCR_CLEAR_RCVR, io + UART_FCR);
545 #endif
546                 /* determine 'virtual' pulse end: */
547                 pulse_end = delta(&last_tv, &last_intr_tv);
548                 dprintk("timeout add %d for %lu usec\n", last_value, pulse_end);
549                 add_read_queue(last_value, pulse_end);
550                 last_value = 0;
551                 last_tv = last_intr_tv;
552         }
553         spin_unlock_irqrestore(&timer_lock, flags);
554 }
555 
556 static irqreturn_t sir_interrupt(int irq, void *dev_id)
557 {
558         unsigned char data;
559         struct timeval curr_tv;
560         static unsigned long deltv;
561 #ifdef LIRC_ON_SA1100
562         int status;
563         static int n;
564 
565         status = Ser2UTSR0;
566         /*
567          * Deal with any receive errors first.  The bytes in error may be
568          * the only bytes in the receive FIFO, so we do this first.
569          */
570         while (status & UTSR0_EIF) {
571                 int bstat;
572 
573                 if (debug) {
574                         dprintk("EIF\n");
575                         bstat = Ser2UTSR1;
576 
577                         if (bstat & UTSR1_FRE)
578                                 dprintk("frame error\n");
579                         if (bstat & UTSR1_ROR)
580                                 dprintk("receive fifo overrun\n");
581                         if (bstat & UTSR1_PRE)
582                                 dprintk("parity error\n");
583                 }
584 
585                 bstat = Ser2UTDR;
586                 n++;
587                 status = Ser2UTSR0;
588         }
589 
590         if (status & (UTSR0_RFS | UTSR0_RID)) {
591                 do_gettimeofday(&curr_tv);
592                 deltv = delta(&last_tv, &curr_tv);
593                 do {
594                         data = Ser2UTDR;
595                         dprintk("%d data: %u\n", n, (unsigned int) data);
596                         n++;
597                 } while (status & UTSR0_RID && /* do not empty fifo in order to
598                                                 * get UTSR0_RID in any case */
599                       Ser2UTSR1 & UTSR1_RNE); /* data ready */
600 
601                 if (status&UTSR0_RID) {
602                         add_read_queue(0 , deltv - n * TIME_CONST); /*space*/
603                         add_read_queue(1, n * TIME_CONST); /*pulse*/
604                         n = 0;
605                         last_tv = curr_tv;
606                 }
607         }
608 
609         if (status & UTSR0_TFS)
610                 pr_err("transmit fifo not full, shouldn't happen\n");
611 
612         /* We must clear certain bits. */
613         status &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
614         if (status)
615                 Ser2UTSR0 = status;
616 #else
617         unsigned long deltintrtv;
618         unsigned long flags;
619         int iir, lsr;
620 
621         while ((iir = inb(io + UART_IIR) & UART_IIR_ID)) {
622                 switch (iir&UART_IIR_ID) { /* FIXME toto treba preriedit */
623                 case UART_IIR_MSI:
624                         (void) inb(io + UART_MSR);
625                         break;
626                 case UART_IIR_RLSI:
627                         (void) inb(io + UART_LSR);
628                         break;
629                 case UART_IIR_THRI:
630 #if 0
631                         if (lsr & UART_LSR_THRE) /* FIFO is empty */
632                                 outb(data, io + UART_TX)
633 #endif
634                         break;
635                 case UART_IIR_RDI:
636                         /* avoid interference with timer */
637                         spin_lock_irqsave(&timer_lock, flags);
638                         do {
639                                 del_timer(&timerlist);
640                                 data = inb(io + UART_RX);
641                                 do_gettimeofday(&curr_tv);
642                                 deltv = delta(&last_tv, &curr_tv);
643                                 deltintrtv = delta(&last_intr_tv, &curr_tv);
644                                 dprintk("t %lu, d %d\n", deltintrtv, (int)data);
645                                 /*
646                                  * if nothing came in last X cycles,
647                                  * it was gap
648                                  */
649                                 if (deltintrtv > TIME_CONST * threshold) {
650                                         if (last_value) {
651                                                 dprintk("GAP\n");
652                                                 /* simulate signal change */
653                                                 add_read_queue(last_value,
654                                                                deltv -
655                                                                deltintrtv);
656                                                 last_value = 0;
657                                                 last_tv.tv_sec =
658                                                         last_intr_tv.tv_sec;
659                                                 last_tv.tv_usec =
660                                                         last_intr_tv.tv_usec;
661                                                 deltv = deltintrtv;
662                                         }
663                                 }
664                                 data = 1;
665                                 if (data ^ last_value) {
666                                         /*
667                                          * deltintrtv > 2*TIME_CONST, remember?
668                                          * the other case is timeout
669                                          */
670                                         add_read_queue(last_value,
671                                                        deltv-TIME_CONST);
672                                         last_value = data;
673                                         last_tv = curr_tv;
674                                         if (last_tv.tv_usec >= TIME_CONST) {
675                                                 last_tv.tv_usec -= TIME_CONST;
676                                         } else {
677                                                 last_tv.tv_sec--;
678                                                 last_tv.tv_usec += 1000000 -
679                                                         TIME_CONST;
680                                         }
681                                 }
682                                 last_intr_tv = curr_tv;
683                                 if (data) {
684                                         /*
685                                          * start timer for end of
686                                          * sequence detection
687                                          */
688                                         timerlist.expires = jiffies +
689                                                                 SIR_TIMEOUT;
690                                         add_timer(&timerlist);
691                                 }
692 
693                                 lsr = inb(io + UART_LSR);
694                         } while (lsr & UART_LSR_DR); /* data ready */
695                         spin_unlock_irqrestore(&timer_lock, flags);
696                         break;
697                 default:
698                         break;
699                 }
700         }
701 #endif
702         return IRQ_RETVAL(IRQ_HANDLED);
703 }
704 
705 #ifdef LIRC_ON_SA1100
706 static void send_pulse(unsigned long length)
707 {
708         unsigned long k, delay;
709         int flag;
710 
711         if (length == 0)
712                 return;
713         /*
714          * this won't give us the carrier frequency we really want
715          * due to integer arithmetic, but we can accept this inaccuracy
716          */
717 
718         for (k = flag = 0; k < length; k += delay, flag = !flag) {
719                 if (flag) {
720                         off();
721                         delay = space_width;
722                 } else {
723                         on();
724                         delay = pulse_width;
725                 }
726                 safe_udelay(delay);
727         }
728         off();
729 }
730 
731 static void send_space(unsigned long length)
732 {
733         if (length == 0)
734                 return;
735         off();
736         safe_udelay(length);
737 }
738 #else
739 static void send_space(unsigned long len)
740 {
741         safe_udelay(len);
742 }
743 
744 static void send_pulse(unsigned long len)
745 {
746         long bytes_out = len / TIME_CONST;
747 
748         if (bytes_out == 0)
749                 bytes_out++;
750 
751         while (bytes_out--) {
752                 outb(PULSE, io + UART_TX);
753                 /* FIXME treba seriozne cakanie z char/serial.c */
754                 while (!(inb(io + UART_LSR) & UART_LSR_THRE))
755                         ;
756         }
757 }
758 #endif
759 
760 #ifdef CONFIG_SA1100_COLLIE
761 static int sa1100_irda_set_power_collie(int state)
762 {
763         if (state) {
764                 /*
765                  *  0 - off
766                  *  1 - short range, lowest power
767                  *  2 - medium range, medium power
768                  *  3 - maximum range, high power
769                  */
770                 ucb1200_set_io_direction(TC35143_GPIO_IR_ON,
771                                          TC35143_IODIR_OUTPUT);
772                 ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_LOW);
773                 udelay(100);
774         } else {
775                 /* OFF */
776                 ucb1200_set_io_direction(TC35143_GPIO_IR_ON,
777                                          TC35143_IODIR_OUTPUT);
778                 ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_HIGH);
779         }
780         return 0;
781 }
782 #endif
783 
784 static int init_hardware(void)
785 {
786         unsigned long flags;
787 
788         spin_lock_irqsave(&hardware_lock, flags);
789         /* reset UART */
790 #ifdef LIRC_ON_SA1100
791 #ifdef CONFIG_SA1100_COLLIE
792         sa1100_irda_set_power_collie(3);        /* power on */
793 #endif
794         sr.hscr0 = Ser2HSCR0;
795 
796         sr.utcr0 = Ser2UTCR0;
797         sr.utcr1 = Ser2UTCR1;
798         sr.utcr2 = Ser2UTCR2;
799         sr.utcr3 = Ser2UTCR3;
800         sr.utcr4 = Ser2UTCR4;
801 
802         sr.utdr = Ser2UTDR;
803         sr.utsr0 = Ser2UTSR0;
804         sr.utsr1 = Ser2UTSR1;
805 
806         /* configure GPIO */
807         /* output */
808         PPDR |= PPC_TXD2;
809         PSDR |= PPC_TXD2;
810         /* set output to 0 */
811         off();
812 
813         /* Enable HP-SIR modulation, and ensure that the port is disabled. */
814         Ser2UTCR3 = 0;
815         Ser2HSCR0 = sr.hscr0 & (~HSCR0_HSSP);
816 
817         /* clear status register to prevent unwanted interrupts */
818         Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
819 
820         /* 7N1 */
821         Ser2UTCR0 = UTCR0_1StpBit|UTCR0_7BitData;
822         /* 115200 */
823         Ser2UTCR1 = 0;
824         Ser2UTCR2 = 1;
825         /* use HPSIR, 1.6 usec pulses */
826         Ser2UTCR4 = UTCR4_HPSIR|UTCR4_Z1_6us;
827 
828         /* enable receiver, receive fifo interrupt */
829         Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE;
830 
831         /* clear status register to prevent unwanted interrupts */
832         Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
833 
834 #elif defined(LIRC_SIR_TEKRAM)
835         /* disable FIFO */
836         soutp(UART_FCR,
837               UART_FCR_CLEAR_RCVR|
838               UART_FCR_CLEAR_XMIT|
839               UART_FCR_TRIGGER_1);
840 
841         /* Set DLAB 0. */
842         soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
843 
844         /* First of all, disable all interrupts */
845         soutp(UART_IER, sinp(UART_IER) &
846               (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI)));
847 
848         /* Set DLAB 1. */
849         soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
850 
851         /* Set divisor to 12 => 9600 Baud */
852         soutp(UART_DLM, 0);
853         soutp(UART_DLL, 12);
854 
855         /* Set DLAB 0. */
856         soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
857 
858         /* power supply */
859         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
860         safe_udelay(50*1000);
861 
862         /* -DTR low -> reset PIC */
863         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
864         udelay(1*1000);
865 
866         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
867         udelay(100);
868 
869 
870         /* -RTS low -> send control byte */
871         soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
872         udelay(7);
873         soutp(UART_TX, TEKRAM_115200|TEKRAM_PW);
874 
875         /* one byte takes ~1042 usec to transmit at 9600,8N1 */
876         udelay(1500);
877 
878         /* back to normal operation */
879         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
880         udelay(50);
881 
882         udelay(1500);
883 
884         /* read previous control byte */
885         pr_info("0x%02x\n", sinp(UART_RX));
886 
887         /* Set DLAB 1. */
888         soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
889 
890         /* Set divisor to 1 => 115200 Baud */
891         soutp(UART_DLM, 0);
892         soutp(UART_DLL, 1);
893 
894         /* Set DLAB 0, 8 Bit */
895         soutp(UART_LCR, UART_LCR_WLEN8);
896         /* enable interrupts */
897         soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
898 #else
899         outb(0, io + UART_MCR);
900         outb(0, io + UART_IER);
901         /* init UART */
902         /* set DLAB, speed = 115200 */
903         outb(UART_LCR_DLAB | UART_LCR_WLEN7, io + UART_LCR);
904         outb(1, io + UART_DLL); outb(0, io + UART_DLM);
905         /* 7N1+start = 9 bits at 115200 ~ 3 bits at 44000 */
906         outb(UART_LCR_WLEN7, io + UART_LCR);
907         /* FIFO operation */
908         outb(UART_FCR_ENABLE_FIFO, io + UART_FCR);
909         /* interrupts */
910         /* outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, io + UART_IER); */
911         outb(UART_IER_RDI, io + UART_IER);
912         /* turn on UART */
913         outb(UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2, io + UART_MCR);
914 #ifdef LIRC_SIR_ACTISYS_ACT200L
915         init_act200();
916 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
917         init_act220();
918 #endif
919 #endif
920         spin_unlock_irqrestore(&hardware_lock, flags);
921         return 0;
922 }
923 
924 static void drop_hardware(void)
925 {
926         unsigned long flags;
927 
928         spin_lock_irqsave(&hardware_lock, flags);
929 
930 #ifdef LIRC_ON_SA1100
931         Ser2UTCR3 = 0;
932 
933         Ser2UTCR0 = sr.utcr0;
934         Ser2UTCR1 = sr.utcr1;
935         Ser2UTCR2 = sr.utcr2;
936         Ser2UTCR4 = sr.utcr4;
937         Ser2UTCR3 = sr.utcr3;
938 
939         Ser2HSCR0 = sr.hscr0;
940 #ifdef CONFIG_SA1100_COLLIE
941         sa1100_irda_set_power_collie(0);        /* power off */
942 #endif
943 #else
944         /* turn off interrupts */
945         outb(0, io + UART_IER);
946 #endif
947         spin_unlock_irqrestore(&hardware_lock, flags);
948 }
949 
950 /* SECTION: Initialisation */
951 
952 static int init_port(void)
953 {
954         int retval;
955 
956         /* get I/O port access and IRQ line */
957 #ifndef LIRC_ON_SA1100
958         if (request_region(io, 8, LIRC_DRIVER_NAME) == NULL) {
959                 pr_err("i/o port 0x%.4x already in use.\n", io);
960                 return -EBUSY;
961         }
962 #endif
963         retval = request_irq(irq, sir_interrupt, 0,
964                              LIRC_DRIVER_NAME, NULL);
965         if (retval < 0) {
966 #               ifndef LIRC_ON_SA1100
967                 release_region(io, 8);
968 #               endif
969                 pr_err("IRQ %d already in use.\n", irq);
970                 return retval;
971         }
972 #ifndef LIRC_ON_SA1100
973         pr_info("I/O port 0x%.4x, IRQ %d.\n", io, irq);
974 #endif
975 
976         init_timer(&timerlist);
977         timerlist.function = sir_timeout;
978         timerlist.data = 0xabadcafe;
979 
980         return 0;
981 }
982 
983 static void drop_port(void)
984 {
985         free_irq(irq, NULL);
986         del_timer_sync(&timerlist);
987 #ifndef LIRC_ON_SA1100
988         release_region(io, 8);
989 #endif
990 }
991 
992 #ifdef LIRC_SIR_ACTISYS_ACT200L
993 /* Crystal/Cirrus CS8130 IR transceiver, used in Actisys Act200L dongle */
994 /* some code borrowed from Linux IRDA driver */
995 
996 /* Register 0: Control register #1 */
997 #define ACT200L_REG0    0x00
998 #define ACT200L_TXEN    0x01 /* Enable transmitter */
999 #define ACT200L_RXEN    0x02 /* Enable receiver */
1000 #define ACT200L_ECHO    0x08 /* Echo control chars */
1001 
1002 /* Register 1: Control register #2 */
1003 #define ACT200L_REG1    0x10
1004 #define ACT200L_LODB    0x01 /* Load new baud rate count value */
1005 #define ACT200L_WIDE    0x04 /* Expand the maximum allowable pulse */
1006 
1007 /* Register 3: Transmit mode register #2 */
1008 #define ACT200L_REG3    0x30
1009 #define ACT200L_B0      0x01 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P)  */
1010 #define ACT200L_B1      0x02 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P)  */
1011 #define ACT200L_CHSY    0x04 /* StartBit Synced 0=bittime, 1=startbit */
1012 
1013 /* Register 4: Output Power register */
1014 #define ACT200L_REG4    0x40
1015 #define ACT200L_OP0     0x01 /* Enable LED1C output */
1016 #define ACT200L_OP1     0x02 /* Enable LED2C output */
1017 #define ACT200L_BLKR    0x04
1018 
1019 /* Register 5: Receive Mode register */
1020 #define ACT200L_REG5    0x50
1021 #define ACT200L_RWIDL   0x01 /* fixed 1.6us pulse mode */
1022     /*.. other various IRDA bit modes, and TV remote modes..*/
1023 
1024 /* Register 6: Receive Sensitivity register #1 */
1025 #define ACT200L_REG6    0x60
1026 #define ACT200L_RS0     0x01 /* receive threshold bit 0 */
1027 #define ACT200L_RS1     0x02 /* receive threshold bit 1 */
1028 
1029 /* Register 7: Receive Sensitivity register #2 */
1030 #define ACT200L_REG7    0x70
1031 #define ACT200L_ENPOS   0x04 /* Ignore the falling edge */
1032 
1033 /* Register 8,9: Baud Rate Divider register #1,#2 */
1034 #define ACT200L_REG8    0x80
1035 #define ACT200L_REG9    0x90
1036 
1037 #define ACT200L_2400    0x5f
1038 #define ACT200L_9600    0x17
1039 #define ACT200L_19200   0x0b
1040 #define ACT200L_38400   0x05
1041 #define ACT200L_57600   0x03
1042 #define ACT200L_115200  0x01
1043 
1044 /* Register 13: Control register #3 */
1045 #define ACT200L_REG13   0xd0
1046 #define ACT200L_SHDW    0x01 /* Enable access to shadow registers */
1047 
1048 /* Register 15: Status register */
1049 #define ACT200L_REG15   0xf0
1050 
1051 /* Register 21: Control register #4 */
1052 #define ACT200L_REG21   0x50
1053 #define ACT200L_EXCK    0x02 /* Disable clock output driver */
1054 #define ACT200L_OSCL    0x04 /* oscillator in low power, medium accuracy mode */
1055 
1056 static void init_act200(void)
1057 {
1058         int i;
1059         __u8 control[] = {
1060                 ACT200L_REG15,
1061                 ACT200L_REG13 | ACT200L_SHDW,
1062                 ACT200L_REG21 | ACT200L_EXCK | ACT200L_OSCL,
1063                 ACT200L_REG13,
1064                 ACT200L_REG7  | ACT200L_ENPOS,
1065                 ACT200L_REG6  | ACT200L_RS0  | ACT200L_RS1,
1066                 ACT200L_REG5  | ACT200L_RWIDL,
1067                 ACT200L_REG4  | ACT200L_OP0  | ACT200L_OP1 | ACT200L_BLKR,
1068                 ACT200L_REG3  | ACT200L_B0,
1069                 ACT200L_REG0  | ACT200L_TXEN | ACT200L_RXEN,
1070                 ACT200L_REG8 |  (ACT200L_115200       & 0x0f),
1071                 ACT200L_REG9 | ((ACT200L_115200 >> 4) & 0x0f),
1072                 ACT200L_REG1 | ACT200L_LODB | ACT200L_WIDE
1073         };
1074 
1075         /* Set DLAB 1. */
1076         soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
1077 
1078         /* Set divisor to 12 => 9600 Baud */
1079         soutp(UART_DLM, 0);
1080         soutp(UART_DLL, 12);
1081 
1082         /* Set DLAB 0. */
1083         soutp(UART_LCR, UART_LCR_WLEN8);
1084         /* Set divisor to 12 => 9600 Baud */
1085 
1086         /* power supply */
1087         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1088         for (i = 0; i < 50; i++)
1089                 safe_udelay(1000);
1090 
1091                 /* Reset the dongle : set RTS low for 25 ms */
1092         soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
1093         for (i = 0; i < 25; i++)
1094                 udelay(1000);
1095 
1096         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1097         udelay(100);
1098 
1099         /* Clear DTR and set RTS to enter command mode */
1100         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
1101         udelay(7);
1102 
1103         /* send out the control register settings for 115K 7N1 SIR operation */
1104         for (i = 0; i < sizeof(control); i++) {
1105                 soutp(UART_TX, control[i]);
1106                 /* one byte takes ~1042 usec to transmit at 9600,8N1 */
1107                 udelay(1500);
1108         }
1109 
1110         /* back to normal operation */
1111         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1112         udelay(50);
1113 
1114         udelay(1500);
1115         soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
1116 
1117         /* Set DLAB 1. */
1118         soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
1119 
1120         /* Set divisor to 1 => 115200 Baud */
1121         soutp(UART_DLM, 0);
1122         soutp(UART_DLL, 1);
1123 
1124         /* Set DLAB 0. */
1125         soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
1126 
1127         /* Set DLAB 0, 7 Bit */
1128         soutp(UART_LCR, UART_LCR_WLEN7);
1129 
1130         /* enable interrupts */
1131         soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
1132 }
1133 #endif
1134 
1135 #ifdef LIRC_SIR_ACTISYS_ACT220L
1136 /*
1137  * Derived from linux IrDA driver (net/irda/actisys.c)
1138  * Drop me a mail for any kind of comment: maxx@spaceboyz.net
1139  */
1140 
1141 void init_act220(void)
1142 {
1143         int i;
1144 
1145         /* DLAB 1 */
1146         soutp(UART_LCR, UART_LCR_DLAB|UART_LCR_WLEN7);
1147 
1148         /* 9600 baud */
1149         soutp(UART_DLM, 0);
1150         soutp(UART_DLL, 12);
1151 
1152         /* DLAB 0 */
1153         soutp(UART_LCR, UART_LCR_WLEN7);
1154 
1155         /* reset the dongle, set DTR low for 10us */
1156         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
1157         udelay(10);
1158 
1159         /* back to normal (still 9600) */
1160         soutp(UART_MCR, UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2);
1161 
1162         /*
1163          * send RTS pulses until we reach 115200
1164          * i hope this is really the same for act220l/act220l+
1165          */
1166         for (i = 0; i < 3; i++) {
1167                 udelay(10);
1168                 /* set RTS low for 10 us */
1169                 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
1170                 udelay(10);
1171                 /* set RTS high for 10 us */
1172                 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1173         }
1174 
1175         /* back to normal operation */
1176         udelay(1500); /* better safe than sorry ;) */
1177 
1178         /* Set DLAB 1. */
1179         soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
1180 
1181         /* Set divisor to 1 => 115200 Baud */
1182         soutp(UART_DLM, 0);
1183         soutp(UART_DLL, 1);
1184 
1185         /* Set DLAB 0, 7 Bit */
1186         /* The dongle doesn't seem to have any problems with operation at 7N1 */
1187         soutp(UART_LCR, UART_LCR_WLEN7);
1188 
1189         /* enable interrupts */
1190         soutp(UART_IER, UART_IER_RDI);
1191 }
1192 #endif
1193 
1194 static int init_lirc_sir(void)
1195 {
1196         int retval;
1197 
1198         init_waitqueue_head(&lirc_read_queue);
1199         retval = init_port();
1200         if (retval < 0)
1201                 return retval;
1202         init_hardware();
1203         pr_info("Installed.\n");
1204         return 0;
1205 }
1206 
1207 static int lirc_sir_probe(struct platform_device *dev)
1208 {
1209         return 0;
1210 }
1211 
1212 static int lirc_sir_remove(struct platform_device *dev)
1213 {
1214         return 0;
1215 }
1216 
1217 static struct platform_driver lirc_sir_driver = {
1218         .probe          = lirc_sir_probe,
1219         .remove         = lirc_sir_remove,
1220         .driver         = {
1221                 .name   = "lirc_sir",
1222                 .owner  = THIS_MODULE,
1223         },
1224 };
1225 
1226 static int __init lirc_sir_init(void)
1227 {
1228         int retval;
1229 
1230         retval = platform_driver_register(&lirc_sir_driver);
1231         if (retval) {
1232                 pr_err("Platform driver register failed!\n");
1233                 return -ENODEV;
1234         }
1235 
1236         lirc_sir_dev = platform_device_alloc("lirc_dev", 0);
1237         if (!lirc_sir_dev) {
1238                 pr_err("Platform device alloc failed!\n");
1239                 retval = -ENOMEM;
1240                 goto pdev_alloc_fail;
1241         }
1242 
1243         retval = platform_device_add(lirc_sir_dev);
1244         if (retval) {
1245                 pr_err("Platform device add failed!\n");
1246                 retval = -ENODEV;
1247                 goto pdev_add_fail;
1248         }
1249 
1250         retval = init_chrdev();
1251         if (retval < 0)
1252                 goto fail;
1253 
1254         retval = init_lirc_sir();
1255         if (retval) {
1256                 drop_chrdev();
1257                 goto fail;
1258         }
1259 
1260         return 0;
1261 
1262 fail:
1263         platform_device_del(lirc_sir_dev);
1264 pdev_add_fail:
1265         platform_device_put(lirc_sir_dev);
1266 pdev_alloc_fail:
1267         platform_driver_unregister(&lirc_sir_driver);
1268         return retval;
1269 }
1270 
1271 static void __exit lirc_sir_exit(void)
1272 {
1273         drop_hardware();
1274         drop_chrdev();
1275         drop_port();
1276         platform_device_unregister(lirc_sir_dev);
1277         platform_driver_unregister(&lirc_sir_driver);
1278         pr_info("Uninstalled.\n");
1279 }
1280 
1281 module_init(lirc_sir_init);
1282 module_exit(lirc_sir_exit);
1283 
1284 #ifdef LIRC_SIR_TEKRAM
1285 MODULE_DESCRIPTION("Infrared receiver driver for Tekram Irmate 210");
1286 MODULE_AUTHOR("Christoph Bartelmus");
1287 #elif defined(LIRC_ON_SA1100)
1288 MODULE_DESCRIPTION("LIRC driver for StrongARM SA1100 embedded microprocessor");
1289 MODULE_AUTHOR("Christoph Bartelmus");
1290 #elif defined(LIRC_SIR_ACTISYS_ACT200L)
1291 MODULE_DESCRIPTION("LIRC driver for Actisys Act200L");
1292 MODULE_AUTHOR("Karl Bongers");
1293 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
1294 MODULE_DESCRIPTION("LIRC driver for Actisys Act220L(+)");
1295 MODULE_AUTHOR("Jan Roemisch");
1296 #else
1297 MODULE_DESCRIPTION("Infrared receiver driver for SIR type serial ports");
1298 MODULE_AUTHOR("Milan Pikula");
1299 #endif
1300 MODULE_LICENSE("GPL");
1301 
1302 #ifdef LIRC_ON_SA1100
1303 module_param(irq, int, S_IRUGO);
1304 MODULE_PARM_DESC(irq, "Interrupt (16)");
1305 #else
1306 module_param(io, int, S_IRUGO);
1307 MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)");
1308 
1309 module_param(irq, int, S_IRUGO);
1310 MODULE_PARM_DESC(irq, "Interrupt (4 or 3)");
1311 
1312 module_param(threshold, int, S_IRUGO);
1313 MODULE_PARM_DESC(threshold, "space detection threshold (3)");
1314 #endif
1315 
1316 module_param(debug, bool, S_IRUGO | S_IWUSR);
1317 MODULE_PARM_DESC(debug, "Enable debugging messages");
1318 

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