Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/staging/media/dt3155v4l/dt3155v4l.c

  1 /***************************************************************************
  2  *   Copyright (C) 2006-2010 by Marin Mitov                                *
  3  *   mitov@issp.bas.bg                                                     *
  4  *                                                                         *
  5  *   This program is free software; you can redistribute it and/or modify  *
  6  *   it under the terms of the GNU General Public License as published by  *
  7  *   the Free Software Foundation; either version 2 of the License, or     *
  8  *   (at your option) any later version.                                   *
  9  *                                                                         *
 10  *   This program is distributed in the hope that it will be useful,       *
 11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 13  *   GNU General Public License for more details.                          *
 14  *                                                                         *
 15  *   You should have received a copy of the GNU General Public License     *
 16  *   along with this program; if not, write to the                         *
 17  *   Free Software Foundation, Inc.,                                       *
 18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
 19  ***************************************************************************/
 20 
 21 #include <linux/module.h>
 22 #include <linux/version.h>
 23 #include <linux/stringify.h>
 24 #include <linux/delay.h>
 25 #include <linux/kthread.h>
 26 #include <linux/slab.h>
 27 #include <media/v4l2-dev.h>
 28 #include <media/v4l2-ioctl.h>
 29 #include <media/v4l2-common.h>
 30 #include <media/videobuf2-dma-contig.h>
 31 
 32 #include "dt3155v4l.h"
 33 
 34 #define DT3155_DEVICE_ID 0x1223
 35 
 36 /* DT3155_CHUNK_SIZE is 4M (2^22) 8 full size buffers */
 37 #define DT3155_CHUNK_SIZE (1U << 22)
 38 
 39 #define DT3155_COH_FLAGS (GFP_KERNEL | GFP_DMA32 | __GFP_COLD | __GFP_NOWARN)
 40 
 41 #define DT3155_BUF_SIZE (768 * 576)
 42 
 43 #ifdef CONFIG_DT3155_STREAMING
 44 #define DT3155_CAPTURE_METHOD V4L2_CAP_STREAMING
 45 #else
 46 #define DT3155_CAPTURE_METHOD V4L2_CAP_READWRITE
 47 #endif
 48 
 49 /*  global initializers (for all boards)  */
 50 #ifdef CONFIG_DT3155_CCIR
 51 static const u8 csr2_init = VT_50HZ;
 52 #define DT3155_CURRENT_NORM V4L2_STD_625_50
 53 static const unsigned int img_width = 768;
 54 static const unsigned int img_height = 576;
 55 static const unsigned int frames_per_sec = 25;
 56 static const struct v4l2_fmtdesc frame_std[] = {
 57         {
 58         .index = 0,
 59         .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
 60         .flags = 0,
 61         .description = "CCIR/50Hz 8 bits gray",
 62         .pixelformat = V4L2_PIX_FMT_GREY,
 63         },
 64 };
 65 #else
 66 static const u8 csr2_init = VT_60HZ;
 67 #define DT3155_CURRENT_NORM V4L2_STD_525_60
 68 static const unsigned int img_width = 640;
 69 static const unsigned int img_height = 480;
 70 static const unsigned int frames_per_sec = 30;
 71 static const struct v4l2_fmtdesc frame_std[] = {
 72         {
 73         .index = 0,
 74         .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
 75         .flags = 0,
 76         .description = "RS-170/60Hz 8 bits gray",
 77         .pixelformat = V4L2_PIX_FMT_GREY,
 78         },
 79 };
 80 #endif
 81 
 82 #define NUM_OF_FORMATS ARRAY_SIZE(frame_std)
 83 
 84 static u8 config_init = ACQ_MODE_EVEN;
 85 
 86 /**
 87  * read_i2c_reg - reads an internal i2c register
 88  *
 89  * @addr:       dt3155 mmio base address
 90  * @index:      index (internal address) of register to read
 91  * @data:       pointer to byte the read data will be placed in
 92  *
 93  * returns:     zero on success or error code
 94  *
 95  * This function starts reading the specified (by index) register
 96  * and busy waits for the process to finish. The result is placed
 97  * in a byte pointed by data.
 98  */
 99 static int
100 read_i2c_reg(void __iomem *addr, u8 index, u8 *data)
101 {
102         u32 tmp = index;
103 
104         iowrite32((tmp<<17) | IIC_READ, addr + IIC_CSR2);
105         mmiowb();
106         udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */
107         if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
108                 return -EIO; /* error: NEW_CYCLE not cleared */
109         tmp = ioread32(addr + IIC_CSR1);
110         if (tmp & DIRECT_ABORT) {
111                 /* reset DIRECT_ABORT bit */
112                 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
113                 return -EIO; /* error: DIRECT_ABORT set */
114         }
115         *data = tmp>>24;
116         return 0;
117 }
118 
119 /**
120  * write_i2c_reg - writes to an internal i2c register
121  *
122  * @addr:       dt3155 mmio base address
123  * @index:      index (internal address) of register to read
124  * @data:       data to be written
125  *
126  * returns:     zero on success or error code
127  *
128  * This function starts writting the specified (by index) register
129  * and busy waits for the process to finish.
130  */
131 static int
132 write_i2c_reg(void __iomem *addr, u8 index, u8 data)
133 {
134         u32 tmp = index;
135 
136         iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
137         mmiowb();
138         udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
139         if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
140                 return -EIO; /* error: NEW_CYCLE not cleared */
141         if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
142                 /* reset DIRECT_ABORT bit */
143                 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
144                 return -EIO; /* error: DIRECT_ABORT set */
145         }
146         return 0;
147 }
148 
149 /**
150  * write_i2c_reg_nowait - writes to an internal i2c register
151  *
152  * @addr:       dt3155 mmio base address
153  * @index:      index (internal address) of register to read
154  * @data:       data to be written
155  *
156  * This function starts writting the specified (by index) register
157  * and then returns.
158  */
159 static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data)
160 {
161         u32 tmp = index;
162 
163         iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
164         mmiowb();
165 }
166 
167 /**
168  * wait_i2c_reg - waits the read/write to finish
169  *
170  * @addr:       dt3155 mmio base address
171  *
172  * returns:     zero on success or error code
173  *
174  * This function waits reading/writting to finish.
175  */
176 static int wait_i2c_reg(void __iomem *addr)
177 {
178         if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
179                 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
180         if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
181                 return -EIO; /* error: NEW_CYCLE not cleared */
182         if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
183                 /* reset DIRECT_ABORT bit */
184                 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
185                 return -EIO; /* error: DIRECT_ABORT set */
186         }
187         return 0;
188 }
189 
190 static int
191 dt3155_start_acq(struct dt3155_priv *pd)
192 {
193         struct vb2_buffer *vb = pd->curr_buf;
194         dma_addr_t dma_addr;
195 
196         dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
197         iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
198         iowrite32(dma_addr + img_width, pd->regs + ODD_DMA_START);
199         iowrite32(img_width, pd->regs + EVEN_DMA_STRIDE);
200         iowrite32(img_width, pd->regs + ODD_DMA_STRIDE);
201         /* enable interrupts, clear all irq flags */
202         iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
203                         FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
204         iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
205                   FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
206                                                         pd->regs + CSR1);
207         wait_i2c_reg(pd->regs);
208         write_i2c_reg(pd->regs, CONFIG, pd->config);
209         write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
210         write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
211 
212         /*  start the board  */
213         write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
214         return 0; /* success  */
215 }
216 
217 /*
218  *      driver-specific callbacks (vb2_ops)
219  */
220 static int
221 dt3155_queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt,
222                 unsigned int *num_buffers, unsigned int *num_planes,
223                 unsigned int sizes[], void *alloc_ctxs[])
224 
225 {
226         struct dt3155_priv *pd = vb2_get_drv_priv(q);
227         void *ret;
228 
229         if (*num_buffers == 0)
230                 *num_buffers = 1;
231         *num_planes = 1;
232         sizes[0] = img_width * img_height;
233         if (pd->q->alloc_ctx[0])
234                 return 0;
235         ret = vb2_dma_contig_init_ctx(&pd->pdev->dev);
236         if (IS_ERR(ret))
237                 return PTR_ERR(ret);
238         pd->q->alloc_ctx[0] = ret;
239         return 0;
240 }
241 
242 static void
243 dt3155_wait_prepare(struct vb2_queue *q)
244 {
245         struct dt3155_priv *pd = vb2_get_drv_priv(q);
246 
247         mutex_unlock(pd->vdev->lock);
248 }
249 
250 static void
251 dt3155_wait_finish(struct vb2_queue *q)
252 {
253         struct dt3155_priv *pd = vb2_get_drv_priv(q);
254 
255         mutex_lock(pd->vdev->lock);
256 }
257 
258 static int
259 dt3155_buf_prepare(struct vb2_buffer *vb)
260 {
261         vb2_set_plane_payload(vb, 0, img_width * img_height);
262         return 0;
263 }
264 
265 static int
266 dt3155_stop_streaming(struct vb2_queue *q)
267 {
268         struct dt3155_priv *pd = vb2_get_drv_priv(q);
269         struct vb2_buffer *vb;
270 
271         spin_lock_irq(&pd->lock);
272         while (!list_empty(&pd->dmaq)) {
273                 vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
274                 list_del(&vb->done_entry);
275                 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
276         }
277         spin_unlock_irq(&pd->lock);
278         msleep(45); /* irq hendler will stop the hardware */
279         return 0;
280 }
281 
282 static void
283 dt3155_buf_queue(struct vb2_buffer *vb)
284 {
285         struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
286 
287         /*  pd->q->streaming = 1 when dt3155_buf_queue() is invoked  */
288         spin_lock_irq(&pd->lock);
289         if (pd->curr_buf)
290                 list_add_tail(&vb->done_entry, &pd->dmaq);
291         else {
292                 pd->curr_buf = vb;
293                 dt3155_start_acq(pd);
294         }
295         spin_unlock_irq(&pd->lock);
296 }
297 /*
298  *      end driver-specific callbacks
299  */
300 
301 static const struct vb2_ops q_ops = {
302         .queue_setup = dt3155_queue_setup,
303         .wait_prepare = dt3155_wait_prepare,
304         .wait_finish = dt3155_wait_finish,
305         .buf_prepare = dt3155_buf_prepare,
306         .stop_streaming = dt3155_stop_streaming,
307         .buf_queue = dt3155_buf_queue,
308 };
309 
310 static irqreturn_t
311 dt3155_irq_handler_even(int irq, void *dev_id)
312 {
313         struct dt3155_priv *ipd = dev_id;
314         struct vb2_buffer *ivb;
315         dma_addr_t dma_addr;
316         u32 tmp;
317 
318         tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);
319         if (!tmp)
320                 return IRQ_NONE;  /* not our irq */
321         if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {
322                 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
323                                                         ipd->regs + INT_CSR);
324                 ipd->field_count++;
325                 return IRQ_HANDLED; /* start of field irq */
326         }
327         if ((tmp & FLD_START) && (tmp & FLD_END_ODD))
328                 ipd->stats.start_before_end++;
329         /*      check for corrupted fields     */
330 /*      write_i2c_reg(ipd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);       */
331 /*      write_i2c_reg(ipd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);        */
332         tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
333         if (tmp) {
334                 ipd->stats.corrupted_fields++;
335                 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
336                                                 FLD_DN_ODD | FLD_DN_EVEN |
337                                                 CAP_CONT_EVEN | CAP_CONT_ODD,
338                                                         ipd->regs + CSR1);
339                 mmiowb();
340         }
341 
342         spin_lock(&ipd->lock);
343         if (ipd->curr_buf) {
344                 v4l2_get_timestamp(&ipd->curr_buf->v4l2_buf.timestamp);
345                 ipd->curr_buf->v4l2_buf.sequence = (ipd->field_count) >> 1;
346                 vb2_buffer_done(ipd->curr_buf, VB2_BUF_STATE_DONE);
347         }
348 
349         if (!ipd->q->streaming || list_empty(&ipd->dmaq))
350                 goto stop_dma;
351         ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry);
352         list_del(&ivb->done_entry);
353         ipd->curr_buf = ivb;
354         dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0);
355         iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
356         iowrite32(dma_addr + img_width, ipd->regs + ODD_DMA_START);
357         iowrite32(img_width, ipd->regs + EVEN_DMA_STRIDE);
358         iowrite32(img_width, ipd->regs + ODD_DMA_STRIDE);
359         mmiowb();
360         /* enable interrupts, clear all irq flags */
361         iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
362                         FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
363         spin_unlock(&ipd->lock);
364         return IRQ_HANDLED;
365 
366 stop_dma:
367         ipd->curr_buf = NULL;
368         /* stop the board */
369         write_i2c_reg_nowait(ipd->regs, CSR2, ipd->csr2);
370         iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
371                   FLD_DN_ODD | FLD_DN_EVEN, ipd->regs + CSR1);
372         /* disable interrupts, clear all irq flags */
373         iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
374         spin_unlock(&ipd->lock);
375         return IRQ_HANDLED;
376 }
377 
378 static int
379 dt3155_open(struct file *filp)
380 {
381         int ret = 0;
382         struct dt3155_priv *pd = video_drvdata(filp);
383 
384         if (mutex_lock_interruptible(&pd->mux))
385                 return -ERESTARTSYS;
386         if (!pd->users) {
387                 pd->q = kzalloc(sizeof(*pd->q), GFP_KERNEL);
388                 if (!pd->q) {
389                         ret = -ENOMEM;
390                         goto err_alloc_queue;
391                 }
392                 pd->q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
393                 pd->q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
394                 pd->q->io_modes = VB2_READ | VB2_MMAP;
395                 pd->q->ops = &q_ops;
396                 pd->q->mem_ops = &vb2_dma_contig_memops;
397                 pd->q->drv_priv = pd;
398                 pd->curr_buf = NULL;
399                 pd->field_count = 0;
400                 ret = vb2_queue_init(pd->q);
401                 if (ret < 0)
402                         goto err_request_irq;
403                 INIT_LIST_HEAD(&pd->dmaq);
404                 spin_lock_init(&pd->lock);
405                 /* disable all irqs, clear all irq flags */
406                 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,
407                                                 pd->regs + INT_CSR);
408                 ret = request_irq(pd->pdev->irq, dt3155_irq_handler_even,
409                                                 IRQF_SHARED, DT3155_NAME, pd);
410                 if (ret)
411                         goto err_request_irq;
412         }
413         pd->users++;
414         mutex_unlock(&pd->mux);
415         return 0; /* success */
416 err_request_irq:
417         kfree(pd->q);
418         pd->q = NULL;
419 err_alloc_queue:
420         mutex_unlock(&pd->mux);
421         return ret;
422 }
423 
424 static int
425 dt3155_release(struct file *filp)
426 {
427         struct dt3155_priv *pd = video_drvdata(filp);
428 
429         mutex_lock(&pd->mux);
430         pd->users--;
431         BUG_ON(pd->users < 0);
432         if (!pd->users) {
433                 vb2_queue_release(pd->q);
434                 free_irq(pd->pdev->irq, pd);
435                 if (pd->q->alloc_ctx[0])
436                         vb2_dma_contig_cleanup_ctx(pd->q->alloc_ctx[0]);
437                 kfree(pd->q);
438                 pd->q = NULL;
439         }
440         mutex_unlock(&pd->mux);
441         return 0;
442 }
443 
444 static ssize_t
445 dt3155_read(struct file *filp, char __user *user, size_t size, loff_t *loff)
446 {
447         struct dt3155_priv *pd = video_drvdata(filp);
448         ssize_t res;
449 
450         if (mutex_lock_interruptible(&pd->mux))
451                 return -ERESTARTSYS;
452         res = vb2_read(pd->q, user, size, loff, filp->f_flags & O_NONBLOCK);
453         mutex_unlock(&pd->mux);
454         return res;
455 }
456 
457 static unsigned int
458 dt3155_poll(struct file *filp, struct poll_table_struct *polltbl)
459 {
460         struct dt3155_priv *pd = video_drvdata(filp);
461         unsigned int res;
462 
463         mutex_lock(&pd->mux);
464         res = vb2_poll(pd->q, filp, polltbl);
465         mutex_unlock(&pd->mux);
466         return res;
467 }
468 
469 static int
470 dt3155_mmap(struct file *filp, struct vm_area_struct *vma)
471 {
472         struct dt3155_priv *pd = video_drvdata(filp);
473         int res;
474 
475         if (mutex_lock_interruptible(&pd->mux))
476                 return -ERESTARTSYS;
477         res = vb2_mmap(pd->q, vma);
478         mutex_unlock(&pd->mux);
479         return res;
480 }
481 
482 static const struct v4l2_file_operations dt3155_fops = {
483         .owner = THIS_MODULE,
484         .open = dt3155_open,
485         .release = dt3155_release,
486         .read = dt3155_read,
487         .poll = dt3155_poll,
488         .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
489         .mmap = dt3155_mmap,
490 };
491 
492 static int
493 dt3155_ioc_streamon(struct file *filp, void *p, enum v4l2_buf_type type)
494 {
495         struct dt3155_priv *pd = video_drvdata(filp);
496 
497         return vb2_streamon(pd->q, type);
498 }
499 
500 static int
501 dt3155_ioc_streamoff(struct file *filp, void *p, enum v4l2_buf_type type)
502 {
503         struct dt3155_priv *pd = video_drvdata(filp);
504 
505         return vb2_streamoff(pd->q, type);
506 }
507 
508 static int
509 dt3155_ioc_querycap(struct file *filp, void *p, struct v4l2_capability *cap)
510 {
511         struct dt3155_priv *pd = video_drvdata(filp);
512 
513         strcpy(cap->driver, DT3155_NAME);
514         strcpy(cap->card, DT3155_NAME " frame grabber");
515         sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev));
516         cap->version =
517                KERNEL_VERSION(DT3155_VER_MAJ, DT3155_VER_MIN, DT3155_VER_EXT);
518         cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
519                                 DT3155_CAPTURE_METHOD;
520         return 0;
521 }
522 
523 static int
524 dt3155_ioc_enum_fmt_vid_cap(struct file *filp, void *p, struct v4l2_fmtdesc *f)
525 {
526         if (f->index >= NUM_OF_FORMATS)
527                 return -EINVAL;
528         *f = frame_std[f->index];
529         return 0;
530 }
531 
532 static int
533 dt3155_ioc_g_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
534 {
535         if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
536                 return -EINVAL;
537         f->fmt.pix.width = img_width;
538         f->fmt.pix.height = img_height;
539         f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY;
540         f->fmt.pix.field = V4L2_FIELD_NONE;
541         f->fmt.pix.bytesperline = f->fmt.pix.width;
542         f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height;
543         f->fmt.pix.colorspace = 0;
544         f->fmt.pix.priv = 0;
545         return 0;
546 }
547 
548 static int
549 dt3155_ioc_try_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
550 {
551         if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
552                 return -EINVAL;
553         if (f->fmt.pix.width == img_width &&
554                 f->fmt.pix.height == img_height &&
555                 f->fmt.pix.pixelformat == V4L2_PIX_FMT_GREY &&
556                 f->fmt.pix.field == V4L2_FIELD_NONE &&
557                 f->fmt.pix.bytesperline == f->fmt.pix.width &&
558                 f->fmt.pix.sizeimage == f->fmt.pix.width * f->fmt.pix.height)
559                         return 0;
560         else
561                 return -EINVAL;
562 }
563 
564 static int
565 dt3155_ioc_s_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
566 {
567         return dt3155_ioc_g_fmt_vid_cap(filp, p, f);
568 }
569 
570 static int
571 dt3155_ioc_reqbufs(struct file *filp, void *p, struct v4l2_requestbuffers *b)
572 {
573         struct dt3155_priv *pd = video_drvdata(filp);
574 
575         return vb2_reqbufs(pd->q, b);
576 }
577 
578 static int
579 dt3155_ioc_querybuf(struct file *filp, void *p, struct v4l2_buffer *b)
580 {
581         struct dt3155_priv *pd = video_drvdata(filp);
582 
583         return vb2_querybuf(pd->q, b);
584 }
585 
586 static int
587 dt3155_ioc_qbuf(struct file *filp, void *p, struct v4l2_buffer *b)
588 {
589         struct dt3155_priv *pd = video_drvdata(filp);
590 
591         return vb2_qbuf(pd->q, b);
592 }
593 
594 static int
595 dt3155_ioc_dqbuf(struct file *filp, void *p, struct v4l2_buffer *b)
596 {
597         struct dt3155_priv *pd = video_drvdata(filp);
598 
599         return vb2_dqbuf(pd->q, b, filp->f_flags & O_NONBLOCK);
600 }
601 
602 static int
603 dt3155_ioc_querystd(struct file *filp, void *p, v4l2_std_id *norm)
604 {
605         *norm = DT3155_CURRENT_NORM;
606         return 0;
607 }
608 
609 static int
610 dt3155_ioc_g_std(struct file *filp, void *p, v4l2_std_id *norm)
611 {
612         *norm = DT3155_CURRENT_NORM;
613         return 0;
614 }
615 
616 static int
617 dt3155_ioc_s_std(struct file *filp, void *p, v4l2_std_id norm)
618 {
619         if (norm & DT3155_CURRENT_NORM)
620                 return 0;
621         return -EINVAL;
622 }
623 
624 static int
625 dt3155_ioc_enum_input(struct file *filp, void *p, struct v4l2_input *input)
626 {
627         if (input->index)
628                 return -EINVAL;
629         strcpy(input->name, "Coax in");
630         input->type = V4L2_INPUT_TYPE_CAMERA;
631         /*
632          * FIXME: input->std = 0 according to v4l2 API
633          * VIDIOC_G_STD, VIDIOC_S_STD, VIDIOC_QUERYSTD and VIDIOC_ENUMSTD
634          * should return -EINVAL
635          */
636         input->std = DT3155_CURRENT_NORM;
637         input->status = 0;/* FIXME: add sync detection & V4L2_IN_ST_NO_H_LOCK */
638         return 0;
639 }
640 
641 static int
642 dt3155_ioc_g_input(struct file *filp, void *p, unsigned int *i)
643 {
644         *i = 0;
645         return 0;
646 }
647 
648 static int
649 dt3155_ioc_s_input(struct file *filp, void *p, unsigned int i)
650 {
651         if (i)
652                 return -EINVAL;
653         return 0;
654 }
655 
656 static int
657 dt3155_ioc_g_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
658 {
659         if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
660                 return -EINVAL;
661         parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
662         parms->parm.capture.capturemode = 0;
663         parms->parm.capture.timeperframe.numerator = 1001;
664         parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
665         parms->parm.capture.extendedmode = 0;
666         parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
667         return 0;
668 }
669 
670 static int
671 dt3155_ioc_s_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
672 {
673         if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
674                 return -EINVAL;
675         parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
676         parms->parm.capture.capturemode = 0;
677         parms->parm.capture.timeperframe.numerator = 1001;
678         parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
679         parms->parm.capture.extendedmode = 0;
680         parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
681         return 0;
682 }
683 
684 static const struct v4l2_ioctl_ops dt3155_ioctl_ops = {
685         .vidioc_streamon = dt3155_ioc_streamon,
686         .vidioc_streamoff = dt3155_ioc_streamoff,
687         .vidioc_querycap = dt3155_ioc_querycap,
688 /*
689         .vidioc_g_priority = dt3155_ioc_g_priority,
690         .vidioc_s_priority = dt3155_ioc_s_priority,
691 */
692         .vidioc_enum_fmt_vid_cap = dt3155_ioc_enum_fmt_vid_cap,
693         .vidioc_try_fmt_vid_cap = dt3155_ioc_try_fmt_vid_cap,
694         .vidioc_g_fmt_vid_cap = dt3155_ioc_g_fmt_vid_cap,
695         .vidioc_s_fmt_vid_cap = dt3155_ioc_s_fmt_vid_cap,
696         .vidioc_reqbufs = dt3155_ioc_reqbufs,
697         .vidioc_querybuf = dt3155_ioc_querybuf,
698         .vidioc_qbuf = dt3155_ioc_qbuf,
699         .vidioc_dqbuf = dt3155_ioc_dqbuf,
700         .vidioc_querystd = dt3155_ioc_querystd,
701         .vidioc_g_std = dt3155_ioc_g_std,
702         .vidioc_s_std = dt3155_ioc_s_std,
703         .vidioc_enum_input = dt3155_ioc_enum_input,
704         .vidioc_g_input = dt3155_ioc_g_input,
705         .vidioc_s_input = dt3155_ioc_s_input,
706 /*
707         .vidioc_queryctrl = dt3155_ioc_queryctrl,
708         .vidioc_g_ctrl = dt3155_ioc_g_ctrl,
709         .vidioc_s_ctrl = dt3155_ioc_s_ctrl,
710         .vidioc_querymenu = dt3155_ioc_querymenu,
711         .vidioc_g_ext_ctrls = dt3155_ioc_g_ext_ctrls,
712         .vidioc_s_ext_ctrls = dt3155_ioc_s_ext_ctrls,
713 */
714         .vidioc_g_parm = dt3155_ioc_g_parm,
715         .vidioc_s_parm = dt3155_ioc_s_parm,
716 /*
717         .vidioc_cropcap = dt3155_ioc_cropcap,
718         .vidioc_g_crop = dt3155_ioc_g_crop,
719         .vidioc_s_crop = dt3155_ioc_s_crop,
720         .vidioc_enum_framesizes = dt3155_ioc_enum_framesizes,
721         .vidioc_enum_frameintervals = dt3155_ioc_enum_frameintervals,
722 */
723 };
724 
725 static int
726 dt3155_init_board(struct pci_dev *pdev)
727 {
728         struct dt3155_priv *pd = pci_get_drvdata(pdev);
729         void *buf_cpu;
730         dma_addr_t buf_dma;
731         int i;
732         u8 tmp;
733 
734         pci_set_master(pdev); /* dt3155 needs it */
735 
736         /*  resetting the adapter  */
737         iowrite32(FLD_CRPT_ODD | FLD_CRPT_EVEN | FLD_DN_ODD | FLD_DN_EVEN,
738                                                         pd->regs + CSR1);
739         mmiowb();
740         msleep(20);
741 
742         /*  initializing adaper registers  */
743         iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
744         mmiowb();
745         iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
746         iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
747         iowrite32(0x00000020, pd->regs + FIFO_TRIGER);
748         iowrite32(0x00000103, pd->regs + XFER_MODE);
749         iowrite32(0, pd->regs + RETRY_WAIT_CNT);
750         iowrite32(0, pd->regs + INT_CSR);
751         iowrite32(1, pd->regs + EVEN_FLD_MASK);
752         iowrite32(1, pd->regs + ODD_FLD_MASK);
753         iowrite32(0, pd->regs + MASK_LENGTH);
754         iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
755         iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
756         mmiowb();
757 
758         /* verifying that we have a DT3155 board (not just a SAA7116 chip) */
759         read_i2c_reg(pd->regs, DT_ID, &tmp);
760         if (tmp != DT3155_ID)
761                 return -ENODEV;
762 
763         /* initialize AD LUT */
764         write_i2c_reg(pd->regs, AD_ADDR, 0);
765         for (i = 0; i < 256; i++)
766                 write_i2c_reg(pd->regs, AD_LUT, i);
767 
768         /* initialize ADC references */
769         /* FIXME: pos_ref & neg_ref depend on VT_50HZ */
770         write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
771         write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
772         write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
773         write_i2c_reg(pd->regs, AD_CMD, 34);
774         write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
775         write_i2c_reg(pd->regs, AD_CMD, 0);
776 
777         /* initialize PM LUT */
778         write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
779         for (i = 0; i < 256; i++) {
780                 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
781                 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
782         }
783         write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
784         for (i = 0; i < 256; i++) {
785                 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
786                 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
787         }
788         write_i2c_reg(pd->regs, CONFIG, pd->config); /*  ACQ_MODE_EVEN  */
789 
790         /* select channel 1 for input and set sync level */
791         write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
792         write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
793 
794         /* allocate memory, and initialize the DMA machine */
795         buf_cpu = dma_alloc_coherent(&pdev->dev, DT3155_BUF_SIZE, &buf_dma,
796                                                                 GFP_KERNEL);
797         if (!buf_cpu)
798                 return -ENOMEM;
799         iowrite32(buf_dma, pd->regs + EVEN_DMA_START);
800         iowrite32(buf_dma, pd->regs + ODD_DMA_START);
801         iowrite32(0, pd->regs + EVEN_DMA_STRIDE);
802         iowrite32(0, pd->regs + ODD_DMA_STRIDE);
803 
804         /*  Perform a pseudo even field acquire    */
805         iowrite32(FIFO_EN | SRST | CAP_CONT_ODD, pd->regs + CSR1);
806         write_i2c_reg(pd->regs, CSR2, pd->csr2 | SYNC_SNTL);
807         write_i2c_reg(pd->regs, CONFIG, pd->config);
808         write_i2c_reg(pd->regs, EVEN_CSR, CSR_SNGL);
809         write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | SYNC_SNTL);
810         msleep(100);
811         read_i2c_reg(pd->regs, CSR2, &tmp);
812         write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
813         write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
814         write_i2c_reg(pd->regs, CSR2, pd->csr2);
815         iowrite32(FIFO_EN | SRST | FLD_DN_EVEN | FLD_DN_ODD, pd->regs + CSR1);
816 
817         /*  deallocate memory  */
818         dma_free_coherent(&pdev->dev, DT3155_BUF_SIZE, buf_cpu, buf_dma);
819         if (tmp & BUSY_EVEN)
820                 return -EIO;
821         return 0;
822 }
823 
824 static struct video_device dt3155_vdev = {
825         .name = DT3155_NAME,
826         .fops = &dt3155_fops,
827         .ioctl_ops = &dt3155_ioctl_ops,
828         .minor = -1,
829         .release = video_device_release,
830         .tvnorms = DT3155_CURRENT_NORM,
831 };
832 
833 /* same as in drivers/base/dma-coherent.c */
834 struct dma_coherent_mem {
835         void            *virt_base;
836         dma_addr_t      device_base;
837         int             size;
838         int             flags;
839         unsigned long   *bitmap;
840 };
841 
842 static int
843 dt3155_alloc_coherent(struct device *dev, size_t size, int flags)
844 {
845         struct dma_coherent_mem *mem;
846         dma_addr_t dev_base;
847         int pages = size >> PAGE_SHIFT;
848         int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
849 
850         if ((flags & DMA_MEMORY_MAP) == 0)
851                 goto out;
852         if (!size)
853                 goto out;
854         if (dev->dma_mem)
855                 goto out;
856 
857         mem = kzalloc(sizeof(*mem), GFP_KERNEL);
858         if (!mem)
859                 goto out;
860         mem->virt_base = dma_alloc_coherent(dev, size, &dev_base,
861                                                         DT3155_COH_FLAGS);
862         if (!mem->virt_base)
863                 goto err_alloc_coherent;
864         mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
865         if (!mem->bitmap)
866                 goto err_bitmap;
867 
868         /* coherent_dma_mask is already set to 32 bits */
869         mem->device_base = dev_base;
870         mem->size = pages;
871         mem->flags = flags;
872         dev->dma_mem = mem;
873         return DMA_MEMORY_MAP;
874 
875 err_bitmap:
876         dma_free_coherent(dev, size, mem->virt_base, dev_base);
877 err_alloc_coherent:
878         kfree(mem);
879 out:
880         return 0;
881 }
882 
883 static void
884 dt3155_free_coherent(struct device *dev)
885 {
886         struct dma_coherent_mem *mem = dev->dma_mem;
887 
888         if (!mem)
889                 return;
890         dev->dma_mem = NULL;
891         dma_free_coherent(dev, mem->size << PAGE_SHIFT,
892                                         mem->virt_base, mem->device_base);
893         kfree(mem->bitmap);
894         kfree(mem);
895 }
896 
897 static int
898 dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id)
899 {
900         int err;
901         struct dt3155_priv *pd;
902 
903         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
904         if (err)
905                 return -ENODEV;
906         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
907         if (!pd)
908                 return -ENOMEM;
909         pd->vdev = video_device_alloc();
910         if (!pd->vdev)
911                 goto err_video_device_alloc;
912         *pd->vdev = dt3155_vdev;
913         pci_set_drvdata(pdev, pd);    /* for use in dt3155_remove() */
914         video_set_drvdata(pd->vdev, pd);  /* for use in video_fops */
915         pd->users = 0;
916         pd->pdev = pdev;
917         INIT_LIST_HEAD(&pd->dmaq);
918         mutex_init(&pd->mux);
919         pd->vdev->lock = &pd->mux; /* for locking v4l2_file_operations */
920         spin_lock_init(&pd->lock);
921         pd->csr2 = csr2_init;
922         pd->config = config_init;
923         err = pci_enable_device(pdev);
924         if (err)
925                 goto err_enable_dev;
926         err = pci_request_region(pdev, 0, pci_name(pdev));
927         if (err)
928                 goto err_req_region;
929         pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
930         if (!pd->regs) {
931                 err = -ENOMEM;
932                 goto err_pci_iomap;
933         }
934         err = dt3155_init_board(pdev);
935         if (err)
936                 goto err_init_board;
937         err = video_register_device(pd->vdev, VFL_TYPE_GRABBER, -1);
938         if (err)
939                 goto err_init_board;
940         if (dt3155_alloc_coherent(&pdev->dev, DT3155_CHUNK_SIZE,
941                                                         DMA_MEMORY_MAP))
942                 dev_info(&pdev->dev, "preallocated 8 buffers\n");
943         dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev->minor);
944         return 0;  /*   success   */
945 
946 err_init_board:
947         pci_iounmap(pdev, pd->regs);
948 err_pci_iomap:
949         pci_release_region(pdev, 0);
950 err_req_region:
951         pci_disable_device(pdev);
952 err_enable_dev:
953         video_device_release(pd->vdev);
954 err_video_device_alloc:
955         kfree(pd);
956         return err;
957 }
958 
959 static void
960 dt3155_remove(struct pci_dev *pdev)
961 {
962         struct dt3155_priv *pd = pci_get_drvdata(pdev);
963 
964         dt3155_free_coherent(&pdev->dev);
965         video_unregister_device(pd->vdev);
966         pci_iounmap(pdev, pd->regs);
967         pci_release_region(pdev, 0);
968         pci_disable_device(pdev);
969         /*
970          * video_device_release() is invoked automatically
971          * see: struct video_device dt3155_vdev
972          */
973         kfree(pd);
974 }
975 
976 static const struct pci_device_id pci_ids[] = {
977         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, DT3155_DEVICE_ID) },
978         { 0, /* zero marks the end */ },
979 };
980 MODULE_DEVICE_TABLE(pci, pci_ids);
981 
982 static struct pci_driver pci_driver = {
983         .name = DT3155_NAME,
984         .id_table = pci_ids,
985         .probe = dt3155_probe,
986         .remove = dt3155_remove,
987 };
988 
989 module_pci_driver(pci_driver);
990 
991 MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
992 MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>");
993 MODULE_VERSION(DT3155_VERSION);
994 MODULE_LICENSE("GPL");
995 

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