Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/staging/imx-drm/imx-tve.c

  1 /*
  2  * i.MX drm driver - Television Encoder (TVEv2)
  3  *
  4  * Copyright (C) 2013 Philipp Zabel, Pengutronix
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License
  8  * as published by the Free Software Foundation; either version 2
  9  * of the License, or (at your option) any later version.
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  *
 15  * You should have received a copy of the GNU General Public License
 16  * along with this program; if not, write to the Free Software
 17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 18  * MA 02110-1301, USA.
 19  */
 20 
 21 #include <linux/clk.h>
 22 #include <linux/clk-provider.h>
 23 #include <linux/component.h>
 24 #include <linux/module.h>
 25 #include <linux/i2c.h>
 26 #include <linux/regmap.h>
 27 #include <linux/regulator/consumer.h>
 28 #include <linux/spinlock.h>
 29 #include <linux/videodev2.h>
 30 #include <drm/drmP.h>
 31 #include <drm/drm_fb_helper.h>
 32 #include <drm/drm_crtc_helper.h>
 33 #include <video/imx-ipu-v3.h>
 34 
 35 #include "imx-drm.h"
 36 
 37 #define TVE_COM_CONF_REG        0x00
 38 #define TVE_TVDAC0_CONT_REG     0x28
 39 #define TVE_TVDAC1_CONT_REG     0x2c
 40 #define TVE_TVDAC2_CONT_REG     0x30
 41 #define TVE_CD_CONT_REG         0x34
 42 #define TVE_INT_CONT_REG        0x64
 43 #define TVE_STAT_REG            0x68
 44 #define TVE_TST_MODE_REG        0x6c
 45 #define TVE_MV_CONT_REG         0xdc
 46 
 47 /* TVE_COM_CONF_REG */
 48 #define TVE_SYNC_CH_2_EN        BIT(22)
 49 #define TVE_SYNC_CH_1_EN        BIT(21)
 50 #define TVE_SYNC_CH_0_EN        BIT(20)
 51 #define TVE_TV_OUT_MODE_MASK    (0x7 << 12)
 52 #define TVE_TV_OUT_DISABLE      (0x0 << 12)
 53 #define TVE_TV_OUT_CVBS_0       (0x1 << 12)
 54 #define TVE_TV_OUT_CVBS_2       (0x2 << 12)
 55 #define TVE_TV_OUT_CVBS_0_2     (0x3 << 12)
 56 #define TVE_TV_OUT_SVIDEO_0_1   (0x4 << 12)
 57 #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2   (0x5 << 12)
 58 #define TVE_TV_OUT_YPBPR        (0x6 << 12)
 59 #define TVE_TV_OUT_RGB          (0x7 << 12)
 60 #define TVE_TV_STAND_MASK       (0xf << 8)
 61 #define TVE_TV_STAND_HD_1080P30 (0xc << 8)
 62 #define TVE_P2I_CONV_EN         BIT(7)
 63 #define TVE_INP_VIDEO_FORM      BIT(6)
 64 #define TVE_INP_YCBCR_422       (0x0 << 6)
 65 #define TVE_INP_YCBCR_444       (0x1 << 6)
 66 #define TVE_DATA_SOURCE_MASK    (0x3 << 4)
 67 #define TVE_DATA_SOURCE_BUS1    (0x0 << 4)
 68 #define TVE_DATA_SOURCE_BUS2    (0x1 << 4)
 69 #define TVE_DATA_SOURCE_EXT     (0x2 << 4)
 70 #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
 71 #define TVE_IPU_CLK_EN_OFS      3
 72 #define TVE_IPU_CLK_EN          BIT(3)
 73 #define TVE_DAC_SAMP_RATE_OFS   1
 74 #define TVE_DAC_SAMP_RATE_WIDTH 2
 75 #define TVE_DAC_SAMP_RATE_MASK  (0x3 << 1)
 76 #define TVE_DAC_FULL_RATE       (0x0 << 1)
 77 #define TVE_DAC_DIV2_RATE       (0x1 << 1)
 78 #define TVE_DAC_DIV4_RATE       (0x2 << 1)
 79 #define TVE_EN                  BIT(0)
 80 
 81 /* TVE_TVDACx_CONT_REG */
 82 #define TVE_TVDAC_GAIN_MASK     (0x3f << 0)
 83 
 84 /* TVE_CD_CONT_REG */
 85 #define TVE_CD_CH_2_SM_EN       BIT(22)
 86 #define TVE_CD_CH_1_SM_EN       BIT(21)
 87 #define TVE_CD_CH_0_SM_EN       BIT(20)
 88 #define TVE_CD_CH_2_LM_EN       BIT(18)
 89 #define TVE_CD_CH_1_LM_EN       BIT(17)
 90 #define TVE_CD_CH_0_LM_EN       BIT(16)
 91 #define TVE_CD_CH_2_REF_LVL     BIT(10)
 92 #define TVE_CD_CH_1_REF_LVL     BIT(9)
 93 #define TVE_CD_CH_0_REF_LVL     BIT(8)
 94 #define TVE_CD_EN               BIT(0)
 95 
 96 /* TVE_INT_CONT_REG */
 97 #define TVE_FRAME_END_IEN       BIT(13)
 98 #define TVE_CD_MON_END_IEN      BIT(2)
 99 #define TVE_CD_SM_IEN           BIT(1)
100 #define TVE_CD_LM_IEN           BIT(0)
101 
102 /* TVE_TST_MODE_REG */
103 #define TVE_TVDAC_TEST_MODE_MASK        (0x7 << 0)
104 
105 #define con_to_tve(x) container_of(x, struct imx_tve, connector)
106 #define enc_to_tve(x) container_of(x, struct imx_tve, encoder)
107 
108 enum {
109         TVE_MODE_TVOUT,
110         TVE_MODE_VGA,
111 };
112 
113 struct imx_tve {
114         struct drm_connector connector;
115         struct drm_encoder encoder;
116         struct device *dev;
117         spinlock_t lock;        /* register lock */
118         bool enabled;
119         int mode;
120 
121         struct regmap *regmap;
122         struct regulator *dac_reg;
123         struct i2c_adapter *ddc;
124         struct clk *clk;
125         struct clk *di_sel_clk;
126         struct clk_hw clk_hw_di;
127         struct clk *di_clk;
128         int vsync_pin;
129         int hsync_pin;
130 };
131 
132 static void tve_lock(void *__tve)
133 __acquires(&tve->lock)
134 {
135         struct imx_tve *tve = __tve;
136 
137         spin_lock(&tve->lock);
138 }
139 
140 static void tve_unlock(void *__tve)
141 __releases(&tve->lock)
142 {
143         struct imx_tve *tve = __tve;
144 
145         spin_unlock(&tve->lock);
146 }
147 
148 static void tve_enable(struct imx_tve *tve)
149 {
150         int ret;
151 
152         if (!tve->enabled) {
153                 tve->enabled = true;
154                 clk_prepare_enable(tve->clk);
155                 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
156                                          TVE_IPU_CLK_EN | TVE_EN,
157                                          TVE_IPU_CLK_EN | TVE_EN);
158         }
159 
160         /* clear interrupt status register */
161         regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
162 
163         /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
164         if (tve->mode == TVE_MODE_VGA)
165                 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
166         else
167                 regmap_write(tve->regmap, TVE_INT_CONT_REG,
168                              TVE_CD_SM_IEN |
169                              TVE_CD_LM_IEN |
170                              TVE_CD_MON_END_IEN);
171 }
172 
173 static void tve_disable(struct imx_tve *tve)
174 {
175         int ret;
176 
177         if (tve->enabled) {
178                 tve->enabled = false;
179                 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
180                                          TVE_IPU_CLK_EN | TVE_EN, 0);
181                 clk_disable_unprepare(tve->clk);
182         }
183 }
184 
185 static int tve_setup_tvout(struct imx_tve *tve)
186 {
187         return -ENOTSUPP;
188 }
189 
190 static int tve_setup_vga(struct imx_tve *tve)
191 {
192         unsigned int mask;
193         unsigned int val;
194         int ret;
195 
196         /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
197         ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
198                                  TVE_TVDAC_GAIN_MASK, 0x0a);
199         ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
200                                  TVE_TVDAC_GAIN_MASK, 0x0a);
201         ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
202                                  TVE_TVDAC_GAIN_MASK, 0x0a);
203 
204         /* set configuration register */
205         mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
206         val  = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
207         mask |= TVE_TV_STAND_MASK       | TVE_P2I_CONV_EN;
208         val  |= TVE_TV_STAND_HD_1080P30 | 0;
209         mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
210         val  |= TVE_TV_OUT_RGB       | TVE_SYNC_CH_0_EN;
211         ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
212         if (ret < 0) {
213                 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
214                 return ret;
215         }
216 
217         /* set test mode (as documented) */
218         ret = regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
219                                  TVE_TVDAC_TEST_MODE_MASK, 1);
220 
221         return 0;
222 }
223 
224 static enum drm_connector_status imx_tve_connector_detect(
225                                 struct drm_connector *connector, bool force)
226 {
227         return connector_status_connected;
228 }
229 
230 static int imx_tve_connector_get_modes(struct drm_connector *connector)
231 {
232         struct imx_tve *tve = con_to_tve(connector);
233         struct edid *edid;
234         int ret = 0;
235 
236         if (!tve->ddc)
237                 return 0;
238 
239         edid = drm_get_edid(connector, tve->ddc);
240         if (edid) {
241                 drm_mode_connector_update_edid_property(connector, edid);
242                 ret = drm_add_edid_modes(connector, edid);
243                 kfree(edid);
244         }
245 
246         return ret;
247 }
248 
249 static int imx_tve_connector_mode_valid(struct drm_connector *connector,
250                                         struct drm_display_mode *mode)
251 {
252         struct imx_tve *tve = con_to_tve(connector);
253         unsigned long rate;
254 
255         /* pixel clock with 2x oversampling */
256         rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
257         if (rate == mode->clock)
258                 return MODE_OK;
259 
260         /* pixel clock without oversampling */
261         rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
262         if (rate == mode->clock)
263                 return MODE_OK;
264 
265         dev_warn(tve->dev, "ignoring mode %dx%d\n",
266                  mode->hdisplay, mode->vdisplay);
267 
268         return MODE_BAD;
269 }
270 
271 static struct drm_encoder *imx_tve_connector_best_encoder(
272                 struct drm_connector *connector)
273 {
274         struct imx_tve *tve = con_to_tve(connector);
275 
276         return &tve->encoder;
277 }
278 
279 static void imx_tve_encoder_dpms(struct drm_encoder *encoder, int mode)
280 {
281         struct imx_tve *tve = enc_to_tve(encoder);
282         int ret;
283 
284         ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
285                                  TVE_TV_OUT_MODE_MASK, TVE_TV_OUT_DISABLE);
286         if (ret < 0)
287                 dev_err(tve->dev, "failed to disable TVOUT: %d\n", ret);
288 }
289 
290 static bool imx_tve_encoder_mode_fixup(struct drm_encoder *encoder,
291                                        const struct drm_display_mode *mode,
292                                        struct drm_display_mode *adjusted_mode)
293 {
294         return true;
295 }
296 
297 static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
298 {
299         struct imx_tve *tve = enc_to_tve(encoder);
300 
301         tve_disable(tve);
302 
303         switch (tve->mode) {
304         case TVE_MODE_VGA:
305                 imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24,
306                                 tve->hsync_pin, tve->vsync_pin);
307                 break;
308         case TVE_MODE_TVOUT:
309                 imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444);
310                 break;
311         }
312 }
313 
314 static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
315                                      struct drm_display_mode *mode,
316                                      struct drm_display_mode *adjusted_mode)
317 {
318         struct imx_tve *tve = enc_to_tve(encoder);
319         unsigned long rounded_rate;
320         unsigned long rate;
321         int div = 1;
322         int ret;
323 
324         /*
325          * FIXME
326          * we should try 4k * mode->clock first,
327          * and enable 4x oversampling for lower resolutions
328          */
329         rate = 2000UL * mode->clock;
330         clk_set_rate(tve->clk, rate);
331         rounded_rate = clk_get_rate(tve->clk);
332         if (rounded_rate >= rate)
333                 div = 2;
334         clk_set_rate(tve->di_clk, rounded_rate / div);
335 
336         ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
337         if (ret < 0) {
338                 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
339                         ret);
340         }
341 
342         if (tve->mode == TVE_MODE_VGA)
343                 tve_setup_vga(tve);
344         else
345                 tve_setup_tvout(tve);
346 }
347 
348 static void imx_tve_encoder_commit(struct drm_encoder *encoder)
349 {
350         struct imx_tve *tve = enc_to_tve(encoder);
351 
352         tve_enable(tve);
353 }
354 
355 static void imx_tve_encoder_disable(struct drm_encoder *encoder)
356 {
357         struct imx_tve *tve = enc_to_tve(encoder);
358 
359         tve_disable(tve);
360 }
361 
362 static struct drm_connector_funcs imx_tve_connector_funcs = {
363         .dpms = drm_helper_connector_dpms,
364         .fill_modes = drm_helper_probe_single_connector_modes,
365         .detect = imx_tve_connector_detect,
366         .destroy = imx_drm_connector_destroy,
367 };
368 
369 static struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
370         .get_modes = imx_tve_connector_get_modes,
371         .best_encoder = imx_tve_connector_best_encoder,
372         .mode_valid = imx_tve_connector_mode_valid,
373 };
374 
375 static struct drm_encoder_funcs imx_tve_encoder_funcs = {
376         .destroy = imx_drm_encoder_destroy,
377 };
378 
379 static struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
380         .dpms = imx_tve_encoder_dpms,
381         .mode_fixup = imx_tve_encoder_mode_fixup,
382         .prepare = imx_tve_encoder_prepare,
383         .mode_set = imx_tve_encoder_mode_set,
384         .commit = imx_tve_encoder_commit,
385         .disable = imx_tve_encoder_disable,
386 };
387 
388 static irqreturn_t imx_tve_irq_handler(int irq, void *data)
389 {
390         struct imx_tve *tve = data;
391         unsigned int val;
392 
393         regmap_read(tve->regmap, TVE_STAT_REG, &val);
394 
395         /* clear interrupt status register */
396         regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
397 
398         return IRQ_HANDLED;
399 }
400 
401 static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
402                                             unsigned long parent_rate)
403 {
404         struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
405         unsigned int val;
406         int ret;
407 
408         ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
409         if (ret < 0)
410                 return 0;
411 
412         switch (val & TVE_DAC_SAMP_RATE_MASK) {
413         case TVE_DAC_DIV4_RATE:
414                 return parent_rate / 4;
415         case TVE_DAC_DIV2_RATE:
416                 return parent_rate / 2;
417         case TVE_DAC_FULL_RATE:
418         default:
419                 return parent_rate;
420         }
421 
422         return 0;
423 }
424 
425 static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
426                                   unsigned long *prate)
427 {
428         unsigned long div;
429 
430         div = *prate / rate;
431         if (div >= 4)
432                 return *prate / 4;
433         else if (div >= 2)
434                 return *prate / 2;
435         return *prate;
436 }
437 
438 static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
439                                unsigned long parent_rate)
440 {
441         struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
442         unsigned long div;
443         u32 val;
444         int ret;
445 
446         div = parent_rate / rate;
447         if (div >= 4)
448                 val = TVE_DAC_DIV4_RATE;
449         else if (div >= 2)
450                 val = TVE_DAC_DIV2_RATE;
451         else
452                 val = TVE_DAC_FULL_RATE;
453 
454         ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
455                                  TVE_DAC_SAMP_RATE_MASK, val);
456 
457         if (ret < 0) {
458                 dev_err(tve->dev, "failed to set divider: %d\n", ret);
459                 return ret;
460         }
461 
462         return 0;
463 }
464 
465 static struct clk_ops clk_tve_di_ops = {
466         .round_rate = clk_tve_di_round_rate,
467         .set_rate = clk_tve_di_set_rate,
468         .recalc_rate = clk_tve_di_recalc_rate,
469 };
470 
471 static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
472 {
473         const char *tve_di_parent[1];
474         struct clk_init_data init = {
475                 .name = "tve_di",
476                 .ops = &clk_tve_di_ops,
477                 .num_parents = 1,
478                 .flags = 0,
479         };
480 
481         tve_di_parent[0] = __clk_get_name(tve->clk);
482         init.parent_names = (const char **)&tve_di_parent;
483 
484         tve->clk_hw_di.init = &init;
485         tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
486         if (IS_ERR(tve->di_clk)) {
487                 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
488                         PTR_ERR(tve->di_clk));
489                 return PTR_ERR(tve->di_clk);
490         }
491 
492         return 0;
493 }
494 
495 static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
496 {
497         int encoder_type;
498         int ret;
499 
500         encoder_type = tve->mode == TVE_MODE_VGA ?
501                                 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
502 
503         ret = imx_drm_encoder_parse_of(drm, &tve->encoder,
504                                        tve->dev->of_node);
505         if (ret)
506                 return ret;
507 
508         drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
509         drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
510                          encoder_type);
511 
512         drm_connector_helper_add(&tve->connector,
513                         &imx_tve_connector_helper_funcs);
514         drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
515                            DRM_MODE_CONNECTOR_VGA);
516 
517         drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
518 
519         return 0;
520 }
521 
522 static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
523 {
524         return (reg % 4 == 0) && (reg <= 0xdc);
525 }
526 
527 static struct regmap_config tve_regmap_config = {
528         .reg_bits = 32,
529         .val_bits = 32,
530         .reg_stride = 4,
531 
532         .readable_reg = imx_tve_readable_reg,
533 
534         .lock = tve_lock,
535         .unlock = tve_unlock,
536 
537         .max_register = 0xdc,
538 };
539 
540 static const char * const imx_tve_modes[] = {
541         [TVE_MODE_TVOUT]  = "tvout",
542         [TVE_MODE_VGA] = "vga",
543 };
544 
545 static const int of_get_tve_mode(struct device_node *np)
546 {
547         const char *bm;
548         int ret, i;
549 
550         ret = of_property_read_string(np, "fsl,tve-mode", &bm);
551         if (ret < 0)
552                 return ret;
553 
554         for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
555                 if (!strcasecmp(bm, imx_tve_modes[i]))
556                         return i;
557 
558         return -EINVAL;
559 }
560 
561 static int imx_tve_bind(struct device *dev, struct device *master, void *data)
562 {
563         struct platform_device *pdev = to_platform_device(dev);
564         struct drm_device *drm = data;
565         struct device_node *np = dev->of_node;
566         struct device_node *ddc_node;
567         struct imx_tve *tve;
568         struct resource *res;
569         void __iomem *base;
570         unsigned int val;
571         int irq;
572         int ret;
573 
574         tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
575         if (!tve)
576                 return -ENOMEM;
577 
578         tve->dev = dev;
579         spin_lock_init(&tve->lock);
580 
581         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
582         if (ddc_node) {
583                 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
584                 of_node_put(ddc_node);
585         }
586 
587         tve->mode = of_get_tve_mode(np);
588         if (tve->mode != TVE_MODE_VGA) {
589                 dev_err(dev, "only VGA mode supported, currently\n");
590                 return -EINVAL;
591         }
592 
593         if (tve->mode == TVE_MODE_VGA) {
594                 ret = of_property_read_u32(np, "fsl,hsync-pin",
595                                            &tve->hsync_pin);
596 
597                 if (ret < 0) {
598                         dev_err(dev, "failed to get vsync pin\n");
599                         return ret;
600                 }
601 
602                 ret |= of_property_read_u32(np, "fsl,vsync-pin",
603                                             &tve->vsync_pin);
604 
605                 if (ret < 0) {
606                         dev_err(dev, "failed to get vsync pin\n");
607                         return ret;
608                 }
609         }
610 
611         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
612         base = devm_ioremap_resource(dev, res);
613         if (IS_ERR(base))
614                 return PTR_ERR(base);
615 
616         tve_regmap_config.lock_arg = tve;
617         tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
618                                                 &tve_regmap_config);
619         if (IS_ERR(tve->regmap)) {
620                 dev_err(dev, "failed to init regmap: %ld\n",
621                         PTR_ERR(tve->regmap));
622                 return PTR_ERR(tve->regmap);
623         }
624 
625         irq = platform_get_irq(pdev, 0);
626         if (irq < 0) {
627                 dev_err(dev, "failed to get irq\n");
628                 return irq;
629         }
630 
631         ret = devm_request_threaded_irq(dev, irq, NULL,
632                                         imx_tve_irq_handler, IRQF_ONESHOT,
633                                         "imx-tve", tve);
634         if (ret < 0) {
635                 dev_err(dev, "failed to request irq: %d\n", ret);
636                 return ret;
637         }
638 
639         tve->dac_reg = devm_regulator_get(dev, "dac");
640         if (!IS_ERR(tve->dac_reg)) {
641                 regulator_set_voltage(tve->dac_reg, 2750000, 2750000);
642                 ret = regulator_enable(tve->dac_reg);
643                 if (ret)
644                         return ret;
645         }
646 
647         tve->clk = devm_clk_get(dev, "tve");
648         if (IS_ERR(tve->clk)) {
649                 dev_err(dev, "failed to get high speed tve clock: %ld\n",
650                         PTR_ERR(tve->clk));
651                 return PTR_ERR(tve->clk);
652         }
653 
654         /* this is the IPU DI clock input selector, can be parented to tve_di */
655         tve->di_sel_clk = devm_clk_get(dev, "di_sel");
656         if (IS_ERR(tve->di_sel_clk)) {
657                 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
658                         PTR_ERR(tve->di_sel_clk));
659                 return PTR_ERR(tve->di_sel_clk);
660         }
661 
662         ret = tve_clk_init(tve, base);
663         if (ret < 0)
664                 return ret;
665 
666         ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
667         if (ret < 0) {
668                 dev_err(dev, "failed to read configuration register: %d\n", ret);
669                 return ret;
670         }
671         if (val != 0x00100000) {
672                 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
673                 return -ENODEV;
674         }
675 
676         /* disable cable detection for VGA mode */
677         ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
678 
679         ret = imx_tve_register(drm, tve);
680         if (ret)
681                 return ret;
682 
683         dev_set_drvdata(dev, tve);
684 
685         return 0;
686 }
687 
688 static void imx_tve_unbind(struct device *dev, struct device *master,
689         void *data)
690 {
691         struct imx_tve *tve = dev_get_drvdata(dev);
692 
693         tve->connector.funcs->destroy(&tve->connector);
694         tve->encoder.funcs->destroy(&tve->encoder);
695 
696         if (!IS_ERR(tve->dac_reg))
697                 regulator_disable(tve->dac_reg);
698 }
699 
700 static const struct component_ops imx_tve_ops = {
701         .bind   = imx_tve_bind,
702         .unbind = imx_tve_unbind,
703 };
704 
705 static int imx_tve_probe(struct platform_device *pdev)
706 {
707         return component_add(&pdev->dev, &imx_tve_ops);
708 }
709 
710 static int imx_tve_remove(struct platform_device *pdev)
711 {
712         component_del(&pdev->dev, &imx_tve_ops);
713         return 0;
714 }
715 
716 static const struct of_device_id imx_tve_dt_ids[] = {
717         { .compatible = "fsl,imx53-tve", },
718         { /* sentinel */ }
719 };
720 
721 static struct platform_driver imx_tve_driver = {
722         .probe          = imx_tve_probe,
723         .remove         = imx_tve_remove,
724         .driver         = {
725                 .of_match_table = imx_tve_dt_ids,
726                 .name   = "imx-tve",
727                 .owner  = THIS_MODULE,
728         },
729 };
730 
731 module_platform_driver(imx_tve_driver);
732 
733 MODULE_DESCRIPTION("i.MX Television Encoder driver");
734 MODULE_AUTHOR("Philipp Zabel, Pengutronix");
735 MODULE_LICENSE("GPL");
736 MODULE_ALIAS("platform:imx-tve");
737 

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