Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/staging/imx-drm/imx-tve.c

  1 /*
  2  * i.MX drm driver - Television Encoder (TVEv2)
  3  *
  4  * Copyright (C) 2013 Philipp Zabel, Pengutronix
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License
  8  * as published by the Free Software Foundation; either version 2
  9  * of the License, or (at your option) any later version.
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  *
 15  * You should have received a copy of the GNU General Public License
 16  * along with this program; if not, write to the Free Software
 17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 18  * MA 02110-1301, USA.
 19  */
 20 
 21 #include <linux/clk.h>
 22 #include <linux/clk-provider.h>
 23 #include <linux/component.h>
 24 #include <linux/module.h>
 25 #include <linux/i2c.h>
 26 #include <linux/regmap.h>
 27 #include <linux/regulator/consumer.h>
 28 #include <linux/spinlock.h>
 29 #include <linux/videodev2.h>
 30 #include <drm/drmP.h>
 31 #include <drm/drm_fb_helper.h>
 32 #include <drm/drm_crtc_helper.h>
 33 #include <video/imx-ipu-v3.h>
 34 
 35 #include "imx-drm.h"
 36 
 37 #define TVE_COM_CONF_REG        0x00
 38 #define TVE_TVDAC0_CONT_REG     0x28
 39 #define TVE_TVDAC1_CONT_REG     0x2c
 40 #define TVE_TVDAC2_CONT_REG     0x30
 41 #define TVE_CD_CONT_REG         0x34
 42 #define TVE_INT_CONT_REG        0x64
 43 #define TVE_STAT_REG            0x68
 44 #define TVE_TST_MODE_REG        0x6c
 45 #define TVE_MV_CONT_REG         0xdc
 46 
 47 /* TVE_COM_CONF_REG */
 48 #define TVE_SYNC_CH_2_EN        BIT(22)
 49 #define TVE_SYNC_CH_1_EN        BIT(21)
 50 #define TVE_SYNC_CH_0_EN        BIT(20)
 51 #define TVE_TV_OUT_MODE_MASK    (0x7 << 12)
 52 #define TVE_TV_OUT_DISABLE      (0x0 << 12)
 53 #define TVE_TV_OUT_CVBS_0       (0x1 << 12)
 54 #define TVE_TV_OUT_CVBS_2       (0x2 << 12)
 55 #define TVE_TV_OUT_CVBS_0_2     (0x3 << 12)
 56 #define TVE_TV_OUT_SVIDEO_0_1   (0x4 << 12)
 57 #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2   (0x5 << 12)
 58 #define TVE_TV_OUT_YPBPR        (0x6 << 12)
 59 #define TVE_TV_OUT_RGB          (0x7 << 12)
 60 #define TVE_TV_STAND_MASK       (0xf << 8)
 61 #define TVE_TV_STAND_HD_1080P30 (0xc << 8)
 62 #define TVE_P2I_CONV_EN         BIT(7)
 63 #define TVE_INP_VIDEO_FORM      BIT(6)
 64 #define TVE_INP_YCBCR_422       (0x0 << 6)
 65 #define TVE_INP_YCBCR_444       (0x1 << 6)
 66 #define TVE_DATA_SOURCE_MASK    (0x3 << 4)
 67 #define TVE_DATA_SOURCE_BUS1    (0x0 << 4)
 68 #define TVE_DATA_SOURCE_BUS2    (0x1 << 4)
 69 #define TVE_DATA_SOURCE_EXT     (0x2 << 4)
 70 #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
 71 #define TVE_IPU_CLK_EN_OFS      3
 72 #define TVE_IPU_CLK_EN          BIT(3)
 73 #define TVE_DAC_SAMP_RATE_OFS   1
 74 #define TVE_DAC_SAMP_RATE_WIDTH 2
 75 #define TVE_DAC_SAMP_RATE_MASK  (0x3 << 1)
 76 #define TVE_DAC_FULL_RATE       (0x0 << 1)
 77 #define TVE_DAC_DIV2_RATE       (0x1 << 1)
 78 #define TVE_DAC_DIV4_RATE       (0x2 << 1)
 79 #define TVE_EN                  BIT(0)
 80 
 81 /* TVE_TVDACx_CONT_REG */
 82 #define TVE_TVDAC_GAIN_MASK     (0x3f << 0)
 83 
 84 /* TVE_CD_CONT_REG */
 85 #define TVE_CD_CH_2_SM_EN       BIT(22)
 86 #define TVE_CD_CH_1_SM_EN       BIT(21)
 87 #define TVE_CD_CH_0_SM_EN       BIT(20)
 88 #define TVE_CD_CH_2_LM_EN       BIT(18)
 89 #define TVE_CD_CH_1_LM_EN       BIT(17)
 90 #define TVE_CD_CH_0_LM_EN       BIT(16)
 91 #define TVE_CD_CH_2_REF_LVL     BIT(10)
 92 #define TVE_CD_CH_1_REF_LVL     BIT(9)
 93 #define TVE_CD_CH_0_REF_LVL     BIT(8)
 94 #define TVE_CD_EN               BIT(0)
 95 
 96 /* TVE_INT_CONT_REG */
 97 #define TVE_FRAME_END_IEN       BIT(13)
 98 #define TVE_CD_MON_END_IEN      BIT(2)
 99 #define TVE_CD_SM_IEN           BIT(1)
100 #define TVE_CD_LM_IEN           BIT(0)
101 
102 /* TVE_TST_MODE_REG */
103 #define TVE_TVDAC_TEST_MODE_MASK        (0x7 << 0)
104 
105 #define con_to_tve(x) container_of(x, struct imx_tve, connector)
106 #define enc_to_tve(x) container_of(x, struct imx_tve, encoder)
107 
108 enum {
109         TVE_MODE_TVOUT,
110         TVE_MODE_VGA,
111 };
112 
113 struct imx_tve {
114         struct drm_connector connector;
115         struct drm_encoder encoder;
116         struct device *dev;
117         spinlock_t lock;        /* register lock */
118         bool enabled;
119         int mode;
120 
121         struct regmap *regmap;
122         struct regulator *dac_reg;
123         struct i2c_adapter *ddc;
124         struct clk *clk;
125         struct clk *di_sel_clk;
126         struct clk_hw clk_hw_di;
127         struct clk *di_clk;
128         int vsync_pin;
129         int hsync_pin;
130 };
131 
132 static void tve_lock(void *__tve)
133 __acquires(&tve->lock)
134 {
135         struct imx_tve *tve = __tve;
136         spin_lock(&tve->lock);
137 }
138 
139 static void tve_unlock(void *__tve)
140 __releases(&tve->lock)
141 {
142         struct imx_tve *tve = __tve;
143         spin_unlock(&tve->lock);
144 }
145 
146 static void tve_enable(struct imx_tve *tve)
147 {
148         int ret;
149 
150         if (!tve->enabled) {
151                 tve->enabled = true;
152                 clk_prepare_enable(tve->clk);
153                 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
154                                          TVE_IPU_CLK_EN | TVE_EN,
155                                          TVE_IPU_CLK_EN | TVE_EN);
156         }
157 
158         /* clear interrupt status register */
159         regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
160 
161         /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
162         if (tve->mode == TVE_MODE_VGA)
163                 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
164         else
165                 regmap_write(tve->regmap, TVE_INT_CONT_REG,
166                              TVE_CD_SM_IEN |
167                              TVE_CD_LM_IEN |
168                              TVE_CD_MON_END_IEN);
169 }
170 
171 static void tve_disable(struct imx_tve *tve)
172 {
173         int ret;
174 
175         if (tve->enabled) {
176                 tve->enabled = false;
177                 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
178                                          TVE_IPU_CLK_EN | TVE_EN, 0);
179                 clk_disable_unprepare(tve->clk);
180         }
181 }
182 
183 static int tve_setup_tvout(struct imx_tve *tve)
184 {
185         return -ENOTSUPP;
186 }
187 
188 static int tve_setup_vga(struct imx_tve *tve)
189 {
190         unsigned int mask;
191         unsigned int val;
192         int ret;
193 
194         /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
195         ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
196                                  TVE_TVDAC_GAIN_MASK, 0x0a);
197         ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
198                                  TVE_TVDAC_GAIN_MASK, 0x0a);
199         ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
200                                  TVE_TVDAC_GAIN_MASK, 0x0a);
201 
202         /* set configuration register */
203         mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
204         val  = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
205         mask |= TVE_TV_STAND_MASK       | TVE_P2I_CONV_EN;
206         val  |= TVE_TV_STAND_HD_1080P30 | 0;
207         mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
208         val  |= TVE_TV_OUT_RGB       | TVE_SYNC_CH_0_EN;
209         ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
210         if (ret < 0) {
211                 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
212                 return ret;
213         }
214 
215         /* set test mode (as documented) */
216         ret = regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
217                                  TVE_TVDAC_TEST_MODE_MASK, 1);
218 
219         return 0;
220 }
221 
222 static enum drm_connector_status imx_tve_connector_detect(
223                                 struct drm_connector *connector, bool force)
224 {
225         return connector_status_connected;
226 }
227 
228 static int imx_tve_connector_get_modes(struct drm_connector *connector)
229 {
230         struct imx_tve *tve = con_to_tve(connector);
231         struct edid *edid;
232         int ret = 0;
233 
234         if (!tve->ddc)
235                 return 0;
236 
237         edid = drm_get_edid(connector, tve->ddc);
238         if (edid) {
239                 drm_mode_connector_update_edid_property(connector, edid);
240                 ret = drm_add_edid_modes(connector, edid);
241                 kfree(edid);
242         }
243 
244         return ret;
245 }
246 
247 static int imx_tve_connector_mode_valid(struct drm_connector *connector,
248                                         struct drm_display_mode *mode)
249 {
250         struct imx_tve *tve = con_to_tve(connector);
251         unsigned long rate;
252 
253         /* pixel clock with 2x oversampling */
254         rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
255         if (rate == mode->clock)
256                 return MODE_OK;
257 
258         /* pixel clock without oversampling */
259         rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
260         if (rate == mode->clock)
261                 return MODE_OK;
262 
263         dev_warn(tve->dev, "ignoring mode %dx%d\n",
264                  mode->hdisplay, mode->vdisplay);
265 
266         return MODE_BAD;
267 }
268 
269 static struct drm_encoder *imx_tve_connector_best_encoder(
270                 struct drm_connector *connector)
271 {
272         struct imx_tve *tve = con_to_tve(connector);
273 
274         return &tve->encoder;
275 }
276 
277 static void imx_tve_encoder_dpms(struct drm_encoder *encoder, int mode)
278 {
279         struct imx_tve *tve = enc_to_tve(encoder);
280         int ret;
281 
282         ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
283                                  TVE_TV_OUT_MODE_MASK, TVE_TV_OUT_DISABLE);
284         if (ret < 0)
285                 dev_err(tve->dev, "failed to disable TVOUT: %d\n", ret);
286 }
287 
288 static bool imx_tve_encoder_mode_fixup(struct drm_encoder *encoder,
289                                        const struct drm_display_mode *mode,
290                                        struct drm_display_mode *adjusted_mode)
291 {
292         return true;
293 }
294 
295 static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
296 {
297         struct imx_tve *tve = enc_to_tve(encoder);
298 
299         tve_disable(tve);
300 
301         switch (tve->mode) {
302         case TVE_MODE_VGA:
303                 imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24,
304                                 tve->hsync_pin, tve->vsync_pin);
305                 break;
306         case TVE_MODE_TVOUT:
307                 imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444);
308                 break;
309         }
310 }
311 
312 static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
313                                      struct drm_display_mode *mode,
314                                      struct drm_display_mode *adjusted_mode)
315 {
316         struct imx_tve *tve = enc_to_tve(encoder);
317         unsigned long rounded_rate;
318         unsigned long rate;
319         int div = 1;
320         int ret;
321 
322         /*
323          * FIXME
324          * we should try 4k * mode->clock first,
325          * and enable 4x oversampling for lower resolutions
326          */
327         rate = 2000UL * mode->clock;
328         clk_set_rate(tve->clk, rate);
329         rounded_rate = clk_get_rate(tve->clk);
330         if (rounded_rate >= rate)
331                 div = 2;
332         clk_set_rate(tve->di_clk, rounded_rate / div);
333 
334         ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
335         if (ret < 0) {
336                 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
337                         ret);
338         }
339 
340         if (tve->mode == TVE_MODE_VGA)
341                 tve_setup_vga(tve);
342         else
343                 tve_setup_tvout(tve);
344 }
345 
346 static void imx_tve_encoder_commit(struct drm_encoder *encoder)
347 {
348         struct imx_tve *tve = enc_to_tve(encoder);
349 
350         tve_enable(tve);
351 }
352 
353 static void imx_tve_encoder_disable(struct drm_encoder *encoder)
354 {
355         struct imx_tve *tve = enc_to_tve(encoder);
356 
357         tve_disable(tve);
358 }
359 
360 static struct drm_connector_funcs imx_tve_connector_funcs = {
361         .dpms = drm_helper_connector_dpms,
362         .fill_modes = drm_helper_probe_single_connector_modes,
363         .detect = imx_tve_connector_detect,
364         .destroy = imx_drm_connector_destroy,
365 };
366 
367 static struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
368         .get_modes = imx_tve_connector_get_modes,
369         .best_encoder = imx_tve_connector_best_encoder,
370         .mode_valid = imx_tve_connector_mode_valid,
371 };
372 
373 static struct drm_encoder_funcs imx_tve_encoder_funcs = {
374         .destroy = imx_drm_encoder_destroy,
375 };
376 
377 static struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
378         .dpms = imx_tve_encoder_dpms,
379         .mode_fixup = imx_tve_encoder_mode_fixup,
380         .prepare = imx_tve_encoder_prepare,
381         .mode_set = imx_tve_encoder_mode_set,
382         .commit = imx_tve_encoder_commit,
383         .disable = imx_tve_encoder_disable,
384 };
385 
386 static irqreturn_t imx_tve_irq_handler(int irq, void *data)
387 {
388         struct imx_tve *tve = data;
389         unsigned int val;
390 
391         regmap_read(tve->regmap, TVE_STAT_REG, &val);
392 
393         /* clear interrupt status register */
394         regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
395 
396         return IRQ_HANDLED;
397 }
398 
399 static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
400                                             unsigned long parent_rate)
401 {
402         struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
403         unsigned int val;
404         int ret;
405 
406         ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
407         if (ret < 0)
408                 return 0;
409 
410         switch (val & TVE_DAC_SAMP_RATE_MASK) {
411         case TVE_DAC_DIV4_RATE:
412                 return parent_rate / 4;
413         case TVE_DAC_DIV2_RATE:
414                 return parent_rate / 2;
415         case TVE_DAC_FULL_RATE:
416         default:
417                 return parent_rate;
418         }
419 
420         return 0;
421 }
422 
423 static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
424                                   unsigned long *prate)
425 {
426         unsigned long div;
427 
428         div = *prate / rate;
429         if (div >= 4)
430                 return *prate / 4;
431         else if (div >= 2)
432                 return *prate / 2;
433         else
434                 return *prate;
435 }
436 
437 static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
438                                unsigned long parent_rate)
439 {
440         struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
441         unsigned long div;
442         u32 val;
443         int ret;
444 
445         div = parent_rate / rate;
446         if (div >= 4)
447                 val = TVE_DAC_DIV4_RATE;
448         else if (div >= 2)
449                 val = TVE_DAC_DIV2_RATE;
450         else
451                 val = TVE_DAC_FULL_RATE;
452 
453         ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
454                                  TVE_DAC_SAMP_RATE_MASK, val);
455 
456         if (ret < 0) {
457                 dev_err(tve->dev, "failed to set divider: %d\n", ret);
458                 return ret;
459         }
460 
461         return 0;
462 }
463 
464 static struct clk_ops clk_tve_di_ops = {
465         .round_rate = clk_tve_di_round_rate,
466         .set_rate = clk_tve_di_set_rate,
467         .recalc_rate = clk_tve_di_recalc_rate,
468 };
469 
470 static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
471 {
472         const char *tve_di_parent[1];
473         struct clk_init_data init = {
474                 .name = "tve_di",
475                 .ops = &clk_tve_di_ops,
476                 .num_parents = 1,
477                 .flags = 0,
478         };
479 
480         tve_di_parent[0] = __clk_get_name(tve->clk);
481         init.parent_names = (const char **)&tve_di_parent;
482 
483         tve->clk_hw_di.init = &init;
484         tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
485         if (IS_ERR(tve->di_clk)) {
486                 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
487                         PTR_ERR(tve->di_clk));
488                 return PTR_ERR(tve->di_clk);
489         }
490 
491         return 0;
492 }
493 
494 static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
495 {
496         int encoder_type;
497         int ret;
498 
499         encoder_type = tve->mode == TVE_MODE_VGA ?
500                                 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
501 
502         ret = imx_drm_encoder_parse_of(drm, &tve->encoder,
503                                        tve->dev->of_node);
504         if (ret)
505                 return ret;
506 
507         drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
508         drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
509                          encoder_type);
510 
511         drm_connector_helper_add(&tve->connector,
512                         &imx_tve_connector_helper_funcs);
513         drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
514                            DRM_MODE_CONNECTOR_VGA);
515 
516         drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
517 
518         return 0;
519 }
520 
521 static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
522 {
523         return (reg % 4 == 0) && (reg <= 0xdc);
524 }
525 
526 static struct regmap_config tve_regmap_config = {
527         .reg_bits = 32,
528         .val_bits = 32,
529         .reg_stride = 4,
530 
531         .readable_reg = imx_tve_readable_reg,
532 
533         .lock = tve_lock,
534         .unlock = tve_unlock,
535 
536         .max_register = 0xdc,
537 };
538 
539 static const char *imx_tve_modes[] = {
540         [TVE_MODE_TVOUT]  = "tvout",
541         [TVE_MODE_VGA] = "vga",
542 };
543 
544 static const int of_get_tve_mode(struct device_node *np)
545 {
546         const char *bm;
547         int ret, i;
548 
549         ret = of_property_read_string(np, "fsl,tve-mode", &bm);
550         if (ret < 0)
551                 return ret;
552 
553         for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
554                 if (!strcasecmp(bm, imx_tve_modes[i]))
555                         return i;
556 
557         return -EINVAL;
558 }
559 
560 static int imx_tve_bind(struct device *dev, struct device *master, void *data)
561 {
562         struct platform_device *pdev = to_platform_device(dev);
563         struct drm_device *drm = data;
564         struct device_node *np = dev->of_node;
565         struct device_node *ddc_node;
566         struct imx_tve *tve;
567         struct resource *res;
568         void __iomem *base;
569         unsigned int val;
570         int irq;
571         int ret;
572 
573         tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
574         if (!tve)
575                 return -ENOMEM;
576 
577         tve->dev = dev;
578         spin_lock_init(&tve->lock);
579 
580         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
581         if (ddc_node) {
582                 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
583                 of_node_put(ddc_node);
584         }
585 
586         tve->mode = of_get_tve_mode(np);
587         if (tve->mode != TVE_MODE_VGA) {
588                 dev_err(dev, "only VGA mode supported, currently\n");
589                 return -EINVAL;
590         }
591 
592         if (tve->mode == TVE_MODE_VGA) {
593                 ret = of_property_read_u32(np, "fsl,hsync-pin",
594                                            &tve->hsync_pin);
595 
596                 if (ret < 0) {
597                         dev_err(dev, "failed to get vsync pin\n");
598                         return ret;
599                 }
600 
601                 ret |= of_property_read_u32(np, "fsl,vsync-pin",
602                                             &tve->vsync_pin);
603 
604                 if (ret < 0) {
605                         dev_err(dev, "failed to get vsync pin\n");
606                         return ret;
607                 }
608         }
609 
610         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
611         base = devm_ioremap_resource(dev, res);
612         if (IS_ERR(base))
613                 return PTR_ERR(base);
614 
615         tve_regmap_config.lock_arg = tve;
616         tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
617                                                 &tve_regmap_config);
618         if (IS_ERR(tve->regmap)) {
619                 dev_err(dev, "failed to init regmap: %ld\n",
620                         PTR_ERR(tve->regmap));
621                 return PTR_ERR(tve->regmap);
622         }
623 
624         irq = platform_get_irq(pdev, 0);
625         if (irq < 0) {
626                 dev_err(dev, "failed to get irq\n");
627                 return irq;
628         }
629 
630         ret = devm_request_threaded_irq(dev, irq, NULL,
631                                         imx_tve_irq_handler, IRQF_ONESHOT,
632                                         "imx-tve", tve);
633         if (ret < 0) {
634                 dev_err(dev, "failed to request irq: %d\n", ret);
635                 return ret;
636         }
637 
638         tve->dac_reg = devm_regulator_get(dev, "dac");
639         if (!IS_ERR(tve->dac_reg)) {
640                 regulator_set_voltage(tve->dac_reg, 2750000, 2750000);
641                 ret = regulator_enable(tve->dac_reg);
642                 if (ret)
643                         return ret;
644         }
645 
646         tve->clk = devm_clk_get(dev, "tve");
647         if (IS_ERR(tve->clk)) {
648                 dev_err(dev, "failed to get high speed tve clock: %ld\n",
649                         PTR_ERR(tve->clk));
650                 return PTR_ERR(tve->clk);
651         }
652 
653         /* this is the IPU DI clock input selector, can be parented to tve_di */
654         tve->di_sel_clk = devm_clk_get(dev, "di_sel");
655         if (IS_ERR(tve->di_sel_clk)) {
656                 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
657                         PTR_ERR(tve->di_sel_clk));
658                 return PTR_ERR(tve->di_sel_clk);
659         }
660 
661         ret = tve_clk_init(tve, base);
662         if (ret < 0)
663                 return ret;
664 
665         ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
666         if (ret < 0) {
667                 dev_err(dev, "failed to read configuration register: %d\n", ret);
668                 return ret;
669         }
670         if (val != 0x00100000) {
671                 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
672                 return -ENODEV;
673         }
674 
675         /* disable cable detection for VGA mode */
676         ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
677 
678         ret = imx_tve_register(drm, tve);
679         if (ret)
680                 return ret;
681 
682         dev_set_drvdata(dev, tve);
683 
684         return 0;
685 }
686 
687 static void imx_tve_unbind(struct device *dev, struct device *master,
688         void *data)
689 {
690         struct imx_tve *tve = dev_get_drvdata(dev);
691 
692         tve->connector.funcs->destroy(&tve->connector);
693         tve->encoder.funcs->destroy(&tve->encoder);
694 
695         if (!IS_ERR(tve->dac_reg))
696                 regulator_disable(tve->dac_reg);
697 }
698 
699 static const struct component_ops imx_tve_ops = {
700         .bind   = imx_tve_bind,
701         .unbind = imx_tve_unbind,
702 };
703 
704 static int imx_tve_probe(struct platform_device *pdev)
705 {
706         return component_add(&pdev->dev, &imx_tve_ops);
707 }
708 
709 static int imx_tve_remove(struct platform_device *pdev)
710 {
711         component_del(&pdev->dev, &imx_tve_ops);
712         return 0;
713 }
714 
715 static const struct of_device_id imx_tve_dt_ids[] = {
716         { .compatible = "fsl,imx53-tve", },
717         { /* sentinel */ }
718 };
719 
720 static struct platform_driver imx_tve_driver = {
721         .probe          = imx_tve_probe,
722         .remove         = imx_tve_remove,
723         .driver         = {
724                 .of_match_table = imx_tve_dt_ids,
725                 .name   = "imx-tve",
726                 .owner  = THIS_MODULE,
727         },
728 };
729 
730 module_platform_driver(imx_tve_driver);
731 
732 MODULE_DESCRIPTION("i.MX Television Encoder driver");
733 MODULE_AUTHOR("Philipp Zabel, Pengutronix");
734 MODULE_LICENSE("GPL");
735 MODULE_ALIAS("platform:imx-tve");
736 

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