Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/staging/imx-drm/imx-hdmi.c

  1 /*
  2  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License as published by
  6  * the Free Software Foundation; either version 2 of the License, or
  7  * (at your option) any later version.
  8  *
  9  * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
 10  * for SLISHDMI13T and SLIPHDMIT IP cores
 11  *
 12  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 13  */
 14 
 15 #include <linux/component.h>
 16 #include <linux/irq.h>
 17 #include <linux/delay.h>
 18 #include <linux/err.h>
 19 #include <linux/clk.h>
 20 #include <linux/hdmi.h>
 21 #include <linux/regmap.h>
 22 #include <linux/mfd/syscon.h>
 23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 24 #include <linux/of_device.h>
 25 
 26 #include <drm/drmP.h>
 27 #include <drm/drm_crtc_helper.h>
 28 #include <drm/drm_edid.h>
 29 #include <drm/drm_encoder_slave.h>
 30 
 31 #include "ipu-v3/imx-ipu-v3.h"
 32 #include "imx-hdmi.h"
 33 #include "imx-drm.h"
 34 
 35 #define HDMI_EDID_LEN           512
 36 
 37 #define RGB                     0
 38 #define YCBCR444                1
 39 #define YCBCR422_16BITS         2
 40 #define YCBCR422_8BITS          3
 41 #define XVYCC444                4
 42 
 43 enum hdmi_datamap {
 44         RGB444_8B = 0x01,
 45         RGB444_10B = 0x03,
 46         RGB444_12B = 0x05,
 47         RGB444_16B = 0x07,
 48         YCbCr444_8B = 0x09,
 49         YCbCr444_10B = 0x0B,
 50         YCbCr444_12B = 0x0D,
 51         YCbCr444_16B = 0x0F,
 52         YCbCr422_8B = 0x16,
 53         YCbCr422_10B = 0x14,
 54         YCbCr422_12B = 0x12,
 55 };
 56 
 57 enum imx_hdmi_devtype {
 58         IMX6Q_HDMI,
 59         IMX6DL_HDMI,
 60 };
 61 
 62 static const u16 csc_coeff_default[3][4] = {
 63         { 0x2000, 0x0000, 0x0000, 0x0000 },
 64         { 0x0000, 0x2000, 0x0000, 0x0000 },
 65         { 0x0000, 0x0000, 0x2000, 0x0000 }
 66 };
 67 
 68 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
 69         { 0x2000, 0x6926, 0x74fd, 0x010e },
 70         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
 71         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
 72 };
 73 
 74 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
 75         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
 76         { 0x2000, 0x3264, 0x0000, 0x7e6d },
 77         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
 78 };
 79 
 80 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
 81         { 0x2591, 0x1322, 0x074b, 0x0000 },
 82         { 0x6535, 0x2000, 0x7acc, 0x0200 },
 83         { 0x6acd, 0x7534, 0x2000, 0x0200 }
 84 };
 85 
 86 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
 87         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
 88         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
 89         { 0x6756, 0x78ab, 0x2000, 0x0200 }
 90 };
 91 
 92 struct hdmi_vmode {
 93         bool mdvi;
 94         bool mhsyncpolarity;
 95         bool mvsyncpolarity;
 96         bool minterlaced;
 97         bool mdataenablepolarity;
 98 
 99         unsigned int mpixelclock;
100         unsigned int mpixelrepetitioninput;
101         unsigned int mpixelrepetitionoutput;
102 };
103 
104 struct hdmi_data_info {
105         unsigned int enc_in_format;
106         unsigned int enc_out_format;
107         unsigned int enc_color_depth;
108         unsigned int colorimetry;
109         unsigned int pix_repet_factor;
110         unsigned int hdcp_enable;
111         struct hdmi_vmode video_mode;
112 };
113 
114 struct imx_hdmi {
115         struct drm_connector connector;
116         struct drm_encoder encoder;
117 
118         enum imx_hdmi_devtype dev_type;
119         struct device *dev;
120         struct clk *isfr_clk;
121         struct clk *iahb_clk;
122 
123         enum drm_connector_status connector_status;
124 
125         struct hdmi_data_info hdmi_data;
126         int vic;
127 
128         u8 edid[HDMI_EDID_LEN];
129         bool cable_plugin;
130 
131         bool phy_enabled;
132         struct drm_display_mode previous_mode;
133 
134         struct regmap *regmap;
135         struct i2c_adapter *ddc;
136         void __iomem *regs;
137 
138         unsigned int sample_rate;
139         int ratio;
140 };
141 
142 static void imx_hdmi_set_ipu_di_mux(struct imx_hdmi *hdmi, int ipu_di)
143 {
144         regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
145                            IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
146                            ipu_di << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
147 }
148 
149 static inline void hdmi_writeb(struct imx_hdmi *hdmi, u8 val, int offset)
150 {
151         writeb(val, hdmi->regs + offset);
152 }
153 
154 static inline u8 hdmi_readb(struct imx_hdmi *hdmi, int offset)
155 {
156         return readb(hdmi->regs + offset);
157 }
158 
159 static void hdmi_modb(struct imx_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
160 {
161         u8 val = hdmi_readb(hdmi, reg) & ~mask;
162         val |= data & mask;
163         hdmi_writeb(hdmi, val, reg);
164 }
165 
166 static void hdmi_mask_writeb(struct imx_hdmi *hdmi, u8 data, unsigned int reg,
167                       u8 shift, u8 mask)
168 {
169         hdmi_modb(hdmi, data << shift, mask, reg);
170 }
171 
172 static void hdmi_set_clock_regenerator_n(struct imx_hdmi *hdmi,
173                                          unsigned int value)
174 {
175         hdmi_writeb(hdmi, value & 0xff, HDMI_AUD_N1);
176         hdmi_writeb(hdmi, (value >> 8) & 0xff, HDMI_AUD_N2);
177         hdmi_writeb(hdmi, (value >> 16) & 0x0f, HDMI_AUD_N3);
178 
179         /* nshift factor = 0 */
180         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
181 }
182 
183 static void hdmi_regenerate_cts(struct imx_hdmi *hdmi, unsigned int cts)
184 {
185         /* Must be set/cleared first */
186         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
187 
188         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
189         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
190         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
191                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
192 }
193 
194 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
195                                    unsigned int ratio)
196 {
197         unsigned int n = (128 * freq) / 1000;
198 
199         switch (freq) {
200         case 32000:
201                 if (pixel_clk == 25170000)
202                         n = (ratio == 150) ? 9152 : 4576;
203                 else if (pixel_clk == 27020000)
204                         n = (ratio == 150) ? 8192 : 4096;
205                 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
206                         n = 11648;
207                 else
208                         n = 4096;
209                 break;
210 
211         case 44100:
212                 if (pixel_clk == 25170000)
213                         n = 7007;
214                 else if (pixel_clk == 74170000)
215                         n = 17836;
216                 else if (pixel_clk == 148350000)
217                         n = (ratio == 150) ? 17836 : 8918;
218                 else
219                         n = 6272;
220                 break;
221 
222         case 48000:
223                 if (pixel_clk == 25170000)
224                         n = (ratio == 150) ? 9152 : 6864;
225                 else if (pixel_clk == 27020000)
226                         n = (ratio == 150) ? 8192 : 6144;
227                 else if (pixel_clk == 74170000)
228                         n = 11648;
229                 else if (pixel_clk == 148350000)
230                         n = (ratio == 150) ? 11648 : 5824;
231                 else
232                         n = 6144;
233                 break;
234 
235         case 88200:
236                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
237                 break;
238 
239         case 96000:
240                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
241                 break;
242 
243         case 176400:
244                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
245                 break;
246 
247         case 192000:
248                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
249                 break;
250 
251         default:
252                 break;
253         }
254 
255         return n;
256 }
257 
258 static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
259                                      unsigned int ratio)
260 {
261         unsigned int cts = 0;
262 
263         pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
264                  pixel_clk, ratio);
265 
266         switch (freq) {
267         case 32000:
268                 if (pixel_clk == 297000000) {
269                         cts = 222750;
270                         break;
271                 }
272         case 48000:
273         case 96000:
274         case 192000:
275                 switch (pixel_clk) {
276                 case 25200000:
277                 case 27000000:
278                 case 54000000:
279                 case 74250000:
280                 case 148500000:
281                         cts = pixel_clk / 1000;
282                         break;
283                 case 297000000:
284                         cts = 247500;
285                         break;
286                 /*
287                  * All other TMDS clocks are not supported by
288                  * DWC_hdmi_tx. The TMDS clocks divided or
289                  * multiplied by 1,001 coefficients are not
290                  * supported.
291                  */
292                 default:
293                         break;
294                 }
295                 break;
296         case 44100:
297         case 88200:
298         case 176400:
299                 switch (pixel_clk) {
300                 case 25200000:
301                         cts = 28000;
302                         break;
303                 case 27000000:
304                         cts = 30000;
305                         break;
306                 case 54000000:
307                         cts = 60000;
308                         break;
309                 case 74250000:
310                         cts = 82500;
311                         break;
312                 case 148500000:
313                         cts = 165000;
314                         break;
315                 case 297000000:
316                         cts = 247500;
317                         break;
318                 default:
319                         break;
320                 }
321                 break;
322         default:
323                 break;
324         }
325         if (ratio == 100)
326                 return cts;
327         else
328                 return (cts * ratio) / 100;
329 }
330 
331 static void hdmi_set_clk_regenerator(struct imx_hdmi *hdmi,
332         unsigned long pixel_clk)
333 {
334         unsigned int clk_n, clk_cts;
335 
336         clk_n = hdmi_compute_n(hdmi->sample_rate, pixel_clk,
337                                hdmi->ratio);
338         clk_cts = hdmi_compute_cts(hdmi->sample_rate, pixel_clk,
339                                    hdmi->ratio);
340 
341         if (!clk_cts) {
342                 dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n",
343                          __func__, pixel_clk);
344                 return;
345         }
346 
347         dev_dbg(hdmi->dev, "%s: samplerate=%d  ratio=%d  pixelclk=%lu  N=%d cts=%d\n",
348                 __func__, hdmi->sample_rate, hdmi->ratio,
349                 pixel_clk, clk_n, clk_cts);
350 
351         hdmi_set_clock_regenerator_n(hdmi, clk_n);
352         hdmi_regenerate_cts(hdmi, clk_cts);
353 }
354 
355 static void hdmi_init_clk_regenerator(struct imx_hdmi *hdmi)
356 {
357         hdmi_set_clk_regenerator(hdmi, 74250000);
358 }
359 
360 static void hdmi_clk_regenerator_update_pixel_clock(struct imx_hdmi *hdmi)
361 {
362         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock);
363 }
364 
365 /*
366  * this submodule is responsible for the video data synchronization.
367  * for example, for RGB 4:4:4 input, the data map is defined as
368  *                      pin{47~40} <==> R[7:0]
369  *                      pin{31~24} <==> G[7:0]
370  *                      pin{15~8}  <==> B[7:0]
371  */
372 static void hdmi_video_sample(struct imx_hdmi *hdmi)
373 {
374         int color_format = 0;
375         u8 val;
376 
377         if (hdmi->hdmi_data.enc_in_format == RGB) {
378                 if (hdmi->hdmi_data.enc_color_depth == 8)
379                         color_format = 0x01;
380                 else if (hdmi->hdmi_data.enc_color_depth == 10)
381                         color_format = 0x03;
382                 else if (hdmi->hdmi_data.enc_color_depth == 12)
383                         color_format = 0x05;
384                 else if (hdmi->hdmi_data.enc_color_depth == 16)
385                         color_format = 0x07;
386                 else
387                         return;
388         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
389                 if (hdmi->hdmi_data.enc_color_depth == 8)
390                         color_format = 0x09;
391                 else if (hdmi->hdmi_data.enc_color_depth == 10)
392                         color_format = 0x0B;
393                 else if (hdmi->hdmi_data.enc_color_depth == 12)
394                         color_format = 0x0D;
395                 else if (hdmi->hdmi_data.enc_color_depth == 16)
396                         color_format = 0x0F;
397                 else
398                         return;
399         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
400                 if (hdmi->hdmi_data.enc_color_depth == 8)
401                         color_format = 0x16;
402                 else if (hdmi->hdmi_data.enc_color_depth == 10)
403                         color_format = 0x14;
404                 else if (hdmi->hdmi_data.enc_color_depth == 12)
405                         color_format = 0x12;
406                 else
407                         return;
408         }
409 
410         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
411                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
412                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
413         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
414 
415         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
416         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
417                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
418                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
419         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
420         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
421         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
422         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
423         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
424         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
425         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
426 }
427 
428 static int is_color_space_conversion(struct imx_hdmi *hdmi)
429 {
430         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
431 }
432 
433 static int is_color_space_decimation(struct imx_hdmi *hdmi)
434 {
435         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
436                 return 0;
437         if (hdmi->hdmi_data.enc_in_format == RGB ||
438             hdmi->hdmi_data.enc_in_format == YCBCR444)
439                 return 1;
440         return 0;
441 }
442 
443 static int is_color_space_interpolation(struct imx_hdmi *hdmi)
444 {
445         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
446                 return 0;
447         if (hdmi->hdmi_data.enc_out_format == RGB ||
448             hdmi->hdmi_data.enc_out_format == YCBCR444)
449                 return 1;
450         return 0;
451 }
452 
453 static void imx_hdmi_update_csc_coeffs(struct imx_hdmi *hdmi)
454 {
455         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
456         unsigned i;
457         u32 csc_scale = 1;
458 
459         if (is_color_space_conversion(hdmi)) {
460                 if (hdmi->hdmi_data.enc_out_format == RGB) {
461                         if (hdmi->hdmi_data.colorimetry ==
462                                         HDMI_COLORIMETRY_ITU_601)
463                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
464                         else
465                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
466                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
467                         if (hdmi->hdmi_data.colorimetry ==
468                                         HDMI_COLORIMETRY_ITU_601)
469                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
470                         else
471                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
472                         csc_scale = 0;
473                 }
474         }
475 
476         /* The CSC registers are sequential, alternating MSB then LSB */
477         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
478                 u16 coeff_a = (*csc_coeff)[0][i];
479                 u16 coeff_b = (*csc_coeff)[1][i];
480                 u16 coeff_c = (*csc_coeff)[2][i];
481 
482                 hdmi_writeb(hdmi, coeff_a & 0xff,
483                         HDMI_CSC_COEF_A1_LSB + i * 2);
484                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
485                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
486                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
487                 hdmi_writeb(hdmi, coeff_c & 0xff,
488                         HDMI_CSC_COEF_C1_LSB + i * 2);
489                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
490         }
491 
492         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
493                   HDMI_CSC_SCALE);
494 }
495 
496 static void hdmi_video_csc(struct imx_hdmi *hdmi)
497 {
498         int color_depth = 0;
499         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
500         int decimation = 0;
501 
502         /* YCC422 interpolation to 444 mode */
503         if (is_color_space_interpolation(hdmi))
504                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
505         else if (is_color_space_decimation(hdmi))
506                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
507 
508         if (hdmi->hdmi_data.enc_color_depth == 8)
509                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
510         else if (hdmi->hdmi_data.enc_color_depth == 10)
511                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
512         else if (hdmi->hdmi_data.enc_color_depth == 12)
513                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
514         else if (hdmi->hdmi_data.enc_color_depth == 16)
515                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
516         else
517                 return;
518 
519         /* Configure the CSC registers */
520         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
521         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
522                   HDMI_CSC_SCALE);
523 
524         imx_hdmi_update_csc_coeffs(hdmi);
525 }
526 
527 /*
528  * HDMI video packetizer is used to packetize the data.
529  * for example, if input is YCC422 mode or repeater is used,
530  * data should be repacked this module can be bypassed.
531  */
532 static void hdmi_video_packetize(struct imx_hdmi *hdmi)
533 {
534         unsigned int color_depth = 0;
535         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
536         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
537         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
538         u8 val, vp_conf;
539 
540         if (hdmi_data->enc_out_format == RGB
541                 || hdmi_data->enc_out_format == YCBCR444) {
542                 if (!hdmi_data->enc_color_depth)
543                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
544                 else if (hdmi_data->enc_color_depth == 8) {
545                         color_depth = 4;
546                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
547                 } else if (hdmi_data->enc_color_depth == 10)
548                         color_depth = 5;
549                 else if (hdmi_data->enc_color_depth == 12)
550                         color_depth = 6;
551                 else if (hdmi_data->enc_color_depth == 16)
552                         color_depth = 7;
553                 else
554                         return;
555         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
556                 if (!hdmi_data->enc_color_depth ||
557                     hdmi_data->enc_color_depth == 8)
558                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
559                 else if (hdmi_data->enc_color_depth == 10)
560                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
561                 else if (hdmi_data->enc_color_depth == 12)
562                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
563                 else
564                         return;
565                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
566         } else
567                 return;
568 
569         /* set the packetizer registers */
570         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
571                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
572                 ((hdmi_data->pix_repet_factor <<
573                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
574                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
575         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
576 
577         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
578                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
579 
580         /* Data from pixel repeater block */
581         if (hdmi_data->pix_repet_factor > 1) {
582                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
583                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
584         } else { /* data from packetizer block */
585                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
586                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
587         }
588 
589         hdmi_modb(hdmi, vp_conf,
590                   HDMI_VP_CONF_PR_EN_MASK |
591                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
592 
593         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
594                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
595 
596         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
597 
598         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
599                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
600                           HDMI_VP_CONF_PP_EN_ENABLE |
601                           HDMI_VP_CONF_YCC422_EN_DISABLE;
602         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
603                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
604                           HDMI_VP_CONF_PP_EN_DISABLE |
605                           HDMI_VP_CONF_YCC422_EN_ENABLE;
606         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
607                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
608                           HDMI_VP_CONF_PP_EN_DISABLE |
609                           HDMI_VP_CONF_YCC422_EN_DISABLE;
610         } else {
611                 return;
612         }
613 
614         hdmi_modb(hdmi, vp_conf,
615                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
616                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
617 
618         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
619                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
620                   HDMI_VP_STUFF_PP_STUFFING_MASK |
621                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
622 
623         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
624                   HDMI_VP_CONF);
625 }
626 
627 static inline void hdmi_phy_test_clear(struct imx_hdmi *hdmi,
628                                                 unsigned char bit)
629 {
630         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
631                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
632 }
633 
634 static inline void hdmi_phy_test_enable(struct imx_hdmi *hdmi,
635                                                 unsigned char bit)
636 {
637         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
638                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
639 }
640 
641 static inline void hdmi_phy_test_clock(struct imx_hdmi *hdmi,
642                                                 unsigned char bit)
643 {
644         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
645                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
646 }
647 
648 static inline void hdmi_phy_test_din(struct imx_hdmi *hdmi,
649                                                 unsigned char bit)
650 {
651         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
652 }
653 
654 static inline void hdmi_phy_test_dout(struct imx_hdmi *hdmi,
655                                                 unsigned char bit)
656 {
657         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
658 }
659 
660 static bool hdmi_phy_wait_i2c_done(struct imx_hdmi *hdmi, int msec)
661 {
662         unsigned char val = 0;
663         val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3;
664         while (!val) {
665                 udelay(1000);
666                 if (msec-- == 0)
667                         return false;
668                 val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3;
669         }
670         return true;
671 }
672 
673 static void __hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data,
674                               unsigned char addr)
675 {
676         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
677         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
678         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
679                 HDMI_PHY_I2CM_DATAO_1_ADDR);
680         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
681                 HDMI_PHY_I2CM_DATAO_0_ADDR);
682         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
683                 HDMI_PHY_I2CM_OPERATION_ADDR);
684         hdmi_phy_wait_i2c_done(hdmi, 1000);
685 }
686 
687 static int hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data,
688                                      unsigned char addr)
689 {
690         __hdmi_phy_i2c_write(hdmi, data, addr);
691         return 0;
692 }
693 
694 static void imx_hdmi_phy_enable_power(struct imx_hdmi *hdmi, u8 enable)
695 {
696         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
697                          HDMI_PHY_CONF0_PDZ_OFFSET,
698                          HDMI_PHY_CONF0_PDZ_MASK);
699 }
700 
701 static void imx_hdmi_phy_enable_tmds(struct imx_hdmi *hdmi, u8 enable)
702 {
703         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
704                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
705                          HDMI_PHY_CONF0_ENTMDS_MASK);
706 }
707 
708 static void imx_hdmi_phy_gen2_pddq(struct imx_hdmi *hdmi, u8 enable)
709 {
710         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
711                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
712                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
713 }
714 
715 static void imx_hdmi_phy_gen2_txpwron(struct imx_hdmi *hdmi, u8 enable)
716 {
717         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
718                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
719                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
720 }
721 
722 static void imx_hdmi_phy_sel_data_en_pol(struct imx_hdmi *hdmi, u8 enable)
723 {
724         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
725                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
726                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
727 }
728 
729 static void imx_hdmi_phy_sel_interface_control(struct imx_hdmi *hdmi, u8 enable)
730 {
731         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
732                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
733                          HDMI_PHY_CONF0_SELDIPIF_MASK);
734 }
735 
736 enum {
737         RES_8,
738         RES_10,
739         RES_12,
740         RES_MAX,
741 };
742 
743 struct mpll_config {
744         unsigned long mpixelclock;
745         struct {
746                 u16 cpce;
747                 u16 gmp;
748         } res[RES_MAX];
749 };
750 
751 static const struct mpll_config mpll_config[] = {
752         {
753                 45250000, {
754                         { 0x01e0, 0x0000 },
755                         { 0x21e1, 0x0000 },
756                         { 0x41e2, 0x0000 }
757                 },
758         }, {
759                 92500000, {
760                         { 0x0140, 0x0005 },
761                         { 0x2141, 0x0005 },
762                         { 0x4142, 0x0005 },
763                 },
764         }, {
765                 148500000, {
766                         { 0x00a0, 0x000a },
767                         { 0x20a1, 0x000a },
768                         { 0x40a2, 0x000a },
769                 },
770         }, {
771                 ~0UL, {
772                         { 0x00a0, 0x000a },
773                         { 0x2001, 0x000f },
774                         { 0x4002, 0x000f },
775                 },
776         }
777 };
778 
779 struct curr_ctrl {
780         unsigned long mpixelclock;
781         u16 curr[RES_MAX];
782 };
783 
784 static const struct curr_ctrl curr_ctrl[] = {
785         /*      pixelclk     bpp8    bpp10   bpp12 */
786         {
787                  54000000, { 0x091c, 0x091c, 0x06dc },
788         }, {
789                  58400000, { 0x091c, 0x06dc, 0x06dc },
790         }, {
791                  72000000, { 0x06dc, 0x06dc, 0x091c },
792         }, {
793                  74250000, { 0x06dc, 0x0b5c, 0x091c },
794         }, {
795                 118800000, { 0x091c, 0x091c, 0x06dc },
796         }, {
797                 216000000, { 0x06dc, 0x0b5c, 0x091c },
798         }
799 };
800 
801 static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep,
802                               unsigned char res, int cscon)
803 {
804         unsigned res_idx, i;
805         u8 val, msec;
806 
807         if (prep)
808                 return -EINVAL;
809 
810         switch (res) {
811         case 0: /* color resolution 0 is 8 bit colour depth */
812         case 8:
813                 res_idx = RES_8;
814                 break;
815         case 10:
816                 res_idx = RES_10;
817                 break;
818         case 12:
819                 res_idx = RES_12;
820                 break;
821         default:
822                 return -EINVAL;
823         }
824 
825         /* Enable csc path */
826         if (cscon)
827                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
828         else
829                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
830 
831         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
832 
833         /* gen2 tx power off */
834         imx_hdmi_phy_gen2_txpwron(hdmi, 0);
835 
836         /* gen2 pddq */
837         imx_hdmi_phy_gen2_pddq(hdmi, 1);
838 
839         /* PHY reset */
840         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
841         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
842 
843         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
844 
845         hdmi_phy_test_clear(hdmi, 1);
846         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
847                         HDMI_PHY_I2CM_SLAVE_ADDR);
848         hdmi_phy_test_clear(hdmi, 0);
849 
850         /* PLL/MPLL Cfg - always match on final entry */
851         for (i = 0; i < ARRAY_SIZE(mpll_config) - 1; i++)
852                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
853                     mpll_config[i].mpixelclock)
854                         break;
855 
856         hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].cpce, 0x06);
857         hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].gmp, 0x15);
858 
859         for (i = 0; i < ARRAY_SIZE(curr_ctrl); i++)
860                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
861                     curr_ctrl[i].mpixelclock)
862                         break;
863 
864         if (i >= ARRAY_SIZE(curr_ctrl)) {
865                 dev_err(hdmi->dev,
866                                 "Pixel clock %d - unsupported by HDMI\n",
867                                 hdmi->hdmi_data.video_mode.mpixelclock);
868                 return -EINVAL;
869         }
870 
871         /* CURRCTRL */
872         hdmi_phy_i2c_write(hdmi, curr_ctrl[i].curr[res_idx], 0x10);
873 
874         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
875         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
876         /* RESISTANCE TERM 133Ohm Cfg */
877         hdmi_phy_i2c_write(hdmi, 0x0005, 0x19);  /* TXTERM */
878         /* PREEMP Cgf 0.00 */
879         hdmi_phy_i2c_write(hdmi, 0x800d, 0x09);  /* CKSYMTXCTRL */
880         /* TX/CK LVL 10 */
881         hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E);  /* VLEVCTRL */
882         /* REMOVE CLK TERM */
883         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
884 
885         imx_hdmi_phy_enable_power(hdmi, 1);
886 
887         /* toggle TMDS enable */
888         imx_hdmi_phy_enable_tmds(hdmi, 0);
889         imx_hdmi_phy_enable_tmds(hdmi, 1);
890 
891         /* gen2 tx power on */
892         imx_hdmi_phy_gen2_txpwron(hdmi, 1);
893         imx_hdmi_phy_gen2_pddq(hdmi, 0);
894 
895         /*Wait for PHY PLL lock */
896         msec = 5;
897         do {
898                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
899                 if (!val)
900                         break;
901 
902                 if (msec == 0) {
903                         dev_err(hdmi->dev, "PHY PLL not locked\n");
904                         return -ETIMEDOUT;
905                 }
906 
907                 udelay(1000);
908                 msec--;
909         } while (1);
910 
911         return 0;
912 }
913 
914 static int imx_hdmi_phy_init(struct imx_hdmi *hdmi)
915 {
916         int i, ret;
917         bool cscon = false;
918 
919         /*check csc whether needed activated in HDMI mode */
920         cscon = (is_color_space_conversion(hdmi) &&
921                         !hdmi->hdmi_data.video_mode.mdvi);
922 
923         /* HDMI Phy spec says to do the phy initialization sequence twice */
924         for (i = 0; i < 2; i++) {
925                 imx_hdmi_phy_sel_data_en_pol(hdmi, 1);
926                 imx_hdmi_phy_sel_interface_control(hdmi, 0);
927                 imx_hdmi_phy_enable_tmds(hdmi, 0);
928                 imx_hdmi_phy_enable_power(hdmi, 0);
929 
930                 /* Enable CSC */
931                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
932                 if (ret)
933                         return ret;
934         }
935 
936         hdmi->phy_enabled = true;
937         return 0;
938 }
939 
940 static void hdmi_tx_hdcp_config(struct imx_hdmi *hdmi)
941 {
942         u8 de;
943 
944         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
945                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
946         else
947                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
948 
949         /* disable rx detect */
950         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
951                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
952 
953         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
954 
955         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
956                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
957 }
958 
959 static void hdmi_config_AVI(struct imx_hdmi *hdmi)
960 {
961         u8 val, pix_fmt, under_scan;
962         u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
963         bool aspect_16_9;
964 
965         aspect_16_9 = false; /* FIXME */
966 
967         /* AVI Data Byte 1 */
968         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
969                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
970         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
971                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
972         else
973                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
974 
975                 under_scan =  HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
976 
977         /*
978          * Active format identification data is present in the AVI InfoFrame.
979          * Under scan info, no bar data
980          */
981         val = pix_fmt | under_scan |
982                 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
983                 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
984 
985         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
986 
987         /* AVI Data Byte 2 -Set the Aspect Ratio */
988         if (aspect_16_9) {
989                 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
990                 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
991         } else {
992                 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
993                 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
994         }
995 
996         /* Set up colorimetry */
997         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
998                 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
999                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1000                         ext_colorimetry =
1001                                 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
1002                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1003                         ext_colorimetry =
1004                                 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
1005         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1006                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1007                         colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
1008                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1009                         colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
1010                 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
1011         } else { /* Carries no data */
1012                 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
1013                 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
1014         }
1015 
1016         val = colorimetry | coded_ratio | act_ratio;
1017         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1018 
1019         /* AVI Data Byte 3 */
1020         val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
1021                 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT |
1022                 HDMI_FC_AVICONF2_SCALING_NONE;
1023         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1024 
1025         /* AVI Data Byte 4 */
1026         hdmi_writeb(hdmi, hdmi->vic, HDMI_FC_AVIVID);
1027 
1028         /* AVI Data Byte 5- set up input and output pixel repetition */
1029         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1030                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1031                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1032                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1033                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1034                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1035         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1036 
1037         /* IT Content and quantization range = don't care */
1038         val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
1039                 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
1040         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1041 
1042         /* AVI Data Bytes 6-13 */
1043         hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB0);
1044         hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB1);
1045         hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB0);
1046         hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB1);
1047         hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB0);
1048         hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB1);
1049         hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB0);
1050         hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB1);
1051 }
1052 
1053 static void hdmi_av_composer(struct imx_hdmi *hdmi,
1054                              const struct drm_display_mode *mode)
1055 {
1056         u8 inv_val;
1057         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1058         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1059 
1060         vmode->mhsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
1061         vmode->mvsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
1062         vmode->minterlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1063         vmode->mpixelclock = mode->clock * 1000;
1064 
1065         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1066 
1067         /* Set up HDMI_FC_INVIDCONF */
1068         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1069                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1070                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1071 
1072         inv_val |= (vmode->mvsyncpolarity ?
1073                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1074                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
1075 
1076         inv_val |= (vmode->mhsyncpolarity ?
1077                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1078                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
1079 
1080         inv_val |= (vmode->mdataenablepolarity ?
1081                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1082                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1083 
1084         if (hdmi->vic == 39)
1085                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1086         else
1087                 inv_val |= (vmode->minterlaced ?
1088                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1089                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
1090 
1091         inv_val |= (vmode->minterlaced ?
1092                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1093                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
1094 
1095         inv_val |= (vmode->mdvi ?
1096                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
1097                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
1098 
1099         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1100 
1101         /* Set up horizontal active pixel width */
1102         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1103         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1104 
1105         /* Set up vertical active lines */
1106         hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
1107         hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
1108 
1109         /* Set up horizontal blanking pixel region width */
1110         hblank = mode->htotal - mode->hdisplay;
1111         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1112         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1113 
1114         /* Set up vertical blanking pixel region width */
1115         vblank = mode->vtotal - mode->vdisplay;
1116         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1117 
1118         /* Set up HSYNC active edge delay width (in pixel clks) */
1119         h_de_hs = mode->hsync_start - mode->hdisplay;
1120         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1121         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1122 
1123         /* Set up VSYNC active edge delay (in lines) */
1124         v_de_vs = mode->vsync_start - mode->vdisplay;
1125         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1126 
1127         /* Set up HSYNC active pulse width (in pixel clks) */
1128         hsync_len = mode->hsync_end - mode->hsync_start;
1129         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1130         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1131 
1132         /* Set up VSYNC active edge delay (in lines) */
1133         vsync_len = mode->vsync_end - mode->vsync_start;
1134         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1135 }
1136 
1137 static void imx_hdmi_phy_disable(struct imx_hdmi *hdmi)
1138 {
1139         if (!hdmi->phy_enabled)
1140                 return;
1141 
1142         imx_hdmi_phy_enable_tmds(hdmi, 0);
1143         imx_hdmi_phy_enable_power(hdmi, 0);
1144 
1145         hdmi->phy_enabled = false;
1146 }
1147 
1148 /* HDMI Initialization Step B.4 */
1149 static void imx_hdmi_enable_video_path(struct imx_hdmi *hdmi)
1150 {
1151         u8 clkdis;
1152 
1153         /* control period minimum duration */
1154         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1155         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1156         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1157 
1158         /* Set to fill TMDS data channels */
1159         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1160         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1161         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1162 
1163         /* Enable pixel clock and tmds data path */
1164         clkdis = 0x7F;
1165         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1166         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1167 
1168         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1169         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1170 
1171         /* Enable csc path */
1172         if (is_color_space_conversion(hdmi)) {
1173                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1174                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1175         }
1176 }
1177 
1178 static void hdmi_enable_audio_clk(struct imx_hdmi *hdmi)
1179 {
1180         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1181 }
1182 
1183 /* Workaround to clear the overflow condition */
1184 static void imx_hdmi_clear_overflow(struct imx_hdmi *hdmi)
1185 {
1186         int count;
1187         u8 val;
1188 
1189         /* TMDS software reset */
1190         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1191 
1192         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1193         if (hdmi->dev_type == IMX6DL_HDMI) {
1194                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1195                 return;
1196         }
1197 
1198         for (count = 0; count < 4; count++)
1199                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1200 }
1201 
1202 static void hdmi_enable_overflow_interrupts(struct imx_hdmi *hdmi)
1203 {
1204         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1205         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1206 }
1207 
1208 static void hdmi_disable_overflow_interrupts(struct imx_hdmi *hdmi)
1209 {
1210         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1211                     HDMI_IH_MUTE_FC_STAT2);
1212 }
1213 
1214 static int imx_hdmi_setup(struct imx_hdmi *hdmi, struct drm_display_mode *mode)
1215 {
1216         int ret;
1217 
1218         hdmi_disable_overflow_interrupts(hdmi);
1219 
1220         hdmi->vic = drm_match_cea_mode(mode);
1221 
1222         if (!hdmi->vic) {
1223                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1224                 hdmi->hdmi_data.video_mode.mdvi = true;
1225         } else {
1226                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1227                 hdmi->hdmi_data.video_mode.mdvi = false;
1228         }
1229 
1230         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1231                 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1232                 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1233                 (hdmi->vic == 17) || (hdmi->vic == 18))
1234                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1235         else
1236                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1237 
1238         if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
1239                 (hdmi->vic == 12) || (hdmi->vic == 13) ||
1240                 (hdmi->vic == 14) || (hdmi->vic == 15) ||
1241                 (hdmi->vic == 25) || (hdmi->vic == 26) ||
1242                 (hdmi->vic == 27) || (hdmi->vic == 28) ||
1243                 (hdmi->vic == 29) || (hdmi->vic == 30) ||
1244                 (hdmi->vic == 35) || (hdmi->vic == 36) ||
1245                 (hdmi->vic == 37) || (hdmi->vic == 38))
1246                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1247         else
1248                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1249 
1250         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1251 
1252         /* TODO: Get input format from IPU (via FB driver interface) */
1253         hdmi->hdmi_data.enc_in_format = RGB;
1254 
1255         hdmi->hdmi_data.enc_out_format = RGB;
1256 
1257         hdmi->hdmi_data.enc_color_depth = 8;
1258         hdmi->hdmi_data.pix_repet_factor = 0;
1259         hdmi->hdmi_data.hdcp_enable = 0;
1260         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1261 
1262         /* HDMI Initialization Step B.1 */
1263         hdmi_av_composer(hdmi, mode);
1264 
1265         /* HDMI Initializateion Step B.2 */
1266         ret = imx_hdmi_phy_init(hdmi);
1267         if (ret)
1268                 return ret;
1269 
1270         /* HDMI Initialization Step B.3 */
1271         imx_hdmi_enable_video_path(hdmi);
1272 
1273         /* not for DVI mode */
1274         if (hdmi->hdmi_data.video_mode.mdvi)
1275                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1276         else {
1277                 dev_dbg(hdmi->dev, "%s CEA mode\n", __func__);
1278 
1279                 /* HDMI Initialization Step E - Configure audio */
1280                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1281                 hdmi_enable_audio_clk(hdmi);
1282 
1283                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1284                 hdmi_config_AVI(hdmi);
1285         }
1286 
1287         hdmi_video_packetize(hdmi);
1288         hdmi_video_csc(hdmi);
1289         hdmi_video_sample(hdmi);
1290         hdmi_tx_hdcp_config(hdmi);
1291 
1292         imx_hdmi_clear_overflow(hdmi);
1293         if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi)
1294                 hdmi_enable_overflow_interrupts(hdmi);
1295 
1296         return 0;
1297 }
1298 
1299 /* Wait until we are registered to enable interrupts */
1300 static int imx_hdmi_fb_registered(struct imx_hdmi *hdmi)
1301 {
1302         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1303                     HDMI_PHY_I2CM_INT_ADDR);
1304 
1305         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1306                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1307                     HDMI_PHY_I2CM_CTLINT_ADDR);
1308 
1309         /* enable cable hot plug irq */
1310         hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
1311 
1312         /* Clear Hotplug interrupts */
1313         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1314 
1315         return 0;
1316 }
1317 
1318 static void initialize_hdmi_ih_mutes(struct imx_hdmi *hdmi)
1319 {
1320         u8 ih_mute;
1321 
1322         /*
1323          * Boot up defaults are:
1324          * HDMI_IH_MUTE   = 0x03 (disabled)
1325          * HDMI_IH_MUTE_* = 0x00 (enabled)
1326          *
1327          * Disable top level interrupt bits in HDMI block
1328          */
1329         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1330                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1331                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1332 
1333         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1334 
1335         /* by default mask all interrupts */
1336         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1337         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1338         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1339         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1340         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1341         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1342         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1343         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1344         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1345         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1346         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1347         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1348         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1349         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1350         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1351 
1352         /* Disable interrupts in the IH_MUTE_* registers */
1353         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1354         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1355         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1356         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1357         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1358         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1359         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1360         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1361         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1362         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1363 
1364         /* Enable top level interrupt bits in HDMI block */
1365         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1366                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1367         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1368 }
1369 
1370 static void imx_hdmi_poweron(struct imx_hdmi *hdmi)
1371 {
1372         imx_hdmi_setup(hdmi, &hdmi->previous_mode);
1373 }
1374 
1375 static void imx_hdmi_poweroff(struct imx_hdmi *hdmi)
1376 {
1377         imx_hdmi_phy_disable(hdmi);
1378 }
1379 
1380 static enum drm_connector_status imx_hdmi_connector_detect(struct drm_connector
1381                                                         *connector, bool force)
1382 {
1383         struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
1384                                              connector);
1385         return hdmi->connector_status;
1386 }
1387 
1388 static int imx_hdmi_connector_get_modes(struct drm_connector *connector)
1389 {
1390         struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
1391                                              connector);
1392         struct edid *edid;
1393         int ret;
1394 
1395         if (!hdmi->ddc)
1396                 return 0;
1397 
1398         edid = drm_get_edid(connector, hdmi->ddc);
1399         if (edid) {
1400                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1401                         edid->width_cm, edid->height_cm);
1402 
1403                 drm_mode_connector_update_edid_property(connector, edid);
1404                 ret = drm_add_edid_modes(connector, edid);
1405                 kfree(edid);
1406         } else {
1407                 dev_dbg(hdmi->dev, "failed to get edid\n");
1408         }
1409 
1410         return 0;
1411 }
1412 
1413 static struct drm_encoder *imx_hdmi_connector_best_encoder(struct drm_connector
1414                                                            *connector)
1415 {
1416         struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
1417                                              connector);
1418 
1419         return &hdmi->encoder;
1420 }
1421 
1422 static void imx_hdmi_encoder_mode_set(struct drm_encoder *encoder,
1423                         struct drm_display_mode *mode,
1424                         struct drm_display_mode *adjusted_mode)
1425 {
1426         struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
1427 
1428         imx_hdmi_setup(hdmi, mode);
1429 
1430         /* Store the display mode for plugin/DKMS poweron events */
1431         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1432 }
1433 
1434 static bool imx_hdmi_encoder_mode_fixup(struct drm_encoder *encoder,
1435                         const struct drm_display_mode *mode,
1436                         struct drm_display_mode *adjusted_mode)
1437 {
1438         return true;
1439 }
1440 
1441 static void imx_hdmi_encoder_disable(struct drm_encoder *encoder)
1442 {
1443 }
1444 
1445 static void imx_hdmi_encoder_dpms(struct drm_encoder *encoder, int mode)
1446 {
1447         struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
1448 
1449         if (mode)
1450                 imx_hdmi_poweroff(hdmi);
1451         else
1452                 imx_hdmi_poweron(hdmi);
1453 }
1454 
1455 static void imx_hdmi_encoder_prepare(struct drm_encoder *encoder)
1456 {
1457         struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
1458 
1459         imx_hdmi_poweroff(hdmi);
1460         imx_drm_panel_format(encoder, V4L2_PIX_FMT_RGB24);
1461 }
1462 
1463 static void imx_hdmi_encoder_commit(struct drm_encoder *encoder)
1464 {
1465         struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
1466         int mux = imx_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder);
1467 
1468         imx_hdmi_set_ipu_di_mux(hdmi, mux);
1469 
1470         imx_hdmi_poweron(hdmi);
1471 }
1472 
1473 static struct drm_encoder_funcs imx_hdmi_encoder_funcs = {
1474         .destroy = imx_drm_encoder_destroy,
1475 };
1476 
1477 static struct drm_encoder_helper_funcs imx_hdmi_encoder_helper_funcs = {
1478         .dpms = imx_hdmi_encoder_dpms,
1479         .prepare = imx_hdmi_encoder_prepare,
1480         .commit = imx_hdmi_encoder_commit,
1481         .mode_set = imx_hdmi_encoder_mode_set,
1482         .mode_fixup = imx_hdmi_encoder_mode_fixup,
1483         .disable = imx_hdmi_encoder_disable,
1484 };
1485 
1486 static struct drm_connector_funcs imx_hdmi_connector_funcs = {
1487         .dpms = drm_helper_connector_dpms,
1488         .fill_modes = drm_helper_probe_single_connector_modes,
1489         .detect = imx_hdmi_connector_detect,
1490         .destroy = imx_drm_connector_destroy,
1491 };
1492 
1493 static struct drm_connector_helper_funcs imx_hdmi_connector_helper_funcs = {
1494         .get_modes = imx_hdmi_connector_get_modes,
1495         .mode_valid = imx_drm_connector_mode_valid,
1496         .best_encoder = imx_hdmi_connector_best_encoder,
1497 };
1498 
1499 static irqreturn_t imx_hdmi_hardirq(int irq, void *dev_id)
1500 {
1501         struct imx_hdmi *hdmi = dev_id;
1502         u8 intr_stat;
1503 
1504         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1505         if (intr_stat)
1506                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1507 
1508         return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1509 }
1510 
1511 static irqreturn_t imx_hdmi_irq(int irq, void *dev_id)
1512 {
1513         struct imx_hdmi *hdmi = dev_id;
1514         u8 intr_stat;
1515         u8 phy_int_pol;
1516 
1517         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1518 
1519         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1520 
1521         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1522                 if (phy_int_pol & HDMI_PHY_HPD) {
1523                         dev_dbg(hdmi->dev, "EVENT=plugin\n");
1524 
1525                         hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
1526 
1527                         hdmi->connector_status = connector_status_connected;
1528                         imx_hdmi_poweron(hdmi);
1529                 } else {
1530                         dev_dbg(hdmi->dev, "EVENT=plugout\n");
1531 
1532                         hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
1533                                 HDMI_PHY_POL0);
1534 
1535                         hdmi->connector_status = connector_status_disconnected;
1536                         imx_hdmi_poweroff(hdmi);
1537                 }
1538                 drm_helper_hpd_irq_event(hdmi->connector.dev);
1539         }
1540 
1541         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1542         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1543 
1544         return IRQ_HANDLED;
1545 }
1546 
1547 static int imx_hdmi_register(struct drm_device *drm, struct imx_hdmi *hdmi)
1548 {
1549         int ret;
1550 
1551         ret = imx_drm_encoder_parse_of(drm, &hdmi->encoder,
1552                                        hdmi->dev->of_node);
1553         if (ret)
1554                 return ret;
1555 
1556         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1557 
1558         drm_encoder_helper_add(&hdmi->encoder, &imx_hdmi_encoder_helper_funcs);
1559         drm_encoder_init(drm, &hdmi->encoder, &imx_hdmi_encoder_funcs,
1560                          DRM_MODE_ENCODER_TMDS);
1561 
1562         drm_connector_helper_add(&hdmi->connector,
1563                         &imx_hdmi_connector_helper_funcs);
1564         drm_connector_init(drm, &hdmi->connector, &imx_hdmi_connector_funcs,
1565                            DRM_MODE_CONNECTOR_HDMIA);
1566 
1567         hdmi->connector.encoder = &hdmi->encoder;
1568 
1569         drm_mode_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
1570 
1571         return 0;
1572 }
1573 
1574 static struct platform_device_id imx_hdmi_devtype[] = {
1575         {
1576                 .name = "imx6q-hdmi",
1577                 .driver_data = IMX6Q_HDMI,
1578         }, {
1579                 .name = "imx6dl-hdmi",
1580                 .driver_data = IMX6DL_HDMI,
1581         }, { /* sentinel */ }
1582 };
1583 MODULE_DEVICE_TABLE(platform, imx_hdmi_devtype);
1584 
1585 static const struct of_device_id imx_hdmi_dt_ids[] = {
1586 { .compatible = "fsl,imx6q-hdmi", .data = &imx_hdmi_devtype[IMX6Q_HDMI], },
1587 { .compatible = "fsl,imx6dl-hdmi", .data = &imx_hdmi_devtype[IMX6DL_HDMI], },
1588 { /* sentinel */ }
1589 };
1590 MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids);
1591 
1592 static int imx_hdmi_bind(struct device *dev, struct device *master, void *data)
1593 {
1594         struct platform_device *pdev = to_platform_device(dev);
1595         const struct of_device_id *of_id =
1596                                 of_match_device(imx_hdmi_dt_ids, dev);
1597         struct drm_device *drm = data;
1598         struct device_node *np = dev->of_node;
1599         struct device_node *ddc_node;
1600         struct imx_hdmi *hdmi;
1601         struct resource *iores;
1602         int ret, irq;
1603 
1604         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1605         if (!hdmi)
1606                 return -ENOMEM;
1607 
1608         hdmi->dev = dev;
1609         hdmi->connector_status = connector_status_disconnected;
1610         hdmi->sample_rate = 48000;
1611         hdmi->ratio = 100;
1612 
1613         if (of_id) {
1614                 const struct platform_device_id *device_id = of_id->data;
1615                 hdmi->dev_type = device_id->driver_data;
1616         }
1617 
1618         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1619         if (ddc_node) {
1620                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1621                 if (!hdmi->ddc)
1622                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
1623 
1624                 of_node_put(ddc_node);
1625         } else {
1626                 dev_dbg(hdmi->dev, "no ddc property found\n");
1627         }
1628 
1629         irq = platform_get_irq(pdev, 0);
1630         if (irq < 0)
1631                 return -EINVAL;
1632 
1633         ret = devm_request_threaded_irq(dev, irq, imx_hdmi_hardirq,
1634                                         imx_hdmi_irq, IRQF_SHARED,
1635                                         dev_name(dev), hdmi);
1636         if (ret)
1637                 return ret;
1638 
1639         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1640         hdmi->regs = devm_ioremap_resource(dev, iores);
1641         if (IS_ERR(hdmi->regs))
1642                 return PTR_ERR(hdmi->regs);
1643 
1644         hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
1645         if (IS_ERR(hdmi->regmap))
1646                 return PTR_ERR(hdmi->regmap);
1647 
1648         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1649         if (IS_ERR(hdmi->isfr_clk)) {
1650                 ret = PTR_ERR(hdmi->isfr_clk);
1651                 dev_err(hdmi->dev,
1652                         "Unable to get HDMI isfr clk: %d\n", ret);
1653                 return ret;
1654         }
1655 
1656         ret = clk_prepare_enable(hdmi->isfr_clk);
1657         if (ret) {
1658                 dev_err(hdmi->dev,
1659                         "Cannot enable HDMI isfr clock: %d\n", ret);
1660                 return ret;
1661         }
1662 
1663         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1664         if (IS_ERR(hdmi->iahb_clk)) {
1665                 ret = PTR_ERR(hdmi->iahb_clk);
1666                 dev_err(hdmi->dev,
1667                         "Unable to get HDMI iahb clk: %d\n", ret);
1668                 goto err_isfr;
1669         }
1670 
1671         ret = clk_prepare_enable(hdmi->iahb_clk);
1672         if (ret) {
1673                 dev_err(hdmi->dev,
1674                         "Cannot enable HDMI iahb clock: %d\n", ret);
1675                 goto err_isfr;
1676         }
1677 
1678         /* Product and revision IDs */
1679         dev_info(dev,
1680                 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1681                 hdmi_readb(hdmi, HDMI_DESIGN_ID),
1682                 hdmi_readb(hdmi, HDMI_REVISION_ID),
1683                 hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1684                 hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1685 
1686         initialize_hdmi_ih_mutes(hdmi);
1687 
1688         /*
1689          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1690          * N and cts values before enabling phy
1691          */
1692         hdmi_init_clk_regenerator(hdmi);
1693 
1694         /*
1695          * Configure registers related to HDMI interrupt
1696          * generation before registering IRQ.
1697          */
1698         hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
1699 
1700         /* Clear Hotplug interrupts */
1701         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1702 
1703         ret = imx_hdmi_fb_registered(hdmi);
1704         if (ret)
1705                 goto err_iahb;
1706 
1707         ret = imx_hdmi_register(drm, hdmi);
1708         if (ret)
1709                 goto err_iahb;
1710 
1711         /* Unmute interrupts */
1712         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1713 
1714         dev_set_drvdata(dev, hdmi);
1715 
1716         return 0;
1717 
1718 err_iahb:
1719         clk_disable_unprepare(hdmi->iahb_clk);
1720 err_isfr:
1721         clk_disable_unprepare(hdmi->isfr_clk);
1722 
1723         return ret;
1724 }
1725 
1726 static void imx_hdmi_unbind(struct device *dev, struct device *master,
1727         void *data)
1728 {
1729         struct imx_hdmi *hdmi = dev_get_drvdata(dev);
1730 
1731         /* Disable all interrupts */
1732         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1733 
1734         hdmi->connector.funcs->destroy(&hdmi->connector);
1735         hdmi->encoder.funcs->destroy(&hdmi->encoder);
1736 
1737         clk_disable_unprepare(hdmi->iahb_clk);
1738         clk_disable_unprepare(hdmi->isfr_clk);
1739         i2c_put_adapter(hdmi->ddc);
1740 }
1741 
1742 static const struct component_ops hdmi_ops = {
1743         .bind   = imx_hdmi_bind,
1744         .unbind = imx_hdmi_unbind,
1745 };
1746 
1747 static int imx_hdmi_platform_probe(struct platform_device *pdev)
1748 {
1749         return component_add(&pdev->dev, &hdmi_ops);
1750 }
1751 
1752 static int imx_hdmi_platform_remove(struct platform_device *pdev)
1753 {
1754         component_del(&pdev->dev, &hdmi_ops);
1755         return 0;
1756 }
1757 
1758 static struct platform_driver imx_hdmi_driver = {
1759         .probe  = imx_hdmi_platform_probe,
1760         .remove = imx_hdmi_platform_remove,
1761         .driver = {
1762                 .name = "imx-hdmi",
1763                 .owner = THIS_MODULE,
1764                 .of_match_table = imx_hdmi_dt_ids,
1765         },
1766 };
1767 
1768 module_platform_driver(imx_hdmi_driver);
1769 
1770 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1771 MODULE_DESCRIPTION("i.MX6 HDMI transmitter driver");
1772 MODULE_LICENSE("GPL");
1773 MODULE_ALIAS("platform:imx-hdmi");
1774 

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