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Linux/drivers/staging/iio/adc/spear_adc.c

  1 /*
  2  * ST SPEAr ADC driver
  3  *
  4  * Copyright 2012 Stefan Roese <sr@denx.de>
  5  *
  6  * Licensed under the GPL-2.
  7  */
  8 
  9 #include <linux/module.h>
 10 #include <linux/platform_device.h>
 11 #include <linux/interrupt.h>
 12 #include <linux/device.h>
 13 #include <linux/kernel.h>
 14 #include <linux/slab.h>
 15 #include <linux/io.h>
 16 #include <linux/clk.h>
 17 #include <linux/err.h>
 18 #include <linux/completion.h>
 19 #include <linux/of.h>
 20 #include <linux/of_address.h>
 21 
 22 #include <linux/iio/iio.h>
 23 #include <linux/iio/sysfs.h>
 24 
 25 /* SPEAR registers definitions */
 26 #define SPEAR600_ADC_SCAN_RATE_LO(x)    ((x) & 0xFFFF)
 27 #define SPEAR600_ADC_SCAN_RATE_HI(x)    (((x) >> 0x10) & 0xFFFF)
 28 #define SPEAR_ADC_CLK_LOW(x)            (((x) & 0xf) << 0)
 29 #define SPEAR_ADC_CLK_HIGH(x)           (((x) & 0xf) << 4)
 30 
 31 /* Bit definitions for SPEAR_ADC_STATUS */
 32 #define SPEAR_ADC_STATUS_START_CONVERSION       BIT(0)
 33 #define SPEAR_ADC_STATUS_CHANNEL_NUM(x)         ((x) << 1)
 34 #define SPEAR_ADC_STATUS_ADC_ENABLE             BIT(4)
 35 #define SPEAR_ADC_STATUS_AVG_SAMPLE(x)          ((x) << 5)
 36 #define SPEAR_ADC_STATUS_VREF_INTERNAL          BIT(9)
 37 
 38 #define SPEAR_ADC_DATA_MASK             0x03ff
 39 #define SPEAR_ADC_DATA_BITS             10
 40 
 41 #define SPEAR_ADC_MOD_NAME "spear-adc"
 42 
 43 #define SPEAR_ADC_CHANNEL_NUM           8
 44 
 45 #define SPEAR_ADC_CLK_MIN                       2500000
 46 #define SPEAR_ADC_CLK_MAX                       20000000
 47 
 48 struct adc_regs_spear3xx {
 49         u32 status;
 50         u32 average;
 51         u32 scan_rate;
 52         u32 clk;        /* Not avail for 1340 & 1310 */
 53         u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM];
 54         u32 ch_data[SPEAR_ADC_CHANNEL_NUM];
 55 };
 56 
 57 struct chan_data {
 58         u32 lsb;
 59         u32 msb;
 60 };
 61 
 62 struct adc_regs_spear6xx {
 63         u32 status;
 64         u32 pad[2];
 65         u32 clk;
 66         u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM];
 67         struct chan_data ch_data[SPEAR_ADC_CHANNEL_NUM];
 68         u32 scan_rate_lo;
 69         u32 scan_rate_hi;
 70         struct chan_data average;
 71 };
 72 
 73 struct spear_adc_state {
 74         struct device_node *np;
 75         struct adc_regs_spear3xx __iomem *adc_base_spear3xx;
 76         struct adc_regs_spear6xx __iomem *adc_base_spear6xx;
 77         struct clk *clk;
 78         struct completion completion;
 79         u32 current_clk;
 80         u32 sampling_freq;
 81         u32 avg_samples;
 82         u32 vref_external;
 83         u32 value;
 84 };
 85 
 86 /*
 87  * Functions to access some SPEAr ADC register. Abstracted into
 88  * static inline functions, because of different register offsets
 89  * on different SoC variants (SPEAr300 vs SPEAr600 etc).
 90  */
 91 static void spear_adc_set_status(struct spear_adc_state *st, u32 val)
 92 {
 93         __raw_writel(val, &st->adc_base_spear6xx->status);
 94 }
 95 
 96 static void spear_adc_set_clk(struct spear_adc_state *st, u32 val)
 97 {
 98         u32 clk_high, clk_low, count;
 99         u32 apb_clk = clk_get_rate(st->clk);
100 
101         count = DIV_ROUND_UP(apb_clk, val);
102         clk_low = count / 2;
103         clk_high = count - clk_low;
104         st->current_clk = apb_clk / count;
105 
106         __raw_writel(SPEAR_ADC_CLK_LOW(clk_low) | SPEAR_ADC_CLK_HIGH(clk_high),
107                      &st->adc_base_spear6xx->clk);
108 }
109 
110 static void spear_adc_set_ctrl(struct spear_adc_state *st, int n,
111                                u32 val)
112 {
113         __raw_writel(val, &st->adc_base_spear6xx->ch_ctrl[n]);
114 }
115 
116 static u32 spear_adc_get_average(struct spear_adc_state *st)
117 {
118         if (of_device_is_compatible(st->np, "st,spear600-adc")) {
119                 return __raw_readl(&st->adc_base_spear6xx->average.msb) &
120                         SPEAR_ADC_DATA_MASK;
121         } else {
122                 return __raw_readl(&st->adc_base_spear3xx->average) &
123                         SPEAR_ADC_DATA_MASK;
124         }
125 }
126 
127 static void spear_adc_set_scanrate(struct spear_adc_state *st, u32 rate)
128 {
129         if (of_device_is_compatible(st->np, "st,spear600-adc")) {
130                 __raw_writel(SPEAR600_ADC_SCAN_RATE_LO(rate),
131                              &st->adc_base_spear6xx->scan_rate_lo);
132                 __raw_writel(SPEAR600_ADC_SCAN_RATE_HI(rate),
133                              &st->adc_base_spear6xx->scan_rate_hi);
134         } else {
135                 __raw_writel(rate, &st->adc_base_spear3xx->scan_rate);
136         }
137 }
138 
139 static int spear_adc_read_raw(struct iio_dev *indio_dev,
140                               struct iio_chan_spec const *chan,
141                               int *val,
142                               int *val2,
143                               long mask)
144 {
145         struct spear_adc_state *st = iio_priv(indio_dev);
146         u32 status;
147 
148         switch (mask) {
149         case IIO_CHAN_INFO_RAW:
150                 mutex_lock(&indio_dev->mlock);
151 
152                 status = SPEAR_ADC_STATUS_CHANNEL_NUM(chan->channel) |
153                         SPEAR_ADC_STATUS_AVG_SAMPLE(st->avg_samples) |
154                         SPEAR_ADC_STATUS_START_CONVERSION |
155                         SPEAR_ADC_STATUS_ADC_ENABLE;
156                 if (st->vref_external == 0)
157                         status |= SPEAR_ADC_STATUS_VREF_INTERNAL;
158 
159                 spear_adc_set_status(st, status);
160                 wait_for_completion(&st->completion); /* set by ISR */
161                 *val = st->value;
162 
163                 mutex_unlock(&indio_dev->mlock);
164 
165                 return IIO_VAL_INT;
166 
167         case IIO_CHAN_INFO_SCALE:
168                 *val = st->vref_external;
169                 *val2 = SPEAR_ADC_DATA_BITS;
170                 return IIO_VAL_FRACTIONAL_LOG2;
171         case IIO_CHAN_INFO_SAMP_FREQ:
172                 *val = st->current_clk;
173                 return IIO_VAL_INT;
174         }
175 
176         return -EINVAL;
177 }
178 
179 static int spear_adc_write_raw(struct iio_dev *indio_dev,
180                                struct iio_chan_spec const *chan,
181                                int val,
182                                int val2,
183                                long mask)
184 {
185         struct spear_adc_state *st = iio_priv(indio_dev);
186         int ret = 0;
187 
188         if (mask != IIO_CHAN_INFO_SAMP_FREQ)
189                 return -EINVAL;
190 
191         mutex_lock(&indio_dev->mlock);
192 
193         if ((val < SPEAR_ADC_CLK_MIN) ||
194             (val > SPEAR_ADC_CLK_MAX) ||
195             (val2 != 0)) {
196                 ret = -EINVAL;
197                 goto out;
198         }
199 
200         spear_adc_set_clk(st, val);
201 
202 out:
203         mutex_unlock(&indio_dev->mlock);
204         return ret;
205 }
206 
207 #define SPEAR_ADC_CHAN(idx) {                           \
208         .type = IIO_VOLTAGE,                            \
209         .indexed = 1,                                   \
210         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
211         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
212         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
213         .channel = idx,                                 \
214 }
215 
216 static const struct iio_chan_spec spear_adc_iio_channels[] = {
217         SPEAR_ADC_CHAN(0),
218         SPEAR_ADC_CHAN(1),
219         SPEAR_ADC_CHAN(2),
220         SPEAR_ADC_CHAN(3),
221         SPEAR_ADC_CHAN(4),
222         SPEAR_ADC_CHAN(5),
223         SPEAR_ADC_CHAN(6),
224         SPEAR_ADC_CHAN(7),
225 };
226 
227 static irqreturn_t spear_adc_isr(int irq, void *dev_id)
228 {
229         struct spear_adc_state *st = dev_id;
230 
231         /* Read value to clear IRQ */
232         st->value = spear_adc_get_average(st);
233         complete(&st->completion);
234 
235         return IRQ_HANDLED;
236 }
237 
238 static int spear_adc_configure(struct spear_adc_state *st)
239 {
240         int i;
241 
242         /* Reset ADC core */
243         spear_adc_set_status(st, 0);
244         __raw_writel(0, &st->adc_base_spear6xx->clk);
245         for (i = 0; i < 8; i++)
246                 spear_adc_set_ctrl(st, i, 0);
247         spear_adc_set_scanrate(st, 0);
248 
249         spear_adc_set_clk(st, st->sampling_freq);
250 
251         return 0;
252 }
253 
254 static const struct iio_info spear_adc_info = {
255         .read_raw = &spear_adc_read_raw,
256         .write_raw = &spear_adc_write_raw,
257         .driver_module = THIS_MODULE,
258 };
259 
260 static int spear_adc_probe(struct platform_device *pdev)
261 {
262         struct device_node *np = pdev->dev.of_node;
263         struct device *dev = &pdev->dev;
264         struct spear_adc_state *st;
265         struct resource *res;
266         struct iio_dev *indio_dev = NULL;
267         int ret = -ENODEV;
268         int irq;
269 
270         indio_dev = devm_iio_device_alloc(dev, sizeof(struct spear_adc_state));
271         if (!indio_dev) {
272                 dev_err(dev, "failed allocating iio device\n");
273                 return -ENOMEM;
274         }
275 
276         st = iio_priv(indio_dev);
277         st->np = np;
278 
279         /*
280          * SPEAr600 has a different register layout than other SPEAr SoC's
281          * (e.g. SPEAr3xx). Let's provide two register base addresses
282          * to support multi-arch kernels.
283          */
284         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
285         st->adc_base_spear6xx = devm_ioremap_resource(&pdev->dev, res);
286         if (IS_ERR(st->adc_base_spear6xx))
287                 return PTR_ERR(st->adc_base_spear6xx);
288 
289         st->adc_base_spear3xx =
290                 (struct adc_regs_spear3xx __iomem *)st->adc_base_spear6xx;
291 
292         st->clk = devm_clk_get(dev, NULL);
293         if (IS_ERR(st->clk)) {
294                 dev_err(dev, "failed getting clock\n");
295                 return PTR_ERR(st->clk);
296         }
297 
298         ret = clk_prepare_enable(st->clk);
299         if (ret) {
300                 dev_err(dev, "failed enabling clock\n");
301                 return ret;
302         }
303 
304         irq = platform_get_irq(pdev, 0);
305         if (irq <= 0) {
306                 dev_err(dev, "failed getting interrupt resource\n");
307                 ret = -EINVAL;
308                 goto errout2;
309         }
310 
311         ret = devm_request_irq(dev, irq, spear_adc_isr, 0, SPEAR_ADC_MOD_NAME,
312                                st);
313         if (ret < 0) {
314                 dev_err(dev, "failed requesting interrupt\n");
315                 goto errout2;
316         }
317 
318         if (of_property_read_u32(np, "sampling-frequency",
319                                  &st->sampling_freq)) {
320                 dev_err(dev, "sampling-frequency missing in DT\n");
321                 ret = -EINVAL;
322                 goto errout2;
323         }
324 
325         /*
326          * Optional avg_samples defaults to 0, resulting in single data
327          * conversion
328          */
329         of_property_read_u32(np, "average-samples", &st->avg_samples);
330 
331         /*
332          * Optional vref_external defaults to 0, resulting in internal vref
333          * selection
334          */
335         of_property_read_u32(np, "vref-external", &st->vref_external);
336 
337         spear_adc_configure(st);
338 
339         platform_set_drvdata(pdev, indio_dev);
340 
341         init_completion(&st->completion);
342 
343         indio_dev->name = SPEAR_ADC_MOD_NAME;
344         indio_dev->dev.parent = dev;
345         indio_dev->info = &spear_adc_info;
346         indio_dev->modes = INDIO_DIRECT_MODE;
347         indio_dev->channels = spear_adc_iio_channels;
348         indio_dev->num_channels = ARRAY_SIZE(spear_adc_iio_channels);
349 
350         ret = iio_device_register(indio_dev);
351         if (ret)
352                 goto errout2;
353 
354         dev_info(dev, "SPEAR ADC driver loaded, IRQ %d\n", irq);
355 
356         return 0;
357 
358 errout2:
359         clk_disable_unprepare(st->clk);
360         return ret;
361 }
362 
363 static int spear_adc_remove(struct platform_device *pdev)
364 {
365         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
366         struct spear_adc_state *st = iio_priv(indio_dev);
367 
368         iio_device_unregister(indio_dev);
369         clk_disable_unprepare(st->clk);
370 
371         return 0;
372 }
373 
374 #ifdef CONFIG_OF
375 static const struct of_device_id spear_adc_dt_ids[] = {
376         { .compatible = "st,spear600-adc", },
377         { /* sentinel */ }
378 };
379 MODULE_DEVICE_TABLE(of, spear_adc_dt_ids);
380 #endif
381 
382 static struct platform_driver spear_adc_driver = {
383         .probe          = spear_adc_probe,
384         .remove         = spear_adc_remove,
385         .driver         = {
386                 .name   = SPEAR_ADC_MOD_NAME,
387                 .of_match_table = of_match_ptr(spear_adc_dt_ids),
388         },
389 };
390 
391 module_platform_driver(spear_adc_driver);
392 
393 MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
394 MODULE_DESCRIPTION("SPEAr ADC driver");
395 MODULE_LICENSE("GPL");
396 

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