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Linux/drivers/staging/iio/adc/mxs-lradc.c

  1 /*
  2  * Freescale i.MX28 LRADC driver
  3  *
  4  * Copyright (c) 2012 DENX Software Engineering, GmbH.
  5  * Marek Vasut <marex@denx.de>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  *
 12  * This program is distributed in the hope that it will be useful,
 13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 15  * GNU General Public License for more details.
 16  */
 17 
 18 #include <linux/err.h>
 19 #include <linux/interrupt.h>
 20 #include <linux/device.h>
 21 #include <linux/kernel.h>
 22 #include <linux/slab.h>
 23 #include <linux/of.h>
 24 #include <linux/of_device.h>
 25 #include <linux/sysfs.h>
 26 #include <linux/list.h>
 27 #include <linux/io.h>
 28 #include <linux/module.h>
 29 #include <linux/platform_device.h>
 30 #include <linux/spinlock.h>
 31 #include <linux/wait.h>
 32 #include <linux/sched.h>
 33 #include <linux/stmp_device.h>
 34 #include <linux/bitops.h>
 35 #include <linux/completion.h>
 36 #include <linux/delay.h>
 37 #include <linux/input.h>
 38 #include <linux/clk.h>
 39 
 40 #include <linux/iio/iio.h>
 41 #include <linux/iio/sysfs.h>
 42 #include <linux/iio/buffer.h>
 43 #include <linux/iio/trigger.h>
 44 #include <linux/iio/trigger_consumer.h>
 45 #include <linux/iio/triggered_buffer.h>
 46 
 47 #define DRIVER_NAME             "mxs-lradc"
 48 
 49 #define LRADC_MAX_DELAY_CHANS   4
 50 #define LRADC_MAX_MAPPED_CHANS  8
 51 #define LRADC_MAX_TOTAL_CHANS   16
 52 
 53 #define LRADC_DELAY_TIMER_HZ    2000
 54 
 55 /*
 56  * Make this runtime configurable if necessary. Currently, if the buffered mode
 57  * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
 58  * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
 59  * seconds. The result is that the samples arrive every 500mS.
 60  */
 61 #define LRADC_DELAY_TIMER_PER   200
 62 #define LRADC_DELAY_TIMER_LOOP  5
 63 
 64 /*
 65  * Once the pen touches the touchscreen, the touchscreen switches from
 66  * IRQ-driven mode to polling mode to prevent interrupt storm. The polling
 67  * is realized by worker thread, which is called every 20 or so milliseconds.
 68  * This gives the touchscreen enough fluence and does not strain the system
 69  * too much.
 70  */
 71 #define LRADC_TS_SAMPLE_DELAY_MS        5
 72 
 73 /*
 74  * The LRADC reads the following amount of samples from each touchscreen
 75  * channel and the driver then computes avarage of these.
 76  */
 77 #define LRADC_TS_SAMPLE_AMOUNT          4
 78 
 79 enum mxs_lradc_id {
 80         IMX23_LRADC,
 81         IMX28_LRADC,
 82 };
 83 
 84 static const char * const mx23_lradc_irq_names[] = {
 85         "mxs-lradc-touchscreen",
 86         "mxs-lradc-channel0",
 87         "mxs-lradc-channel1",
 88         "mxs-lradc-channel2",
 89         "mxs-lradc-channel3",
 90         "mxs-lradc-channel4",
 91         "mxs-lradc-channel5",
 92         "mxs-lradc-channel6",
 93         "mxs-lradc-channel7",
 94 };
 95 
 96 static const char * const mx28_lradc_irq_names[] = {
 97         "mxs-lradc-touchscreen",
 98         "mxs-lradc-thresh0",
 99         "mxs-lradc-thresh1",
100         "mxs-lradc-channel0",
101         "mxs-lradc-channel1",
102         "mxs-lradc-channel2",
103         "mxs-lradc-channel3",
104         "mxs-lradc-channel4",
105         "mxs-lradc-channel5",
106         "mxs-lradc-channel6",
107         "mxs-lradc-channel7",
108         "mxs-lradc-button0",
109         "mxs-lradc-button1",
110 };
111 
112 struct mxs_lradc_of_config {
113         const int               irq_count;
114         const char * const      *irq_name;
115         const uint32_t          *vref_mv;
116 };
117 
118 #define VREF_MV_BASE 1850
119 
120 static const uint32_t mx23_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
121         VREF_MV_BASE,           /* CH0 */
122         VREF_MV_BASE,           /* CH1 */
123         VREF_MV_BASE,           /* CH2 */
124         VREF_MV_BASE,           /* CH3 */
125         VREF_MV_BASE,           /* CH4 */
126         VREF_MV_BASE,           /* CH5 */
127         VREF_MV_BASE * 2,       /* CH6 VDDIO */
128         VREF_MV_BASE * 4,       /* CH7 VBATT */
129         VREF_MV_BASE,           /* CH8 Temp sense 0 */
130         VREF_MV_BASE,           /* CH9 Temp sense 1 */
131         VREF_MV_BASE,           /* CH10 */
132         VREF_MV_BASE,           /* CH11 */
133         VREF_MV_BASE,           /* CH12 USB_DP */
134         VREF_MV_BASE,           /* CH13 USB_DN */
135         VREF_MV_BASE,           /* CH14 VBG */
136         VREF_MV_BASE * 4,       /* CH15 VDD5V */
137 };
138 
139 static const uint32_t mx28_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
140         VREF_MV_BASE,           /* CH0 */
141         VREF_MV_BASE,           /* CH1 */
142         VREF_MV_BASE,           /* CH2 */
143         VREF_MV_BASE,           /* CH3 */
144         VREF_MV_BASE,           /* CH4 */
145         VREF_MV_BASE,           /* CH5 */
146         VREF_MV_BASE,           /* CH6 */
147         VREF_MV_BASE * 4,       /* CH7 VBATT */
148         VREF_MV_BASE,           /* CH8 Temp sense 0 */
149         VREF_MV_BASE,           /* CH9 Temp sense 1 */
150         VREF_MV_BASE * 2,       /* CH10 VDDIO */
151         VREF_MV_BASE,           /* CH11 VTH */
152         VREF_MV_BASE * 2,       /* CH12 VDDA */
153         VREF_MV_BASE,           /* CH13 VDDD */
154         VREF_MV_BASE,           /* CH14 VBG */
155         VREF_MV_BASE * 4,       /* CH15 VDD5V */
156 };
157 
158 static const struct mxs_lradc_of_config mxs_lradc_of_config[] = {
159         [IMX23_LRADC] = {
160                 .irq_count      = ARRAY_SIZE(mx23_lradc_irq_names),
161                 .irq_name       = mx23_lradc_irq_names,
162                 .vref_mv        = mx23_vref_mv,
163         },
164         [IMX28_LRADC] = {
165                 .irq_count      = ARRAY_SIZE(mx28_lradc_irq_names),
166                 .irq_name       = mx28_lradc_irq_names,
167                 .vref_mv        = mx28_vref_mv,
168         },
169 };
170 
171 enum mxs_lradc_ts {
172         MXS_LRADC_TOUCHSCREEN_NONE = 0,
173         MXS_LRADC_TOUCHSCREEN_4WIRE,
174         MXS_LRADC_TOUCHSCREEN_5WIRE,
175 };
176 
177 /*
178  * Touchscreen handling
179  */
180 enum lradc_ts_plate {
181         LRADC_TOUCH = 0,
182         LRADC_SAMPLE_X,
183         LRADC_SAMPLE_Y,
184         LRADC_SAMPLE_PRESSURE,
185         LRADC_SAMPLE_VALID,
186 };
187 
188 enum mxs_lradc_divbytwo {
189         MXS_LRADC_DIV_DISABLED = 0,
190         MXS_LRADC_DIV_ENABLED,
191 };
192 
193 struct mxs_lradc_scale {
194         unsigned int            integer;
195         unsigned int            nano;
196 };
197 
198 struct mxs_lradc {
199         struct device           *dev;
200         void __iomem            *base;
201         int                     irq[13];
202 
203         struct clk              *clk;
204 
205         uint32_t                *buffer;
206         struct iio_trigger      *trig;
207 
208         struct mutex            lock;
209 
210         struct completion       completion;
211 
212         const uint32_t          *vref_mv;
213         struct mxs_lradc_scale  scale_avail[LRADC_MAX_TOTAL_CHANS][2];
214         unsigned long           is_divided;
215 
216         /*
217          * Touchscreen LRADC channels receives a private slot in the CTRL4
218          * register, the slot #7. Therefore only 7 slots instead of 8 in the
219          * CTRL4 register can be mapped to LRADC channels when using the
220          * touchscreen.
221          *
222          * Furthermore, certain LRADC channels are shared between touchscreen
223          * and/or touch-buttons and generic LRADC block. Therefore when using
224          * either of these, these channels are not available for the regular
225          * sampling. The shared channels are as follows:
226          *
227          * CH0 -- Touch button #0
228          * CH1 -- Touch button #1
229          * CH2 -- Touch screen XPUL
230          * CH3 -- Touch screen YPLL
231          * CH4 -- Touch screen XNUL
232          * CH5 -- Touch screen YNLR
233          * CH6 -- Touch screen WIPER (5-wire only)
234          *
235          * The bitfields below represents which parts of the LRADC block are
236          * switched into special mode of operation. These channels can not
237          * be sampled as regular LRADC channels. The driver will refuse any
238          * attempt to sample these channels.
239          */
240 #define CHAN_MASK_TOUCHBUTTON           (0x3 << 0)
241 #define CHAN_MASK_TOUCHSCREEN_4WIRE     (0xf << 2)
242 #define CHAN_MASK_TOUCHSCREEN_5WIRE     (0x1f << 2)
243         enum mxs_lradc_ts       use_touchscreen;
244         bool                    use_touchbutton;
245 
246         struct input_dev        *ts_input;
247 
248         enum mxs_lradc_id       soc;
249         enum lradc_ts_plate     cur_plate; /* statemachine */
250         bool                    ts_valid;
251         unsigned                ts_x_pos;
252         unsigned                ts_y_pos;
253         unsigned                ts_pressure;
254 
255         /* handle touchscreen's physical behaviour */
256         /* samples per coordinate */
257         unsigned                over_sample_cnt;
258         /* time clocks between samples */
259         unsigned                over_sample_delay;
260         /* time in clocks to wait after the plates where switched */
261         unsigned                settling_delay;
262 };
263 
264 #define LRADC_CTRL0                             0x00
265 # define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE   (1 << 23)
266 # define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE     (1 << 22)
267 # define LRADC_CTRL0_MX28_YNNSW /* YM */        (1 << 21)
268 # define LRADC_CTRL0_MX28_YPNSW /* YP */        (1 << 20)
269 # define LRADC_CTRL0_MX28_YPPSW /* YP */        (1 << 19)
270 # define LRADC_CTRL0_MX28_XNNSW /* XM */        (1 << 18)
271 # define LRADC_CTRL0_MX28_XNPSW /* XM */        (1 << 17)
272 # define LRADC_CTRL0_MX28_XPPSW /* XP */        (1 << 16)
273 
274 # define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE   (1 << 20)
275 # define LRADC_CTRL0_MX23_YM                    (1 << 19)
276 # define LRADC_CTRL0_MX23_XM                    (1 << 18)
277 # define LRADC_CTRL0_MX23_YP                    (1 << 17)
278 # define LRADC_CTRL0_MX23_XP                    (1 << 16)
279 
280 # define LRADC_CTRL0_MX28_PLATE_MASK \
281                 (LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \
282                 LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \
283                 LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \
284                 LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW)
285 
286 # define LRADC_CTRL0_MX23_PLATE_MASK \
287                 (LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE | \
288                 LRADC_CTRL0_MX23_YM | LRADC_CTRL0_MX23_XM | \
289                 LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XP)
290 
291 #define LRADC_CTRL1                             0x10
292 #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN         (1 << 24)
293 #define LRADC_CTRL1_LRADC_IRQ_EN(n)             (1 << ((n) + 16))
294 #define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK      (0x1fff << 16)
295 #define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK      (0x01ff << 16)
296 #define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET         16
297 #define LRADC_CTRL1_TOUCH_DETECT_IRQ            (1 << 8)
298 #define LRADC_CTRL1_LRADC_IRQ(n)                (1 << (n))
299 #define LRADC_CTRL1_MX28_LRADC_IRQ_MASK         0x1fff
300 #define LRADC_CTRL1_MX23_LRADC_IRQ_MASK         0x01ff
301 #define LRADC_CTRL1_LRADC_IRQ_OFFSET            0
302 
303 #define LRADC_CTRL2                             0x20
304 #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET        24
305 #define LRADC_CTRL2_TEMPSENSE_PWD               (1 << 15)
306 
307 #define LRADC_STATUS                            0x40
308 #define LRADC_STATUS_TOUCH_DETECT_RAW           (1 << 0)
309 
310 #define LRADC_CH(n)                             (0x50 + (0x10 * (n)))
311 #define LRADC_CH_ACCUMULATE                     (1 << 29)
312 #define LRADC_CH_NUM_SAMPLES_MASK               (0x1f << 24)
313 #define LRADC_CH_NUM_SAMPLES_OFFSET             24
314 #define LRADC_CH_NUM_SAMPLES(x) \
315                                 ((x) << LRADC_CH_NUM_SAMPLES_OFFSET)
316 #define LRADC_CH_VALUE_MASK                     0x3ffff
317 #define LRADC_CH_VALUE_OFFSET                   0
318 
319 #define LRADC_DELAY(n)                          (0xd0 + (0x10 * (n)))
320 #define LRADC_DELAY_TRIGGER_LRADCS_MASK         (0xff << 24)
321 #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET       24
322 #define LRADC_DELAY_TRIGGER(x) \
323                                 (((x) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) & \
324                                 LRADC_DELAY_TRIGGER_LRADCS_MASK)
325 #define LRADC_DELAY_KICK                        (1 << 20)
326 #define LRADC_DELAY_TRIGGER_DELAYS_MASK         (0xf << 16)
327 #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET       16
328 #define LRADC_DELAY_TRIGGER_DELAYS(x) \
329                                 (((x) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) & \
330                                 LRADC_DELAY_TRIGGER_DELAYS_MASK)
331 #define LRADC_DELAY_LOOP_COUNT_MASK             (0x1f << 11)
332 #define LRADC_DELAY_LOOP_COUNT_OFFSET           11
333 #define LRADC_DELAY_LOOP(x) \
334                                 (((x) << LRADC_DELAY_LOOP_COUNT_OFFSET) & \
335                                 LRADC_DELAY_LOOP_COUNT_MASK)
336 #define LRADC_DELAY_DELAY_MASK                  0x7ff
337 #define LRADC_DELAY_DELAY_OFFSET                0
338 #define LRADC_DELAY_DELAY(x) \
339                                 (((x) << LRADC_DELAY_DELAY_OFFSET) & \
340                                 LRADC_DELAY_DELAY_MASK)
341 
342 #define LRADC_CTRL4                             0x140
343 #define LRADC_CTRL4_LRADCSELECT_MASK(n)         (0xf << ((n) * 4))
344 #define LRADC_CTRL4_LRADCSELECT_OFFSET(n)       ((n) * 4)
345 
346 #define LRADC_RESOLUTION                        12
347 #define LRADC_SINGLE_SAMPLE_MASK                ((1 << LRADC_RESOLUTION) - 1)
348 
349 static void mxs_lradc_reg_set(struct mxs_lradc *lradc, u32 val, u32 reg)
350 {
351         writel(val, lradc->base + reg + STMP_OFFSET_REG_SET);
352 }
353 
354 static void mxs_lradc_reg_clear(struct mxs_lradc *lradc, u32 val, u32 reg)
355 {
356         writel(val, lradc->base + reg + STMP_OFFSET_REG_CLR);
357 }
358 
359 static void mxs_lradc_reg_wrt(struct mxs_lradc *lradc, u32 val, u32 reg)
360 {
361         writel(val, lradc->base + reg);
362 }
363 
364 static u32 mxs_lradc_plate_mask(struct mxs_lradc *lradc)
365 {
366         if (lradc->soc == IMX23_LRADC)
367                 return LRADC_CTRL0_MX23_PLATE_MASK;
368         return LRADC_CTRL0_MX28_PLATE_MASK;
369 }
370 
371 static u32 mxs_lradc_irq_en_mask(struct mxs_lradc *lradc)
372 {
373         if (lradc->soc == IMX23_LRADC)
374                 return LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK;
375         return LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK;
376 }
377 
378 static u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc)
379 {
380         if (lradc->soc == IMX23_LRADC)
381                 return LRADC_CTRL1_MX23_LRADC_IRQ_MASK;
382         return LRADC_CTRL1_MX28_LRADC_IRQ_MASK;
383 }
384 
385 static u32 mxs_lradc_touch_detect_bit(struct mxs_lradc *lradc)
386 {
387         if (lradc->soc == IMX23_LRADC)
388                 return LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE;
389         return LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE;
390 }
391 
392 static u32 mxs_lradc_drive_x_plate(struct mxs_lradc *lradc)
393 {
394         if (lradc->soc == IMX23_LRADC)
395                 return LRADC_CTRL0_MX23_XP | LRADC_CTRL0_MX23_XM;
396         return LRADC_CTRL0_MX28_XPPSW | LRADC_CTRL0_MX28_XNNSW;
397 }
398 
399 static u32 mxs_lradc_drive_y_plate(struct mxs_lradc *lradc)
400 {
401         if (lradc->soc == IMX23_LRADC)
402                 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_YM;
403         return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_YNNSW;
404 }
405 
406 static u32 mxs_lradc_drive_pressure(struct mxs_lradc *lradc)
407 {
408         if (lradc->soc == IMX23_LRADC)
409                 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XM;
410         return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW;
411 }
412 
413 static bool mxs_lradc_check_touch_event(struct mxs_lradc *lradc)
414 {
415         return !!(readl(lradc->base + LRADC_STATUS) &
416                                         LRADC_STATUS_TOUCH_DETECT_RAW);
417 }
418 
419 static void mxs_lradc_setup_ts_channel(struct mxs_lradc *lradc, unsigned ch)
420 {
421         /*
422          * prepare for oversampling conversion
423          *
424          * from the datasheet:
425          * "The ACCUMULATE bit in the appropriate channel register
426          * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
427          * otherwise, the IRQs will not fire."
428          */
429         mxs_lradc_reg_wrt(lradc, LRADC_CH_ACCUMULATE |
430                         LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1),
431                         LRADC_CH(ch));
432 
433         /* from the datasheet:
434          * "Software must clear this register in preparation for a
435          * multi-cycle accumulation.
436          */
437         mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch));
438 
439         /* prepare the delay/loop unit according to the oversampling count */
440         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch) |
441                 LRADC_DELAY_TRIGGER_DELAYS(0) |
442                 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
443                 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
444                         LRADC_DELAY(3));
445 
446         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(2) |
447                         LRADC_CTRL1_LRADC_IRQ(3) | LRADC_CTRL1_LRADC_IRQ(4) |
448                         LRADC_CTRL1_LRADC_IRQ(5), LRADC_CTRL1);
449 
450         /* wake us again, when the complete conversion is done */
451         mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(ch), LRADC_CTRL1);
452         /*
453          * after changing the touchscreen plates setting
454          * the signals need some initial time to settle. Start the
455          * SoC's delay unit and start the conversion later
456          * and automatically.
457          */
458         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
459                 LRADC_DELAY_TRIGGER_DELAYS(1 << 3) | /* trigger DELAY unit#3 */
460                 LRADC_DELAY_KICK |
461                 LRADC_DELAY_DELAY(lradc->settling_delay),
462                         LRADC_DELAY(2));
463 }
464 
465 /*
466  * Pressure detection is special:
467  * We want to do both required measurements for the pressure detection in
468  * one turn. Use the hardware features to chain both conversions and let the
469  * hardware report one interrupt if both conversions are done
470  */
471 static void mxs_lradc_setup_ts_pressure(struct mxs_lradc *lradc, unsigned ch1,
472                                                         unsigned ch2)
473 {
474         u32 reg;
475 
476         /*
477          * prepare for oversampling conversion
478          *
479          * from the datasheet:
480          * "The ACCUMULATE bit in the appropriate channel register
481          * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
482          * otherwise, the IRQs will not fire."
483          */
484         reg = LRADC_CH_ACCUMULATE |
485                 LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1);
486         mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch1));
487         mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch2));
488 
489         /* from the datasheet:
490          * "Software must clear this register in preparation for a
491          * multi-cycle accumulation.
492          */
493         mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch1));
494         mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch2));
495 
496         /* prepare the delay/loop unit according to the oversampling count */
497         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch1) |
498                 LRADC_DELAY_TRIGGER(1 << ch2) | /* start both channels */
499                 LRADC_DELAY_TRIGGER_DELAYS(0) |
500                 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
501                 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
502                                         LRADC_DELAY(3));
503 
504         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(2) |
505                         LRADC_CTRL1_LRADC_IRQ(3) | LRADC_CTRL1_LRADC_IRQ(4) |
506                         LRADC_CTRL1_LRADC_IRQ(5), LRADC_CTRL1);
507 
508         /* wake us again, when the conversions are done */
509         mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(ch2), LRADC_CTRL1);
510         /*
511          * after changing the touchscreen plates setting
512          * the signals need some initial time to settle. Start the
513          * SoC's delay unit and start the conversion later
514          * and automatically.
515          */
516         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
517                 LRADC_DELAY_TRIGGER_DELAYS(1 << 3) | /* trigger DELAY unit#3 */
518                 LRADC_DELAY_KICK |
519                 LRADC_DELAY_DELAY(lradc->settling_delay), LRADC_DELAY(2));
520 }
521 
522 static unsigned mxs_lradc_read_raw_channel(struct mxs_lradc *lradc,
523                                                         unsigned channel)
524 {
525         u32 reg;
526         unsigned num_samples, val;
527 
528         reg = readl(lradc->base + LRADC_CH(channel));
529         if (reg & LRADC_CH_ACCUMULATE)
530                 num_samples = lradc->over_sample_cnt;
531         else
532                 num_samples = 1;
533 
534         val = (reg & LRADC_CH_VALUE_MASK) >> LRADC_CH_VALUE_OFFSET;
535         return val / num_samples;
536 }
537 
538 static unsigned mxs_lradc_read_ts_pressure(struct mxs_lradc *lradc,
539                                                 unsigned ch1, unsigned ch2)
540 {
541         u32 reg, mask;
542         unsigned pressure, m1, m2;
543 
544         mask = LRADC_CTRL1_LRADC_IRQ(ch1) | LRADC_CTRL1_LRADC_IRQ(ch2);
545         reg = readl(lradc->base + LRADC_CTRL1) & mask;
546 
547         while (reg != mask) {
548                 reg = readl(lradc->base + LRADC_CTRL1) & mask;
549                 dev_dbg(lradc->dev, "One channel is still busy: %X\n", reg);
550         }
551 
552         m1 = mxs_lradc_read_raw_channel(lradc, ch1);
553         m2 = mxs_lradc_read_raw_channel(lradc, ch2);
554 
555         if (m2 == 0) {
556                 dev_warn(lradc->dev, "Cannot calculate pressure\n");
557                 return 1 << (LRADC_RESOLUTION - 1);
558         }
559 
560         /* simply scale the value from 0 ... max ADC resolution */
561         pressure = m1;
562         pressure *= (1 << LRADC_RESOLUTION);
563         pressure /= m2;
564 
565         dev_dbg(lradc->dev, "Pressure = %u\n", pressure);
566         return pressure;
567 }
568 
569 #define TS_CH_XP 2
570 #define TS_CH_YP 3
571 #define TS_CH_XM 4
572 #define TS_CH_YM 5
573 
574 static int mxs_lradc_read_ts_channel(struct mxs_lradc *lradc)
575 {
576         u32 reg;
577         int val;
578 
579         reg = readl(lradc->base + LRADC_CTRL1);
580 
581         /* only channels 3 to 5 are of interest here */
582         if (reg & LRADC_CTRL1_LRADC_IRQ(TS_CH_YP)) {
583                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(TS_CH_YP) |
584                         LRADC_CTRL1_LRADC_IRQ(TS_CH_YP), LRADC_CTRL1);
585                 val = mxs_lradc_read_raw_channel(lradc, TS_CH_YP);
586         } else if (reg & LRADC_CTRL1_LRADC_IRQ(TS_CH_XM)) {
587                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(TS_CH_XM) |
588                         LRADC_CTRL1_LRADC_IRQ(TS_CH_XM), LRADC_CTRL1);
589                 val = mxs_lradc_read_raw_channel(lradc, TS_CH_XM);
590         } else if (reg & LRADC_CTRL1_LRADC_IRQ(TS_CH_YM)) {
591                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(TS_CH_YM) |
592                         LRADC_CTRL1_LRADC_IRQ(TS_CH_YM), LRADC_CTRL1);
593                 val = mxs_lradc_read_raw_channel(lradc, TS_CH_YM);
594         } else {
595                 return -EIO;
596         }
597 
598         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
599         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
600 
601         return val;
602 }
603 
604 /*
605  * YP(open)--+-------------+
606  *           |             |--+
607  *           |             |  |
608  *    YM(-)--+-------------+  |
609  *             +--------------+
610  *             |              |
611  *         XP(weak+)        XM(open)
612  *
613  * "weak+" means 200k Ohm VDDIO
614  * (-) means GND
615  */
616 static void mxs_lradc_setup_touch_detection(struct mxs_lradc *lradc)
617 {
618         /*
619          * In order to detect a touch event the 'touch detect enable' bit
620          * enables:
621          *  - a weak pullup to the X+ connector
622          *  - a strong ground at the Y- connector
623          */
624         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
625         mxs_lradc_reg_set(lradc, mxs_lradc_touch_detect_bit(lradc),
626                                 LRADC_CTRL0);
627 }
628 
629 /*
630  * YP(meas)--+-------------+
631  *           |             |--+
632  *           |             |  |
633  * YM(open)--+-------------+  |
634  *             +--------------+
635  *             |              |
636  *           XP(+)          XM(-)
637  *
638  * (+) means here 1.85 V
639  * (-) means here GND
640  */
641 static void mxs_lradc_prepare_x_pos(struct mxs_lradc *lradc)
642 {
643         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
644         mxs_lradc_reg_set(lradc, mxs_lradc_drive_x_plate(lradc), LRADC_CTRL0);
645 
646         lradc->cur_plate = LRADC_SAMPLE_X;
647         mxs_lradc_setup_ts_channel(lradc, TS_CH_YP);
648 }
649 
650 /*
651  *   YP(+)--+-------------+
652  *          |             |--+
653  *          |             |  |
654  *   YM(-)--+-------------+  |
655  *            +--------------+
656  *            |              |
657  *         XP(open)        XM(meas)
658  *
659  * (+) means here 1.85 V
660  * (-) means here GND
661  */
662 static void mxs_lradc_prepare_y_pos(struct mxs_lradc *lradc)
663 {
664         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
665         mxs_lradc_reg_set(lradc, mxs_lradc_drive_y_plate(lradc), LRADC_CTRL0);
666 
667         lradc->cur_plate = LRADC_SAMPLE_Y;
668         mxs_lradc_setup_ts_channel(lradc, TS_CH_XM);
669 }
670 
671 /*
672  *    YP(+)--+-------------+
673  *           |             |--+
674  *           |             |  |
675  * YM(meas)--+-------------+  |
676  *             +--------------+
677  *             |              |
678  *          XP(meas)        XM(-)
679  *
680  * (+) means here 1.85 V
681  * (-) means here GND
682  */
683 static void mxs_lradc_prepare_pressure(struct mxs_lradc *lradc)
684 {
685         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
686         mxs_lradc_reg_set(lradc, mxs_lradc_drive_pressure(lradc), LRADC_CTRL0);
687 
688         lradc->cur_plate = LRADC_SAMPLE_PRESSURE;
689         mxs_lradc_setup_ts_pressure(lradc, TS_CH_XP, TS_CH_YM);
690 }
691 
692 static void mxs_lradc_enable_touch_detection(struct mxs_lradc *lradc)
693 {
694         mxs_lradc_setup_touch_detection(lradc);
695 
696         lradc->cur_plate = LRADC_TOUCH;
697         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ |
698                                 LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
699         mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
700 }
701 
702 static void mxs_lradc_report_ts_event(struct mxs_lradc *lradc)
703 {
704         input_report_abs(lradc->ts_input, ABS_X, lradc->ts_x_pos);
705         input_report_abs(lradc->ts_input, ABS_Y, lradc->ts_y_pos);
706         input_report_abs(lradc->ts_input, ABS_PRESSURE, lradc->ts_pressure);
707         input_report_key(lradc->ts_input, BTN_TOUCH, 1);
708         input_sync(lradc->ts_input);
709 }
710 
711 static void mxs_lradc_complete_touch_event(struct mxs_lradc *lradc)
712 {
713         mxs_lradc_setup_touch_detection(lradc);
714         lradc->cur_plate = LRADC_SAMPLE_VALID;
715         /*
716          * start a dummy conversion to burn time to settle the signals
717          * note: we are not interested in the conversion's value
718          */
719         mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(5));
720         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(5), LRADC_CTRL1);
721         mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(5), LRADC_CTRL1);
722         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << 5) |
723                 LRADC_DELAY_KICK | LRADC_DELAY_DELAY(10), /* waste 5 ms */
724                         LRADC_DELAY(2));
725 }
726 
727 /*
728  * in order to avoid false measurements, report only samples where
729  * the surface is still touched after the position measurement
730  */
731 static void mxs_lradc_finish_touch_event(struct mxs_lradc *lradc, bool valid)
732 {
733         /* if it is still touched, report the sample */
734         if (valid && mxs_lradc_check_touch_event(lradc)) {
735                 lradc->ts_valid = true;
736                 mxs_lradc_report_ts_event(lradc);
737         }
738 
739         /* if it is even still touched, continue with the next measurement */
740         if (mxs_lradc_check_touch_event(lradc)) {
741                 mxs_lradc_prepare_y_pos(lradc);
742                 return;
743         }
744 
745         if (lradc->ts_valid) {
746                 /* signal the release */
747                 lradc->ts_valid = false;
748                 input_report_key(lradc->ts_input, BTN_TOUCH, 0);
749                 input_sync(lradc->ts_input);
750         }
751 
752         /* if it is released, wait for the next touch via IRQ */
753         lradc->cur_plate = LRADC_TOUCH;
754         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ, LRADC_CTRL1);
755         mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
756 }
757 
758 /* touchscreen's state machine */
759 static void mxs_lradc_handle_touch(struct mxs_lradc *lradc)
760 {
761         int val;
762 
763         switch (lradc->cur_plate) {
764         case LRADC_TOUCH:
765                 /*
766                  * start with the Y-pos, because it uses nearly the same plate
767                  * settings like the touch detection
768                  */
769                 if (mxs_lradc_check_touch_event(lradc)) {
770                         mxs_lradc_reg_clear(lradc,
771                                         LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
772                                         LRADC_CTRL1);
773                         mxs_lradc_prepare_y_pos(lradc);
774                 }
775                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ,
776                                         LRADC_CTRL1);
777                 return;
778 
779         case LRADC_SAMPLE_Y:
780                 val = mxs_lradc_read_ts_channel(lradc);
781                 if (val < 0) {
782                         mxs_lradc_enable_touch_detection(lradc); /* re-start */
783                         return;
784                 }
785                 lradc->ts_y_pos = val;
786                 mxs_lradc_prepare_x_pos(lradc);
787                 return;
788 
789         case LRADC_SAMPLE_X:
790                 val = mxs_lradc_read_ts_channel(lradc);
791                 if (val < 0) {
792                         mxs_lradc_enable_touch_detection(lradc); /* re-start */
793                         return;
794                 }
795                 lradc->ts_x_pos = val;
796                 mxs_lradc_prepare_pressure(lradc);
797                 return;
798 
799         case LRADC_SAMPLE_PRESSURE:
800                 lradc->ts_pressure =
801                         mxs_lradc_read_ts_pressure(lradc, TS_CH_XP, TS_CH_YM);
802                 mxs_lradc_complete_touch_event(lradc);
803                 return;
804 
805         case LRADC_SAMPLE_VALID:
806                 val = mxs_lradc_read_ts_channel(lradc); /* ignore the value */
807                 mxs_lradc_finish_touch_event(lradc, 1);
808                 break;
809         }
810 }
811 
812 /*
813  * Raw I/O operations
814  */
815 static int mxs_lradc_read_single(struct iio_dev *iio_dev, int chan, int *val)
816 {
817         struct mxs_lradc *lradc = iio_priv(iio_dev);
818         int ret;
819 
820         /*
821          * See if there is no buffered operation in progess. If there is, simply
822          * bail out. This can be improved to support both buffered and raw IO at
823          * the same time, yet the code becomes horribly complicated. Therefore I
824          * applied KISS principle here.
825          */
826         ret = mutex_trylock(&lradc->lock);
827         if (!ret)
828                 return -EBUSY;
829 
830         reinit_completion(&lradc->completion);
831 
832         /*
833          * No buffered operation in progress, map the channel and trigger it.
834          * Virtual channel 0 is always used here as the others are always not
835          * used if doing raw sampling.
836          */
837         if (lradc->soc == IMX28_LRADC)
838                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
839                         LRADC_CTRL1);
840         mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
841 
842         /* Enable / disable the divider per requirement */
843         if (test_bit(chan, &lradc->is_divided))
844                 mxs_lradc_reg_set(lradc, 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
845                         LRADC_CTRL2);
846         else
847                 mxs_lradc_reg_clear(lradc,
848                         1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, LRADC_CTRL2);
849 
850         /* Clean the slot's previous content, then set new one. */
851         mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0),
852                         LRADC_CTRL4);
853         mxs_lradc_reg_set(lradc, chan, LRADC_CTRL4);
854 
855         mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(0));
856 
857         /* Enable the IRQ and start sampling the channel. */
858         mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
859         mxs_lradc_reg_set(lradc, 1 << 0, LRADC_CTRL0);
860 
861         /* Wait for completion on the channel, 1 second max. */
862         ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
863         if (!ret)
864                 ret = -ETIMEDOUT;
865         if (ret < 0)
866                 goto err;
867 
868         /* Read the data. */
869         *val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
870         ret = IIO_VAL_INT;
871 
872 err:
873         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
874 
875         mutex_unlock(&lradc->lock);
876 
877         return ret;
878 }
879 
880 static int mxs_lradc_read_temp(struct iio_dev *iio_dev, int *val)
881 {
882         int ret, min, max;
883 
884         ret = mxs_lradc_read_single(iio_dev, 8, &min);
885         if (ret != IIO_VAL_INT)
886                 return ret;
887 
888         ret = mxs_lradc_read_single(iio_dev, 9, &max);
889         if (ret != IIO_VAL_INT)
890                 return ret;
891 
892         *val = max - min;
893 
894         return IIO_VAL_INT;
895 }
896 
897 static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
898                         const struct iio_chan_spec *chan,
899                         int *val, int *val2, long m)
900 {
901         struct mxs_lradc *lradc = iio_priv(iio_dev);
902 
903         switch (m) {
904         case IIO_CHAN_INFO_RAW:
905                 if (chan->type == IIO_TEMP)
906                         return mxs_lradc_read_temp(iio_dev, val);
907 
908                 return mxs_lradc_read_single(iio_dev, chan->channel, val);
909 
910         case IIO_CHAN_INFO_SCALE:
911                 if (chan->type == IIO_TEMP) {
912                         /* From the datasheet, we have to multiply by 1.012 and
913                          * divide by 4
914                          */
915                         *val = 0;
916                         *val2 = 253000;
917                         return IIO_VAL_INT_PLUS_MICRO;
918                 }
919 
920                 *val = lradc->vref_mv[chan->channel];
921                 *val2 = chan->scan_type.realbits -
922                         test_bit(chan->channel, &lradc->is_divided);
923                 return IIO_VAL_FRACTIONAL_LOG2;
924 
925         case IIO_CHAN_INFO_OFFSET:
926                 if (chan->type == IIO_TEMP) {
927                         /* The calculated value from the ADC is in Kelvin, we
928                          * want Celsius for hwmon so the offset is
929                          * -272.15 * scale
930                          */
931                         *val = -1075;
932                         *val2 = 691699;
933 
934                         return IIO_VAL_INT_PLUS_MICRO;
935                 }
936 
937                 return -EINVAL;
938 
939         default:
940                 break;
941         }
942 
943         return -EINVAL;
944 }
945 
946 static int mxs_lradc_write_raw(struct iio_dev *iio_dev,
947                                const struct iio_chan_spec *chan,
948                                int val, int val2, long m)
949 {
950         struct mxs_lradc *lradc = iio_priv(iio_dev);
951         struct mxs_lradc_scale *scale_avail =
952                         lradc->scale_avail[chan->channel];
953         int ret;
954 
955         ret = mutex_trylock(&lradc->lock);
956         if (!ret)
957                 return -EBUSY;
958 
959         switch (m) {
960         case IIO_CHAN_INFO_SCALE:
961                 ret = -EINVAL;
962                 if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
963                     val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
964                         /* divider by two disabled */
965                         clear_bit(chan->channel, &lradc->is_divided);
966                         ret = 0;
967                 } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
968                            val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
969                         /* divider by two enabled */
970                         set_bit(chan->channel, &lradc->is_divided);
971                         ret = 0;
972                 }
973 
974                 break;
975         default:
976                 ret = -EINVAL;
977                 break;
978         }
979 
980         mutex_unlock(&lradc->lock);
981 
982         return ret;
983 }
984 
985 static int mxs_lradc_write_raw_get_fmt(struct iio_dev *iio_dev,
986                                        const struct iio_chan_spec *chan,
987                                        long m)
988 {
989         return IIO_VAL_INT_PLUS_NANO;
990 }
991 
992 static ssize_t mxs_lradc_show_scale_available_ch(struct device *dev,
993                 struct device_attribute *attr,
994                 char *buf,
995                 int ch)
996 {
997         struct iio_dev *iio = dev_to_iio_dev(dev);
998         struct mxs_lradc *lradc = iio_priv(iio);
999         int i, len = 0;
1000 
1001         for (i = 0; i < ARRAY_SIZE(lradc->scale_avail[ch]); i++)
1002                 len += sprintf(buf + len, "%d.%09u ",
1003                                lradc->scale_avail[ch][i].integer,
1004                                lradc->scale_avail[ch][i].nano);
1005 
1006         len += sprintf(buf + len, "\n");
1007 
1008         return len;
1009 }
1010 
1011 static ssize_t mxs_lradc_show_scale_available(struct device *dev,
1012                 struct device_attribute *attr,
1013                 char *buf)
1014 {
1015         struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
1016 
1017         return mxs_lradc_show_scale_available_ch(dev, attr, buf,
1018                                                  iio_attr->address);
1019 }
1020 
1021 #define SHOW_SCALE_AVAILABLE_ATTR(ch)                                   \
1022 static IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, S_IRUGO,       \
1023                        mxs_lradc_show_scale_available, NULL, ch)
1024 
1025 SHOW_SCALE_AVAILABLE_ATTR(0);
1026 SHOW_SCALE_AVAILABLE_ATTR(1);
1027 SHOW_SCALE_AVAILABLE_ATTR(2);
1028 SHOW_SCALE_AVAILABLE_ATTR(3);
1029 SHOW_SCALE_AVAILABLE_ATTR(4);
1030 SHOW_SCALE_AVAILABLE_ATTR(5);
1031 SHOW_SCALE_AVAILABLE_ATTR(6);
1032 SHOW_SCALE_AVAILABLE_ATTR(7);
1033 SHOW_SCALE_AVAILABLE_ATTR(10);
1034 SHOW_SCALE_AVAILABLE_ATTR(11);
1035 SHOW_SCALE_AVAILABLE_ATTR(12);
1036 SHOW_SCALE_AVAILABLE_ATTR(13);
1037 SHOW_SCALE_AVAILABLE_ATTR(14);
1038 SHOW_SCALE_AVAILABLE_ATTR(15);
1039 
1040 static struct attribute *mxs_lradc_attributes[] = {
1041         &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
1042         &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
1043         &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
1044         &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
1045         &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
1046         &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
1047         &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
1048         &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
1049         &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
1050         &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
1051         &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
1052         &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
1053         &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
1054         &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
1055         NULL
1056 };
1057 
1058 static const struct attribute_group mxs_lradc_attribute_group = {
1059         .attrs = mxs_lradc_attributes,
1060 };
1061 
1062 static const struct iio_info mxs_lradc_iio_info = {
1063         .driver_module          = THIS_MODULE,
1064         .read_raw               = mxs_lradc_read_raw,
1065         .write_raw              = mxs_lradc_write_raw,
1066         .write_raw_get_fmt      = mxs_lradc_write_raw_get_fmt,
1067         .attrs                  = &mxs_lradc_attribute_group,
1068 };
1069 
1070 static int mxs_lradc_ts_open(struct input_dev *dev)
1071 {
1072         struct mxs_lradc *lradc = input_get_drvdata(dev);
1073 
1074         /* Enable the touch-detect circuitry. */
1075         mxs_lradc_enable_touch_detection(lradc);
1076 
1077         return 0;
1078 }
1079 
1080 static void mxs_lradc_disable_ts(struct mxs_lradc *lradc)
1081 {
1082         /* stop all interrupts from firing */
1083         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN |
1084                 LRADC_CTRL1_LRADC_IRQ_EN(2) | LRADC_CTRL1_LRADC_IRQ_EN(3) |
1085                 LRADC_CTRL1_LRADC_IRQ_EN(4) | LRADC_CTRL1_LRADC_IRQ_EN(5),
1086                 LRADC_CTRL1);
1087 
1088         /* Power-down touchscreen touch-detect circuitry. */
1089         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
1090 }
1091 
1092 static void mxs_lradc_ts_close(struct input_dev *dev)
1093 {
1094         struct mxs_lradc *lradc = input_get_drvdata(dev);
1095 
1096         mxs_lradc_disable_ts(lradc);
1097 }
1098 
1099 static int mxs_lradc_ts_register(struct mxs_lradc *lradc)
1100 {
1101         struct input_dev *input;
1102         struct device *dev = lradc->dev;
1103         int ret;
1104 
1105         if (!lradc->use_touchscreen)
1106                 return 0;
1107 
1108         input = input_allocate_device();
1109         if (!input)
1110                 return -ENOMEM;
1111 
1112         input->name = DRIVER_NAME;
1113         input->id.bustype = BUS_HOST;
1114         input->dev.parent = dev;
1115         input->open = mxs_lradc_ts_open;
1116         input->close = mxs_lradc_ts_close;
1117 
1118         __set_bit(EV_ABS, input->evbit);
1119         __set_bit(EV_KEY, input->evbit);
1120         __set_bit(BTN_TOUCH, input->keybit);
1121         input_set_abs_params(input, ABS_X, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1122         input_set_abs_params(input, ABS_Y, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1123         input_set_abs_params(input, ABS_PRESSURE, 0, LRADC_SINGLE_SAMPLE_MASK,
1124                              0, 0);
1125 
1126         lradc->ts_input = input;
1127         input_set_drvdata(input, lradc);
1128         ret = input_register_device(input);
1129         if (ret)
1130                 input_free_device(lradc->ts_input);
1131 
1132         return ret;
1133 }
1134 
1135 static void mxs_lradc_ts_unregister(struct mxs_lradc *lradc)
1136 {
1137         if (!lradc->use_touchscreen)
1138                 return;
1139 
1140         mxs_lradc_disable_ts(lradc);
1141         input_unregister_device(lradc->ts_input);
1142 }
1143 
1144 /*
1145  * IRQ Handling
1146  */
1147 static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
1148 {
1149         struct iio_dev *iio = data;
1150         struct mxs_lradc *lradc = iio_priv(iio);
1151         unsigned long reg = readl(lradc->base + LRADC_CTRL1);
1152         const uint32_t ts_irq_mask =
1153                 LRADC_CTRL1_TOUCH_DETECT_IRQ |
1154                 LRADC_CTRL1_LRADC_IRQ(2) |
1155                 LRADC_CTRL1_LRADC_IRQ(3) |
1156                 LRADC_CTRL1_LRADC_IRQ(4) |
1157                 LRADC_CTRL1_LRADC_IRQ(5);
1158 
1159         if (!(reg & mxs_lradc_irq_mask(lradc)))
1160                 return IRQ_NONE;
1161 
1162         if (lradc->use_touchscreen && (reg & ts_irq_mask))
1163                 mxs_lradc_handle_touch(lradc);
1164 
1165         if (iio_buffer_enabled(iio))
1166                 iio_trigger_poll(iio->trig);
1167         else if (reg & LRADC_CTRL1_LRADC_IRQ(0))
1168                 complete(&lradc->completion);
1169 
1170         mxs_lradc_reg_clear(lradc, reg & mxs_lradc_irq_mask(lradc),
1171                         LRADC_CTRL1);
1172 
1173         return IRQ_HANDLED;
1174 }
1175 
1176 /*
1177  * Trigger handling
1178  */
1179 static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
1180 {
1181         struct iio_poll_func *pf = p;
1182         struct iio_dev *iio = pf->indio_dev;
1183         struct mxs_lradc *lradc = iio_priv(iio);
1184         const uint32_t chan_value = LRADC_CH_ACCUMULATE |
1185                 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1186         unsigned int i, j = 0;
1187 
1188         for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1189                 lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
1190                 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(j));
1191                 lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
1192                 lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
1193                 j++;
1194         }
1195 
1196         iio_push_to_buffers_with_timestamp(iio, lradc->buffer, pf->timestamp);
1197 
1198         iio_trigger_notify_done(iio->trig);
1199 
1200         return IRQ_HANDLED;
1201 }
1202 
1203 static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
1204 {
1205         struct iio_dev *iio = iio_trigger_get_drvdata(trig);
1206         struct mxs_lradc *lradc = iio_priv(iio);
1207         const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
1208 
1209         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_KICK, LRADC_DELAY(0) + st);
1210 
1211         return 0;
1212 }
1213 
1214 static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
1215         .owner = THIS_MODULE,
1216         .set_trigger_state = &mxs_lradc_configure_trigger,
1217 };
1218 
1219 static int mxs_lradc_trigger_init(struct iio_dev *iio)
1220 {
1221         int ret;
1222         struct iio_trigger *trig;
1223         struct mxs_lradc *lradc = iio_priv(iio);
1224 
1225         trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
1226         if (trig == NULL)
1227                 return -ENOMEM;
1228 
1229         trig->dev.parent = lradc->dev;
1230         iio_trigger_set_drvdata(trig, iio);
1231         trig->ops = &mxs_lradc_trigger_ops;
1232 
1233         ret = iio_trigger_register(trig);
1234         if (ret) {
1235                 iio_trigger_free(trig);
1236                 return ret;
1237         }
1238 
1239         lradc->trig = trig;
1240 
1241         return 0;
1242 }
1243 
1244 static void mxs_lradc_trigger_remove(struct iio_dev *iio)
1245 {
1246         struct mxs_lradc *lradc = iio_priv(iio);
1247 
1248         iio_trigger_unregister(lradc->trig);
1249         iio_trigger_free(lradc->trig);
1250 }
1251 
1252 static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
1253 {
1254         struct mxs_lradc *lradc = iio_priv(iio);
1255         int ret = 0, chan, ofs = 0;
1256         unsigned long enable = 0;
1257         uint32_t ctrl4_set = 0;
1258         uint32_t ctrl4_clr = 0;
1259         uint32_t ctrl1_irq = 0;
1260         const uint32_t chan_value = LRADC_CH_ACCUMULATE |
1261                 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1262         const int len = bitmap_weight(iio->active_scan_mask,
1263                         LRADC_MAX_TOTAL_CHANS);
1264 
1265         if (!len)
1266                 return -EINVAL;
1267 
1268         /*
1269          * Lock the driver so raw access can not be done during buffered
1270          * operation. This simplifies the code a lot.
1271          */
1272         ret = mutex_trylock(&lradc->lock);
1273         if (!ret)
1274                 return -EBUSY;
1275 
1276         lradc->buffer = kmalloc_array(len, sizeof(*lradc->buffer), GFP_KERNEL);
1277         if (!lradc->buffer) {
1278                 ret = -ENOMEM;
1279                 goto err_mem;
1280         }
1281 
1282         if (lradc->soc == IMX28_LRADC)
1283                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
1284                                                         LRADC_CTRL1);
1285         mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
1286 
1287         for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1288                 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
1289                 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
1290                 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
1291                 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(ofs));
1292                 bitmap_set(&enable, ofs, 1);
1293                 ofs++;
1294         }
1295 
1296         mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1297                                         LRADC_DELAY_KICK, LRADC_DELAY(0));
1298         mxs_lradc_reg_clear(lradc, ctrl4_clr, LRADC_CTRL4);
1299         mxs_lradc_reg_set(lradc, ctrl4_set, LRADC_CTRL4);
1300         mxs_lradc_reg_set(lradc, ctrl1_irq, LRADC_CTRL1);
1301         mxs_lradc_reg_set(lradc, enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
1302                                         LRADC_DELAY(0));
1303 
1304         return 0;
1305 
1306 err_mem:
1307         mutex_unlock(&lradc->lock);
1308         return ret;
1309 }
1310 
1311 static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
1312 {
1313         struct mxs_lradc *lradc = iio_priv(iio);
1314 
1315         mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1316                                         LRADC_DELAY_KICK, LRADC_DELAY(0));
1317 
1318         mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
1319         if (lradc->soc == IMX28_LRADC)
1320                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
1321                                         LRADC_CTRL1);
1322 
1323         kfree(lradc->buffer);
1324         mutex_unlock(&lradc->lock);
1325 
1326         return 0;
1327 }
1328 
1329 static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
1330                                         const unsigned long *mask)
1331 {
1332         struct mxs_lradc *lradc = iio_priv(iio);
1333         const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
1334         int rsvd_chans = 0;
1335         unsigned long rsvd_mask = 0;
1336 
1337         if (lradc->use_touchbutton)
1338                 rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
1339         if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_4WIRE)
1340                 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
1341         if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1342                 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
1343 
1344         if (lradc->use_touchbutton)
1345                 rsvd_chans++;
1346         if (lradc->use_touchscreen)
1347                 rsvd_chans++;
1348 
1349         /* Test for attempts to map channels with special mode of operation. */
1350         if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
1351                 return false;
1352 
1353         /* Test for attempts to map more channels then available slots. */
1354         if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
1355                 return false;
1356 
1357         return true;
1358 }
1359 
1360 static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
1361         .preenable = &mxs_lradc_buffer_preenable,
1362         .postenable = &iio_triggered_buffer_postenable,
1363         .predisable = &iio_triggered_buffer_predisable,
1364         .postdisable = &mxs_lradc_buffer_postdisable,
1365         .validate_scan_mask = &mxs_lradc_validate_scan_mask,
1366 };
1367 
1368 /*
1369  * Driver initialization
1370  */
1371 
1372 #define MXS_ADC_CHAN(idx, chan_type) {                          \
1373         .type = (chan_type),                                    \
1374         .indexed = 1,                                           \
1375         .scan_index = (idx),                                    \
1376         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
1377                               BIT(IIO_CHAN_INFO_SCALE),         \
1378         .channel = (idx),                                       \
1379         .address = (idx),                                       \
1380         .scan_type = {                                          \
1381                 .sign = 'u',                                    \
1382                 .realbits = LRADC_RESOLUTION,                   \
1383                 .storagebits = 32,                              \
1384         },                                                      \
1385 }
1386 
1387 static const struct iio_chan_spec mxs_lradc_chan_spec[] = {
1388         MXS_ADC_CHAN(0, IIO_VOLTAGE),
1389         MXS_ADC_CHAN(1, IIO_VOLTAGE),
1390         MXS_ADC_CHAN(2, IIO_VOLTAGE),
1391         MXS_ADC_CHAN(3, IIO_VOLTAGE),
1392         MXS_ADC_CHAN(4, IIO_VOLTAGE),
1393         MXS_ADC_CHAN(5, IIO_VOLTAGE),
1394         MXS_ADC_CHAN(6, IIO_VOLTAGE),
1395         MXS_ADC_CHAN(7, IIO_VOLTAGE),   /* VBATT */
1396         /* Combined Temperature sensors */
1397         {
1398                 .type = IIO_TEMP,
1399                 .indexed = 1,
1400                 .scan_index = 8,
1401                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1402                                       BIT(IIO_CHAN_INFO_OFFSET) |
1403                                       BIT(IIO_CHAN_INFO_SCALE),
1404                 .channel = 8,
1405                 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
1406         },
1407         MXS_ADC_CHAN(10, IIO_VOLTAGE),  /* VDDIO */
1408         MXS_ADC_CHAN(11, IIO_VOLTAGE),  /* VTH */
1409         MXS_ADC_CHAN(12, IIO_VOLTAGE),  /* VDDA */
1410         MXS_ADC_CHAN(13, IIO_VOLTAGE),  /* VDDD */
1411         MXS_ADC_CHAN(14, IIO_VOLTAGE),  /* VBG */
1412         MXS_ADC_CHAN(15, IIO_VOLTAGE),  /* VDD5V */
1413 };
1414 
1415 static int mxs_lradc_hw_init(struct mxs_lradc *lradc)
1416 {
1417         /* The ADC always uses DELAY CHANNEL 0. */
1418         const uint32_t adc_cfg =
1419                 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
1420                 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
1421 
1422         int ret = stmp_reset_block(lradc->base);
1423 
1424         if (ret)
1425                 return ret;
1426 
1427         /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
1428         mxs_lradc_reg_wrt(lradc, adc_cfg, LRADC_DELAY(0));
1429 
1430         /* Disable remaining DELAY CHANNELs */
1431         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(1));
1432         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
1433         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
1434 
1435         /* Configure the touchscreen type */
1436         if (lradc->soc == IMX28_LRADC) {
1437                 mxs_lradc_reg_clear(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
1438                                                         LRADC_CTRL0);
1439 
1440         if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1441                 mxs_lradc_reg_set(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
1442                                 LRADC_CTRL0);
1443         }
1444 
1445         /* Start internal temperature sensing. */
1446         mxs_lradc_reg_wrt(lradc, 0, LRADC_CTRL2);
1447 
1448         return 0;
1449 }
1450 
1451 static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
1452 {
1453         int i;
1454 
1455         mxs_lradc_reg_clear(lradc, mxs_lradc_irq_en_mask(lradc), LRADC_CTRL1);
1456 
1457         for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
1458                 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(i));
1459 }
1460 
1461 static const struct of_device_id mxs_lradc_dt_ids[] = {
1462         { .compatible = "fsl,imx23-lradc", .data = (void *)IMX23_LRADC, },
1463         { .compatible = "fsl,imx28-lradc", .data = (void *)IMX28_LRADC, },
1464         { /* sentinel */ }
1465 };
1466 MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
1467 
1468 static int mxs_lradc_probe_touchscreen(struct mxs_lradc *lradc,
1469                                                 struct device_node *lradc_node)
1470 {
1471         int ret;
1472         u32 ts_wires = 0, adapt;
1473 
1474         ret = of_property_read_u32(lradc_node, "fsl,lradc-touchscreen-wires",
1475                                 &ts_wires);
1476         if (ret)
1477                 return -ENODEV; /* touchscreen feature disabled */
1478 
1479         switch (ts_wires) {
1480         case 4:
1481                 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_4WIRE;
1482                 break;
1483         case 5:
1484                 if (lradc->soc == IMX28_LRADC) {
1485                         lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_5WIRE;
1486                         break;
1487                 }
1488                 /* fall through an error message for i.MX23 */
1489         default:
1490                 dev_err(lradc->dev,
1491                         "Unsupported number of touchscreen wires (%d)\n",
1492                         ts_wires);
1493                 return -EINVAL;
1494         }
1495 
1496         lradc->over_sample_cnt = 4;
1497         ret = of_property_read_u32(lradc_node, "fsl,ave-ctrl", &adapt);
1498         if (ret == 0)
1499                 lradc->over_sample_cnt = adapt;
1500 
1501         lradc->over_sample_delay = 2;
1502         ret = of_property_read_u32(lradc_node, "fsl,ave-delay", &adapt);
1503         if (ret == 0)
1504                 lradc->over_sample_delay = adapt;
1505 
1506         lradc->settling_delay = 10;
1507         ret = of_property_read_u32(lradc_node, "fsl,settling", &adapt);
1508         if (ret == 0)
1509                 lradc->settling_delay = adapt;
1510 
1511         return 0;
1512 }
1513 
1514 static int mxs_lradc_probe(struct platform_device *pdev)
1515 {
1516         const struct of_device_id *of_id =
1517                 of_match_device(mxs_lradc_dt_ids, &pdev->dev);
1518         const struct mxs_lradc_of_config *of_cfg =
1519                 &mxs_lradc_of_config[(enum mxs_lradc_id)of_id->data];
1520         struct device *dev = &pdev->dev;
1521         struct device_node *node = dev->of_node;
1522         struct mxs_lradc *lradc;
1523         struct iio_dev *iio;
1524         struct resource *iores;
1525         int ret = 0, touch_ret;
1526         int i, s;
1527         uint64_t scale_uv;
1528 
1529         /* Allocate the IIO device. */
1530         iio = devm_iio_device_alloc(dev, sizeof(*lradc));
1531         if (!iio) {
1532                 dev_err(dev, "Failed to allocate IIO device\n");
1533                 return -ENOMEM;
1534         }
1535 
1536         lradc = iio_priv(iio);
1537         lradc->soc = (enum mxs_lradc_id)of_id->data;
1538 
1539         /* Grab the memory area */
1540         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1541         lradc->dev = &pdev->dev;
1542         lradc->base = devm_ioremap_resource(dev, iores);
1543         if (IS_ERR(lradc->base))
1544                 return PTR_ERR(lradc->base);
1545 
1546         lradc->clk = devm_clk_get(&pdev->dev, NULL);
1547         if (IS_ERR(lradc->clk)) {
1548                 dev_err(dev, "Failed to get the delay unit clock\n");
1549                 return PTR_ERR(lradc->clk);
1550         }
1551         ret = clk_prepare_enable(lradc->clk);
1552         if (ret != 0) {
1553                 dev_err(dev, "Failed to enable the delay unit clock\n");
1554                 return ret;
1555         }
1556 
1557         touch_ret = mxs_lradc_probe_touchscreen(lradc, node);
1558 
1559         /* Grab all IRQ sources */
1560         for (i = 0; i < of_cfg->irq_count; i++) {
1561                 lradc->irq[i] = platform_get_irq(pdev, i);
1562                 if (lradc->irq[i] < 0) {
1563                         ret = lradc->irq[i];
1564                         goto err_clk;
1565                 }
1566 
1567                 ret = devm_request_irq(dev, lradc->irq[i],
1568                                         mxs_lradc_handle_irq, 0,
1569                                         of_cfg->irq_name[i], iio);
1570                 if (ret)
1571                         goto err_clk;
1572         }
1573 
1574         lradc->vref_mv = of_cfg->vref_mv;
1575 
1576         platform_set_drvdata(pdev, iio);
1577 
1578         init_completion(&lradc->completion);
1579         mutex_init(&lradc->lock);
1580 
1581         iio->name = pdev->name;
1582         iio->dev.parent = &pdev->dev;
1583         iio->info = &mxs_lradc_iio_info;
1584         iio->modes = INDIO_DIRECT_MODE;
1585         iio->channels = mxs_lradc_chan_spec;
1586         iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec);
1587         iio->masklength = LRADC_MAX_TOTAL_CHANS;
1588 
1589         ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
1590                                 &mxs_lradc_trigger_handler,
1591                                 &mxs_lradc_buffer_ops);
1592         if (ret)
1593                 goto err_clk;
1594 
1595         ret = mxs_lradc_trigger_init(iio);
1596         if (ret)
1597                 goto err_trig;
1598 
1599         /* Populate available ADC input ranges */
1600         for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
1601                 for (s = 0; s < ARRAY_SIZE(lradc->scale_avail[i]); s++) {
1602                         /*
1603                          * [s=0] = optional divider by two disabled (default)
1604                          * [s=1] = optional divider by two enabled
1605                          *
1606                          * The scale is calculated by doing:
1607                          *   Vref >> (realbits - s)
1608                          * which multiplies by two on the second component
1609                          * of the array.
1610                          */
1611                         scale_uv = ((u64)lradc->vref_mv[i] * 100000000) >>
1612                                    (LRADC_RESOLUTION - s);
1613                         lradc->scale_avail[i][s].nano =
1614                                         do_div(scale_uv, 100000000) * 10;
1615                         lradc->scale_avail[i][s].integer = scale_uv;
1616                 }
1617         }
1618 
1619         /* Configure the hardware. */
1620         ret = mxs_lradc_hw_init(lradc);
1621         if (ret)
1622                 goto err_dev;
1623 
1624         /* Register the touchscreen input device. */
1625         if (touch_ret == 0) {
1626                 ret = mxs_lradc_ts_register(lradc);
1627                 if (ret)
1628                         goto err_ts_register;
1629         }
1630 
1631         /* Register IIO device. */
1632         ret = iio_device_register(iio);
1633         if (ret) {
1634                 dev_err(dev, "Failed to register IIO device\n");
1635                 goto err_ts;
1636         }
1637 
1638         return 0;
1639 
1640 err_ts:
1641         mxs_lradc_ts_unregister(lradc);
1642 err_ts_register:
1643         mxs_lradc_hw_stop(lradc);
1644 err_dev:
1645         mxs_lradc_trigger_remove(iio);
1646 err_trig:
1647         iio_triggered_buffer_cleanup(iio);
1648 err_clk:
1649         clk_disable_unprepare(lradc->clk);
1650         return ret;
1651 }
1652 
1653 static int mxs_lradc_remove(struct platform_device *pdev)
1654 {
1655         struct iio_dev *iio = platform_get_drvdata(pdev);
1656         struct mxs_lradc *lradc = iio_priv(iio);
1657 
1658         iio_device_unregister(iio);
1659         mxs_lradc_ts_unregister(lradc);
1660         mxs_lradc_hw_stop(lradc);
1661         mxs_lradc_trigger_remove(iio);
1662         iio_triggered_buffer_cleanup(iio);
1663 
1664         clk_disable_unprepare(lradc->clk);
1665         return 0;
1666 }
1667 
1668 static struct platform_driver mxs_lradc_driver = {
1669         .driver = {
1670                 .name   = DRIVER_NAME,
1671                 .owner  = THIS_MODULE,
1672                 .of_match_table = mxs_lradc_dt_ids,
1673         },
1674         .probe  = mxs_lradc_probe,
1675         .remove = mxs_lradc_remove,
1676 };
1677 
1678 module_platform_driver(mxs_lradc_driver);
1679 
1680 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1681 MODULE_DESCRIPTION("Freescale i.MX28 LRADC driver");
1682 MODULE_LICENSE("GPL v2");
1683 MODULE_ALIAS("platform:" DRIVER_NAME);
1684 

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