Version:  2.0.40 2.2.26 2.4.37 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19

Linux/drivers/staging/iio/adc/mxs-lradc.c

  1 /*
  2  * Freescale i.MX28 LRADC driver
  3  *
  4  * Copyright (c) 2012 DENX Software Engineering, GmbH.
  5  * Marek Vasut <marex@denx.de>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  *
 12  * This program is distributed in the hope that it will be useful,
 13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 15  * GNU General Public License for more details.
 16  */
 17 
 18 #include <linux/err.h>
 19 #include <linux/interrupt.h>
 20 #include <linux/device.h>
 21 #include <linux/kernel.h>
 22 #include <linux/slab.h>
 23 #include <linux/of.h>
 24 #include <linux/of_device.h>
 25 #include <linux/sysfs.h>
 26 #include <linux/list.h>
 27 #include <linux/io.h>
 28 #include <linux/module.h>
 29 #include <linux/platform_device.h>
 30 #include <linux/spinlock.h>
 31 #include <linux/wait.h>
 32 #include <linux/sched.h>
 33 #include <linux/stmp_device.h>
 34 #include <linux/bitops.h>
 35 #include <linux/completion.h>
 36 #include <linux/delay.h>
 37 #include <linux/input.h>
 38 #include <linux/clk.h>
 39 
 40 #include <linux/iio/iio.h>
 41 #include <linux/iio/sysfs.h>
 42 #include <linux/iio/buffer.h>
 43 #include <linux/iio/trigger.h>
 44 #include <linux/iio/trigger_consumer.h>
 45 #include <linux/iio/triggered_buffer.h>
 46 
 47 #define DRIVER_NAME             "mxs-lradc"
 48 
 49 #define LRADC_MAX_DELAY_CHANS   4
 50 #define LRADC_MAX_MAPPED_CHANS  8
 51 #define LRADC_MAX_TOTAL_CHANS   16
 52 
 53 #define LRADC_DELAY_TIMER_HZ    2000
 54 
 55 /*
 56  * Make this runtime configurable if necessary. Currently, if the buffered mode
 57  * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
 58  * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
 59  * seconds. The result is that the samples arrive every 500mS.
 60  */
 61 #define LRADC_DELAY_TIMER_PER   200
 62 #define LRADC_DELAY_TIMER_LOOP  5
 63 
 64 /*
 65  * Once the pen touches the touchscreen, the touchscreen switches from
 66  * IRQ-driven mode to polling mode to prevent interrupt storm. The polling
 67  * is realized by worker thread, which is called every 20 or so milliseconds.
 68  * This gives the touchscreen enough fluence and does not strain the system
 69  * too much.
 70  */
 71 #define LRADC_TS_SAMPLE_DELAY_MS        5
 72 
 73 /*
 74  * The LRADC reads the following amount of samples from each touchscreen
 75  * channel and the driver then computes avarage of these.
 76  */
 77 #define LRADC_TS_SAMPLE_AMOUNT          4
 78 
 79 enum mxs_lradc_id {
 80         IMX23_LRADC,
 81         IMX28_LRADC,
 82 };
 83 
 84 static const char * const mx23_lradc_irq_names[] = {
 85         "mxs-lradc-touchscreen",
 86         "mxs-lradc-channel0",
 87         "mxs-lradc-channel1",
 88         "mxs-lradc-channel2",
 89         "mxs-lradc-channel3",
 90         "mxs-lradc-channel4",
 91         "mxs-lradc-channel5",
 92         "mxs-lradc-channel6",
 93         "mxs-lradc-channel7",
 94 };
 95 
 96 static const char * const mx28_lradc_irq_names[] = {
 97         "mxs-lradc-touchscreen",
 98         "mxs-lradc-thresh0",
 99         "mxs-lradc-thresh1",
100         "mxs-lradc-channel0",
101         "mxs-lradc-channel1",
102         "mxs-lradc-channel2",
103         "mxs-lradc-channel3",
104         "mxs-lradc-channel4",
105         "mxs-lradc-channel5",
106         "mxs-lradc-channel6",
107         "mxs-lradc-channel7",
108         "mxs-lradc-button0",
109         "mxs-lradc-button1",
110 };
111 
112 struct mxs_lradc_of_config {
113         const int               irq_count;
114         const char * const      *irq_name;
115         const uint32_t          *vref_mv;
116 };
117 
118 #define VREF_MV_BASE 1850
119 
120 static const uint32_t mx23_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
121         VREF_MV_BASE,           /* CH0 */
122         VREF_MV_BASE,           /* CH1 */
123         VREF_MV_BASE,           /* CH2 */
124         VREF_MV_BASE,           /* CH3 */
125         VREF_MV_BASE,           /* CH4 */
126         VREF_MV_BASE,           /* CH5 */
127         VREF_MV_BASE * 2,       /* CH6 VDDIO */
128         VREF_MV_BASE * 4,       /* CH7 VBATT */
129         VREF_MV_BASE,           /* CH8 Temp sense 0 */
130         VREF_MV_BASE,           /* CH9 Temp sense 1 */
131         VREF_MV_BASE,           /* CH10 */
132         VREF_MV_BASE,           /* CH11 */
133         VREF_MV_BASE,           /* CH12 USB_DP */
134         VREF_MV_BASE,           /* CH13 USB_DN */
135         VREF_MV_BASE,           /* CH14 VBG */
136         VREF_MV_BASE * 4,       /* CH15 VDD5V */
137 };
138 
139 static const uint32_t mx28_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
140         VREF_MV_BASE,           /* CH0 */
141         VREF_MV_BASE,           /* CH1 */
142         VREF_MV_BASE,           /* CH2 */
143         VREF_MV_BASE,           /* CH3 */
144         VREF_MV_BASE,           /* CH4 */
145         VREF_MV_BASE,           /* CH5 */
146         VREF_MV_BASE,           /* CH6 */
147         VREF_MV_BASE * 4,       /* CH7 VBATT */
148         VREF_MV_BASE,           /* CH8 Temp sense 0 */
149         VREF_MV_BASE,           /* CH9 Temp sense 1 */
150         VREF_MV_BASE * 2,       /* CH10 VDDIO */
151         VREF_MV_BASE,           /* CH11 VTH */
152         VREF_MV_BASE * 2,       /* CH12 VDDA */
153         VREF_MV_BASE,           /* CH13 VDDD */
154         VREF_MV_BASE,           /* CH14 VBG */
155         VREF_MV_BASE * 4,       /* CH15 VDD5V */
156 };
157 
158 static const struct mxs_lradc_of_config mxs_lradc_of_config[] = {
159         [IMX23_LRADC] = {
160                 .irq_count      = ARRAY_SIZE(mx23_lradc_irq_names),
161                 .irq_name       = mx23_lradc_irq_names,
162                 .vref_mv        = mx23_vref_mv,
163         },
164         [IMX28_LRADC] = {
165                 .irq_count      = ARRAY_SIZE(mx28_lradc_irq_names),
166                 .irq_name       = mx28_lradc_irq_names,
167                 .vref_mv        = mx28_vref_mv,
168         },
169 };
170 
171 enum mxs_lradc_ts {
172         MXS_LRADC_TOUCHSCREEN_NONE = 0,
173         MXS_LRADC_TOUCHSCREEN_4WIRE,
174         MXS_LRADC_TOUCHSCREEN_5WIRE,
175 };
176 
177 /*
178  * Touchscreen handling
179  */
180 enum lradc_ts_plate {
181         LRADC_TOUCH = 0,
182         LRADC_SAMPLE_X,
183         LRADC_SAMPLE_Y,
184         LRADC_SAMPLE_PRESSURE,
185         LRADC_SAMPLE_VALID,
186 };
187 
188 enum mxs_lradc_divbytwo {
189         MXS_LRADC_DIV_DISABLED = 0,
190         MXS_LRADC_DIV_ENABLED,
191 };
192 
193 struct mxs_lradc_scale {
194         unsigned int            integer;
195         unsigned int            nano;
196 };
197 
198 struct mxs_lradc {
199         struct device           *dev;
200         void __iomem            *base;
201         int                     irq[13];
202 
203         struct clk              *clk;
204 
205         uint32_t                *buffer;
206         struct iio_trigger      *trig;
207 
208         struct mutex            lock;
209 
210         struct completion       completion;
211 
212         const uint32_t          *vref_mv;
213         struct mxs_lradc_scale  scale_avail[LRADC_MAX_TOTAL_CHANS][2];
214         unsigned long           is_divided;
215 
216         /*
217          * Touchscreen LRADC channels receives a private slot in the CTRL4
218          * register, the slot #7. Therefore only 7 slots instead of 8 in the
219          * CTRL4 register can be mapped to LRADC channels when using the
220          * touchscreen.
221          *
222          * Furthermore, certain LRADC channels are shared between touchscreen
223          * and/or touch-buttons and generic LRADC block. Therefore when using
224          * either of these, these channels are not available for the regular
225          * sampling. The shared channels are as follows:
226          *
227          * CH0 -- Touch button #0
228          * CH1 -- Touch button #1
229          * CH2 -- Touch screen XPUL
230          * CH3 -- Touch screen YPLL
231          * CH4 -- Touch screen XNUL
232          * CH5 -- Touch screen YNLR
233          * CH6 -- Touch screen WIPER (5-wire only)
234          *
235          * The bitfields below represents which parts of the LRADC block are
236          * switched into special mode of operation. These channels can not
237          * be sampled as regular LRADC channels. The driver will refuse any
238          * attempt to sample these channels.
239          */
240 #define CHAN_MASK_TOUCHBUTTON           (0x3 << 0)
241 #define CHAN_MASK_TOUCHSCREEN_4WIRE     (0xf << 2)
242 #define CHAN_MASK_TOUCHSCREEN_5WIRE     (0x1f << 2)
243         enum mxs_lradc_ts       use_touchscreen;
244         bool                    use_touchbutton;
245 
246         struct input_dev        *ts_input;
247 
248         enum mxs_lradc_id       soc;
249         enum lradc_ts_plate     cur_plate; /* statemachine */
250         bool                    ts_valid;
251         unsigned                ts_x_pos;
252         unsigned                ts_y_pos;
253         unsigned                ts_pressure;
254 
255         /* handle touchscreen's physical behaviour */
256         /* samples per coordinate */
257         unsigned                over_sample_cnt;
258         /* time clocks between samples */
259         unsigned                over_sample_delay;
260         /* time in clocks to wait after the plates where switched */
261         unsigned                settling_delay;
262 };
263 
264 #define LRADC_CTRL0                             0x00
265 # define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE   (1 << 23)
266 # define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE     (1 << 22)
267 # define LRADC_CTRL0_MX28_YNNSW /* YM */        (1 << 21)
268 # define LRADC_CTRL0_MX28_YPNSW /* YP */        (1 << 20)
269 # define LRADC_CTRL0_MX28_YPPSW /* YP */        (1 << 19)
270 # define LRADC_CTRL0_MX28_XNNSW /* XM */        (1 << 18)
271 # define LRADC_CTRL0_MX28_XNPSW /* XM */        (1 << 17)
272 # define LRADC_CTRL0_MX28_XPPSW /* XP */        (1 << 16)
273 
274 # define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE   (1 << 20)
275 # define LRADC_CTRL0_MX23_YM                    (1 << 19)
276 # define LRADC_CTRL0_MX23_XM                    (1 << 18)
277 # define LRADC_CTRL0_MX23_YP                    (1 << 17)
278 # define LRADC_CTRL0_MX23_XP                    (1 << 16)
279 
280 # define LRADC_CTRL0_MX28_PLATE_MASK \
281                 (LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \
282                 LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \
283                 LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \
284                 LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW)
285 
286 # define LRADC_CTRL0_MX23_PLATE_MASK \
287                 (LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE | \
288                 LRADC_CTRL0_MX23_YM | LRADC_CTRL0_MX23_XM | \
289                 LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XP)
290 
291 #define LRADC_CTRL1                             0x10
292 #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN         (1 << 24)
293 #define LRADC_CTRL1_LRADC_IRQ_EN(n)             (1 << ((n) + 16))
294 #define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK      (0x1fff << 16)
295 #define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK      (0x01ff << 16)
296 #define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET         16
297 #define LRADC_CTRL1_TOUCH_DETECT_IRQ            (1 << 8)
298 #define LRADC_CTRL1_LRADC_IRQ(n)                (1 << (n))
299 #define LRADC_CTRL1_MX28_LRADC_IRQ_MASK         0x1fff
300 #define LRADC_CTRL1_MX23_LRADC_IRQ_MASK         0x01ff
301 #define LRADC_CTRL1_LRADC_IRQ_OFFSET            0
302 
303 #define LRADC_CTRL2                             0x20
304 #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET        24
305 #define LRADC_CTRL2_TEMPSENSE_PWD               (1 << 15)
306 
307 #define LRADC_STATUS                            0x40
308 #define LRADC_STATUS_TOUCH_DETECT_RAW           (1 << 0)
309 
310 #define LRADC_CH(n)                             (0x50 + (0x10 * (n)))
311 #define LRADC_CH_ACCUMULATE                     (1 << 29)
312 #define LRADC_CH_NUM_SAMPLES_MASK               (0x1f << 24)
313 #define LRADC_CH_NUM_SAMPLES_OFFSET             24
314 #define LRADC_CH_NUM_SAMPLES(x) \
315                                 ((x) << LRADC_CH_NUM_SAMPLES_OFFSET)
316 #define LRADC_CH_VALUE_MASK                     0x3ffff
317 #define LRADC_CH_VALUE_OFFSET                   0
318 
319 #define LRADC_DELAY(n)                          (0xd0 + (0x10 * (n)))
320 #define LRADC_DELAY_TRIGGER_LRADCS_MASK         (0xff << 24)
321 #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET       24
322 #define LRADC_DELAY_TRIGGER(x) \
323                                 (((x) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) & \
324                                 LRADC_DELAY_TRIGGER_LRADCS_MASK)
325 #define LRADC_DELAY_KICK                        (1 << 20)
326 #define LRADC_DELAY_TRIGGER_DELAYS_MASK         (0xf << 16)
327 #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET       16
328 #define LRADC_DELAY_TRIGGER_DELAYS(x) \
329                                 (((x) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) & \
330                                 LRADC_DELAY_TRIGGER_DELAYS_MASK)
331 #define LRADC_DELAY_LOOP_COUNT_MASK             (0x1f << 11)
332 #define LRADC_DELAY_LOOP_COUNT_OFFSET           11
333 #define LRADC_DELAY_LOOP(x) \
334                                 (((x) << LRADC_DELAY_LOOP_COUNT_OFFSET) & \
335                                 LRADC_DELAY_LOOP_COUNT_MASK)
336 #define LRADC_DELAY_DELAY_MASK                  0x7ff
337 #define LRADC_DELAY_DELAY_OFFSET                0
338 #define LRADC_DELAY_DELAY(x) \
339                                 (((x) << LRADC_DELAY_DELAY_OFFSET) & \
340                                 LRADC_DELAY_DELAY_MASK)
341 
342 #define LRADC_CTRL4                             0x140
343 #define LRADC_CTRL4_LRADCSELECT_MASK(n)         (0xf << ((n) * 4))
344 #define LRADC_CTRL4_LRADCSELECT_OFFSET(n)       ((n) * 4)
345 
346 #define LRADC_RESOLUTION                        12
347 #define LRADC_SINGLE_SAMPLE_MASK                ((1 << LRADC_RESOLUTION) - 1)
348 
349 static void mxs_lradc_reg_set(struct mxs_lradc *lradc, u32 val, u32 reg)
350 {
351         writel(val, lradc->base + reg + STMP_OFFSET_REG_SET);
352 }
353 
354 static void mxs_lradc_reg_clear(struct mxs_lradc *lradc, u32 val, u32 reg)
355 {
356         writel(val, lradc->base + reg + STMP_OFFSET_REG_CLR);
357 }
358 
359 static void mxs_lradc_reg_wrt(struct mxs_lradc *lradc, u32 val, u32 reg)
360 {
361         writel(val, lradc->base + reg);
362 }
363 
364 static u32 mxs_lradc_plate_mask(struct mxs_lradc *lradc)
365 {
366         if (lradc->soc == IMX23_LRADC)
367                 return LRADC_CTRL0_MX23_PLATE_MASK;
368         return LRADC_CTRL0_MX28_PLATE_MASK;
369 }
370 
371 static u32 mxs_lradc_irq_en_mask(struct mxs_lradc *lradc)
372 {
373         if (lradc->soc == IMX23_LRADC)
374                 return LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK;
375         return LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK;
376 }
377 
378 static u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc)
379 {
380         if (lradc->soc == IMX23_LRADC)
381                 return LRADC_CTRL1_MX23_LRADC_IRQ_MASK;
382         return LRADC_CTRL1_MX28_LRADC_IRQ_MASK;
383 }
384 
385 static u32 mxs_lradc_touch_detect_bit(struct mxs_lradc *lradc)
386 {
387         if (lradc->soc == IMX23_LRADC)
388                 return LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE;
389         return LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE;
390 }
391 
392 static u32 mxs_lradc_drive_x_plate(struct mxs_lradc *lradc)
393 {
394         if (lradc->soc == IMX23_LRADC)
395                 return LRADC_CTRL0_MX23_XP | LRADC_CTRL0_MX23_XM;
396         return LRADC_CTRL0_MX28_XPPSW | LRADC_CTRL0_MX28_XNNSW;
397 }
398 
399 static u32 mxs_lradc_drive_y_plate(struct mxs_lradc *lradc)
400 {
401         if (lradc->soc == IMX23_LRADC)
402                 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_YM;
403         return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_YNNSW;
404 }
405 
406 static u32 mxs_lradc_drive_pressure(struct mxs_lradc *lradc)
407 {
408         if (lradc->soc == IMX23_LRADC)
409                 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XM;
410         return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW;
411 }
412 
413 static bool mxs_lradc_check_touch_event(struct mxs_lradc *lradc)
414 {
415         return !!(readl(lradc->base + LRADC_STATUS) &
416                                         LRADC_STATUS_TOUCH_DETECT_RAW);
417 }
418 
419 static void mxs_lradc_setup_ts_channel(struct mxs_lradc *lradc, unsigned ch)
420 {
421         /*
422          * prepare for oversampling conversion
423          *
424          * from the datasheet:
425          * "The ACCUMULATE bit in the appropriate channel register
426          * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
427          * otherwise, the IRQs will not fire."
428          */
429         mxs_lradc_reg_wrt(lradc, LRADC_CH_ACCUMULATE |
430                         LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1),
431                         LRADC_CH(ch));
432 
433         /* from the datasheet:
434          * "Software must clear this register in preparation for a
435          * multi-cycle accumulation.
436          */
437         mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch));
438 
439         /* prepare the delay/loop unit according to the oversampling count */
440         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch) |
441                 LRADC_DELAY_TRIGGER_DELAYS(0) |
442                 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
443                 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
444                         LRADC_DELAY(3));
445 
446         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(2) |
447                         LRADC_CTRL1_LRADC_IRQ(3) | LRADC_CTRL1_LRADC_IRQ(4) |
448                         LRADC_CTRL1_LRADC_IRQ(5), LRADC_CTRL1);
449 
450         /* wake us again, when the complete conversion is done */
451         mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(ch), LRADC_CTRL1);
452         /*
453          * after changing the touchscreen plates setting
454          * the signals need some initial time to settle. Start the
455          * SoC's delay unit and start the conversion later
456          * and automatically.
457          */
458         mxs_lradc_reg_wrt(lradc,
459                 LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
460                 LRADC_DELAY_TRIGGER_DELAYS(1 << 3) | /* trigger DELAY unit#3 */
461                 LRADC_DELAY_KICK |
462                 LRADC_DELAY_DELAY(lradc->settling_delay),
463                         LRADC_DELAY(2));
464 }
465 
466 /*
467  * Pressure detection is special:
468  * We want to do both required measurements for the pressure detection in
469  * one turn. Use the hardware features to chain both conversions and let the
470  * hardware report one interrupt if both conversions are done
471  */
472 static void mxs_lradc_setup_ts_pressure(struct mxs_lradc *lradc, unsigned ch1,
473                                                         unsigned ch2)
474 {
475         u32 reg;
476 
477         /*
478          * prepare for oversampling conversion
479          *
480          * from the datasheet:
481          * "The ACCUMULATE bit in the appropriate channel register
482          * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
483          * otherwise, the IRQs will not fire."
484          */
485         reg = LRADC_CH_ACCUMULATE |
486                 LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1);
487         mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch1));
488         mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch2));
489 
490         /* from the datasheet:
491          * "Software must clear this register in preparation for a
492          * multi-cycle accumulation.
493          */
494         mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch1));
495         mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch2));
496 
497         /* prepare the delay/loop unit according to the oversampling count */
498         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch1) |
499                 LRADC_DELAY_TRIGGER(1 << ch2) | /* start both channels */
500                 LRADC_DELAY_TRIGGER_DELAYS(0) |
501                 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
502                 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
503                                         LRADC_DELAY(3));
504 
505         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(2) |
506                         LRADC_CTRL1_LRADC_IRQ(3) | LRADC_CTRL1_LRADC_IRQ(4) |
507                         LRADC_CTRL1_LRADC_IRQ(5), LRADC_CTRL1);
508 
509         /* wake us again, when the conversions are done */
510         mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(ch2), LRADC_CTRL1);
511         /*
512          * after changing the touchscreen plates setting
513          * the signals need some initial time to settle. Start the
514          * SoC's delay unit and start the conversion later
515          * and automatically.
516          */
517         mxs_lradc_reg_wrt(lradc,
518                 LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
519                 LRADC_DELAY_TRIGGER_DELAYS(1 << 3) | /* trigger DELAY unit#3 */
520                 LRADC_DELAY_KICK |
521                 LRADC_DELAY_DELAY(lradc->settling_delay), LRADC_DELAY(2));
522 }
523 
524 static unsigned mxs_lradc_read_raw_channel(struct mxs_lradc *lradc,
525                                                         unsigned channel)
526 {
527         u32 reg;
528         unsigned num_samples, val;
529 
530         reg = readl(lradc->base + LRADC_CH(channel));
531         if (reg & LRADC_CH_ACCUMULATE)
532                 num_samples = lradc->over_sample_cnt;
533         else
534                 num_samples = 1;
535 
536         val = (reg & LRADC_CH_VALUE_MASK) >> LRADC_CH_VALUE_OFFSET;
537         return val / num_samples;
538 }
539 
540 static unsigned mxs_lradc_read_ts_pressure(struct mxs_lradc *lradc,
541                                                 unsigned ch1, unsigned ch2)
542 {
543         u32 reg, mask;
544         unsigned pressure, m1, m2;
545 
546         mask = LRADC_CTRL1_LRADC_IRQ(ch1) | LRADC_CTRL1_LRADC_IRQ(ch2);
547         reg = readl(lradc->base + LRADC_CTRL1) & mask;
548 
549         while (reg != mask) {
550                 reg = readl(lradc->base + LRADC_CTRL1) & mask;
551                 dev_dbg(lradc->dev, "One channel is still busy: %X\n", reg);
552         }
553 
554         m1 = mxs_lradc_read_raw_channel(lradc, ch1);
555         m2 = mxs_lradc_read_raw_channel(lradc, ch2);
556 
557         if (m2 == 0) {
558                 dev_warn(lradc->dev, "Cannot calculate pressure\n");
559                 return 1 << (LRADC_RESOLUTION - 1);
560         }
561 
562         /* simply scale the value from 0 ... max ADC resolution */
563         pressure = m1;
564         pressure *= (1 << LRADC_RESOLUTION);
565         pressure /= m2;
566 
567         dev_dbg(lradc->dev, "Pressure = %u\n", pressure);
568         return pressure;
569 }
570 
571 #define TS_CH_XP 2
572 #define TS_CH_YP 3
573 #define TS_CH_XM 4
574 #define TS_CH_YM 5
575 
576 static int mxs_lradc_read_ts_channel(struct mxs_lradc *lradc)
577 {
578         u32 reg;
579         int val;
580 
581         reg = readl(lradc->base + LRADC_CTRL1);
582 
583         /* only channels 3 to 5 are of interest here */
584         if (reg & LRADC_CTRL1_LRADC_IRQ(TS_CH_YP)) {
585                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(TS_CH_YP) |
586                         LRADC_CTRL1_LRADC_IRQ(TS_CH_YP), LRADC_CTRL1);
587                 val = mxs_lradc_read_raw_channel(lradc, TS_CH_YP);
588         } else if (reg & LRADC_CTRL1_LRADC_IRQ(TS_CH_XM)) {
589                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(TS_CH_XM) |
590                         LRADC_CTRL1_LRADC_IRQ(TS_CH_XM), LRADC_CTRL1);
591                 val = mxs_lradc_read_raw_channel(lradc, TS_CH_XM);
592         } else if (reg & LRADC_CTRL1_LRADC_IRQ(TS_CH_YM)) {
593                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(TS_CH_YM) |
594                         LRADC_CTRL1_LRADC_IRQ(TS_CH_YM), LRADC_CTRL1);
595                 val = mxs_lradc_read_raw_channel(lradc, TS_CH_YM);
596         } else {
597                 return -EIO;
598         }
599 
600         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
601         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
602 
603         return val;
604 }
605 
606 /*
607  * YP(open)--+-------------+
608  *           |             |--+
609  *           |             |  |
610  *    YM(-)--+-------------+  |
611  *             +--------------+
612  *             |              |
613  *         XP(weak+)        XM(open)
614  *
615  * "weak+" means 200k Ohm VDDIO
616  * (-) means GND
617  */
618 static void mxs_lradc_setup_touch_detection(struct mxs_lradc *lradc)
619 {
620         /*
621          * In order to detect a touch event the 'touch detect enable' bit
622          * enables:
623          *  - a weak pullup to the X+ connector
624          *  - a strong ground at the Y- connector
625          */
626         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
627         mxs_lradc_reg_set(lradc, mxs_lradc_touch_detect_bit(lradc),
628                                 LRADC_CTRL0);
629 }
630 
631 /*
632  * YP(meas)--+-------------+
633  *           |             |--+
634  *           |             |  |
635  * YM(open)--+-------------+  |
636  *             +--------------+
637  *             |              |
638  *           XP(+)          XM(-)
639  *
640  * (+) means here 1.85 V
641  * (-) means here GND
642  */
643 static void mxs_lradc_prepare_x_pos(struct mxs_lradc *lradc)
644 {
645         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
646         mxs_lradc_reg_set(lradc, mxs_lradc_drive_x_plate(lradc), LRADC_CTRL0);
647 
648         lradc->cur_plate = LRADC_SAMPLE_X;
649         mxs_lradc_setup_ts_channel(lradc, TS_CH_YP);
650 }
651 
652 /*
653  *   YP(+)--+-------------+
654  *          |             |--+
655  *          |             |  |
656  *   YM(-)--+-------------+  |
657  *            +--------------+
658  *            |              |
659  *         XP(open)        XM(meas)
660  *
661  * (+) means here 1.85 V
662  * (-) means here GND
663  */
664 static void mxs_lradc_prepare_y_pos(struct mxs_lradc *lradc)
665 {
666         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
667         mxs_lradc_reg_set(lradc, mxs_lradc_drive_y_plate(lradc), LRADC_CTRL0);
668 
669         lradc->cur_plate = LRADC_SAMPLE_Y;
670         mxs_lradc_setup_ts_channel(lradc, TS_CH_XM);
671 }
672 
673 /*
674  *    YP(+)--+-------------+
675  *           |             |--+
676  *           |             |  |
677  * YM(meas)--+-------------+  |
678  *             +--------------+
679  *             |              |
680  *          XP(meas)        XM(-)
681  *
682  * (+) means here 1.85 V
683  * (-) means here GND
684  */
685 static void mxs_lradc_prepare_pressure(struct mxs_lradc *lradc)
686 {
687         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
688         mxs_lradc_reg_set(lradc, mxs_lradc_drive_pressure(lradc), LRADC_CTRL0);
689 
690         lradc->cur_plate = LRADC_SAMPLE_PRESSURE;
691         mxs_lradc_setup_ts_pressure(lradc, TS_CH_XP, TS_CH_YM);
692 }
693 
694 static void mxs_lradc_enable_touch_detection(struct mxs_lradc *lradc)
695 {
696         mxs_lradc_setup_touch_detection(lradc);
697 
698         lradc->cur_plate = LRADC_TOUCH;
699         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ |
700                                 LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
701         mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
702 }
703 
704 static void mxs_lradc_report_ts_event(struct mxs_lradc *lradc)
705 {
706         input_report_abs(lradc->ts_input, ABS_X, lradc->ts_x_pos);
707         input_report_abs(lradc->ts_input, ABS_Y, lradc->ts_y_pos);
708         input_report_abs(lradc->ts_input, ABS_PRESSURE, lradc->ts_pressure);
709         input_report_key(lradc->ts_input, BTN_TOUCH, 1);
710         input_sync(lradc->ts_input);
711 }
712 
713 static void mxs_lradc_complete_touch_event(struct mxs_lradc *lradc)
714 {
715         mxs_lradc_setup_touch_detection(lradc);
716         lradc->cur_plate = LRADC_SAMPLE_VALID;
717         /*
718          * start a dummy conversion to burn time to settle the signals
719          * note: we are not interested in the conversion's value
720          */
721         mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(5));
722         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(5), LRADC_CTRL1);
723         mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(5), LRADC_CTRL1);
724         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << 5) |
725                 LRADC_DELAY_KICK | LRADC_DELAY_DELAY(10), /* waste 5 ms */
726                         LRADC_DELAY(2));
727 }
728 
729 /*
730  * in order to avoid false measurements, report only samples where
731  * the surface is still touched after the position measurement
732  */
733 static void mxs_lradc_finish_touch_event(struct mxs_lradc *lradc, bool valid)
734 {
735         /* if it is still touched, report the sample */
736         if (valid && mxs_lradc_check_touch_event(lradc)) {
737                 lradc->ts_valid = true;
738                 mxs_lradc_report_ts_event(lradc);
739         }
740 
741         /* if it is even still touched, continue with the next measurement */
742         if (mxs_lradc_check_touch_event(lradc)) {
743                 mxs_lradc_prepare_y_pos(lradc);
744                 return;
745         }
746 
747         if (lradc->ts_valid) {
748                 /* signal the release */
749                 lradc->ts_valid = false;
750                 input_report_key(lradc->ts_input, BTN_TOUCH, 0);
751                 input_sync(lradc->ts_input);
752         }
753 
754         /* if it is released, wait for the next touch via IRQ */
755         lradc->cur_plate = LRADC_TOUCH;
756         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ, LRADC_CTRL1);
757         mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
758 }
759 
760 /* touchscreen's state machine */
761 static void mxs_lradc_handle_touch(struct mxs_lradc *lradc)
762 {
763         int val;
764 
765         switch (lradc->cur_plate) {
766         case LRADC_TOUCH:
767                 /*
768                  * start with the Y-pos, because it uses nearly the same plate
769                  * settings like the touch detection
770                  */
771                 if (mxs_lradc_check_touch_event(lradc)) {
772                         mxs_lradc_reg_clear(lradc,
773                                         LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
774                                         LRADC_CTRL1);
775                         mxs_lradc_prepare_y_pos(lradc);
776                 }
777                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ,
778                                         LRADC_CTRL1);
779                 return;
780 
781         case LRADC_SAMPLE_Y:
782                 val = mxs_lradc_read_ts_channel(lradc);
783                 if (val < 0) {
784                         mxs_lradc_enable_touch_detection(lradc); /* re-start */
785                         return;
786                 }
787                 lradc->ts_y_pos = val;
788                 mxs_lradc_prepare_x_pos(lradc);
789                 return;
790 
791         case LRADC_SAMPLE_X:
792                 val = mxs_lradc_read_ts_channel(lradc);
793                 if (val < 0) {
794                         mxs_lradc_enable_touch_detection(lradc); /* re-start */
795                         return;
796                 }
797                 lradc->ts_x_pos = val;
798                 mxs_lradc_prepare_pressure(lradc);
799                 return;
800 
801         case LRADC_SAMPLE_PRESSURE:
802                 lradc->ts_pressure =
803                         mxs_lradc_read_ts_pressure(lradc, TS_CH_XP, TS_CH_YM);
804                 mxs_lradc_complete_touch_event(lradc);
805                 return;
806 
807         case LRADC_SAMPLE_VALID:
808                 val = mxs_lradc_read_ts_channel(lradc); /* ignore the value */
809                 mxs_lradc_finish_touch_event(lradc, 1);
810                 break;
811         }
812 }
813 
814 /*
815  * Raw I/O operations
816  */
817 static int mxs_lradc_read_single(struct iio_dev *iio_dev, int chan, int *val)
818 {
819         struct mxs_lradc *lradc = iio_priv(iio_dev);
820         int ret;
821 
822         /*
823          * See if there is no buffered operation in progess. If there is, simply
824          * bail out. This can be improved to support both buffered and raw IO at
825          * the same time, yet the code becomes horribly complicated. Therefore I
826          * applied KISS principle here.
827          */
828         ret = mutex_trylock(&lradc->lock);
829         if (!ret)
830                 return -EBUSY;
831 
832         reinit_completion(&lradc->completion);
833 
834         /*
835          * No buffered operation in progress, map the channel and trigger it.
836          * Virtual channel 0 is always used here as the others are always not
837          * used if doing raw sampling.
838          */
839         if (lradc->soc == IMX28_LRADC)
840                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
841                         LRADC_CTRL1);
842         mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
843 
844         /* Enable / disable the divider per requirement */
845         if (test_bit(chan, &lradc->is_divided))
846                 mxs_lradc_reg_set(lradc, 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
847                         LRADC_CTRL2);
848         else
849                 mxs_lradc_reg_clear(lradc,
850                         1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, LRADC_CTRL2);
851 
852         /* Clean the slot's previous content, then set new one. */
853         mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0),
854                         LRADC_CTRL4);
855         mxs_lradc_reg_set(lradc, chan, LRADC_CTRL4);
856 
857         mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(0));
858 
859         /* Enable the IRQ and start sampling the channel. */
860         mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
861         mxs_lradc_reg_set(lradc, 1 << 0, LRADC_CTRL0);
862 
863         /* Wait for completion on the channel, 1 second max. */
864         ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
865         if (!ret)
866                 ret = -ETIMEDOUT;
867         if (ret < 0)
868                 goto err;
869 
870         /* Read the data. */
871         *val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
872         ret = IIO_VAL_INT;
873 
874 err:
875         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
876 
877         mutex_unlock(&lradc->lock);
878 
879         return ret;
880 }
881 
882 static int mxs_lradc_read_temp(struct iio_dev *iio_dev, int *val)
883 {
884         int ret, min, max;
885 
886         ret = mxs_lradc_read_single(iio_dev, 8, &min);
887         if (ret != IIO_VAL_INT)
888                 return ret;
889 
890         ret = mxs_lradc_read_single(iio_dev, 9, &max);
891         if (ret != IIO_VAL_INT)
892                 return ret;
893 
894         *val = max - min;
895 
896         return IIO_VAL_INT;
897 }
898 
899 static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
900                         const struct iio_chan_spec *chan,
901                         int *val, int *val2, long m)
902 {
903         struct mxs_lradc *lradc = iio_priv(iio_dev);
904 
905         switch (m) {
906         case IIO_CHAN_INFO_RAW:
907                 if (chan->type == IIO_TEMP)
908                         return mxs_lradc_read_temp(iio_dev, val);
909 
910                 return mxs_lradc_read_single(iio_dev, chan->channel, val);
911 
912         case IIO_CHAN_INFO_SCALE:
913                 if (chan->type == IIO_TEMP) {
914                         /* From the datasheet, we have to multiply by 1.012 and
915                          * divide by 4
916                          */
917                         *val = 0;
918                         *val2 = 253000;
919                         return IIO_VAL_INT_PLUS_MICRO;
920                 }
921 
922                 *val = lradc->vref_mv[chan->channel];
923                 *val2 = chan->scan_type.realbits -
924                         test_bit(chan->channel, &lradc->is_divided);
925                 return IIO_VAL_FRACTIONAL_LOG2;
926 
927         case IIO_CHAN_INFO_OFFSET:
928                 if (chan->type == IIO_TEMP) {
929                         /* The calculated value from the ADC is in Kelvin, we
930                          * want Celsius for hwmon so the offset is
931                          * -272.15 * scale
932                          */
933                         *val = -1075;
934                         *val2 = 691699;
935 
936                         return IIO_VAL_INT_PLUS_MICRO;
937                 }
938 
939                 return -EINVAL;
940 
941         default:
942                 break;
943         }
944 
945         return -EINVAL;
946 }
947 
948 static int mxs_lradc_write_raw(struct iio_dev *iio_dev,
949                                const struct iio_chan_spec *chan,
950                                int val, int val2, long m)
951 {
952         struct mxs_lradc *lradc = iio_priv(iio_dev);
953         struct mxs_lradc_scale *scale_avail =
954                         lradc->scale_avail[chan->channel];
955         int ret;
956 
957         ret = mutex_trylock(&lradc->lock);
958         if (!ret)
959                 return -EBUSY;
960 
961         switch (m) {
962         case IIO_CHAN_INFO_SCALE:
963                 ret = -EINVAL;
964                 if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
965                     val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
966                         /* divider by two disabled */
967                         clear_bit(chan->channel, &lradc->is_divided);
968                         ret = 0;
969                 } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
970                            val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
971                         /* divider by two enabled */
972                         set_bit(chan->channel, &lradc->is_divided);
973                         ret = 0;
974                 }
975 
976                 break;
977         default:
978                 ret = -EINVAL;
979                 break;
980         }
981 
982         mutex_unlock(&lradc->lock);
983 
984         return ret;
985 }
986 
987 static int mxs_lradc_write_raw_get_fmt(struct iio_dev *iio_dev,
988                                        const struct iio_chan_spec *chan,
989                                        long m)
990 {
991         return IIO_VAL_INT_PLUS_NANO;
992 }
993 
994 static ssize_t mxs_lradc_show_scale_available_ch(struct device *dev,
995                 struct device_attribute *attr,
996                 char *buf,
997                 int ch)
998 {
999         struct iio_dev *iio = dev_to_iio_dev(dev);
1000         struct mxs_lradc *lradc = iio_priv(iio);
1001         int i, len = 0;
1002 
1003         for (i = 0; i < ARRAY_SIZE(lradc->scale_avail[ch]); i++)
1004                 len += sprintf(buf + len, "%d.%09u ",
1005                                lradc->scale_avail[ch][i].integer,
1006                                lradc->scale_avail[ch][i].nano);
1007 
1008         len += sprintf(buf + len, "\n");
1009 
1010         return len;
1011 }
1012 
1013 static ssize_t mxs_lradc_show_scale_available(struct device *dev,
1014                 struct device_attribute *attr,
1015                 char *buf)
1016 {
1017         struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
1018 
1019         return mxs_lradc_show_scale_available_ch(dev, attr, buf,
1020                                                  iio_attr->address);
1021 }
1022 
1023 #define SHOW_SCALE_AVAILABLE_ATTR(ch)                                   \
1024 static IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, S_IRUGO,       \
1025                        mxs_lradc_show_scale_available, NULL, ch)
1026 
1027 SHOW_SCALE_AVAILABLE_ATTR(0);
1028 SHOW_SCALE_AVAILABLE_ATTR(1);
1029 SHOW_SCALE_AVAILABLE_ATTR(2);
1030 SHOW_SCALE_AVAILABLE_ATTR(3);
1031 SHOW_SCALE_AVAILABLE_ATTR(4);
1032 SHOW_SCALE_AVAILABLE_ATTR(5);
1033 SHOW_SCALE_AVAILABLE_ATTR(6);
1034 SHOW_SCALE_AVAILABLE_ATTR(7);
1035 SHOW_SCALE_AVAILABLE_ATTR(10);
1036 SHOW_SCALE_AVAILABLE_ATTR(11);
1037 SHOW_SCALE_AVAILABLE_ATTR(12);
1038 SHOW_SCALE_AVAILABLE_ATTR(13);
1039 SHOW_SCALE_AVAILABLE_ATTR(14);
1040 SHOW_SCALE_AVAILABLE_ATTR(15);
1041 
1042 static struct attribute *mxs_lradc_attributes[] = {
1043         &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
1044         &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
1045         &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
1046         &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
1047         &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
1048         &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
1049         &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
1050         &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
1051         &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
1052         &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
1053         &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
1054         &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
1055         &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
1056         &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
1057         NULL
1058 };
1059 
1060 static const struct attribute_group mxs_lradc_attribute_group = {
1061         .attrs = mxs_lradc_attributes,
1062 };
1063 
1064 static const struct iio_info mxs_lradc_iio_info = {
1065         .driver_module          = THIS_MODULE,
1066         .read_raw               = mxs_lradc_read_raw,
1067         .write_raw              = mxs_lradc_write_raw,
1068         .write_raw_get_fmt      = mxs_lradc_write_raw_get_fmt,
1069         .attrs                  = &mxs_lradc_attribute_group,
1070 };
1071 
1072 static int mxs_lradc_ts_open(struct input_dev *dev)
1073 {
1074         struct mxs_lradc *lradc = input_get_drvdata(dev);
1075 
1076         /* Enable the touch-detect circuitry. */
1077         mxs_lradc_enable_touch_detection(lradc);
1078 
1079         return 0;
1080 }
1081 
1082 static void mxs_lradc_disable_ts(struct mxs_lradc *lradc)
1083 {
1084         /* stop all interrupts from firing */
1085         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN |
1086                 LRADC_CTRL1_LRADC_IRQ_EN(2) | LRADC_CTRL1_LRADC_IRQ_EN(3) |
1087                 LRADC_CTRL1_LRADC_IRQ_EN(4) | LRADC_CTRL1_LRADC_IRQ_EN(5),
1088                 LRADC_CTRL1);
1089 
1090         /* Power-down touchscreen touch-detect circuitry. */
1091         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
1092 }
1093 
1094 static void mxs_lradc_ts_close(struct input_dev *dev)
1095 {
1096         struct mxs_lradc *lradc = input_get_drvdata(dev);
1097 
1098         mxs_lradc_disable_ts(lradc);
1099 }
1100 
1101 static int mxs_lradc_ts_register(struct mxs_lradc *lradc)
1102 {
1103         struct input_dev *input;
1104         struct device *dev = lradc->dev;
1105         int ret;
1106 
1107         if (!lradc->use_touchscreen)
1108                 return 0;
1109 
1110         input = input_allocate_device();
1111         if (!input)
1112                 return -ENOMEM;
1113 
1114         input->name = DRIVER_NAME;
1115         input->id.bustype = BUS_HOST;
1116         input->dev.parent = dev;
1117         input->open = mxs_lradc_ts_open;
1118         input->close = mxs_lradc_ts_close;
1119 
1120         __set_bit(EV_ABS, input->evbit);
1121         __set_bit(EV_KEY, input->evbit);
1122         __set_bit(BTN_TOUCH, input->keybit);
1123         input_set_abs_params(input, ABS_X, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1124         input_set_abs_params(input, ABS_Y, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1125         input_set_abs_params(input, ABS_PRESSURE, 0, LRADC_SINGLE_SAMPLE_MASK,
1126                              0, 0);
1127 
1128         lradc->ts_input = input;
1129         input_set_drvdata(input, lradc);
1130         ret = input_register_device(input);
1131         if (ret)
1132                 input_free_device(lradc->ts_input);
1133 
1134         return ret;
1135 }
1136 
1137 static void mxs_lradc_ts_unregister(struct mxs_lradc *lradc)
1138 {
1139         if (!lradc->use_touchscreen)
1140                 return;
1141 
1142         mxs_lradc_disable_ts(lradc);
1143         input_unregister_device(lradc->ts_input);
1144 }
1145 
1146 /*
1147  * IRQ Handling
1148  */
1149 static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
1150 {
1151         struct iio_dev *iio = data;
1152         struct mxs_lradc *lradc = iio_priv(iio);
1153         unsigned long reg = readl(lradc->base + LRADC_CTRL1);
1154         const uint32_t ts_irq_mask =
1155                 LRADC_CTRL1_TOUCH_DETECT_IRQ |
1156                 LRADC_CTRL1_LRADC_IRQ(2) |
1157                 LRADC_CTRL1_LRADC_IRQ(3) |
1158                 LRADC_CTRL1_LRADC_IRQ(4) |
1159                 LRADC_CTRL1_LRADC_IRQ(5);
1160 
1161         if (!(reg & mxs_lradc_irq_mask(lradc)))
1162                 return IRQ_NONE;
1163 
1164         if (lradc->use_touchscreen && (reg & ts_irq_mask))
1165                 mxs_lradc_handle_touch(lradc);
1166 
1167         if (iio_buffer_enabled(iio))
1168                 iio_trigger_poll(iio->trig);
1169         else if (reg & LRADC_CTRL1_LRADC_IRQ(0))
1170                 complete(&lradc->completion);
1171 
1172         mxs_lradc_reg_clear(lradc, reg & mxs_lradc_irq_mask(lradc),
1173                         LRADC_CTRL1);
1174 
1175         return IRQ_HANDLED;
1176 }
1177 
1178 /*
1179  * Trigger handling
1180  */
1181 static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
1182 {
1183         struct iio_poll_func *pf = p;
1184         struct iio_dev *iio = pf->indio_dev;
1185         struct mxs_lradc *lradc = iio_priv(iio);
1186         const uint32_t chan_value = LRADC_CH_ACCUMULATE |
1187                 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1188         unsigned int i, j = 0;
1189 
1190         for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1191                 lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
1192                 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(j));
1193                 lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
1194                 lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
1195                 j++;
1196         }
1197 
1198         iio_push_to_buffers_with_timestamp(iio, lradc->buffer, pf->timestamp);
1199 
1200         iio_trigger_notify_done(iio->trig);
1201 
1202         return IRQ_HANDLED;
1203 }
1204 
1205 static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
1206 {
1207         struct iio_dev *iio = iio_trigger_get_drvdata(trig);
1208         struct mxs_lradc *lradc = iio_priv(iio);
1209         const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
1210 
1211         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_KICK, LRADC_DELAY(0) + st);
1212 
1213         return 0;
1214 }
1215 
1216 static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
1217         .owner = THIS_MODULE,
1218         .set_trigger_state = &mxs_lradc_configure_trigger,
1219 };
1220 
1221 static int mxs_lradc_trigger_init(struct iio_dev *iio)
1222 {
1223         int ret;
1224         struct iio_trigger *trig;
1225         struct mxs_lradc *lradc = iio_priv(iio);
1226 
1227         trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
1228         if (trig == NULL)
1229                 return -ENOMEM;
1230 
1231         trig->dev.parent = lradc->dev;
1232         iio_trigger_set_drvdata(trig, iio);
1233         trig->ops = &mxs_lradc_trigger_ops;
1234 
1235         ret = iio_trigger_register(trig);
1236         if (ret) {
1237                 iio_trigger_free(trig);
1238                 return ret;
1239         }
1240 
1241         lradc->trig = trig;
1242 
1243         return 0;
1244 }
1245 
1246 static void mxs_lradc_trigger_remove(struct iio_dev *iio)
1247 {
1248         struct mxs_lradc *lradc = iio_priv(iio);
1249 
1250         iio_trigger_unregister(lradc->trig);
1251         iio_trigger_free(lradc->trig);
1252 }
1253 
1254 static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
1255 {
1256         struct mxs_lradc *lradc = iio_priv(iio);
1257         int ret = 0, chan, ofs = 0;
1258         unsigned long enable = 0;
1259         uint32_t ctrl4_set = 0;
1260         uint32_t ctrl4_clr = 0;
1261         uint32_t ctrl1_irq = 0;
1262         const uint32_t chan_value = LRADC_CH_ACCUMULATE |
1263                 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1264         const int len = bitmap_weight(iio->active_scan_mask,
1265                         LRADC_MAX_TOTAL_CHANS);
1266 
1267         if (!len)
1268                 return -EINVAL;
1269 
1270         /*
1271          * Lock the driver so raw access can not be done during buffered
1272          * operation. This simplifies the code a lot.
1273          */
1274         ret = mutex_trylock(&lradc->lock);
1275         if (!ret)
1276                 return -EBUSY;
1277 
1278         lradc->buffer = kmalloc_array(len, sizeof(*lradc->buffer), GFP_KERNEL);
1279         if (!lradc->buffer) {
1280                 ret = -ENOMEM;
1281                 goto err_mem;
1282         }
1283 
1284         if (lradc->soc == IMX28_LRADC)
1285                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
1286                                                         LRADC_CTRL1);
1287         mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
1288 
1289         for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1290                 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
1291                 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
1292                 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
1293                 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(ofs));
1294                 bitmap_set(&enable, ofs, 1);
1295                 ofs++;
1296         }
1297 
1298         mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1299                                         LRADC_DELAY_KICK, LRADC_DELAY(0));
1300         mxs_lradc_reg_clear(lradc, ctrl4_clr, LRADC_CTRL4);
1301         mxs_lradc_reg_set(lradc, ctrl4_set, LRADC_CTRL4);
1302         mxs_lradc_reg_set(lradc, ctrl1_irq, LRADC_CTRL1);
1303         mxs_lradc_reg_set(lradc, enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
1304                                         LRADC_DELAY(0));
1305 
1306         return 0;
1307 
1308 err_mem:
1309         mutex_unlock(&lradc->lock);
1310         return ret;
1311 }
1312 
1313 static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
1314 {
1315         struct mxs_lradc *lradc = iio_priv(iio);
1316 
1317         mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1318                                         LRADC_DELAY_KICK, LRADC_DELAY(0));
1319 
1320         mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
1321         if (lradc->soc == IMX28_LRADC)
1322                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
1323                                         LRADC_CTRL1);
1324 
1325         kfree(lradc->buffer);
1326         mutex_unlock(&lradc->lock);
1327 
1328         return 0;
1329 }
1330 
1331 static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
1332                                         const unsigned long *mask)
1333 {
1334         struct mxs_lradc *lradc = iio_priv(iio);
1335         const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
1336         int rsvd_chans = 0;
1337         unsigned long rsvd_mask = 0;
1338 
1339         if (lradc->use_touchbutton)
1340                 rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
1341         if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_4WIRE)
1342                 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
1343         if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1344                 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
1345 
1346         if (lradc->use_touchbutton)
1347                 rsvd_chans++;
1348         if (lradc->use_touchscreen)
1349                 rsvd_chans++;
1350 
1351         /* Test for attempts to map channels with special mode of operation. */
1352         if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
1353                 return false;
1354 
1355         /* Test for attempts to map more channels then available slots. */
1356         if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
1357                 return false;
1358 
1359         return true;
1360 }
1361 
1362 static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
1363         .preenable = &mxs_lradc_buffer_preenable,
1364         .postenable = &iio_triggered_buffer_postenable,
1365         .predisable = &iio_triggered_buffer_predisable,
1366         .postdisable = &mxs_lradc_buffer_postdisable,
1367         .validate_scan_mask = &mxs_lradc_validate_scan_mask,
1368 };
1369 
1370 /*
1371  * Driver initialization
1372  */
1373 
1374 #define MXS_ADC_CHAN(idx, chan_type) {                          \
1375         .type = (chan_type),                                    \
1376         .indexed = 1,                                           \
1377         .scan_index = (idx),                                    \
1378         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
1379                               BIT(IIO_CHAN_INFO_SCALE),         \
1380         .channel = (idx),                                       \
1381         .address = (idx),                                       \
1382         .scan_type = {                                          \
1383                 .sign = 'u',                                    \
1384                 .realbits = LRADC_RESOLUTION,                   \
1385                 .storagebits = 32,                              \
1386         },                                                      \
1387 }
1388 
1389 static const struct iio_chan_spec mxs_lradc_chan_spec[] = {
1390         MXS_ADC_CHAN(0, IIO_VOLTAGE),
1391         MXS_ADC_CHAN(1, IIO_VOLTAGE),
1392         MXS_ADC_CHAN(2, IIO_VOLTAGE),
1393         MXS_ADC_CHAN(3, IIO_VOLTAGE),
1394         MXS_ADC_CHAN(4, IIO_VOLTAGE),
1395         MXS_ADC_CHAN(5, IIO_VOLTAGE),
1396         MXS_ADC_CHAN(6, IIO_VOLTAGE),
1397         MXS_ADC_CHAN(7, IIO_VOLTAGE),   /* VBATT */
1398         /* Combined Temperature sensors */
1399         {
1400                 .type = IIO_TEMP,
1401                 .indexed = 1,
1402                 .scan_index = 8,
1403                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1404                                       BIT(IIO_CHAN_INFO_OFFSET) |
1405                                       BIT(IIO_CHAN_INFO_SCALE),
1406                 .channel = 8,
1407                 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
1408         },
1409         MXS_ADC_CHAN(10, IIO_VOLTAGE),  /* VDDIO */
1410         MXS_ADC_CHAN(11, IIO_VOLTAGE),  /* VTH */
1411         MXS_ADC_CHAN(12, IIO_VOLTAGE),  /* VDDA */
1412         MXS_ADC_CHAN(13, IIO_VOLTAGE),  /* VDDD */
1413         MXS_ADC_CHAN(14, IIO_VOLTAGE),  /* VBG */
1414         MXS_ADC_CHAN(15, IIO_VOLTAGE),  /* VDD5V */
1415 };
1416 
1417 static int mxs_lradc_hw_init(struct mxs_lradc *lradc)
1418 {
1419         /* The ADC always uses DELAY CHANNEL 0. */
1420         const uint32_t adc_cfg =
1421                 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
1422                 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
1423 
1424         int ret = stmp_reset_block(lradc->base);
1425 
1426         if (ret)
1427                 return ret;
1428 
1429         /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
1430         mxs_lradc_reg_wrt(lradc, adc_cfg, LRADC_DELAY(0));
1431 
1432         /* Disable remaining DELAY CHANNELs */
1433         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(1));
1434         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
1435         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
1436 
1437         /* Configure the touchscreen type */
1438         if (lradc->soc == IMX28_LRADC) {
1439                 mxs_lradc_reg_clear(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
1440                                                         LRADC_CTRL0);
1441 
1442         if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1443                 mxs_lradc_reg_set(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
1444                                 LRADC_CTRL0);
1445         }
1446 
1447         /* Start internal temperature sensing. */
1448         mxs_lradc_reg_wrt(lradc, 0, LRADC_CTRL2);
1449 
1450         return 0;
1451 }
1452 
1453 static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
1454 {
1455         int i;
1456 
1457         mxs_lradc_reg_clear(lradc, mxs_lradc_irq_en_mask(lradc), LRADC_CTRL1);
1458 
1459         for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
1460                 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(i));
1461 }
1462 
1463 static const struct of_device_id mxs_lradc_dt_ids[] = {
1464         { .compatible = "fsl,imx23-lradc", .data = (void *)IMX23_LRADC, },
1465         { .compatible = "fsl,imx28-lradc", .data = (void *)IMX28_LRADC, },
1466         { /* sentinel */ }
1467 };
1468 MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
1469 
1470 static int mxs_lradc_probe_touchscreen(struct mxs_lradc *lradc,
1471                                                 struct device_node *lradc_node)
1472 {
1473         int ret;
1474         u32 ts_wires = 0, adapt;
1475 
1476         ret = of_property_read_u32(lradc_node, "fsl,lradc-touchscreen-wires",
1477                                 &ts_wires);
1478         if (ret)
1479                 return -ENODEV; /* touchscreen feature disabled */
1480 
1481         switch (ts_wires) {
1482         case 4:
1483                 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_4WIRE;
1484                 break;
1485         case 5:
1486                 if (lradc->soc == IMX28_LRADC) {
1487                         lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_5WIRE;
1488                         break;
1489                 }
1490                 /* fall through an error message for i.MX23 */
1491         default:
1492                 dev_err(lradc->dev,
1493                         "Unsupported number of touchscreen wires (%d)\n",
1494                         ts_wires);
1495                 return -EINVAL;
1496         }
1497 
1498         lradc->over_sample_cnt = 4;
1499         ret = of_property_read_u32(lradc_node, "fsl,ave-ctrl", &adapt);
1500         if (ret == 0)
1501                 lradc->over_sample_cnt = adapt;
1502 
1503         lradc->over_sample_delay = 2;
1504         ret = of_property_read_u32(lradc_node, "fsl,ave-delay", &adapt);
1505         if (ret == 0)
1506                 lradc->over_sample_delay = adapt;
1507 
1508         lradc->settling_delay = 10;
1509         ret = of_property_read_u32(lradc_node, "fsl,settling", &adapt);
1510         if (ret == 0)
1511                 lradc->settling_delay = adapt;
1512 
1513         return 0;
1514 }
1515 
1516 static int mxs_lradc_probe(struct platform_device *pdev)
1517 {
1518         const struct of_device_id *of_id =
1519                 of_match_device(mxs_lradc_dt_ids, &pdev->dev);
1520         const struct mxs_lradc_of_config *of_cfg =
1521                 &mxs_lradc_of_config[(enum mxs_lradc_id)of_id->data];
1522         struct device *dev = &pdev->dev;
1523         struct device_node *node = dev->of_node;
1524         struct mxs_lradc *lradc;
1525         struct iio_dev *iio;
1526         struct resource *iores;
1527         int ret = 0, touch_ret;
1528         int i, s;
1529         uint64_t scale_uv;
1530 
1531         /* Allocate the IIO device. */
1532         iio = devm_iio_device_alloc(dev, sizeof(*lradc));
1533         if (!iio) {
1534                 dev_err(dev, "Failed to allocate IIO device\n");
1535                 return -ENOMEM;
1536         }
1537 
1538         lradc = iio_priv(iio);
1539         lradc->soc = (enum mxs_lradc_id)of_id->data;
1540 
1541         /* Grab the memory area */
1542         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1543         lradc->dev = &pdev->dev;
1544         lradc->base = devm_ioremap_resource(dev, iores);
1545         if (IS_ERR(lradc->base))
1546                 return PTR_ERR(lradc->base);
1547 
1548         lradc->clk = devm_clk_get(&pdev->dev, NULL);
1549         if (IS_ERR(lradc->clk)) {
1550                 dev_err(dev, "Failed to get the delay unit clock\n");
1551                 return PTR_ERR(lradc->clk);
1552         }
1553         ret = clk_prepare_enable(lradc->clk);
1554         if (ret != 0) {
1555                 dev_err(dev, "Failed to enable the delay unit clock\n");
1556                 return ret;
1557         }
1558 
1559         touch_ret = mxs_lradc_probe_touchscreen(lradc, node);
1560 
1561         /* Grab all IRQ sources */
1562         for (i = 0; i < of_cfg->irq_count; i++) {
1563                 lradc->irq[i] = platform_get_irq(pdev, i);
1564                 if (lradc->irq[i] < 0) {
1565                         ret = lradc->irq[i];
1566                         goto err_clk;
1567                 }
1568 
1569                 ret = devm_request_irq(dev, lradc->irq[i],
1570                                         mxs_lradc_handle_irq, 0,
1571                                         of_cfg->irq_name[i], iio);
1572                 if (ret)
1573                         goto err_clk;
1574         }
1575 
1576         lradc->vref_mv = of_cfg->vref_mv;
1577 
1578         platform_set_drvdata(pdev, iio);
1579 
1580         init_completion(&lradc->completion);
1581         mutex_init(&lradc->lock);
1582 
1583         iio->name = pdev->name;
1584         iio->dev.parent = &pdev->dev;
1585         iio->info = &mxs_lradc_iio_info;
1586         iio->modes = INDIO_DIRECT_MODE;
1587         iio->channels = mxs_lradc_chan_spec;
1588         iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec);
1589         iio->masklength = LRADC_MAX_TOTAL_CHANS;
1590 
1591         ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
1592                                 &mxs_lradc_trigger_handler,
1593                                 &mxs_lradc_buffer_ops);
1594         if (ret)
1595                 goto err_clk;
1596 
1597         ret = mxs_lradc_trigger_init(iio);
1598         if (ret)
1599                 goto err_trig;
1600 
1601         /* Populate available ADC input ranges */
1602         for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
1603                 for (s = 0; s < ARRAY_SIZE(lradc->scale_avail[i]); s++) {
1604                         /*
1605                          * [s=0] = optional divider by two disabled (default)
1606                          * [s=1] = optional divider by two enabled
1607                          *
1608                          * The scale is calculated by doing:
1609                          *   Vref >> (realbits - s)
1610                          * which multiplies by two on the second component
1611                          * of the array.
1612                          */
1613                         scale_uv = ((u64)lradc->vref_mv[i] * 100000000) >>
1614                                    (LRADC_RESOLUTION - s);
1615                         lradc->scale_avail[i][s].nano =
1616                                         do_div(scale_uv, 100000000) * 10;
1617                         lradc->scale_avail[i][s].integer = scale_uv;
1618                 }
1619         }
1620 
1621         /* Configure the hardware. */
1622         ret = mxs_lradc_hw_init(lradc);
1623         if (ret)
1624                 goto err_dev;
1625 
1626         /* Register the touchscreen input device. */
1627         if (touch_ret == 0) {
1628                 ret = mxs_lradc_ts_register(lradc);
1629                 if (ret)
1630                         goto err_ts_register;
1631         }
1632 
1633         /* Register IIO device. */
1634         ret = iio_device_register(iio);
1635         if (ret) {
1636                 dev_err(dev, "Failed to register IIO device\n");
1637                 goto err_ts;
1638         }
1639 
1640         return 0;
1641 
1642 err_ts:
1643         mxs_lradc_ts_unregister(lradc);
1644 err_ts_register:
1645         mxs_lradc_hw_stop(lradc);
1646 err_dev:
1647         mxs_lradc_trigger_remove(iio);
1648 err_trig:
1649         iio_triggered_buffer_cleanup(iio);
1650 err_clk:
1651         clk_disable_unprepare(lradc->clk);
1652         return ret;
1653 }
1654 
1655 static int mxs_lradc_remove(struct platform_device *pdev)
1656 {
1657         struct iio_dev *iio = platform_get_drvdata(pdev);
1658         struct mxs_lradc *lradc = iio_priv(iio);
1659 
1660         iio_device_unregister(iio);
1661         mxs_lradc_ts_unregister(lradc);
1662         mxs_lradc_hw_stop(lradc);
1663         mxs_lradc_trigger_remove(iio);
1664         iio_triggered_buffer_cleanup(iio);
1665 
1666         clk_disable_unprepare(lradc->clk);
1667         return 0;
1668 }
1669 
1670 static struct platform_driver mxs_lradc_driver = {
1671         .driver = {
1672                 .name   = DRIVER_NAME,
1673                 .of_match_table = mxs_lradc_dt_ids,
1674         },
1675         .probe  = mxs_lradc_probe,
1676         .remove = mxs_lradc_remove,
1677 };
1678 
1679 module_platform_driver(mxs_lradc_driver);
1680 
1681 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1682 MODULE_DESCRIPTION("Freescale i.MX28 LRADC driver");
1683 MODULE_LICENSE("GPL v2");
1684 MODULE_ALIAS("platform:" DRIVER_NAME);
1685 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us