Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/staging/iio/adc/mxs-lradc.c

  1 /*
  2  * Freescale i.MX28 LRADC driver
  3  *
  4  * Copyright (c) 2012 DENX Software Engineering, GmbH.
  5  * Marek Vasut <marex@denx.de>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  *
 12  * This program is distributed in the hope that it will be useful,
 13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 15  * GNU General Public License for more details.
 16  */
 17 
 18 #include <linux/err.h>
 19 #include <linux/interrupt.h>
 20 #include <linux/device.h>
 21 #include <linux/kernel.h>
 22 #include <linux/slab.h>
 23 #include <linux/of.h>
 24 #include <linux/of_device.h>
 25 #include <linux/sysfs.h>
 26 #include <linux/list.h>
 27 #include <linux/io.h>
 28 #include <linux/module.h>
 29 #include <linux/platform_device.h>
 30 #include <linux/spinlock.h>
 31 #include <linux/wait.h>
 32 #include <linux/sched.h>
 33 #include <linux/stmp_device.h>
 34 #include <linux/bitops.h>
 35 #include <linux/completion.h>
 36 #include <linux/delay.h>
 37 #include <linux/input.h>
 38 #include <linux/clk.h>
 39 
 40 #include <linux/iio/iio.h>
 41 #include <linux/iio/sysfs.h>
 42 #include <linux/iio/buffer.h>
 43 #include <linux/iio/trigger.h>
 44 #include <linux/iio/trigger_consumer.h>
 45 #include <linux/iio/triggered_buffer.h>
 46 
 47 #define DRIVER_NAME             "mxs-lradc"
 48 
 49 #define LRADC_MAX_DELAY_CHANS   4
 50 #define LRADC_MAX_MAPPED_CHANS  8
 51 #define LRADC_MAX_TOTAL_CHANS   16
 52 
 53 #define LRADC_DELAY_TIMER_HZ    2000
 54 
 55 /*
 56  * Make this runtime configurable if necessary. Currently, if the buffered mode
 57  * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
 58  * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
 59  * seconds. The result is that the samples arrive every 500mS.
 60  */
 61 #define LRADC_DELAY_TIMER_PER   200
 62 #define LRADC_DELAY_TIMER_LOOP  5
 63 
 64 /*
 65  * Once the pen touches the touchscreen, the touchscreen switches from
 66  * IRQ-driven mode to polling mode to prevent interrupt storm. The polling
 67  * is realized by worker thread, which is called every 20 or so milliseconds.
 68  * This gives the touchscreen enough fluence and does not strain the system
 69  * too much.
 70  */
 71 #define LRADC_TS_SAMPLE_DELAY_MS        5
 72 
 73 /*
 74  * The LRADC reads the following amount of samples from each touchscreen
 75  * channel and the driver then computes avarage of these.
 76  */
 77 #define LRADC_TS_SAMPLE_AMOUNT          4
 78 
 79 enum mxs_lradc_id {
 80         IMX23_LRADC,
 81         IMX28_LRADC,
 82 };
 83 
 84 static const char * const mx23_lradc_irq_names[] = {
 85         "mxs-lradc-touchscreen",
 86         "mxs-lradc-channel0",
 87         "mxs-lradc-channel1",
 88         "mxs-lradc-channel2",
 89         "mxs-lradc-channel3",
 90         "mxs-lradc-channel4",
 91         "mxs-lradc-channel5",
 92         "mxs-lradc-channel6",
 93         "mxs-lradc-channel7",
 94 };
 95 
 96 static const char * const mx28_lradc_irq_names[] = {
 97         "mxs-lradc-touchscreen",
 98         "mxs-lradc-thresh0",
 99         "mxs-lradc-thresh1",
100         "mxs-lradc-channel0",
101         "mxs-lradc-channel1",
102         "mxs-lradc-channel2",
103         "mxs-lradc-channel3",
104         "mxs-lradc-channel4",
105         "mxs-lradc-channel5",
106         "mxs-lradc-channel6",
107         "mxs-lradc-channel7",
108         "mxs-lradc-button0",
109         "mxs-lradc-button1",
110 };
111 
112 struct mxs_lradc_of_config {
113         const int               irq_count;
114         const char * const      *irq_name;
115         const uint32_t          *vref_mv;
116 };
117 
118 #define VREF_MV_BASE 1850
119 
120 static const uint32_t mx23_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
121         VREF_MV_BASE,           /* CH0 */
122         VREF_MV_BASE,           /* CH1 */
123         VREF_MV_BASE,           /* CH2 */
124         VREF_MV_BASE,           /* CH3 */
125         VREF_MV_BASE,           /* CH4 */
126         VREF_MV_BASE,           /* CH5 */
127         VREF_MV_BASE * 2,       /* CH6 VDDIO */
128         VREF_MV_BASE * 4,       /* CH7 VBATT */
129         VREF_MV_BASE,           /* CH8 Temp sense 0 */
130         VREF_MV_BASE,           /* CH9 Temp sense 1 */
131         VREF_MV_BASE,           /* CH10 */
132         VREF_MV_BASE,           /* CH11 */
133         VREF_MV_BASE,           /* CH12 USB_DP */
134         VREF_MV_BASE,           /* CH13 USB_DN */
135         VREF_MV_BASE,           /* CH14 VBG */
136         VREF_MV_BASE * 4,       /* CH15 VDD5V */
137 };
138 
139 static const uint32_t mx28_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
140         VREF_MV_BASE,           /* CH0 */
141         VREF_MV_BASE,           /* CH1 */
142         VREF_MV_BASE,           /* CH2 */
143         VREF_MV_BASE,           /* CH3 */
144         VREF_MV_BASE,           /* CH4 */
145         VREF_MV_BASE,           /* CH5 */
146         VREF_MV_BASE,           /* CH6 */
147         VREF_MV_BASE * 4,       /* CH7 VBATT */
148         VREF_MV_BASE,           /* CH8 Temp sense 0 */
149         VREF_MV_BASE,           /* CH9 Temp sense 1 */
150         VREF_MV_BASE * 2,       /* CH10 VDDIO */
151         VREF_MV_BASE,           /* CH11 VTH */
152         VREF_MV_BASE * 2,       /* CH12 VDDA */
153         VREF_MV_BASE,           /* CH13 VDDD */
154         VREF_MV_BASE,           /* CH14 VBG */
155         VREF_MV_BASE * 4,       /* CH15 VDD5V */
156 };
157 
158 static const struct mxs_lradc_of_config mxs_lradc_of_config[] = {
159         [IMX23_LRADC] = {
160                 .irq_count      = ARRAY_SIZE(mx23_lradc_irq_names),
161                 .irq_name       = mx23_lradc_irq_names,
162                 .vref_mv        = mx23_vref_mv,
163         },
164         [IMX28_LRADC] = {
165                 .irq_count      = ARRAY_SIZE(mx28_lradc_irq_names),
166                 .irq_name       = mx28_lradc_irq_names,
167                 .vref_mv        = mx28_vref_mv,
168         },
169 };
170 
171 enum mxs_lradc_ts {
172         MXS_LRADC_TOUCHSCREEN_NONE = 0,
173         MXS_LRADC_TOUCHSCREEN_4WIRE,
174         MXS_LRADC_TOUCHSCREEN_5WIRE,
175 };
176 
177 /*
178  * Touchscreen handling
179  */
180 enum lradc_ts_plate {
181         LRADC_TOUCH = 0,
182         LRADC_SAMPLE_X,
183         LRADC_SAMPLE_Y,
184         LRADC_SAMPLE_PRESSURE,
185         LRADC_SAMPLE_VALID,
186 };
187 
188 enum mxs_lradc_divbytwo {
189         MXS_LRADC_DIV_DISABLED = 0,
190         MXS_LRADC_DIV_ENABLED,
191 };
192 
193 struct mxs_lradc_scale {
194         unsigned int            integer;
195         unsigned int            nano;
196 };
197 
198 struct mxs_lradc {
199         struct device           *dev;
200         void __iomem            *base;
201         int                     irq[13];
202 
203         struct clk              *clk;
204 
205         uint32_t                *buffer;
206         struct iio_trigger      *trig;
207 
208         struct mutex            lock;
209 
210         struct completion       completion;
211 
212         const uint32_t          *vref_mv;
213         struct mxs_lradc_scale  scale_avail[LRADC_MAX_TOTAL_CHANS][2];
214         unsigned long           is_divided;
215 
216         /*
217          * Touchscreen LRADC channels receives a private slot in the CTRL4
218          * register, the slot #7. Therefore only 7 slots instead of 8 in the
219          * CTRL4 register can be mapped to LRADC channels when using the
220          * touchscreen.
221          *
222          * Furthermore, certain LRADC channels are shared between touchscreen
223          * and/or touch-buttons and generic LRADC block. Therefore when using
224          * either of these, these channels are not available for the regular
225          * sampling. The shared channels are as follows:
226          *
227          * CH0 -- Touch button #0
228          * CH1 -- Touch button #1
229          * CH2 -- Touch screen XPUL
230          * CH3 -- Touch screen YPLL
231          * CH4 -- Touch screen XNUL
232          * CH5 -- Touch screen YNLR
233          * CH6 -- Touch screen WIPER (5-wire only)
234          *
235          * The bitfields below represents which parts of the LRADC block are
236          * switched into special mode of operation. These channels can not
237          * be sampled as regular LRADC channels. The driver will refuse any
238          * attempt to sample these channels.
239          */
240 #define CHAN_MASK_TOUCHBUTTON           (0x3 << 0)
241 #define CHAN_MASK_TOUCHSCREEN_4WIRE     (0xf << 2)
242 #define CHAN_MASK_TOUCHSCREEN_5WIRE     (0x1f << 2)
243         enum mxs_lradc_ts       use_touchscreen;
244         bool                    use_touchbutton;
245 
246         struct input_dev        *ts_input;
247 
248         enum mxs_lradc_id       soc;
249         enum lradc_ts_plate     cur_plate; /* statemachine */
250         bool                    ts_valid;
251         unsigned                ts_x_pos;
252         unsigned                ts_y_pos;
253         unsigned                ts_pressure;
254 
255         /* handle touchscreen's physical behaviour */
256         /* samples per coordinate */
257         unsigned                over_sample_cnt;
258         /* time clocks between samples */
259         unsigned                over_sample_delay;
260         /* time in clocks to wait after the plates where switched */
261         unsigned                settling_delay;
262 };
263 
264 #define LRADC_CTRL0                             0x00
265 # define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE   (1 << 23)
266 # define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE     (1 << 22)
267 # define LRADC_CTRL0_MX28_YNNSW /* YM */        (1 << 21)
268 # define LRADC_CTRL0_MX28_YPNSW /* YP */        (1 << 20)
269 # define LRADC_CTRL0_MX28_YPPSW /* YP */        (1 << 19)
270 # define LRADC_CTRL0_MX28_XNNSW /* XM */        (1 << 18)
271 # define LRADC_CTRL0_MX28_XNPSW /* XM */        (1 << 17)
272 # define LRADC_CTRL0_MX28_XPPSW /* XP */        (1 << 16)
273 
274 # define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE   (1 << 20)
275 # define LRADC_CTRL0_MX23_YM                    (1 << 19)
276 # define LRADC_CTRL0_MX23_XM                    (1 << 18)
277 # define LRADC_CTRL0_MX23_YP                    (1 << 17)
278 # define LRADC_CTRL0_MX23_XP                    (1 << 16)
279 
280 # define LRADC_CTRL0_MX28_PLATE_MASK \
281                 (LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \
282                 LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \
283                 LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \
284                 LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW)
285 
286 # define LRADC_CTRL0_MX23_PLATE_MASK \
287                 (LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE | \
288                 LRADC_CTRL0_MX23_YM | LRADC_CTRL0_MX23_XM | \
289                 LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XP)
290 
291 #define LRADC_CTRL1                             0x10
292 #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN         (1 << 24)
293 #define LRADC_CTRL1_LRADC_IRQ_EN(n)             (1 << ((n) + 16))
294 #define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK      (0x1fff << 16)
295 #define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK      (0x01ff << 16)
296 #define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET         16
297 #define LRADC_CTRL1_TOUCH_DETECT_IRQ            (1 << 8)
298 #define LRADC_CTRL1_LRADC_IRQ(n)                (1 << (n))
299 #define LRADC_CTRL1_MX28_LRADC_IRQ_MASK         0x1fff
300 #define LRADC_CTRL1_MX23_LRADC_IRQ_MASK         0x01ff
301 #define LRADC_CTRL1_LRADC_IRQ_OFFSET            0
302 
303 #define LRADC_CTRL2                             0x20
304 #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET        24
305 #define LRADC_CTRL2_TEMPSENSE_PWD               (1 << 15)
306 
307 #define LRADC_STATUS                            0x40
308 #define LRADC_STATUS_TOUCH_DETECT_RAW           (1 << 0)
309 
310 #define LRADC_CH(n)                             (0x50 + (0x10 * (n)))
311 #define LRADC_CH_ACCUMULATE                     (1 << 29)
312 #define LRADC_CH_NUM_SAMPLES_MASK               (0x1f << 24)
313 #define LRADC_CH_NUM_SAMPLES_OFFSET             24
314 #define LRADC_CH_NUM_SAMPLES(x) \
315                                 ((x) << LRADC_CH_NUM_SAMPLES_OFFSET)
316 #define LRADC_CH_VALUE_MASK                     0x3ffff
317 #define LRADC_CH_VALUE_OFFSET                   0
318 
319 #define LRADC_DELAY(n)                          (0xd0 + (0x10 * (n)))
320 #define LRADC_DELAY_TRIGGER_LRADCS_MASK         (0xff << 24)
321 #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET       24
322 #define LRADC_DELAY_TRIGGER(x) \
323                                 (((x) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) & \
324                                 LRADC_DELAY_TRIGGER_LRADCS_MASK)
325 #define LRADC_DELAY_KICK                        (1 << 20)
326 #define LRADC_DELAY_TRIGGER_DELAYS_MASK         (0xf << 16)
327 #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET       16
328 #define LRADC_DELAY_TRIGGER_DELAYS(x) \
329                                 (((x) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) & \
330                                 LRADC_DELAY_TRIGGER_DELAYS_MASK)
331 #define LRADC_DELAY_LOOP_COUNT_MASK             (0x1f << 11)
332 #define LRADC_DELAY_LOOP_COUNT_OFFSET           11
333 #define LRADC_DELAY_LOOP(x) \
334                                 (((x) << LRADC_DELAY_LOOP_COUNT_OFFSET) & \
335                                 LRADC_DELAY_LOOP_COUNT_MASK)
336 #define LRADC_DELAY_DELAY_MASK                  0x7ff
337 #define LRADC_DELAY_DELAY_OFFSET                0
338 #define LRADC_DELAY_DELAY(x) \
339                                 (((x) << LRADC_DELAY_DELAY_OFFSET) & \
340                                 LRADC_DELAY_DELAY_MASK)
341 
342 #define LRADC_CTRL4                             0x140
343 #define LRADC_CTRL4_LRADCSELECT_MASK(n)         (0xf << ((n) * 4))
344 #define LRADC_CTRL4_LRADCSELECT_OFFSET(n)       ((n) * 4)
345 
346 #define LRADC_RESOLUTION                        12
347 #define LRADC_SINGLE_SAMPLE_MASK                ((1 << LRADC_RESOLUTION) - 1)
348 
349 static void mxs_lradc_reg_set(struct mxs_lradc *lradc, u32 val, u32 reg)
350 {
351         writel(val, lradc->base + reg + STMP_OFFSET_REG_SET);
352 }
353 
354 static void mxs_lradc_reg_clear(struct mxs_lradc *lradc, u32 val, u32 reg)
355 {
356         writel(val, lradc->base + reg + STMP_OFFSET_REG_CLR);
357 }
358 
359 static void mxs_lradc_reg_wrt(struct mxs_lradc *lradc, u32 val, u32 reg)
360 {
361         writel(val, lradc->base + reg);
362 }
363 
364 static u32 mxs_lradc_plate_mask(struct mxs_lradc *lradc)
365 {
366         if (lradc->soc == IMX23_LRADC)
367                 return LRADC_CTRL0_MX23_PLATE_MASK;
368         else
369                 return LRADC_CTRL0_MX28_PLATE_MASK;
370 }
371 
372 static u32 mxs_lradc_irq_en_mask(struct mxs_lradc *lradc)
373 {
374         if (lradc->soc == IMX23_LRADC)
375                 return LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK;
376         else
377                 return LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK;
378 }
379 
380 static u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc)
381 {
382         if (lradc->soc == IMX23_LRADC)
383                 return LRADC_CTRL1_MX23_LRADC_IRQ_MASK;
384         else
385                 return LRADC_CTRL1_MX28_LRADC_IRQ_MASK;
386 }
387 
388 static u32 mxs_lradc_touch_detect_bit(struct mxs_lradc *lradc)
389 {
390         if (lradc->soc == IMX23_LRADC)
391                 return LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE;
392         else
393                 return LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE;
394 }
395 
396 static u32 mxs_lradc_drive_x_plate(struct mxs_lradc *lradc)
397 {
398         if (lradc->soc == IMX23_LRADC)
399                 return LRADC_CTRL0_MX23_XP | LRADC_CTRL0_MX23_XM;
400         else
401                 return LRADC_CTRL0_MX28_XPPSW | LRADC_CTRL0_MX28_XNNSW;
402 }
403 
404 static u32 mxs_lradc_drive_y_plate(struct mxs_lradc *lradc)
405 {
406         if (lradc->soc == IMX23_LRADC)
407                 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_YM;
408         else
409                 return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_YNNSW;
410 }
411 
412 static u32 mxs_lradc_drive_pressure(struct mxs_lradc *lradc)
413 {
414         if (lradc->soc == IMX23_LRADC)
415                 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XM;
416         else
417                 return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW;
418 }
419 
420 static bool mxs_lradc_check_touch_event(struct mxs_lradc *lradc)
421 {
422         return !!(readl(lradc->base + LRADC_STATUS) &
423                                         LRADC_STATUS_TOUCH_DETECT_RAW);
424 }
425 
426 static void mxs_lradc_setup_ts_channel(struct mxs_lradc *lradc, unsigned ch)
427 {
428         /*
429          * prepare for oversampling conversion
430          *
431          * from the datasheet:
432          * "The ACCUMULATE bit in the appropriate channel register
433          * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
434          * otherwise, the IRQs will not fire."
435          */
436         mxs_lradc_reg_wrt(lradc, LRADC_CH_ACCUMULATE |
437                         LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1),
438                         LRADC_CH(ch));
439 
440         /* from the datasheet:
441          * "Software must clear this register in preparation for a
442          * multi-cycle accumulation.
443          */
444         mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch));
445 
446         /* prepare the delay/loop unit according to the oversampling count */
447         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch) |
448                 LRADC_DELAY_TRIGGER_DELAYS(0) |
449                 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
450                 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
451                         LRADC_DELAY(3));
452 
453         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(2) |
454                         LRADC_CTRL1_LRADC_IRQ(3) | LRADC_CTRL1_LRADC_IRQ(4) |
455                         LRADC_CTRL1_LRADC_IRQ(5), LRADC_CTRL1);
456 
457         /* wake us again, when the complete conversion is done */
458         mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(ch), LRADC_CTRL1);
459         /*
460          * after changing the touchscreen plates setting
461          * the signals need some initial time to settle. Start the
462          * SoC's delay unit and start the conversion later
463          * and automatically.
464          */
465         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
466                 LRADC_DELAY_TRIGGER_DELAYS(1 << 3) | /* trigger DELAY unit#3 */
467                 LRADC_DELAY_KICK |
468                 LRADC_DELAY_DELAY(lradc->settling_delay),
469                         LRADC_DELAY(2));
470 }
471 
472 /*
473  * Pressure detection is special:
474  * We want to do both required measurements for the pressure detection in
475  * one turn. Use the hardware features to chain both conversions and let the
476  * hardware report one interrupt if both conversions are done
477  */
478 static void mxs_lradc_setup_ts_pressure(struct mxs_lradc *lradc, unsigned ch1,
479                                                         unsigned ch2)
480 {
481         u32 reg;
482 
483         /*
484          * prepare for oversampling conversion
485          *
486          * from the datasheet:
487          * "The ACCUMULATE bit in the appropriate channel register
488          * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
489          * otherwise, the IRQs will not fire."
490          */
491         reg = LRADC_CH_ACCUMULATE |
492                 LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1);
493         mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch1));
494         mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch2));
495 
496         /* from the datasheet:
497          * "Software must clear this register in preparation for a
498          * multi-cycle accumulation.
499          */
500         mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch1));
501         mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch2));
502 
503         /* prepare the delay/loop unit according to the oversampling count */
504         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch1) |
505                 LRADC_DELAY_TRIGGER(1 << ch2) | /* start both channels */
506                 LRADC_DELAY_TRIGGER_DELAYS(0) |
507                 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
508                 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
509                                         LRADC_DELAY(3));
510 
511         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(2) |
512                         LRADC_CTRL1_LRADC_IRQ(3) | LRADC_CTRL1_LRADC_IRQ(4) |
513                         LRADC_CTRL1_LRADC_IRQ(5), LRADC_CTRL1);
514 
515         /* wake us again, when the conversions are done */
516         mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(ch2), LRADC_CTRL1);
517         /*
518          * after changing the touchscreen plates setting
519          * the signals need some initial time to settle. Start the
520          * SoC's delay unit and start the conversion later
521          * and automatically.
522          */
523         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
524                 LRADC_DELAY_TRIGGER_DELAYS(1 << 3) | /* trigger DELAY unit#3 */
525                 LRADC_DELAY_KICK |
526                 LRADC_DELAY_DELAY(lradc->settling_delay), LRADC_DELAY(2));
527 }
528 
529 static unsigned mxs_lradc_read_raw_channel(struct mxs_lradc *lradc,
530                                                         unsigned channel)
531 {
532         u32 reg;
533         unsigned num_samples, val;
534 
535         reg = readl(lradc->base + LRADC_CH(channel));
536         if (reg & LRADC_CH_ACCUMULATE)
537                 num_samples = lradc->over_sample_cnt;
538         else
539                 num_samples = 1;
540 
541         val = (reg & LRADC_CH_VALUE_MASK) >> LRADC_CH_VALUE_OFFSET;
542         return val / num_samples;
543 }
544 
545 static unsigned mxs_lradc_read_ts_pressure(struct mxs_lradc *lradc,
546                                                 unsigned ch1, unsigned ch2)
547 {
548         u32 reg, mask;
549         unsigned pressure, m1, m2;
550 
551         mask = LRADC_CTRL1_LRADC_IRQ(ch1) | LRADC_CTRL1_LRADC_IRQ(ch2);
552         reg = readl(lradc->base + LRADC_CTRL1) & mask;
553 
554         while (reg != mask) {
555                 reg = readl(lradc->base + LRADC_CTRL1) & mask;
556                 dev_dbg(lradc->dev, "One channel is still busy: %X\n", reg);
557         }
558 
559         m1 = mxs_lradc_read_raw_channel(lradc, ch1);
560         m2 = mxs_lradc_read_raw_channel(lradc, ch2);
561 
562         if (m2 == 0) {
563                 dev_warn(lradc->dev, "Cannot calculate pressure\n");
564                 return 1 << (LRADC_RESOLUTION - 1);
565         }
566 
567         /* simply scale the value from 0 ... max ADC resolution */
568         pressure = m1;
569         pressure *= (1 << LRADC_RESOLUTION);
570         pressure /= m2;
571 
572         dev_dbg(lradc->dev, "Pressure = %u\n", pressure);
573         return pressure;
574 }
575 
576 #define TS_CH_XP 2
577 #define TS_CH_YP 3
578 #define TS_CH_XM 4
579 #define TS_CH_YM 5
580 
581 static int mxs_lradc_read_ts_channel(struct mxs_lradc *lradc)
582 {
583         u32 reg;
584         int val;
585 
586         reg = readl(lradc->base + LRADC_CTRL1);
587 
588         /* only channels 3 to 5 are of interest here */
589         if (reg & LRADC_CTRL1_LRADC_IRQ(TS_CH_YP)) {
590                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(TS_CH_YP) |
591                         LRADC_CTRL1_LRADC_IRQ(TS_CH_YP), LRADC_CTRL1);
592                 val = mxs_lradc_read_raw_channel(lradc, TS_CH_YP);
593         } else if (reg & LRADC_CTRL1_LRADC_IRQ(TS_CH_XM)) {
594                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(TS_CH_XM) |
595                         LRADC_CTRL1_LRADC_IRQ(TS_CH_XM), LRADC_CTRL1);
596                 val = mxs_lradc_read_raw_channel(lradc, TS_CH_XM);
597         } else if (reg & LRADC_CTRL1_LRADC_IRQ(TS_CH_YM)) {
598                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(TS_CH_YM) |
599                         LRADC_CTRL1_LRADC_IRQ(TS_CH_YM), LRADC_CTRL1);
600                 val = mxs_lradc_read_raw_channel(lradc, TS_CH_YM);
601         } else {
602                 return -EIO;
603         }
604 
605         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
606         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
607 
608         return val;
609 }
610 
611 /*
612  * YP(open)--+-------------+
613  *           |             |--+
614  *           |             |  |
615  *    YM(-)--+-------------+  |
616  *             +--------------+
617  *             |              |
618  *         XP(weak+)        XM(open)
619  *
620  * "weak+" means 200k Ohm VDDIO
621  * (-) means GND
622  */
623 static void mxs_lradc_setup_touch_detection(struct mxs_lradc *lradc)
624 {
625         /*
626          * In order to detect a touch event the 'touch detect enable' bit
627          * enables:
628          *  - a weak pullup to the X+ connector
629          *  - a strong ground at the Y- connector
630          */
631         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
632         mxs_lradc_reg_set(lradc, mxs_lradc_touch_detect_bit(lradc),
633                                 LRADC_CTRL0);
634 }
635 
636 /*
637  * YP(meas)--+-------------+
638  *           |             |--+
639  *           |             |  |
640  * YM(open)--+-------------+  |
641  *             +--------------+
642  *             |              |
643  *           XP(+)          XM(-)
644  *
645  * (+) means here 1.85 V
646  * (-) means here GND
647  */
648 static void mxs_lradc_prepare_x_pos(struct mxs_lradc *lradc)
649 {
650         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
651         mxs_lradc_reg_set(lradc, mxs_lradc_drive_x_plate(lradc), LRADC_CTRL0);
652 
653         lradc->cur_plate = LRADC_SAMPLE_X;
654         mxs_lradc_setup_ts_channel(lradc, TS_CH_YP);
655 }
656 
657 /*
658  *   YP(+)--+-------------+
659  *          |             |--+
660  *          |             |  |
661  *   YM(-)--+-------------+  |
662  *            +--------------+
663  *            |              |
664  *         XP(open)        XM(meas)
665  *
666  * (+) means here 1.85 V
667  * (-) means here GND
668  */
669 static void mxs_lradc_prepare_y_pos(struct mxs_lradc *lradc)
670 {
671         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
672         mxs_lradc_reg_set(lradc, mxs_lradc_drive_y_plate(lradc), LRADC_CTRL0);
673 
674         lradc->cur_plate = LRADC_SAMPLE_Y;
675         mxs_lradc_setup_ts_channel(lradc, TS_CH_XM);
676 }
677 
678 /*
679  *    YP(+)--+-------------+
680  *           |             |--+
681  *           |             |  |
682  * YM(meas)--+-------------+  |
683  *             +--------------+
684  *             |              |
685  *          XP(meas)        XM(-)
686  *
687  * (+) means here 1.85 V
688  * (-) means here GND
689  */
690 static void mxs_lradc_prepare_pressure(struct mxs_lradc *lradc)
691 {
692         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
693         mxs_lradc_reg_set(lradc, mxs_lradc_drive_pressure(lradc), LRADC_CTRL0);
694 
695         lradc->cur_plate = LRADC_SAMPLE_PRESSURE;
696         mxs_lradc_setup_ts_pressure(lradc, TS_CH_XP, TS_CH_YM);
697 }
698 
699 static void mxs_lradc_enable_touch_detection(struct mxs_lradc *lradc)
700 {
701         mxs_lradc_setup_touch_detection(lradc);
702 
703         lradc->cur_plate = LRADC_TOUCH;
704         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ |
705                                 LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
706         mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
707 }
708 
709 static void mxs_lradc_report_ts_event(struct mxs_lradc *lradc)
710 {
711         input_report_abs(lradc->ts_input, ABS_X, lradc->ts_x_pos);
712         input_report_abs(lradc->ts_input, ABS_Y, lradc->ts_y_pos);
713         input_report_abs(lradc->ts_input, ABS_PRESSURE, lradc->ts_pressure);
714         input_report_key(lradc->ts_input, BTN_TOUCH, 1);
715         input_sync(lradc->ts_input);
716 }
717 
718 static void mxs_lradc_complete_touch_event(struct mxs_lradc *lradc)
719 {
720         mxs_lradc_setup_touch_detection(lradc);
721         lradc->cur_plate = LRADC_SAMPLE_VALID;
722         /*
723          * start a dummy conversion to burn time to settle the signals
724          * note: we are not interested in the conversion's value
725          */
726         mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(5));
727         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(5), LRADC_CTRL1);
728         mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(5), LRADC_CTRL1);
729         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << 5) |
730                 LRADC_DELAY_KICK | LRADC_DELAY_DELAY(10), /* waste 5 ms */
731                         LRADC_DELAY(2));
732 }
733 
734 /*
735  * in order to avoid false measurements, report only samples where
736  * the surface is still touched after the position measurement
737  */
738 static void mxs_lradc_finish_touch_event(struct mxs_lradc *lradc, bool valid)
739 {
740         /* if it is still touched, report the sample */
741         if (valid && mxs_lradc_check_touch_event(lradc)) {
742                 lradc->ts_valid = true;
743                 mxs_lradc_report_ts_event(lradc);
744         }
745 
746         /* if it is even still touched, continue with the next measurement */
747         if (mxs_lradc_check_touch_event(lradc)) {
748                 mxs_lradc_prepare_y_pos(lradc);
749                 return;
750         }
751 
752         if (lradc->ts_valid) {
753                 /* signal the release */
754                 lradc->ts_valid = false;
755                 input_report_key(lradc->ts_input, BTN_TOUCH, 0);
756                 input_sync(lradc->ts_input);
757         }
758 
759         /* if it is released, wait for the next touch via IRQ */
760         lradc->cur_plate = LRADC_TOUCH;
761         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ, LRADC_CTRL1);
762         mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
763 }
764 
765 /* touchscreen's state machine */
766 static void mxs_lradc_handle_touch(struct mxs_lradc *lradc)
767 {
768         int val;
769 
770         switch (lradc->cur_plate) {
771         case LRADC_TOUCH:
772                 /*
773                  * start with the Y-pos, because it uses nearly the same plate
774                  * settings like the touch detection
775                  */
776                 if (mxs_lradc_check_touch_event(lradc)) {
777                         mxs_lradc_reg_clear(lradc,
778                                         LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
779                                         LRADC_CTRL1);
780                         mxs_lradc_prepare_y_pos(lradc);
781                 }
782                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ,
783                                         LRADC_CTRL1);
784                 return;
785 
786         case LRADC_SAMPLE_Y:
787                 val = mxs_lradc_read_ts_channel(lradc);
788                 if (val < 0) {
789                         mxs_lradc_enable_touch_detection(lradc); /* re-start */
790                         return;
791                 }
792                 lradc->ts_y_pos = val;
793                 mxs_lradc_prepare_x_pos(lradc);
794                 return;
795 
796         case LRADC_SAMPLE_X:
797                 val = mxs_lradc_read_ts_channel(lradc);
798                 if (val < 0) {
799                         mxs_lradc_enable_touch_detection(lradc); /* re-start */
800                         return;
801                 }
802                 lradc->ts_x_pos = val;
803                 mxs_lradc_prepare_pressure(lradc);
804                 return;
805 
806         case LRADC_SAMPLE_PRESSURE:
807                 lradc->ts_pressure =
808                         mxs_lradc_read_ts_pressure(lradc, TS_CH_XP, TS_CH_YM);
809                 mxs_lradc_complete_touch_event(lradc);
810                 return;
811 
812         case LRADC_SAMPLE_VALID:
813                 val = mxs_lradc_read_ts_channel(lradc); /* ignore the value */
814                 mxs_lradc_finish_touch_event(lradc, 1);
815                 break;
816         }
817 }
818 
819 /*
820  * Raw I/O operations
821  */
822 static int mxs_lradc_read_single(struct iio_dev *iio_dev, int chan, int *val)
823 {
824         struct mxs_lradc *lradc = iio_priv(iio_dev);
825         int ret;
826 
827         /*
828          * See if there is no buffered operation in progess. If there is, simply
829          * bail out. This can be improved to support both buffered and raw IO at
830          * the same time, yet the code becomes horribly complicated. Therefore I
831          * applied KISS principle here.
832          */
833         ret = mutex_trylock(&lradc->lock);
834         if (!ret)
835                 return -EBUSY;
836 
837         reinit_completion(&lradc->completion);
838 
839         /*
840          * No buffered operation in progress, map the channel and trigger it.
841          * Virtual channel 0 is always used here as the others are always not
842          * used if doing raw sampling.
843          */
844         if (lradc->soc == IMX28_LRADC)
845                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
846                         LRADC_CTRL1);
847         mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
848 
849         /* Clean the slot's previous content, then set new one. */
850         mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0),
851                         LRADC_CTRL4);
852         mxs_lradc_reg_set(lradc, chan, LRADC_CTRL4);
853 
854         mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(0));
855 
856         /* Enable the IRQ and start sampling the channel. */
857         mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
858         mxs_lradc_reg_set(lradc, 1 << 0, LRADC_CTRL0);
859 
860         /* Wait for completion on the channel, 1 second max. */
861         ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
862         if (!ret)
863                 ret = -ETIMEDOUT;
864         if (ret < 0)
865                 goto err;
866 
867         /* Read the data. */
868         *val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
869         ret = IIO_VAL_INT;
870 
871 err:
872         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
873 
874         mutex_unlock(&lradc->lock);
875 
876         return ret;
877 }
878 
879 static int mxs_lradc_read_temp(struct iio_dev *iio_dev, int *val)
880 {
881         int ret, min, max;
882 
883         ret = mxs_lradc_read_single(iio_dev, 8, &min);
884         if (ret != IIO_VAL_INT)
885                 return ret;
886 
887         ret = mxs_lradc_read_single(iio_dev, 9, &max);
888         if (ret != IIO_VAL_INT)
889                 return ret;
890 
891         *val = max - min;
892 
893         return IIO_VAL_INT;
894 }
895 
896 static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
897                         const struct iio_chan_spec *chan,
898                         int *val, int *val2, long m)
899 {
900         struct mxs_lradc *lradc = iio_priv(iio_dev);
901 
902         switch (m) {
903         case IIO_CHAN_INFO_RAW:
904                 if (chan->type == IIO_TEMP)
905                         return mxs_lradc_read_temp(iio_dev, val);
906 
907                 return mxs_lradc_read_single(iio_dev, chan->channel, val);
908 
909         case IIO_CHAN_INFO_SCALE:
910                 if (chan->type == IIO_TEMP) {
911                         /* From the datasheet, we have to multiply by 1.012 and
912                          * divide by 4
913                          */
914                         *val = 0;
915                         *val2 = 253000;
916                         return IIO_VAL_INT_PLUS_MICRO;
917                 }
918 
919                 *val = lradc->vref_mv[chan->channel];
920                 *val2 = chan->scan_type.realbits -
921                         test_bit(chan->channel, &lradc->is_divided);
922                 return IIO_VAL_FRACTIONAL_LOG2;
923 
924         case IIO_CHAN_INFO_OFFSET:
925                 if (chan->type == IIO_TEMP) {
926                         /* The calculated value from the ADC is in Kelvin, we
927                          * want Celsius for hwmon so the offset is
928                          * -272.15 * scale
929                          */
930                         *val = -1075;
931                         *val2 = 691699;
932 
933                         return IIO_VAL_INT_PLUS_MICRO;
934                 }
935 
936                 return -EINVAL;
937 
938         default:
939                 break;
940         }
941 
942         return -EINVAL;
943 }
944 
945 static int mxs_lradc_write_raw(struct iio_dev *iio_dev,
946                                const struct iio_chan_spec *chan,
947                                int val, int val2, long m)
948 {
949         struct mxs_lradc *lradc = iio_priv(iio_dev);
950         struct mxs_lradc_scale *scale_avail =
951                         lradc->scale_avail[chan->channel];
952         int ret;
953 
954         ret = mutex_trylock(&lradc->lock);
955         if (!ret)
956                 return -EBUSY;
957 
958         switch (m) {
959         case IIO_CHAN_INFO_SCALE:
960                 ret = -EINVAL;
961                 if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
962                     val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
963                         /* divider by two disabled */
964                         writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
965                                lradc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR);
966                         clear_bit(chan->channel, &lradc->is_divided);
967                         ret = 0;
968                 } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
969                            val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
970                         /* divider by two enabled */
971                         writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
972                                lradc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET);
973                         set_bit(chan->channel, &lradc->is_divided);
974                         ret = 0;
975                 }
976 
977                 break;
978         default:
979                 ret = -EINVAL;
980                 break;
981         }
982 
983         mutex_unlock(&lradc->lock);
984 
985         return ret;
986 }
987 
988 static int mxs_lradc_write_raw_get_fmt(struct iio_dev *iio_dev,
989                                        const struct iio_chan_spec *chan,
990                                        long m)
991 {
992         return IIO_VAL_INT_PLUS_NANO;
993 }
994 
995 static ssize_t mxs_lradc_show_scale_available_ch(struct device *dev,
996                 struct device_attribute *attr,
997                 char *buf,
998                 int ch)
999 {
1000         struct iio_dev *iio = dev_to_iio_dev(dev);
1001         struct mxs_lradc *lradc = iio_priv(iio);
1002         int i, len = 0;
1003 
1004         for (i = 0; i < ARRAY_SIZE(lradc->scale_avail[ch]); i++)
1005                 len += sprintf(buf + len, "%d.%09u ",
1006                                lradc->scale_avail[ch][i].integer,
1007                                lradc->scale_avail[ch][i].nano);
1008 
1009         len += sprintf(buf + len, "\n");
1010 
1011         return len;
1012 }
1013 
1014 static ssize_t mxs_lradc_show_scale_available(struct device *dev,
1015                 struct device_attribute *attr,
1016                 char *buf)
1017 {
1018         struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
1019 
1020         return mxs_lradc_show_scale_available_ch(dev, attr, buf,
1021                                                  iio_attr->address);
1022 }
1023 
1024 #define SHOW_SCALE_AVAILABLE_ATTR(ch)                                   \
1025 static IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, S_IRUGO,       \
1026                        mxs_lradc_show_scale_available, NULL, ch)
1027 
1028 SHOW_SCALE_AVAILABLE_ATTR(0);
1029 SHOW_SCALE_AVAILABLE_ATTR(1);
1030 SHOW_SCALE_AVAILABLE_ATTR(2);
1031 SHOW_SCALE_AVAILABLE_ATTR(3);
1032 SHOW_SCALE_AVAILABLE_ATTR(4);
1033 SHOW_SCALE_AVAILABLE_ATTR(5);
1034 SHOW_SCALE_AVAILABLE_ATTR(6);
1035 SHOW_SCALE_AVAILABLE_ATTR(7);
1036 SHOW_SCALE_AVAILABLE_ATTR(10);
1037 SHOW_SCALE_AVAILABLE_ATTR(11);
1038 SHOW_SCALE_AVAILABLE_ATTR(12);
1039 SHOW_SCALE_AVAILABLE_ATTR(13);
1040 SHOW_SCALE_AVAILABLE_ATTR(14);
1041 SHOW_SCALE_AVAILABLE_ATTR(15);
1042 
1043 static struct attribute *mxs_lradc_attributes[] = {
1044         &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
1045         &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
1046         &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
1047         &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
1048         &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
1049         &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
1050         &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
1051         &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
1052         &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
1053         &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
1054         &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
1055         &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
1056         &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
1057         &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
1058         NULL
1059 };
1060 
1061 static const struct attribute_group mxs_lradc_attribute_group = {
1062         .attrs = mxs_lradc_attributes,
1063 };
1064 
1065 static const struct iio_info mxs_lradc_iio_info = {
1066         .driver_module          = THIS_MODULE,
1067         .read_raw               = mxs_lradc_read_raw,
1068         .write_raw              = mxs_lradc_write_raw,
1069         .write_raw_get_fmt      = mxs_lradc_write_raw_get_fmt,
1070         .attrs                  = &mxs_lradc_attribute_group,
1071 };
1072 
1073 static int mxs_lradc_ts_open(struct input_dev *dev)
1074 {
1075         struct mxs_lradc *lradc = input_get_drvdata(dev);
1076 
1077         /* Enable the touch-detect circuitry. */
1078         mxs_lradc_enable_touch_detection(lradc);
1079 
1080         return 0;
1081 }
1082 
1083 static void mxs_lradc_disable_ts(struct mxs_lradc *lradc)
1084 {
1085         /* stop all interrupts from firing */
1086         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN |
1087                 LRADC_CTRL1_LRADC_IRQ_EN(2) | LRADC_CTRL1_LRADC_IRQ_EN(3) |
1088                 LRADC_CTRL1_LRADC_IRQ_EN(4) | LRADC_CTRL1_LRADC_IRQ_EN(5),
1089                 LRADC_CTRL1);
1090 
1091         /* Power-down touchscreen touch-detect circuitry. */
1092         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
1093 }
1094 
1095 static void mxs_lradc_ts_close(struct input_dev *dev)
1096 {
1097         struct mxs_lradc *lradc = input_get_drvdata(dev);
1098 
1099         mxs_lradc_disable_ts(lradc);
1100 }
1101 
1102 static int mxs_lradc_ts_register(struct mxs_lradc *lradc)
1103 {
1104         struct input_dev *input;
1105         struct device *dev = lradc->dev;
1106         int ret;
1107 
1108         if (!lradc->use_touchscreen)
1109                 return 0;
1110 
1111         input = input_allocate_device();
1112         if (!input)
1113                 return -ENOMEM;
1114 
1115         input->name = DRIVER_NAME;
1116         input->id.bustype = BUS_HOST;
1117         input->dev.parent = dev;
1118         input->open = mxs_lradc_ts_open;
1119         input->close = mxs_lradc_ts_close;
1120 
1121         __set_bit(EV_ABS, input->evbit);
1122         __set_bit(EV_KEY, input->evbit);
1123         __set_bit(BTN_TOUCH, input->keybit);
1124         input_set_abs_params(input, ABS_X, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1125         input_set_abs_params(input, ABS_Y, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1126         input_set_abs_params(input, ABS_PRESSURE, 0, LRADC_SINGLE_SAMPLE_MASK,
1127                              0, 0);
1128 
1129         lradc->ts_input = input;
1130         input_set_drvdata(input, lradc);
1131         ret = input_register_device(input);
1132         if (ret)
1133                 input_free_device(lradc->ts_input);
1134 
1135         return ret;
1136 }
1137 
1138 static void mxs_lradc_ts_unregister(struct mxs_lradc *lradc)
1139 {
1140         if (!lradc->use_touchscreen)
1141                 return;
1142 
1143         mxs_lradc_disable_ts(lradc);
1144         input_unregister_device(lradc->ts_input);
1145 }
1146 
1147 /*
1148  * IRQ Handling
1149  */
1150 static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
1151 {
1152         struct iio_dev *iio = data;
1153         struct mxs_lradc *lradc = iio_priv(iio);
1154         unsigned long reg = readl(lradc->base + LRADC_CTRL1);
1155         const uint32_t ts_irq_mask =
1156                 LRADC_CTRL1_TOUCH_DETECT_IRQ |
1157                 LRADC_CTRL1_LRADC_IRQ(2) |
1158                 LRADC_CTRL1_LRADC_IRQ(3) |
1159                 LRADC_CTRL1_LRADC_IRQ(4) |
1160                 LRADC_CTRL1_LRADC_IRQ(5);
1161 
1162         if (!(reg & mxs_lradc_irq_mask(lradc)))
1163                 return IRQ_NONE;
1164 
1165         if (lradc->use_touchscreen && (reg & ts_irq_mask))
1166                 mxs_lradc_handle_touch(lradc);
1167 
1168         if (iio_buffer_enabled(iio))
1169                 iio_trigger_poll(iio->trig, iio_get_time_ns());
1170         else if (reg & LRADC_CTRL1_LRADC_IRQ(0))
1171                 complete(&lradc->completion);
1172 
1173         mxs_lradc_reg_clear(lradc, reg & mxs_lradc_irq_mask(lradc),
1174                         LRADC_CTRL1);
1175 
1176         return IRQ_HANDLED;
1177 }
1178 
1179 /*
1180  * Trigger handling
1181  */
1182 static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
1183 {
1184         struct iio_poll_func *pf = p;
1185         struct iio_dev *iio = pf->indio_dev;
1186         struct mxs_lradc *lradc = iio_priv(iio);
1187         const uint32_t chan_value = LRADC_CH_ACCUMULATE |
1188                 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1189         unsigned int i, j = 0;
1190 
1191         for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1192                 lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
1193                 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(j));
1194                 lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
1195                 lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
1196                 j++;
1197         }
1198 
1199         iio_push_to_buffers_with_timestamp(iio, lradc->buffer, pf->timestamp);
1200 
1201         iio_trigger_notify_done(iio->trig);
1202 
1203         return IRQ_HANDLED;
1204 }
1205 
1206 static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
1207 {
1208         struct iio_dev *iio = iio_trigger_get_drvdata(trig);
1209         struct mxs_lradc *lradc = iio_priv(iio);
1210         const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
1211 
1212         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_KICK, LRADC_DELAY(0) + st);
1213 
1214         return 0;
1215 }
1216 
1217 static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
1218         .owner = THIS_MODULE,
1219         .set_trigger_state = &mxs_lradc_configure_trigger,
1220 };
1221 
1222 static int mxs_lradc_trigger_init(struct iio_dev *iio)
1223 {
1224         int ret;
1225         struct iio_trigger *trig;
1226         struct mxs_lradc *lradc = iio_priv(iio);
1227 
1228         trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
1229         if (trig == NULL)
1230                 return -ENOMEM;
1231 
1232         trig->dev.parent = lradc->dev;
1233         iio_trigger_set_drvdata(trig, iio);
1234         trig->ops = &mxs_lradc_trigger_ops;
1235 
1236         ret = iio_trigger_register(trig);
1237         if (ret) {
1238                 iio_trigger_free(trig);
1239                 return ret;
1240         }
1241 
1242         lradc->trig = trig;
1243 
1244         return 0;
1245 }
1246 
1247 static void mxs_lradc_trigger_remove(struct iio_dev *iio)
1248 {
1249         struct mxs_lradc *lradc = iio_priv(iio);
1250 
1251         iio_trigger_unregister(lradc->trig);
1252         iio_trigger_free(lradc->trig);
1253 }
1254 
1255 static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
1256 {
1257         struct mxs_lradc *lradc = iio_priv(iio);
1258         int ret = 0, chan, ofs = 0;
1259         unsigned long enable = 0;
1260         uint32_t ctrl4_set = 0;
1261         uint32_t ctrl4_clr = 0;
1262         uint32_t ctrl1_irq = 0;
1263         const uint32_t chan_value = LRADC_CH_ACCUMULATE |
1264                 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1265         const int len = bitmap_weight(iio->active_scan_mask,
1266                         LRADC_MAX_TOTAL_CHANS);
1267 
1268         if (!len)
1269                 return -EINVAL;
1270 
1271         /*
1272          * Lock the driver so raw access can not be done during buffered
1273          * operation. This simplifies the code a lot.
1274          */
1275         ret = mutex_trylock(&lradc->lock);
1276         if (!ret)
1277                 return -EBUSY;
1278 
1279         lradc->buffer = kmalloc(len * sizeof(*lradc->buffer), GFP_KERNEL);
1280         if (!lradc->buffer) {
1281                 ret = -ENOMEM;
1282                 goto err_mem;
1283         }
1284 
1285         if (lradc->soc == IMX28_LRADC)
1286                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
1287                                                         LRADC_CTRL1);
1288         mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
1289 
1290         for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1291                 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
1292                 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
1293                 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
1294                 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(ofs));
1295                 bitmap_set(&enable, ofs, 1);
1296                 ofs++;
1297         }
1298 
1299         mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1300                                         LRADC_DELAY_KICK, LRADC_DELAY(0));
1301         mxs_lradc_reg_clear(lradc, ctrl4_clr, LRADC_CTRL4);
1302         mxs_lradc_reg_set(lradc, ctrl4_set, LRADC_CTRL4);
1303         mxs_lradc_reg_set(lradc, ctrl1_irq, LRADC_CTRL1);
1304         mxs_lradc_reg_set(lradc, enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
1305                                         LRADC_DELAY(0));
1306 
1307         return 0;
1308 
1309 err_mem:
1310         mutex_unlock(&lradc->lock);
1311         return ret;
1312 }
1313 
1314 static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
1315 {
1316         struct mxs_lradc *lradc = iio_priv(iio);
1317 
1318         mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1319                                         LRADC_DELAY_KICK, LRADC_DELAY(0));
1320 
1321         mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
1322         if (lradc->soc == IMX28_LRADC)
1323                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
1324                                         LRADC_CTRL1);
1325 
1326         kfree(lradc->buffer);
1327         mutex_unlock(&lradc->lock);
1328 
1329         return 0;
1330 }
1331 
1332 static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
1333                                         const unsigned long *mask)
1334 {
1335         struct mxs_lradc *lradc = iio_priv(iio);
1336         const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
1337         int rsvd_chans = 0;
1338         unsigned long rsvd_mask = 0;
1339 
1340         if (lradc->use_touchbutton)
1341                 rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
1342         if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_4WIRE)
1343                 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
1344         if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1345                 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
1346 
1347         if (lradc->use_touchbutton)
1348                 rsvd_chans++;
1349         if (lradc->use_touchscreen)
1350                 rsvd_chans++;
1351 
1352         /* Test for attempts to map channels with special mode of operation. */
1353         if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
1354                 return false;
1355 
1356         /* Test for attempts to map more channels then available slots. */
1357         if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
1358                 return false;
1359 
1360         return true;
1361 }
1362 
1363 static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
1364         .preenable = &mxs_lradc_buffer_preenable,
1365         .postenable = &iio_triggered_buffer_postenable,
1366         .predisable = &iio_triggered_buffer_predisable,
1367         .postdisable = &mxs_lradc_buffer_postdisable,
1368         .validate_scan_mask = &mxs_lradc_validate_scan_mask,
1369 };
1370 
1371 /*
1372  * Driver initialization
1373  */
1374 
1375 #define MXS_ADC_CHAN(idx, chan_type) {                          \
1376         .type = (chan_type),                                    \
1377         .indexed = 1,                                           \
1378         .scan_index = (idx),                                    \
1379         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
1380                               BIT(IIO_CHAN_INFO_SCALE),         \
1381         .channel = (idx),                                       \
1382         .address = (idx),                                       \
1383         .scan_type = {                                          \
1384                 .sign = 'u',                                    \
1385                 .realbits = LRADC_RESOLUTION,                   \
1386                 .storagebits = 32,                              \
1387         },                                                      \
1388 }
1389 
1390 static const struct iio_chan_spec mxs_lradc_chan_spec[] = {
1391         MXS_ADC_CHAN(0, IIO_VOLTAGE),
1392         MXS_ADC_CHAN(1, IIO_VOLTAGE),
1393         MXS_ADC_CHAN(2, IIO_VOLTAGE),
1394         MXS_ADC_CHAN(3, IIO_VOLTAGE),
1395         MXS_ADC_CHAN(4, IIO_VOLTAGE),
1396         MXS_ADC_CHAN(5, IIO_VOLTAGE),
1397         MXS_ADC_CHAN(6, IIO_VOLTAGE),
1398         MXS_ADC_CHAN(7, IIO_VOLTAGE),   /* VBATT */
1399         /* Combined Temperature sensors */
1400         {
1401                 .type = IIO_TEMP,
1402                 .indexed = 1,
1403                 .scan_index = 8,
1404                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1405                                       BIT(IIO_CHAN_INFO_OFFSET) |
1406                                       BIT(IIO_CHAN_INFO_SCALE),
1407                 .channel = 8,
1408                 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
1409         },
1410         MXS_ADC_CHAN(10, IIO_VOLTAGE),  /* VDDIO */
1411         MXS_ADC_CHAN(11, IIO_VOLTAGE),  /* VTH */
1412         MXS_ADC_CHAN(12, IIO_VOLTAGE),  /* VDDA */
1413         MXS_ADC_CHAN(13, IIO_VOLTAGE),  /* VDDD */
1414         MXS_ADC_CHAN(14, IIO_VOLTAGE),  /* VBG */
1415         MXS_ADC_CHAN(15, IIO_VOLTAGE),  /* VDD5V */
1416 };
1417 
1418 static int mxs_lradc_hw_init(struct mxs_lradc *lradc)
1419 {
1420         /* The ADC always uses DELAY CHANNEL 0. */
1421         const uint32_t adc_cfg =
1422                 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
1423                 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
1424 
1425         int ret = stmp_reset_block(lradc->base);
1426         if (ret)
1427                 return ret;
1428 
1429         /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
1430         mxs_lradc_reg_wrt(lradc, adc_cfg, LRADC_DELAY(0));
1431 
1432         /* Disable remaining DELAY CHANNELs */
1433         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(1));
1434         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
1435         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
1436 
1437         /* Configure the touchscreen type */
1438         if (lradc->soc == IMX28_LRADC) {
1439                 mxs_lradc_reg_clear(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
1440                                                         LRADC_CTRL0);
1441 
1442         if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1443                 mxs_lradc_reg_set(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
1444                                 LRADC_CTRL0);
1445         }
1446 
1447         /* Start internal temperature sensing. */
1448         mxs_lradc_reg_wrt(lradc, 0, LRADC_CTRL2);
1449 
1450         return 0;
1451 }
1452 
1453 static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
1454 {
1455         int i;
1456 
1457         mxs_lradc_reg_clear(lradc, mxs_lradc_irq_en_mask(lradc), LRADC_CTRL1);
1458 
1459         for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
1460                 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(i));
1461 }
1462 
1463 static const struct of_device_id mxs_lradc_dt_ids[] = {
1464         { .compatible = "fsl,imx23-lradc", .data = (void *)IMX23_LRADC, },
1465         { .compatible = "fsl,imx28-lradc", .data = (void *)IMX28_LRADC, },
1466         { /* sentinel */ }
1467 };
1468 MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
1469 
1470 static int mxs_lradc_probe_touchscreen(struct mxs_lradc *lradc,
1471                                                 struct device_node *lradc_node)
1472 {
1473         int ret;
1474         u32 ts_wires = 0, adapt;
1475 
1476         ret = of_property_read_u32(lradc_node, "fsl,lradc-touchscreen-wires",
1477                                 &ts_wires);
1478         if (ret)
1479                 return -ENODEV; /* touchscreen feature disabled */
1480 
1481         switch (ts_wires) {
1482         case 4:
1483                 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_4WIRE;
1484                 break;
1485         case 5:
1486                 if (lradc->soc == IMX28_LRADC) {
1487                         lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_5WIRE;
1488                         break;
1489                 }
1490                 /* fall through an error message for i.MX23 */
1491         default:
1492                 dev_err(lradc->dev,
1493                         "Unsupported number of touchscreen wires (%d)\n",
1494                         ts_wires);
1495                 return -EINVAL;
1496         }
1497 
1498         lradc->over_sample_cnt = 4;
1499         ret = of_property_read_u32(lradc_node, "fsl,ave-ctrl", &adapt);
1500         if (ret == 0)
1501                 lradc->over_sample_cnt = adapt;
1502 
1503         lradc->over_sample_delay = 2;
1504         ret = of_property_read_u32(lradc_node, "fsl,ave-delay", &adapt);
1505         if (ret == 0)
1506                 lradc->over_sample_delay = adapt;
1507 
1508         lradc->settling_delay = 10;
1509         ret = of_property_read_u32(lradc_node, "fsl,settling", &adapt);
1510         if (ret == 0)
1511                 lradc->settling_delay = adapt;
1512 
1513         return 0;
1514 }
1515 
1516 static int mxs_lradc_probe(struct platform_device *pdev)
1517 {
1518         const struct of_device_id *of_id =
1519                 of_match_device(mxs_lradc_dt_ids, &pdev->dev);
1520         const struct mxs_lradc_of_config *of_cfg =
1521                 &mxs_lradc_of_config[(enum mxs_lradc_id)of_id->data];
1522         struct device *dev = &pdev->dev;
1523         struct device_node *node = dev->of_node;
1524         struct mxs_lradc *lradc;
1525         struct iio_dev *iio;
1526         struct resource *iores;
1527         int ret = 0, touch_ret;
1528         int i, s;
1529         uint64_t scale_uv;
1530 
1531         /* Allocate the IIO device. */
1532         iio = devm_iio_device_alloc(dev, sizeof(*lradc));
1533         if (!iio) {
1534                 dev_err(dev, "Failed to allocate IIO device\n");
1535                 return -ENOMEM;
1536         }
1537 
1538         lradc = iio_priv(iio);
1539         lradc->soc = (enum mxs_lradc_id)of_id->data;
1540 
1541         /* Grab the memory area */
1542         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1543         lradc->dev = &pdev->dev;
1544         lradc->base = devm_ioremap_resource(dev, iores);
1545         if (IS_ERR(lradc->base))
1546                 return PTR_ERR(lradc->base);
1547 
1548         lradc->clk = devm_clk_get(&pdev->dev, NULL);
1549         if (IS_ERR(lradc->clk)) {
1550                 dev_err(dev, "Failed to get the delay unit clock\n");
1551                 return PTR_ERR(lradc->clk);
1552         }
1553         ret = clk_prepare_enable(lradc->clk);
1554         if (ret != 0) {
1555                 dev_err(dev, "Failed to enable the delay unit clock\n");
1556                 return ret;
1557         }
1558 
1559         touch_ret = mxs_lradc_probe_touchscreen(lradc, node);
1560 
1561         /* Grab all IRQ sources */
1562         for (i = 0; i < of_cfg->irq_count; i++) {
1563                 lradc->irq[i] = platform_get_irq(pdev, i);
1564                 if (lradc->irq[i] < 0)
1565                         return lradc->irq[i];
1566 
1567                 ret = devm_request_irq(dev, lradc->irq[i],
1568                                         mxs_lradc_handle_irq, 0,
1569                                         of_cfg->irq_name[i], iio);
1570                 if (ret)
1571                         return ret;
1572         }
1573 
1574         lradc->vref_mv = of_cfg->vref_mv;
1575 
1576         platform_set_drvdata(pdev, iio);
1577 
1578         init_completion(&lradc->completion);
1579         mutex_init(&lradc->lock);
1580 
1581         iio->name = pdev->name;
1582         iio->dev.parent = &pdev->dev;
1583         iio->info = &mxs_lradc_iio_info;
1584         iio->modes = INDIO_DIRECT_MODE;
1585         iio->channels = mxs_lradc_chan_spec;
1586         iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec);
1587         iio->masklength = LRADC_MAX_TOTAL_CHANS;
1588 
1589         ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
1590                                 &mxs_lradc_trigger_handler,
1591                                 &mxs_lradc_buffer_ops);
1592         if (ret)
1593                 return ret;
1594 
1595         ret = mxs_lradc_trigger_init(iio);
1596         if (ret)
1597                 goto err_trig;
1598 
1599         /* Populate available ADC input ranges */
1600         for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
1601                 for (s = 0; s < ARRAY_SIZE(lradc->scale_avail[i]); s++) {
1602                         /*
1603                          * [s=0] = optional divider by two disabled (default)
1604                          * [s=1] = optional divider by two enabled
1605                          *
1606                          * The scale is calculated by doing:
1607                          *   Vref >> (realbits - s)
1608                          * which multiplies by two on the second component
1609                          * of the array.
1610                          */
1611                         scale_uv = ((u64)lradc->vref_mv[i] * 100000000) >>
1612                                    (LRADC_RESOLUTION - s);
1613                         lradc->scale_avail[i][s].nano =
1614                                         do_div(scale_uv, 100000000) * 10;
1615                         lradc->scale_avail[i][s].integer = scale_uv;
1616                 }
1617         }
1618 
1619         /* Configure the hardware. */
1620         ret = mxs_lradc_hw_init(lradc);
1621         if (ret)
1622                 goto err_dev;
1623 
1624         /* Register the touchscreen input device. */
1625         if (touch_ret == 0) {
1626                 ret = mxs_lradc_ts_register(lradc);
1627                 if (ret)
1628                         goto err_ts_register;
1629         }
1630 
1631         /* Register IIO device. */
1632         ret = iio_device_register(iio);
1633         if (ret) {
1634                 dev_err(dev, "Failed to register IIO device\n");
1635                 goto err_ts;
1636         }
1637 
1638         return 0;
1639 
1640 err_ts:
1641         mxs_lradc_ts_unregister(lradc);
1642 err_ts_register:
1643         mxs_lradc_hw_stop(lradc);
1644 err_dev:
1645         mxs_lradc_trigger_remove(iio);
1646 err_trig:
1647         iio_triggered_buffer_cleanup(iio);
1648         return ret;
1649 }
1650 
1651 static int mxs_lradc_remove(struct platform_device *pdev)
1652 {
1653         struct iio_dev *iio = platform_get_drvdata(pdev);
1654         struct mxs_lradc *lradc = iio_priv(iio);
1655 
1656         iio_device_unregister(iio);
1657         mxs_lradc_ts_unregister(lradc);
1658         mxs_lradc_hw_stop(lradc);
1659         mxs_lradc_trigger_remove(iio);
1660         iio_triggered_buffer_cleanup(iio);
1661 
1662         clk_disable_unprepare(lradc->clk);
1663         return 0;
1664 }
1665 
1666 static struct platform_driver mxs_lradc_driver = {
1667         .driver = {
1668                 .name   = DRIVER_NAME,
1669                 .owner  = THIS_MODULE,
1670                 .of_match_table = mxs_lradc_dt_ids,
1671         },
1672         .probe  = mxs_lradc_probe,
1673         .remove = mxs_lradc_remove,
1674 };
1675 
1676 module_platform_driver(mxs_lradc_driver);
1677 
1678 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1679 MODULE_DESCRIPTION("Freescale i.MX28 LRADC driver");
1680 MODULE_LICENSE("GPL v2");
1681 MODULE_ALIAS("platform:" DRIVER_NAME);
1682 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us