Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/staging/iio/adc/mxs-lradc.c

  1 /*
  2  * Freescale i.MX28 LRADC driver
  3  *
  4  * Copyright (c) 2012 DENX Software Engineering, GmbH.
  5  * Marek Vasut <marex@denx.de>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  *
 12  * This program is distributed in the hope that it will be useful,
 13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 15  * GNU General Public License for more details.
 16  */
 17 
 18 #include <linux/err.h>
 19 #include <linux/interrupt.h>
 20 #include <linux/device.h>
 21 #include <linux/kernel.h>
 22 #include <linux/slab.h>
 23 #include <linux/of.h>
 24 #include <linux/of_device.h>
 25 #include <linux/sysfs.h>
 26 #include <linux/list.h>
 27 #include <linux/io.h>
 28 #include <linux/module.h>
 29 #include <linux/platform_device.h>
 30 #include <linux/spinlock.h>
 31 #include <linux/wait.h>
 32 #include <linux/sched.h>
 33 #include <linux/stmp_device.h>
 34 #include <linux/bitops.h>
 35 #include <linux/completion.h>
 36 #include <linux/delay.h>
 37 #include <linux/input.h>
 38 #include <linux/clk.h>
 39 
 40 #include <linux/iio/iio.h>
 41 #include <linux/iio/sysfs.h>
 42 #include <linux/iio/buffer.h>
 43 #include <linux/iio/trigger.h>
 44 #include <linux/iio/trigger_consumer.h>
 45 #include <linux/iio/triggered_buffer.h>
 46 
 47 #define DRIVER_NAME             "mxs-lradc"
 48 
 49 #define LRADC_MAX_DELAY_CHANS   4
 50 #define LRADC_MAX_MAPPED_CHANS  8
 51 #define LRADC_MAX_TOTAL_CHANS   16
 52 
 53 #define LRADC_DELAY_TIMER_HZ    2000
 54 
 55 /*
 56  * Make this runtime configurable if necessary. Currently, if the buffered mode
 57  * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
 58  * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
 59  * seconds. The result is that the samples arrive every 500mS.
 60  */
 61 #define LRADC_DELAY_TIMER_PER   200
 62 #define LRADC_DELAY_TIMER_LOOP  5
 63 
 64 /*
 65  * Once the pen touches the touchscreen, the touchscreen switches from
 66  * IRQ-driven mode to polling mode to prevent interrupt storm. The polling
 67  * is realized by worker thread, which is called every 20 or so milliseconds.
 68  * This gives the touchscreen enough fluence and does not strain the system
 69  * too much.
 70  */
 71 #define LRADC_TS_SAMPLE_DELAY_MS        5
 72 
 73 /*
 74  * The LRADC reads the following amount of samples from each touchscreen
 75  * channel and the driver then computes avarage of these.
 76  */
 77 #define LRADC_TS_SAMPLE_AMOUNT          4
 78 
 79 enum mxs_lradc_id {
 80         IMX23_LRADC,
 81         IMX28_LRADC,
 82 };
 83 
 84 static const char * const mx23_lradc_irq_names[] = {
 85         "mxs-lradc-touchscreen",
 86         "mxs-lradc-channel0",
 87         "mxs-lradc-channel1",
 88         "mxs-lradc-channel2",
 89         "mxs-lradc-channel3",
 90         "mxs-lradc-channel4",
 91         "mxs-lradc-channel5",
 92         "mxs-lradc-channel6",
 93         "mxs-lradc-channel7",
 94 };
 95 
 96 static const char * const mx28_lradc_irq_names[] = {
 97         "mxs-lradc-touchscreen",
 98         "mxs-lradc-thresh0",
 99         "mxs-lradc-thresh1",
100         "mxs-lradc-channel0",
101         "mxs-lradc-channel1",
102         "mxs-lradc-channel2",
103         "mxs-lradc-channel3",
104         "mxs-lradc-channel4",
105         "mxs-lradc-channel5",
106         "mxs-lradc-channel6",
107         "mxs-lradc-channel7",
108         "mxs-lradc-button0",
109         "mxs-lradc-button1",
110 };
111 
112 struct mxs_lradc_of_config {
113         const int               irq_count;
114         const char * const      *irq_name;
115         const uint32_t          *vref_mv;
116 };
117 
118 #define VREF_MV_BASE 1850
119 
120 static const uint32_t mx23_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
121         VREF_MV_BASE,           /* CH0 */
122         VREF_MV_BASE,           /* CH1 */
123         VREF_MV_BASE,           /* CH2 */
124         VREF_MV_BASE,           /* CH3 */
125         VREF_MV_BASE,           /* CH4 */
126         VREF_MV_BASE,           /* CH5 */
127         VREF_MV_BASE * 2,       /* CH6 VDDIO */
128         VREF_MV_BASE * 4,       /* CH7 VBATT */
129         VREF_MV_BASE,           /* CH8 Temp sense 0 */
130         VREF_MV_BASE,           /* CH9 Temp sense 1 */
131         VREF_MV_BASE,           /* CH10 */
132         VREF_MV_BASE,           /* CH11 */
133         VREF_MV_BASE,           /* CH12 USB_DP */
134         VREF_MV_BASE,           /* CH13 USB_DN */
135         VREF_MV_BASE,           /* CH14 VBG */
136         VREF_MV_BASE * 4,       /* CH15 VDD5V */
137 };
138 
139 static const uint32_t mx28_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
140         VREF_MV_BASE,           /* CH0 */
141         VREF_MV_BASE,           /* CH1 */
142         VREF_MV_BASE,           /* CH2 */
143         VREF_MV_BASE,           /* CH3 */
144         VREF_MV_BASE,           /* CH4 */
145         VREF_MV_BASE,           /* CH5 */
146         VREF_MV_BASE,           /* CH6 */
147         VREF_MV_BASE * 4,       /* CH7 VBATT */
148         VREF_MV_BASE,           /* CH8 Temp sense 0 */
149         VREF_MV_BASE,           /* CH9 Temp sense 1 */
150         VREF_MV_BASE * 2,       /* CH10 VDDIO */
151         VREF_MV_BASE,           /* CH11 VTH */
152         VREF_MV_BASE * 2,       /* CH12 VDDA */
153         VREF_MV_BASE,           /* CH13 VDDD */
154         VREF_MV_BASE,           /* CH14 VBG */
155         VREF_MV_BASE * 4,       /* CH15 VDD5V */
156 };
157 
158 static const struct mxs_lradc_of_config mxs_lradc_of_config[] = {
159         [IMX23_LRADC] = {
160                 .irq_count      = ARRAY_SIZE(mx23_lradc_irq_names),
161                 .irq_name       = mx23_lradc_irq_names,
162                 .vref_mv        = mx23_vref_mv,
163         },
164         [IMX28_LRADC] = {
165                 .irq_count      = ARRAY_SIZE(mx28_lradc_irq_names),
166                 .irq_name       = mx28_lradc_irq_names,
167                 .vref_mv        = mx28_vref_mv,
168         },
169 };
170 
171 enum mxs_lradc_ts {
172         MXS_LRADC_TOUCHSCREEN_NONE = 0,
173         MXS_LRADC_TOUCHSCREEN_4WIRE,
174         MXS_LRADC_TOUCHSCREEN_5WIRE,
175 };
176 
177 /*
178  * Touchscreen handling
179  */
180 enum lradc_ts_plate {
181         LRADC_TOUCH = 0,
182         LRADC_SAMPLE_X,
183         LRADC_SAMPLE_Y,
184         LRADC_SAMPLE_PRESSURE,
185         LRADC_SAMPLE_VALID,
186 };
187 
188 enum mxs_lradc_divbytwo {
189         MXS_LRADC_DIV_DISABLED = 0,
190         MXS_LRADC_DIV_ENABLED,
191 };
192 
193 struct mxs_lradc_scale {
194         unsigned int            integer;
195         unsigned int            nano;
196 };
197 
198 struct mxs_lradc {
199         struct device           *dev;
200         void __iomem            *base;
201         int                     irq[13];
202 
203         struct clk              *clk;
204 
205         uint32_t                *buffer;
206         struct iio_trigger      *trig;
207 
208         struct mutex            lock;
209 
210         struct completion       completion;
211 
212         const uint32_t          *vref_mv;
213         struct mxs_lradc_scale  scale_avail[LRADC_MAX_TOTAL_CHANS][2];
214         unsigned long           is_divided;
215 
216         /*
217          * Touchscreen LRADC channels receives a private slot in the CTRL4
218          * register, the slot #7. Therefore only 7 slots instead of 8 in the
219          * CTRL4 register can be mapped to LRADC channels when using the
220          * touchscreen.
221          *
222          * Furthermore, certain LRADC channels are shared between touchscreen
223          * and/or touch-buttons and generic LRADC block. Therefore when using
224          * either of these, these channels are not available for the regular
225          * sampling. The shared channels are as follows:
226          *
227          * CH0 -- Touch button #0
228          * CH1 -- Touch button #1
229          * CH2 -- Touch screen XPUL
230          * CH3 -- Touch screen YPLL
231          * CH4 -- Touch screen XNUL
232          * CH5 -- Touch screen YNLR
233          * CH6 -- Touch screen WIPER (5-wire only)
234          *
235          * The bitfields below represents which parts of the LRADC block are
236          * switched into special mode of operation. These channels can not
237          * be sampled as regular LRADC channels. The driver will refuse any
238          * attempt to sample these channels.
239          */
240 #define CHAN_MASK_TOUCHBUTTON           (0x3 << 0)
241 #define CHAN_MASK_TOUCHSCREEN_4WIRE     (0xf << 2)
242 #define CHAN_MASK_TOUCHSCREEN_5WIRE     (0x1f << 2)
243         enum mxs_lradc_ts       use_touchscreen;
244         bool                    use_touchbutton;
245 
246         struct input_dev        *ts_input;
247 
248         enum mxs_lradc_id       soc;
249         enum lradc_ts_plate     cur_plate; /* statemachine */
250         bool                    ts_valid;
251         unsigned                ts_x_pos;
252         unsigned                ts_y_pos;
253         unsigned                ts_pressure;
254 
255         /* handle touchscreen's physical behaviour */
256         /* samples per coordinate */
257         unsigned                over_sample_cnt;
258         /* time clocks between samples */
259         unsigned                over_sample_delay;
260         /* time in clocks to wait after the plates where switched */
261         unsigned                settling_delay;
262 };
263 
264 #define LRADC_CTRL0                             0x00
265 # define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE   (1 << 23)
266 # define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE     (1 << 22)
267 # define LRADC_CTRL0_MX28_YNNSW /* YM */        (1 << 21)
268 # define LRADC_CTRL0_MX28_YPNSW /* YP */        (1 << 20)
269 # define LRADC_CTRL0_MX28_YPPSW /* YP */        (1 << 19)
270 # define LRADC_CTRL0_MX28_XNNSW /* XM */        (1 << 18)
271 # define LRADC_CTRL0_MX28_XNPSW /* XM */        (1 << 17)
272 # define LRADC_CTRL0_MX28_XPPSW /* XP */        (1 << 16)
273 
274 # define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE   (1 << 20)
275 # define LRADC_CTRL0_MX23_YM                    (1 << 19)
276 # define LRADC_CTRL0_MX23_XM                    (1 << 18)
277 # define LRADC_CTRL0_MX23_YP                    (1 << 17)
278 # define LRADC_CTRL0_MX23_XP                    (1 << 16)
279 
280 # define LRADC_CTRL0_MX28_PLATE_MASK \
281                 (LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \
282                 LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \
283                 LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \
284                 LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW)
285 
286 # define LRADC_CTRL0_MX23_PLATE_MASK \
287                 (LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE | \
288                 LRADC_CTRL0_MX23_YM | LRADC_CTRL0_MX23_XM | \
289                 LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XP)
290 
291 #define LRADC_CTRL1                             0x10
292 #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN         (1 << 24)
293 #define LRADC_CTRL1_LRADC_IRQ_EN(n)             (1 << ((n) + 16))
294 #define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK      (0x1fff << 16)
295 #define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK      (0x01ff << 16)
296 #define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET         16
297 #define LRADC_CTRL1_TOUCH_DETECT_IRQ            (1 << 8)
298 #define LRADC_CTRL1_LRADC_IRQ(n)                (1 << (n))
299 #define LRADC_CTRL1_MX28_LRADC_IRQ_MASK         0x1fff
300 #define LRADC_CTRL1_MX23_LRADC_IRQ_MASK         0x01ff
301 #define LRADC_CTRL1_LRADC_IRQ_OFFSET            0
302 
303 #define LRADC_CTRL2                             0x20
304 #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET        24
305 #define LRADC_CTRL2_TEMPSENSE_PWD               (1 << 15)
306 
307 #define LRADC_STATUS                            0x40
308 #define LRADC_STATUS_TOUCH_DETECT_RAW           (1 << 0)
309 
310 #define LRADC_CH(n)                             (0x50 + (0x10 * (n)))
311 #define LRADC_CH_ACCUMULATE                     (1 << 29)
312 #define LRADC_CH_NUM_SAMPLES_MASK               (0x1f << 24)
313 #define LRADC_CH_NUM_SAMPLES_OFFSET             24
314 #define LRADC_CH_NUM_SAMPLES(x) \
315                                 ((x) << LRADC_CH_NUM_SAMPLES_OFFSET)
316 #define LRADC_CH_VALUE_MASK                     0x3ffff
317 #define LRADC_CH_VALUE_OFFSET                   0
318 
319 #define LRADC_DELAY(n)                          (0xd0 + (0x10 * (n)))
320 #define LRADC_DELAY_TRIGGER_LRADCS_MASK         (0xff << 24)
321 #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET       24
322 #define LRADC_DELAY_TRIGGER(x) \
323                                 (((x) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) & \
324                                 LRADC_DELAY_TRIGGER_LRADCS_MASK)
325 #define LRADC_DELAY_KICK                        (1 << 20)
326 #define LRADC_DELAY_TRIGGER_DELAYS_MASK         (0xf << 16)
327 #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET       16
328 #define LRADC_DELAY_TRIGGER_DELAYS(x) \
329                                 (((x) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) & \
330                                 LRADC_DELAY_TRIGGER_DELAYS_MASK)
331 #define LRADC_DELAY_LOOP_COUNT_MASK             (0x1f << 11)
332 #define LRADC_DELAY_LOOP_COUNT_OFFSET           11
333 #define LRADC_DELAY_LOOP(x) \
334                                 (((x) << LRADC_DELAY_LOOP_COUNT_OFFSET) & \
335                                 LRADC_DELAY_LOOP_COUNT_MASK)
336 #define LRADC_DELAY_DELAY_MASK                  0x7ff
337 #define LRADC_DELAY_DELAY_OFFSET                0
338 #define LRADC_DELAY_DELAY(x) \
339                                 (((x) << LRADC_DELAY_DELAY_OFFSET) & \
340                                 LRADC_DELAY_DELAY_MASK)
341 
342 #define LRADC_CTRL4                             0x140
343 #define LRADC_CTRL4_LRADCSELECT_MASK(n)         (0xf << ((n) * 4))
344 #define LRADC_CTRL4_LRADCSELECT_OFFSET(n)       ((n) * 4)
345 
346 #define LRADC_RESOLUTION                        12
347 #define LRADC_SINGLE_SAMPLE_MASK                ((1 << LRADC_RESOLUTION) - 1)
348 
349 static void mxs_lradc_reg_set(struct mxs_lradc *lradc, u32 val, u32 reg)
350 {
351         writel(val, lradc->base + reg + STMP_OFFSET_REG_SET);
352 }
353 
354 static void mxs_lradc_reg_clear(struct mxs_lradc *lradc, u32 val, u32 reg)
355 {
356         writel(val, lradc->base + reg + STMP_OFFSET_REG_CLR);
357 }
358 
359 static void mxs_lradc_reg_wrt(struct mxs_lradc *lradc, u32 val, u32 reg)
360 {
361         writel(val, lradc->base + reg);
362 }
363 
364 static u32 mxs_lradc_plate_mask(struct mxs_lradc *lradc)
365 {
366         if (lradc->soc == IMX23_LRADC)
367                 return LRADC_CTRL0_MX23_PLATE_MASK;
368         else
369                 return LRADC_CTRL0_MX28_PLATE_MASK;
370 }
371 
372 static u32 mxs_lradc_irq_en_mask(struct mxs_lradc *lradc)
373 {
374         if (lradc->soc == IMX23_LRADC)
375                 return LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK;
376         else
377                 return LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK;
378 }
379 
380 static u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc)
381 {
382         if (lradc->soc == IMX23_LRADC)
383                 return LRADC_CTRL1_MX23_LRADC_IRQ_MASK;
384         else
385                 return LRADC_CTRL1_MX28_LRADC_IRQ_MASK;
386 }
387 
388 static u32 mxs_lradc_touch_detect_bit(struct mxs_lradc *lradc)
389 {
390         if (lradc->soc == IMX23_LRADC)
391                 return LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE;
392         else
393                 return LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE;
394 }
395 
396 static u32 mxs_lradc_drive_x_plate(struct mxs_lradc *lradc)
397 {
398         if (lradc->soc == IMX23_LRADC)
399                 return LRADC_CTRL0_MX23_XP | LRADC_CTRL0_MX23_XM;
400         else
401                 return LRADC_CTRL0_MX28_XPPSW | LRADC_CTRL0_MX28_XNNSW;
402 }
403 
404 static u32 mxs_lradc_drive_y_plate(struct mxs_lradc *lradc)
405 {
406         if (lradc->soc == IMX23_LRADC)
407                 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_YM;
408         else
409                 return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_YNNSW;
410 }
411 
412 static u32 mxs_lradc_drive_pressure(struct mxs_lradc *lradc)
413 {
414         if (lradc->soc == IMX23_LRADC)
415                 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XM;
416         else
417                 return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW;
418 }
419 
420 static bool mxs_lradc_check_touch_event(struct mxs_lradc *lradc)
421 {
422         return !!(readl(lradc->base + LRADC_STATUS) &
423                                         LRADC_STATUS_TOUCH_DETECT_RAW);
424 }
425 
426 static void mxs_lradc_setup_ts_channel(struct mxs_lradc *lradc, unsigned ch)
427 {
428         /*
429          * prepare for oversampling conversion
430          *
431          * from the datasheet:
432          * "The ACCUMULATE bit in the appropriate channel register
433          * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
434          * otherwise, the IRQs will not fire."
435          */
436         mxs_lradc_reg_wrt(lradc, LRADC_CH_ACCUMULATE |
437                         LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1),
438                         LRADC_CH(ch));
439 
440         /* from the datasheet:
441          * "Software must clear this register in preparation for a
442          * multi-cycle accumulation.
443          */
444         mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch));
445 
446         /* prepare the delay/loop unit according to the oversampling count */
447         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch) |
448                 LRADC_DELAY_TRIGGER_DELAYS(0) |
449                 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
450                 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
451                         LRADC_DELAY(3));
452 
453         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(2) |
454                         LRADC_CTRL1_LRADC_IRQ(3) | LRADC_CTRL1_LRADC_IRQ(4) |
455                         LRADC_CTRL1_LRADC_IRQ(5), LRADC_CTRL1);
456 
457         /* wake us again, when the complete conversion is done */
458         mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(ch), LRADC_CTRL1);
459         /*
460          * after changing the touchscreen plates setting
461          * the signals need some initial time to settle. Start the
462          * SoC's delay unit and start the conversion later
463          * and automatically.
464          */
465         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
466                 LRADC_DELAY_TRIGGER_DELAYS(1 << 3) | /* trigger DELAY unit#3 */
467                 LRADC_DELAY_KICK |
468                 LRADC_DELAY_DELAY(lradc->settling_delay),
469                         LRADC_DELAY(2));
470 }
471 
472 /*
473  * Pressure detection is special:
474  * We want to do both required measurements for the pressure detection in
475  * one turn. Use the hardware features to chain both conversions and let the
476  * hardware report one interrupt if both conversions are done
477  */
478 static void mxs_lradc_setup_ts_pressure(struct mxs_lradc *lradc, unsigned ch1,
479                                                         unsigned ch2)
480 {
481         u32 reg;
482 
483         /*
484          * prepare for oversampling conversion
485          *
486          * from the datasheet:
487          * "The ACCUMULATE bit in the appropriate channel register
488          * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
489          * otherwise, the IRQs will not fire."
490          */
491         reg = LRADC_CH_ACCUMULATE |
492                 LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1);
493         mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch1));
494         mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch2));
495 
496         /* from the datasheet:
497          * "Software must clear this register in preparation for a
498          * multi-cycle accumulation.
499          */
500         mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch1));
501         mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch2));
502 
503         /* prepare the delay/loop unit according to the oversampling count */
504         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch1) |
505                 LRADC_DELAY_TRIGGER(1 << ch2) | /* start both channels */
506                 LRADC_DELAY_TRIGGER_DELAYS(0) |
507                 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
508                 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
509                                         LRADC_DELAY(3));
510 
511         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(2) |
512                         LRADC_CTRL1_LRADC_IRQ(3) | LRADC_CTRL1_LRADC_IRQ(4) |
513                         LRADC_CTRL1_LRADC_IRQ(5), LRADC_CTRL1);
514 
515         /* wake us again, when the conversions are done */
516         mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(ch2), LRADC_CTRL1);
517         /*
518          * after changing the touchscreen plates setting
519          * the signals need some initial time to settle. Start the
520          * SoC's delay unit and start the conversion later
521          * and automatically.
522          */
523         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
524                 LRADC_DELAY_TRIGGER_DELAYS(1 << 3) | /* trigger DELAY unit#3 */
525                 LRADC_DELAY_KICK |
526                 LRADC_DELAY_DELAY(lradc->settling_delay), LRADC_DELAY(2));
527 }
528 
529 static unsigned mxs_lradc_read_raw_channel(struct mxs_lradc *lradc,
530                                                         unsigned channel)
531 {
532         u32 reg;
533         unsigned num_samples, val;
534 
535         reg = readl(lradc->base + LRADC_CH(channel));
536         if (reg & LRADC_CH_ACCUMULATE)
537                 num_samples = lradc->over_sample_cnt;
538         else
539                 num_samples = 1;
540 
541         val = (reg & LRADC_CH_VALUE_MASK) >> LRADC_CH_VALUE_OFFSET;
542         return val / num_samples;
543 }
544 
545 static unsigned mxs_lradc_read_ts_pressure(struct mxs_lradc *lradc,
546                                                 unsigned ch1, unsigned ch2)
547 {
548         u32 reg, mask;
549         unsigned pressure, m1, m2;
550 
551         mask = LRADC_CTRL1_LRADC_IRQ(ch1) | LRADC_CTRL1_LRADC_IRQ(ch2);
552         reg = readl(lradc->base + LRADC_CTRL1) & mask;
553 
554         while (reg != mask) {
555                 reg = readl(lradc->base + LRADC_CTRL1) & mask;
556                 dev_dbg(lradc->dev, "One channel is still busy: %X\n", reg);
557         }
558 
559         m1 = mxs_lradc_read_raw_channel(lradc, ch1);
560         m2 = mxs_lradc_read_raw_channel(lradc, ch2);
561 
562         if (m2 == 0) {
563                 dev_warn(lradc->dev, "Cannot calculate pressure\n");
564                 return 1 << (LRADC_RESOLUTION - 1);
565         }
566 
567         /* simply scale the value from 0 ... max ADC resolution */
568         pressure = m1;
569         pressure *= (1 << LRADC_RESOLUTION);
570         pressure /= m2;
571 
572         dev_dbg(lradc->dev, "Pressure = %u\n", pressure);
573         return pressure;
574 }
575 
576 #define TS_CH_XP 2
577 #define TS_CH_YP 3
578 #define TS_CH_XM 4
579 #define TS_CH_YM 5
580 
581 static int mxs_lradc_read_ts_channel(struct mxs_lradc *lradc)
582 {
583         u32 reg;
584         int val;
585 
586         reg = readl(lradc->base + LRADC_CTRL1);
587 
588         /* only channels 3 to 5 are of interest here */
589         if (reg & LRADC_CTRL1_LRADC_IRQ(TS_CH_YP)) {
590                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(TS_CH_YP) |
591                         LRADC_CTRL1_LRADC_IRQ(TS_CH_YP), LRADC_CTRL1);
592                 val = mxs_lradc_read_raw_channel(lradc, TS_CH_YP);
593         } else if (reg & LRADC_CTRL1_LRADC_IRQ(TS_CH_XM)) {
594                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(TS_CH_XM) |
595                         LRADC_CTRL1_LRADC_IRQ(TS_CH_XM), LRADC_CTRL1);
596                 val = mxs_lradc_read_raw_channel(lradc, TS_CH_XM);
597         } else if (reg & LRADC_CTRL1_LRADC_IRQ(TS_CH_YM)) {
598                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(TS_CH_YM) |
599                         LRADC_CTRL1_LRADC_IRQ(TS_CH_YM), LRADC_CTRL1);
600                 val = mxs_lradc_read_raw_channel(lradc, TS_CH_YM);
601         } else {
602                 return -EIO;
603         }
604 
605         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
606         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
607 
608         return val;
609 }
610 
611 /*
612  * YP(open)--+-------------+
613  *           |             |--+
614  *           |             |  |
615  *    YM(-)--+-------------+  |
616  *             +--------------+
617  *             |              |
618  *         XP(weak+)        XM(open)
619  *
620  * "weak+" means 200k Ohm VDDIO
621  * (-) means GND
622  */
623 static void mxs_lradc_setup_touch_detection(struct mxs_lradc *lradc)
624 {
625         /*
626          * In order to detect a touch event the 'touch detect enable' bit
627          * enables:
628          *  - a weak pullup to the X+ connector
629          *  - a strong ground at the Y- connector
630          */
631         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
632         mxs_lradc_reg_set(lradc, mxs_lradc_touch_detect_bit(lradc),
633                                 LRADC_CTRL0);
634 }
635 
636 /*
637  * YP(meas)--+-------------+
638  *           |             |--+
639  *           |             |  |
640  * YM(open)--+-------------+  |
641  *             +--------------+
642  *             |              |
643  *           XP(+)          XM(-)
644  *
645  * (+) means here 1.85 V
646  * (-) means here GND
647  */
648 static void mxs_lradc_prepare_x_pos(struct mxs_lradc *lradc)
649 {
650         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
651         mxs_lradc_reg_set(lradc, mxs_lradc_drive_x_plate(lradc), LRADC_CTRL0);
652 
653         lradc->cur_plate = LRADC_SAMPLE_X;
654         mxs_lradc_setup_ts_channel(lradc, TS_CH_YP);
655 }
656 
657 /*
658  *   YP(+)--+-------------+
659  *          |             |--+
660  *          |             |  |
661  *   YM(-)--+-------------+  |
662  *            +--------------+
663  *            |              |
664  *         XP(open)        XM(meas)
665  *
666  * (+) means here 1.85 V
667  * (-) means here GND
668  */
669 static void mxs_lradc_prepare_y_pos(struct mxs_lradc *lradc)
670 {
671         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
672         mxs_lradc_reg_set(lradc, mxs_lradc_drive_y_plate(lradc), LRADC_CTRL0);
673 
674         lradc->cur_plate = LRADC_SAMPLE_Y;
675         mxs_lradc_setup_ts_channel(lradc, TS_CH_XM);
676 }
677 
678 /*
679  *    YP(+)--+-------------+
680  *           |             |--+
681  *           |             |  |
682  * YM(meas)--+-------------+  |
683  *             +--------------+
684  *             |              |
685  *          XP(meas)        XM(-)
686  *
687  * (+) means here 1.85 V
688  * (-) means here GND
689  */
690 static void mxs_lradc_prepare_pressure(struct mxs_lradc *lradc)
691 {
692         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
693         mxs_lradc_reg_set(lradc, mxs_lradc_drive_pressure(lradc), LRADC_CTRL0);
694 
695         lradc->cur_plate = LRADC_SAMPLE_PRESSURE;
696         mxs_lradc_setup_ts_pressure(lradc, TS_CH_XP, TS_CH_YM);
697 }
698 
699 static void mxs_lradc_enable_touch_detection(struct mxs_lradc *lradc)
700 {
701         mxs_lradc_setup_touch_detection(lradc);
702 
703         lradc->cur_plate = LRADC_TOUCH;
704         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ |
705                                 LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
706         mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
707 }
708 
709 static void mxs_lradc_report_ts_event(struct mxs_lradc *lradc)
710 {
711         input_report_abs(lradc->ts_input, ABS_X, lradc->ts_x_pos);
712         input_report_abs(lradc->ts_input, ABS_Y, lradc->ts_y_pos);
713         input_report_abs(lradc->ts_input, ABS_PRESSURE, lradc->ts_pressure);
714         input_report_key(lradc->ts_input, BTN_TOUCH, 1);
715         input_sync(lradc->ts_input);
716 }
717 
718 static void mxs_lradc_complete_touch_event(struct mxs_lradc *lradc)
719 {
720         mxs_lradc_setup_touch_detection(lradc);
721         lradc->cur_plate = LRADC_SAMPLE_VALID;
722         /*
723          * start a dummy conversion to burn time to settle the signals
724          * note: we are not interested in the conversion's value
725          */
726         mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(5));
727         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(5), LRADC_CTRL1);
728         mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(5), LRADC_CTRL1);
729         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << 5) |
730                 LRADC_DELAY_KICK | LRADC_DELAY_DELAY(10), /* waste 5 ms */
731                         LRADC_DELAY(2));
732 }
733 
734 /*
735  * in order to avoid false measurements, report only samples where
736  * the surface is still touched after the position measurement
737  */
738 static void mxs_lradc_finish_touch_event(struct mxs_lradc *lradc, bool valid)
739 {
740         /* if it is still touched, report the sample */
741         if (valid && mxs_lradc_check_touch_event(lradc)) {
742                 lradc->ts_valid = true;
743                 mxs_lradc_report_ts_event(lradc);
744         }
745 
746         /* if it is even still touched, continue with the next measurement */
747         if (mxs_lradc_check_touch_event(lradc)) {
748                 mxs_lradc_prepare_y_pos(lradc);
749                 return;
750         }
751 
752         if (lradc->ts_valid) {
753                 /* signal the release */
754                 lradc->ts_valid = false;
755                 input_report_key(lradc->ts_input, BTN_TOUCH, 0);
756                 input_sync(lradc->ts_input);
757         }
758 
759         /* if it is released, wait for the next touch via IRQ */
760         lradc->cur_plate = LRADC_TOUCH;
761         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ, LRADC_CTRL1);
762         mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
763 }
764 
765 /* touchscreen's state machine */
766 static void mxs_lradc_handle_touch(struct mxs_lradc *lradc)
767 {
768         int val;
769 
770         switch (lradc->cur_plate) {
771         case LRADC_TOUCH:
772                 /*
773                  * start with the Y-pos, because it uses nearly the same plate
774                  * settings like the touch detection
775                  */
776                 if (mxs_lradc_check_touch_event(lradc)) {
777                         mxs_lradc_reg_clear(lradc,
778                                         LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
779                                         LRADC_CTRL1);
780                         mxs_lradc_prepare_y_pos(lradc);
781                 }
782                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ,
783                                         LRADC_CTRL1);
784                 return;
785 
786         case LRADC_SAMPLE_Y:
787                 val = mxs_lradc_read_ts_channel(lradc);
788                 if (val < 0) {
789                         mxs_lradc_enable_touch_detection(lradc); /* re-start */
790                         return;
791                 }
792                 lradc->ts_y_pos = val;
793                 mxs_lradc_prepare_x_pos(lradc);
794                 return;
795 
796         case LRADC_SAMPLE_X:
797                 val = mxs_lradc_read_ts_channel(lradc);
798                 if (val < 0) {
799                         mxs_lradc_enable_touch_detection(lradc); /* re-start */
800                         return;
801                 }
802                 lradc->ts_x_pos = val;
803                 mxs_lradc_prepare_pressure(lradc);
804                 return;
805 
806         case LRADC_SAMPLE_PRESSURE:
807                 lradc->ts_pressure =
808                         mxs_lradc_read_ts_pressure(lradc, TS_CH_XP, TS_CH_YM);
809                 mxs_lradc_complete_touch_event(lradc);
810                 return;
811 
812         case LRADC_SAMPLE_VALID:
813                 val = mxs_lradc_read_ts_channel(lradc); /* ignore the value */
814                 mxs_lradc_finish_touch_event(lradc, 1);
815                 break;
816         }
817 }
818 
819 /*
820  * Raw I/O operations
821  */
822 static int mxs_lradc_read_single(struct iio_dev *iio_dev, int chan, int *val)
823 {
824         struct mxs_lradc *lradc = iio_priv(iio_dev);
825         int ret;
826 
827         /*
828          * See if there is no buffered operation in progess. If there is, simply
829          * bail out. This can be improved to support both buffered and raw IO at
830          * the same time, yet the code becomes horribly complicated. Therefore I
831          * applied KISS principle here.
832          */
833         ret = mutex_trylock(&lradc->lock);
834         if (!ret)
835                 return -EBUSY;
836 
837         reinit_completion(&lradc->completion);
838 
839         /*
840          * No buffered operation in progress, map the channel and trigger it.
841          * Virtual channel 0 is always used here as the others are always not
842          * used if doing raw sampling.
843          */
844         if (lradc->soc == IMX28_LRADC)
845                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
846                         LRADC_CTRL1);
847         mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
848 
849         /* Enable / disable the divider per requirement */
850         if (test_bit(chan, &lradc->is_divided))
851                 mxs_lradc_reg_set(lradc, 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
852                         LRADC_CTRL2);
853         else
854                 mxs_lradc_reg_clear(lradc,
855                         1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, LRADC_CTRL2);
856 
857         /* Clean the slot's previous content, then set new one. */
858         mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0),
859                         LRADC_CTRL4);
860         mxs_lradc_reg_set(lradc, chan, LRADC_CTRL4);
861 
862         mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(0));
863 
864         /* Enable the IRQ and start sampling the channel. */
865         mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
866         mxs_lradc_reg_set(lradc, 1 << 0, LRADC_CTRL0);
867 
868         /* Wait for completion on the channel, 1 second max. */
869         ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
870         if (!ret)
871                 ret = -ETIMEDOUT;
872         if (ret < 0)
873                 goto err;
874 
875         /* Read the data. */
876         *val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
877         ret = IIO_VAL_INT;
878 
879 err:
880         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
881 
882         mutex_unlock(&lradc->lock);
883 
884         return ret;
885 }
886 
887 static int mxs_lradc_read_temp(struct iio_dev *iio_dev, int *val)
888 {
889         int ret, min, max;
890 
891         ret = mxs_lradc_read_single(iio_dev, 8, &min);
892         if (ret != IIO_VAL_INT)
893                 return ret;
894 
895         ret = mxs_lradc_read_single(iio_dev, 9, &max);
896         if (ret != IIO_VAL_INT)
897                 return ret;
898 
899         *val = max - min;
900 
901         return IIO_VAL_INT;
902 }
903 
904 static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
905                         const struct iio_chan_spec *chan,
906                         int *val, int *val2, long m)
907 {
908         struct mxs_lradc *lradc = iio_priv(iio_dev);
909 
910         switch (m) {
911         case IIO_CHAN_INFO_RAW:
912                 if (chan->type == IIO_TEMP)
913                         return mxs_lradc_read_temp(iio_dev, val);
914 
915                 return mxs_lradc_read_single(iio_dev, chan->channel, val);
916 
917         case IIO_CHAN_INFO_SCALE:
918                 if (chan->type == IIO_TEMP) {
919                         /* From the datasheet, we have to multiply by 1.012 and
920                          * divide by 4
921                          */
922                         *val = 0;
923                         *val2 = 253000;
924                         return IIO_VAL_INT_PLUS_MICRO;
925                 }
926 
927                 *val = lradc->vref_mv[chan->channel];
928                 *val2 = chan->scan_type.realbits -
929                         test_bit(chan->channel, &lradc->is_divided);
930                 return IIO_VAL_FRACTIONAL_LOG2;
931 
932         case IIO_CHAN_INFO_OFFSET:
933                 if (chan->type == IIO_TEMP) {
934                         /* The calculated value from the ADC is in Kelvin, we
935                          * want Celsius for hwmon so the offset is
936                          * -272.15 * scale
937                          */
938                         *val = -1075;
939                         *val2 = 691699;
940 
941                         return IIO_VAL_INT_PLUS_MICRO;
942                 }
943 
944                 return -EINVAL;
945 
946         default:
947                 break;
948         }
949 
950         return -EINVAL;
951 }
952 
953 static int mxs_lradc_write_raw(struct iio_dev *iio_dev,
954                                const struct iio_chan_spec *chan,
955                                int val, int val2, long m)
956 {
957         struct mxs_lradc *lradc = iio_priv(iio_dev);
958         struct mxs_lradc_scale *scale_avail =
959                         lradc->scale_avail[chan->channel];
960         int ret;
961 
962         ret = mutex_trylock(&lradc->lock);
963         if (!ret)
964                 return -EBUSY;
965 
966         switch (m) {
967         case IIO_CHAN_INFO_SCALE:
968                 ret = -EINVAL;
969                 if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
970                     val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
971                         /* divider by two disabled */
972                         clear_bit(chan->channel, &lradc->is_divided);
973                         ret = 0;
974                 } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
975                            val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
976                         /* divider by two enabled */
977                         set_bit(chan->channel, &lradc->is_divided);
978                         ret = 0;
979                 }
980 
981                 break;
982         default:
983                 ret = -EINVAL;
984                 break;
985         }
986 
987         mutex_unlock(&lradc->lock);
988 
989         return ret;
990 }
991 
992 static int mxs_lradc_write_raw_get_fmt(struct iio_dev *iio_dev,
993                                        const struct iio_chan_spec *chan,
994                                        long m)
995 {
996         return IIO_VAL_INT_PLUS_NANO;
997 }
998 
999 static ssize_t mxs_lradc_show_scale_available_ch(struct device *dev,
1000                 struct device_attribute *attr,
1001                 char *buf,
1002                 int ch)
1003 {
1004         struct iio_dev *iio = dev_to_iio_dev(dev);
1005         struct mxs_lradc *lradc = iio_priv(iio);
1006         int i, len = 0;
1007 
1008         for (i = 0; i < ARRAY_SIZE(lradc->scale_avail[ch]); i++)
1009                 len += sprintf(buf + len, "%d.%09u ",
1010                                lradc->scale_avail[ch][i].integer,
1011                                lradc->scale_avail[ch][i].nano);
1012 
1013         len += sprintf(buf + len, "\n");
1014 
1015         return len;
1016 }
1017 
1018 static ssize_t mxs_lradc_show_scale_available(struct device *dev,
1019                 struct device_attribute *attr,
1020                 char *buf)
1021 {
1022         struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
1023 
1024         return mxs_lradc_show_scale_available_ch(dev, attr, buf,
1025                                                  iio_attr->address);
1026 }
1027 
1028 #define SHOW_SCALE_AVAILABLE_ATTR(ch)                                   \
1029 static IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, S_IRUGO,       \
1030                        mxs_lradc_show_scale_available, NULL, ch)
1031 
1032 SHOW_SCALE_AVAILABLE_ATTR(0);
1033 SHOW_SCALE_AVAILABLE_ATTR(1);
1034 SHOW_SCALE_AVAILABLE_ATTR(2);
1035 SHOW_SCALE_AVAILABLE_ATTR(3);
1036 SHOW_SCALE_AVAILABLE_ATTR(4);
1037 SHOW_SCALE_AVAILABLE_ATTR(5);
1038 SHOW_SCALE_AVAILABLE_ATTR(6);
1039 SHOW_SCALE_AVAILABLE_ATTR(7);
1040 SHOW_SCALE_AVAILABLE_ATTR(10);
1041 SHOW_SCALE_AVAILABLE_ATTR(11);
1042 SHOW_SCALE_AVAILABLE_ATTR(12);
1043 SHOW_SCALE_AVAILABLE_ATTR(13);
1044 SHOW_SCALE_AVAILABLE_ATTR(14);
1045 SHOW_SCALE_AVAILABLE_ATTR(15);
1046 
1047 static struct attribute *mxs_lradc_attributes[] = {
1048         &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
1049         &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
1050         &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
1051         &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
1052         &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
1053         &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
1054         &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
1055         &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
1056         &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
1057         &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
1058         &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
1059         &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
1060         &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
1061         &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
1062         NULL
1063 };
1064 
1065 static const struct attribute_group mxs_lradc_attribute_group = {
1066         .attrs = mxs_lradc_attributes,
1067 };
1068 
1069 static const struct iio_info mxs_lradc_iio_info = {
1070         .driver_module          = THIS_MODULE,
1071         .read_raw               = mxs_lradc_read_raw,
1072         .write_raw              = mxs_lradc_write_raw,
1073         .write_raw_get_fmt      = mxs_lradc_write_raw_get_fmt,
1074         .attrs                  = &mxs_lradc_attribute_group,
1075 };
1076 
1077 static int mxs_lradc_ts_open(struct input_dev *dev)
1078 {
1079         struct mxs_lradc *lradc = input_get_drvdata(dev);
1080 
1081         /* Enable the touch-detect circuitry. */
1082         mxs_lradc_enable_touch_detection(lradc);
1083 
1084         return 0;
1085 }
1086 
1087 static void mxs_lradc_disable_ts(struct mxs_lradc *lradc)
1088 {
1089         /* stop all interrupts from firing */
1090         mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN |
1091                 LRADC_CTRL1_LRADC_IRQ_EN(2) | LRADC_CTRL1_LRADC_IRQ_EN(3) |
1092                 LRADC_CTRL1_LRADC_IRQ_EN(4) | LRADC_CTRL1_LRADC_IRQ_EN(5),
1093                 LRADC_CTRL1);
1094 
1095         /* Power-down touchscreen touch-detect circuitry. */
1096         mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
1097 }
1098 
1099 static void mxs_lradc_ts_close(struct input_dev *dev)
1100 {
1101         struct mxs_lradc *lradc = input_get_drvdata(dev);
1102 
1103         mxs_lradc_disable_ts(lradc);
1104 }
1105 
1106 static int mxs_lradc_ts_register(struct mxs_lradc *lradc)
1107 {
1108         struct input_dev *input;
1109         struct device *dev = lradc->dev;
1110         int ret;
1111 
1112         if (!lradc->use_touchscreen)
1113                 return 0;
1114 
1115         input = input_allocate_device();
1116         if (!input)
1117                 return -ENOMEM;
1118 
1119         input->name = DRIVER_NAME;
1120         input->id.bustype = BUS_HOST;
1121         input->dev.parent = dev;
1122         input->open = mxs_lradc_ts_open;
1123         input->close = mxs_lradc_ts_close;
1124 
1125         __set_bit(EV_ABS, input->evbit);
1126         __set_bit(EV_KEY, input->evbit);
1127         __set_bit(BTN_TOUCH, input->keybit);
1128         input_set_abs_params(input, ABS_X, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1129         input_set_abs_params(input, ABS_Y, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1130         input_set_abs_params(input, ABS_PRESSURE, 0, LRADC_SINGLE_SAMPLE_MASK,
1131                              0, 0);
1132 
1133         lradc->ts_input = input;
1134         input_set_drvdata(input, lradc);
1135         ret = input_register_device(input);
1136         if (ret)
1137                 input_free_device(lradc->ts_input);
1138 
1139         return ret;
1140 }
1141 
1142 static void mxs_lradc_ts_unregister(struct mxs_lradc *lradc)
1143 {
1144         if (!lradc->use_touchscreen)
1145                 return;
1146 
1147         mxs_lradc_disable_ts(lradc);
1148         input_unregister_device(lradc->ts_input);
1149 }
1150 
1151 /*
1152  * IRQ Handling
1153  */
1154 static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
1155 {
1156         struct iio_dev *iio = data;
1157         struct mxs_lradc *lradc = iio_priv(iio);
1158         unsigned long reg = readl(lradc->base + LRADC_CTRL1);
1159         const uint32_t ts_irq_mask =
1160                 LRADC_CTRL1_TOUCH_DETECT_IRQ |
1161                 LRADC_CTRL1_LRADC_IRQ(2) |
1162                 LRADC_CTRL1_LRADC_IRQ(3) |
1163                 LRADC_CTRL1_LRADC_IRQ(4) |
1164                 LRADC_CTRL1_LRADC_IRQ(5);
1165 
1166         if (!(reg & mxs_lradc_irq_mask(lradc)))
1167                 return IRQ_NONE;
1168 
1169         if (lradc->use_touchscreen && (reg & ts_irq_mask))
1170                 mxs_lradc_handle_touch(lradc);
1171 
1172         if (iio_buffer_enabled(iio))
1173                 iio_trigger_poll(iio->trig);
1174         else if (reg & LRADC_CTRL1_LRADC_IRQ(0))
1175                 complete(&lradc->completion);
1176 
1177         mxs_lradc_reg_clear(lradc, reg & mxs_lradc_irq_mask(lradc),
1178                         LRADC_CTRL1);
1179 
1180         return IRQ_HANDLED;
1181 }
1182 
1183 /*
1184  * Trigger handling
1185  */
1186 static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
1187 {
1188         struct iio_poll_func *pf = p;
1189         struct iio_dev *iio = pf->indio_dev;
1190         struct mxs_lradc *lradc = iio_priv(iio);
1191         const uint32_t chan_value = LRADC_CH_ACCUMULATE |
1192                 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1193         unsigned int i, j = 0;
1194 
1195         for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1196                 lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
1197                 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(j));
1198                 lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
1199                 lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
1200                 j++;
1201         }
1202 
1203         iio_push_to_buffers_with_timestamp(iio, lradc->buffer, pf->timestamp);
1204 
1205         iio_trigger_notify_done(iio->trig);
1206 
1207         return IRQ_HANDLED;
1208 }
1209 
1210 static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
1211 {
1212         struct iio_dev *iio = iio_trigger_get_drvdata(trig);
1213         struct mxs_lradc *lradc = iio_priv(iio);
1214         const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
1215 
1216         mxs_lradc_reg_wrt(lradc, LRADC_DELAY_KICK, LRADC_DELAY(0) + st);
1217 
1218         return 0;
1219 }
1220 
1221 static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
1222         .owner = THIS_MODULE,
1223         .set_trigger_state = &mxs_lradc_configure_trigger,
1224 };
1225 
1226 static int mxs_lradc_trigger_init(struct iio_dev *iio)
1227 {
1228         int ret;
1229         struct iio_trigger *trig;
1230         struct mxs_lradc *lradc = iio_priv(iio);
1231 
1232         trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
1233         if (trig == NULL)
1234                 return -ENOMEM;
1235 
1236         trig->dev.parent = lradc->dev;
1237         iio_trigger_set_drvdata(trig, iio);
1238         trig->ops = &mxs_lradc_trigger_ops;
1239 
1240         ret = iio_trigger_register(trig);
1241         if (ret) {
1242                 iio_trigger_free(trig);
1243                 return ret;
1244         }
1245 
1246         lradc->trig = trig;
1247 
1248         return 0;
1249 }
1250 
1251 static void mxs_lradc_trigger_remove(struct iio_dev *iio)
1252 {
1253         struct mxs_lradc *lradc = iio_priv(iio);
1254 
1255         iio_trigger_unregister(lradc->trig);
1256         iio_trigger_free(lradc->trig);
1257 }
1258 
1259 static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
1260 {
1261         struct mxs_lradc *lradc = iio_priv(iio);
1262         int ret = 0, chan, ofs = 0;
1263         unsigned long enable = 0;
1264         uint32_t ctrl4_set = 0;
1265         uint32_t ctrl4_clr = 0;
1266         uint32_t ctrl1_irq = 0;
1267         const uint32_t chan_value = LRADC_CH_ACCUMULATE |
1268                 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1269         const int len = bitmap_weight(iio->active_scan_mask,
1270                         LRADC_MAX_TOTAL_CHANS);
1271 
1272         if (!len)
1273                 return -EINVAL;
1274 
1275         /*
1276          * Lock the driver so raw access can not be done during buffered
1277          * operation. This simplifies the code a lot.
1278          */
1279         ret = mutex_trylock(&lradc->lock);
1280         if (!ret)
1281                 return -EBUSY;
1282 
1283         lradc->buffer = kmalloc(len * sizeof(*lradc->buffer), GFP_KERNEL);
1284         if (!lradc->buffer) {
1285                 ret = -ENOMEM;
1286                 goto err_mem;
1287         }
1288 
1289         if (lradc->soc == IMX28_LRADC)
1290                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
1291                                                         LRADC_CTRL1);
1292         mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
1293 
1294         for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1295                 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
1296                 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
1297                 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
1298                 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(ofs));
1299                 bitmap_set(&enable, ofs, 1);
1300                 ofs++;
1301         }
1302 
1303         mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1304                                         LRADC_DELAY_KICK, LRADC_DELAY(0));
1305         mxs_lradc_reg_clear(lradc, ctrl4_clr, LRADC_CTRL4);
1306         mxs_lradc_reg_set(lradc, ctrl4_set, LRADC_CTRL4);
1307         mxs_lradc_reg_set(lradc, ctrl1_irq, LRADC_CTRL1);
1308         mxs_lradc_reg_set(lradc, enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
1309                                         LRADC_DELAY(0));
1310 
1311         return 0;
1312 
1313 err_mem:
1314         mutex_unlock(&lradc->lock);
1315         return ret;
1316 }
1317 
1318 static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
1319 {
1320         struct mxs_lradc *lradc = iio_priv(iio);
1321 
1322         mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1323                                         LRADC_DELAY_KICK, LRADC_DELAY(0));
1324 
1325         mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
1326         if (lradc->soc == IMX28_LRADC)
1327                 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
1328                                         LRADC_CTRL1);
1329 
1330         kfree(lradc->buffer);
1331         mutex_unlock(&lradc->lock);
1332 
1333         return 0;
1334 }
1335 
1336 static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
1337                                         const unsigned long *mask)
1338 {
1339         struct mxs_lradc *lradc = iio_priv(iio);
1340         const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
1341         int rsvd_chans = 0;
1342         unsigned long rsvd_mask = 0;
1343 
1344         if (lradc->use_touchbutton)
1345                 rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
1346         if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_4WIRE)
1347                 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
1348         if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1349                 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
1350 
1351         if (lradc->use_touchbutton)
1352                 rsvd_chans++;
1353         if (lradc->use_touchscreen)
1354                 rsvd_chans++;
1355 
1356         /* Test for attempts to map channels with special mode of operation. */
1357         if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
1358                 return false;
1359 
1360         /* Test for attempts to map more channels then available slots. */
1361         if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
1362                 return false;
1363 
1364         return true;
1365 }
1366 
1367 static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
1368         .preenable = &mxs_lradc_buffer_preenable,
1369         .postenable = &iio_triggered_buffer_postenable,
1370         .predisable = &iio_triggered_buffer_predisable,
1371         .postdisable = &mxs_lradc_buffer_postdisable,
1372         .validate_scan_mask = &mxs_lradc_validate_scan_mask,
1373 };
1374 
1375 /*
1376  * Driver initialization
1377  */
1378 
1379 #define MXS_ADC_CHAN(idx, chan_type) {                          \
1380         .type = (chan_type),                                    \
1381         .indexed = 1,                                           \
1382         .scan_index = (idx),                                    \
1383         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
1384                               BIT(IIO_CHAN_INFO_SCALE),         \
1385         .channel = (idx),                                       \
1386         .address = (idx),                                       \
1387         .scan_type = {                                          \
1388                 .sign = 'u',                                    \
1389                 .realbits = LRADC_RESOLUTION,                   \
1390                 .storagebits = 32,                              \
1391         },                                                      \
1392 }
1393 
1394 static const struct iio_chan_spec mxs_lradc_chan_spec[] = {
1395         MXS_ADC_CHAN(0, IIO_VOLTAGE),
1396         MXS_ADC_CHAN(1, IIO_VOLTAGE),
1397         MXS_ADC_CHAN(2, IIO_VOLTAGE),
1398         MXS_ADC_CHAN(3, IIO_VOLTAGE),
1399         MXS_ADC_CHAN(4, IIO_VOLTAGE),
1400         MXS_ADC_CHAN(5, IIO_VOLTAGE),
1401         MXS_ADC_CHAN(6, IIO_VOLTAGE),
1402         MXS_ADC_CHAN(7, IIO_VOLTAGE),   /* VBATT */
1403         /* Combined Temperature sensors */
1404         {
1405                 .type = IIO_TEMP,
1406                 .indexed = 1,
1407                 .scan_index = 8,
1408                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1409                                       BIT(IIO_CHAN_INFO_OFFSET) |
1410                                       BIT(IIO_CHAN_INFO_SCALE),
1411                 .channel = 8,
1412                 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
1413         },
1414         MXS_ADC_CHAN(10, IIO_VOLTAGE),  /* VDDIO */
1415         MXS_ADC_CHAN(11, IIO_VOLTAGE),  /* VTH */
1416         MXS_ADC_CHAN(12, IIO_VOLTAGE),  /* VDDA */
1417         MXS_ADC_CHAN(13, IIO_VOLTAGE),  /* VDDD */
1418         MXS_ADC_CHAN(14, IIO_VOLTAGE),  /* VBG */
1419         MXS_ADC_CHAN(15, IIO_VOLTAGE),  /* VDD5V */
1420 };
1421 
1422 static int mxs_lradc_hw_init(struct mxs_lradc *lradc)
1423 {
1424         /* The ADC always uses DELAY CHANNEL 0. */
1425         const uint32_t adc_cfg =
1426                 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
1427                 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
1428 
1429         int ret = stmp_reset_block(lradc->base);
1430         if (ret)
1431                 return ret;
1432 
1433         /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
1434         mxs_lradc_reg_wrt(lradc, adc_cfg, LRADC_DELAY(0));
1435 
1436         /* Disable remaining DELAY CHANNELs */
1437         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(1));
1438         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
1439         mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
1440 
1441         /* Configure the touchscreen type */
1442         if (lradc->soc == IMX28_LRADC) {
1443                 mxs_lradc_reg_clear(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
1444                                                         LRADC_CTRL0);
1445 
1446         if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1447                 mxs_lradc_reg_set(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
1448                                 LRADC_CTRL0);
1449         }
1450 
1451         /* Start internal temperature sensing. */
1452         mxs_lradc_reg_wrt(lradc, 0, LRADC_CTRL2);
1453 
1454         return 0;
1455 }
1456 
1457 static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
1458 {
1459         int i;
1460 
1461         mxs_lradc_reg_clear(lradc, mxs_lradc_irq_en_mask(lradc), LRADC_CTRL1);
1462 
1463         for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
1464                 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(i));
1465 }
1466 
1467 static const struct of_device_id mxs_lradc_dt_ids[] = {
1468         { .compatible = "fsl,imx23-lradc", .data = (void *)IMX23_LRADC, },
1469         { .compatible = "fsl,imx28-lradc", .data = (void *)IMX28_LRADC, },
1470         { /* sentinel */ }
1471 };
1472 MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
1473 
1474 static int mxs_lradc_probe_touchscreen(struct mxs_lradc *lradc,
1475                                                 struct device_node *lradc_node)
1476 {
1477         int ret;
1478         u32 ts_wires = 0, adapt;
1479 
1480         ret = of_property_read_u32(lradc_node, "fsl,lradc-touchscreen-wires",
1481                                 &ts_wires);
1482         if (ret)
1483                 return -ENODEV; /* touchscreen feature disabled */
1484 
1485         switch (ts_wires) {
1486         case 4:
1487                 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_4WIRE;
1488                 break;
1489         case 5:
1490                 if (lradc->soc == IMX28_LRADC) {
1491                         lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_5WIRE;
1492                         break;
1493                 }
1494                 /* fall through an error message for i.MX23 */
1495         default:
1496                 dev_err(lradc->dev,
1497                         "Unsupported number of touchscreen wires (%d)\n",
1498                         ts_wires);
1499                 return -EINVAL;
1500         }
1501 
1502         lradc->over_sample_cnt = 4;
1503         ret = of_property_read_u32(lradc_node, "fsl,ave-ctrl", &adapt);
1504         if (ret == 0)
1505                 lradc->over_sample_cnt = adapt;
1506 
1507         lradc->over_sample_delay = 2;
1508         ret = of_property_read_u32(lradc_node, "fsl,ave-delay", &adapt);
1509         if (ret == 0)
1510                 lradc->over_sample_delay = adapt;
1511 
1512         lradc->settling_delay = 10;
1513         ret = of_property_read_u32(lradc_node, "fsl,settling", &adapt);
1514         if (ret == 0)
1515                 lradc->settling_delay = adapt;
1516 
1517         return 0;
1518 }
1519 
1520 static int mxs_lradc_probe(struct platform_device *pdev)
1521 {
1522         const struct of_device_id *of_id =
1523                 of_match_device(mxs_lradc_dt_ids, &pdev->dev);
1524         const struct mxs_lradc_of_config *of_cfg =
1525                 &mxs_lradc_of_config[(enum mxs_lradc_id)of_id->data];
1526         struct device *dev = &pdev->dev;
1527         struct device_node *node = dev->of_node;
1528         struct mxs_lradc *lradc;
1529         struct iio_dev *iio;
1530         struct resource *iores;
1531         int ret = 0, touch_ret;
1532         int i, s;
1533         uint64_t scale_uv;
1534 
1535         /* Allocate the IIO device. */
1536         iio = devm_iio_device_alloc(dev, sizeof(*lradc));
1537         if (!iio) {
1538                 dev_err(dev, "Failed to allocate IIO device\n");
1539                 return -ENOMEM;
1540         }
1541 
1542         lradc = iio_priv(iio);
1543         lradc->soc = (enum mxs_lradc_id)of_id->data;
1544 
1545         /* Grab the memory area */
1546         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1547         lradc->dev = &pdev->dev;
1548         lradc->base = devm_ioremap_resource(dev, iores);
1549         if (IS_ERR(lradc->base))
1550                 return PTR_ERR(lradc->base);
1551 
1552         lradc->clk = devm_clk_get(&pdev->dev, NULL);
1553         if (IS_ERR(lradc->clk)) {
1554                 dev_err(dev, "Failed to get the delay unit clock\n");
1555                 return PTR_ERR(lradc->clk);
1556         }
1557         ret = clk_prepare_enable(lradc->clk);
1558         if (ret != 0) {
1559                 dev_err(dev, "Failed to enable the delay unit clock\n");
1560                 return ret;
1561         }
1562 
1563         touch_ret = mxs_lradc_probe_touchscreen(lradc, node);
1564 
1565         /* Grab all IRQ sources */
1566         for (i = 0; i < of_cfg->irq_count; i++) {
1567                 lradc->irq[i] = platform_get_irq(pdev, i);
1568                 if (lradc->irq[i] < 0)
1569                         return lradc->irq[i];
1570 
1571                 ret = devm_request_irq(dev, lradc->irq[i],
1572                                         mxs_lradc_handle_irq, 0,
1573                                         of_cfg->irq_name[i], iio);
1574                 if (ret)
1575                         return ret;
1576         }
1577 
1578         lradc->vref_mv = of_cfg->vref_mv;
1579 
1580         platform_set_drvdata(pdev, iio);
1581 
1582         init_completion(&lradc->completion);
1583         mutex_init(&lradc->lock);
1584 
1585         iio->name = pdev->name;
1586         iio->dev.parent = &pdev->dev;
1587         iio->info = &mxs_lradc_iio_info;
1588         iio->modes = INDIO_DIRECT_MODE;
1589         iio->channels = mxs_lradc_chan_spec;
1590         iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec);
1591         iio->masklength = LRADC_MAX_TOTAL_CHANS;
1592 
1593         ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
1594                                 &mxs_lradc_trigger_handler,
1595                                 &mxs_lradc_buffer_ops);
1596         if (ret)
1597                 return ret;
1598 
1599         ret = mxs_lradc_trigger_init(iio);
1600         if (ret)
1601                 goto err_trig;
1602 
1603         /* Populate available ADC input ranges */
1604         for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
1605                 for (s = 0; s < ARRAY_SIZE(lradc->scale_avail[i]); s++) {
1606                         /*
1607                          * [s=0] = optional divider by two disabled (default)
1608                          * [s=1] = optional divider by two enabled
1609                          *
1610                          * The scale is calculated by doing:
1611                          *   Vref >> (realbits - s)
1612                          * which multiplies by two on the second component
1613                          * of the array.
1614                          */
1615                         scale_uv = ((u64)lradc->vref_mv[i] * 100000000) >>
1616                                    (LRADC_RESOLUTION - s);
1617                         lradc->scale_avail[i][s].nano =
1618                                         do_div(scale_uv, 100000000) * 10;
1619                         lradc->scale_avail[i][s].integer = scale_uv;
1620                 }
1621         }
1622 
1623         /* Configure the hardware. */
1624         ret = mxs_lradc_hw_init(lradc);
1625         if (ret)
1626                 goto err_dev;
1627 
1628         /* Register the touchscreen input device. */
1629         if (touch_ret == 0) {
1630                 ret = mxs_lradc_ts_register(lradc);
1631                 if (ret)
1632                         goto err_ts_register;
1633         }
1634 
1635         /* Register IIO device. */
1636         ret = iio_device_register(iio);
1637         if (ret) {
1638                 dev_err(dev, "Failed to register IIO device\n");
1639                 goto err_ts;
1640         }
1641 
1642         return 0;
1643 
1644 err_ts:
1645         mxs_lradc_ts_unregister(lradc);
1646 err_ts_register:
1647         mxs_lradc_hw_stop(lradc);
1648 err_dev:
1649         mxs_lradc_trigger_remove(iio);
1650 err_trig:
1651         iio_triggered_buffer_cleanup(iio);
1652         return ret;
1653 }
1654 
1655 static int mxs_lradc_remove(struct platform_device *pdev)
1656 {
1657         struct iio_dev *iio = platform_get_drvdata(pdev);
1658         struct mxs_lradc *lradc = iio_priv(iio);
1659 
1660         iio_device_unregister(iio);
1661         mxs_lradc_ts_unregister(lradc);
1662         mxs_lradc_hw_stop(lradc);
1663         mxs_lradc_trigger_remove(iio);
1664         iio_triggered_buffer_cleanup(iio);
1665 
1666         clk_disable_unprepare(lradc->clk);
1667         return 0;
1668 }
1669 
1670 static struct platform_driver mxs_lradc_driver = {
1671         .driver = {
1672                 .name   = DRIVER_NAME,
1673                 .owner  = THIS_MODULE,
1674                 .of_match_table = mxs_lradc_dt_ids,
1675         },
1676         .probe  = mxs_lradc_probe,
1677         .remove = mxs_lradc_remove,
1678 };
1679 
1680 module_platform_driver(mxs_lradc_driver);
1681 
1682 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1683 MODULE_DESCRIPTION("Freescale i.MX28 LRADC driver");
1684 MODULE_LICENSE("GPL v2");
1685 MODULE_ALIAS("platform:" DRIVER_NAME);
1686 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us