Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/staging/et131x/et131x.c

  1 /* Agere Systems Inc.
  2  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
  3  *
  4  * Copyright © 2005 Agere Systems Inc.
  5  * All rights reserved.
  6  *   http://www.agere.com
  7  *
  8  * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
  9  *
 10  *------------------------------------------------------------------------------
 11  *
 12  * SOFTWARE LICENSE
 13  *
 14  * This software is provided subject to the following terms and conditions,
 15  * which you should read carefully before using the software.  Using this
 16  * software indicates your acceptance of these terms and conditions.  If you do
 17  * not agree with these terms and conditions, do not use the software.
 18  *
 19  * Copyright © 2005 Agere Systems Inc.
 20  * All rights reserved.
 21  *
 22  * Redistribution and use in source or binary forms, with or without
 23  * modifications, are permitted provided that the following conditions are met:
 24  *
 25  * . Redistributions of source code must retain the above copyright notice, this
 26  *    list of conditions and the following Disclaimer as comments in the code as
 27  *    well as in the documentation and/or other materials provided with the
 28  *    distribution.
 29  *
 30  * . Redistributions in binary form must reproduce the above copyright notice,
 31  *    this list of conditions and the following Disclaimer in the documentation
 32  *    and/or other materials provided with the distribution.
 33  *
 34  * . Neither the name of Agere Systems Inc. nor the names of the contributors
 35  *    may be used to endorse or promote products derived from this software
 36  *    without specific prior written permission.
 37  *
 38  * Disclaimer
 39  *
 40  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 41  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
 42  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
 43  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
 44  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
 45  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 46  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 47  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 48  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
 49  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
 50  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
 51  * DAMAGE.
 52  */
 53 
 54 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 55 
 56 #include <linux/pci.h>
 57 #include <linux/module.h>
 58 #include <linux/types.h>
 59 #include <linux/kernel.h>
 60 
 61 #include <linux/sched.h>
 62 #include <linux/ptrace.h>
 63 #include <linux/slab.h>
 64 #include <linux/ctype.h>
 65 #include <linux/string.h>
 66 #include <linux/timer.h>
 67 #include <linux/interrupt.h>
 68 #include <linux/in.h>
 69 #include <linux/delay.h>
 70 #include <linux/bitops.h>
 71 #include <linux/io.h>
 72 
 73 #include <linux/netdevice.h>
 74 #include <linux/etherdevice.h>
 75 #include <linux/skbuff.h>
 76 #include <linux/if_arp.h>
 77 #include <linux/ioport.h>
 78 #include <linux/crc32.h>
 79 #include <linux/random.h>
 80 #include <linux/phy.h>
 81 
 82 #include "et131x.h"
 83 
 84 MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
 85 MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>");
 86 MODULE_LICENSE("Dual BSD/GPL");
 87 MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver for the ET1310 by Agere Systems");
 88 
 89 /* EEPROM defines */
 90 #define MAX_NUM_REGISTER_POLLS          1000
 91 #define MAX_NUM_WRITE_RETRIES           2
 92 
 93 /* MAC defines */
 94 #define COUNTER_WRAP_16_BIT 0x10000
 95 #define COUNTER_WRAP_12_BIT 0x1000
 96 
 97 /* PCI defines */
 98 #define INTERNAL_MEM_SIZE       0x400   /* 1024 of internal memory */
 99 #define INTERNAL_MEM_RX_OFFSET  0x1FF   /* 50%   Tx, 50%   Rx */
100 
101 /* ISR defines */
102 /* For interrupts, normal running is:
103  *       rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
104  *       watchdog_interrupt & txdma_xfer_done
105  *
106  * In both cases, when flow control is enabled for either Tx or bi-direction,
107  * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
108  * buffer rings are running low.
109  */
110 #define INT_MASK_DISABLE            0xffffffff
111 
112 /* NOTE: Masking out MAC_STAT Interrupt for now...
113  * #define INT_MASK_ENABLE             0xfff6bf17
114  * #define INT_MASK_ENABLE_NO_FLOW     0xfff6bfd7
115  */
116 #define INT_MASK_ENABLE             0xfffebf17
117 #define INT_MASK_ENABLE_NO_FLOW     0xfffebfd7
118 
119 /* General defines */
120 /* Packet and header sizes */
121 #define NIC_MIN_PACKET_SIZE     60
122 
123 /* Multicast list size */
124 #define NIC_MAX_MCAST_LIST      128
125 
126 /* Supported Filters */
127 #define ET131X_PACKET_TYPE_DIRECTED             0x0001
128 #define ET131X_PACKET_TYPE_MULTICAST            0x0002
129 #define ET131X_PACKET_TYPE_BROADCAST            0x0004
130 #define ET131X_PACKET_TYPE_PROMISCUOUS          0x0008
131 #define ET131X_PACKET_TYPE_ALL_MULTICAST        0x0010
132 
133 /* Tx Timeout */
134 #define ET131X_TX_TIMEOUT       (1 * HZ)
135 #define NIC_SEND_HANG_THRESHOLD 0
136 
137 /* MP_TCB flags */
138 #define FMP_DEST_MULTI                  0x00000001
139 #define FMP_DEST_BROAD                  0x00000002
140 
141 /* MP_ADAPTER flags */
142 #define FMP_ADAPTER_INTERRUPT_IN_USE    0x00000008
143 
144 /* MP_SHARED flags */
145 #define FMP_ADAPTER_LOWER_POWER         0x00200000
146 
147 #define FMP_ADAPTER_NON_RECOVER_ERROR   0x00800000
148 #define FMP_ADAPTER_HARDWARE_ERROR      0x04000000
149 
150 #define FMP_ADAPTER_FAIL_SEND_MASK      0x3ff00000
151 
152 /* Some offsets in PCI config space that are actually used. */
153 #define ET1310_PCI_MAC_ADDRESS          0xA4
154 #define ET1310_PCI_EEPROM_STATUS        0xB2
155 #define ET1310_PCI_ACK_NACK             0xC0
156 #define ET1310_PCI_REPLAY               0xC2
157 #define ET1310_PCI_L0L1LATENCY          0xCF
158 
159 /* PCI Product IDs */
160 #define ET131X_PCI_DEVICE_ID_GIG        0xED00  /* ET1310 1000 Base-T 8 */
161 #define ET131X_PCI_DEVICE_ID_FAST       0xED01  /* ET1310 100  Base-T */
162 
163 /* Define order of magnitude converter */
164 #define NANO_IN_A_MICRO 1000
165 
166 #define PARM_RX_NUM_BUFS_DEF    4
167 #define PARM_RX_TIME_INT_DEF    10
168 #define PARM_RX_MEM_END_DEF     0x2bc
169 #define PARM_TX_TIME_INT_DEF    40
170 #define PARM_TX_NUM_BUFS_DEF    4
171 #define PARM_DMA_CACHE_DEF      0
172 
173 /* RX defines */
174 #define FBR_CHUNKS              32
175 #define MAX_DESC_PER_RING_RX    1024
176 
177 /* number of RFDs - default and min */
178 #define RFD_LOW_WATER_MARK      40
179 #define NIC_DEFAULT_NUM_RFD     1024
180 #define NUM_FBRS                2
181 
182 #define NUM_PACKETS_HANDLED     256
183 
184 #define ALCATEL_MULTICAST_PKT   0x01000000
185 #define ALCATEL_BROADCAST_PKT   0x02000000
186 
187 /* typedefs for Free Buffer Descriptors */
188 struct fbr_desc {
189         u32 addr_lo;
190         u32 addr_hi;
191         u32 word2;              /* Bits 10-31 reserved, 0-9 descriptor */
192 };
193 
194 /* Packet Status Ring Descriptors
195  *
196  * Word 0:
197  *
198  * top 16 bits are from the Alcatel Status Word as enumerated in
199  * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
200  *
201  * 0: hp                        hash pass
202  * 1: ipa                       IP checksum assist
203  * 2: ipp                       IP checksum pass
204  * 3: tcpa                      TCP checksum assist
205  * 4: tcpp                      TCP checksum pass
206  * 5: wol                       WOL Event
207  * 6: rxmac_error               RXMAC Error Indicator
208  * 7: drop                      Drop packet
209  * 8: ft                        Frame Truncated
210  * 9: jp                        Jumbo Packet
211  * 10: vp                       VLAN Packet
212  * 11-15: unused
213  * 16: asw_prev_pkt_dropped     e.g. IFG too small on previous
214  * 17: asw_RX_DV_event          short receive event detected
215  * 18: asw_false_carrier_event  bad carrier since last good packet
216  * 19: asw_code_err             one or more nibbles signalled as errors
217  * 20: asw_CRC_err              CRC error
218  * 21: asw_len_chk_err          frame length field incorrect
219  * 22: asw_too_long             frame length > 1518 bytes
220  * 23: asw_OK                   valid CRC + no code error
221  * 24: asw_multicast            has a multicast address
222  * 25: asw_broadcast            has a broadcast address
223  * 26: asw_dribble_nibble       spurious bits after EOP
224  * 27: asw_control_frame        is a control frame
225  * 28: asw_pause_frame          is a pause frame
226  * 29: asw_unsupported_op       unsupported OP code
227  * 30: asw_VLAN_tag             VLAN tag detected
228  * 31: asw_long_evt             Rx long event
229  *
230  * Word 1:
231  * 0-15: length                 length in bytes
232  * 16-25: bi                    Buffer Index
233  * 26-27: ri                    Ring Index
234  * 28-31: reserved
235  */
236 
237 struct pkt_stat_desc {
238         u32 word0;
239         u32 word1;
240 };
241 
242 /* Typedefs for the RX DMA status word */
243 
244 /* rx status word 0 holds part of the status bits of the Rx DMA engine
245  * that get copied out to memory by the ET-1310.  Word 0 is a 32 bit word
246  * which contains the Free Buffer ring 0 and 1 available offset.
247  *
248  * bit 0-9 FBR1 offset
249  * bit 10 Wrap flag for FBR1
250  * bit 16-25 FBR0 offset
251  * bit 26 Wrap flag for FBR0
252  */
253 
254 /* RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
255  * that get copied out to memory by the ET-1310.  Word 3 is a 32 bit word
256  * which contains the Packet Status Ring available offset.
257  *
258  * bit 0-15 reserved
259  * bit 16-27 PSRoffset
260  * bit 28 PSRwrap
261  * bit 29-31 unused
262  */
263 
264 /* struct rx_status_block is a structure representing the status of the Rx
265  * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
266  */
267 struct rx_status_block {
268         u32 word0;
269         u32 word1;
270 };
271 
272 /* Structure for look-up table holding free buffer ring pointers, addresses
273  * and state.
274  */
275 struct fbr_lookup {
276         void            *virt[MAX_DESC_PER_RING_RX];
277         u32              bus_high[MAX_DESC_PER_RING_RX];
278         u32              bus_low[MAX_DESC_PER_RING_RX];
279         void            *ring_virtaddr;
280         dma_addr_t       ring_physaddr;
281         void            *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
282         dma_addr_t       mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
283         u32              local_full;
284         u32              num_entries;
285         dma_addr_t       buffsize;
286 };
287 
288 /* struct rx_ring is the structure representing the adaptor's local
289  * reference(s) to the rings
290  */
291 struct rx_ring {
292         struct fbr_lookup *fbr[NUM_FBRS];
293         void *ps_ring_virtaddr;
294         dma_addr_t ps_ring_physaddr;
295         u32 local_psr_full;
296         u32 psr_num_entries;
297 
298         struct rx_status_block *rx_status_block;
299         dma_addr_t rx_status_bus;
300 
301         /* RECV */
302         struct list_head recv_list;
303         u32 num_ready_recv;
304 
305         u32 num_rfd;
306 
307         bool unfinished_receives;
308 };
309 
310 /* TX defines */
311 /* word 2 of the control bits in the Tx Descriptor ring for the ET-1310
312  *
313  * 0-15: length of packet
314  * 16-27: VLAN tag
315  * 28: VLAN CFI
316  * 29-31: VLAN priority
317  *
318  * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
319  *
320  * 0: last packet in the sequence
321  * 1: first packet in the sequence
322  * 2: interrupt the processor when this pkt sent
323  * 3: Control word - no packet data
324  * 4: Issue half-duplex backpressure : XON/XOFF
325  * 5: send pause frame
326  * 6: Tx frame has error
327  * 7: append CRC
328  * 8: MAC override
329  * 9: pad packet
330  * 10: Packet is a Huge packet
331  * 11: append VLAN tag
332  * 12: IP checksum assist
333  * 13: TCP checksum assist
334  * 14: UDP checksum assist
335  */
336 
337 #define TXDESC_FLAG_LASTPKT             0x0001
338 #define TXDESC_FLAG_FIRSTPKT            0x0002
339 #define TXDESC_FLAG_INTPROC             0x0004
340 
341 /* struct tx_desc represents each descriptor on the ring */
342 struct tx_desc {
343         u32 addr_hi;
344         u32 addr_lo;
345         u32 len_vlan;   /* control words how to xmit the */
346         u32 flags;      /* data (detailed above) */
347 };
348 
349 /* The status of the Tx DMA engine it sits in free memory, and is pointed to
350  * by 0x101c / 0x1020. This is a DMA10 type
351  */
352 
353 /* TCB (Transmit Control Block: Host Side) */
354 struct tcb {
355         struct tcb *next;       /* Next entry in ring */
356         u32 flags;              /* Our flags for the packet */
357         u32 count;              /* Used to spot stuck/lost packets */
358         u32 stale;              /* Used to spot stuck/lost packets */
359         struct sk_buff *skb;    /* Network skb we are tied to */
360         u32 index;              /* Ring indexes */
361         u32 index_start;
362 };
363 
364 /* Structure representing our local reference(s) to the ring */
365 struct tx_ring {
366         /* TCB (Transmit Control Block) memory and lists */
367         struct tcb *tcb_ring;
368 
369         /* List of TCBs that are ready to be used */
370         struct tcb *tcb_qhead;
371         struct tcb *tcb_qtail;
372 
373         /* list of TCBs that are currently being sent.  NOTE that access to all
374          * three of these (including used) are controlled via the
375          * TCBSendQLock.  This lock should be secured prior to incementing /
376          * decrementing used, or any queue manipulation on send_head /
377          * tail
378          */
379         struct tcb *send_head;
380         struct tcb *send_tail;
381         int used;
382 
383         /* The actual descriptor ring */
384         struct tx_desc *tx_desc_ring;
385         dma_addr_t tx_desc_ring_pa;
386 
387         /* send_idx indicates where we last wrote to in the descriptor ring. */
388         u32 send_idx;
389 
390         /* The location of the write-back status block */
391         u32 *tx_status;
392         dma_addr_t tx_status_pa;
393 
394         /* Packets since the last IRQ: used for interrupt coalescing */
395         int since_irq;
396 };
397 
398 /* Do not change these values: if changed, then change also in respective
399  * TXdma and Rxdma engines
400  */
401 #define NUM_DESC_PER_RING_TX         512    /* TX Do not change these values */
402 #define NUM_TCB                      64
403 
404 /* These values are all superseded by registry entries to facilitate tuning.
405  * Once the desired performance has been achieved, the optimal registry values
406  * should be re-populated to these #defines:
407  */
408 #define TX_ERROR_PERIOD             1000
409 
410 #define LO_MARK_PERCENT_FOR_PSR     15
411 #define LO_MARK_PERCENT_FOR_RX      15
412 
413 /* RFD (Receive Frame Descriptor) */
414 struct rfd {
415         struct list_head list_node;
416         struct sk_buff *skb;
417         u32 len;        /* total size of receive frame */
418         u16 bufferindex;
419         u8 ringindex;
420 };
421 
422 /* Flow Control */
423 #define FLOW_BOTH       0
424 #define FLOW_TXONLY     1
425 #define FLOW_RXONLY     2
426 #define FLOW_NONE       3
427 
428 /* Struct to define some device statistics */
429 struct ce_stats {
430         /* MIB II variables
431          *
432          * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
433          * MUST have 32, then we'll need another way to perform atomic
434          * operations
435          */
436         u32             unicast_pkts_rcvd;
437         atomic_t        unicast_pkts_xmtd;
438         u32             multicast_pkts_rcvd;
439         atomic_t        multicast_pkts_xmtd;
440         u32             broadcast_pkts_rcvd;
441         atomic_t        broadcast_pkts_xmtd;
442         u32             rcvd_pkts_dropped;
443 
444         /* Tx Statistics. */
445         u32             tx_underflows;
446 
447         u32             tx_collisions;
448         u32             tx_excessive_collisions;
449         u32             tx_first_collisions;
450         u32             tx_late_collisions;
451         u32             tx_max_pkt_errs;
452         u32             tx_deferred;
453 
454         /* Rx Statistics. */
455         u32             rx_overflows;
456 
457         u32             rx_length_errs;
458         u32             rx_align_errs;
459         u32             rx_crc_errs;
460         u32             rx_code_violations;
461         u32             rx_other_errs;
462 
463         u32             synchronous_iterations;
464         u32             interrupt_status;
465 };
466 
467 /* The private adapter structure */
468 struct et131x_adapter {
469         struct net_device *netdev;
470         struct pci_dev *pdev;
471         struct mii_bus *mii_bus;
472         struct phy_device *phydev;
473         struct work_struct task;
474 
475         /* Flags that indicate current state of the adapter */
476         u32 flags;
477 
478         /* local link state, to determine if a state change has occurred */
479         int link;
480 
481         /* Configuration  */
482         u8 rom_addr[ETH_ALEN];
483         u8 addr[ETH_ALEN];
484         bool has_eeprom;
485         u8 eeprom_data[2];
486 
487         /* Spinlocks */
488         spinlock_t tcb_send_qlock;
489         spinlock_t tcb_ready_qlock;
490         spinlock_t send_hw_lock;
491 
492         spinlock_t rcv_lock;
493         spinlock_t fbr_lock;
494 
495         /* Packet Filter and look ahead size */
496         u32 packet_filter;
497 
498         /* multicast list */
499         u32 multicast_addr_count;
500         u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN];
501 
502         /* Pointer to the device's PCI register space */
503         struct address_map __iomem *regs;
504 
505         /* Registry parameters */
506         u8 wanted_flow;         /* Flow we want for 802.3x flow control */
507         u32 registry_jumbo_packet;      /* Max supported ethernet packet size */
508 
509         /* Derived from the registry: */
510         u8 flowcontrol;         /* flow control validated by the far-end */
511 
512         /* Minimize init-time */
513         struct timer_list error_timer;
514 
515         /* variable putting the phy into coma mode when boot up with no cable
516          * plugged in after 5 seconds
517          */
518         u8 boot_coma;
519 
520         /* Next two used to save power information at power down. This
521          * information will be used during power up to set up parts of Power
522          * Management in JAGCore
523          */
524         u16 pdown_speed;
525         u8 pdown_duplex;
526 
527         /* Tx Memory Variables */
528         struct tx_ring tx_ring;
529 
530         /* Rx Memory Variables */
531         struct rx_ring rx_ring;
532 
533         /* Stats */
534         struct ce_stats stats;
535 };
536 
537 static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
538 {
539         u32 reg;
540         int i;
541 
542         /* 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
543          *    bits 7,1:0 both equal to 1, at least once after reset.
544          *    Subsequent operations need only to check that bits 1:0 are equal
545          *    to 1 prior to starting a single byte read/write
546          */
547 
548         for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
549                 /* Read registers grouped in DWORD1 */
550                 if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, &reg))
551                         return -EIO;
552 
553                 /* I2C idle and Phy Queue Avail both true */
554                 if ((reg & 0x3000) == 0x3000) {
555                         if (status)
556                                 *status = reg;
557                         return reg & 0xFF;
558                 }
559         }
560         return -ETIMEDOUT;
561 }
562 
563 /* eeprom_write - Write a byte to the ET1310's EEPROM
564  * @adapter: pointer to our private adapter structure
565  * @addr: the address to write
566  * @data: the value to write
567  *
568  * Returns 1 for a successful write.
569  */
570 static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data)
571 {
572         struct pci_dev *pdev = adapter->pdev;
573         int index = 0;
574         int retries;
575         int err = 0;
576         int i2c_wack = 0;
577         int writeok = 0;
578         u32 status;
579         u32 val = 0;
580 
581         /* For an EEPROM, an I2C single byte write is defined as a START
582          * condition followed by the device address, EEPROM address, one byte
583          * of data and a STOP condition.  The STOP condition will trigger the
584          * EEPROM's internally timed write cycle to the nonvolatile memory.
585          * All inputs are disabled during this write cycle and the EEPROM will
586          * not respond to any access until the internal write is complete.
587          */
588 
589         err = eeprom_wait_ready(pdev, NULL);
590         if (err < 0)
591                 return err;
592 
593          /* 2. Write to the LBCIF Control Register:  bit 7=1, bit 6=1, bit 3=0,
594           *    and bits 1:0 both =0.  Bit 5 should be set according to the
595           *    type of EEPROM being accessed (1=two byte addressing, 0=one
596           *    byte addressing).
597           */
598         if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
599                         LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE))
600                 return -EIO;
601 
602         i2c_wack = 1;
603 
604         /* Prepare EEPROM address for Step 3 */
605 
606         for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
607                 /* Write the address to the LBCIF Address Register */
608                 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
609                         break;
610                 /* Write the data to the LBCIF Data Register (the I2C write
611                  * will begin).
612                  */
613                 if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
614                         break;
615                 /* Monitor bit 1:0 of the LBCIF Status Register.  When bits
616                  * 1:0 are both equal to 1, the I2C write has completed and the
617                  * internal write cycle of the EEPROM is about to start.
618                  * (bits 1:0 = 01 is a legal state while waiting from both
619                  * equal to 1, but bits 1:0 = 10 is invalid and implies that
620                  * something is broken).
621                  */
622                 err = eeprom_wait_ready(pdev, &status);
623                 if (err < 0)
624                         return 0;
625 
626                 /* Check bit 3 of the LBCIF Status Register.  If  equal to 1,
627                  * an error has occurred.Don't break here if we are revision
628                  * 1, this is so we do a blind write for load bug.
629                  */
630                 if ((status & LBCIF_STATUS_GENERAL_ERROR)
631                         && adapter->pdev->revision == 0)
632                         break;
633 
634                 /* Check bit 2 of the LBCIF Status Register.  If equal to 1 an
635                  * ACK error has occurred on the address phase of the write.
636                  * This could be due to an actual hardware failure or the
637                  * EEPROM may still be in its internal write cycle from a
638                  * previous write. This write operation was ignored and must be
639                   *repeated later.
640                  */
641                 if (status & LBCIF_STATUS_ACK_ERROR) {
642                         /* This could be due to an actual hardware failure
643                          * or the EEPROM may still be in its internal write
644                          * cycle from a previous write. This write operation
645                          * was ignored and must be repeated later.
646                          */
647                         udelay(10);
648                         continue;
649                 }
650 
651                 writeok = 1;
652                 break;
653         }
654 
655         /* Set bit 6 of the LBCIF Control Register = 0.
656          */
657         udelay(10);
658 
659         while (i2c_wack) {
660                 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
661                         LBCIF_CONTROL_LBCIF_ENABLE))
662                         writeok = 0;
663 
664                 /* Do read until internal ACK_ERROR goes away meaning write
665                  * completed
666                  */
667                 do {
668                         pci_write_config_dword(pdev,
669                                                LBCIF_ADDRESS_REGISTER,
670                                                addr);
671                         do {
672                                 pci_read_config_dword(pdev,
673                                         LBCIF_DATA_REGISTER, &val);
674                         } while ((val & 0x00010000) == 0);
675                 } while (val & 0x00040000);
676 
677                 if ((val & 0xFF00) != 0xC000 || index == 10000)
678                         break;
679                 index++;
680         }
681         return writeok ? 0 : -EIO;
682 }
683 
684 /* eeprom_read - Read a byte from the ET1310's EEPROM
685  * @adapter: pointer to our private adapter structure
686  * @addr: the address from which to read
687  * @pdata: a pointer to a byte in which to store the value of the read
688  * @eeprom_id: the ID of the EEPROM
689  * @addrmode: how the EEPROM is to be accessed
690  *
691  * Returns 1 for a successful read
692  */
693 static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata)
694 {
695         struct pci_dev *pdev = adapter->pdev;
696         int err;
697         u32 status;
698 
699         /* A single byte read is similar to the single byte write, with the
700          * exception of the data flow:
701          */
702 
703         err = eeprom_wait_ready(pdev, NULL);
704         if (err < 0)
705                 return err;
706         /* Write to the LBCIF Control Register:  bit 7=1, bit 6=0, bit 3=0,
707          * and bits 1:0 both =0.  Bit 5 should be set according to the type
708          * of EEPROM being accessed (1=two byte addressing, 0=one byte
709          * addressing).
710          */
711         if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
712                                   LBCIF_CONTROL_LBCIF_ENABLE))
713                 return -EIO;
714         /* Write the address to the LBCIF Address Register (I2C read will
715          * begin).
716          */
717         if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
718                 return -EIO;
719         /* Monitor bit 0 of the LBCIF Status Register.  When = 1, I2C read
720          * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
721          * has occurred).
722          */
723         err = eeprom_wait_ready(pdev, &status);
724         if (err < 0)
725                 return err;
726         /* Regardless of error status, read data byte from LBCIF Data
727          * Register.
728          */
729         *pdata = err;
730         /* Check bit 2 of the LBCIF Status Register.  If = 1,
731          * then an error has occurred.
732          */
733         return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
734 }
735 
736 static int et131x_init_eeprom(struct et131x_adapter *adapter)
737 {
738         struct pci_dev *pdev = adapter->pdev;
739         u8 eestatus;
740 
741         /* We first need to check the EEPROM Status code located at offset
742          * 0xB2 of config space
743          */
744         pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus);
745 
746         /* THIS IS A WORKAROUND:
747          * I need to call this function twice to get my card in a
748          * LG M1 Express Dual running. I tried also a msleep before this
749          * function, because I thought there could be some time conditions
750          * but it didn't work. Call the whole function twice also work.
751          */
752         if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
753                 dev_err(&pdev->dev,
754                        "Could not read PCI config space for EEPROM Status\n");
755                 return -EIO;
756         }
757 
758         /* Determine if the error(s) we care about are present. If they are
759          * present we need to fail.
760          */
761         if (eestatus & 0x4C) {
762                 int write_failed = 0;
763 
764                 if (pdev->revision == 0x01) {
765                         int     i;
766                         static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
767 
768                         /* Re-write the first 4 bytes if we have an eeprom
769                          * present and the revision id is 1, this fixes the
770                          * corruption seen with 1310 B Silicon
771                          */
772                         for (i = 0; i < 3; i++)
773                                 if (eeprom_write(adapter, i, eedata[i]) < 0)
774                                         write_failed = 1;
775                 }
776                 if (pdev->revision  != 0x01 || write_failed) {
777                         dev_err(&pdev->dev,
778                             "Fatal EEPROM Status Error - 0x%04x\n", eestatus);
779 
780                         /* This error could mean that there was an error
781                          * reading the eeprom or that the eeprom doesn't exist.
782                          * We will treat each case the same and not try to
783                          * gather additional information that normally would
784                          * come from the eeprom, like MAC Address
785                          */
786                         adapter->has_eeprom = 0;
787                         return -EIO;
788                 }
789         }
790         adapter->has_eeprom = 1;
791 
792         /* Read the EEPROM for information regarding LED behavior. Refer to
793          * ET1310_phy.c, et131x_xcvr_init(), for its use.
794          */
795         eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]);
796         eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]);
797 
798         if (adapter->eeprom_data[0] != 0xcd)
799                 /* Disable all optional features */
800                 adapter->eeprom_data[1] = 0x00;
801 
802         return 0;
803 }
804 
805 /* et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
806  * @adapter: pointer to our adapter structure
807  */
808 static void et131x_rx_dma_enable(struct et131x_adapter *adapter)
809 {
810         /* Setup the receive dma configuration register for normal operation */
811         u32 csr =  ET_RXDMA_CSR_FBR1_ENABLE;
812         struct rx_ring *rx_ring = &adapter->rx_ring;
813 
814         if (rx_ring->fbr[1]->buffsize == 4096)
815                 csr |= ET_RXDMA_CSR_FBR1_SIZE_LO;
816         else if (rx_ring->fbr[1]->buffsize == 8192)
817                 csr |= ET_RXDMA_CSR_FBR1_SIZE_HI;
818         else if (rx_ring->fbr[1]->buffsize == 16384)
819                 csr |= ET_RXDMA_CSR_FBR1_SIZE_LO | ET_RXDMA_CSR_FBR1_SIZE_HI;
820 
821         csr |= ET_RXDMA_CSR_FBR0_ENABLE;
822         if (rx_ring->fbr[0]->buffsize == 256)
823                 csr |= ET_RXDMA_CSR_FBR0_SIZE_LO;
824         else if (rx_ring->fbr[0]->buffsize == 512)
825                 csr |= ET_RXDMA_CSR_FBR0_SIZE_HI;
826         else if (rx_ring->fbr[0]->buffsize == 1024)
827                 csr |= ET_RXDMA_CSR_FBR0_SIZE_LO | ET_RXDMA_CSR_FBR0_SIZE_HI;
828         writel(csr, &adapter->regs->rxdma.csr);
829 
830         csr = readl(&adapter->regs->rxdma.csr);
831         if (csr & ET_RXDMA_CSR_HALT_STATUS) {
832                 udelay(5);
833                 csr = readl(&adapter->regs->rxdma.csr);
834                 if (csr & ET_RXDMA_CSR_HALT_STATUS) {
835                         dev_err(&adapter->pdev->dev,
836                             "RX Dma failed to exit halt state.  CSR 0x%08x\n",
837                                 csr);
838                 }
839         }
840 }
841 
842 /* et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
843  * @adapter: pointer to our adapter structure
844  */
845 static void et131x_rx_dma_disable(struct et131x_adapter *adapter)
846 {
847         u32 csr;
848         /* Setup the receive dma configuration register */
849         writel(ET_RXDMA_CSR_HALT | ET_RXDMA_CSR_FBR1_ENABLE,
850                &adapter->regs->rxdma.csr);
851         csr = readl(&adapter->regs->rxdma.csr);
852         if (!(csr & ET_RXDMA_CSR_HALT_STATUS)) {
853                 udelay(5);
854                 csr = readl(&adapter->regs->rxdma.csr);
855                 if (!(csr & ET_RXDMA_CSR_HALT_STATUS))
856                         dev_err(&adapter->pdev->dev,
857                               "RX Dma failed to enter halt state. CSR 0x%08x\n",
858                               csr);
859         }
860 }
861 
862 /* et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
863  * @adapter: pointer to our adapter structure
864  *
865  * Mainly used after a return to the D0 (full-power) state from a lower state.
866  */
867 static void et131x_tx_dma_enable(struct et131x_adapter *adapter)
868 {
869         /* Setup the transmit dma configuration register for normal
870          * operation
871          */
872         writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
873                                         &adapter->regs->txdma.csr);
874 }
875 
876 static inline void add_10bit(u32 *v, int n)
877 {
878         *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
879 }
880 
881 static inline void add_12bit(u32 *v, int n)
882 {
883         *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
884 }
885 
886 /* et1310_config_mac_regs1 - Initialize the first part of MAC regs
887  * @adapter: pointer to our adapter structure
888  */
889 static void et1310_config_mac_regs1(struct et131x_adapter *adapter)
890 {
891         struct mac_regs __iomem *macregs = &adapter->regs->mac;
892         u32 station1;
893         u32 station2;
894         u32 ipg;
895 
896         /* First we need to reset everything.  Write to MAC configuration
897          * register 1 to perform reset.
898          */
899         writel(ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET  |
900                ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
901                ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC,
902                &macregs->cfg1);
903 
904         /* Next lets configure the MAC Inter-packet gap register */
905         ipg = 0x38005860;               /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
906         ipg |= 0x50 << 8;               /* ifg enforce 0x50 */
907         writel(ipg, &macregs->ipg);
908 
909         /* Next lets configure the MAC Half Duplex register */
910         /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
911         writel(0x00A1F037, &macregs->hfdp);
912 
913         /* Next lets configure the MAC Interface Control register */
914         writel(0, &macregs->if_ctrl);
915 
916         /* Let's move on to setting up the mii management configuration */
917         writel(ET_MAC_MIIMGMT_CLK_RST, &macregs->mii_mgmt_cfg);
918 
919         /* Next lets configure the MAC Station Address register.  These
920          * values are read from the EEPROM during initialization and stored
921          * in the adapter structure.  We write what is stored in the adapter
922          * structure to the MAC Station Address registers high and low.  This
923          * station address is used for generating and checking pause control
924          * packets.
925          */
926         station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) |
927                    (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT);
928         station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) |
929                    (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) |
930                    (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) |
931                     adapter->addr[2];
932         writel(station1, &macregs->station_addr_1);
933         writel(station2, &macregs->station_addr_2);
934 
935         /* Max ethernet packet in bytes that will be passed by the mac without
936          * being truncated.  Allow the MAC to pass 4 more than our max packet
937          * size.  This is 4 for the Ethernet CRC.
938          *
939          * Packets larger than (registry_jumbo_packet) that do not contain a
940          * VLAN ID will be dropped by the Rx function.
941          */
942         writel(adapter->registry_jumbo_packet + 4, &macregs->max_fm_len);
943 
944         /* clear out MAC config reset */
945         writel(0, &macregs->cfg1);
946 }
947 
948 /* et1310_config_mac_regs2 - Initialize the second part of MAC regs
949  * @adapter: pointer to our adapter structure
950  */
951 static void et1310_config_mac_regs2(struct et131x_adapter *adapter)
952 {
953         int32_t delay = 0;
954         struct mac_regs __iomem *mac = &adapter->regs->mac;
955         struct phy_device *phydev = adapter->phydev;
956         u32 cfg1;
957         u32 cfg2;
958         u32 ifctrl;
959         u32 ctl;
960 
961         ctl = readl(&adapter->regs->txmac.ctl);
962         cfg1 = readl(&mac->cfg1);
963         cfg2 = readl(&mac->cfg2);
964         ifctrl = readl(&mac->if_ctrl);
965 
966         /* Set up the if mode bits */
967         cfg2 &= ~ET_MAC_CFG2_IFMODE_MASK;
968         if (phydev->speed == SPEED_1000) {
969                 cfg2 |= ET_MAC_CFG2_IFMODE_1000;
970                 /* Phy mode bit */
971                 ifctrl &= ~ET_MAC_IFCTRL_PHYMODE;
972         } else {
973                 cfg2 |= ET_MAC_CFG2_IFMODE_100;
974                 ifctrl |= ET_MAC_IFCTRL_PHYMODE;
975         }
976 
977         /* We need to enable Rx/Tx */
978         cfg1 |= ET_MAC_CFG1_RX_ENABLE | ET_MAC_CFG1_TX_ENABLE |
979                                                         ET_MAC_CFG1_TX_FLOW;
980         /* Initialize loop back to off */
981         cfg1 &= ~(ET_MAC_CFG1_LOOPBACK | ET_MAC_CFG1_RX_FLOW);
982         if (adapter->flowcontrol == FLOW_RXONLY ||
983                                 adapter->flowcontrol == FLOW_BOTH)
984                 cfg1 |= ET_MAC_CFG1_RX_FLOW;
985         writel(cfg1, &mac->cfg1);
986 
987         /* Now we need to initialize the MAC Configuration 2 register */
988         /* preamble 7, check length, huge frame off, pad crc, crc enable
989          * full duplex off
990          */
991         cfg2 |= 0x7 << ET_MAC_CFG2_PREAMBLE_SHIFT;
992         cfg2 |= ET_MAC_CFG2_IFMODE_LEN_CHECK;
993         cfg2 |= ET_MAC_CFG2_IFMODE_PAD_CRC;
994         cfg2 |= ET_MAC_CFG2_IFMODE_CRC_ENABLE;
995         cfg2 &= ~ET_MAC_CFG2_IFMODE_HUGE_FRAME;
996         cfg2 &= ~ET_MAC_CFG2_IFMODE_FULL_DPLX;
997 
998         /* Turn on duplex if needed */
999         if (phydev->duplex == DUPLEX_FULL)
1000                 cfg2 |= ET_MAC_CFG2_IFMODE_FULL_DPLX;
1001 
1002         ifctrl &= ~ET_MAC_IFCTRL_GHDMODE;
1003         if (phydev->duplex == DUPLEX_HALF)
1004                 ifctrl |= ET_MAC_IFCTRL_GHDMODE;
1005 
1006         writel(ifctrl, &mac->if_ctrl);
1007         writel(cfg2, &mac->cfg2);
1008 
1009         do {
1010                 udelay(10);
1011                 delay++;
1012                 cfg1 = readl(&mac->cfg1);
1013         } while ((cfg1 & ET_MAC_CFG1_WAIT) != ET_MAC_CFG1_WAIT && delay < 100);
1014 
1015         if (delay == 100) {
1016                 dev_warn(&adapter->pdev->dev,
1017                     "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
1018                         cfg1);
1019         }
1020 
1021         /* Enable txmac */
1022         ctl |= ET_TX_CTRL_TXMAC_ENABLE | ET_TX_CTRL_FC_DISABLE;
1023         writel(ctl, &adapter->regs->txmac.ctl);
1024 
1025         /* Ready to start the RXDMA/TXDMA engine */
1026         if (adapter->flags & FMP_ADAPTER_LOWER_POWER) {
1027                 et131x_rx_dma_enable(adapter);
1028                 et131x_tx_dma_enable(adapter);
1029         }
1030 }
1031 
1032 /* et1310_in_phy_coma - check if the device is in phy coma
1033  * @adapter: pointer to our adapter structure
1034  *
1035  * Returns 0 if the device is not in phy coma, 1 if it is in phy coma
1036  */
1037 static int et1310_in_phy_coma(struct et131x_adapter *adapter)
1038 {
1039         u32 pmcsr = readl(&adapter->regs->global.pm_csr);
1040 
1041         return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
1042 }
1043 
1044 static void et1310_setup_device_for_multicast(struct et131x_adapter *adapter)
1045 {
1046         struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1047         u32 hash1 = 0;
1048         u32 hash2 = 0;
1049         u32 hash3 = 0;
1050         u32 hash4 = 0;
1051         u32 pm_csr;
1052 
1053         /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
1054          * the multi-cast LIST.  If it is NOT specified, (and "ALL" is not
1055          * specified) then we should pass NO multi-cast addresses to the
1056          * driver.
1057          */
1058         if (adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) {
1059                 int i;
1060 
1061                 /* Loop through our multicast array and set up the device */
1062                 for (i = 0; i < adapter->multicast_addr_count; i++) {
1063                         u32 result;
1064 
1065                         result = ether_crc(6, adapter->multicast_list[i]);
1066 
1067                         result = (result & 0x3F800000) >> 23;
1068 
1069                         if (result < 32) {
1070                                 hash1 |= (1 << result);
1071                         } else if ((31 < result) && (result < 64)) {
1072                                 result -= 32;
1073                                 hash2 |= (1 << result);
1074                         } else if ((63 < result) && (result < 96)) {
1075                                 result -= 64;
1076                                 hash3 |= (1 << result);
1077                         } else {
1078                                 result -= 96;
1079                                 hash4 |= (1 << result);
1080                         }
1081                 }
1082         }
1083 
1084         /* Write out the new hash to the device */
1085         pm_csr = readl(&adapter->regs->global.pm_csr);
1086         if (!et1310_in_phy_coma(adapter)) {
1087                 writel(hash1, &rxmac->multi_hash1);
1088                 writel(hash2, &rxmac->multi_hash2);
1089                 writel(hash3, &rxmac->multi_hash3);
1090                 writel(hash4, &rxmac->multi_hash4);
1091         }
1092 }
1093 
1094 static void et1310_setup_device_for_unicast(struct et131x_adapter *adapter)
1095 {
1096         struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1097         u32 uni_pf1;
1098         u32 uni_pf2;
1099         u32 uni_pf3;
1100         u32 pm_csr;
1101 
1102         /* Set up unicast packet filter reg 3 to be the first two octets of
1103          * the MAC address for both address
1104          *
1105          * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
1106          * MAC address for second address
1107          *
1108          * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
1109          * MAC address for first address
1110          */
1111         uni_pf3 = (adapter->addr[0] << ET_RX_UNI_PF_ADDR2_1_SHIFT) |
1112                   (adapter->addr[1] << ET_RX_UNI_PF_ADDR2_2_SHIFT) |
1113                   (adapter->addr[0] << ET_RX_UNI_PF_ADDR1_1_SHIFT) |
1114                    adapter->addr[1];
1115 
1116         uni_pf2 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR2_3_SHIFT) |
1117                   (adapter->addr[3] << ET_RX_UNI_PF_ADDR2_4_SHIFT) |
1118                   (adapter->addr[4] << ET_RX_UNI_PF_ADDR2_5_SHIFT) |
1119                    adapter->addr[5];
1120 
1121         uni_pf1 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR1_3_SHIFT) |
1122                   (adapter->addr[3] << ET_RX_UNI_PF_ADDR1_4_SHIFT) |
1123                   (adapter->addr[4] << ET_RX_UNI_PF_ADDR1_5_SHIFT) |
1124                    adapter->addr[5];
1125 
1126         pm_csr = readl(&adapter->regs->global.pm_csr);
1127         if (!et1310_in_phy_coma(adapter)) {
1128                 writel(uni_pf1, &rxmac->uni_pf_addr1);
1129                 writel(uni_pf2, &rxmac->uni_pf_addr2);
1130                 writel(uni_pf3, &rxmac->uni_pf_addr3);
1131         }
1132 }
1133 
1134 static void et1310_config_rxmac_regs(struct et131x_adapter *adapter)
1135 {
1136         struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1137         struct phy_device *phydev = adapter->phydev;
1138         u32 sa_lo;
1139         u32 sa_hi = 0;
1140         u32 pf_ctrl = 0;
1141 
1142         /* Disable the MAC while it is being configured (also disable WOL) */
1143         writel(0x8, &rxmac->ctrl);
1144 
1145         /* Initialize WOL to disabled. */
1146         writel(0, &rxmac->crc0);
1147         writel(0, &rxmac->crc12);
1148         writel(0, &rxmac->crc34);
1149 
1150         /* We need to set the WOL mask0 - mask4 next.  We initialize it to
1151          * its default Values of 0x00000000 because there are not WOL masks
1152          * as of this time.
1153          */
1154         writel(0, &rxmac->mask0_word0);
1155         writel(0, &rxmac->mask0_word1);
1156         writel(0, &rxmac->mask0_word2);
1157         writel(0, &rxmac->mask0_word3);
1158 
1159         writel(0, &rxmac->mask1_word0);
1160         writel(0, &rxmac->mask1_word1);
1161         writel(0, &rxmac->mask1_word2);
1162         writel(0, &rxmac->mask1_word3);
1163 
1164         writel(0, &rxmac->mask2_word0);
1165         writel(0, &rxmac->mask2_word1);
1166         writel(0, &rxmac->mask2_word2);
1167         writel(0, &rxmac->mask2_word3);
1168 
1169         writel(0, &rxmac->mask3_word0);
1170         writel(0, &rxmac->mask3_word1);
1171         writel(0, &rxmac->mask3_word2);
1172         writel(0, &rxmac->mask3_word3);
1173 
1174         writel(0, &rxmac->mask4_word0);
1175         writel(0, &rxmac->mask4_word1);
1176         writel(0, &rxmac->mask4_word2);
1177         writel(0, &rxmac->mask4_word3);
1178 
1179         /* Lets setup the WOL Source Address */
1180         sa_lo = (adapter->addr[2] << ET_RX_WOL_LO_SA3_SHIFT) |
1181                 (adapter->addr[3] << ET_RX_WOL_LO_SA4_SHIFT) |
1182                 (adapter->addr[4] << ET_RX_WOL_LO_SA5_SHIFT) |
1183                  adapter->addr[5];
1184         writel(sa_lo, &rxmac->sa_lo);
1185 
1186         sa_hi = (u32) (adapter->addr[0] << ET_RX_WOL_HI_SA1_SHIFT) |
1187                        adapter->addr[1];
1188         writel(sa_hi, &rxmac->sa_hi);
1189 
1190         /* Disable all Packet Filtering */
1191         writel(0, &rxmac->pf_ctrl);
1192 
1193         /* Let's initialize the Unicast Packet filtering address */
1194         if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) {
1195                 et1310_setup_device_for_unicast(adapter);
1196                 pf_ctrl |= ET_RX_PFCTRL_UNICST_FILTER_ENABLE;
1197         } else {
1198                 writel(0, &rxmac->uni_pf_addr1);
1199                 writel(0, &rxmac->uni_pf_addr2);
1200                 writel(0, &rxmac->uni_pf_addr3);
1201         }
1202 
1203         /* Let's initialize the Multicast hash */
1204         if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
1205                 pf_ctrl |= ET_RX_PFCTRL_MLTCST_FILTER_ENABLE;
1206                 et1310_setup_device_for_multicast(adapter);
1207         }
1208 
1209         /* Runt packet filtering.  Didn't work in version A silicon. */
1210         pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT;
1211         pf_ctrl |= ET_RX_PFCTRL_FRAG_FILTER_ENABLE;
1212 
1213         if (adapter->registry_jumbo_packet > 8192)
1214                 /* In order to transmit jumbo packets greater than 8k, the
1215                  * FIFO between RxMAC and RxDMA needs to be reduced in size
1216                  * to (16k - Jumbo packet size).  In order to implement this,
1217                  * we must use "cut through" mode in the RxMAC, which chops
1218                  * packets down into segments which are (max_size * 16).  In
1219                  * this case we selected 256 bytes, since this is the size of
1220                  * the PCI-Express TLP's that the 1310 uses.
1221                  *
1222                  * seg_en on, fc_en off, size 0x10
1223                  */
1224                 writel(0x41, &rxmac->mcif_ctrl_max_seg);
1225         else
1226                 writel(0, &rxmac->mcif_ctrl_max_seg);
1227 
1228         /* Initialize the MCIF water marks */
1229         writel(0, &rxmac->mcif_water_mark);
1230 
1231         /*  Initialize the MIF control */
1232         writel(0, &rxmac->mif_ctrl);
1233 
1234         /* Initialize the Space Available Register */
1235         writel(0, &rxmac->space_avail);
1236 
1237         /* Initialize the the mif_ctrl register
1238          * bit 3:  Receive code error. One or more nibbles were signaled as
1239          *         errors  during the reception of the packet.  Clear this
1240          *         bit in Gigabit, set it in 100Mbit.  This was derived
1241          *         experimentally at UNH.
1242          * bit 4:  Receive CRC error. The packet's CRC did not match the
1243          *         internally generated CRC.
1244          * bit 5:  Receive length check error. Indicates that frame length
1245          *         field value in the packet does not match the actual data
1246          *         byte length and is not a type field.
1247          * bit 16: Receive frame truncated.
1248          * bit 17: Drop packet enable
1249          */
1250         if (phydev && phydev->speed == SPEED_100)
1251                 writel(0x30038, &rxmac->mif_ctrl);
1252         else
1253                 writel(0x30030, &rxmac->mif_ctrl);
1254 
1255         /* Finally we initialize RxMac to be enabled & WOL disabled.  Packet
1256          * filter is always enabled since it is where the runt packets are
1257          * supposed to be dropped.  For version A silicon, runt packet
1258          * dropping doesn't work, so it is disabled in the pf_ctrl register,
1259          * but we still leave the packet filter on.
1260          */
1261         writel(pf_ctrl, &rxmac->pf_ctrl);
1262         writel(ET_RX_CTRL_RXMAC_ENABLE | ET_RX_CTRL_WOL_DISABLE, &rxmac->ctrl);
1263 }
1264 
1265 static void et1310_config_txmac_regs(struct et131x_adapter *adapter)
1266 {
1267         struct txmac_regs __iomem *txmac = &adapter->regs->txmac;
1268 
1269         /* We need to update the Control Frame Parameters
1270          * cfpt - control frame pause timer set to 64 (0x40)
1271          * cfep - control frame extended pause timer set to 0x0
1272          */
1273         if (adapter->flowcontrol == FLOW_NONE)
1274                 writel(0, &txmac->cf_param);
1275         else
1276                 writel(0x40, &txmac->cf_param);
1277 }
1278 
1279 static void et1310_config_macstat_regs(struct et131x_adapter *adapter)
1280 {
1281         struct macstat_regs __iomem *macstat =
1282                 &adapter->regs->macstat;
1283 
1284         /* Next we need to initialize all the macstat registers to zero on
1285          * the device.
1286          */
1287         writel(0, &macstat->txrx_0_64_byte_frames);
1288         writel(0, &macstat->txrx_65_127_byte_frames);
1289         writel(0, &macstat->txrx_128_255_byte_frames);
1290         writel(0, &macstat->txrx_256_511_byte_frames);
1291         writel(0, &macstat->txrx_512_1023_byte_frames);
1292         writel(0, &macstat->txrx_1024_1518_byte_frames);
1293         writel(0, &macstat->txrx_1519_1522_gvln_frames);
1294 
1295         writel(0, &macstat->rx_bytes);
1296         writel(0, &macstat->rx_packets);
1297         writel(0, &macstat->rx_fcs_errs);
1298         writel(0, &macstat->rx_multicast_packets);
1299         writel(0, &macstat->rx_broadcast_packets);
1300         writel(0, &macstat->rx_control_frames);
1301         writel(0, &macstat->rx_pause_frames);
1302         writel(0, &macstat->rx_unknown_opcodes);
1303         writel(0, &macstat->rx_align_errs);
1304         writel(0, &macstat->rx_frame_len_errs);
1305         writel(0, &macstat->rx_code_errs);
1306         writel(0, &macstat->rx_carrier_sense_errs);
1307         writel(0, &macstat->rx_undersize_packets);
1308         writel(0, &macstat->rx_oversize_packets);
1309         writel(0, &macstat->rx_fragment_packets);
1310         writel(0, &macstat->rx_jabbers);
1311         writel(0, &macstat->rx_drops);
1312 
1313         writel(0, &macstat->tx_bytes);
1314         writel(0, &macstat->tx_packets);
1315         writel(0, &macstat->tx_multicast_packets);
1316         writel(0, &macstat->tx_broadcast_packets);
1317         writel(0, &macstat->tx_pause_frames);
1318         writel(0, &macstat->tx_deferred);
1319         writel(0, &macstat->tx_excessive_deferred);
1320         writel(0, &macstat->tx_single_collisions);
1321         writel(0, &macstat->tx_multiple_collisions);
1322         writel(0, &macstat->tx_late_collisions);
1323         writel(0, &macstat->tx_excessive_collisions);
1324         writel(0, &macstat->tx_total_collisions);
1325         writel(0, &macstat->tx_pause_honored_frames);
1326         writel(0, &macstat->tx_drops);
1327         writel(0, &macstat->tx_jabbers);
1328         writel(0, &macstat->tx_fcs_errs);
1329         writel(0, &macstat->tx_control_frames);
1330         writel(0, &macstat->tx_oversize_frames);
1331         writel(0, &macstat->tx_undersize_frames);
1332         writel(0, &macstat->tx_fragments);
1333         writel(0, &macstat->carry_reg1);
1334         writel(0, &macstat->carry_reg2);
1335 
1336         /* Unmask any counters that we want to track the overflow of.
1337          * Initially this will be all counters.  It may become clear later
1338          * that we do not need to track all counters.
1339          */
1340         writel(0xFFFFBE32, &macstat->carry_reg1_mask);
1341         writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
1342 }
1343 
1344 /* et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
1345  * @adapter: pointer to our private adapter structure
1346  * @addr: the address of the transceiver
1347  * @reg: the register to read
1348  * @value: pointer to a 16-bit value in which the value will be stored
1349  */
1350 static int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
1351               u8 reg, u16 *value)
1352 {
1353         struct mac_regs __iomem *mac = &adapter->regs->mac;
1354         int status = 0;
1355         u32 delay = 0;
1356         u32 mii_addr;
1357         u32 mii_cmd;
1358         u32 mii_indicator;
1359 
1360         /* Save a local copy of the registers we are dealing with so we can
1361          * set them back
1362          */
1363         mii_addr = readl(&mac->mii_mgmt_addr);
1364         mii_cmd = readl(&mac->mii_mgmt_cmd);
1365 
1366         /* Stop the current operation */
1367         writel(0, &mac->mii_mgmt_cmd);
1368 
1369         /* Set up the register we need to read from on the correct PHY */
1370         writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1371 
1372         writel(0x1, &mac->mii_mgmt_cmd);
1373 
1374         do {
1375                 udelay(50);
1376                 delay++;
1377                 mii_indicator = readl(&mac->mii_mgmt_indicator);
1378         } while ((mii_indicator & ET_MAC_MGMT_WAIT) && delay < 50);
1379 
1380         /* If we hit the max delay, we could not read the register */
1381         if (delay == 50) {
1382                 dev_warn(&adapter->pdev->dev,
1383                             "reg 0x%08x could not be read\n", reg);
1384                 dev_warn(&adapter->pdev->dev, "status is  0x%08x\n",
1385                             mii_indicator);
1386 
1387                 status = -EIO;
1388                 goto out;
1389         }
1390 
1391         /* If we hit here we were able to read the register and we need to
1392          * return the value to the caller
1393          */
1394         *value = readl(&mac->mii_mgmt_stat) & ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK;
1395 
1396 out:
1397         /* Stop the read operation */
1398         writel(0, &mac->mii_mgmt_cmd);
1399 
1400         /* set the registers we touched back to the state at which we entered
1401          * this function
1402          */
1403         writel(mii_addr, &mac->mii_mgmt_addr);
1404         writel(mii_cmd, &mac->mii_mgmt_cmd);
1405 
1406         return status;
1407 }
1408 
1409 static int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
1410 {
1411         struct phy_device *phydev = adapter->phydev;
1412 
1413         if (!phydev)
1414                 return -EIO;
1415 
1416         return et131x_phy_mii_read(adapter, phydev->addr, reg, value);
1417 }
1418 
1419 /* et131x_mii_write - Write to a PHY reg through the MII interface of the MAC
1420  * @adapter: pointer to our private adapter structure
1421  * @reg: the register to read
1422  * @value: 16-bit value to write
1423  */
1424 static int et131x_mii_write(struct et131x_adapter *adapter, u8 addr, u8 reg,
1425                             u16 value)
1426 {
1427         struct mac_regs __iomem *mac = &adapter->regs->mac;
1428         int status = 0;
1429         u32 delay = 0;
1430         u32 mii_addr;
1431         u32 mii_cmd;
1432         u32 mii_indicator;
1433 
1434         /* Save a local copy of the registers we are dealing with so we can
1435          * set them back
1436          */
1437         mii_addr = readl(&mac->mii_mgmt_addr);
1438         mii_cmd = readl(&mac->mii_mgmt_cmd);
1439 
1440         /* Stop the current operation */
1441         writel(0, &mac->mii_mgmt_cmd);
1442 
1443         /* Set up the register we need to write to on the correct PHY */
1444         writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1445 
1446         /* Add the value to write to the registers to the mac */
1447         writel(value, &mac->mii_mgmt_ctrl);
1448 
1449         do {
1450                 udelay(50);
1451                 delay++;
1452                 mii_indicator = readl(&mac->mii_mgmt_indicator);
1453         } while ((mii_indicator & ET_MAC_MGMT_BUSY) && delay < 100);
1454 
1455         /* If we hit the max delay, we could not write the register */
1456         if (delay == 100) {
1457                 u16 tmp;
1458 
1459                 dev_warn(&adapter->pdev->dev,
1460                     "reg 0x%08x could not be written", reg);
1461                 dev_warn(&adapter->pdev->dev, "status is  0x%08x\n",
1462                             mii_indicator);
1463                 dev_warn(&adapter->pdev->dev, "command is  0x%08x\n",
1464                             readl(&mac->mii_mgmt_cmd));
1465 
1466                 et131x_mii_read(adapter, reg, &tmp);
1467 
1468                 status = -EIO;
1469         }
1470         /* Stop the write operation */
1471         writel(0, &mac->mii_mgmt_cmd);
1472 
1473         /* set the registers we touched back to the state at which we entered
1474          * this function
1475          */
1476         writel(mii_addr, &mac->mii_mgmt_addr);
1477         writel(mii_cmd, &mac->mii_mgmt_cmd);
1478 
1479         return status;
1480 }
1481 
1482 static void et1310_phy_read_mii_bit(struct et131x_adapter *adapter,
1483                                     u16 regnum,
1484                                     u16 bitnum,
1485                                     u8 *value)
1486 {
1487         u16 reg;
1488         u16 mask = 1 << bitnum;
1489 
1490         /* Read the requested register */
1491         et131x_mii_read(adapter, regnum, &reg);
1492 
1493         *value = (reg & mask) >> bitnum;
1494 }
1495 
1496 static void et1310_config_flow_control(struct et131x_adapter *adapter)
1497 {
1498         struct phy_device *phydev = adapter->phydev;
1499 
1500         if (phydev->duplex == DUPLEX_HALF) {
1501                 adapter->flowcontrol = FLOW_NONE;
1502         } else {
1503                 char remote_pause, remote_async_pause;
1504 
1505                 et1310_phy_read_mii_bit(adapter, 5, 10, &remote_pause);
1506                 et1310_phy_read_mii_bit(adapter, 5, 11, &remote_async_pause);
1507 
1508                 if (remote_pause && remote_async_pause) {
1509                         adapter->flowcontrol = adapter->wanted_flow;
1510                 } else if (remote_pause && !remote_async_pause) {
1511                         if (adapter->wanted_flow == FLOW_BOTH)
1512                                 adapter->flowcontrol = FLOW_BOTH;
1513                         else
1514                                 adapter->flowcontrol = FLOW_NONE;
1515                 } else if (!remote_pause && !remote_async_pause) {
1516                         adapter->flowcontrol = FLOW_NONE;
1517                 } else {
1518                         if (adapter->wanted_flow == FLOW_BOTH)
1519                                 adapter->flowcontrol = FLOW_RXONLY;
1520                         else
1521                                 adapter->flowcontrol = FLOW_NONE;
1522                 }
1523         }
1524 }
1525 
1526 /* et1310_update_macstat_host_counters - Update local copy of the statistics */
1527 static void et1310_update_macstat_host_counters(struct et131x_adapter *adapter)
1528 {
1529         struct ce_stats *stats = &adapter->stats;
1530         struct macstat_regs __iomem *macstat =
1531                 &adapter->regs->macstat;
1532 
1533         stats->tx_collisions           += readl(&macstat->tx_total_collisions);
1534         stats->tx_first_collisions     += readl(&macstat->tx_single_collisions);
1535         stats->tx_deferred             += readl(&macstat->tx_deferred);
1536         stats->tx_excessive_collisions +=
1537                                 readl(&macstat->tx_multiple_collisions);
1538         stats->tx_late_collisions      += readl(&macstat->tx_late_collisions);
1539         stats->tx_underflows           += readl(&macstat->tx_undersize_frames);
1540         stats->tx_max_pkt_errs         += readl(&macstat->tx_oversize_frames);
1541 
1542         stats->rx_align_errs        += readl(&macstat->rx_align_errs);
1543         stats->rx_crc_errs          += readl(&macstat->rx_code_errs);
1544         stats->rcvd_pkts_dropped    += readl(&macstat->rx_drops);
1545         stats->rx_overflows         += readl(&macstat->rx_oversize_packets);
1546         stats->rx_code_violations   += readl(&macstat->rx_fcs_errs);
1547         stats->rx_length_errs       += readl(&macstat->rx_frame_len_errs);
1548         stats->rx_other_errs        += readl(&macstat->rx_fragment_packets);
1549 }
1550 
1551 /* et1310_handle_macstat_interrupt
1552  *
1553  * One of the MACSTAT counters has wrapped.  Update the local copy of
1554  * the statistics held in the adapter structure, checking the "wrap"
1555  * bit for each counter.
1556  */
1557 static void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter)
1558 {
1559         u32 carry_reg1;
1560         u32 carry_reg2;
1561 
1562         /* Read the interrupt bits from the register(s).  These are Clear On
1563          * Write.
1564          */
1565         carry_reg1 = readl(&adapter->regs->macstat.carry_reg1);
1566         carry_reg2 = readl(&adapter->regs->macstat.carry_reg2);
1567 
1568         writel(carry_reg1, &adapter->regs->macstat.carry_reg1);
1569         writel(carry_reg2, &adapter->regs->macstat.carry_reg2);
1570 
1571         /* We need to do update the host copy of all the MAC_STAT counters.
1572          * For each counter, check it's overflow bit.  If the overflow bit is
1573          * set, then increment the host version of the count by one complete
1574          * revolution of the counter.  This routine is called when the counter
1575          * block indicates that one of the counters has wrapped.
1576          */
1577         if (carry_reg1 & (1 << 14))
1578                 adapter->stats.rx_code_violations       += COUNTER_WRAP_16_BIT;
1579         if (carry_reg1 & (1 << 8))
1580                 adapter->stats.rx_align_errs    += COUNTER_WRAP_12_BIT;
1581         if (carry_reg1 & (1 << 7))
1582                 adapter->stats.rx_length_errs   += COUNTER_WRAP_16_BIT;
1583         if (carry_reg1 & (1 << 2))
1584                 adapter->stats.rx_other_errs    += COUNTER_WRAP_16_BIT;
1585         if (carry_reg1 & (1 << 6))
1586                 adapter->stats.rx_crc_errs      += COUNTER_WRAP_16_BIT;
1587         if (carry_reg1 & (1 << 3))
1588                 adapter->stats.rx_overflows     += COUNTER_WRAP_16_BIT;
1589         if (carry_reg1 & (1 << 0))
1590                 adapter->stats.rcvd_pkts_dropped        += COUNTER_WRAP_16_BIT;
1591         if (carry_reg2 & (1 << 16))
1592                 adapter->stats.tx_max_pkt_errs  += COUNTER_WRAP_12_BIT;
1593         if (carry_reg2 & (1 << 15))
1594                 adapter->stats.tx_underflows    += COUNTER_WRAP_12_BIT;
1595         if (carry_reg2 & (1 << 6))
1596                 adapter->stats.tx_first_collisions += COUNTER_WRAP_12_BIT;
1597         if (carry_reg2 & (1 << 8))
1598                 adapter->stats.tx_deferred      += COUNTER_WRAP_12_BIT;
1599         if (carry_reg2 & (1 << 5))
1600                 adapter->stats.tx_excessive_collisions += COUNTER_WRAP_12_BIT;
1601         if (carry_reg2 & (1 << 4))
1602                 adapter->stats.tx_late_collisions       += COUNTER_WRAP_12_BIT;
1603         if (carry_reg2 & (1 << 2))
1604                 adapter->stats.tx_collisions    += COUNTER_WRAP_12_BIT;
1605 }
1606 
1607 static int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg)
1608 {
1609         struct net_device *netdev = bus->priv;
1610         struct et131x_adapter *adapter = netdev_priv(netdev);
1611         u16 value;
1612         int ret;
1613 
1614         ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value);
1615 
1616         if (ret < 0)
1617                 return ret;
1618         else
1619                 return value;
1620 }
1621 
1622 static int et131x_mdio_write(struct mii_bus *bus, int phy_addr,
1623                              int reg, u16 value)
1624 {
1625         struct net_device *netdev = bus->priv;
1626         struct et131x_adapter *adapter = netdev_priv(netdev);
1627 
1628         return et131x_mii_write(adapter, phy_addr, reg, value);
1629 }
1630 
1631 /*      et1310_phy_power_switch -       PHY power control
1632  *      @adapter: device to control
1633  *      @down: true for off/false for back on
1634  *
1635  *      one hundred, ten, one thousand megs
1636  *      How would you like to have your LAN accessed
1637  *      Can't you see that this code processed
1638  *      Phy power, phy power..
1639  */
1640 static void et1310_phy_power_switch(struct et131x_adapter *adapter, bool down)
1641 {
1642         u16 data;
1643         struct  phy_device *phydev = adapter->phydev;
1644 
1645         et131x_mii_read(adapter, MII_BMCR, &data);
1646         data &= ~BMCR_PDOWN;
1647         if (down)
1648                 data |= BMCR_PDOWN;
1649         et131x_mii_write(adapter, phydev->addr, MII_BMCR, data);
1650 }
1651 
1652 /* et131x_xcvr_init - Init the phy if we are setting it into force mode */
1653 static void et131x_xcvr_init(struct et131x_adapter *adapter)
1654 {
1655         u16 lcr2;
1656         struct  phy_device *phydev = adapter->phydev;
1657 
1658         /* Set the LED behavior such that LED 1 indicates speed (off =
1659          * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
1660          * link and activity (on for link, blink off for activity).
1661          *
1662          * NOTE: Some customizations have been added here for specific
1663          * vendors; The LED behavior is now determined by vendor data in the
1664          * EEPROM. However, the above description is the default.
1665          */
1666         if ((adapter->eeprom_data[1] & 0x4) == 0) {
1667                 et131x_mii_read(adapter, PHY_LED_2, &lcr2);
1668 
1669                 lcr2 &= (ET_LED2_LED_100TX | ET_LED2_LED_1000T);
1670                 lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT);
1671 
1672                 if ((adapter->eeprom_data[1] & 0x8) == 0)
1673                         lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT);
1674                 else
1675                         lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT);
1676 
1677                 et131x_mii_write(adapter, phydev->addr, PHY_LED_2, lcr2);
1678         }
1679 }
1680 
1681 /* et131x_configure_global_regs - configure JAGCore global regs
1682  *
1683  * Used to configure the global registers on the JAGCore
1684  */
1685 static void et131x_configure_global_regs(struct et131x_adapter *adapter)
1686 {
1687         struct global_regs __iomem *regs = &adapter->regs->global;
1688 
1689         writel(0, &regs->rxq_start_addr);
1690         writel(INTERNAL_MEM_SIZE - 1, &regs->txq_end_addr);
1691 
1692         if (adapter->registry_jumbo_packet < 2048) {
1693                 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
1694                  * block of RAM that the driver can split between Tx
1695                  * and Rx as it desires.  Our default is to split it
1696                  * 50/50:
1697                  */
1698                 writel(PARM_RX_MEM_END_DEF, &regs->rxq_end_addr);
1699                 writel(PARM_RX_MEM_END_DEF + 1, &regs->txq_start_addr);
1700         } else if (adapter->registry_jumbo_packet < 8192) {
1701                 /* For jumbo packets > 2k but < 8k, split 50-50. */
1702                 writel(INTERNAL_MEM_RX_OFFSET, &regs->rxq_end_addr);
1703                 writel(INTERNAL_MEM_RX_OFFSET + 1, &regs->txq_start_addr);
1704         } else {
1705                 /* 9216 is the only packet size greater than 8k that
1706                  * is available. The Tx buffer has to be big enough
1707                  * for one whole packet on the Tx side. We'll make
1708                  * the Tx 9408, and give the rest to Rx
1709                  */
1710                 writel(0x01b3, &regs->rxq_end_addr);
1711                 writel(0x01b4, &regs->txq_start_addr);
1712         }
1713 
1714         /* Initialize the loopback register. Disable all loopbacks. */
1715         writel(0, &regs->loopback);
1716 
1717         /* MSI Register */
1718         writel(0, &regs->msi_config);
1719 
1720         /* By default, disable the watchdog timer.  It will be enabled when
1721          * a packet is queued.
1722          */
1723         writel(0, &regs->watchdog_timer);
1724 }
1725 
1726 /* et131x_config_rx_dma_regs - Start of Rx_DMA init sequence */
1727 static void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
1728 {
1729         struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
1730         struct rx_ring *rx_local = &adapter->rx_ring;
1731         struct fbr_desc *fbr_entry;
1732         u32 entry;
1733         u32 psr_num_des;
1734         unsigned long flags;
1735         u8 id;
1736 
1737         /* Halt RXDMA to perform the reconfigure.  */
1738         et131x_rx_dma_disable(adapter);
1739 
1740         /* Load the completion writeback physical address */
1741         writel(upper_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_hi);
1742         writel(lower_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_lo);
1743 
1744         memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block));
1745 
1746         /* Set the address and parameters of the packet status ring into the
1747          * 1310's registers
1748          */
1749         writel(upper_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_hi);
1750         writel(lower_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_lo);
1751         writel(rx_local->psr_num_entries - 1, &rx_dma->psr_num_des);
1752         writel(0, &rx_dma->psr_full_offset);
1753 
1754         psr_num_des = readl(&rx_dma->psr_num_des) & ET_RXDMA_PSR_NUM_DES_MASK;
1755         writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
1756                &rx_dma->psr_min_des);
1757 
1758         spin_lock_irqsave(&adapter->rcv_lock, flags);
1759 
1760         /* These local variables track the PSR in the adapter structure */
1761         rx_local->local_psr_full = 0;
1762 
1763         for (id = 0; id < NUM_FBRS; id++) {
1764                 u32 __iomem *num_des;
1765                 u32 __iomem *full_offset;
1766                 u32 __iomem *min_des;
1767                 u32 __iomem *base_hi;
1768                 u32 __iomem *base_lo;
1769                 struct fbr_lookup *fbr = rx_local->fbr[id];
1770 
1771                 if (id == 0) {
1772                         num_des = &rx_dma->fbr0_num_des;
1773                         full_offset = &rx_dma->fbr0_full_offset;
1774                         min_des = &rx_dma->fbr0_min_des;
1775                         base_hi = &rx_dma->fbr0_base_hi;
1776                         base_lo = &rx_dma->fbr0_base_lo;
1777                 } else {
1778                         num_des = &rx_dma->fbr1_num_des;
1779                         full_offset = &rx_dma->fbr1_full_offset;
1780                         min_des = &rx_dma->fbr1_min_des;
1781                         base_hi = &rx_dma->fbr1_base_hi;
1782                         base_lo = &rx_dma->fbr1_base_lo;
1783                 }
1784 
1785                 /* Now's the best time to initialize FBR contents */
1786                 fbr_entry = fbr->ring_virtaddr;
1787                 for (entry = 0; entry < fbr->num_entries; entry++) {
1788                         fbr_entry->addr_hi = fbr->bus_high[entry];
1789                         fbr_entry->addr_lo = fbr->bus_low[entry];
1790                         fbr_entry->word2 = entry;
1791                         fbr_entry++;
1792                 }
1793 
1794                 /* Set the address and parameters of Free buffer ring 1 and 0
1795                  * into the 1310's registers
1796                  */
1797                 writel(upper_32_bits(fbr->ring_physaddr), base_hi);
1798                 writel(lower_32_bits(fbr->ring_physaddr), base_lo);
1799                 writel(fbr->num_entries - 1, num_des);
1800                 writel(ET_DMA10_WRAP, full_offset);
1801 
1802                 /* This variable tracks the free buffer ring 1 full position,
1803                  * so it has to match the above.
1804                  */
1805                 fbr->local_full = ET_DMA10_WRAP;
1806                 writel(((fbr->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
1807                        min_des);
1808         }
1809 
1810         /* Program the number of packets we will receive before generating an
1811          * interrupt.
1812          * For version B silicon, this value gets updated once autoneg is
1813          *complete.
1814          */
1815         writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
1816 
1817         /* The "time_done" is not working correctly to coalesce interrupts
1818          * after a given time period, but rather is giving us an interrupt
1819          * regardless of whether we have received packets.
1820          * This value gets updated once autoneg is complete.
1821          */
1822         writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
1823 
1824         spin_unlock_irqrestore(&adapter->rcv_lock, flags);
1825 }
1826 
1827 /* et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
1828  *
1829  * Configure the transmit engine with the ring buffers we have created
1830  * and prepare it for use.
1831  */
1832 static void et131x_config_tx_dma_regs(struct et131x_adapter *adapter)
1833 {
1834         struct txdma_regs __iomem *txdma = &adapter->regs->txdma;
1835         struct tx_ring *tx_ring = &adapter->tx_ring;
1836 
1837         /* Load the hardware with the start of the transmit descriptor ring. */
1838         writel(upper_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_hi);
1839         writel(lower_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_lo);
1840 
1841         /* Initialise the transmit DMA engine */
1842         writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
1843 
1844         /* Load the completion writeback physical address */
1845         writel(upper_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_hi);
1846         writel(lower_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_lo);
1847 
1848         *tx_ring->tx_status = 0;
1849 
1850         writel(0, &txdma->service_request);
1851         tx_ring->send_idx = 0;
1852 }
1853 
1854 /* et131x_adapter_setup - Set the adapter up as per cassini+ documentation */
1855 static void et131x_adapter_setup(struct et131x_adapter *adapter)
1856 {
1857         /* Configure the JAGCore */
1858         et131x_configure_global_regs(adapter);
1859 
1860         et1310_config_mac_regs1(adapter);
1861 
1862         /* Configure the MMC registers */
1863         /* All we need to do is initialize the Memory Control Register */
1864         writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
1865 
1866         et1310_config_rxmac_regs(adapter);
1867         et1310_config_txmac_regs(adapter);
1868 
1869         et131x_config_rx_dma_regs(adapter);
1870         et131x_config_tx_dma_regs(adapter);
1871 
1872         et1310_config_macstat_regs(adapter);
1873 
1874         et1310_phy_power_switch(adapter, 0);
1875         et131x_xcvr_init(adapter);
1876 }
1877 
1878 /* et131x_soft_reset - Issue soft reset to the hardware, complete for ET1310 */
1879 static void et131x_soft_reset(struct et131x_adapter *adapter)
1880 {
1881         u32 reg;
1882 
1883         /* Disable MAC Core */
1884         reg = ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET |
1885               ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
1886               ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC;
1887         writel(reg, &adapter->regs->mac.cfg1);
1888 
1889         reg = ET_RESET_ALL;
1890         writel(reg, &adapter->regs->global.sw_reset);
1891 
1892         reg = ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
1893               ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC;
1894         writel(reg, &adapter->regs->mac.cfg1);
1895         writel(0, &adapter->regs->mac.cfg1);
1896 }
1897 
1898 /*      et131x_enable_interrupts        -       enable interrupt
1899  *
1900  *      Enable the appropriate interrupts on the ET131x according to our
1901  *      configuration
1902  */
1903 static void et131x_enable_interrupts(struct et131x_adapter *adapter)
1904 {
1905         u32 mask;
1906 
1907         /* Enable all global interrupts */
1908         if (adapter->flowcontrol == FLOW_TXONLY ||
1909             adapter->flowcontrol == FLOW_BOTH)
1910                 mask = INT_MASK_ENABLE;
1911         else
1912                 mask = INT_MASK_ENABLE_NO_FLOW;
1913 
1914         writel(mask, &adapter->regs->global.int_mask);
1915 }
1916 
1917 /*      et131x_disable_interrupts       -       interrupt disable
1918  *
1919  *      Block all interrupts from the et131x device at the device itself
1920  */
1921 static void et131x_disable_interrupts(struct et131x_adapter *adapter)
1922 {
1923         /* Disable all global interrupts */
1924         writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
1925 }
1926 
1927 /* et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310 */
1928 static void et131x_tx_dma_disable(struct et131x_adapter *adapter)
1929 {
1930         /* Setup the transmit dma configuration register */
1931         writel(ET_TXDMA_CSR_HALT | ET_TXDMA_SNGL_EPKT,
1932                                         &adapter->regs->txdma.csr);
1933 }
1934 
1935 /* et131x_enable_txrx - Enable tx/rx queues */
1936 static void et131x_enable_txrx(struct net_device *netdev)
1937 {
1938         struct et131x_adapter *adapter = netdev_priv(netdev);
1939 
1940         /* Enable the Tx and Rx DMA engines (if not already enabled) */
1941         et131x_rx_dma_enable(adapter);
1942         et131x_tx_dma_enable(adapter);
1943 
1944         /* Enable device interrupts */
1945         if (adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE)
1946                 et131x_enable_interrupts(adapter);
1947 
1948         /* We're ready to move some data, so start the queue */
1949         netif_start_queue(netdev);
1950 }
1951 
1952 /* et131x_disable_txrx - Disable tx/rx queues */
1953 static void et131x_disable_txrx(struct net_device *netdev)
1954 {
1955         struct et131x_adapter *adapter = netdev_priv(netdev);
1956 
1957         /* First thing is to stop the queue */
1958         netif_stop_queue(netdev);
1959 
1960         /* Stop the Tx and Rx DMA engines */
1961         et131x_rx_dma_disable(adapter);
1962         et131x_tx_dma_disable(adapter);
1963 
1964         /* Disable device interrupts */
1965         et131x_disable_interrupts(adapter);
1966 }
1967 
1968 /* et131x_init_send - Initialize send data structures */
1969 static void et131x_init_send(struct et131x_adapter *adapter)
1970 {
1971         u32 ct;
1972         struct tx_ring *tx_ring = &adapter->tx_ring;
1973         struct tcb *tcb = tx_ring->tcb_ring;
1974 
1975         tx_ring->tcb_qhead = tcb;
1976 
1977         memset(tcb, 0, sizeof(struct tcb) * NUM_TCB);
1978 
1979         /* Go through and set up each TCB */
1980         for (ct = 0; ct++ < NUM_TCB; tcb++)
1981                 /* Set the link pointer in HW TCB to the next TCB in the
1982                  * chain
1983                  */
1984                 tcb->next = tcb + 1;
1985 
1986         /* Set the  tail pointer */
1987         tcb--;
1988         tx_ring->tcb_qtail = tcb;
1989         tcb->next = NULL;
1990         /* Curr send queue should now be empty */
1991         tx_ring->send_head = NULL;
1992         tx_ring->send_tail = NULL;
1993 }
1994 
1995 /* et1310_enable_phy_coma - called when network cable is unplugged
1996  *
1997  * driver receive an phy status change interrupt while in D0 and check that
1998  * phy_status is down.
1999  *
2000  *          -- gate off JAGCore;
2001  *          -- set gigE PHY in Coma mode
2002  *          -- wake on phy_interrupt; Perform software reset JAGCore,
2003  *             re-initialize jagcore and gigE PHY
2004  *
2005  *      Add D0-ASPM-PhyLinkDown Support:
2006  *          -- while in D0, when there is a phy_interrupt indicating phy link
2007  *             down status, call the MPSetPhyComa routine to enter this active
2008  *             state power saving mode
2009  *          -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
2010  *       indicating linkup status, call the MPDisablePhyComa routine to
2011  *             restore JAGCore and gigE PHY
2012  */
2013 static void et1310_enable_phy_coma(struct et131x_adapter *adapter)
2014 {
2015         unsigned long flags;
2016         u32 pmcsr;
2017 
2018         pmcsr = readl(&adapter->regs->global.pm_csr);
2019 
2020         /* Save the GbE PHY speed and duplex modes. Need to restore this
2021          * when cable is plugged back in
2022          */
2023 
2024         /* Stop sending packets. */
2025         spin_lock_irqsave(&adapter->send_hw_lock, flags);
2026         adapter->flags |= FMP_ADAPTER_LOWER_POWER;
2027         spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
2028 
2029         /* Wait for outstanding Receive packets */
2030 
2031         et131x_disable_txrx(adapter->netdev);
2032 
2033         /* Gate off JAGCore 3 clock domains */
2034         pmcsr &= ~ET_PMCSR_INIT;
2035         writel(pmcsr, &adapter->regs->global.pm_csr);
2036 
2037         /* Program gigE PHY in to Coma mode */
2038         pmcsr |= ET_PM_PHY_SW_COMA;
2039         writel(pmcsr, &adapter->regs->global.pm_csr);
2040 }
2041 
2042 /* et1310_disable_phy_coma - Disable the Phy Coma Mode */
2043 static void et1310_disable_phy_coma(struct et131x_adapter *adapter)
2044 {
2045         u32 pmcsr;
2046 
2047         pmcsr = readl(&adapter->regs->global.pm_csr);
2048 
2049         /* Disable phy_sw_coma register and re-enable JAGCore clocks */
2050         pmcsr |= ET_PMCSR_INIT;
2051         pmcsr &= ~ET_PM_PHY_SW_COMA;
2052         writel(pmcsr, &adapter->regs->global.pm_csr);
2053 
2054         /* Restore the GbE PHY speed and duplex modes;
2055          * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
2056          */
2057 
2058         /* Re-initialize the send structures */
2059         et131x_init_send(adapter);
2060 
2061         /* Bring the device back to the state it was during init prior to
2062          * autonegotiation being complete.  This way, when we get the auto-neg
2063          * complete interrupt, we can complete init by calling ConfigMacREGS2.
2064          */
2065         et131x_soft_reset(adapter);
2066 
2067         /* setup et1310 as per the documentation ?? */
2068         et131x_adapter_setup(adapter);
2069 
2070         /* Allow Tx to restart */
2071         adapter->flags &= ~FMP_ADAPTER_LOWER_POWER;
2072 
2073         et131x_enable_txrx(adapter->netdev);
2074 }
2075 
2076 static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit)
2077 {
2078         u32 tmp_free_buff_ring = *free_buff_ring;
2079 
2080         tmp_free_buff_ring++;
2081         /* This works for all cases where limit < 1024. The 1023 case
2082          * works because 1023++ is 1024 which means the if condition is not
2083          * taken but the carry of the bit into the wrap bit toggles the wrap
2084          * value correctly
2085          */
2086         if ((tmp_free_buff_ring & ET_DMA10_MASK) > limit) {
2087                 tmp_free_buff_ring &= ~ET_DMA10_MASK;
2088                 tmp_free_buff_ring ^= ET_DMA10_WRAP;
2089         }
2090         /* For the 1023 case */
2091         tmp_free_buff_ring &= (ET_DMA10_MASK | ET_DMA10_WRAP);
2092         *free_buff_ring = tmp_free_buff_ring;
2093         return tmp_free_buff_ring;
2094 }
2095 
2096 /* et131x_rx_dma_memory_alloc
2097  *
2098  * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
2099  * and the Packet Status Ring.
2100  */
2101 static int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
2102 {
2103         u8 id;
2104         u32 i, j;
2105         u32 bufsize;
2106         u32 pktstat_ringsize;
2107         u32 fbr_chunksize;
2108         struct rx_ring *rx_ring = &adapter->rx_ring;
2109         struct fbr_lookup *fbr;
2110 
2111         /* Alloc memory for the lookup table */
2112         rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
2113         if (rx_ring->fbr[0] == NULL)
2114                 return -ENOMEM;
2115         rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
2116         if (rx_ring->fbr[1] == NULL)
2117                 return -ENOMEM;
2118 
2119         /* The first thing we will do is configure the sizes of the buffer
2120          * rings. These will change based on jumbo packet support.  Larger
2121          * jumbo packets increases the size of each entry in FBR0, and the
2122          * number of entries in FBR0, while at the same time decreasing the
2123          * number of entries in FBR1.
2124          *
2125          * FBR1 holds "large" frames, FBR0 holds "small" frames.  If FBR1
2126          * entries are huge in order to accommodate a "jumbo" frame, then it
2127          * will have less entries.  Conversely, FBR1 will now be relied upon
2128          * to carry more "normal" frames, thus it's entry size also increases
2129          * and the number of entries goes up too (since it now carries
2130          * "small" + "regular" packets.
2131          *
2132          * In this scheme, we try to maintain 512 entries between the two
2133          * rings. Also, FBR1 remains a constant size - when it's size doubles
2134          * the number of entries halves.  FBR0 increases in size, however.
2135          */
2136 
2137         if (adapter->registry_jumbo_packet < 2048) {
2138                 rx_ring->fbr[0]->buffsize = 256;
2139                 rx_ring->fbr[0]->num_entries = 512;
2140                 rx_ring->fbr[1]->buffsize = 2048;
2141                 rx_ring->fbr[1]->num_entries = 512;
2142         } else if (adapter->registry_jumbo_packet < 4096) {
2143                 rx_ring->fbr[0]->buffsize = 512;
2144                 rx_ring->fbr[0]->num_entries = 1024;
2145                 rx_ring->fbr[1]->buffsize = 4096;
2146                 rx_ring->fbr[1]->num_entries = 512;
2147         } else {
2148                 rx_ring->fbr[0]->buffsize = 1024;
2149                 rx_ring->fbr[0]->num_entries = 768;
2150                 rx_ring->fbr[1]->buffsize = 16384;
2151                 rx_ring->fbr[1]->num_entries = 128;
2152         }
2153 
2154         rx_ring->psr_num_entries = rx_ring->fbr[0]->num_entries +
2155                                    rx_ring->fbr[1]->num_entries;
2156 
2157         for (id = 0; id < NUM_FBRS; id++) {
2158                 fbr = rx_ring->fbr[id];
2159                 /* Allocate an area of memory for Free Buffer Ring */
2160                 bufsize = sizeof(struct fbr_desc) * fbr->num_entries;
2161                 fbr->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2162                                                         bufsize,
2163                                                         &fbr->ring_physaddr,
2164                                                         GFP_KERNEL);
2165                 if (!fbr->ring_virtaddr) {
2166                         dev_err(&adapter->pdev->dev,
2167                            "Cannot alloc memory for Free Buffer Ring %d\n", id);
2168                         return -ENOMEM;
2169                 }
2170         }
2171 
2172         for (id = 0; id < NUM_FBRS; id++) {
2173                 fbr = rx_ring->fbr[id];
2174                 fbr_chunksize = (FBR_CHUNKS * fbr->buffsize);
2175 
2176                 for (i = 0; i < fbr->num_entries / FBR_CHUNKS; i++) {
2177                         dma_addr_t fbr_tmp_physaddr;
2178 
2179                         fbr->mem_virtaddrs[i] = dma_alloc_coherent(
2180                                         &adapter->pdev->dev, fbr_chunksize,
2181                                         &fbr->mem_physaddrs[i],
2182                                         GFP_KERNEL);
2183 
2184                         if (!fbr->mem_virtaddrs[i]) {
2185                                 dev_err(&adapter->pdev->dev,
2186                                         "Could not alloc memory\n");
2187                                 return -ENOMEM;
2188                         }
2189 
2190                         /* See NOTE in "Save Physical Address" comment above */
2191                         fbr_tmp_physaddr = fbr->mem_physaddrs[i];
2192 
2193                         for (j = 0; j < FBR_CHUNKS; j++) {
2194                                 u32 index = (i * FBR_CHUNKS) + j;
2195 
2196                                 /* Save the Virtual address of this index for
2197                                  * quick access later
2198                                  */
2199                                 fbr->virt[index] = (u8 *)fbr->mem_virtaddrs[i] +
2200                                                    (j * fbr->buffsize);
2201 
2202                                 /* now store the physical address in the
2203                                  * descriptor so the device can access it
2204                                  */
2205                                 fbr->bus_high[index] =
2206                                                 upper_32_bits(fbr_tmp_physaddr);
2207                                 fbr->bus_low[index] =
2208                                                 lower_32_bits(fbr_tmp_physaddr);
2209 
2210                                 fbr_tmp_physaddr += fbr->buffsize;
2211                         }
2212                 }
2213         }
2214 
2215         /* Allocate an area of memory for FIFO of Packet Status ring entries */
2216         pktstat_ringsize =
2217                 sizeof(struct pkt_stat_desc) * rx_ring->psr_num_entries;
2218 
2219         rx_ring->ps_ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2220                                                   pktstat_ringsize,
2221                                                   &rx_ring->ps_ring_physaddr,
2222                                                   GFP_KERNEL);
2223 
2224         if (!rx_ring->ps_ring_virtaddr) {
2225                 dev_err(&adapter->pdev->dev,
2226                           "Cannot alloc memory for Packet Status Ring\n");
2227                 return -ENOMEM;
2228         }
2229 
2230         /* NOTE : dma_alloc_coherent(), used above to alloc DMA regions,
2231          * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2232          * are ever returned, make sure the high part is retrieved here before
2233          * storing the adjusted address.
2234          */
2235 
2236         /* Allocate an area of memory for writeback of status information */
2237         rx_ring->rx_status_block = dma_alloc_coherent(&adapter->pdev->dev,
2238                                             sizeof(struct rx_status_block),
2239                                             &rx_ring->rx_status_bus,
2240                                             GFP_KERNEL);
2241         if (!rx_ring->rx_status_block) {
2242                 dev_err(&adapter->pdev->dev,
2243                           "Cannot alloc memory for Status Block\n");
2244                 return -ENOMEM;
2245         }
2246         rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD;
2247 
2248         /* The RFDs are going to be put on lists later on, so initialize the
2249          * lists now.
2250          */
2251         INIT_LIST_HEAD(&rx_ring->recv_list);
2252         return 0;
2253 }
2254 
2255 /* et131x_rx_dma_memory_free - Free all memory allocated within this module */
2256 static void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
2257 {
2258         u8 id;
2259         u32 index;
2260         u32 bufsize;
2261         u32 pktstat_ringsize;
2262         struct rfd *rfd;
2263         struct rx_ring *rx_ring = &adapter->rx_ring;
2264         struct fbr_lookup *fbr;
2265 
2266         /* Free RFDs and associated packet descriptors */
2267         WARN_ON(rx_ring->num_ready_recv != rx_ring->num_rfd);
2268 
2269         while (!list_empty(&rx_ring->recv_list)) {
2270                 rfd = list_entry(rx_ring->recv_list.next,
2271                                  struct rfd, list_node);
2272 
2273                 list_del(&rfd->list_node);
2274                 rfd->skb = NULL;
2275                 kfree(rfd);
2276         }
2277 
2278         /* Free Free Buffer Rings */
2279         for (id = 0; id < NUM_FBRS; id++) {
2280                 fbr = rx_ring->fbr[id];
2281 
2282                 if (!fbr || !fbr->ring_virtaddr)
2283                         continue;
2284 
2285                 /* First the packet memory */
2286                 for (index = 0;
2287                      index < fbr->num_entries / FBR_CHUNKS;
2288                      index++) {
2289                         if (fbr->mem_virtaddrs[index]) {
2290                                 bufsize = fbr->buffsize * FBR_CHUNKS;
2291 
2292                                 dma_free_coherent(&adapter->pdev->dev,
2293                                                   bufsize,
2294                                                   fbr->mem_virtaddrs[index],
2295                                                   fbr->mem_physaddrs[index]);
2296 
2297                                 fbr->mem_virtaddrs[index] = NULL;
2298                         }
2299                 }
2300 
2301                 bufsize = sizeof(struct fbr_desc) * fbr->num_entries;
2302 
2303                 dma_free_coherent(&adapter->pdev->dev,
2304                                   bufsize,
2305                                   fbr->ring_virtaddr,
2306                                   fbr->ring_physaddr);
2307 
2308                 fbr->ring_virtaddr = NULL;
2309         }
2310 
2311         /* Free Packet Status Ring */
2312         if (rx_ring->ps_ring_virtaddr) {
2313                 pktstat_ringsize = sizeof(struct pkt_stat_desc) *
2314                                         rx_ring->psr_num_entries;
2315 
2316                 dma_free_coherent(&adapter->pdev->dev, pktstat_ringsize,
2317                                     rx_ring->ps_ring_virtaddr,
2318                                     rx_ring->ps_ring_physaddr);
2319 
2320                 rx_ring->ps_ring_virtaddr = NULL;
2321         }
2322 
2323         /* Free area of memory for the writeback of status information */
2324         if (rx_ring->rx_status_block) {
2325                 dma_free_coherent(&adapter->pdev->dev,
2326                         sizeof(struct rx_status_block),
2327                         rx_ring->rx_status_block, rx_ring->rx_status_bus);
2328                 rx_ring->rx_status_block = NULL;
2329         }
2330 
2331         /* Free the FBR Lookup Table */
2332         kfree(rx_ring->fbr[0]);
2333         kfree(rx_ring->fbr[1]);
2334 
2335         /* Reset Counters */
2336         rx_ring->num_ready_recv = 0;
2337 }
2338 
2339 /* et131x_init_recv - Initialize receive data structures */
2340 static int et131x_init_recv(struct et131x_adapter *adapter)
2341 {
2342         struct rfd *rfd;
2343         u32 rfdct;
2344         struct rx_ring *rx_ring = &adapter->rx_ring;
2345 
2346         /* Setup each RFD */
2347         for (rfdct = 0; rfdct < rx_ring->num_rfd; rfdct++) {
2348                 rfd = kzalloc(sizeof(struct rfd), GFP_ATOMIC | GFP_DMA);
2349                 if (!rfd)
2350                         return -ENOMEM;
2351 
2352                 rfd->skb = NULL;
2353 
2354                 /* Add this RFD to the recv_list */
2355                 list_add_tail(&rfd->list_node, &rx_ring->recv_list);
2356 
2357                 /* Increment the available RFD's */
2358                 rx_ring->num_ready_recv++;
2359         }
2360 
2361         return 0;
2362 }
2363 
2364 /* et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate */
2365 static void et131x_set_rx_dma_timer(struct et131x_adapter *adapter)
2366 {
2367         struct phy_device *phydev = adapter->phydev;
2368 
2369         /* For version B silicon, we do not use the RxDMA timer for 10 and 100
2370          * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
2371          */
2372         if ((phydev->speed == SPEED_100) || (phydev->speed == SPEED_10)) {
2373                 writel(0, &adapter->regs->rxdma.max_pkt_time);
2374                 writel(1, &adapter->regs->rxdma.num_pkt_done);
2375         }
2376 }
2377 
2378 /* NICReturnRFD - Recycle a RFD and put it back onto the receive list
2379  * @adapter: pointer to our adapter
2380  * @rfd: pointer to the RFD
2381  */
2382 static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
2383 {
2384         struct rx_ring *rx_local = &adapter->rx_ring;
2385         struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
2386         u16 buff_index = rfd->bufferindex;
2387         u8 ring_index = rfd->ringindex;
2388         unsigned long flags;
2389         struct fbr_lookup *fbr = rx_local->fbr[ring_index];
2390 
2391         /* We don't use any of the OOB data besides status. Otherwise, we
2392          * need to clean up OOB data
2393          */
2394         if (buff_index < fbr->num_entries) {
2395                 u32 free_buff_ring;
2396                 u32 __iomem *offset;
2397                 struct fbr_desc *next;
2398 
2399                 spin_lock_irqsave(&adapter->fbr_lock, flags);
2400 
2401                 if (ring_index == 0)
2402                         offset = &rx_dma->fbr0_full_offset;
2403                 else
2404                         offset = &rx_dma->fbr1_full_offset;
2405 
2406                 next = (struct fbr_desc *)(fbr->ring_virtaddr) +
2407                        INDEX10(fbr->local_full);
2408 
2409                 /* Handle the Free Buffer Ring advancement here. Write
2410                  * the PA / Buffer Index for the returned buffer into
2411                  * the oldest (next to be freed)FBR entry
2412                  */
2413                 next->addr_hi = fbr->bus_high[buff_index];
2414                 next->addr_lo = fbr->bus_low[buff_index];
2415                 next->word2 = buff_index;
2416 
2417                 free_buff_ring = bump_free_buff_ring(&fbr->local_full,
2418                                                      fbr->num_entries - 1);
2419                 writel(free_buff_ring, offset);
2420 
2421                 spin_unlock_irqrestore(&adapter->fbr_lock, flags);
2422         } else {
2423                 dev_err(&adapter->pdev->dev,
2424                           "%s illegal Buffer Index returned\n", __func__);
2425         }
2426 
2427         /* The processing on this RFD is done, so put it back on the tail of
2428          * our list
2429          */
2430         spin_lock_irqsave(&adapter->rcv_lock, flags);
2431         list_add_tail(&rfd->list_node, &rx_local->recv_list);
2432         rx_local->num_ready_recv++;
2433         spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2434 
2435         WARN_ON(rx_local->num_ready_recv > rx_local->num_rfd);
2436 }
2437 
2438 /* nic_rx_pkts - Checks the hardware for available packets
2439  *
2440  * Returns rfd, a pointer to our MPRFD.
2441  *
2442  * Checks the hardware for available packets, using completion ring
2443  * If packets are available, it gets an RFD from the recv_list, attaches
2444  * the packet to it, puts the RFD in the RecvPendList, and also returns
2445  * the pointer to the RFD.
2446  */
2447 static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
2448 {
2449         struct rx_ring *rx_local = &adapter->rx_ring;
2450         struct rx_status_block *status;
2451         struct pkt_stat_desc *psr;
2452         struct rfd *rfd;
2453         u32 i;
2454         u8 *buf;
2455         unsigned long flags;
2456         struct list_head *element;
2457         u8 ring_index;
2458         u16 buff_index;
2459         u32 len;
2460         u32 word0;
2461         u32 word1;
2462         struct sk_buff *skb;
2463         struct fbr_lookup *fbr;
2464 
2465         /* RX Status block is written by the DMA engine prior to every
2466          * interrupt. It contains the next to be used entry in the Packet
2467          * Status Ring, and also the two Free Buffer rings.
2468          */
2469         status = rx_local->rx_status_block;
2470         word1 = status->word1 >> 16;    /* Get the useful bits */
2471 
2472         /* Check the PSR and wrap bits do not match */
2473         if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF))
2474                 return NULL; /* Looks like this ring is not updated yet */
2475 
2476         /* The packet status ring indicates that data is available. */
2477         psr = (struct pkt_stat_desc *) (rx_local->ps_ring_virtaddr) +
2478                         (rx_local->local_psr_full & 0xFFF);
2479 
2480         /* Grab any information that is required once the PSR is advanced,
2481          * since we can no longer rely on the memory being accurate
2482          */
2483         len = psr->word1 & 0xFFFF;
2484         ring_index = (psr->word1 >> 26) & 0x03;
2485         fbr = rx_local->fbr[ring_index];
2486         buff_index = (psr->word1 >> 16) & 0x3FF;
2487         word0 = psr->word0;
2488 
2489         /* Indicate that we have used this PSR entry. */
2490         /* FIXME wrap 12 */
2491         add_12bit(&rx_local->local_psr_full, 1);
2492         if (
2493           (rx_local->local_psr_full & 0xFFF) > rx_local->psr_num_entries - 1) {
2494                 /* Clear psr full and toggle the wrap bit */
2495                 rx_local->local_psr_full &=  ~0xFFF;
2496                 rx_local->local_psr_full ^= 0x1000;
2497         }
2498 
2499         writel(rx_local->local_psr_full, &adapter->regs->rxdma.psr_full_offset);
2500 
2501         if (ring_index > 1 || buff_index > fbr->num_entries - 1) {
2502                 /* Illegal buffer or ring index cannot be used by S/W*/
2503                 dev_err(&adapter->pdev->dev,
2504                         "NICRxPkts PSR Entry %d indicates length of %d and/or bad bi(%d)\n",
2505                         rx_local->local_psr_full & 0xFFF, len, buff_index);
2506                 return NULL;
2507         }
2508 
2509         /* Get and fill the RFD. */
2510         spin_lock_irqsave(&adapter->rcv_lock, flags);
2511 
2512         element = rx_local->recv_list.next;
2513         rfd = list_entry(element, struct rfd, list_node);
2514 
2515         if (!rfd) {
2516                 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2517                 return NULL;
2518         }
2519 
2520         list_del(&rfd->list_node);
2521         rx_local->num_ready_recv--;
2522 
2523         spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2524 
2525         rfd->bufferindex = buff_index;
2526         rfd->ringindex = ring_index;
2527 
2528         /* In V1 silicon, there is a bug which screws up filtering of runt
2529          * packets. Therefore runt packet filtering is disabled in the MAC and
2530          * the packets are dropped here. They are also counted here.
2531          */
2532         if (len < (NIC_MIN_PACKET_SIZE + 4)) {
2533                 adapter->stats.rx_other_errs++;
2534                 len = 0;
2535         }
2536 
2537         if (len == 0) {
2538                 rfd->len = 0;
2539                 goto out;
2540         }
2541 
2542         /* Determine if this is a multicast packet coming in */
2543         if ((word0 & ALCATEL_MULTICAST_PKT) &&
2544             !(word0 & ALCATEL_BROADCAST_PKT)) {
2545                 /* Promiscuous mode and Multicast mode are not mutually
2546                  * exclusive as was first thought. I guess Promiscuous is just
2547                  * considered a super-set of the other filters. Generally filter
2548                  * is 0x2b when in promiscuous mode.
2549                  */
2550                 if ((adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST)
2551                    && !(adapter->packet_filter & ET131X_PACKET_TYPE_PROMISCUOUS)
2552                    && !(adapter->packet_filter &
2553                                         ET131X_PACKET_TYPE_ALL_MULTICAST)) {
2554                         buf = fbr->virt[buff_index];
2555 
2556                         /* Loop through our list to see if the destination
2557                          * address of this packet matches one in our list.
2558                          */
2559                         for (i = 0; i < adapter->multicast_addr_count; i++) {
2560                                 if (buf[0] == adapter->multicast_list[i][0]
2561                                  && buf[1] == adapter->multicast_list[i][1]
2562                                  && buf[2] == adapter->multicast_list[i][2]
2563                                  && buf[3] == adapter->multicast_list[i][3]
2564                                  && buf[4] == adapter->multicast_list[i][4]
2565                                  && buf[5] == adapter->multicast_list[i][5]) {
2566                                         break;
2567                                 }
2568                         }
2569 
2570                         /* If our index is equal to the number of Multicast
2571                          * address we have, then this means we did not find this
2572                          * packet's matching address in our list. Set the len to
2573                          * zero, so we free our RFD when we return from this
2574                          * function.
2575                          */
2576                         if (i == adapter->multicast_addr_count)
2577                                 len = 0;
2578                 }
2579 
2580                 if (len > 0)
2581                         adapter->stats.multicast_pkts_rcvd++;
2582         } else if (word0 & ALCATEL_BROADCAST_PKT) {
2583                 adapter->stats.broadcast_pkts_rcvd++;
2584         } else {
2585                 /* Not sure what this counter measures in promiscuous mode.
2586                  * Perhaps we should check the MAC address to see if it is
2587                  * directed to us in promiscuous mode.
2588                  */
2589                 adapter->stats.unicast_pkts_rcvd++;
2590         }
2591 
2592         if (!len) {
2593                 rfd->len = 0;
2594                 goto out;
2595         }
2596 
2597         rfd->len = len;
2598 
2599         skb = dev_alloc_skb(rfd->len + 2);
2600         if (!skb) {
2601                 dev_err(&adapter->pdev->dev, "Couldn't alloc an SKB for Rx\n");
2602                 return NULL;
2603         }
2604 
2605         adapter->netdev->stats.rx_bytes += rfd->len;
2606 
2607         memcpy(skb_put(skb, rfd->len), fbr->virt[buff_index], rfd->len);
2608 
2609         skb->protocol = eth_type_trans(skb, adapter->netdev);
2610         skb->ip_summed = CHECKSUM_NONE;
2611         netif_rx_ni(skb);
2612 
2613 out:
2614         nic_return_rfd(adapter, rfd);
2615         return rfd;
2616 }
2617 
2618 /* et131x_handle_recv_interrupt - Interrupt handler for receive processing
2619  *
2620  * Assumption, Rcv spinlock has been acquired.
2621  */
2622 static void et131x_handle_recv_interrupt(struct et131x_adapter *adapter)
2623 {
2624         struct rfd *rfd = NULL;
2625         u32 count = 0;
2626         bool done = true;
2627         struct rx_ring *rx_ring = &adapter->rx_ring;
2628 
2629         /* Process up to available RFD's */
2630         while (count < NUM_PACKETS_HANDLED) {
2631                 if (list_empty(&rx_ring->recv_list)) {
2632                         WARN_ON(rx_ring->num_ready_recv != 0);
2633                         done = false;
2634                         break;
2635                 }
2636 
2637                 rfd = nic_rx_pkts(adapter);
2638 
2639                 if (rfd == NULL)
2640                         break;
2641 
2642                 /* Do not receive any packets until a filter has been set.
2643                  * Do not receive any packets until we have link.
2644                  * If length is zero, return the RFD in order to advance the
2645                  * Free buffer ring.
2646                  */
2647                 if (!adapter->packet_filter ||
2648                     !netif_carrier_ok(adapter->netdev) ||
2649                     rfd->len == 0)
2650                         continue;
2651 
2652                 /* Increment the number of packets we received */
2653                 adapter->netdev->stats.rx_packets++;
2654 
2655                 /* Set the status on the packet, either resources or success */
2656                 if (rx_ring->num_ready_recv < RFD_LOW_WATER_MARK)
2657                         dev_warn(&adapter->pdev->dev, "RFD's are running out\n");
2658 
2659                 count++;
2660         }
2661 
2662         if (count == NUM_PACKETS_HANDLED || !done) {
2663                 rx_ring->unfinished_receives = true;
2664                 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
2665                        &adapter->regs->global.watchdog_timer);
2666         } else
2667                 /* Watchdog timer will disable itself if appropriate. */
2668                 rx_ring->unfinished_receives = false;
2669 }
2670 
2671 /* et131x_tx_dma_memory_alloc
2672  *
2673  * Allocates memory that will be visible both to the device and to the CPU.
2674  * The OS will pass us packets, pointers to which we will insert in the Tx
2675  * Descriptor queue. The device will read this queue to find the packets in
2676  * memory. The device will update the "status" in memory each time it xmits a
2677  * packet.
2678  */
2679 static int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
2680 {
2681         int desc_size = 0;
2682         struct tx_ring *tx_ring = &adapter->tx_ring;
2683 
2684         /* Allocate memory for the TCB's (Transmit Control Block) */
2685         tx_ring->tcb_ring = kcalloc(NUM_TCB, sizeof(struct tcb),
2686                                     GFP_ATOMIC | GFP_DMA);
2687         if (!tx_ring->tcb_ring)
2688                 return -ENOMEM;
2689 
2690         desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
2691         tx_ring->tx_desc_ring = dma_alloc_coherent(&adapter->pdev->dev,
2692                                                    desc_size,
2693                                                    &tx_ring->tx_desc_ring_pa,
2694                                                    GFP_KERNEL);
2695         if (!tx_ring->tx_desc_ring) {
2696                 dev_err(&adapter->pdev->dev,
2697                         "Cannot alloc memory for Tx Ring\n");
2698                 return -ENOMEM;
2699         }
2700 
2701         /* Save physical address
2702          *
2703          * NOTE: dma_alloc_coherent(), used above to alloc DMA regions,
2704          * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2705          * are ever returned, make sure the high part is retrieved here before
2706          * storing the adjusted address.
2707          */
2708         /* Allocate memory for the Tx status block */
2709         tx_ring->tx_status = dma_alloc_coherent(&adapter->pdev->dev,
2710                                                     sizeof(u32),
2711                                                     &tx_ring->tx_status_pa,
2712                                                     GFP_KERNEL);
2713         if (!tx_ring->tx_status_pa) {
2714                 dev_err(&adapter->pdev->dev,
2715                         "Cannot alloc memory for Tx status block\n");
2716                 return -ENOMEM;
2717         }
2718         return 0;
2719 }
2720 
2721 /* et131x_tx_dma_memory_free - Free all memory allocated within this module */
2722 static void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
2723 {
2724         int desc_size = 0;
2725         struct tx_ring *tx_ring = &adapter->tx_ring;
2726 
2727         if (tx_ring->tx_desc_ring) {
2728                 /* Free memory relating to Tx rings here */
2729                 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
2730                 dma_free_coherent(&adapter->pdev->dev,
2731                                   desc_size,
2732                                   tx_ring->tx_desc_ring,
2733                                   tx_ring->tx_desc_ring_pa);
2734                 tx_ring->tx_desc_ring = NULL;
2735         }
2736 
2737         /* Free memory for the Tx status block */
2738         if (tx_ring->tx_status) {
2739                 dma_free_coherent(&adapter->pdev->dev,
2740                                   sizeof(u32),
2741                                   tx_ring->tx_status,
2742                                   tx_ring->tx_status_pa);
2743 
2744                 tx_ring->tx_status = NULL;
2745         }
2746         /* Free the memory for the tcb structures */
2747         kfree(tx_ring->tcb_ring);
2748 }
2749 
2750 /* nic_send_packet - NIC specific send handler for version B silicon.
2751  * @adapter: pointer to our adapter
2752  * @tcb: pointer to struct tcb
2753  */
2754 static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb)
2755 {
2756         u32 i;
2757         struct tx_desc desc[24];        /* 24 x 16 byte */
2758         u32 frag = 0;
2759         u32 thiscopy, remainder;
2760         struct sk_buff *skb = tcb->skb;
2761         u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
2762         struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
2763         unsigned long flags;
2764         struct phy_device *phydev = adapter->phydev;
2765         dma_addr_t dma_addr;
2766         struct tx_ring *tx_ring = &adapter->tx_ring;
2767 
2768         /* Part of the optimizations of this send routine restrict us to
2769          * sending 24 fragments at a pass.  In practice we should never see
2770          * more than 5 fragments.
2771          *
2772          * NOTE: The older version of this function (below) can handle any
2773          * number of fragments. If needed, we can call this function,
2774          * although it is less efficient.
2775          */
2776 
2777         /* nr_frags should be no more than 18. */
2778         BUILD_BUG_ON(MAX_SKB_FRAGS + 1 > 23);
2779 
2780         memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
2781 
2782         for (i = 0; i < nr_frags; i++) {
2783                 /* If there is something in this element, lets get a
2784                  * descriptor from the ring and get the necessary data
2785                  */
2786                 if (i == 0) {
2787                         /* If the fragments are smaller than a standard MTU,
2788                          * then map them to a single descriptor in the Tx
2789                          * Desc ring. However, if they're larger, as is
2790                          * possible with support for jumbo packets, then
2791                          * split them each across 2 descriptors.
2792                          *
2793                          * This will work until we determine why the hardware
2794                          * doesn't seem to like large fragments.
2795                          */
2796                         if (skb_headlen(skb) <= 1514) {
2797                                 /* Low 16bits are length, high is vlan and
2798                                  * unused currently so zero
2799                                  */
2800                                 desc[frag].len_vlan = skb_headlen(skb);
2801                                 dma_addr = dma_map_single(&adapter->pdev->dev,
2802                                                           skb->data,
2803                                                           skb_headlen(skb),
2804                                                           DMA_TO_DEVICE);
2805                                 desc[frag].addr_lo = lower_32_bits(dma_addr);
2806                                 desc[frag].addr_hi = upper_32_bits(dma_addr);
2807                                 frag++;
2808                         } else {
2809                                 desc[frag].len_vlan = skb_headlen(skb) / 2;
2810                                 dma_addr = dma_map_single(&adapter->pdev->dev,
2811                                                          skb->data,
2812                                                          (skb_headlen(skb) / 2),
2813                                                          DMA_TO_DEVICE);
2814                                 desc[frag].addr_lo = lower_32_bits(dma_addr);
2815                                 desc[frag].addr_hi = upper_32_bits(dma_addr);
2816                                 frag++;
2817 
2818                                 desc[frag].len_vlan = skb_headlen(skb) / 2;
2819                                 dma_addr = dma_map_single(&adapter->pdev->dev,
2820                                                          skb->data +
2821                                                          (skb_headlen(skb) / 2),
2822                                                          (skb_headlen(skb) / 2),
2823                                                          DMA_TO_DEVICE);
2824                                 desc[frag].addr_lo = lower_32_bits(dma_addr);
2825                                 desc[frag].addr_hi = upper_32_bits(dma_addr);
2826                                 frag++;
2827                         }
2828                 } else {
2829                         desc[frag].len_vlan = frags[i - 1].size;
2830                         dma_addr = skb_frag_dma_map(&adapter->pdev->dev,
2831                                                     &frags[i - 1],
2832                                                     0,
2833                                                     frags[i - 1].size,
2834                                                     DMA_TO_DEVICE);
2835                         desc[frag].addr_lo = lower_32_bits(dma_addr);
2836                         desc[frag].addr_hi = upper_32_bits(dma_addr);
2837                         frag++;
2838                 }
2839         }
2840 
2841         if (phydev && phydev->speed == SPEED_1000) {
2842                 if (++tx_ring->since_irq == PARM_TX_NUM_BUFS_DEF) {
2843                         /* Last element & Interrupt flag */
2844                         desc[frag - 1].flags =
2845                                     TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT;
2846                         tx_ring->since_irq = 0;
2847                 } else { /* Last element */
2848                         desc[frag - 1].flags = TXDESC_FLAG_LASTPKT;
2849                 }
2850         } else
2851                 desc[frag - 1].flags =
2852                                     TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT;
2853 
2854         desc[0].flags |= TXDESC_FLAG_FIRSTPKT;
2855 
2856         tcb->index_start = tx_ring->send_idx;
2857         tcb->stale = 0;
2858 
2859         spin_lock_irqsave(&adapter->send_hw_lock, flags);
2860 
2861         thiscopy = NUM_DESC_PER_RING_TX - INDEX10(tx_ring->send_idx);
2862 
2863         if (thiscopy >= frag) {
2864                 remainder = 0;
2865                 thiscopy = frag;
2866         } else {
2867                 remainder = frag - thiscopy;
2868         }
2869 
2870         memcpy(tx_ring->tx_desc_ring + INDEX10(tx_ring->send_idx),
2871                desc,
2872                sizeof(struct tx_desc) * thiscopy);
2873 
2874         add_10bit(&tx_ring->send_idx, thiscopy);
2875 
2876         if (INDEX10(tx_ring->send_idx) == 0 ||
2877                   INDEX10(tx_ring->send_idx) == NUM_DESC_PER_RING_TX) {
2878                 tx_ring->send_idx &= ~ET_DMA10_MASK;
2879                 tx_ring->send_idx ^= ET_DMA10_WRAP;
2880         }
2881 
2882         if (remainder) {
2883                 memcpy(tx_ring->tx_desc_ring,
2884                        desc + thiscopy,
2885                        sizeof(struct tx_desc) * remainder);
2886 
2887                 add_10bit(&tx_ring->send_idx, remainder);
2888         }
2889 
2890         if (INDEX10(tx_ring->send_idx) == 0) {
2891                 if (tx_ring->send_idx)
2892                         tcb->index = NUM_DESC_PER_RING_TX - 1;
2893                 else
2894                         tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
2895         } else
2896                 tcb->index = tx_ring->send_idx - 1;
2897 
2898         spin_lock(&adapter->tcb_send_qlock);
2899 
2900         if (tx_ring->send_tail)
2901                 tx_ring->send_tail->next = tcb;
2902         else
2903                 tx_ring->send_head = tcb;
2904 
2905         tx_ring->send_tail = tcb;
2906 
2907         WARN_ON(tcb->next != NULL);
2908 
2909         tx_ring->used++;
2910 
2911         spin_unlock(&adapter->tcb_send_qlock);
2912 
2913         /* Write the new write pointer back to the device. */
2914         writel(tx_ring->send_idx, &adapter->regs->txdma.service_request);
2915 
2916         /* For Gig only, we use Tx Interrupt coalescing.  Enable the software
2917          * timer to wake us up if this packet isn't followed by N more.
2918          */
2919         if (phydev && phydev->speed == SPEED_1000) {
2920                 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
2921                        &adapter->regs->global.watchdog_timer);
2922         }
2923         spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
2924 
2925         return 0;
2926 }
2927 
2928 /* send_packet - Do the work to send a packet
2929  *
2930  * Assumption: Send spinlock has been acquired
2931  */
2932 static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter)
2933 {
2934         int status;
2935         struct tcb *tcb;
2936         u16 *shbufva;
2937         unsigned long flags;
2938         struct tx_ring *tx_ring = &adapter->tx_ring;
2939 
2940         /* All packets must have at least a MAC address and a protocol type */
2941         if (skb->len < ETH_HLEN)
2942                 return -EIO;
2943 
2944         /* Get a TCB for this packet */
2945         spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
2946 
2947         tcb = tx_ring->tcb_qhead;
2948 
2949         if (tcb == NULL) {
2950                 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2951                 return -ENOMEM;
2952         }
2953 
2954         tx_ring->tcb_qhead = tcb->next;
2955 
2956         if (tx_ring->tcb_qhead == NULL)
2957                 tx_ring->tcb_qtail = NULL;
2958 
2959         spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2960 
2961         tcb->skb = skb;
2962 
2963         if (skb->data != NULL && skb_headlen(skb) >= 6) {
2964                 shbufva = (u16 *) skb->data;
2965 
2966                 if ((shbufva[0] == 0xffff) &&
2967                     (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff))
2968                         tcb->flags |= FMP_DEST_BROAD;
2969                 else if ((shbufva[0] & 0x3) == 0x0001)
2970                         tcb->flags |=  FMP_DEST_MULTI;
2971         }
2972 
2973         tcb->next = NULL;
2974 
2975         /* Call the NIC specific send handler. */
2976         status = nic_send_packet(adapter, tcb);
2977 
2978         if (status != 0) {
2979                 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
2980 
2981                 if (tx_ring->tcb_qtail)
2982                         tx_ring->tcb_qtail->next = tcb;
2983                 else
2984                         /* Apparently ready Q is empty. */
2985                         tx_ring->tcb_qhead = tcb;
2986 
2987                 tx_ring->tcb_qtail = tcb;
2988                 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2989                 return status;
2990         }
2991         WARN_ON(tx_ring->used > NUM_TCB);
2992         return 0;
2993 }
2994 
2995 /* et131x_send_packets - This function is called by the OS to send packets */
2996 static int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
2997 {
2998         int status = 0;
2999         struct et131x_adapter *adapter = netdev_priv(netdev);
3000         struct tx_ring *tx_ring = &adapter->tx_ring;
3001 
3002         /* Send these packets
3003          *
3004          * NOTE: The Linux Tx entry point is only given one packet at a time
3005          * to Tx, so the PacketCount and it's array used makes no sense here
3006          */
3007 
3008         /* TCB is not available */
3009         if (tx_ring->used >= NUM_TCB) {
3010                 /* NOTE: If there's an error on send, no need to queue the
3011                  * packet under Linux; if we just send an error up to the
3012                  * netif layer, it will resend the skb to us.
3013                  */
3014                 status = -ENOMEM;
3015         } else {
3016                 /* We need to see if the link is up; if it's not, make the
3017                  * netif layer think we're good and drop the packet
3018                  */
3019                 if ((adapter->flags & FMP_ADAPTER_FAIL_SEND_MASK) ||
3020                                         !netif_carrier_ok(netdev)) {
3021                         dev_kfree_skb_any(skb);
3022                         skb = NULL;
3023 
3024                         adapter->netdev->stats.tx_dropped++;
3025                 } else {
3026                         status = send_packet(skb, adapter);
3027                         if (status != 0 && status != -ENOMEM) {
3028                                 /* On any other error, make netif think we're
3029                                  * OK and drop the packet
3030                                  */
3031                                 dev_kfree_skb_any(skb);
3032                                 skb = NULL;
3033                                 adapter->netdev->stats.tx_dropped++;
3034                         }
3035                 }
3036         }
3037         return status;
3038 }
3039 
3040 /* free_send_packet - Recycle a struct tcb
3041  * @adapter: pointer to our adapter
3042  * @tcb: pointer to struct tcb
3043  *
3044  * Complete the packet if necessary
3045  * Assumption - Send spinlock has been acquired
3046  */
3047 static inline void free_send_packet(struct et131x_adapter *adapter,
3048                                                 struct tcb *tcb)
3049 {
3050         unsigned long flags;
3051         struct tx_desc *desc = NULL;
3052         struct net_device_stats *stats = &adapter->netdev->stats;
3053         struct tx_ring *tx_ring = &adapter->tx_ring;
3054         u64  dma_addr;
3055 
3056         if (tcb->flags & FMP_DEST_BROAD)
3057                 atomic_inc(&adapter->stats.broadcast_pkts_xmtd);
3058         else if (tcb->flags & FMP_DEST_MULTI)
3059                 atomic_inc(&adapter->stats.multicast_pkts_xmtd);
3060         else
3061                 atomic_inc(&adapter->stats.unicast_pkts_xmtd);
3062 
3063         if (tcb->skb) {
3064                 stats->tx_bytes += tcb->skb->len;
3065 
3066                 /* Iterate through the TX descriptors on the ring
3067                  * corresponding to this packet and umap the fragments
3068                  * they point to
3069                  */
3070                 do {
3071                         desc = tx_ring->tx_desc_ring +
3072                                INDEX10(tcb->index_start);
3073 
3074                         dma_addr = desc->addr_lo;
3075                         dma_addr |= (u64)desc->addr_hi << 32;
3076 
3077                         dma_unmap_single(&adapter->pdev->dev,
3078                                          dma_addr,
3079                                          desc->len_vlan, DMA_TO_DEVICE);
3080 
3081                         add_10bit(&tcb->index_start, 1);
3082                         if (INDEX10(tcb->index_start) >=
3083                                                         NUM_DESC_PER_RING_TX) {
3084                                 tcb->index_start &= ~ET_DMA10_MASK;
3085                                 tcb->index_start ^= ET_DMA10_WRAP;
3086                         }
3087                 } while (desc != tx_ring->tx_desc_ring + INDEX10(tcb->index));
3088 
3089                 dev_kfree_skb_any(tcb->skb);
3090         }
3091 
3092         memset(tcb, 0, sizeof(struct tcb));
3093 
3094         /* Add the TCB to the Ready Q */
3095         spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3096 
3097         stats->tx_packets++;
3098 
3099         if (tx_ring->tcb_qtail)
3100                 tx_ring->tcb_qtail->next = tcb;
3101         else
3102                 /* Apparently ready Q is empty. */
3103                 tx_ring->tcb_qhead = tcb;
3104 
3105         tx_ring->tcb_qtail = tcb;
3106 
3107         spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3108         WARN_ON(tx_ring->used < 0);
3109 }
3110 
3111 /* et131x_free_busy_send_packets - Free and complete the stopped active sends
3112  *
3113  * Assumption - Send spinlock has been acquired
3114  */
3115 static void et131x_free_busy_send_packets(struct et131x_adapter *adapter)
3116 {
3117         struct tcb *tcb;
3118         unsigned long flags;
3119         u32 freed = 0;
3120         struct tx_ring *tx_ring = &adapter->tx_ring;
3121 
3122         /* Any packets being sent? Check the first TCB on the send list */
3123         spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3124 
3125         tcb = tx_ring->send_head;
3126 
3127         while (tcb != NULL && freed < NUM_TCB) {
3128                 struct tcb *next = tcb->next;
3129 
3130                 tx_ring->send_head = next;
3131 
3132                 if (next == NULL)
3133                         tx_ring->send_tail = NULL;
3134 
3135                 tx_ring->used--;
3136 
3137                 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3138 
3139                 freed++;
3140                 free_send_packet(adapter, tcb);
3141 
3142                 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3143 
3144                 tcb = tx_ring->send_head;
3145         }
3146 
3147         WARN_ON(freed == NUM_TCB);
3148 
3149         spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3150 
3151         tx_ring->used = 0;
3152 }
3153 
3154 /* et131x_handle_send_interrupt - Interrupt handler for sending processing
3155  *
3156  * Re-claim the send resources, complete sends and get more to send from
3157  * the send wait queue.
3158  *
3159  * Assumption - Send spinlock has been acquired
3160  */
3161 static void et131x_handle_send_interrupt(struct et131x_adapter *adapter)
3162 {
3163         unsigned long flags;
3164         u32 serviced;
3165         struct tcb *tcb;
3166         u32 index;
3167         struct tx_ring *tx_ring = &adapter->tx_ring;
3168 
3169         serviced = readl(&adapter->regs->txdma.new_service_complete);
3170         index = INDEX10(serviced);
3171 
3172         /* Has the ring wrapped?  Process any descriptors that do not have
3173          * the same "wrap" indicator as the current completion indicator
3174          */
3175         spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3176 
3177         tcb = tx_ring->send_head;
3178 
3179         while (tcb &&
3180                ((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
3181                index < INDEX10(tcb->index)) {
3182                 tx_ring->used--;
3183                 tx_ring->send_head = tcb->next;
3184                 if (tcb->next == NULL)
3185                         tx_ring->send_tail = NULL;
3186 
3187                 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3188                 free_send_packet(adapter, tcb);
3189                 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3190 
3191                 /* Goto the next packet */
3192                 tcb = tx_ring->send_head;
3193         }
3194         while (tcb &&
3195                !((serviced ^ tcb->index) & ET_DMA10_WRAP)
3196                && index > (tcb->index & ET_DMA10_MASK)) {
3197                 tx_ring->used--;
3198                 tx_ring->send_head = tcb->next;
3199                 if (tcb->next == NULL)
3200                         tx_ring->send_tail = NULL;
3201 
3202                 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3203                 free_send_packet(adapter, tcb);
3204                 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3205 
3206                 /* Goto the next packet */
3207                 tcb = tx_ring->send_head;
3208         }
3209 
3210         /* Wake up the queue when we hit a low-water mark */
3211         if (tx_ring->used <= NUM_TCB / 3)
3212                 netif_wake_queue(adapter->netdev);
3213 
3214         spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3215 }
3216 
3217 static int et131x_get_settings(struct net_device *netdev,
3218                                struct ethtool_cmd *cmd)
3219 {
3220         struct et131x_adapter *adapter = netdev_priv(netdev);
3221 
3222         return phy_ethtool_gset(adapter->phydev, cmd);
3223 }
3224 
3225 static int et131x_set_settings(struct net_device *netdev,
3226                                struct ethtool_cmd *cmd)
3227 {
3228         struct et131x_adapter *adapter = netdev_priv(netdev);
3229 
3230         return phy_ethtool_sset(adapter->phydev, cmd);
3231 }
3232 
3233 static int et131x_get_regs_len(struct net_device *netdev)
3234 {
3235 #define ET131X_REGS_LEN 256
3236         return ET131X_REGS_LEN * sizeof(u32);
3237 }
3238 
3239 static void et131x_get_regs(struct net_device *netdev,
3240                             struct ethtool_regs *regs, void *regs_data)
3241 {
3242         struct et131x_adapter *adapter = netdev_priv(netdev);
3243         struct address_map __iomem *aregs = adapter->regs;
3244         u32 *regs_buff = regs_data;
3245         u32 num = 0;
3246         u16 tmp;
3247 
3248         memset(regs_data, 0, et131x_get_regs_len(netdev));
3249 
3250         regs->version = (1 << 24) | (adapter->pdev->revision << 16) |
3251                         adapter->pdev->device;
3252 
3253         /* PHY regs */
3254         et131x_mii_read(adapter, MII_BMCR, &tmp);
3255         regs_buff[num++] = tmp;
3256         et131x_mii_read(adapter, MII_BMSR, &tmp);
3257         regs_buff[num++] = tmp;
3258         et131x_mii_read(adapter, MII_PHYSID1, &tmp);
3259         regs_buff[num++] = tmp;
3260         et131x_mii_read(adapter, MII_PHYSID2, &tmp);
3261         regs_buff[num++] = tmp;
3262         et131x_mii_read(adapter, MII_ADVERTISE, &tmp);
3263         regs_buff[num++] = tmp;
3264         et131x_mii_read(adapter, MII_LPA, &tmp);
3265         regs_buff[num++] = tmp;
3266         et131x_mii_read(adapter, MII_EXPANSION, &tmp);
3267         regs_buff[num++] = tmp;
3268         /* Autoneg next page transmit reg */
3269         et131x_mii_read(adapter, 0x07, &tmp);
3270         regs_buff[num++] = tmp;
3271         /* Link partner next page reg */
3272         et131x_mii_read(adapter, 0x08, &tmp);
3273         regs_buff[num++] = tmp;
3274         et131x_mii_read(adapter, MII_CTRL1000, &tmp);
3275         regs_buff[num++] = tmp;
3276         et131x_mii_read(adapter, MII_STAT1000, &tmp);
3277         regs_buff[num++] = tmp;
3278         et131x_mii_read(adapter, 0x0b, &tmp);
3279         regs_buff[num++] = tmp;
3280         et131x_mii_read(adapter, 0x0c, &tmp);
3281         regs_buff[num++] = tmp;
3282         et131x_mii_read(adapter, MII_MMD_CTRL, &tmp);
3283         regs_buff[num++] = tmp;
3284         et131x_mii_read(adapter, MII_MMD_DATA, &tmp);
3285         regs_buff[num++] = tmp;
3286         et131x_mii_read(adapter, MII_ESTATUS, &tmp);
3287         regs_buff[num++] = tmp;
3288 
3289         et131x_mii_read(adapter, PHY_INDEX_REG, &tmp);
3290         regs_buff[num++] = tmp;
3291         et131x_mii_read(adapter, PHY_DATA_REG, &tmp);
3292         regs_buff[num++] = tmp;
3293         et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, &tmp);
3294         regs_buff[num++] = tmp;
3295         et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL, &tmp);
3296         regs_buff[num++] = tmp;
3297         et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL + 1, &tmp);
3298         regs_buff[num++] = tmp;
3299 
3300         et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL, &tmp);
3301         regs_buff[num++] = tmp;
3302         et131x_mii_read(adapter, PHY_CONFIG, &tmp);
3303         regs_buff[num++] = tmp;
3304         et131x_mii_read(adapter, PHY_PHY_CONTROL, &tmp);
3305         regs_buff[num++] = tmp;
3306         et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &tmp);
3307         regs_buff[num++] = tmp;
3308         et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &tmp);
3309         regs_buff[num++] = tmp;
3310         et131x_mii_read(adapter, PHY_PHY_STATUS, &tmp);
3311         regs_buff[num++] = tmp;
3312         et131x_mii_read(adapter, PHY_LED_1, &tmp);
3313         regs_buff[num++] = tmp;
3314         et131x_mii_read(adapter, PHY_LED_2, &tmp);
3315         regs_buff[num++] = tmp;
3316 
3317         /* Global regs */
3318         regs_buff[num++] = readl(&aregs->global.txq_start_addr);
3319         regs_buff[num++] = readl(&aregs->global.txq_end_addr);
3320         regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
3321         regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
3322         regs_buff[num++] = readl(&aregs->global.pm_csr);
3323         regs_buff[num++] = adapter->stats.interrupt_status;
3324         regs_buff[num++] = readl(&aregs->global.int_mask);
3325         regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
3326         regs_buff[num++] = readl(&aregs->global.int_status_alias);
3327         regs_buff[num++] = readl(&aregs->global.sw_reset);
3328         regs_buff[num++] = readl(&aregs->global.slv_timer);
3329         regs_buff[num++] = readl(&aregs->global.msi_config);
3330         regs_buff[num++] = readl(&aregs->global.loopback);
3331         regs_buff[num++] = readl(&aregs->global.watchdog_timer);
3332 
3333         /* TXDMA regs */
3334         regs_buff[num++] = readl(&aregs->txdma.csr);
3335         regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
3336         regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
3337         regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
3338         regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
3339         regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
3340         regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
3341         regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
3342         regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
3343         regs_buff[num++] = readl(&aregs->txdma.service_request);
3344         regs_buff[num++] = readl(&aregs->txdma.service_complete);
3345         regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
3346         regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
3347         regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
3348         regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
3349         regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
3350         regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
3351         regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
3352         regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
3353         regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
3354         regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
3355         regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
3356         regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
3357         regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
3358         regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
3359         regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
3360 
3361         /* RXDMA regs */
3362         regs_buff[num++] = readl(&aregs->rxdma.csr);
3363         regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
3364         regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
3365         regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
3366         regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
3367         regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
3368         regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
3369         regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
3370         regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
3371         regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
3372         regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
3373         regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
3374         regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
3375         regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
3376         regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
3377         regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
3378         regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
3379         regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
3380         regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
3381         regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
3382         regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
3383         regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
3384         regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
3385         regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
3386         regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
3387         regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
3388         regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
3389         regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
3390         regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);
3391 }
3392 
3393 static void et131x_get_drvinfo(struct net_device *netdev,
3394                                struct ethtool_drvinfo *info)
3395 {
3396         struct et131x_adapter *adapter = netdev_priv(netdev);
3397 
3398         strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver));
3399         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3400         strlcpy(info->bus_info, pci_name(adapter->pdev),
3401                 sizeof(info->bus_info));
3402 }
3403 
3404 static struct ethtool_ops et131x_ethtool_ops = {
3405         .get_settings   = et131x_get_settings,
3406         .set_settings   = et131x_set_settings,
3407         .get_drvinfo    = et131x_get_drvinfo,
3408         .get_regs_len   = et131x_get_regs_len,
3409         .get_regs       = et131x_get_regs,
3410         .get_link       = ethtool_op_get_link,
3411 };
3412 
3413 /* et131x_hwaddr_init - set up the MAC Address on the ET1310 */
3414 static void et131x_hwaddr_init(struct et131x_adapter *adapter)
3415 {
3416         /* If have our default mac from init and no mac address from
3417          * EEPROM then we need to generate the last octet and set it on the
3418          * device
3419          */
3420         if (is_zero_ether_addr(adapter->rom_addr)) {
3421                 /* We need to randomly generate the last octet so we
3422                  * decrease our chances of setting the mac address to
3423                  * same as another one of our cards in the system
3424                  */
3425                 get_random_bytes(&adapter->addr[5], 1);
3426                 /* We have the default value in the register we are
3427                  * working with so we need to copy the current
3428                  * address into the permanent address
3429                  */
3430                 memcpy(adapter->rom_addr,
3431                         adapter->addr, ETH_ALEN);
3432         } else {
3433                 /* We do not have an override address, so set the
3434                  * current address to the permanent address and add
3435                  * it to the device
3436                  */
3437                 memcpy(adapter->addr,
3438                        adapter->rom_addr, ETH_ALEN);
3439         }
3440 }
3441 
3442 /* et131x_pci_init       - initial PCI setup
3443  *
3444  * Perform the initial setup of PCI registers and if possible initialise
3445  * the MAC address. At this point the I/O registers have yet to be mapped
3446  */
3447 static int et131x_pci_init(struct et131x_adapter *adapter,
3448                            struct pci_dev *pdev)
3449 {
3450         u16 max_payload;
3451         int i, rc;
3452 
3453         rc = et131x_init_eeprom(adapter);
3454         if (rc < 0)
3455                 goto out;
3456 
3457         if (!pci_is_pcie(pdev)) {
3458                 dev_err(&pdev->dev, "Missing PCIe capabilities\n");
3459                 goto err_out;
3460         }
3461 
3462         /* Let's set up the PORT LOGIC Register. */
3463 
3464         /* Program the Ack/Nak latency and replay timers */
3465         max_payload = pdev->pcie_mpss;
3466 
3467         if (max_payload < 2) {
3468                 static const u16 acknak[2] = { 0x76, 0xD0 };
3469                 static const u16 replay[2] = { 0x1E0, 0x2ED };
3470 
3471                 if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
3472                                                acknak[max_payload])) {
3473                         dev_err(&pdev->dev,
3474                           "Could not write PCI config space for ACK/NAK\n");
3475                         goto err_out;
3476                 }
3477                 if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
3478                                                replay[max_payload])) {
3479                         dev_err(&pdev->dev,
3480                           "Could not write PCI config space for Replay Timer\n");
3481                         goto err_out;
3482                 }
3483         }
3484 
3485         /* l0s and l1 latency timers.  We are using default values.
3486          * Representing 001 for L0s and 010 for L1
3487          */
3488         if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
3489                 dev_err(&pdev->dev,
3490                   "Could not write PCI config space for Latency Timers\n");
3491                 goto err_out;
3492         }
3493 
3494         /* Change the max read size to 2k */
3495         if (pcie_set_readrq(pdev, 2048)) {
3496                 dev_err(&pdev->dev,
3497                         "Couldn't change PCI config space for Max read size\n");
3498                 goto err_out;
3499         }
3500 
3501         /* Get MAC address from config space if an eeprom exists, otherwise
3502          * the MAC address there will not be valid
3503          */
3504         if (!adapter->has_eeprom) {
3505                 et131x_hwaddr_init(adapter);
3506                 return 0;
3507         }
3508 
3509         for (i = 0; i < ETH_ALEN; i++) {
3510                 if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
3511                                         adapter->rom_addr + i)) {
3512                         dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
3513                         goto err_out;
3514                 }
3515         }
3516         ether_addr_copy(adapter->addr, adapter->rom_addr);
3517 out:
3518         return rc;
3519 err_out:
3520         rc = -EIO;
3521         goto out;
3522 }
3523 
3524 /* et131x_error_timer_handler
3525  * @data: timer-specific variable; here a pointer to our adapter structure
3526  *
3527  * The routine called when the error timer expires, to track the number of
3528  * recurring errors.
3529  */
3530 static void et131x_error_timer_handler(unsigned long data)
3531 {
3532         struct et131x_adapter *adapter = (struct et131x_adapter *) data;
3533         struct phy_device *phydev = adapter->phydev;
3534 
3535         if (et1310_in_phy_coma(adapter)) {
3536                 /* Bring the device immediately out of coma, to
3537                  * prevent it from sleeping indefinitely, this
3538                  * mechanism could be improved!
3539                  */
3540                 et1310_disable_phy_coma(adapter);
3541                 adapter->boot_coma = 20;
3542         } else {
3543                 et1310_update_macstat_host_counters(adapter);
3544         }
3545 
3546         if (!phydev->link && adapter->boot_coma < 11)
3547                 adapter->boot_coma++;
3548 
3549         if (adapter->boot_coma == 10) {
3550                 if (!phydev->link) {
3551                         if (!et1310_in_phy_coma(adapter)) {
3552                                 /* NOTE - This was originally a 'sync with
3553                                  *  interrupt'. How to do that under Linux?
3554                                  */
3555                                 et131x_enable_interrupts(adapter);
3556                                 et1310_enable_phy_coma(adapter);
3557                         }
3558                 }
3559         }
3560 
3561         /* This is a periodic timer, so reschedule */
3562         mod_timer(&adapter->error_timer, jiffies + TX_ERROR_PERIOD * HZ / 1000);
3563 }
3564 
3565 /* et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx */
3566 static void et131x_adapter_memory_free(struct et131x_adapter *adapter)
3567 {
3568         et131x_tx_dma_memory_free(adapter);
3569         et131x_rx_dma_memory_free(adapter);
3570 }
3571 
3572 /* et131x_adapter_memory_alloc
3573  * Allocate all the memory blocks for send, receive and others.
3574  */
3575 static int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
3576 {
3577         int status;
3578 
3579         /* Allocate memory for the Tx Ring */
3580         status = et131x_tx_dma_memory_alloc(adapter);
3581         if (status) {
3582                 dev_err(&adapter->pdev->dev,
3583                           "et131x_tx_dma_memory_alloc FAILED\n");
3584                 et131x_tx_dma_memory_free(adapter);
3585                 return status;
3586         }
3587         /* Receive buffer memory allocation */
3588         status = et131x_rx_dma_memory_alloc(adapter);
3589         if (status) {
3590                 dev_err(&adapter->pdev->dev,
3591                           "et131x_rx_dma_memory_alloc FAILED\n");
3592                 et131x_adapter_memory_free(adapter);
3593                 return status;
3594         }
3595 
3596         /* Init receive data structures */
3597         status = et131x_init_recv(adapter);
3598         if (status) {
3599                 dev_err(&adapter->pdev->dev, "et131x_init_recv FAILED\n");
3600                 et131x_adapter_memory_free(adapter);
3601         }
3602         return status;
3603 }
3604 
3605 static void et131x_adjust_link(struct net_device *netdev)
3606 {
3607         struct et131x_adapter *adapter = netdev_priv(netdev);
3608         struct  phy_device *phydev = adapter->phydev;
3609 
3610         if (!phydev)
3611                 return;
3612         if (phydev->link == adapter->link)
3613                 return;
3614 
3615         /* Check to see if we are in coma mode and if
3616          * so, disable it because we will not be able
3617          * to read PHY values until we are out.
3618          */
3619         if (et1310_in_phy_coma(adapter))
3620                 et1310_disable_phy_coma(adapter);
3621 
3622         adapter->link = phydev->link;
3623         phy_print_status(phydev);
3624 
3625         if (phydev->link) {
3626                 adapter->boot_coma = 20;
3627                 if (phydev->speed == SPEED_10) {
3628                         u16 register18;
3629 
3630                         et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3631                                          &register18);
3632                         et131x_mii_write(adapter, phydev->addr,
3633                                          PHY_MPHY_CONTROL_REG, register18 | 0x4);
3634                         et131x_mii_write(adapter, phydev->addr, PHY_INDEX_REG,
3635                                          register18 | 0x8402);
3636                         et131x_mii_write(adapter, phydev->addr, PHY_DATA_REG,
3637                                          register18 | 511);
3638                         et131x_mii_write(adapter, phydev->addr,
3639                                          PHY_MPHY_CONTROL_REG, register18);
3640                 }
3641 
3642                 et1310_config_flow_control(adapter);
3643 
3644                 if (phydev->speed == SPEED_1000 &&
3645                     adapter->registry_jumbo_packet > 2048) {
3646                         u16 reg;
3647 
3648                         et131x_mii_read(adapter, PHY_CONFIG, &reg);
3649                         reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH;
3650                         reg |= ET_PHY_CONFIG_FIFO_DEPTH_32;
3651                         et131x_mii_write(adapter, phydev->addr, PHY_CONFIG,
3652                                          reg);
3653                 }
3654 
3655                 et131x_set_rx_dma_timer(adapter);
3656                 et1310_config_mac_regs2(adapter);
3657         } else {
3658                 adapter->boot_coma = 0;
3659 
3660                 if (phydev->speed == SPEED_10) {
3661                         u16 register18;
3662 
3663                         et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3664                                          &register18);
3665                         et131x_mii_write(adapter, phydev->addr,
3666                                         PHY_MPHY_CONTROL_REG, register18 | 0x4);
3667                         et131x_mii_write(adapter, phydev->addr,
3668                                         PHY_INDEX_REG, register18 | 0x8402);
3669                         et131x_mii_write(adapter, phydev->addr,
3670                                         PHY_DATA_REG, register18 | 511);
3671                         et131x_mii_write(adapter, phydev->addr,
3672                                         PHY_MPHY_CONTROL_REG, register18);
3673                 }
3674 
3675                 /* Free the packets being actively sent & stopped */
3676                 et131x_free_busy_send_packets(adapter);
3677 
3678                 /* Re-initialize the send structures */
3679                 et131x_init_send(adapter);
3680 
3681                 /* Bring the device back to the state it was during
3682                  * init prior to autonegotiation being complete. This
3683                  * way, when we get the auto-neg complete interrupt,
3684                  * we can complete init by calling config_mac_regs2.
3685                  */
3686                 et131x_soft_reset(adapter);
3687 
3688                 /* Setup ET1310 as per the documentation */
3689                 et131x_adapter_setup(adapter);
3690 
3691                 /* perform reset of tx/rx */
3692                 et131x_disable_txrx(netdev);
3693                 et131x_enable_txrx(netdev);
3694         }
3695 }
3696 
3697 static int et131x_mii_probe(struct net_device *netdev)
3698 {
3699         struct et131x_adapter *adapter = netdev_priv(netdev);
3700         struct  phy_device *phydev = NULL;
3701 
3702         phydev = phy_find_first(adapter->mii_bus);
3703         if (!phydev) {
3704                 dev_err(&adapter->pdev->dev, "no PHY found\n");
3705                 return -ENODEV;
3706         }
3707 
3708         phydev = phy_connect(netdev, dev_name(&phydev->dev),
3709                              &et131x_adjust_link, PHY_INTERFACE_MODE_MII);
3710 
3711         if (IS_ERR(phydev)) {
3712                 dev_err(&adapter->pdev->dev, "Could not attach to PHY\n");
3713                 return PTR_ERR(phydev);
3714         }
3715 
3716         phydev->supported &= (SUPPORTED_10baseT_Half
3717                                 | SUPPORTED_10baseT_Full
3718                                 | SUPPORTED_100baseT_Half
3719                                 | SUPPORTED_100baseT_Full
3720                                 | SUPPORTED_Autoneg
3721                                 | SUPPORTED_MII
3722                                 | SUPPORTED_TP);
3723 
3724         if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
3725                 phydev->supported |= SUPPORTED_1000baseT_Full;
3726 
3727         phydev->advertising = phydev->supported;
3728         adapter->phydev = phydev;
3729 
3730         dev_info(&adapter->pdev->dev,
3731                  "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3732                  phydev->drv->name, dev_name(&phydev->dev));
3733 
3734         return 0;
3735 }
3736 
3737 /* et131x_adapter_init
3738  *
3739  * Initialize the data structures for the et131x_adapter object and link
3740  * them together with the platform provided device structures.
3741  */
3742 static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
3743                                                   struct pci_dev *pdev)
3744 {
3745         static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
3746 
3747         struct et131x_adapter *adapter;
3748 
3749         /* Allocate private adapter struct and copy in relevant information */
3750         adapter = netdev_priv(netdev);
3751         adapter->pdev = pci_dev_get(pdev);
3752         adapter->netdev = netdev;
3753 
3754         /* Initialize spinlocks here */
3755         spin_lock_init(&adapter->tcb_send_qlock);
3756         spin_lock_init(&adapter->tcb_ready_qlock);
3757         spin_lock_init(&adapter->send_hw_lock);
3758         spin_lock_init(&adapter->rcv_lock);
3759         spin_lock_init(&adapter->fbr_lock);
3760 
3761         adapter->registry_jumbo_packet = 1514;  /* 1514-9216 */
3762 
3763         /* Set the MAC address to a default */
3764         ether_addr_copy(adapter->addr, default_mac);
3765 
3766         return adapter;
3767 }
3768 
3769 /* et131x_pci_remove
3770  *
3771  * Registered in the pci_driver structure, this function is called when the
3772  * PCI subsystem detects that a PCI device which matches the information
3773  * contained in the pci_device_id table has been removed.
3774  */
3775 static void et131x_pci_remove(struct pci_dev *pdev)
3776 {
3777         struct net_device *netdev = pci_get_drvdata(pdev);
3778         struct et131x_adapter *adapter = netdev_priv(netdev);
3779 
3780         unregister_netdev(netdev);
3781         phy_disconnect(adapter->phydev);
3782         mdiobus_unregister(adapter->mii_bus);
3783         cancel_work_sync(&adapter->task);
3784         kfree(adapter->mii_bus->irq);
3785         mdiobus_free(adapter->mii_bus);
3786 
3787         et131x_adapter_memory_free(adapter);
3788         iounmap(adapter->regs);
3789         pci_dev_put(pdev);
3790 
3791         free_netdev(netdev);
3792         pci_release_regions(pdev);
3793         pci_disable_device(pdev);
3794 }
3795 
3796 /* et131x_up - Bring up a device for use.  */
3797 static void et131x_up(struct net_device *netdev)
3798 {
3799         struct et131x_adapter *adapter = netdev_priv(netdev);
3800 
3801         et131x_enable_txrx(netdev);
3802         phy_start(adapter->phydev);
3803 }
3804 
3805 /* et131x_down - Bring down the device */
3806 static void et131x_down(struct net_device *netdev)
3807 {
3808         struct et131x_adapter *adapter = netdev_priv(netdev);
3809 
3810         /* Save the timestamp for the TX watchdog, prevent a timeout */
3811         netdev->trans_start = jiffies;
3812 
3813         phy_stop(adapter->phydev);
3814         et131x_disable_txrx(netdev);
3815 }
3816 
3817 #ifdef CONFIG_PM_SLEEP
3818 static int et131x_suspend(struct device *dev)
3819 {
3820         struct pci_dev *pdev = to_pci_dev(dev);
3821         struct net_device *netdev = pci_get_drvdata(pdev);
3822 
3823         if (netif_running(netdev)) {
3824                 netif_device_detach(netdev);
3825                 et131x_down(netdev);
3826                 pci_save_state(pdev);
3827         }
3828 
3829         return 0;
3830 }
3831 
3832 static int et131x_resume(struct device *dev)
3833 {
3834         struct pci_dev *pdev = to_pci_dev(dev);
3835         struct net_device *netdev = pci_get_drvdata(pdev);
3836 
3837         if (netif_running(netdev)) {
3838                 pci_restore_state(pdev);
3839                 et131x_up(netdev);
3840                 netif_device_attach(netdev);
3841         }
3842 
3843         return 0;
3844 }
3845 
3846 static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume);
3847 #define ET131X_PM_OPS (&et131x_pm_ops)
3848 #else
3849 #define ET131X_PM_OPS NULL
3850 #endif
3851 
3852 /* et131x_isr - The Interrupt Service Routine for the driver.
3853  * @irq: the IRQ on which the interrupt was received.
3854  * @dev_id: device-specific info (here a pointer to a net_device struct)
3855  *
3856  * Returns a value indicating if the interrupt was handled.
3857  */
3858 static irqreturn_t et131x_isr(int irq, void *dev_id)
3859 {
3860         bool handled = true;
3861         struct net_device *netdev = (struct net_device *)dev_id;
3862         struct et131x_adapter *adapter = netdev_priv(netdev);
3863         struct rx_ring *rx_ring = &adapter->rx_ring;
3864         struct tx_ring *tx_ring = &adapter->tx_ring;
3865         u32 status;
3866 
3867         if (!netif_device_present(netdev)) {
3868                 handled = false;
3869                 goto out;
3870         }
3871 
3872         /* If the adapter is in low power state, then it should not
3873          * recognize any interrupt
3874          */
3875 
3876         /* Disable Device Interrupts */
3877         et131x_disable_interrupts(adapter);
3878 
3879         /* Get a copy of the value in the interrupt status register
3880          * so we can process the interrupting section
3881          */
3882         status = readl(&adapter->regs->global.int_status);
3883 
3884         if (adapter->flowcontrol == FLOW_TXONLY ||
3885             adapter->flowcontrol == FLOW_BOTH) {
3886                 status &= ~INT_MASK_ENABLE;
3887         } else {
3888                 status &= ~INT_MASK_ENABLE_NO_FLOW;
3889         }
3890 
3891         /* Make sure this is our interrupt */
3892         if (!status) {
3893                 handled = false;
3894                 et131x_enable_interrupts(adapter);
3895                 goto out;
3896         }
3897 
3898         /* This is our interrupt, so process accordingly */
3899 
3900         if (status & ET_INTR_WATCHDOG) {
3901                 struct tcb *tcb = tx_ring->send_head;
3902 
3903                 if (tcb)
3904                         if (++tcb->stale > 1)
3905                                 status |= ET_INTR_TXDMA_ISR;
3906 
3907                 if (rx_ring->unfinished_receives)
3908                         status |= ET_INTR_RXDMA_XFR_DONE;
3909                 else if (tcb == NULL)
3910                         writel(0, &adapter->regs->global.watchdog_timer);
3911 
3912                 status &= ~ET_INTR_WATCHDOG;
3913         }
3914 
3915         if (!status) {
3916                 /* This interrupt has in some way been "handled" by
3917                  * the ISR. Either it was a spurious Rx interrupt, or
3918                  * it was a Tx interrupt that has been filtered by
3919                  * the ISR.
3920                  */
3921                 et131x_enable_interrupts(adapter);
3922                 goto out;
3923         }
3924 
3925         /* We need to save the interrupt status value for use in our
3926          * DPC. We will clear the software copy of that in that
3927          * routine.
3928          */
3929         adapter->stats.interrupt_status = status;
3930 
3931         /* Schedule the ISR handler as a bottom-half task in the
3932          * kernel's tq_immediate queue, and mark the queue for
3933          * execution
3934          */
3935         schedule_work(&adapter->task);
3936 out:
3937         return IRQ_RETVAL(handled);
3938 }
3939 
3940 /* et131x_isr_handler - The ISR handler
3941  *
3942  * scheduled to run in a deferred context by the ISR. This is where the ISR's
3943  * work actually gets done.
3944  */
3945 static void et131x_isr_handler(struct work_struct *work)
3946 {
3947         struct et131x_adapter *adapter =
3948                 container_of(work, struct et131x_adapter, task);
3949         u32 status = adapter->stats.interrupt_status;
3950         struct address_map __iomem *iomem = adapter->regs;
3951 
3952         /* These first two are by far the most common.  Once handled, we clear
3953          * their two bits in the status word.  If the word is now zero, we
3954          * exit.
3955          */
3956         /* Handle all the completed Transmit interrupts */
3957         if (status & ET_INTR_TXDMA_ISR)
3958                 et131x_handle_send_interrupt(adapter);
3959 
3960         /* Handle all the completed Receives interrupts */
3961         if (status & ET_INTR_RXDMA_XFR_DONE)
3962                 et131x_handle_recv_interrupt(adapter);
3963 
3964         status &= ~(ET_INTR_TXDMA_ERR | ET_INTR_RXDMA_XFR_DONE);
3965 
3966         if (!status)
3967                 goto out;
3968 
3969         /* Handle the TXDMA Error interrupt */
3970         if (status & ET_INTR_TXDMA_ERR) {
3971                 /* Following read also clears the register (COR) */
3972                 u32 txdma_err = readl(&iomem->txdma.tx_dma_error);
3973 
3974                 dev_warn(&adapter->pdev->dev,
3975                             "TXDMA_ERR interrupt, error = %d\n",
3976                             txdma_err);
3977         }
3978 
3979         /* Handle Free Buffer Ring 0 and 1 Low interrupt */
3980         if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
3981                 /* This indicates the number of unused buffers in RXDMA free
3982                  * buffer ring 0 is <= the limit you programmed. Free buffer
3983                  * resources need to be returned.  Free buffers are consumed as
3984                  * packets are passed from the network to the host. The host
3985                  * becomes aware of the packets from the contents of the packet
3986                  * status ring. This ring is queried when the packet done
3987                  * interrupt occurs. Packets are then passed to the OS. When
3988                  * the OS is done with the packets the resources can be
3989                  * returned to the ET1310 for re-use. This interrupt is one
3990                  * method of returning resources.
3991                  */
3992 
3993                 /*  If the user has flow control on, then we will
3994                  * send a pause packet, otherwise just exit
3995                  */
3996                 if (adapter->flowcontrol == FLOW_TXONLY ||
3997                     adapter->flowcontrol == FLOW_BOTH) {
3998                         u32 pm_csr;
3999 
4000                         /* Tell the device to send a pause packet via the back
4001                          * pressure register (bp req and bp xon/xoff)
4002                          */
4003                         pm_csr = readl(&iomem->global.pm_csr);
4004                         if (!et1310_in_phy_coma(adapter))
4005                                 writel(3, &iomem->txmac.bp_ctrl);
4006                 }
4007         }
4008 
4009         /* Handle Packet Status Ring Low Interrupt */
4010         if (status & ET_INTR_RXDMA_STAT_LOW) {
4011                 /* Same idea as with the two Free Buffer Rings. Packets going
4012                  * from the network to the host each consume a free buffer
4013                  * resource and a packet status resource. These resources are
4014                  * passed to the OS. When the OS is done with the resources,
4015                  * they need to be returned to the ET1310. This is one method
4016                  * of returning the resources.
4017                  */
4018         }
4019 
4020         /* Handle RXDMA Error Interrupt */
4021         if (status & ET_INTR_RXDMA_ERR) {
4022                 /* The rxdma_error interrupt is sent when a time-out on a
4023                  * request issued by the JAGCore has occurred or a completion is
4024                  * returned with an un-successful status. In both cases the
4025                  * request is considered complete. The JAGCore will
4026                  * automatically re-try the request in question. Normally
4027                  * information on events like these are sent to the host using
4028                  * the "Advanced Error Reporting" capability. This interrupt is
4029                  * another way of getting similar information. The only thing
4030                  * required is to clear the interrupt by reading the ISR in the
4031                  * global resources. The JAGCore will do a re-try on the
4032                  * request. Normally you should never see this interrupt. If
4033                  * you start to see this interrupt occurring frequently then
4034                  * something bad has occurred. A reset might be the thing to do.
4035                  */
4036                 /* TRAP();*/
4037 
4038                 dev_warn(&adapter->pdev->dev,
4039                             "RxDMA_ERR interrupt, error %x\n",
4040                             readl(&iomem->txmac.tx_test));
4041         }
4042 
4043         /* Handle the Wake on LAN Event */
4044         if (status & ET_INTR_WOL) {
4045                 /* This is a secondary interrupt for wake on LAN. The driver
4046                  * should never see this, if it does, something serious is
4047                  * wrong. We will TRAP the message when we are in DBG mode,
4048                  * otherwise we will ignore it.
4049                  */
4050                 dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n");
4051         }
4052 
4053         /* Let's move on to the TxMac */
4054         if (status & ET_INTR_TXMAC) {
4055                 u32 err = readl(&iomem->txmac.err);
4056 
4057                 /* When any of the errors occur and TXMAC generates an
4058                  * interrupt to report these errors, it usually means that
4059                  * TXMAC has detected an error in the data stream retrieved
4060                  * from the on-chip Tx Q. All of these errors are catastrophic
4061                  * and TXMAC won't be able to recover data when these errors
4062                  * occur. In a nutshell, the whole Tx path will have to be reset
4063                  * and re-configured afterwards.
4064                  */
4065                 dev_warn(&adapter->pdev->dev,
4066                          "TXMAC interrupt, error 0x%08x\n",
4067                          err);
4068 
4069                 /* If we are debugging, we want to see this error, otherwise we
4070                  * just want the device to be reset and continue
4071                  */
4072         }
4073 
4074         /* Handle RXMAC Interrupt */
4075         if (status & ET_INTR_RXMAC) {
4076                 /* These interrupts are catastrophic to the device, what we need
4077                  * to do is disable the interrupts and set the flag to cause us
4078                  * to reset so we can solve this issue.
4079                  */
4080                 /* MP_SET_FLAG( adapter, FMP_ADAPTER_HARDWARE_ERROR); */
4081 
4082                 dev_warn(&adapter->pdev->dev,
4083                          "RXMAC interrupt, error 0x%08x.  Requesting reset\n",
4084                          readl(&iomem->rxmac.err_reg));
4085 
4086                 dev_warn(&adapter->pdev->dev,
4087                          "Enable 0x%08x, Diag 0x%08x\n",
4088                          readl(&iomem->rxmac.ctrl),
4089                          readl(&iomem->rxmac.rxq_diag));
4090 
4091                 /* If we are debugging, we want to see this error, otherwise we
4092                  * just want the device to be reset and continue
4093                  */
4094         }
4095 
4096         /* Handle MAC_STAT Interrupt */
4097         if (status & ET_INTR_MAC_STAT) {
4098                 /* This means at least one of the un-masked counters in the
4099                  * MAC_STAT block has rolled over. Use this to maintain the top,
4100                  * software managed bits of the counter(s).
4101                  */
4102                 et1310_handle_macstat_interrupt(adapter);
4103         }
4104 
4105         /* Handle SLV Timeout Interrupt */
4106         if (status & ET_INTR_SLV_TIMEOUT) {
4107                 /* This means a timeout has occurred on a read or write request
4108                  * to one of the JAGCore registers. The Global Resources block
4109                  * has terminated the request and on a read request, returned a
4110                  * "fake" value. The most likely reasons are: Bad Address or the
4111                  * addressed module is in a power-down state and can't respond.
4112                  */
4113         }
4114 out:
4115         et131x_enable_interrupts(adapter);
4116 }
4117 
4118 /* et131x_stats - Return the current device statistics  */
4119 static struct net_device_stats *et131x_stats(struct net_device *netdev)
4120 {
4121         struct et131x_adapter *adapter = netdev_priv(netdev);
4122         struct net_device_stats *stats = &adapter->netdev->stats;
4123         struct ce_stats *devstat = &adapter->stats;
4124 
4125         stats->rx_errors = devstat->rx_length_errs +
4126                            devstat->rx_align_errs +
4127                            devstat->rx_crc_errs +
4128                            devstat->rx_code_violations +
4129                            devstat->rx_other_errs;
4130         stats->tx_errors = devstat->tx_max_pkt_errs;
4131         stats->multicast = devstat->multicast_pkts_rcvd;
4132         stats->collisions = devstat->tx_collisions;
4133 
4134         stats->rx_length_errors = devstat->rx_length_errs;
4135         stats->rx_over_errors = devstat->rx_overflows;
4136         stats->rx_crc_errors = devstat->rx_crc_errs;
4137 
4138         /* NOTE: These stats don't have corresponding values in CE_STATS,
4139          * so we're going to have to update these directly from within the
4140          * TX/RX code
4141          */
4142         /* stats->rx_bytes            = 20; devstat->; */
4143         /* stats->tx_bytes            = 20;  devstat->; */
4144         /* stats->rx_dropped          = devstat->; */
4145         /* stats->tx_dropped          = devstat->; */
4146 
4147         /*  NOTE: Not used, can't find analogous statistics */
4148         /* stats->rx_frame_errors     = devstat->; */
4149         /* stats->rx_fifo_errors      = devstat->; */
4150         /* stats->rx_missed_errors    = devstat->; */
4151 
4152         /* stats->tx_aborted_errors   = devstat->; */
4153         /* stats->tx_carrier_errors   = devstat->; */
4154         /* stats->tx_fifo_errors      = devstat->; */
4155         /* stats->tx_heartbeat_errors = devstat->; */
4156         /* stats->tx_window_errors    = devstat->; */
4157         return stats;
4158 }
4159 
4160 /* et131x_open - Open the device for use.  */
4161 static int et131x_open(struct net_device *netdev)
4162 {
4163         struct et131x_adapter *adapter = netdev_priv(netdev);
4164         struct pci_dev *pdev = adapter->pdev;
4165         unsigned int irq = pdev->irq;
4166         int result;
4167 
4168         /* Start the timer to track NIC errors */
4169         init_timer(&adapter->error_timer);
4170         adapter->error_timer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
4171         adapter->error_timer.function = et131x_error_timer_handler;
4172         adapter->error_timer.data = (unsigned long)adapter;
4173         add_timer(&adapter->error_timer);
4174 
4175         result = request_irq(irq, et131x_isr,
4176                              IRQF_SHARED, netdev->name, netdev);
4177         if (result) {
4178                 dev_err(&pdev->dev, "could not register IRQ %d\n", irq);
4179                 return result;
4180         }
4181 
4182         adapter->flags |= FMP_ADAPTER_INTERRUPT_IN_USE;
4183 
4184         et131x_up(netdev);
4185 
4186         return result;
4187 }
4188 
4189 /* et131x_close - Close the device */
4190 static int et131x_close(struct net_device *netdev)
4191 {
4192         struct et131x_adapter *adapter = netdev_priv(netdev);
4193 
4194         et131x_down(netdev);
4195 
4196         adapter->flags &= ~FMP_ADAPTER_INTERRUPT_IN_USE;
4197         free_irq(adapter->pdev->irq, netdev);
4198 
4199         /* Stop the error timer */
4200         return del_timer_sync(&adapter->error_timer);
4201 }
4202 
4203 /* et131x_ioctl - The I/O Control handler for the driver
4204  * @netdev: device on which the control request is being made
4205  * @reqbuf: a pointer to the IOCTL request buffer
4206  * @cmd: the IOCTL command code
4207  */
4208 static int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf,
4209                         int cmd)
4210 {
4211         struct et131x_adapter *adapter = netdev_priv(netdev);
4212 
4213         if (!adapter->phydev)
4214                 return -EINVAL;
4215 
4216         return phy_mii_ioctl(adapter->phydev, reqbuf, cmd);
4217 }
4218 
4219 /* et131x_set_packet_filter - Configures the Rx Packet filtering on the device
4220  * @adapter: pointer to our private adapter structure
4221  *
4222  * FIXME: lot of dups with MAC code
4223  */
4224 static int et131x_set_packet_filter(struct et131x_adapter *adapter)
4225 {
4226         int filter = adapter->packet_filter;
4227         u32 ctrl;
4228         u32 pf_ctrl;
4229 
4230         ctrl = readl(&adapter->regs->rxmac.ctrl);
4231         pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl);
4232 
4233         /* Default to disabled packet filtering.  Enable it in the individual
4234          * case statements that require the device to filter something
4235          */
4236         ctrl |= 0x04;
4237 
4238         /* Set us to be in promiscuous mode so we receive everything, this
4239          * is also true when we get a packet filter of 0
4240          */
4241         if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0)
4242                 pf_ctrl &= ~7;  /* Clear filter bits */
4243         else {
4244                 /* Set us up with Multicast packet filtering.  Three cases are
4245                  * possible - (1) we have a multi-cast list, (2) we receive ALL
4246                  * multicast entries or (3) we receive none.
4247                  */
4248                 if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST)
4249                         pf_ctrl &= ~2;  /* Multicast filter bit */
4250                 else {
4251                         et1310_setup_device_for_multicast(adapter);
4252                         pf_ctrl |= 2;
4253                         ctrl &= ~0x04;
4254                 }
4255 
4256                 /* Set us up with Unicast packet filtering */
4257                 if (filter & ET131X_PACKET_TYPE_DIRECTED) {
4258                         et1310_setup_device_for_unicast(adapter);
4259                         pf_ctrl |= 4;
4260                         ctrl &= ~0x04;
4261                 }
4262 
4263                 /* Set us up with Broadcast packet filtering */
4264                 if (filter & ET131X_PACKET_TYPE_BROADCAST) {
4265                         pf_ctrl |= 1;   /* Broadcast filter bit */
4266                         ctrl &= ~0x04;
4267                 } else
4268                         pf_ctrl &= ~1;
4269 
4270                 /* Setup the receive mac configuration registers - Packet
4271                  * Filter control + the enable / disable for packet filter
4272                  * in the control reg.
4273                  */
4274                 writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);
4275                 writel(ctrl, &adapter->regs->rxmac.ctrl);
4276         }
4277         return 0;
4278 }
4279 
4280 /* et131x_multicast - The handler to configure multicasting on the interface */
4281 static void et131x_multicast(struct net_device *netdev)
4282 {
4283         struct et131x_adapter *adapter = netdev_priv(netdev);
4284         int packet_filter;
4285         struct netdev_hw_addr *ha;
4286         int i;
4287 
4288         /* Before we modify the platform-independent filter flags, store them
4289          * locally. This allows us to determine if anything's changed and if
4290          * we even need to bother the hardware
4291          */
4292         packet_filter = adapter->packet_filter;
4293 
4294         /* Clear the 'multicast' flag locally; because we only have a single
4295          * flag to check multicast, and multiple multicast addresses can be
4296          * set, this is the easiest way to determine if more than one
4297          * multicast address is being set.
4298          */
4299         packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4300 
4301         /* Check the net_device flags and set the device independent flags
4302          * accordingly
4303          */
4304 
4305         if (netdev->flags & IFF_PROMISC)
4306                 adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS;
4307         else
4308                 adapter->packet_filter &= ~ET131X_PACKET_TYPE_PROMISCUOUS;
4309 
4310         if (netdev->flags & IFF_ALLMULTI)
4311                 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
4312 
4313         if (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST)
4314                 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
4315 
4316         if (netdev_mc_count(netdev) < 1) {
4317                 adapter->packet_filter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST;
4318                 adapter->packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4319         } else
4320                 adapter->packet_filter |= ET131X_PACKET_TYPE_MULTICAST;
4321 
4322         /* Set values in the private adapter struct */
4323         i = 0;
4324         netdev_for_each_mc_addr(ha, netdev) {
4325                 if (i == NIC_MAX_MCAST_LIST)
4326                         break;
4327                 memcpy(adapter->multicast_list[i++], ha->addr, ETH_ALEN);
4328         }
4329         adapter->multicast_addr_count = i;
4330 
4331         /* Are the new flags different from the previous ones? If not, then no
4332          * action is required
4333          *
4334          * NOTE - This block will always update the multicast_list with the
4335          *        hardware, even if the addresses aren't the same.
4336          */
4337         if (packet_filter != adapter->packet_filter)
4338                 et131x_set_packet_filter(adapter);
4339 }
4340 
4341 /* et131x_tx - The handler to tx a packet on the device */
4342 static int et131x_tx(struct sk_buff *skb, struct net_device *netdev)
4343 {
4344         int status = 0;
4345         struct et131x_adapter *adapter = netdev_priv(netdev);
4346         struct tx_ring *tx_ring = &adapter->tx_ring;
4347 
4348         /* stop the queue if it's getting full */
4349         if (tx_ring->used >= NUM_TCB - 1 && !netif_queue_stopped(netdev))
4350                 netif_stop_queue(netdev);
4351 
4352         /* Save the timestamp for the TX timeout watchdog */
4353         netdev->trans_start = jiffies;
4354 
4355         /* Call the device-specific data Tx routine */
4356         status = et131x_send_packets(skb, netdev);
4357 
4358         /* Check status and manage the netif queue if necessary */
4359         if (status != 0) {
4360                 if (status == -ENOMEM)
4361                         status = NETDEV_TX_BUSY;
4362                 else
4363                         status = NETDEV_TX_OK;
4364         }
4365         return status;
4366 }
4367 
4368 /* et131x_tx_timeout - Timeout handler
4369  *
4370  * The handler called when a Tx request times out. The timeout period is
4371  * specified by the 'tx_timeo" element in the net_device structure (see
4372  * et131x_alloc_device() to see how this value is set).
4373  */
4374 static void et131x_tx_timeout(struct net_device *netdev)
4375 {
4376         struct et131x_adapter *adapter = netdev_priv(netdev);
4377         struct tx_ring *tx_ring = &adapter->tx_ring;
4378         struct tcb *tcb;
4379         unsigned long flags;
4380 
4381         /* If the device is closed, ignore the timeout */
4382         if (~(adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE))
4383                 return;
4384 
4385         /* Any nonrecoverable hardware error?
4386          * Checks adapter->flags for any failure in phy reading
4387          */
4388         if (adapter->flags & FMP_ADAPTER_NON_RECOVER_ERROR)
4389                 return;
4390 
4391         /* Hardware failure? */
4392         if (adapter->flags & FMP_ADAPTER_HARDWARE_ERROR) {
4393                 dev_err(&adapter->pdev->dev, "hardware error - reset\n");
4394                 return;
4395         }
4396 
4397         /* Is send stuck? */
4398         spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
4399 
4400         tcb = tx_ring->send_head;
4401 
4402         if (tcb != NULL) {
4403                 tcb->count++;
4404 
4405                 if (tcb->count > NIC_SEND_HANG_THRESHOLD) {
4406                         spin_unlock_irqrestore(&adapter->tcb_send_qlock,
4407                                                flags);
4408 
4409                         dev_warn(&adapter->pdev->dev,
4410                                 "Send stuck - reset.  tcb->WrIndex %x, flags 0x%08x\n",
4411                                 tcb->index,
4412                                 tcb->flags);
4413 
4414                         adapter->netdev->stats.tx_errors++;
4415 
4416                         /* perform reset of tx/rx */
4417                         et131x_disable_txrx(netdev);
4418                         et131x_enable_txrx(netdev);
4419                         return;
4420                 }
4421         }
4422 
4423         spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
4424 }
4425 
4426 /* et131x_change_mtu - The handler called to change the MTU for the device */
4427 static int et131x_change_mtu(struct net_device *netdev, int new_mtu)
4428 {
4429         int result = 0;
4430         struct et131x_adapter *adapter = netdev_priv(netdev);
4431 
4432         /* Make sure the requested MTU is valid */
4433         if (new_mtu < 64 || new_mtu > 9216)
4434                 return -EINVAL;
4435 
4436         et131x_disable_txrx(netdev);
4437         et131x_handle_send_interrupt(adapter);
4438         et131x_handle_recv_interrupt(adapter);
4439 
4440         /* Set the new MTU */
4441         netdev->mtu = new_mtu;
4442 
4443         /* Free Rx DMA memory */
4444         et131x_adapter_memory_free(adapter);
4445 
4446         /* Set the config parameter for Jumbo Packet support */
4447         adapter->registry_jumbo_packet = new_mtu + 14;
4448         et131x_soft_reset(adapter);
4449 
4450         /* Alloc and init Rx DMA memory */
4451         result = et131x_adapter_memory_alloc(adapter);
4452         if (result != 0) {
4453                 dev_warn(&adapter->pdev->dev,
4454                         "Change MTU failed; couldn't re-alloc DMA memory\n");
4455                 return result;
4456         }
4457 
4458         et131x_init_send(adapter);
4459 
4460         et131x_hwaddr_init(adapter);
4461         memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
4462 
4463         /* Init the device with the new settings */
4464         et131x_adapter_setup(adapter);
4465 
4466         et131x_enable_txrx(netdev);
4467 
4468         return result;
4469 }
4470 
4471 /* et131x_set_mac_addr - handler to change the MAC address for the device */
4472 static int et131x_set_mac_addr(struct net_device *netdev, void *new_mac)
4473 {
4474         int result = 0;
4475         struct et131x_adapter *adapter = netdev_priv(netdev);
4476         struct sockaddr *address = new_mac;
4477 
4478         if (adapter == NULL)
4479                 return -ENODEV;
4480 
4481         /* Make sure the requested MAC is valid */
4482         if (!is_valid_ether_addr(address->sa_data))
4483                 return -EADDRNOTAVAIL;
4484 
4485         et131x_disable_txrx(netdev);
4486         et131x_handle_send_interrupt(adapter);
4487         et131x_handle_recv_interrupt(adapter);
4488 
4489         /* Set the new MAC */
4490         /* netdev->set_mac_address  = &new_mac; */
4491 
4492         memcpy(netdev->dev_addr, address->sa_data, netdev->addr_len);
4493 
4494         netdev_info(netdev, "Setting MAC address to %pM\n",
4495                     netdev->dev_addr);
4496 
4497         /* Free Rx DMA memory */
4498         et131x_adapter_memory_free(adapter);
4499 
4500         et131x_soft_reset(adapter);
4501 
4502         /* Alloc and init Rx DMA memory */
4503         result = et131x_adapter_memory_alloc(adapter);
4504         if (result != 0) {
4505                 dev_err(&adapter->pdev->dev,
4506                         "Change MAC failed; couldn't re-alloc DMA memory\n");
4507                 return result;
4508         }
4509 
4510         et131x_init_send(adapter);
4511 
4512         et131x_hwaddr_init(adapter);
4513 
4514         /* Init the device with the new settings */
4515         et131x_adapter_setup(adapter);
4516 
4517         et131x_enable_txrx(netdev);
4518 
4519         return result;
4520 }
4521 
4522 static const struct net_device_ops et131x_netdev_ops = {
4523         .ndo_open               = et131x_open,
4524         .ndo_stop               = et131x_close,
4525         .ndo_start_xmit         = et131x_tx,
4526         .ndo_set_rx_mode        = et131x_multicast,
4527         .ndo_tx_timeout         = et131x_tx_timeout,
4528         .ndo_change_mtu         = et131x_change_mtu,
4529         .ndo_set_mac_address    = et131x_set_mac_addr,
4530         .ndo_validate_addr      = eth_validate_addr,
4531         .ndo_get_stats          = et131x_stats,
4532         .ndo_do_ioctl           = et131x_ioctl,
4533 };
4534 
4535 /* et131x_pci_setup - Perform device initialization
4536  * @pdev: a pointer to the device's pci_dev structure
4537  * @ent: this device's entry in the pci_device_id table
4538  *
4539  * Registered in the pci_driver structure, this function is called when the
4540  * PCI subsystem finds a new PCI device which matches the information
4541  * contained in the pci_device_id table. This routine is the equivalent to
4542  * a device insertion routine.
4543  */
4544 static int et131x_pci_setup(struct pci_dev *pdev,
4545                             const struct pci_device_id *ent)
4546 {
4547         struct net_device *netdev;
4548         struct et131x_adapter *adapter;
4549         int rc;
4550         int ii;
4551 
4552         rc = pci_enable_device(pdev);
4553         if (rc < 0) {
4554                 dev_err(&pdev->dev, "pci_enable_device() failed\n");
4555                 goto out;
4556         }
4557 
4558         /* Perform some basic PCI checks */
4559         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4560                 dev_err(&pdev->dev, "Can't find PCI device's base address\n");
4561                 rc = -ENODEV;
4562                 goto err_disable;
4563         }
4564 
4565         rc = pci_request_regions(pdev, DRIVER_NAME);
4566         if (rc < 0) {
4567                 dev_err(&pdev->dev, "Can't get PCI resources\n");
4568                 goto err_disable;
4569         }
4570 
4571         pci_set_master(pdev);
4572 
4573         /* Check the DMA addressing support of this device */
4574         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
4575             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) {
4576                 dev_err(&pdev->dev, "No usable DMA addressing method\n");
4577                 rc = -EIO;
4578                 goto err_release_res;
4579         }
4580 
4581         /* Allocate netdev and private adapter structs */
4582         netdev = alloc_etherdev(sizeof(struct et131x_adapter));
4583         if (!netdev) {
4584                 dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
4585                 rc = -ENOMEM;
4586                 goto err_release_res;
4587         }
4588 
4589         netdev->watchdog_timeo = ET131X_TX_TIMEOUT;
4590         netdev->netdev_ops     = &et131x_netdev_ops;
4591 
4592         SET_NETDEV_DEV(netdev, &pdev->dev);
4593         netdev->ethtool_ops = &et131x_ethtool_ops;
4594 
4595         adapter = et131x_adapter_init(netdev, pdev);
4596 
4597         rc = et131x_pci_init(adapter, pdev);
4598         if (rc < 0)
4599                 goto err_free_dev;
4600 
4601         /* Map the bus-relative registers to system virtual memory */
4602         adapter->regs = pci_ioremap_bar(pdev, 0);
4603         if (!adapter->regs) {
4604                 dev_err(&pdev->dev, "Cannot map device registers\n");
4605                 rc = -ENOMEM;
4606                 goto err_free_dev;
4607         }
4608 
4609         /* If Phy COMA mode was enabled when we went down, disable it here. */
4610         writel(ET_PMCSR_INIT,  &adapter->regs->global.pm_csr);
4611 
4612         /* Issue a global reset to the et1310 */
4613         et131x_soft_reset(adapter);
4614 
4615         /* Disable all interrupts (paranoid) */
4616         et131x_disable_interrupts(adapter);
4617 
4618         /* Allocate DMA memory */
4619         rc = et131x_adapter_memory_alloc(adapter);
4620         if (rc < 0) {
4621                 dev_err(&pdev->dev, "Could not alloc adapter memory (DMA)\n");
4622                 goto err_iounmap;
4623         }
4624 
4625         /* Init send data structures */
4626         et131x_init_send(adapter);
4627 
4628         /* Set up the task structure for the ISR's deferred handler */
4629         INIT_WORK(&adapter->task, et131x_isr_handler);
4630 
4631         /* Copy address into the net_device struct */
4632         memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
4633 
4634         rc = -ENOMEM;
4635 
4636         /* Setup the mii_bus struct */
4637         adapter->mii_bus = mdiobus_alloc();
4638         if (!adapter->mii_bus) {
4639                 dev_err(&pdev->dev, "Alloc of mii_bus struct failed\n");
4640                 goto err_mem_free;
4641         }
4642 
4643         adapter->mii_bus->name = "et131x_eth_mii";
4644         snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x",
4645                 (adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
4646         adapter->mii_bus->priv = netdev;
4647         adapter->mii_bus->read = et131x_mdio_read;
4648         adapter->mii_bus->write = et131x_mdio_write;
4649         adapter->mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int),
4650                                               GFP_KERNEL);
4651         if (!adapter->mii_bus->irq)
4652                 goto err_mdio_free;
4653 
4654         for (ii = 0; ii < PHY_MAX_ADDR; ii++)
4655                 adapter->mii_bus->irq[ii] = PHY_POLL;
4656 
4657         rc = mdiobus_register(adapter->mii_bus);
4658         if (rc < 0) {
4659                 dev_err(&pdev->dev, "failed to register MII bus\n");
4660                 goto err_mdio_free_irq;
4661         }
4662 
4663         rc = et131x_mii_probe(netdev);
4664         if (rc < 0) {
4665                 dev_err(&pdev->dev, "failed to probe MII bus\n");
4666                 goto err_mdio_unregister;
4667         }
4668 
4669         /* Setup et1310 as per the documentation */
4670         et131x_adapter_setup(adapter);
4671 
4672         /* Init variable for counting how long we do not have link status */
4673         adapter->boot_coma = 0;
4674         et1310_disable_phy_coma(adapter);
4675 
4676         /* We can enable interrupts now
4677          *
4678          *  NOTE - Because registration of interrupt handler is done in the
4679          *         device's open(), defer enabling device interrupts to that
4680          *         point
4681          */
4682 
4683         /* Register the net_device struct with the Linux network layer */
4684         rc = register_netdev(netdev);
4685         if (rc < 0) {
4686                 dev_err(&pdev->dev, "register_netdev() failed\n");
4687                 goto err_phy_disconnect;
4688         }
4689 
4690         /* Register the net_device struct with the PCI subsystem. Save a copy
4691          * of the PCI config space for this device now that the device has
4692          * been initialized, just in case it needs to be quickly restored.
4693          */
4694         pci_set_drvdata(pdev, netdev);
4695 out:
4696         return rc;
4697 
4698 err_phy_disconnect:
4699         phy_disconnect(adapter->phydev);
4700 err_mdio_unregister:
4701         mdiobus_unregister(adapter->mii_bus);
4702 err_mdio_free_irq:
4703         kfree(adapter->mii_bus->irq);
4704 err_mdio_free:
4705         mdiobus_free(adapter->mii_bus);
4706 err_mem_free:
4707         et131x_adapter_memory_free(adapter);
4708 err_iounmap:
4709         iounmap(adapter->regs);
4710 err_free_dev:
4711         pci_dev_put(pdev);
4712         free_netdev(netdev);
4713 err_release_res:
4714         pci_release_regions(pdev);
4715 err_disable:
4716         pci_disable_device(pdev);
4717         goto out;
4718 }
4719 
4720 static const struct pci_device_id et131x_pci_table[] = {
4721         { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_GIG), 0UL},
4722         { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_FAST), 0UL},
4723         {0,}
4724 };
4725 MODULE_DEVICE_TABLE(pci, et131x_pci_table);
4726 
4727 static struct pci_driver et131x_driver = {
4728         .name           = DRIVER_NAME,
4729         .id_table       = et131x_pci_table,
4730         .probe          = et131x_pci_setup,
4731         .remove         = et131x_pci_remove,
4732         .driver.pm      = ET131X_PM_OPS,
4733 };
4734 
4735 module_pci_driver(et131x_driver);
4736 

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