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Linux/drivers/staging/comedi/drivers/s626.c

  1 /*
  2  * comedi/drivers/s626.c
  3  * Sensoray s626 Comedi driver
  4  *
  5  * COMEDI - Linux Control and Measurement Device Interface
  6  * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
  7  *
  8  * Based on Sensoray Model 626 Linux driver Version 0.2
  9  * Copyright (C) 2002-2004 Sensoray Co., Inc.
 10  *
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License as published by
 13  * the Free Software Foundation; either version 2 of the License, or
 14  * (at your option) any later version.
 15  *
 16  * This program is distributed in the hope that it will be useful,
 17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19  * GNU General Public License for more details.
 20  */
 21 
 22 /*
 23  * Driver: s626
 24  * Description: Sensoray 626 driver
 25  * Devices: [Sensoray] 626 (s626)
 26  * Authors: Gianluca Palli <gpalli@deis.unibo.it>,
 27  * Updated: Fri, 15 Feb 2008 10:28:42 +0000
 28  * Status: experimental
 29 
 30  * Configuration options: not applicable, uses PCI auto config
 31 
 32  * INSN_CONFIG instructions:
 33  *   analog input:
 34  *    none
 35  *
 36  *   analog output:
 37  *    none
 38  *
 39  *   digital channel:
 40  *    s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
 41  *    supported configuration options:
 42  *    INSN_CONFIG_DIO_QUERY
 43  *    COMEDI_INPUT
 44  *    COMEDI_OUTPUT
 45  *
 46  *   encoder:
 47  *    Every channel must be configured before reading.
 48  *
 49  *   Example code
 50  *
 51  *    insn.insn=INSN_CONFIG;   //configuration instruction
 52  *    insn.n=1;                //number of operation (must be 1)
 53  *    insn.data=&initialvalue; //initial value loaded into encoder
 54  *                             //during configuration
 55  *    insn.subdev=5;           //encoder subdevice
 56  *    insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
 57  *                                                         //to configure
 58  *
 59  *    comedi_do_insn(cf,&insn); //executing configuration
 60  */
 61 
 62 #include <linux/module.h>
 63 #include <linux/delay.h>
 64 #include <linux/pci.h>
 65 #include <linux/interrupt.h>
 66 #include <linux/kernel.h>
 67 #include <linux/types.h>
 68 
 69 #include "../comedidev.h"
 70 
 71 #include "comedi_fc.h"
 72 #include "s626.h"
 73 
 74 struct s626_buffer_dma {
 75         dma_addr_t physical_base;
 76         void *logical_base;
 77 };
 78 
 79 struct s626_private {
 80         uint8_t ai_cmd_running;         /* ai_cmd is running */
 81         int ai_sample_count;            /* number of samples to acquire */
 82         unsigned int ai_sample_timer;   /* time between samples in
 83                                          * units of the timer */
 84         int ai_convert_count;           /* conversion counter */
 85         unsigned int ai_convert_timer;  /* time between conversion in
 86                                          * units of the timer */
 87         uint16_t counter_int_enabs;     /* counter interrupt enable mask
 88                                          * for MISC2 register */
 89         uint8_t adc_items;              /* number of items in ADC poll list */
 90         struct s626_buffer_dma rps_buf; /* DMA buffer used to hold ADC (RPS1)
 91                                          * program */
 92         struct s626_buffer_dma ana_buf; /* DMA buffer used to receive ADC data
 93                                          * and hold DAC data */
 94         uint32_t *dac_wbuf;             /* pointer to logical adrs of DMA buffer
 95                                          * used to hold DAC data */
 96         uint16_t dacpol;                /* image of DAC polarity register */
 97         uint8_t trim_setpoint[12];      /* images of TrimDAC setpoints */
 98         uint32_t i2c_adrs;              /* I2C device address for onboard EEPROM
 99                                          * (board rev dependent) */
100 };
101 
102 /* Counter overflow/index event flag masks for RDMISC2. */
103 #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 +  4)))
104 #define S626_OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
105 
106 /*
107  * Enable/disable a function or test status bit(s) that are accessed
108  * through Main Control Registers 1 or 2.
109  */
110 static void s626_mc_enable(struct comedi_device *dev,
111                            unsigned int cmd, unsigned int reg)
112 {
113         unsigned int val = (cmd << 16) | cmd;
114 
115         mmiowb();
116         writel(val, dev->mmio + reg);
117 }
118 
119 static void s626_mc_disable(struct comedi_device *dev,
120                             unsigned int cmd, unsigned int reg)
121 {
122         writel(cmd << 16 , dev->mmio + reg);
123         mmiowb();
124 }
125 
126 static bool s626_mc_test(struct comedi_device *dev,
127                          unsigned int cmd, unsigned int reg)
128 {
129         unsigned int val;
130 
131         val = readl(dev->mmio + reg);
132 
133         return (val & cmd) ? true : false;
134 }
135 
136 #define S626_BUGFIX_STREG(REGADRS)   ((REGADRS) - 4)
137 
138 /* Write a time slot control record to TSL2. */
139 #define S626_VECTPORT(VECTNUM)          (S626_P_TSL2 + ((VECTNUM) << 2))
140 
141 static const struct comedi_lrange s626_range_table = {
142         2, {
143                 BIP_RANGE(5),
144                 BIP_RANGE(10)
145         }
146 };
147 
148 /*
149  * Execute a DEBI transfer.  This must be called from within a critical section.
150  */
151 static void s626_debi_transfer(struct comedi_device *dev)
152 {
153         static const int timeout = 10000;
154         int i;
155 
156         /* Initiate upload of shadow RAM to DEBI control register */
157         s626_mc_enable(dev, S626_MC2_UPLD_DEBI, S626_P_MC2);
158 
159         /*
160          * Wait for completion of upload from shadow RAM to
161          * DEBI control register.
162          */
163         for (i = 0; i < timeout; i++) {
164                 if (s626_mc_test(dev, S626_MC2_UPLD_DEBI, S626_P_MC2))
165                         break;
166                 udelay(1);
167         }
168         if (i == timeout)
169                 dev_err(dev->class_dev,
170                         "Timeout while uploading to DEBI control register\n");
171 
172         /* Wait until DEBI transfer is done */
173         for (i = 0; i < timeout; i++) {
174                 if (!(readl(dev->mmio + S626_P_PSR) & S626_PSR_DEBI_S))
175                         break;
176                 udelay(1);
177         }
178         if (i == timeout)
179                 dev_err(dev->class_dev, "DEBI transfer timeout\n");
180 }
181 
182 /*
183  * Read a value from a gate array register.
184  */
185 static uint16_t s626_debi_read(struct comedi_device *dev, uint16_t addr)
186 {
187         /* Set up DEBI control register value in shadow RAM */
188         writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD);
189 
190         /*  Execute the DEBI transfer. */
191         s626_debi_transfer(dev);
192 
193         return readl(dev->mmio + S626_P_DEBIAD);
194 }
195 
196 /*
197  * Write a value to a gate array register.
198  */
199 static void s626_debi_write(struct comedi_device *dev, uint16_t addr,
200                             uint16_t wdata)
201 {
202         /* Set up DEBI control register value in shadow RAM */
203         writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD);
204         writel(wdata, dev->mmio + S626_P_DEBIAD);
205 
206         /*  Execute the DEBI transfer. */
207         s626_debi_transfer(dev);
208 }
209 
210 /*
211  * Replace the specified bits in a gate array register.  Imports: mask
212  * specifies bits that are to be preserved, wdata is new value to be
213  * or'd with the masked original.
214  */
215 static void s626_debi_replace(struct comedi_device *dev, unsigned int addr,
216                               unsigned int mask, unsigned int wdata)
217 {
218         unsigned int val;
219 
220         addr &= 0xffff;
221         writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD);
222         s626_debi_transfer(dev);
223 
224         writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD);
225         val = readl(dev->mmio + S626_P_DEBIAD);
226         val &= mask;
227         val |= wdata;
228         writel(val & 0xffff, dev->mmio + S626_P_DEBIAD);
229         s626_debi_transfer(dev);
230 }
231 
232 /* **************  EEPROM ACCESS FUNCTIONS  ************** */
233 
234 static int s626_i2c_handshake_eoc(struct comedi_device *dev,
235                                  struct comedi_subdevice *s,
236                                  struct comedi_insn *insn,
237                                  unsigned long context)
238 {
239         bool status;
240 
241         status = s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
242         if (status)
243                 return 0;
244         return -EBUSY;
245 }
246 
247 static int s626_i2c_handshake(struct comedi_device *dev, uint32_t val)
248 {
249         unsigned int ctrl;
250         int ret;
251 
252         /* Write I2C command to I2C Transfer Control shadow register */
253         writel(val, dev->mmio + S626_P_I2CCTRL);
254 
255         /*
256          * Upload I2C shadow registers into working registers and
257          * wait for upload confirmation.
258          */
259         s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
260         ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
261         if (ret)
262                 return ret;
263 
264         /* Wait until I2C bus transfer is finished or an error occurs */
265         do {
266                 ctrl = readl(dev->mmio + S626_P_I2CCTRL);
267         } while ((ctrl & (S626_I2C_BUSY | S626_I2C_ERR)) == S626_I2C_BUSY);
268 
269         /* Return non-zero if I2C error occurred */
270         return ctrl & S626_I2C_ERR;
271 }
272 
273 /* Read uint8_t from EEPROM. */
274 static uint8_t s626_i2c_read(struct comedi_device *dev, uint8_t addr)
275 {
276         struct s626_private *devpriv = dev->private;
277 
278         /*
279          * Send EEPROM target address:
280          *  Byte2 = I2C command: write to I2C EEPROM device.
281          *  Byte1 = EEPROM internal target address.
282          *  Byte0 = Not sent.
283          */
284         if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
285                                                 devpriv->i2c_adrs) |
286                                     S626_I2C_B1(S626_I2C_ATTRSTOP, addr) |
287                                     S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
288                 /* Abort function and declare error if handshake failed. */
289                 return 0;
290 
291         /*
292          * Execute EEPROM read:
293          *  Byte2 = I2C command: read from I2C EEPROM device.
294          *  Byte1 receives uint8_t from EEPROM.
295          *  Byte0 = Not sent.
296          */
297         if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
298                                            (devpriv->i2c_adrs | 1)) |
299                                     S626_I2C_B1(S626_I2C_ATTRSTOP, 0) |
300                                     S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
301                 /* Abort function and declare error if handshake failed. */
302                 return 0;
303 
304         return (readl(dev->mmio + S626_P_I2CCTRL) >> 16) & 0xff;
305 }
306 
307 /* ***********  DAC FUNCTIONS *********** */
308 
309 /* TrimDac LogicalChan-to-PhysicalChan mapping table. */
310 static const uint8_t s626_trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
311 
312 /* TrimDac LogicalChan-to-EepromAdrs mapping table. */
313 static const uint8_t s626_trimadrs[] = {
314         0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63
315 };
316 
317 enum {
318         s626_send_dac_wait_not_mc1_a2out,
319         s626_send_dac_wait_ssr_af2_out,
320         s626_send_dac_wait_fb_buffer2_msb_00,
321         s626_send_dac_wait_fb_buffer2_msb_ff
322 };
323 
324 static int s626_send_dac_eoc(struct comedi_device *dev,
325                              struct comedi_subdevice *s,
326                              struct comedi_insn *insn,
327                              unsigned long context)
328 {
329         unsigned int status;
330 
331         switch (context) {
332         case s626_send_dac_wait_not_mc1_a2out:
333                 status = readl(dev->mmio + S626_P_MC1);
334                 if (!(status & S626_MC1_A2OUT))
335                         return 0;
336                 break;
337         case s626_send_dac_wait_ssr_af2_out:
338                 status = readl(dev->mmio + S626_P_SSR);
339                 if (status & S626_SSR_AF2_OUT)
340                         return 0;
341                 break;
342         case s626_send_dac_wait_fb_buffer2_msb_00:
343                 status = readl(dev->mmio + S626_P_FB_BUFFER2);
344                 if (!(status & 0xff000000))
345                         return 0;
346                 break;
347         case s626_send_dac_wait_fb_buffer2_msb_ff:
348                 status = readl(dev->mmio + S626_P_FB_BUFFER2);
349                 if (status & 0xff000000)
350                         return 0;
351                 break;
352         default:
353                 return -EINVAL;
354         }
355         return -EBUSY;
356 }
357 
358 /*
359  * Private helper function: Transmit serial data to DAC via Audio
360  * channel 2.  Assumes: (1) TSL2 slot records initialized, and (2)
361  * dacpol contains valid target image.
362  */
363 static int s626_send_dac(struct comedi_device *dev, uint32_t val)
364 {
365         struct s626_private *devpriv = dev->private;
366         int ret;
367 
368         /* START THE SERIAL CLOCK RUNNING ------------- */
369 
370         /*
371          * Assert DAC polarity control and enable gating of DAC serial clock
372          * and audio bit stream signals.  At this point in time we must be
373          * assured of being in time slot 0.  If we are not in slot 0, the
374          * serial clock and audio stream signals will be disabled; this is
375          * because the following s626_debi_write statement (which enables
376          * signals to be passed through the gate array) would execute before
377          * the trailing edge of WS1/WS3 (which turns off the signals), thus
378          * causing the signals to be inactive during the DAC write.
379          */
380         s626_debi_write(dev, S626_LP_DACPOL, devpriv->dacpol);
381 
382         /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
383 
384         /* Copy DAC setpoint value to DAC's output DMA buffer. */
385         /* writel(val, dev->mmio + (uint32_t)devpriv->dac_wbuf); */
386         *devpriv->dac_wbuf = val;
387 
388         /*
389          * Enable the output DMA transfer. This will cause the DMAC to copy
390          * the DAC's data value to A2's output FIFO. The DMA transfer will
391          * then immediately terminate because the protection address is
392          * reached upon transfer of the first DWORD value.
393          */
394         s626_mc_enable(dev, S626_MC1_A2OUT, S626_P_MC1);
395 
396         /* While the DMA transfer is executing ... */
397 
398         /*
399          * Reset Audio2 output FIFO's underflow flag (along with any
400          * other FIFO underflow/overflow flags). When set, this flag
401          * will indicate that we have emerged from slot 0.
402          */
403         writel(S626_ISR_AFOU, dev->mmio + S626_P_ISR);
404 
405         /*
406          * Wait for the DMA transfer to finish so that there will be data
407          * available in the FIFO when time slot 1 tries to transfer a DWORD
408          * from the FIFO to the output buffer register.  We test for DMA
409          * Done by polling the DMAC enable flag; this flag is automatically
410          * cleared when the transfer has finished.
411          */
412         ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
413                              s626_send_dac_wait_not_mc1_a2out);
414         if (ret) {
415                 dev_err(dev->class_dev, "DMA transfer timeout\n");
416                 return ret;
417         }
418 
419         /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
420 
421         /*
422          * FIFO data is now available, so we enable execution of time slots
423          * 1 and higher by clearing the EOS flag in slot 0.  Note that SD3
424          * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
425          * detection.
426          */
427         writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2,
428                dev->mmio + S626_VECTPORT(0));
429 
430         /*
431          * Wait for slot 1 to execute to ensure that the Packet will be
432          * transmitted.  This is detected by polling the Audio2 output FIFO
433          * underflow flag, which will be set when slot 1 execution has
434          * finished transferring the DAC's data DWORD from the output FIFO
435          * to the output buffer register.
436          */
437         ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
438                              s626_send_dac_wait_ssr_af2_out);
439         if (ret) {
440                 dev_err(dev->class_dev,
441                         "TSL timeout waiting for slot 1 to execute\n");
442                 return ret;
443         }
444 
445         /*
446          * Set up to trap execution at slot 0 when the TSL sequencer cycles
447          * back to slot 0 after executing the EOS in slot 5.  Also,
448          * simultaneously shift out and in the 0x00 that is ALWAYS the value
449          * stored in the last byte to be shifted out of the FIFO's DWORD
450          * buffer register.
451          */
452         writel(S626_XSD2 | S626_XFIFO_2 | S626_RSD2 | S626_SIB_A2 | S626_EOS,
453                dev->mmio + S626_VECTPORT(0));
454 
455         /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
456 
457         /*
458          * Wait for the TSL to finish executing all time slots before
459          * exiting this function.  We must do this so that the next DAC
460          * write doesn't start, thereby enabling clock/chip select signals:
461          *
462          * 1. Before the TSL sequence cycles back to slot 0, which disables
463          *    the clock/cs signal gating and traps slot // list execution.
464          *    we have not yet finished slot 5 then the clock/cs signals are
465          *    still gated and we have not finished transmitting the stream.
466          *
467          * 2. While slots 2-5 are executing due to a late slot 0 trap.  In
468          *    this case, the slot sequence is currently repeating, but with
469          *    clock/cs signals disabled.  We must wait for slot 0 to trap
470          *    execution before setting up the next DAC setpoint DMA transfer
471          *    and enabling the clock/cs signals.  To detect the end of slot 5,
472          *    we test for the FB_BUFFER2 MSB contents to be equal to 0xFF.  If
473          *    the TSL has not yet finished executing slot 5 ...
474          */
475         if (readl(dev->mmio + S626_P_FB_BUFFER2) & 0xff000000) {
476                 /*
477                  * The trap was set on time and we are still executing somewhere
478                  * in slots 2-5, so we now wait for slot 0 to execute and trap
479                  * TSL execution.  This is detected when FB_BUFFER2 MSB changes
480                  * from 0xFF to 0x00, which slot 0 causes to happen by shifting
481                  * out/in on SD2 the 0x00 that is always referenced by slot 5.
482                  */
483                 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
484                                      s626_send_dac_wait_fb_buffer2_msb_00);
485                 if (ret) {
486                         dev_err(dev->class_dev,
487                                 "TSL timeout waiting for slot 0 to execute\n");
488                         return ret;
489                 }
490         }
491         /*
492          * Either (1) we were too late setting the slot 0 trap; the TSL
493          * sequencer restarted slot 0 before we could set the EOS trap flag,
494          * or (2) we were not late and execution is now trapped at slot 0.
495          * In either case, we must now change slot 0 so that it will store
496          * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
497          * In order to do this, we reprogram slot 0 so that it will shift in
498          * SD3, which is driven only by a pull-up resistor.
499          */
500         writel(S626_RSD3 | S626_SIB_A2 | S626_EOS,
501                dev->mmio + S626_VECTPORT(0));
502 
503         /*
504          * Wait for slot 0 to execute, at which time the TSL is setup for
505          * the next DAC write.  This is detected when FB_BUFFER2 MSB changes
506          * from 0x00 to 0xFF.
507          */
508         ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
509                              s626_send_dac_wait_fb_buffer2_msb_ff);
510         if (ret) {
511                 dev_err(dev->class_dev,
512                         "TSL timeout waiting for slot 0 to execute\n");
513                 return ret;
514         }
515         return 0;
516 }
517 
518 /*
519  * Private helper function: Write setpoint to an application DAC channel.
520  */
521 static int s626_set_dac(struct comedi_device *dev, uint16_t chan,
522                          int16_t dacdata)
523 {
524         struct s626_private *devpriv = dev->private;
525         uint16_t signmask;
526         uint32_t ws_image;
527         uint32_t val;
528 
529         /*
530          * Adjust DAC data polarity and set up Polarity Control Register image.
531          */
532         signmask = 1 << chan;
533         if (dacdata < 0) {
534                 dacdata = -dacdata;
535                 devpriv->dacpol |= signmask;
536         } else {
537                 devpriv->dacpol &= ~signmask;
538         }
539 
540         /* Limit DAC setpoint value to valid range. */
541         if ((uint16_t)dacdata > 0x1FFF)
542                 dacdata = 0x1FFF;
543 
544         /*
545          * Set up TSL2 records (aka "vectors") for DAC update.  Vectors V2
546          * and V3 transmit the setpoint to the target DAC.  V4 and V5 send
547          * data to a non-existent TrimDac channel just to keep the clock
548          * running after sending data to the target DAC.  This is necessary
549          * to eliminate the clock glitch that would otherwise occur at the
550          * end of the target DAC's serial data stream.  When the sequence
551          * restarts at V0 (after executing V5), the gate array automatically
552          * disables gating for the DAC clock and all DAC chip selects.
553          */
554 
555         /* Choose DAC chip select to be asserted */
556         ws_image = (chan & 2) ? S626_WS1 : S626_WS2;
557         /* Slot 2: Transmit high data byte to target DAC */
558         writel(S626_XSD2 | S626_XFIFO_1 | ws_image,
559                dev->mmio + S626_VECTPORT(2));
560         /* Slot 3: Transmit low data byte to target DAC */
561         writel(S626_XSD2 | S626_XFIFO_0 | ws_image,
562                dev->mmio + S626_VECTPORT(3));
563         /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
564         writel(S626_XSD2 | S626_XFIFO_3 | S626_WS3,
565                dev->mmio + S626_VECTPORT(4));
566         /* Slot 5: running after writing target DAC's low data byte */
567         writel(S626_XSD2 | S626_XFIFO_2 | S626_WS3 | S626_EOS,
568                dev->mmio + S626_VECTPORT(5));
569 
570         /*
571          * Construct and transmit target DAC's serial packet:
572          * (A10D DDDD), (DDDD DDDD), (0x0F), (0x00) where A is chan<0>,
573          * and D<12:0> is the DAC setpoint.  Append a WORD value (that writes
574          * to a  non-existent TrimDac channel) that serves to keep the clock
575          * running after the packet has been sent to the target DAC.
576          */
577         val = 0x0F000000;       /* Continue clock after target DAC data
578                                  * (write to non-existent trimdac). */
579         val |= 0x00004000;      /* Address the two main dual-DAC devices
580                                  * (TSL's chip select enables target device). */
581         val |= ((uint32_t)(chan & 1) << 15);    /* Address the DAC channel
582                                                  * within the device. */
583         val |= (uint32_t)dacdata;       /* Include DAC setpoint data. */
584         return s626_send_dac(dev, val);
585 }
586 
587 static int s626_write_trim_dac(struct comedi_device *dev, uint8_t logical_chan,
588                                 uint8_t dac_data)
589 {
590         struct s626_private *devpriv = dev->private;
591         uint32_t chan;
592 
593         /*
594          * Save the new setpoint in case the application needs to read it back
595          * later.
596          */
597         devpriv->trim_setpoint[logical_chan] = (uint8_t)dac_data;
598 
599         /* Map logical channel number to physical channel number. */
600         chan = s626_trimchan[logical_chan];
601 
602         /*
603          * Set up TSL2 records for TrimDac write operation.  All slots shift
604          * 0xFF in from pulled-up SD3 so that the end of the slot sequence
605          * can be detected.
606          */
607 
608         /* Slot 2: Send high uint8_t to target TrimDac */
609         writel(S626_XSD2 | S626_XFIFO_1 | S626_WS3,
610                dev->mmio + S626_VECTPORT(2));
611         /* Slot 3: Send low uint8_t to target TrimDac */
612         writel(S626_XSD2 | S626_XFIFO_0 | S626_WS3,
613                dev->mmio + S626_VECTPORT(3));
614         /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */
615         writel(S626_XSD2 | S626_XFIFO_3 | S626_WS1,
616                dev->mmio + S626_VECTPORT(4));
617         /* Slot 5: Send NOP low  uint8_t to DAC0 */
618         writel(S626_XSD2 | S626_XFIFO_2 | S626_WS1 | S626_EOS,
619                dev->mmio + S626_VECTPORT(5));
620 
621         /*
622          * Construct and transmit target DAC's serial packet:
623          * (0000 AAAA), (DDDD DDDD), (0x00), (0x00) where A<3:0> is the
624          * DAC channel's address, and D<7:0> is the DAC setpoint.  Append a
625          * WORD value (that writes a channel 0 NOP command to a non-existent
626          * main DAC channel) that serves to keep the clock running after the
627          * packet has been sent to the target DAC.
628          */
629 
630         /*
631          * Address the DAC channel within the trimdac device.
632          * Include DAC setpoint data.
633          */
634         return s626_send_dac(dev, (chan << 8) | dac_data);
635 }
636 
637 static int s626_load_trim_dacs(struct comedi_device *dev)
638 {
639         uint8_t i;
640         int ret;
641 
642         /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
643         for (i = 0; i < ARRAY_SIZE(s626_trimchan); i++) {
644                 ret = s626_write_trim_dac(dev, i,
645                                     s626_i2c_read(dev, s626_trimadrs[i]));
646                 if (ret)
647                         return ret;
648         }
649         return 0;
650 }
651 
652 /* ******  COUNTER FUNCTIONS  ******* */
653 
654 /*
655  * All counter functions address a specific counter by means of the
656  * "Counter" argument, which is a logical counter number.  The Counter
657  * argument may have any of the following legal values: 0=0A, 1=1A,
658  * 2=2A, 3=0B, 4=1B, 5=2B.
659  */
660 
661 /*
662  * Return/set a counter pair's latch trigger source.  0: On read
663  * access, 1: A index latches A, 2: B index latches B, 3: A overflow
664  * latches B.
665  */
666 static void s626_set_latch_source(struct comedi_device *dev,
667                                   unsigned int chan, uint16_t value)
668 {
669         s626_debi_replace(dev, S626_LP_CRB(chan),
670                           ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_LATCHSRC),
671                           S626_SET_CRB_LATCHSRC(value));
672 }
673 
674 /*
675  * Write value into counter preload register.
676  */
677 static void s626_preload(struct comedi_device *dev,
678                          unsigned int chan, uint32_t value)
679 {
680         s626_debi_write(dev, S626_LP_CNTR(chan), value);
681         s626_debi_write(dev, S626_LP_CNTR(chan) + 2, value >> 16);
682 }
683 
684 /* ******  PRIVATE COUNTER FUNCTIONS ****** */
685 
686 /*
687  * Reset a counter's index and overflow event capture flags.
688  */
689 static void s626_reset_cap_flags(struct comedi_device *dev,
690                                  unsigned int chan)
691 {
692         uint16_t set;
693 
694         set = S626_SET_CRB_INTRESETCMD(1);
695         if (chan < 3)
696                 set |= S626_SET_CRB_INTRESET_A(1);
697         else
698                 set |= S626_SET_CRB_INTRESET_B(1);
699 
700         s626_debi_replace(dev, S626_LP_CRB(chan), ~S626_CRBMSK_INTCTRL, set);
701 }
702 
703 #ifdef unused
704 /*
705  * Return counter setup in a format (COUNTER_SETUP) that is consistent
706  * for both A and B counters.
707  */
708 static uint16_t s626_get_mode_a(struct comedi_device *dev,
709                                 unsigned int chan)
710 {
711         uint16_t cra;
712         uint16_t crb;
713         uint16_t setup;
714         unsigned cntsrc, clkmult, clkpol, encmode;
715 
716         /* Fetch CRA and CRB register images. */
717         cra = s626_debi_read(dev, S626_LP_CRA(chan));
718         crb = s626_debi_read(dev, S626_LP_CRB(chan));
719 
720         /*
721          * Populate the standardized counter setup bit fields.
722          */
723         setup =
724                 /* LoadSrc  = LoadSrcA. */
725                 S626_SET_STD_LOADSRC(S626_GET_CRA_LOADSRC_A(cra)) |
726                 /* LatchSrc = LatchSrcA. */
727                 S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) |
728                 /* IntSrc   = IntSrcA. */
729                 S626_SET_STD_INTSRC(S626_GET_CRA_INTSRC_A(cra)) |
730                 /* IndxSrc  = IndxSrcA. */
731                 S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_A(cra)) |
732                 /* IndxPol  = IndxPolA. */
733                 S626_SET_STD_INDXPOL(S626_GET_CRA_INDXPOL_A(cra)) |
734                 /* ClkEnab  = ClkEnabA. */
735                 S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_A(crb));
736 
737         /* Adjust mode-dependent parameters. */
738         cntsrc = S626_GET_CRA_CNTSRC_A(cra);
739         if (cntsrc & S626_CNTSRC_SYSCLK) {
740                 /* Timer mode (CntSrcA<1> == 1): */
741                 encmode = S626_ENCMODE_TIMER;
742                 /* Set ClkPol to indicate count direction (CntSrcA<0>). */
743                 clkpol = cntsrc & 1;
744                 /* ClkMult must be 1x in Timer mode. */
745                 clkmult = S626_CLKMULT_1X;
746         } else {
747                 /* Counter mode (CntSrcA<1> == 0): */
748                 encmode = S626_ENCMODE_COUNTER;
749                 /* Pass through ClkPol. */
750                 clkpol = S626_GET_CRA_CLKPOL_A(cra);
751                 /* Force ClkMult to 1x if not legal, else pass through. */
752                 clkmult = S626_GET_CRA_CLKMULT_A(cra);
753                 if (clkmult == S626_CLKMULT_SPECIAL)
754                         clkmult = S626_CLKMULT_1X;
755         }
756         setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) |
757                  S626_SET_STD_CLKPOL(clkpol);
758 
759         /* Return adjusted counter setup. */
760         return setup;
761 }
762 
763 static uint16_t s626_get_mode_b(struct comedi_device *dev,
764                                 unsigned int chan)
765 {
766         uint16_t cra;
767         uint16_t crb;
768         uint16_t setup;
769         unsigned cntsrc, clkmult, clkpol, encmode;
770 
771         /* Fetch CRA and CRB register images. */
772         cra = s626_debi_read(dev, S626_LP_CRA(chan));
773         crb = s626_debi_read(dev, S626_LP_CRB(chan));
774 
775         /*
776          * Populate the standardized counter setup bit fields.
777          */
778         setup =
779                 /* IntSrc   = IntSrcB. */
780                 S626_SET_STD_INTSRC(S626_GET_CRB_INTSRC_B(crb)) |
781                 /* LatchSrc = LatchSrcB. */
782                 S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) |
783                 /* LoadSrc  = LoadSrcB. */
784                 S626_SET_STD_LOADSRC(S626_GET_CRB_LOADSRC_B(crb)) |
785                 /* IndxPol  = IndxPolB. */
786                 S626_SET_STD_INDXPOL(S626_GET_CRB_INDXPOL_B(crb)) |
787                 /* ClkEnab  = ClkEnabB. */
788                 S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_B(crb)) |
789                 /* IndxSrc  = IndxSrcB. */
790                 S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_B(cra));
791 
792         /* Adjust mode-dependent parameters. */
793         cntsrc = S626_GET_CRA_CNTSRC_B(cra);
794         clkmult = S626_GET_CRB_CLKMULT_B(crb);
795         if (clkmult == S626_CLKMULT_SPECIAL) {
796                 /* Extender mode (ClkMultB == S626_CLKMULT_SPECIAL): */
797                 encmode = S626_ENCMODE_EXTENDER;
798                 /* Indicate multiplier is 1x. */
799                 clkmult = S626_CLKMULT_1X;
800                 /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
801                 clkpol = cntsrc & 1;
802         } else if (cntsrc & S626_CNTSRC_SYSCLK) {
803                 /* Timer mode (CntSrcB<1> == 1): */
804                 encmode = S626_ENCMODE_TIMER;
805                 /* Indicate multiplier is 1x. */
806                 clkmult = S626_CLKMULT_1X;
807                 /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
808                 clkpol = cntsrc & 1;
809         } else {
810                 /* If Counter mode (CntSrcB<1> == 0): */
811                 encmode = S626_ENCMODE_COUNTER;
812                 /* Clock multiplier is passed through. */
813                 /* Clock polarity is passed through. */
814                 clkpol = S626_GET_CRB_CLKPOL_B(crb);
815         }
816         setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) |
817                  S626_SET_STD_CLKPOL(clkpol);
818 
819         /* Return adjusted counter setup. */
820         return setup;
821 }
822 
823 static uint16_t s626_get_mode(struct comedi_device *dev,
824                               unsigned int chan)
825 {
826         return (chan < 3) ? s626_get_mode_a(dev, chan)
827                           : s626_get_mode_b(dev, chan);
828 }
829 #endif
830 
831 /*
832  * Set the operating mode for the specified counter.  The setup
833  * parameter is treated as a COUNTER_SETUP data type.  The following
834  * parameters are programmable (all other parms are ignored): ClkMult,
835  * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
836  */
837 static void s626_set_mode_a(struct comedi_device *dev,
838                             unsigned int chan, uint16_t setup,
839                             uint16_t disable_int_src)
840 {
841         struct s626_private *devpriv = dev->private;
842         uint16_t cra;
843         uint16_t crb;
844         unsigned cntsrc, clkmult, clkpol;
845 
846         /* Initialize CRA and CRB images. */
847         /* Preload trigger is passed through. */
848         cra = S626_SET_CRA_LOADSRC_A(S626_GET_STD_LOADSRC(setup));
849         /* IndexSrc is passed through. */
850         cra |= S626_SET_CRA_INDXSRC_A(S626_GET_STD_INDXSRC(setup));
851 
852         /* Reset any pending CounterA event captures. */
853         crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_A(1);
854         /* Clock enable is passed through. */
855         crb |= S626_SET_CRB_CLKENAB_A(S626_GET_STD_CLKENAB(setup));
856 
857         /* Force IntSrc to Disabled if disable_int_src is asserted. */
858         if (!disable_int_src)
859                 cra |= S626_SET_CRA_INTSRC_A(S626_GET_STD_INTSRC(setup));
860 
861         /* Populate all mode-dependent attributes of CRA & CRB images. */
862         clkpol = S626_GET_STD_CLKPOL(setup);
863         switch (S626_GET_STD_ENCMODE(setup)) {
864         case S626_ENCMODE_EXTENDER: /* Extender Mode: */
865                 /* Force to Timer mode (Extender valid only for B counters). */
866                 /* Fall through to case S626_ENCMODE_TIMER: */
867         case S626_ENCMODE_TIMER:        /* Timer Mode: */
868                 /* CntSrcA<1> selects system clock */
869                 cntsrc = S626_CNTSRC_SYSCLK;
870                 /* Count direction (CntSrcA<0>) obtained from ClkPol. */
871                 cntsrc |= clkpol;
872                 /* ClkPolA behaves as always-on clock enable. */
873                 clkpol = 1;
874                 /* ClkMult must be 1x. */
875                 clkmult = S626_CLKMULT_1X;
876                 break;
877         default:                /* Counter Mode: */
878                 /* Select ENC_C and ENC_D as clock/direction inputs. */
879                 cntsrc = S626_CNTSRC_ENCODER;
880                 /* Clock polarity is passed through. */
881                 /* Force multiplier to x1 if not legal, else pass through. */
882                 clkmult = S626_GET_STD_CLKMULT(setup);
883                 if (clkmult == S626_CLKMULT_SPECIAL)
884                         clkmult = S626_CLKMULT_1X;
885                 break;
886         }
887         cra |= S626_SET_CRA_CNTSRC_A(cntsrc) | S626_SET_CRA_CLKPOL_A(clkpol) |
888                S626_SET_CRA_CLKMULT_A(clkmult);
889 
890         /*
891          * Force positive index polarity if IndxSrc is software-driven only,
892          * otherwise pass it through.
893          */
894         if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
895                 cra |= S626_SET_CRA_INDXPOL_A(S626_GET_STD_INDXPOL(setup));
896 
897         /*
898          * If IntSrc has been forced to Disabled, update the MISC2 interrupt
899          * enable mask to indicate the counter interrupt is disabled.
900          */
901         if (disable_int_src)
902                 devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
903                                                 S626_INDXMASK(chan));
904 
905         /*
906          * While retaining CounterB and LatchSrc configurations, program the
907          * new counter operating mode.
908          */
909         s626_debi_replace(dev, S626_LP_CRA(chan),
910                           S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B, cra);
911         s626_debi_replace(dev, S626_LP_CRB(chan),
912                           ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), crb);
913 }
914 
915 static void s626_set_mode_b(struct comedi_device *dev,
916                             unsigned int chan, uint16_t setup,
917                             uint16_t disable_int_src)
918 {
919         struct s626_private *devpriv = dev->private;
920         uint16_t cra;
921         uint16_t crb;
922         unsigned cntsrc, clkmult, clkpol;
923 
924         /* Initialize CRA and CRB images. */
925         /* IndexSrc is passed through. */
926         cra = S626_SET_CRA_INDXSRC_B(S626_GET_STD_INDXSRC(setup));
927 
928         /* Reset event captures and disable interrupts. */
929         crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_B(1);
930         /* Clock enable is passed through. */
931         crb |= S626_SET_CRB_CLKENAB_B(S626_GET_STD_CLKENAB(setup));
932         /* Preload trigger source is passed through. */
933         crb |= S626_SET_CRB_LOADSRC_B(S626_GET_STD_LOADSRC(setup));
934 
935         /* Force IntSrc to Disabled if disable_int_src is asserted. */
936         if (!disable_int_src)
937                 crb |= S626_SET_CRB_INTSRC_B(S626_GET_STD_INTSRC(setup));
938 
939         /* Populate all mode-dependent attributes of CRA & CRB images. */
940         clkpol = S626_GET_STD_CLKPOL(setup);
941         switch (S626_GET_STD_ENCMODE(setup)) {
942         case S626_ENCMODE_TIMER:        /* Timer Mode: */
943                 /* CntSrcB<1> selects system clock */
944                 cntsrc = S626_CNTSRC_SYSCLK;
945                 /* with direction (CntSrcB<0>) obtained from ClkPol. */
946                 cntsrc |= clkpol;
947                 /* ClkPolB behaves as always-on clock enable. */
948                 clkpol = 1;
949                 /* ClkMultB must be 1x. */
950                 clkmult = S626_CLKMULT_1X;
951                 break;
952         case S626_ENCMODE_EXTENDER:     /* Extender Mode: */
953                 /* CntSrcB source is OverflowA (same as "timer") */
954                 cntsrc = S626_CNTSRC_SYSCLK;
955                 /* with direction obtained from ClkPol. */
956                 cntsrc |= clkpol;
957                 /* ClkPolB controls IndexB -- always set to active. */
958                 clkpol = 1;
959                 /* ClkMultB selects OverflowA as the clock source. */
960                 clkmult = S626_CLKMULT_SPECIAL;
961                 break;
962         default:                /* Counter Mode: */
963                 /* Select ENC_C and ENC_D as clock/direction inputs. */
964                 cntsrc = S626_CNTSRC_ENCODER;
965                 /* ClkPol is passed through. */
966                 /* Force ClkMult to x1 if not legal, otherwise pass through. */
967                 clkmult = S626_GET_STD_CLKMULT(setup);
968                 if (clkmult == S626_CLKMULT_SPECIAL)
969                         clkmult = S626_CLKMULT_1X;
970                 break;
971         }
972         cra |= S626_SET_CRA_CNTSRC_B(cntsrc);
973         crb |= S626_SET_CRB_CLKPOL_B(clkpol) | S626_SET_CRB_CLKMULT_B(clkmult);
974 
975         /*
976          * Force positive index polarity if IndxSrc is software-driven only,
977          * otherwise pass it through.
978          */
979         if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
980                 crb |= S626_SET_CRB_INDXPOL_B(S626_GET_STD_INDXPOL(setup));
981 
982         /*
983          * If IntSrc has been forced to Disabled, update the MISC2 interrupt
984          * enable mask to indicate the counter interrupt is disabled.
985          */
986         if (disable_int_src)
987                 devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
988                                                 S626_INDXMASK(chan));
989 
990         /*
991          * While retaining CounterA and LatchSrc configurations, program the
992          * new counter operating mode.
993          */
994         s626_debi_replace(dev, S626_LP_CRA(chan),
995                           ~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B), cra);
996         s626_debi_replace(dev, S626_LP_CRB(chan),
997                           S626_CRBMSK_CLKENAB_A | S626_CRBMSK_LATCHSRC, crb);
998 }
999 
1000 static void s626_set_mode(struct comedi_device *dev,
1001                           unsigned int chan,
1002                           uint16_t setup, uint16_t disable_int_src)
1003 {
1004         if (chan < 3)
1005                 s626_set_mode_a(dev, chan, setup, disable_int_src);
1006         else
1007                 s626_set_mode_b(dev, chan, setup, disable_int_src);
1008 }
1009 
1010 /*
1011  * Return/set a counter's enable.  enab: 0=always enabled, 1=enabled by index.
1012  */
1013 static void s626_set_enable(struct comedi_device *dev,
1014                             unsigned int chan, uint16_t enab)
1015 {
1016         unsigned int mask = S626_CRBMSK_INTCTRL;
1017         unsigned int set;
1018 
1019         if (chan < 3) {
1020                 mask |= S626_CRBMSK_CLKENAB_A;
1021                 set = S626_SET_CRB_CLKENAB_A(enab);
1022         } else {
1023                 mask |= S626_CRBMSK_CLKENAB_B;
1024                 set = S626_SET_CRB_CLKENAB_B(enab);
1025         }
1026         s626_debi_replace(dev, S626_LP_CRB(chan), ~mask, set);
1027 }
1028 
1029 #ifdef unused
1030 static uint16_t s626_get_enable(struct comedi_device *dev,
1031                                 unsigned int chan)
1032 {
1033         uint16_t crb = s626_debi_read(dev, S626_LP_CRB(chan));
1034 
1035         return (chan < 3) ? S626_GET_CRB_CLKENAB_A(crb)
1036                           : S626_GET_CRB_CLKENAB_B(crb);
1037 }
1038 #endif
1039 
1040 #ifdef unused
1041 static uint16_t s626_get_latch_source(struct comedi_device *dev,
1042                                       unsigned int chan)
1043 {
1044         return S626_GET_CRB_LATCHSRC(s626_debi_read(dev, S626_LP_CRB(chan)));
1045 }
1046 #endif
1047 
1048 /*
1049  * Return/set the event that will trigger transfer of the preload
1050  * register into the counter.  0=ThisCntr_Index, 1=ThisCntr_Overflow,
1051  * 2=OverflowA (B counters only), 3=disabled.
1052  */
1053 static void s626_set_load_trig(struct comedi_device *dev,
1054                                unsigned int chan, uint16_t trig)
1055 {
1056         uint16_t reg;
1057         uint16_t mask;
1058         uint16_t set;
1059 
1060         if (chan < 3) {
1061                 reg = S626_LP_CRA(chan);
1062                 mask = S626_CRAMSK_LOADSRC_A;
1063                 set = S626_SET_CRA_LOADSRC_A(trig);
1064         } else {
1065                 reg = S626_LP_CRB(chan);
1066                 mask = S626_CRBMSK_LOADSRC_B | S626_CRBMSK_INTCTRL;
1067                 set = S626_SET_CRB_LOADSRC_B(trig);
1068         }
1069         s626_debi_replace(dev, reg, ~mask, set);
1070 }
1071 
1072 #ifdef unused
1073 static uint16_t s626_get_load_trig(struct comedi_device *dev,
1074                                    unsigned int chan)
1075 {
1076         if (chan < 3)
1077                 return S626_GET_CRA_LOADSRC_A(s626_debi_read(dev,
1078                                                         S626_LP_CRA(chan)));
1079         else
1080                 return S626_GET_CRB_LOADSRC_B(s626_debi_read(dev,
1081                                                         S626_LP_CRB(chan)));
1082 }
1083 #endif
1084 
1085 /*
1086  * Return/set counter interrupt source and clear any captured
1087  * index/overflow events.  int_source: 0=Disabled, 1=OverflowOnly,
1088  * 2=IndexOnly, 3=IndexAndOverflow.
1089  */
1090 static void s626_set_int_src(struct comedi_device *dev,
1091                              unsigned int chan, uint16_t int_source)
1092 {
1093         struct s626_private *devpriv = dev->private;
1094         uint16_t cra_reg = S626_LP_CRA(chan);
1095         uint16_t crb_reg = S626_LP_CRB(chan);
1096 
1097         if (chan < 3) {
1098                 /* Reset any pending counter overflow or index captures */
1099                 s626_debi_replace(dev, crb_reg, ~S626_CRBMSK_INTCTRL,
1100                                   S626_SET_CRB_INTRESETCMD(1) |
1101                                   S626_SET_CRB_INTRESET_A(1));
1102 
1103                 /* Program counter interrupt source */
1104                 s626_debi_replace(dev, cra_reg, ~S626_CRAMSK_INTSRC_A,
1105                                   S626_SET_CRA_INTSRC_A(int_source));
1106         } else {
1107                 uint16_t crb;
1108 
1109                 /* Cache writeable CRB register image */
1110                 crb = s626_debi_read(dev, crb_reg);
1111                 crb &= ~S626_CRBMSK_INTCTRL;
1112 
1113                 /* Reset any pending counter overflow or index captures */
1114                 s626_debi_write(dev, crb_reg,
1115                                 crb | S626_SET_CRB_INTRESETCMD(1) |
1116                                 S626_SET_CRB_INTRESET_B(1));
1117 
1118                 /* Program counter interrupt source */
1119                 s626_debi_write(dev, crb_reg,
1120                                 (crb & ~S626_CRBMSK_INTSRC_B) |
1121                                 S626_SET_CRB_INTSRC_B(int_source));
1122         }
1123 
1124         /* Update MISC2 interrupt enable mask. */
1125         devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
1126                                         S626_INDXMASK(chan));
1127         switch (int_source) {
1128         case 0:
1129         default:
1130                 break;
1131         case 1:
1132                 devpriv->counter_int_enabs |= S626_OVERMASK(chan);
1133                 break;
1134         case 2:
1135                 devpriv->counter_int_enabs |= S626_INDXMASK(chan);
1136                 break;
1137         case 3:
1138                 devpriv->counter_int_enabs |= (S626_OVERMASK(chan) |
1139                                                S626_INDXMASK(chan));
1140                 break;
1141         }
1142 }
1143 
1144 #ifdef unused
1145 static uint16_t s626_get_int_src(struct comedi_device *dev,
1146                                  unsigned int chan)
1147 {
1148         if (chan < 3)
1149                 return S626_GET_CRA_INTSRC_A(s626_debi_read(dev,
1150                                                         S626_LP_CRA(chan)));
1151         else
1152                 return S626_GET_CRB_INTSRC_B(s626_debi_read(dev,
1153                                                         S626_LP_CRB(chan)));
1154 }
1155 #endif
1156 
1157 #ifdef unused
1158 /*
1159  * Return/set the clock multiplier.
1160  */
1161 static void s626_set_clk_mult(struct comedi_device *dev,
1162                               unsigned int chan, uint16_t value)
1163 {
1164         uint16_t mode;
1165 
1166         mode = s626_get_mode(dev, chan);
1167         mode &= ~S626_STDMSK_CLKMULT;
1168         mode |= S626_SET_STD_CLKMULT(value);
1169 
1170         s626_set_mode(dev, chan, mode, false);
1171 }
1172 
1173 static uint16_t s626_get_clk_mult(struct comedi_device *dev,
1174                                   unsigned int chan)
1175 {
1176         return S626_GET_STD_CLKMULT(s626_get_mode(dev, chan));
1177 }
1178 
1179 /*
1180  * Return/set the clock polarity.
1181  */
1182 static void s626_set_clk_pol(struct comedi_device *dev,
1183                              unsigned int chan, uint16_t value)
1184 {
1185         uint16_t mode;
1186 
1187         mode = s626_get_mode(dev, chan);
1188         mode &= ~S626_STDMSK_CLKPOL;
1189         mode |= S626_SET_STD_CLKPOL(value);
1190 
1191         s626_set_mode(dev, chan, mode, false);
1192 }
1193 
1194 static uint16_t s626_get_clk_pol(struct comedi_device *dev,
1195                                  unsigned int chan)
1196 {
1197         return S626_GET_STD_CLKPOL(s626_get_mode(dev, chan));
1198 }
1199 
1200 /*
1201  * Return/set the encoder mode.
1202  */
1203 static void s626_set_enc_mode(struct comedi_device *dev,
1204                               unsigned int chan, uint16_t value)
1205 {
1206         uint16_t mode;
1207 
1208         mode = s626_get_mode(dev, chan);
1209         mode &= ~S626_STDMSK_ENCMODE;
1210         mode |= S626_SET_STD_ENCMODE(value);
1211 
1212         s626_set_mode(dev, chan, mode, false);
1213 }
1214 
1215 static uint16_t s626_get_enc_mode(struct comedi_device *dev,
1216                                   unsigned int chan)
1217 {
1218         return S626_GET_STD_ENCMODE(s626_get_mode(dev, chan));
1219 }
1220 
1221 /*
1222  * Return/set the index polarity.
1223  */
1224 static void s626_set_index_pol(struct comedi_device *dev,
1225                                unsigned int chan, uint16_t value)
1226 {
1227         uint16_t mode;
1228 
1229         mode = s626_get_mode(dev, chan);
1230         mode &= ~S626_STDMSK_INDXPOL;
1231         mode |= S626_SET_STD_INDXPOL(value != 0);
1232 
1233         s626_set_mode(dev, chan, mode, false);
1234 }
1235 
1236 static uint16_t s626_get_index_pol(struct comedi_device *dev,
1237                                    unsigned int chan)
1238 {
1239         return S626_GET_STD_INDXPOL(s626_get_mode(dev, chan));
1240 }
1241 
1242 /*
1243  * Return/set the index source.
1244  */
1245 static void s626_set_index_src(struct comedi_device *dev,
1246                                unsigned int chan, uint16_t value)
1247 {
1248         uint16_t mode;
1249 
1250         mode = s626_get_mode(dev, chan);
1251         mode &= ~S626_STDMSK_INDXSRC;
1252         mode |= S626_SET_STD_INDXSRC(value != 0);
1253 
1254         s626_set_mode(dev, chan, mode, false);
1255 }
1256 
1257 static uint16_t s626_get_index_src(struct comedi_device *dev,
1258                                    unsigned int chan)
1259 {
1260         return S626_GET_STD_INDXSRC(s626_get_mode(dev, chan));
1261 }
1262 #endif
1263 
1264 /*
1265  * Generate an index pulse.
1266  */
1267 static void s626_pulse_index(struct comedi_device *dev,
1268                              unsigned int chan)
1269 {
1270         if (chan < 3) {
1271                 uint16_t cra;
1272 
1273                 cra = s626_debi_read(dev, S626_LP_CRA(chan));
1274 
1275                 /* Pulse index */
1276                 s626_debi_write(dev, S626_LP_CRA(chan),
1277                                 (cra ^ S626_CRAMSK_INDXPOL_A));
1278                 s626_debi_write(dev, S626_LP_CRA(chan), cra);
1279         } else {
1280                 uint16_t crb;
1281 
1282                 crb = s626_debi_read(dev, S626_LP_CRB(chan));
1283                 crb &= ~S626_CRBMSK_INTCTRL;
1284 
1285                 /* Pulse index */
1286                 s626_debi_write(dev, S626_LP_CRB(chan),
1287                                 (crb ^ S626_CRBMSK_INDXPOL_B));
1288                 s626_debi_write(dev, S626_LP_CRB(chan), crb);
1289         }
1290 }
1291 
1292 static unsigned int s626_ai_reg_to_uint(unsigned int data)
1293 {
1294         return ((data >> 18) & 0x3fff) ^ 0x2000;
1295 }
1296 
1297 static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
1298 {
1299         unsigned int group = chan / 16;
1300         unsigned int mask = 1 << (chan - (16 * group));
1301         unsigned int status;
1302 
1303         /* set channel to capture positive edge */
1304         status = s626_debi_read(dev, S626_LP_RDEDGSEL(group));
1305         s626_debi_write(dev, S626_LP_WREDGSEL(group), mask | status);
1306 
1307         /* enable interrupt on selected channel */
1308         status = s626_debi_read(dev, S626_LP_RDINTSEL(group));
1309         s626_debi_write(dev, S626_LP_WRINTSEL(group), mask | status);
1310 
1311         /* enable edge capture write command */
1312         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_EDCAP);
1313 
1314         /* enable edge capture on selected channel */
1315         status = s626_debi_read(dev, S626_LP_RDCAPSEL(group));
1316         s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask | status);
1317 
1318         return 0;
1319 }
1320 
1321 static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
1322                               unsigned int mask)
1323 {
1324         /* disable edge capture write command */
1325         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1326 
1327         /* enable edge capture on selected channel */
1328         s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask);
1329 
1330         return 0;
1331 }
1332 
1333 static int s626_dio_clear_irq(struct comedi_device *dev)
1334 {
1335         unsigned int group;
1336 
1337         /* disable edge capture write command */
1338         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1339 
1340         /* clear all dio pending events and interrupt */
1341         for (group = 0; group < S626_DIO_BANKS; group++)
1342                 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
1343 
1344         return 0;
1345 }
1346 
1347 static void s626_handle_dio_interrupt(struct comedi_device *dev,
1348                                       uint16_t irqbit, uint8_t group)
1349 {
1350         struct s626_private *devpriv = dev->private;
1351         struct comedi_subdevice *s = dev->read_subdev;
1352         struct comedi_cmd *cmd = &s->async->cmd;
1353 
1354         s626_dio_reset_irq(dev, group, irqbit);
1355 
1356         if (devpriv->ai_cmd_running) {
1357                 /* check if interrupt is an ai acquisition start trigger */
1358                 if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 &&
1359                     cmd->start_src == TRIG_EXT) {
1360                         /* Start executing the RPS program */
1361                         s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1362 
1363                         if (cmd->scan_begin_src == TRIG_EXT)
1364                                 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1365                 }
1366                 if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 &&
1367                     cmd->scan_begin_src == TRIG_EXT) {
1368                         /* Trigger ADC scan loop start */
1369                         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1370 
1371                         if (cmd->convert_src == TRIG_EXT) {
1372                                 devpriv->ai_convert_count = cmd->chanlist_len;
1373 
1374                                 s626_dio_set_irq(dev, cmd->convert_arg);
1375                         }
1376 
1377                         if (cmd->convert_src == TRIG_TIMER) {
1378                                 devpriv->ai_convert_count = cmd->chanlist_len;
1379                                 s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS);
1380                         }
1381                 }
1382                 if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 &&
1383                     cmd->convert_src == TRIG_EXT) {
1384                         /* Trigger ADC scan loop start */
1385                         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1386 
1387                         devpriv->ai_convert_count--;
1388                         if (devpriv->ai_convert_count > 0)
1389                                 s626_dio_set_irq(dev, cmd->convert_arg);
1390                 }
1391         }
1392 }
1393 
1394 static void s626_check_dio_interrupts(struct comedi_device *dev)
1395 {
1396         uint16_t irqbit;
1397         uint8_t group;
1398 
1399         for (group = 0; group < S626_DIO_BANKS; group++) {
1400                 /* read interrupt type */
1401                 irqbit = s626_debi_read(dev, S626_LP_RDCAPFLG(group));
1402 
1403                 /* check if interrupt is generated from dio channels */
1404                 if (irqbit) {
1405                         s626_handle_dio_interrupt(dev, irqbit, group);
1406                         return;
1407                 }
1408         }
1409 }
1410 
1411 static void s626_check_counter_interrupts(struct comedi_device *dev)
1412 {
1413         struct s626_private *devpriv = dev->private;
1414         struct comedi_subdevice *s = dev->read_subdev;
1415         struct comedi_async *async = s->async;
1416         struct comedi_cmd *cmd = &async->cmd;
1417         uint16_t irqbit;
1418 
1419         /* read interrupt type */
1420         irqbit = s626_debi_read(dev, S626_LP_RDMISC2);
1421 
1422         /* check interrupt on counters */
1423         if (irqbit & S626_IRQ_COINT1A) {
1424                 /* clear interrupt capture flag */
1425                 s626_reset_cap_flags(dev, 0);
1426         }
1427         if (irqbit & S626_IRQ_COINT2A) {
1428                 /* clear interrupt capture flag */
1429                 s626_reset_cap_flags(dev, 1);
1430         }
1431         if (irqbit & S626_IRQ_COINT3A) {
1432                 /* clear interrupt capture flag */
1433                 s626_reset_cap_flags(dev, 2);
1434         }
1435         if (irqbit & S626_IRQ_COINT1B) {
1436                 /* clear interrupt capture flag */
1437                 s626_reset_cap_flags(dev, 3);
1438         }
1439         if (irqbit & S626_IRQ_COINT2B) {
1440                 /* clear interrupt capture flag */
1441                 s626_reset_cap_flags(dev, 4);
1442 
1443                 if (devpriv->ai_convert_count > 0) {
1444                         devpriv->ai_convert_count--;
1445                         if (devpriv->ai_convert_count == 0)
1446                                 s626_set_enable(dev, 4, S626_CLKENAB_INDEX);
1447 
1448                         if (cmd->convert_src == TRIG_TIMER) {
1449                                 /* Trigger ADC scan loop start */
1450                                 s626_mc_enable(dev, S626_MC2_ADC_RPS,
1451                                                S626_P_MC2);
1452                         }
1453                 }
1454         }
1455         if (irqbit & S626_IRQ_COINT3B) {
1456                 /* clear interrupt capture flag */
1457                 s626_reset_cap_flags(dev, 5);
1458 
1459                 if (cmd->scan_begin_src == TRIG_TIMER) {
1460                         /* Trigger ADC scan loop start */
1461                         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1462                 }
1463 
1464                 if (cmd->convert_src == TRIG_TIMER) {
1465                         devpriv->ai_convert_count = cmd->chanlist_len;
1466                         s626_set_enable(dev, 4, S626_CLKENAB_ALWAYS);
1467                 }
1468         }
1469 }
1470 
1471 static bool s626_handle_eos_interrupt(struct comedi_device *dev)
1472 {
1473         struct s626_private *devpriv = dev->private;
1474         struct comedi_subdevice *s = dev->read_subdev;
1475         struct comedi_async *async = s->async;
1476         struct comedi_cmd *cmd = &async->cmd;
1477         /*
1478          * Init ptr to DMA buffer that holds new ADC data.  We skip the
1479          * first uint16_t in the buffer because it contains junk data
1480          * from the final ADC of the previous poll list scan.
1481          */
1482         uint32_t *readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1483         bool finished = false;
1484         int i;
1485 
1486         /* get the data and hand it over to comedi */
1487         for (i = 0; i < cmd->chanlist_len; i++) {
1488                 unsigned short tempdata;
1489 
1490                 /*
1491                  * Convert ADC data to 16-bit integer values and copy
1492                  * to application buffer.
1493                  */
1494                 tempdata = s626_ai_reg_to_uint(*readaddr);
1495                 readaddr++;
1496 
1497                 /* put data into read buffer */
1498                 cfc_write_to_buffer(s, tempdata);
1499         }
1500 
1501         /* end of scan occurs */
1502         async->events |= COMEDI_CB_EOS;
1503 
1504         if (cmd->stop_src == TRIG_COUNT) {
1505                 devpriv->ai_sample_count--;
1506                 if (devpriv->ai_sample_count <= 0) {
1507                         devpriv->ai_cmd_running = 0;
1508 
1509                         /* Stop RPS program */
1510                         s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1511 
1512                         /* send end of acquisition */
1513                         async->events |= COMEDI_CB_EOA;
1514 
1515                         /* disable master interrupt */
1516                         finished = true;
1517                 }
1518         }
1519 
1520         if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT)
1521                 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1522 
1523         /* tell comedi that data is there */
1524         comedi_event(dev, s);
1525 
1526         return finished;
1527 }
1528 
1529 static irqreturn_t s626_irq_handler(int irq, void *d)
1530 {
1531         struct comedi_device *dev = d;
1532         unsigned long flags;
1533         uint32_t irqtype, irqstatus;
1534 
1535         if (!dev->attached)
1536                 return IRQ_NONE;
1537         /* lock to avoid race with comedi_poll */
1538         spin_lock_irqsave(&dev->spinlock, flags);
1539 
1540         /* save interrupt enable register state */
1541         irqstatus = readl(dev->mmio + S626_P_IER);
1542 
1543         /* read interrupt type */
1544         irqtype = readl(dev->mmio + S626_P_ISR);
1545 
1546         /* disable master interrupt */
1547         writel(0, dev->mmio + S626_P_IER);
1548 
1549         /* clear interrupt */
1550         writel(irqtype, dev->mmio + S626_P_ISR);
1551 
1552         switch (irqtype) {
1553         case S626_IRQ_RPS1:     /* end_of_scan occurs */
1554                 if (s626_handle_eos_interrupt(dev))
1555                         irqstatus = 0;
1556                 break;
1557         case S626_IRQ_GPIO3:    /* check dio and counter interrupt */
1558                 /* s626_dio_clear_irq(dev); */
1559                 s626_check_dio_interrupts(dev);
1560                 s626_check_counter_interrupts(dev);
1561                 break;
1562         }
1563 
1564         /* enable interrupt */
1565         writel(irqstatus, dev->mmio + S626_P_IER);
1566 
1567         spin_unlock_irqrestore(&dev->spinlock, flags);
1568         return IRQ_HANDLED;
1569 }
1570 
1571 /*
1572  * This function builds the RPS program for hardware driven acquisition.
1573  */
1574 static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl)
1575 {
1576         struct s626_private *devpriv = dev->private;
1577         struct comedi_subdevice *s = dev->read_subdev;
1578         struct comedi_cmd *cmd = &s->async->cmd;
1579         uint32_t *rps;
1580         uint32_t jmp_adrs;
1581         uint16_t i;
1582         uint16_t n;
1583         uint32_t local_ppl;
1584 
1585         /* Stop RPS program in case it is currently running */
1586         s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1587 
1588         /* Set starting logical address to write RPS commands. */
1589         rps = (uint32_t *)devpriv->rps_buf.logical_base;
1590 
1591         /* Initialize RPS instruction pointer */
1592         writel((uint32_t)devpriv->rps_buf.physical_base,
1593                dev->mmio + S626_P_RPSADDR1);
1594 
1595         /* Construct RPS program in rps_buf DMA buffer */
1596         if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
1597                 /* Wait for Start trigger. */
1598                 *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1599                 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1600         }
1601 
1602         /*
1603          * SAA7146 BUG WORKAROUND Do a dummy DEBI Write.  This is necessary
1604          * because the first RPS DEBI Write following a non-RPS DEBI write
1605          * seems to always fail.  If we don't do this dummy write, the ADC
1606          * gain might not be set to the value required for the first slot in
1607          * the poll list; the ADC gain would instead remain unchanged from
1608          * the previously programmed value.
1609          */
1610         /* Write DEBI Write command and address to shadow RAM. */
1611         *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1612         *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1613         *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1614         /* Write DEBI immediate data  to shadow RAM: */
1615         *rps++ = S626_GSEL_BIPOLAR5V;   /* arbitrary immediate data  value. */
1616         *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1617         /* Reset "shadow RAM  uploaded" flag. */
1618         /* Invoke shadow RAM upload. */
1619         *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1620         /* Wait for shadow upload to finish. */
1621         *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1622 
1623         /*
1624          * Digitize all slots in the poll list. This is implemented as a
1625          * for loop to limit the slot count to 16 in case the application
1626          * forgot to set the S626_EOPL flag in the final slot.
1627          */
1628         for (devpriv->adc_items = 0; devpriv->adc_items < 16;
1629              devpriv->adc_items++) {
1630                 /*
1631                  * Convert application's poll list item to private board class
1632                  * format.  Each app poll list item is an uint8_t with form
1633                  * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
1634                  * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
1635                  */
1636                 local_ppl = (*ppl << 8) | (*ppl & 0x10 ? S626_GSEL_BIPOLAR5V :
1637                                            S626_GSEL_BIPOLAR10V);
1638 
1639                 /* Switch ADC analog gain. */
1640                 /* Write DEBI command and address to shadow RAM. */
1641                 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1642                 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1643                 /* Write DEBI immediate data to shadow RAM. */
1644                 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1645                 *rps++ = local_ppl;
1646                 /* Reset "shadow RAM uploaded" flag. */
1647                 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1648                 /* Invoke shadow RAM upload. */
1649                 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1650                 /* Wait for shadow upload to finish. */
1651                 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1652                 /* Select ADC analog input channel. */
1653                 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1654                 /* Write DEBI command and address to shadow RAM. */
1655                 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_ISEL;
1656                 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1657                 /* Write DEBI immediate data to shadow RAM. */
1658                 *rps++ = local_ppl;
1659                 /* Reset "shadow RAM uploaded" flag. */
1660                 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1661                 /* Invoke shadow RAM upload. */
1662                 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1663                 /* Wait for shadow upload to finish. */
1664                 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1665 
1666                 /*
1667                  * Delay at least 10 microseconds for analog input settling.
1668                  * Instead of padding with NOPs, we use S626_RPS_JUMP
1669                  * instructions here; this allows us to produce a longer delay
1670                  * than is possible with NOPs because each S626_RPS_JUMP
1671                  * flushes the RPS' instruction prefetch pipeline.
1672                  */
1673                 jmp_adrs =
1674                         (uint32_t)devpriv->rps_buf.physical_base +
1675                         (uint32_t)((unsigned long)rps -
1676                                    (unsigned long)devpriv->
1677                                                   rps_buf.logical_base);
1678                 for (i = 0; i < (10 * S626_RPSCLK_PER_US / 2); i++) {
1679                         jmp_adrs += 8;  /* Repeat to implement time delay: */
1680                         /* Jump to next RPS instruction. */
1681                         *rps++ = S626_RPS_JUMP;
1682                         *rps++ = jmp_adrs;
1683                 }
1684 
1685                 if (cmd != NULL && cmd->convert_src != TRIG_NOW) {
1686                         /* Wait for Start trigger. */
1687                         *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1688                         *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1689                 }
1690                 /* Start ADC by pulsing GPIO1. */
1691                 /* Begin ADC Start pulse. */
1692                 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1693                 *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1694                 *rps++ = S626_RPS_NOP;
1695                 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1696                 /* End ADC Start pulse. */
1697                 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1698                 *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1699                 /*
1700                  * Wait for ADC to complete (GPIO2 is asserted high when ADC not
1701                  * busy) and for data from previous conversion to shift into FB
1702                  * BUFFER 1 register.
1703                  */
1704                 /* Wait for ADC done. */
1705                 *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;
1706 
1707                 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
1708                 *rps++ = S626_RPS_STREG |
1709                          (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1710                 *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1711                          (devpriv->adc_items << 2);
1712 
1713                 /*
1714                  * If this slot's EndOfPollList flag is set, all channels have
1715                  * now been processed.
1716                  */
1717                 if (*ppl++ & S626_EOPL) {
1718                         devpriv->adc_items++; /* Adjust poll list item count. */
1719                         break;  /* Exit poll list processing loop. */
1720                 }
1721         }
1722 
1723         /*
1724          * VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US.  Allow the
1725          * ADC to stabilize for 2 microseconds before starting the final
1726          * (dummy) conversion.  This delay is necessary to allow sufficient
1727          * time between last conversion finished and the start of the dummy
1728          * conversion.  Without this delay, the last conversion's data value
1729          * is sometimes set to the previous conversion's data value.
1730          */
1731         for (n = 0; n < (2 * S626_RPSCLK_PER_US); n++)
1732                 *rps++ = S626_RPS_NOP;
1733 
1734         /*
1735          * Start a dummy conversion to cause the data from the last
1736          * conversion of interest to be shifted in.
1737          */
1738         /* Begin ADC Start pulse. */
1739         *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1740         *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1741         *rps++ = S626_RPS_NOP;
1742         /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1743         *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); /* End ADC Start pulse. */
1744         *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1745 
1746         /*
1747          * Wait for the data from the last conversion of interest to arrive
1748          * in FB BUFFER 1 register.
1749          */
1750         *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;       /* Wait for ADC done. */
1751 
1752         /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1753         *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1754         *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1755                  (devpriv->adc_items << 2);
1756 
1757         /* Indicate ADC scan loop is finished. */
1758         /* Signal ReadADC() that scan is done. */
1759         /* *rps++= S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; */
1760 
1761         /* invoke interrupt */
1762         if (devpriv->ai_cmd_running == 1)
1763                 *rps++ = S626_RPS_IRQ;
1764 
1765         /* Restart RPS program at its beginning. */
1766         *rps++ = S626_RPS_JUMP; /* Branch to start of RPS program. */
1767         *rps++ = (uint32_t)devpriv->rps_buf.physical_base;
1768 
1769         /* End of RPS program build */
1770 }
1771 
1772 #ifdef unused_code
1773 static int s626_ai_rinsn(struct comedi_device *dev,
1774                          struct comedi_subdevice *s,
1775                          struct comedi_insn *insn,
1776                          unsigned int *data)
1777 {
1778         struct s626_private *devpriv = dev->private;
1779         uint8_t i;
1780         int32_t *readaddr;
1781 
1782         /* Trigger ADC scan loop start */
1783         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1784 
1785         /* Wait until ADC scan loop is finished (RPS Signal 0 reset) */
1786         while (s626_mc_test(dev, S626_MC2_ADC_RPS, S626_P_MC2))
1787                 ;
1788 
1789         /*
1790          * Init ptr to DMA buffer that holds new ADC data.  We skip the
1791          * first uint16_t in the buffer because it contains junk data from
1792          * the final ADC of the previous poll list scan.
1793          */
1794         readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1795 
1796         /*
1797          * Convert ADC data to 16-bit integer values and
1798          * copy to application buffer.
1799          */
1800         for (i = 0; i < devpriv->adc_items; i++) {
1801                 *data = s626_ai_reg_to_uint(*readaddr++);
1802                 data++;
1803         }
1804 
1805         return i;
1806 }
1807 #endif
1808 
1809 static int s626_ai_eoc(struct comedi_device *dev,
1810                        struct comedi_subdevice *s,
1811                        struct comedi_insn *insn,
1812                        unsigned long context)
1813 {
1814         unsigned int status;
1815 
1816         status = readl(dev->mmio + S626_P_PSR);
1817         if (status & S626_PSR_GPIO2)
1818                 return 0;
1819         return -EBUSY;
1820 }
1821 
1822 static int s626_ai_insn_read(struct comedi_device *dev,
1823                              struct comedi_subdevice *s,
1824                              struct comedi_insn *insn,
1825                              unsigned int *data)
1826 {
1827         uint16_t chan = CR_CHAN(insn->chanspec);
1828         uint16_t range = CR_RANGE(insn->chanspec);
1829         uint16_t adc_spec = 0;
1830         uint32_t gpio_image;
1831         uint32_t tmp;
1832         int ret;
1833         int n;
1834 
1835         /*
1836          * Convert application's ADC specification into form
1837          *  appropriate for register programming.
1838          */
1839         if (range == 0)
1840                 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR5V);
1841         else
1842                 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR10V);
1843 
1844         /* Switch ADC analog gain. */
1845         s626_debi_write(dev, S626_LP_GSEL, adc_spec);   /* Set gain. */
1846 
1847         /* Select ADC analog input channel. */
1848         s626_debi_write(dev, S626_LP_ISEL, adc_spec);   /* Select channel. */
1849 
1850         for (n = 0; n < insn->n; n++) {
1851                 /* Delay 10 microseconds for analog input settling. */
1852                 udelay(10);
1853 
1854                 /* Start ADC by pulsing GPIO1 low */
1855                 gpio_image = readl(dev->mmio + S626_P_GPIO);
1856                 /* Assert ADC Start command */
1857                 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1858                 /* and stretch it out */
1859                 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1860                 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1861                 /* Negate ADC Start command */
1862                 writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1863 
1864                 /*
1865                  * Wait for ADC to complete (GPIO2 is asserted high when
1866                  * ADC not busy) and for data from previous conversion to
1867                  * shift into FB BUFFER 1 register.
1868                  */
1869 
1870                 /* Wait for ADC done */
1871                 ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
1872                 if (ret)
1873                         return ret;
1874 
1875                 /* Fetch ADC data */
1876                 if (n != 0) {
1877                         tmp = readl(dev->mmio + S626_P_FB_BUFFER1);
1878                         data[n - 1] = s626_ai_reg_to_uint(tmp);
1879                 }
1880 
1881                 /*
1882                  * Allow the ADC to stabilize for 4 microseconds before
1883                  * starting the next (final) conversion.  This delay is
1884                  * necessary to allow sufficient time between last
1885                  * conversion finished and the start of the next
1886                  * conversion.  Without this delay, the last conversion's
1887                  * data value is sometimes set to the previous
1888                  * conversion's data value.
1889                  */
1890                 udelay(4);
1891         }
1892 
1893         /*
1894          * Start a dummy conversion to cause the data from the
1895          * previous conversion to be shifted in.
1896          */
1897         gpio_image = readl(dev->mmio + S626_P_GPIO);
1898         /* Assert ADC Start command */
1899         writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1900         /* and stretch it out */
1901         writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1902         writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1903         /* Negate ADC Start command */
1904         writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1905 
1906         /* Wait for the data to arrive in FB BUFFER 1 register. */
1907 
1908         /* Wait for ADC done */
1909         ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
1910         if (ret)
1911                 return ret;
1912 
1913         /* Fetch ADC data from audio interface's input shift register. */
1914 
1915         /* Fetch ADC data */
1916         if (n != 0) {
1917                 tmp = readl(dev->mmio + S626_P_FB_BUFFER1);
1918                 data[n - 1] = s626_ai_reg_to_uint(tmp);
1919         }
1920 
1921         return n;
1922 }
1923 
1924 static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd)
1925 {
1926         int n;
1927 
1928         for (n = 0; n < cmd->chanlist_len; n++) {
1929                 if (CR_RANGE(cmd->chanlist[n]) == 0)
1930                         ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_5V;
1931                 else
1932                         ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_10V;
1933         }
1934         if (n != 0)
1935                 ppl[n - 1] |= S626_EOPL;
1936 
1937         return n;
1938 }
1939 
1940 static int s626_ai_inttrig(struct comedi_device *dev,
1941                            struct comedi_subdevice *s,
1942                            unsigned int trig_num)
1943 {
1944         struct comedi_cmd *cmd = &s->async->cmd;
1945 
1946         if (trig_num != cmd->start_arg)
1947                 return -EINVAL;
1948 
1949         /* Start executing the RPS program */
1950         s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1951 
1952         s->async->inttrig = NULL;
1953 
1954         return 1;
1955 }
1956 
1957 /*
1958  * This function doesn't require a particular form, this is just what
1959  * happens to be used in some of the drivers.  It should convert ns
1960  * nanoseconds to a counter value suitable for programming the device.
1961  * Also, it should adjust ns so that it cooresponds to the actual time
1962  * that the device will use.
1963  */
1964 static int s626_ns_to_timer(unsigned int *nanosec, unsigned int flags)
1965 {
1966         int divider, base;
1967 
1968         base = 500;             /* 2MHz internal clock */
1969 
1970         switch (flags & CMDF_ROUND_MASK) {
1971         case CMDF_ROUND_NEAREST:
1972         default:
1973                 divider = (*nanosec + base / 2) / base;
1974                 break;
1975         case CMDF_ROUND_DOWN:
1976                 divider = (*nanosec) / base;
1977                 break;
1978         case CMDF_ROUND_UP:
1979                 divider = (*nanosec + base - 1) / base;
1980                 break;
1981         }
1982 
1983         *nanosec = base * divider;
1984         return divider - 1;
1985 }
1986 
1987 static void s626_timer_load(struct comedi_device *dev,
1988                             unsigned int chan, int tick)
1989 {
1990         uint16_t setup =
1991                 /* Preload upon index. */
1992                 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
1993                 /* Disable hardware index. */
1994                 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
1995                 /* Operating mode is Timer. */
1996                 S626_SET_STD_ENCMODE(S626_ENCMODE_TIMER) |
1997                 /* Count direction is Down. */
1998                 S626_SET_STD_CLKPOL(S626_CNTDIR_DOWN) |
1999                 /* Clock multiplier is 1x. */
2000                 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2001                 /* Enabled by index */
2002                 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2003         uint16_t value_latchsrc = S626_LATCHSRC_A_INDXA;
2004         /* uint16_t enab = S626_CLKENAB_ALWAYS; */
2005 
2006         s626_set_mode(dev, chan, setup, false);
2007 
2008         /* Set the preload register */
2009         s626_preload(dev, chan, tick);
2010 
2011         /*
2012          * Software index pulse forces the preload register to load
2013          * into the counter
2014          */
2015         s626_set_load_trig(dev, chan, 0);
2016         s626_pulse_index(dev, chan);
2017 
2018         /* set reload on counter overflow */
2019         s626_set_load_trig(dev, chan, 1);
2020 
2021         /* set interrupt on overflow */
2022         s626_set_int_src(dev, chan, S626_INTSRC_OVER);
2023 
2024         s626_set_latch_source(dev, chan, value_latchsrc);
2025         /* s626_set_enable(dev, chan, (uint16_t)(enab != 0)); */
2026 }
2027 
2028 /* TO COMPLETE  */
2029 static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2030 {
2031         struct s626_private *devpriv = dev->private;
2032         uint8_t ppl[16];
2033         struct comedi_cmd *cmd = &s->async->cmd;
2034         int tick;
2035 
2036         if (devpriv->ai_cmd_running) {
2037                 dev_err(dev->class_dev,
2038                         "s626_ai_cmd: Another ai_cmd is running\n");
2039                 return -EBUSY;
2040         }
2041         /* disable interrupt */
2042         writel(0, dev->mmio + S626_P_IER);
2043 
2044         /* clear interrupt request */
2045         writel(S626_IRQ_RPS1 | S626_IRQ_GPIO3, dev->mmio + S626_P_ISR);
2046 
2047         /* clear any pending interrupt */
2048         s626_dio_clear_irq(dev);
2049         /* s626_enc_clear_irq(dev); */
2050 
2051         /* reset ai_cmd_running flag */
2052         devpriv->ai_cmd_running = 0;
2053 
2054         /* test if cmd is valid */
2055         if (cmd == NULL)
2056                 return -EINVAL;
2057 
2058         s626_ai_load_polllist(ppl, cmd);
2059         devpriv->ai_cmd_running = 1;
2060         devpriv->ai_convert_count = 0;
2061 
2062         switch (cmd->scan_begin_src) {
2063         case TRIG_FOLLOW:
2064                 break;
2065         case TRIG_TIMER:
2066                 /*
2067                  * set a counter to generate adc trigger at scan_begin_arg
2068                  * interval
2069                  */
2070                 tick = s626_ns_to_timer(&cmd->scan_begin_arg, cmd->flags);
2071 
2072                 /* load timer value and enable interrupt */
2073                 s626_timer_load(dev, 5, tick);
2074                 s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS);
2075                 break;
2076         case TRIG_EXT:
2077                 /* set the digital line and interrupt for scan trigger */
2078                 if (cmd->start_src != TRIG_EXT)
2079                         s626_dio_set_irq(dev, cmd->scan_begin_arg);
2080                 break;
2081         }
2082 
2083         switch (cmd->convert_src) {
2084         case TRIG_NOW:
2085                 break;
2086         case TRIG_TIMER:
2087                 /*
2088                  * set a counter to generate adc trigger at convert_arg
2089                  * interval
2090                  */
2091                 tick = s626_ns_to_timer(&cmd->convert_arg, cmd->flags);
2092 
2093                 /* load timer value and enable interrupt */
2094                 s626_timer_load(dev, 4, tick);
2095                 s626_set_enable(dev, 4, S626_CLKENAB_INDEX);
2096                 break;
2097         case TRIG_EXT:
2098                 /* set the digital line and interrupt for convert trigger */
2099                 if (cmd->scan_begin_src != TRIG_EXT &&
2100                     cmd->start_src == TRIG_EXT)
2101                         s626_dio_set_irq(dev, cmd->convert_arg);
2102                 break;
2103         }
2104 
2105         devpriv->ai_sample_count = cmd->stop_arg;
2106 
2107         s626_reset_adc(dev, ppl);
2108 
2109         switch (cmd->start_src) {
2110         case TRIG_NOW:
2111                 /* Trigger ADC scan loop start */
2112                 /* s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); */
2113 
2114                 /* Start executing the RPS program */
2115                 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
2116                 s->async->inttrig = NULL;
2117                 break;
2118         case TRIG_EXT:
2119                 /* configure DIO channel for acquisition trigger */
2120                 s626_dio_set_irq(dev, cmd->start_arg);
2121                 s->async->inttrig = NULL;
2122                 break;
2123         case TRIG_INT:
2124                 s->async->inttrig = s626_ai_inttrig;
2125                 break;
2126         }
2127 
2128         /* enable interrupt */
2129         writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, dev->mmio + S626_P_IER);
2130 
2131         return 0;
2132 }
2133 
2134 static int s626_ai_cmdtest(struct comedi_device *dev,
2135                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
2136 {
2137         int err = 0;
2138         unsigned int arg;
2139 
2140         /* Step 1 : check if triggers are trivially valid */
2141 
2142         err |= cfc_check_trigger_src(&cmd->start_src,
2143                                      TRIG_NOW | TRIG_INT | TRIG_EXT);
2144         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2145                                      TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW);
2146         err |= cfc_check_trigger_src(&cmd->convert_src,
2147                                      TRIG_TIMER | TRIG_EXT | TRIG_NOW);
2148         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2149         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2150 
2151         if (err)
2152                 return 1;
2153 
2154         /* Step 2a : make sure trigger sources are unique */
2155 
2156         err |= cfc_check_trigger_is_unique(cmd->start_src);
2157         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2158         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2159         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2160 
2161         /* Step 2b : and mutually compatible */
2162 
2163         if (err)
2164                 return 2;
2165 
2166         /* Step 3: check if arguments are trivially valid */
2167 
2168         switch (cmd->start_src) {
2169         case TRIG_NOW:
2170         case TRIG_INT:
2171                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2172                 break;
2173         case TRIG_EXT:
2174                 err |= cfc_check_trigger_arg_max(&cmd->start_arg, 39);
2175                 break;
2176         }
2177 
2178         if (cmd->scan_begin_src == TRIG_EXT)
2179                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 39);
2180         if (cmd->convert_src == TRIG_EXT)
2181                 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 39);
2182 
2183 #define S626_MAX_SPEED  200000  /* in nanoseconds */
2184 #define S626_MIN_SPEED  2000000000      /* in nanoseconds */
2185 
2186         if (cmd->scan_begin_src == TRIG_TIMER) {
2187                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2188                                                  S626_MAX_SPEED);
2189                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2190                                                  S626_MIN_SPEED);
2191         } else {
2192                 /* external trigger */
2193                 /* should be level/edge, hi/lo specification here */
2194                 /* should specify multiple external triggers */
2195                 /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
2196         }
2197         if (cmd->convert_src == TRIG_TIMER) {
2198                 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2199                                                  S626_MAX_SPEED);
2200                 err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2201                                                  S626_MIN_SPEED);
2202         } else {
2203                 /* external trigger */
2204                 /* see above */
2205                 /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
2206         }
2207 
2208         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2209 
2210         if (cmd->stop_src == TRIG_COUNT)
2211                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2212         else    /* TRIG_NONE */
2213                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2214 
2215         if (err)
2216                 return 3;
2217 
2218         /* step 4: fix up any arguments */
2219 
2220         if (cmd->scan_begin_src == TRIG_TIMER) {
2221                 arg = cmd->scan_begin_arg;
2222                 s626_ns_to_timer(&arg, cmd->flags);
2223                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
2224         }
2225 
2226         if (cmd->convert_src == TRIG_TIMER) {
2227                 arg = cmd->convert_arg;
2228                 s626_ns_to_timer(&arg, cmd->flags);
2229                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, arg);
2230 
2231                 if (cmd->scan_begin_src == TRIG_TIMER) {
2232                         arg = cmd->convert_arg * cmd->scan_end_arg;
2233                         err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2234                                                          arg);
2235                 }
2236         }
2237 
2238         if (err)
2239                 return 4;
2240 
2241         return 0;
2242 }
2243 
2244 static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
2245 {
2246         struct s626_private *devpriv = dev->private;
2247 
2248         /* Stop RPS program in case it is currently running */
2249         s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
2250 
2251         /* disable master interrupt */
2252         writel(0, dev->mmio + S626_P_IER);
2253 
2254         devpriv->ai_cmd_running = 0;
2255 
2256         return 0;
2257 }
2258 
2259 static int s626_ao_insn_write(struct comedi_device *dev,
2260                               struct comedi_subdevice *s,
2261                               struct comedi_insn *insn,
2262                               unsigned int *data)
2263 {
2264         unsigned int chan = CR_CHAN(insn->chanspec);
2265         int i;
2266 
2267         for (i = 0; i < insn->n; i++) {
2268                 int16_t dacdata = (int16_t)data[i];
2269                 int ret;
2270 
2271                 dacdata -= (0x1fff);
2272 
2273                 ret = s626_set_dac(dev, chan, dacdata);
2274                 if (ret)
2275                         return ret;
2276 
2277                 s->readback[chan] = data[i];
2278         }
2279 
2280         return insn->n;
2281 }
2282 
2283 /* *************** DIGITAL I/O FUNCTIONS *************** */
2284 
2285 /*
2286  * All DIO functions address a group of DIO channels by means of
2287  * "group" argument.  group may be 0, 1 or 2, which correspond to DIO
2288  * ports A, B and C, respectively.
2289  */
2290 
2291 static void s626_dio_init(struct comedi_device *dev)
2292 {
2293         uint16_t group;
2294 
2295         /* Prepare to treat writes to WRCapSel as capture disables. */
2296         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
2297 
2298         /* For each group of sixteen channels ... */
2299         for (group = 0; group < S626_DIO_BANKS; group++) {
2300                 /* Disable all interrupts */
2301                 s626_debi_write(dev, S626_LP_WRINTSEL(group), 0);
2302                 /* Disable all event captures */
2303                 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
2304                 /* Init all DIOs to default edge polarity */
2305                 s626_debi_write(dev, S626_LP_WREDGSEL(group), 0);
2306                 /* Program all outputs to inactive state */
2307                 s626_debi_write(dev, S626_LP_WRDOUT(group), 0);
2308         }
2309 }
2310 
2311 static int s626_dio_insn_bits(struct comedi_device *dev,
2312                               struct comedi_subdevice *s,
2313                               struct comedi_insn *insn,
2314                               unsigned int *data)
2315 {
2316         unsigned long group = (unsigned long)s->private;
2317 
2318         if (comedi_dio_update_state(s, data))
2319                 s626_debi_write(dev, S626_LP_WRDOUT(group), s->state);
2320 
2321         data[1] = s626_debi_read(dev, S626_LP_RDDIN(group));
2322 
2323         return insn->n;
2324 }
2325 
2326 static int s626_dio_insn_config(struct comedi_device *dev,
2327                                 struct comedi_subdevice *s,
2328                                 struct comedi_insn *insn,
2329                                 unsigned int *data)
2330 {
2331         unsigned long group = (unsigned long)s->private;
2332         int ret;
2333 
2334         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
2335         if (ret)
2336                 return ret;
2337 
2338         s626_debi_write(dev, S626_LP_WRDOUT(group), s->io_bits);
2339 
2340         return insn->n;
2341 }
2342 
2343 /*
2344  * Now this function initializes the value of the counter (data[0])
2345  * and set the subdevice. To complete with trigger and interrupt
2346  * configuration.
2347  *
2348  * FIXME: data[0] is supposed to be an INSN_CONFIG_xxx constant indicating
2349  * what is being configured, but this function appears to be using data[0]
2350  * as a variable.
2351  */
2352 static int s626_enc_insn_config(struct comedi_device *dev,
2353                                 struct comedi_subdevice *s,
2354                                 struct comedi_insn *insn, unsigned int *data)
2355 {
2356         unsigned int chan = CR_CHAN(insn->chanspec);
2357         uint16_t setup =
2358                 /* Preload upon index. */
2359                 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2360                 /* Disable hardware index. */
2361                 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2362                 /* Operating mode is Counter. */
2363                 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2364                 /* Active high clock. */
2365                 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2366                 /* Clock multiplier is 1x. */
2367                 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2368                 /* Enabled by index */
2369                 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2370         /* uint16_t disable_int_src = true; */
2371         /* uint32_t Preloadvalue;              //Counter initial value */
2372         uint16_t value_latchsrc = S626_LATCHSRC_AB_READ;
2373         uint16_t enab = S626_CLKENAB_ALWAYS;
2374 
2375         /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
2376 
2377         s626_set_mode(dev, chan, setup, true);
2378         s626_preload(dev, chan, data[0]);
2379         s626_pulse_index(dev, chan);
2380         s626_set_latch_source(dev, chan, value_latchsrc);
2381         s626_set_enable(dev, chan, (enab != 0));
2382 
2383         return insn->n;
2384 }
2385 
2386 static int s626_enc_insn_read(struct comedi_device *dev,
2387                               struct comedi_subdevice *s,
2388                               struct comedi_insn *insn,
2389                               unsigned int *data)
2390 {
2391         unsigned int chan = CR_CHAN(insn->chanspec);
2392         uint16_t cntr_latch_reg = S626_LP_CNTR(chan);
2393         int i;
2394 
2395         for (i = 0; i < insn->n; i++) {
2396                 unsigned int val;
2397 
2398                 /*
2399                  * Read the counter's output latch LSW/MSW.
2400                  * Latches on LSW read.
2401                  */
2402                 val = s626_debi_read(dev, cntr_latch_reg);
2403                 val |= (s626_debi_read(dev, cntr_latch_reg + 2) << 16);
2404                 data[i] = val;
2405         }
2406 
2407         return insn->n;
2408 }
2409 
2410 static int s626_enc_insn_write(struct comedi_device *dev,
2411                                struct comedi_subdevice *s,
2412                                struct comedi_insn *insn, unsigned int *data)
2413 {
2414         unsigned int chan = CR_CHAN(insn->chanspec);
2415 
2416         /* Set the preload register */
2417         s626_preload(dev, chan, data[0]);
2418 
2419         /*
2420          * Software index pulse forces the preload register to load
2421          * into the counter
2422          */
2423         s626_set_load_trig(dev, chan, 0);
2424         s626_pulse_index(dev, chan);
2425         s626_set_load_trig(dev, chan, 2);
2426 
2427         return 1;
2428 }
2429 
2430 static void s626_write_misc2(struct comedi_device *dev, uint16_t new_image)
2431 {
2432         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WENABLE);
2433         s626_debi_write(dev, S626_LP_WRMISC2, new_image);
2434         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WDISABLE);
2435 }
2436 
2437 static void s626_counters_init(struct comedi_device *dev)
2438 {
2439         int chan;
2440         uint16_t setup =
2441                 /* Preload upon index. */
2442                 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2443                 /* Disable hardware index. */
2444                 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2445                 /* Operating mode is counter. */
2446                 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2447                 /* Active high clock. */
2448                 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2449                 /* Clock multiplier is 1x. */
2450                 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2451                 /* Enabled by index */
2452                 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2453 
2454         /*
2455          * Disable all counter interrupts and clear any captured counter events.
2456          */
2457         for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
2458                 s626_set_mode(dev, chan, setup, true);
2459                 s626_set_int_src(dev, chan, 0);
2460                 s626_reset_cap_flags(dev, chan);
2461                 s626_set_enable(dev, chan, S626_CLKENAB_ALWAYS);
2462         }
2463 }
2464 
2465 static int s626_allocate_dma_buffers(struct comedi_device *dev)
2466 {
2467         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2468         struct s626_private *devpriv = dev->private;
2469         void *addr;
2470         dma_addr_t appdma;
2471 
2472         addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2473         if (!addr)
2474                 return -ENOMEM;
2475         devpriv->ana_buf.logical_base = addr;
2476         devpriv->ana_buf.physical_base = appdma;
2477 
2478         addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2479         if (!addr)
2480                 return -ENOMEM;
2481         devpriv->rps_buf.logical_base = addr;
2482         devpriv->rps_buf.physical_base = appdma;
2483 
2484         return 0;
2485 }
2486 
2487 static void s626_free_dma_buffers(struct comedi_device *dev)
2488 {
2489         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2490         struct s626_private *devpriv = dev->private;
2491 
2492         if (!devpriv)
2493                 return;
2494 
2495         if (devpriv->rps_buf.logical_base)
2496                 pci_free_consistent(pcidev, S626_DMABUF_SIZE,
2497                                     devpriv->rps_buf.logical_base,
2498                                     devpriv->rps_buf.physical_base);
2499         if (devpriv->ana_buf.logical_base)
2500                 pci_free_consistent(pcidev, S626_DMABUF_SIZE,
2501                                     devpriv->ana_buf.logical_base,
2502                                     devpriv->ana_buf.physical_base);
2503 }
2504 
2505 static int s626_initialize(struct comedi_device *dev)
2506 {
2507         struct s626_private *devpriv = dev->private;
2508         dma_addr_t phys_buf;
2509         uint16_t chan;
2510         int i;
2511         int ret;
2512 
2513         /* Enable DEBI and audio pins, enable I2C interface */
2514         s626_mc_enable(dev, S626_MC1_DEBI | S626_MC1_AUDIO | S626_MC1_I2C,
2515                        S626_P_MC1);
2516 
2517         /*
2518          * Configure DEBI operating mode
2519          *
2520          *  Local bus is 16 bits wide
2521          *  Declare DEBI transfer timeout interval
2522          *  Set up byte lane steering
2523          *  Intel-compatible local bus (DEBI never times out)
2524          */
2525         writel(S626_DEBI_CFG_SLAVE16 |
2526                (S626_DEBI_TOUT << S626_DEBI_CFG_TOUT_BIT) | S626_DEBI_SWAP |
2527                S626_DEBI_CFG_INTEL, dev->mmio + S626_P_DEBICFG);
2528 
2529         /* Disable MMU paging */
2530         writel(S626_DEBI_PAGE_DISABLE, dev->mmio + S626_P_DEBIPAGE);
2531 
2532         /* Init GPIO so that ADC Start* is negated */
2533         writel(S626_GPIO_BASE | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
2534 
2535         /* I2C device address for onboard eeprom (revb) */
2536         devpriv->i2c_adrs = 0xA0;
2537 
2538         /*
2539          * Issue an I2C ABORT command to halt any I2C
2540          * operation in progress and reset BUSY flag.
2541          */
2542         writel(S626_I2C_CLKSEL | S626_I2C_ABORT,
2543                dev->mmio + S626_P_I2CSTAT);
2544         s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2545         ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
2546         if (ret)
2547                 return ret;
2548 
2549         /*
2550          * Per SAA7146 data sheet, write to STATUS
2551          * reg twice to reset all  I2C error flags.
2552          */
2553         for (i = 0; i < 2; i++) {
2554                 writel(S626_I2C_CLKSEL, dev->mmio + S626_P_I2CSTAT);
2555                 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2556                 ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
2557                 if (ret)
2558                         return ret;
2559         }
2560 
2561         /*
2562          * Init audio interface functional attributes: set DAC/ADC
2563          * serial clock rates, invert DAC serial clock so that
2564          * DAC data setup times are satisfied, enable DAC serial
2565          * clock out.
2566          */
2567         writel(S626_ACON2_INIT, dev->mmio + S626_P_ACON2);
2568 
2569         /*
2570          * Set up TSL1 slot list, which is used to control the
2571          * accumulation of ADC data: S626_RSD1 = shift data in on SD1.
2572          * S626_SIB_A1  = store data uint8_t at next available location
2573          * in FB BUFFER1 register.
2574          */
2575         writel(S626_RSD1 | S626_SIB_A1, dev->mmio + S626_P_TSL1);
2576         writel(S626_RSD1 | S626_SIB_A1 | S626_EOS,
2577                dev->mmio + S626_P_TSL1 + 4);
2578 
2579         /* Enable TSL1 slot list so that it executes all the time */
2580         writel(S626_ACON1_ADCSTART, dev->mmio + S626_P_ACON1);
2581 
2582         /*
2583          * Initialize RPS registers used for ADC
2584          */
2585 
2586         /* Physical start of RPS program */
2587         writel((uint32_t)devpriv->rps_buf.physical_base,
2588                dev->mmio + S626_P_RPSADDR1);
2589         /* RPS program performs no explicit mem writes */
2590         writel(0, dev->mmio + S626_P_RPSPAGE1);
2591         /* Disable RPS timeouts */
2592         writel(0, dev->mmio + S626_P_RPS1_TOUT);
2593 
2594 #if 0
2595         /*
2596          * SAA7146 BUG WORKAROUND
2597          *
2598          * Initialize SAA7146 ADC interface to a known state by
2599          * invoking ADCs until FB BUFFER 1 register shows that it
2600          * is correctly receiving ADC data. This is necessary
2601          * because the SAA7146 ADC interface does not start up in
2602          * a defined state after a PCI reset.
2603          */
2604         {
2605                 struct comedi_subdevice *s = dev->read_subdev;
2606                 uint8_t poll_list;
2607                 uint16_t adc_data;
2608                 uint16_t start_val;
2609                 uint16_t index;
2610                 unsigned int data[16];
2611 
2612                 /* Create a simple polling list for analog input channel 0 */
2613                 poll_list = S626_EOPL;
2614                 s626_reset_adc(dev, &poll_list);
2615 
2616                 /* Get initial ADC value */
2617                 s626_ai_rinsn(dev, s, NULL, data);
2618                 start_val = data[0];
2619 
2620                 /*
2621                  * VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED
2622                  * EXECUTION.
2623                  *
2624                  * Invoke ADCs until the new ADC value differs from the initial
2625                  * value or a timeout occurs.  The timeout protects against the
2626                  * possibility that the driver is restarting and the ADC data is
2627                  * a fixed value resulting from the applied ADC analog input
2628                  * being unusually quiet or at the rail.
2629                  */
2630                 for (index = 0; index < 500; index++) {
2631                         s626_ai_rinsn(dev, s, NULL, data);
2632                         adc_data = data[0];
2633                         if (adc_data != start_val)
2634                                 break;
2635                 }
2636         }
2637 #endif  /* SAA7146 BUG WORKAROUND */
2638 
2639         /*
2640          * Initialize the DAC interface
2641          */
2642 
2643         /*
2644          * Init Audio2's output DMAC attributes:
2645          *   burst length = 1 DWORD
2646          *   threshold = 1 DWORD.
2647          */
2648         writel(0, dev->mmio + S626_P_PCI_BT_A);
2649 
2650         /*
2651          * Init Audio2's output DMA physical addresses.  The protection
2652          * address is set to 1 DWORD past the base address so that a
2653          * single DWORD will be transferred each time a DMA transfer is
2654          * enabled.
2655          */
2656         phys_buf = devpriv->ana_buf.physical_base +
2657                    (S626_DAC_WDMABUF_OS * sizeof(uint32_t));
2658         writel((uint32_t)phys_buf, dev->mmio + S626_P_BASEA2_OUT);
2659         writel((uint32_t)(phys_buf + sizeof(uint32_t)),
2660                dev->mmio + S626_P_PROTA2_OUT);
2661 
2662         /*
2663          * Cache Audio2's output DMA buffer logical address.  This is
2664          * where DAC data is buffered for A2 output DMA transfers.
2665          */
2666         devpriv->dac_wbuf = (uint32_t *)devpriv->ana_buf.logical_base +
2667                             S626_DAC_WDMABUF_OS;
2668 
2669         /*
2670          * Audio2's output channels does not use paging.  The
2671          * protection violation handling bit is set so that the
2672          * DMAC will automatically halt and its PCI address pointer
2673          * will be reset when the protection address is reached.
2674          */
2675         writel(8, dev->mmio + S626_P_PAGEA2_OUT);
2676 
2677         /*
2678          * Initialize time slot list 2 (TSL2), which is used to control
2679          * the clock generation for and serialization of data to be sent
2680          * to the DAC devices.  Slot 0 is a NOP that is used to trap TSL
2681          * execution; this permits other slots to be safely modified
2682          * without first turning off the TSL sequencer (which is
2683          * apparently impossible to do).  Also, SD3 (which is driven by a
2684          * pull-up resistor) is shifted in and stored to the MSB of
2685          * FB_BUFFER2 to be used as evidence that the slot sequence has
2686          * not yet finished executing.
2687          */
2688 
2689         /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */
2690         writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2 | S626_EOS,
2691                dev->mmio + S626_VECTPORT(0));
2692 
2693         /*
2694          * Initialize slot 1, which is constant.  Slot 1 causes a
2695          * DWORD to be transferred from audio channel 2's output FIFO
2696          * to the FIFO's output buffer so that it can be serialized
2697          * and sent to the DAC during subsequent slots.  All remaining
2698          * slots are dynamically populated as required by the target
2699          * DAC device.
2700          */
2701 
2702         /* Slot 1: Fetch DWORD from Audio2's output FIFO */
2703         writel(S626_LF_A2, dev->mmio + S626_VECTPORT(1));
2704 
2705         /* Start DAC's audio interface (TSL2) running */
2706         writel(S626_ACON1_DACSTART, dev->mmio + S626_P_ACON1);
2707 
2708         /*
2709          * Init Trim DACs to calibrated values.  Do it twice because the
2710          * SAA7146 audio channel does not always reset properly and
2711          * sometimes causes the first few TrimDAC writes to malfunction.
2712          */
2713         s626_load_trim_dacs(dev);
2714         ret = s626_load_trim_dacs(dev);
2715         if (ret)
2716                 return ret;
2717 
2718         /*
2719          * Manually init all gate array hardware in case this is a soft
2720          * reset (we have no way of determining whether this is a warm
2721          * or cold start).  This is necessary because the gate array will
2722          * reset only in response to a PCI hard reset; there is no soft
2723          * reset function.
2724          */
2725 
2726         /*
2727          * Init all DAC outputs to 0V and init all DAC setpoint and
2728          * polarity images.
2729          */
2730         for (chan = 0; chan < S626_DAC_CHANNELS; chan++) {
2731                 ret = s626_set_dac(dev, chan, 0);
2732                 if (ret)
2733                         return ret;
2734         }
2735 
2736         /* Init counters */
2737         s626_counters_init(dev);
2738 
2739         /*
2740          * Without modifying the state of the Battery Backup enab, disable
2741          * the watchdog timer, set DIO channels 0-5 to operate in the
2742          * standard DIO (vs. counter overflow) mode, disable the battery
2743          * charger, and reset the watchdog interval selector to zero.
2744          */
2745         s626_write_misc2(dev, (s626_debi_read(dev, S626_LP_RDMISC2) &
2746                                S626_MISC2_BATT_ENABLE));
2747 
2748         /* Initialize the digital I/O subsystem */
2749         s626_dio_init(dev);
2750 
2751         return 0;
2752 }
2753 
2754 static int s626_auto_attach(struct comedi_device *dev,
2755                                       unsigned long context_unused)
2756 {
2757         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2758         struct s626_private *devpriv;
2759         struct comedi_subdevice *s;
2760         int ret;
2761 
2762         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
2763         if (!devpriv)
2764                 return -ENOMEM;
2765 
2766         ret = comedi_pci_enable(dev);
2767         if (ret)
2768                 return ret;
2769 
2770         dev->mmio = pci_ioremap_bar(pcidev, 0);
2771         if (!dev->mmio)
2772                 return -ENOMEM;
2773 
2774         /* disable master interrupt */
2775         writel(0, dev->mmio + S626_P_IER);
2776 
2777         /* soft reset */
2778         writel(S626_MC1_SOFT_RESET, dev->mmio + S626_P_MC1);
2779 
2780         /* DMA FIXME DMA// */
2781 
2782         ret = s626_allocate_dma_buffers(dev);
2783         if (ret)
2784                 return ret;
2785 
2786         if (pcidev->irq) {
2787                 ret = request_irq(pcidev->irq, s626_irq_handler, IRQF_SHARED,
2788                                   dev->board_name, dev);
2789 
2790                 if (ret == 0)
2791                         dev->irq = pcidev->irq;
2792         }
2793 
2794         ret = comedi_alloc_subdevices(dev, 6);
2795         if (ret)
2796                 return ret;
2797 
2798         s = &dev->subdevices[0];
2799         /* analog input subdevice */
2800         s->type         = COMEDI_SUBD_AI;
2801         s->subdev_flags = SDF_READABLE | SDF_DIFF;
2802         s->n_chan       = S626_ADC_CHANNELS;
2803         s->maxdata      = 0x3fff;
2804         s->range_table  = &s626_range_table;
2805         s->len_chanlist = S626_ADC_CHANNELS;
2806         s->insn_read    = s626_ai_insn_read;
2807         if (dev->irq) {
2808                 dev->read_subdev = s;
2809                 s->subdev_flags |= SDF_CMD_READ;
2810                 s->do_cmd       = s626_ai_cmd;
2811                 s->do_cmdtest   = s626_ai_cmdtest;
2812                 s->cancel       = s626_ai_cancel;
2813         }
2814 
2815         s = &dev->subdevices[1];
2816         /* analog output subdevice */
2817         s->type         = COMEDI_SUBD_AO;
2818         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2819         s->n_chan       = S626_DAC_CHANNELS;
2820         s->maxdata      = 0x3fff;
2821         s->range_table  = &range_bipolar10;
2822         s->insn_write   = s626_ao_insn_write;
2823         s->insn_read    = comedi_readback_insn_read;
2824 
2825         ret = comedi_alloc_subdev_readback(s);
2826         if (ret)
2827                 return ret;
2828 
2829         s = &dev->subdevices[2];
2830         /* digital I/O subdevice */
2831         s->type         = COMEDI_SUBD_DIO;
2832         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2833         s->n_chan       = 16;
2834         s->maxdata      = 1;
2835         s->io_bits      = 0xffff;
2836         s->private      = (void *)0;    /* DIO group 0 */
2837         s->range_table  = &range_digital;
2838         s->insn_config  = s626_dio_insn_config;
2839         s->insn_bits    = s626_dio_insn_bits;
2840 
2841         s = &dev->subdevices[3];
2842         /* digital I/O subdevice */
2843         s->type         = COMEDI_SUBD_DIO;
2844         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2845         s->n_chan       = 16;
2846         s->maxdata      = 1;
2847         s->io_bits      = 0xffff;
2848         s->private      = (void *)1;    /* DIO group 1 */
2849         s->range_table  = &range_digital;
2850         s->insn_config  = s626_dio_insn_config;
2851         s->insn_bits    = s626_dio_insn_bits;
2852 
2853         s = &dev->subdevices[4];
2854         /* digital I/O subdevice */
2855         s->type         = COMEDI_SUBD_DIO;
2856         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2857         s->n_chan       = 16;
2858         s->maxdata      = 1;
2859         s->io_bits      = 0xffff;
2860         s->private      = (void *)2;    /* DIO group 2 */
2861         s->range_table  = &range_digital;
2862         s->insn_config  = s626_dio_insn_config;
2863         s->insn_bits    = s626_dio_insn_bits;
2864 
2865         s = &dev->subdevices[5];
2866         /* encoder (counter) subdevice */
2867         s->type         = COMEDI_SUBD_COUNTER;
2868         s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
2869         s->n_chan       = S626_ENCODER_CHANNELS;
2870         s->maxdata      = 0xffffff;
2871         s->range_table  = &range_unknown;
2872         s->insn_config  = s626_enc_insn_config;
2873         s->insn_read    = s626_enc_insn_read;
2874         s->insn_write   = s626_enc_insn_write;
2875 
2876         ret = s626_initialize(dev);
2877         if (ret)
2878                 return ret;
2879 
2880         return 0;
2881 }
2882 
2883 static void s626_detach(struct comedi_device *dev)
2884 {
2885         struct s626_private *devpriv = dev->private;
2886 
2887         if (devpriv) {
2888                 /* stop ai_command */
2889                 devpriv->ai_cmd_running = 0;
2890 
2891                 if (dev->mmio) {
2892                         /* interrupt mask */
2893                         /* Disable master interrupt */
2894                         writel(0, dev->mmio + S626_P_IER);
2895                         /* Clear board's IRQ status flag */
2896                         writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1,
2897                                dev->mmio + S626_P_ISR);
2898 
2899                         /* Disable the watchdog timer and battery charger. */
2900                         s626_write_misc2(dev, 0);
2901 
2902                         /* Close all interfaces on 7146 device */
2903                         writel(S626_MC1_SHUTDOWN, dev->mmio + S626_P_MC1);
2904                         writel(S626_ACON1_BASE, dev->mmio + S626_P_ACON1);
2905                 }
2906         }
2907         comedi_pci_detach(dev);
2908         s626_free_dma_buffers(dev);
2909 }
2910 
2911 static struct comedi_driver s626_driver = {
2912         .driver_name    = "s626",
2913         .module         = THIS_MODULE,
2914         .auto_attach    = s626_auto_attach,
2915         .detach         = s626_detach,
2916 };
2917 
2918 static int s626_pci_probe(struct pci_dev *dev,
2919                           const struct pci_device_id *id)
2920 {
2921         return comedi_pci_auto_config(dev, &s626_driver, id->driver_data);
2922 }
2923 
2924 /*
2925  * For devices with vendor:device id == 0x1131:0x7146 you must specify
2926  * also subvendor:subdevice ids, because otherwise it will conflict with
2927  * Philips SAA7146 media/dvb based cards.
2928  */
2929 static const struct pci_device_id s626_pci_table[] = {
2930         { PCI_DEVICE_SUB(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA7146,
2931                          0x6000, 0x0272) },
2932         { 0 }
2933 };
2934 MODULE_DEVICE_TABLE(pci, s626_pci_table);
2935 
2936 static struct pci_driver s626_pci_driver = {
2937         .name           = "s626",
2938         .id_table       = s626_pci_table,
2939         .probe          = s626_pci_probe,
2940         .remove         = comedi_pci_auto_unconfig,
2941 };
2942 module_comedi_pci_driver(s626_driver, s626_pci_driver);
2943 
2944 MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
2945 MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
2946 MODULE_LICENSE("GPL");
2947 

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