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Linux/drivers/staging/comedi/drivers/s626.c

  1 /*
  2  * comedi/drivers/s626.c
  3  * Sensoray s626 Comedi driver
  4  *
  5  * COMEDI - Linux Control and Measurement Device Interface
  6  * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
  7  *
  8  * Based on Sensoray Model 626 Linux driver Version 0.2
  9  * Copyright (C) 2002-2004 Sensoray Co., Inc.
 10  *
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License as published by
 13  * the Free Software Foundation; either version 2 of the License, or
 14  * (at your option) any later version.
 15  *
 16  * This program is distributed in the hope that it will be useful,
 17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19  * GNU General Public License for more details.
 20  */
 21 
 22 /*
 23  * Driver: s626
 24  * Description: Sensoray 626 driver
 25  * Devices: [Sensoray] 626 (s626)
 26  * Authors: Gianluca Palli <gpalli@deis.unibo.it>,
 27  * Updated: Fri, 15 Feb 2008 10:28:42 +0000
 28  * Status: experimental
 29 
 30  * Configuration options: not applicable, uses PCI auto config
 31 
 32  * INSN_CONFIG instructions:
 33  *   analog input:
 34  *    none
 35  *
 36  *   analog output:
 37  *    none
 38  *
 39  *   digital channel:
 40  *    s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
 41  *    supported configuration options:
 42  *    INSN_CONFIG_DIO_QUERY
 43  *    COMEDI_INPUT
 44  *    COMEDI_OUTPUT
 45  *
 46  *   encoder:
 47  *    Every channel must be configured before reading.
 48  *
 49  *   Example code
 50  *
 51  *    insn.insn=INSN_CONFIG;   //configuration instruction
 52  *    insn.n=1;                //number of operation (must be 1)
 53  *    insn.data=&initialvalue; //initial value loaded into encoder
 54  *                             //during configuration
 55  *    insn.subdev=5;           //encoder subdevice
 56  *    insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
 57  *                                                         //to configure
 58  *
 59  *    comedi_do_insn(cf,&insn); //executing configuration
 60  */
 61 
 62 #include <linux/module.h>
 63 #include <linux/delay.h>
 64 #include <linux/interrupt.h>
 65 #include <linux/kernel.h>
 66 #include <linux/types.h>
 67 
 68 #include "../comedi_pci.h"
 69 
 70 #include "s626.h"
 71 
 72 struct s626_buffer_dma {
 73         dma_addr_t physical_base;
 74         void *logical_base;
 75 };
 76 
 77 struct s626_private {
 78         uint8_t ai_cmd_running;         /* ai_cmd is running */
 79         unsigned int ai_sample_timer;   /* time between samples in
 80                                          * units of the timer */
 81         int ai_convert_count;           /* conversion counter */
 82         unsigned int ai_convert_timer;  /* time between conversion in
 83                                          * units of the timer */
 84         uint16_t counter_int_enabs;     /* counter interrupt enable mask
 85                                          * for MISC2 register */
 86         uint8_t adc_items;              /* number of items in ADC poll list */
 87         struct s626_buffer_dma rps_buf; /* DMA buffer used to hold ADC (RPS1)
 88                                          * program */
 89         struct s626_buffer_dma ana_buf; /* DMA buffer used to receive ADC data
 90                                          * and hold DAC data */
 91         uint32_t *dac_wbuf;             /* pointer to logical adrs of DMA buffer
 92                                          * used to hold DAC data */
 93         uint16_t dacpol;                /* image of DAC polarity register */
 94         uint8_t trim_setpoint[12];      /* images of TrimDAC setpoints */
 95         uint32_t i2c_adrs;              /* I2C device address for onboard EEPROM
 96                                          * (board rev dependent) */
 97 };
 98 
 99 /* Counter overflow/index event flag masks for RDMISC2. */
100 #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 +  4)))
101 #define S626_OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
102 
103 /*
104  * Enable/disable a function or test status bit(s) that are accessed
105  * through Main Control Registers 1 or 2.
106  */
107 static void s626_mc_enable(struct comedi_device *dev,
108                            unsigned int cmd, unsigned int reg)
109 {
110         unsigned int val = (cmd << 16) | cmd;
111 
112         mmiowb();
113         writel(val, dev->mmio + reg);
114 }
115 
116 static void s626_mc_disable(struct comedi_device *dev,
117                             unsigned int cmd, unsigned int reg)
118 {
119         writel(cmd << 16, dev->mmio + reg);
120         mmiowb();
121 }
122 
123 static bool s626_mc_test(struct comedi_device *dev,
124                          unsigned int cmd, unsigned int reg)
125 {
126         unsigned int val;
127 
128         val = readl(dev->mmio + reg);
129 
130         return (val & cmd) ? true : false;
131 }
132 
133 #define S626_BUGFIX_STREG(REGADRS)   ((REGADRS) - 4)
134 
135 /* Write a time slot control record to TSL2. */
136 #define S626_VECTPORT(VECTNUM)          (S626_P_TSL2 + ((VECTNUM) << 2))
137 
138 static const struct comedi_lrange s626_range_table = {
139         2, {
140                 BIP_RANGE(5),
141                 BIP_RANGE(10)
142         }
143 };
144 
145 /*
146  * Execute a DEBI transfer.  This must be called from within a critical section.
147  */
148 static void s626_debi_transfer(struct comedi_device *dev)
149 {
150         static const int timeout = 10000;
151         int i;
152 
153         /* Initiate upload of shadow RAM to DEBI control register */
154         s626_mc_enable(dev, S626_MC2_UPLD_DEBI, S626_P_MC2);
155 
156         /*
157          * Wait for completion of upload from shadow RAM to
158          * DEBI control register.
159          */
160         for (i = 0; i < timeout; i++) {
161                 if (s626_mc_test(dev, S626_MC2_UPLD_DEBI, S626_P_MC2))
162                         break;
163                 udelay(1);
164         }
165         if (i == timeout)
166                 dev_err(dev->class_dev,
167                         "Timeout while uploading to DEBI control register\n");
168 
169         /* Wait until DEBI transfer is done */
170         for (i = 0; i < timeout; i++) {
171                 if (!(readl(dev->mmio + S626_P_PSR) & S626_PSR_DEBI_S))
172                         break;
173                 udelay(1);
174         }
175         if (i == timeout)
176                 dev_err(dev->class_dev, "DEBI transfer timeout\n");
177 }
178 
179 /*
180  * Read a value from a gate array register.
181  */
182 static uint16_t s626_debi_read(struct comedi_device *dev, uint16_t addr)
183 {
184         /* Set up DEBI control register value in shadow RAM */
185         writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD);
186 
187         /*  Execute the DEBI transfer. */
188         s626_debi_transfer(dev);
189 
190         return readl(dev->mmio + S626_P_DEBIAD);
191 }
192 
193 /*
194  * Write a value to a gate array register.
195  */
196 static void s626_debi_write(struct comedi_device *dev, uint16_t addr,
197                             uint16_t wdata)
198 {
199         /* Set up DEBI control register value in shadow RAM */
200         writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD);
201         writel(wdata, dev->mmio + S626_P_DEBIAD);
202 
203         /*  Execute the DEBI transfer. */
204         s626_debi_transfer(dev);
205 }
206 
207 /*
208  * Replace the specified bits in a gate array register.  Imports: mask
209  * specifies bits that are to be preserved, wdata is new value to be
210  * or'd with the masked original.
211  */
212 static void s626_debi_replace(struct comedi_device *dev, unsigned int addr,
213                               unsigned int mask, unsigned int wdata)
214 {
215         unsigned int val;
216 
217         addr &= 0xffff;
218         writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD);
219         s626_debi_transfer(dev);
220 
221         writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD);
222         val = readl(dev->mmio + S626_P_DEBIAD);
223         val &= mask;
224         val |= wdata;
225         writel(val & 0xffff, dev->mmio + S626_P_DEBIAD);
226         s626_debi_transfer(dev);
227 }
228 
229 /* **************  EEPROM ACCESS FUNCTIONS  ************** */
230 
231 static int s626_i2c_handshake_eoc(struct comedi_device *dev,
232                                   struct comedi_subdevice *s,
233                                   struct comedi_insn *insn,
234                                   unsigned long context)
235 {
236         bool status;
237 
238         status = s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
239         if (status)
240                 return 0;
241         return -EBUSY;
242 }
243 
244 static int s626_i2c_handshake(struct comedi_device *dev, uint32_t val)
245 {
246         unsigned int ctrl;
247         int ret;
248 
249         /* Write I2C command to I2C Transfer Control shadow register */
250         writel(val, dev->mmio + S626_P_I2CCTRL);
251 
252         /*
253          * Upload I2C shadow registers into working registers and
254          * wait for upload confirmation.
255          */
256         s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
257         ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
258         if (ret)
259                 return ret;
260 
261         /* Wait until I2C bus transfer is finished or an error occurs */
262         do {
263                 ctrl = readl(dev->mmio + S626_P_I2CCTRL);
264         } while ((ctrl & (S626_I2C_BUSY | S626_I2C_ERR)) == S626_I2C_BUSY);
265 
266         /* Return non-zero if I2C error occurred */
267         return ctrl & S626_I2C_ERR;
268 }
269 
270 /* Read uint8_t from EEPROM. */
271 static uint8_t s626_i2c_read(struct comedi_device *dev, uint8_t addr)
272 {
273         struct s626_private *devpriv = dev->private;
274 
275         /*
276          * Send EEPROM target address:
277          *  Byte2 = I2C command: write to I2C EEPROM device.
278          *  Byte1 = EEPROM internal target address.
279          *  Byte0 = Not sent.
280          */
281         if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
282                                                 devpriv->i2c_adrs) |
283                                     S626_I2C_B1(S626_I2C_ATTRSTOP, addr) |
284                                     S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
285                 /* Abort function and declare error if handshake failed. */
286                 return 0;
287 
288         /*
289          * Execute EEPROM read:
290          *  Byte2 = I2C command: read from I2C EEPROM device.
291          *  Byte1 receives uint8_t from EEPROM.
292          *  Byte0 = Not sent.
293          */
294         if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
295                                                 (devpriv->i2c_adrs | 1)) |
296                                     S626_I2C_B1(S626_I2C_ATTRSTOP, 0) |
297                                     S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
298                 /* Abort function and declare error if handshake failed. */
299                 return 0;
300 
301         return (readl(dev->mmio + S626_P_I2CCTRL) >> 16) & 0xff;
302 }
303 
304 /* ***********  DAC FUNCTIONS *********** */
305 
306 /* TrimDac LogicalChan-to-PhysicalChan mapping table. */
307 static const uint8_t s626_trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
308 
309 /* TrimDac LogicalChan-to-EepromAdrs mapping table. */
310 static const uint8_t s626_trimadrs[] = {
311         0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63
312 };
313 
314 enum {
315         s626_send_dac_wait_not_mc1_a2out,
316         s626_send_dac_wait_ssr_af2_out,
317         s626_send_dac_wait_fb_buffer2_msb_00,
318         s626_send_dac_wait_fb_buffer2_msb_ff
319 };
320 
321 static int s626_send_dac_eoc(struct comedi_device *dev,
322                              struct comedi_subdevice *s,
323                              struct comedi_insn *insn,
324                              unsigned long context)
325 {
326         unsigned int status;
327 
328         switch (context) {
329         case s626_send_dac_wait_not_mc1_a2out:
330                 status = readl(dev->mmio + S626_P_MC1);
331                 if (!(status & S626_MC1_A2OUT))
332                         return 0;
333                 break;
334         case s626_send_dac_wait_ssr_af2_out:
335                 status = readl(dev->mmio + S626_P_SSR);
336                 if (status & S626_SSR_AF2_OUT)
337                         return 0;
338                 break;
339         case s626_send_dac_wait_fb_buffer2_msb_00:
340                 status = readl(dev->mmio + S626_P_FB_BUFFER2);
341                 if (!(status & 0xff000000))
342                         return 0;
343                 break;
344         case s626_send_dac_wait_fb_buffer2_msb_ff:
345                 status = readl(dev->mmio + S626_P_FB_BUFFER2);
346                 if (status & 0xff000000)
347                         return 0;
348                 break;
349         default:
350                 return -EINVAL;
351         }
352         return -EBUSY;
353 }
354 
355 /*
356  * Private helper function: Transmit serial data to DAC via Audio
357  * channel 2.  Assumes: (1) TSL2 slot records initialized, and (2)
358  * dacpol contains valid target image.
359  */
360 static int s626_send_dac(struct comedi_device *dev, uint32_t val)
361 {
362         struct s626_private *devpriv = dev->private;
363         int ret;
364 
365         /* START THE SERIAL CLOCK RUNNING ------------- */
366 
367         /*
368          * Assert DAC polarity control and enable gating of DAC serial clock
369          * and audio bit stream signals.  At this point in time we must be
370          * assured of being in time slot 0.  If we are not in slot 0, the
371          * serial clock and audio stream signals will be disabled; this is
372          * because the following s626_debi_write statement (which enables
373          * signals to be passed through the gate array) would execute before
374          * the trailing edge of WS1/WS3 (which turns off the signals), thus
375          * causing the signals to be inactive during the DAC write.
376          */
377         s626_debi_write(dev, S626_LP_DACPOL, devpriv->dacpol);
378 
379         /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
380 
381         /* Copy DAC setpoint value to DAC's output DMA buffer. */
382         /* writel(val, dev->mmio + (uint32_t)devpriv->dac_wbuf); */
383         *devpriv->dac_wbuf = val;
384 
385         /*
386          * Enable the output DMA transfer. This will cause the DMAC to copy
387          * the DAC's data value to A2's output FIFO. The DMA transfer will
388          * then immediately terminate because the protection address is
389          * reached upon transfer of the first DWORD value.
390          */
391         s626_mc_enable(dev, S626_MC1_A2OUT, S626_P_MC1);
392 
393         /* While the DMA transfer is executing ... */
394 
395         /*
396          * Reset Audio2 output FIFO's underflow flag (along with any
397          * other FIFO underflow/overflow flags). When set, this flag
398          * will indicate that we have emerged from slot 0.
399          */
400         writel(S626_ISR_AFOU, dev->mmio + S626_P_ISR);
401 
402         /*
403          * Wait for the DMA transfer to finish so that there will be data
404          * available in the FIFO when time slot 1 tries to transfer a DWORD
405          * from the FIFO to the output buffer register.  We test for DMA
406          * Done by polling the DMAC enable flag; this flag is automatically
407          * cleared when the transfer has finished.
408          */
409         ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
410                              s626_send_dac_wait_not_mc1_a2out);
411         if (ret) {
412                 dev_err(dev->class_dev, "DMA transfer timeout\n");
413                 return ret;
414         }
415 
416         /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
417 
418         /*
419          * FIFO data is now available, so we enable execution of time slots
420          * 1 and higher by clearing the EOS flag in slot 0.  Note that SD3
421          * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
422          * detection.
423          */
424         writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2,
425                dev->mmio + S626_VECTPORT(0));
426 
427         /*
428          * Wait for slot 1 to execute to ensure that the Packet will be
429          * transmitted.  This is detected by polling the Audio2 output FIFO
430          * underflow flag, which will be set when slot 1 execution has
431          * finished transferring the DAC's data DWORD from the output FIFO
432          * to the output buffer register.
433          */
434         ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
435                              s626_send_dac_wait_ssr_af2_out);
436         if (ret) {
437                 dev_err(dev->class_dev,
438                         "TSL timeout waiting for slot 1 to execute\n");
439                 return ret;
440         }
441 
442         /*
443          * Set up to trap execution at slot 0 when the TSL sequencer cycles
444          * back to slot 0 after executing the EOS in slot 5.  Also,
445          * simultaneously shift out and in the 0x00 that is ALWAYS the value
446          * stored in the last byte to be shifted out of the FIFO's DWORD
447          * buffer register.
448          */
449         writel(S626_XSD2 | S626_XFIFO_2 | S626_RSD2 | S626_SIB_A2 | S626_EOS,
450                dev->mmio + S626_VECTPORT(0));
451 
452         /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
453 
454         /*
455          * Wait for the TSL to finish executing all time slots before
456          * exiting this function.  We must do this so that the next DAC
457          * write doesn't start, thereby enabling clock/chip select signals:
458          *
459          * 1. Before the TSL sequence cycles back to slot 0, which disables
460          *    the clock/cs signal gating and traps slot // list execution.
461          *    we have not yet finished slot 5 then the clock/cs signals are
462          *    still gated and we have not finished transmitting the stream.
463          *
464          * 2. While slots 2-5 are executing due to a late slot 0 trap.  In
465          *    this case, the slot sequence is currently repeating, but with
466          *    clock/cs signals disabled.  We must wait for slot 0 to trap
467          *    execution before setting up the next DAC setpoint DMA transfer
468          *    and enabling the clock/cs signals.  To detect the end of slot 5,
469          *    we test for the FB_BUFFER2 MSB contents to be equal to 0xFF.  If
470          *    the TSL has not yet finished executing slot 5 ...
471          */
472         if (readl(dev->mmio + S626_P_FB_BUFFER2) & 0xff000000) {
473                 /*
474                  * The trap was set on time and we are still executing somewhere
475                  * in slots 2-5, so we now wait for slot 0 to execute and trap
476                  * TSL execution.  This is detected when FB_BUFFER2 MSB changes
477                  * from 0xFF to 0x00, which slot 0 causes to happen by shifting
478                  * out/in on SD2 the 0x00 that is always referenced by slot 5.
479                  */
480                 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
481                                      s626_send_dac_wait_fb_buffer2_msb_00);
482                 if (ret) {
483                         dev_err(dev->class_dev,
484                                 "TSL timeout waiting for slot 0 to execute\n");
485                         return ret;
486                 }
487         }
488         /*
489          * Either (1) we were too late setting the slot 0 trap; the TSL
490          * sequencer restarted slot 0 before we could set the EOS trap flag,
491          * or (2) we were not late and execution is now trapped at slot 0.
492          * In either case, we must now change slot 0 so that it will store
493          * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
494          * In order to do this, we reprogram slot 0 so that it will shift in
495          * SD3, which is driven only by a pull-up resistor.
496          */
497         writel(S626_RSD3 | S626_SIB_A2 | S626_EOS,
498                dev->mmio + S626_VECTPORT(0));
499 
500         /*
501          * Wait for slot 0 to execute, at which time the TSL is setup for
502          * the next DAC write.  This is detected when FB_BUFFER2 MSB changes
503          * from 0x00 to 0xFF.
504          */
505         ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
506                              s626_send_dac_wait_fb_buffer2_msb_ff);
507         if (ret) {
508                 dev_err(dev->class_dev,
509                         "TSL timeout waiting for slot 0 to execute\n");
510                 return ret;
511         }
512         return 0;
513 }
514 
515 /*
516  * Private helper function: Write setpoint to an application DAC channel.
517  */
518 static int s626_set_dac(struct comedi_device *dev,
519                         uint16_t chan, int16_t dacdata)
520 {
521         struct s626_private *devpriv = dev->private;
522         uint16_t signmask;
523         uint32_t ws_image;
524         uint32_t val;
525 
526         /*
527          * Adjust DAC data polarity and set up Polarity Control Register image.
528          */
529         signmask = 1 << chan;
530         if (dacdata < 0) {
531                 dacdata = -dacdata;
532                 devpriv->dacpol |= signmask;
533         } else {
534                 devpriv->dacpol &= ~signmask;
535         }
536 
537         /* Limit DAC setpoint value to valid range. */
538         if ((uint16_t)dacdata > 0x1FFF)
539                 dacdata = 0x1FFF;
540 
541         /*
542          * Set up TSL2 records (aka "vectors") for DAC update.  Vectors V2
543          * and V3 transmit the setpoint to the target DAC.  V4 and V5 send
544          * data to a non-existent TrimDac channel just to keep the clock
545          * running after sending data to the target DAC.  This is necessary
546          * to eliminate the clock glitch that would otherwise occur at the
547          * end of the target DAC's serial data stream.  When the sequence
548          * restarts at V0 (after executing V5), the gate array automatically
549          * disables gating for the DAC clock and all DAC chip selects.
550          */
551 
552         /* Choose DAC chip select to be asserted */
553         ws_image = (chan & 2) ? S626_WS1 : S626_WS2;
554         /* Slot 2: Transmit high data byte to target DAC */
555         writel(S626_XSD2 | S626_XFIFO_1 | ws_image,
556                dev->mmio + S626_VECTPORT(2));
557         /* Slot 3: Transmit low data byte to target DAC */
558         writel(S626_XSD2 | S626_XFIFO_0 | ws_image,
559                dev->mmio + S626_VECTPORT(3));
560         /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
561         writel(S626_XSD2 | S626_XFIFO_3 | S626_WS3,
562                dev->mmio + S626_VECTPORT(4));
563         /* Slot 5: running after writing target DAC's low data byte */
564         writel(S626_XSD2 | S626_XFIFO_2 | S626_WS3 | S626_EOS,
565                dev->mmio + S626_VECTPORT(5));
566 
567         /*
568          * Construct and transmit target DAC's serial packet:
569          * (A10D DDDD), (DDDD DDDD), (0x0F), (0x00) where A is chan<0>,
570          * and D<12:0> is the DAC setpoint.  Append a WORD value (that writes
571          * to a  non-existent TrimDac channel) that serves to keep the clock
572          * running after the packet has been sent to the target DAC.
573          */
574         val = 0x0F000000;       /* Continue clock after target DAC data
575                                  * (write to non-existent trimdac). */
576         val |= 0x00004000;      /* Address the two main dual-DAC devices
577                                  * (TSL's chip select enables target device). */
578         val |= ((uint32_t)(chan & 1) << 15);    /* Address the DAC channel
579                                                  * within the device. */
580         val |= (uint32_t)dacdata;       /* Include DAC setpoint data. */
581         return s626_send_dac(dev, val);
582 }
583 
584 static int s626_write_trim_dac(struct comedi_device *dev,
585                                uint8_t logical_chan, uint8_t dac_data)
586 {
587         struct s626_private *devpriv = dev->private;
588         uint32_t chan;
589 
590         /*
591          * Save the new setpoint in case the application needs to read it back
592          * later.
593          */
594         devpriv->trim_setpoint[logical_chan] = (uint8_t)dac_data;
595 
596         /* Map logical channel number to physical channel number. */
597         chan = s626_trimchan[logical_chan];
598 
599         /*
600          * Set up TSL2 records for TrimDac write operation.  All slots shift
601          * 0xFF in from pulled-up SD3 so that the end of the slot sequence
602          * can be detected.
603          */
604 
605         /* Slot 2: Send high uint8_t to target TrimDac */
606         writel(S626_XSD2 | S626_XFIFO_1 | S626_WS3,
607                dev->mmio + S626_VECTPORT(2));
608         /* Slot 3: Send low uint8_t to target TrimDac */
609         writel(S626_XSD2 | S626_XFIFO_0 | S626_WS3,
610                dev->mmio + S626_VECTPORT(3));
611         /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */
612         writel(S626_XSD2 | S626_XFIFO_3 | S626_WS1,
613                dev->mmio + S626_VECTPORT(4));
614         /* Slot 5: Send NOP low  uint8_t to DAC0 */
615         writel(S626_XSD2 | S626_XFIFO_2 | S626_WS1 | S626_EOS,
616                dev->mmio + S626_VECTPORT(5));
617 
618         /*
619          * Construct and transmit target DAC's serial packet:
620          * (0000 AAAA), (DDDD DDDD), (0x00), (0x00) where A<3:0> is the
621          * DAC channel's address, and D<7:0> is the DAC setpoint.  Append a
622          * WORD value (that writes a channel 0 NOP command to a non-existent
623          * main DAC channel) that serves to keep the clock running after the
624          * packet has been sent to the target DAC.
625          */
626 
627         /*
628          * Address the DAC channel within the trimdac device.
629          * Include DAC setpoint data.
630          */
631         return s626_send_dac(dev, (chan << 8) | dac_data);
632 }
633 
634 static int s626_load_trim_dacs(struct comedi_device *dev)
635 {
636         uint8_t i;
637         int ret;
638 
639         /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
640         for (i = 0; i < ARRAY_SIZE(s626_trimchan); i++) {
641                 ret = s626_write_trim_dac(dev, i,
642                                           s626_i2c_read(dev, s626_trimadrs[i]));
643                 if (ret)
644                         return ret;
645         }
646         return 0;
647 }
648 
649 /* ******  COUNTER FUNCTIONS  ******* */
650 
651 /*
652  * All counter functions address a specific counter by means of the
653  * "Counter" argument, which is a logical counter number.  The Counter
654  * argument may have any of the following legal values: 0=0A, 1=1A,
655  * 2=2A, 3=0B, 4=1B, 5=2B.
656  */
657 
658 /*
659  * Return/set a counter pair's latch trigger source.  0: On read
660  * access, 1: A index latches A, 2: B index latches B, 3: A overflow
661  * latches B.
662  */
663 static void s626_set_latch_source(struct comedi_device *dev,
664                                   unsigned int chan, uint16_t value)
665 {
666         s626_debi_replace(dev, S626_LP_CRB(chan),
667                           ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_LATCHSRC),
668                           S626_SET_CRB_LATCHSRC(value));
669 }
670 
671 /*
672  * Write value into counter preload register.
673  */
674 static void s626_preload(struct comedi_device *dev,
675                          unsigned int chan, uint32_t value)
676 {
677         s626_debi_write(dev, S626_LP_CNTR(chan), value);
678         s626_debi_write(dev, S626_LP_CNTR(chan) + 2, value >> 16);
679 }
680 
681 /* ******  PRIVATE COUNTER FUNCTIONS ****** */
682 
683 /*
684  * Reset a counter's index and overflow event capture flags.
685  */
686 static void s626_reset_cap_flags(struct comedi_device *dev,
687                                  unsigned int chan)
688 {
689         uint16_t set;
690 
691         set = S626_SET_CRB_INTRESETCMD(1);
692         if (chan < 3)
693                 set |= S626_SET_CRB_INTRESET_A(1);
694         else
695                 set |= S626_SET_CRB_INTRESET_B(1);
696 
697         s626_debi_replace(dev, S626_LP_CRB(chan), ~S626_CRBMSK_INTCTRL, set);
698 }
699 
700 #ifdef unused
701 /*
702  * Return counter setup in a format (COUNTER_SETUP) that is consistent
703  * for both A and B counters.
704  */
705 static uint16_t s626_get_mode_a(struct comedi_device *dev,
706                                 unsigned int chan)
707 {
708         uint16_t cra;
709         uint16_t crb;
710         uint16_t setup;
711         unsigned cntsrc, clkmult, clkpol, encmode;
712 
713         /* Fetch CRA and CRB register images. */
714         cra = s626_debi_read(dev, S626_LP_CRA(chan));
715         crb = s626_debi_read(dev, S626_LP_CRB(chan));
716 
717         /*
718          * Populate the standardized counter setup bit fields.
719          */
720         setup =
721                 /* LoadSrc  = LoadSrcA. */
722                 S626_SET_STD_LOADSRC(S626_GET_CRA_LOADSRC_A(cra)) |
723                 /* LatchSrc = LatchSrcA. */
724                 S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) |
725                 /* IntSrc   = IntSrcA. */
726                 S626_SET_STD_INTSRC(S626_GET_CRA_INTSRC_A(cra)) |
727                 /* IndxSrc  = IndxSrcA. */
728                 S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_A(cra)) |
729                 /* IndxPol  = IndxPolA. */
730                 S626_SET_STD_INDXPOL(S626_GET_CRA_INDXPOL_A(cra)) |
731                 /* ClkEnab  = ClkEnabA. */
732                 S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_A(crb));
733 
734         /* Adjust mode-dependent parameters. */
735         cntsrc = S626_GET_CRA_CNTSRC_A(cra);
736         if (cntsrc & S626_CNTSRC_SYSCLK) {
737                 /* Timer mode (CntSrcA<1> == 1): */
738                 encmode = S626_ENCMODE_TIMER;
739                 /* Set ClkPol to indicate count direction (CntSrcA<0>). */
740                 clkpol = cntsrc & 1;
741                 /* ClkMult must be 1x in Timer mode. */
742                 clkmult = S626_CLKMULT_1X;
743         } else {
744                 /* Counter mode (CntSrcA<1> == 0): */
745                 encmode = S626_ENCMODE_COUNTER;
746                 /* Pass through ClkPol. */
747                 clkpol = S626_GET_CRA_CLKPOL_A(cra);
748                 /* Force ClkMult to 1x if not legal, else pass through. */
749                 clkmult = S626_GET_CRA_CLKMULT_A(cra);
750                 if (clkmult == S626_CLKMULT_SPECIAL)
751                         clkmult = S626_CLKMULT_1X;
752         }
753         setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) |
754                  S626_SET_STD_CLKPOL(clkpol);
755 
756         /* Return adjusted counter setup. */
757         return setup;
758 }
759 
760 static uint16_t s626_get_mode_b(struct comedi_device *dev,
761                                 unsigned int chan)
762 {
763         uint16_t cra;
764         uint16_t crb;
765         uint16_t setup;
766         unsigned cntsrc, clkmult, clkpol, encmode;
767 
768         /* Fetch CRA and CRB register images. */
769         cra = s626_debi_read(dev, S626_LP_CRA(chan));
770         crb = s626_debi_read(dev, S626_LP_CRB(chan));
771 
772         /*
773          * Populate the standardized counter setup bit fields.
774          */
775         setup =
776                 /* IntSrc   = IntSrcB. */
777                 S626_SET_STD_INTSRC(S626_GET_CRB_INTSRC_B(crb)) |
778                 /* LatchSrc = LatchSrcB. */
779                 S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) |
780                 /* LoadSrc  = LoadSrcB. */
781                 S626_SET_STD_LOADSRC(S626_GET_CRB_LOADSRC_B(crb)) |
782                 /* IndxPol  = IndxPolB. */
783                 S626_SET_STD_INDXPOL(S626_GET_CRB_INDXPOL_B(crb)) |
784                 /* ClkEnab  = ClkEnabB. */
785                 S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_B(crb)) |
786                 /* IndxSrc  = IndxSrcB. */
787                 S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_B(cra));
788 
789         /* Adjust mode-dependent parameters. */
790         cntsrc = S626_GET_CRA_CNTSRC_B(cra);
791         clkmult = S626_GET_CRB_CLKMULT_B(crb);
792         if (clkmult == S626_CLKMULT_SPECIAL) {
793                 /* Extender mode (ClkMultB == S626_CLKMULT_SPECIAL): */
794                 encmode = S626_ENCMODE_EXTENDER;
795                 /* Indicate multiplier is 1x. */
796                 clkmult = S626_CLKMULT_1X;
797                 /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
798                 clkpol = cntsrc & 1;
799         } else if (cntsrc & S626_CNTSRC_SYSCLK) {
800                 /* Timer mode (CntSrcB<1> == 1): */
801                 encmode = S626_ENCMODE_TIMER;
802                 /* Indicate multiplier is 1x. */
803                 clkmult = S626_CLKMULT_1X;
804                 /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
805                 clkpol = cntsrc & 1;
806         } else {
807                 /* If Counter mode (CntSrcB<1> == 0): */
808                 encmode = S626_ENCMODE_COUNTER;
809                 /* Clock multiplier is passed through. */
810                 /* Clock polarity is passed through. */
811                 clkpol = S626_GET_CRB_CLKPOL_B(crb);
812         }
813         setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) |
814                  S626_SET_STD_CLKPOL(clkpol);
815 
816         /* Return adjusted counter setup. */
817         return setup;
818 }
819 
820 static uint16_t s626_get_mode(struct comedi_device *dev,
821                               unsigned int chan)
822 {
823         return (chan < 3) ? s626_get_mode_a(dev, chan)
824                           : s626_get_mode_b(dev, chan);
825 }
826 #endif
827 
828 /*
829  * Set the operating mode for the specified counter.  The setup
830  * parameter is treated as a COUNTER_SETUP data type.  The following
831  * parameters are programmable (all other parms are ignored): ClkMult,
832  * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
833  */
834 static void s626_set_mode_a(struct comedi_device *dev,
835                             unsigned int chan, uint16_t setup,
836                             uint16_t disable_int_src)
837 {
838         struct s626_private *devpriv = dev->private;
839         uint16_t cra;
840         uint16_t crb;
841         unsigned cntsrc, clkmult, clkpol;
842 
843         /* Initialize CRA and CRB images. */
844         /* Preload trigger is passed through. */
845         cra = S626_SET_CRA_LOADSRC_A(S626_GET_STD_LOADSRC(setup));
846         /* IndexSrc is passed through. */
847         cra |= S626_SET_CRA_INDXSRC_A(S626_GET_STD_INDXSRC(setup));
848 
849         /* Reset any pending CounterA event captures. */
850         crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_A(1);
851         /* Clock enable is passed through. */
852         crb |= S626_SET_CRB_CLKENAB_A(S626_GET_STD_CLKENAB(setup));
853 
854         /* Force IntSrc to Disabled if disable_int_src is asserted. */
855         if (!disable_int_src)
856                 cra |= S626_SET_CRA_INTSRC_A(S626_GET_STD_INTSRC(setup));
857 
858         /* Populate all mode-dependent attributes of CRA & CRB images. */
859         clkpol = S626_GET_STD_CLKPOL(setup);
860         switch (S626_GET_STD_ENCMODE(setup)) {
861         case S626_ENCMODE_EXTENDER: /* Extender Mode: */
862                 /* Force to Timer mode (Extender valid only for B counters). */
863                 /* Fall through to case S626_ENCMODE_TIMER: */
864         case S626_ENCMODE_TIMER:        /* Timer Mode: */
865                 /* CntSrcA<1> selects system clock */
866                 cntsrc = S626_CNTSRC_SYSCLK;
867                 /* Count direction (CntSrcA<0>) obtained from ClkPol. */
868                 cntsrc |= clkpol;
869                 /* ClkPolA behaves as always-on clock enable. */
870                 clkpol = 1;
871                 /* ClkMult must be 1x. */
872                 clkmult = S626_CLKMULT_1X;
873                 break;
874         default:                /* Counter Mode: */
875                 /* Select ENC_C and ENC_D as clock/direction inputs. */
876                 cntsrc = S626_CNTSRC_ENCODER;
877                 /* Clock polarity is passed through. */
878                 /* Force multiplier to x1 if not legal, else pass through. */
879                 clkmult = S626_GET_STD_CLKMULT(setup);
880                 if (clkmult == S626_CLKMULT_SPECIAL)
881                         clkmult = S626_CLKMULT_1X;
882                 break;
883         }
884         cra |= S626_SET_CRA_CNTSRC_A(cntsrc) | S626_SET_CRA_CLKPOL_A(clkpol) |
885                S626_SET_CRA_CLKMULT_A(clkmult);
886 
887         /*
888          * Force positive index polarity if IndxSrc is software-driven only,
889          * otherwise pass it through.
890          */
891         if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
892                 cra |= S626_SET_CRA_INDXPOL_A(S626_GET_STD_INDXPOL(setup));
893 
894         /*
895          * If IntSrc has been forced to Disabled, update the MISC2 interrupt
896          * enable mask to indicate the counter interrupt is disabled.
897          */
898         if (disable_int_src)
899                 devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
900                                                 S626_INDXMASK(chan));
901 
902         /*
903          * While retaining CounterB and LatchSrc configurations, program the
904          * new counter operating mode.
905          */
906         s626_debi_replace(dev, S626_LP_CRA(chan),
907                           S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B, cra);
908         s626_debi_replace(dev, S626_LP_CRB(chan),
909                           ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), crb);
910 }
911 
912 static void s626_set_mode_b(struct comedi_device *dev,
913                             unsigned int chan, uint16_t setup,
914                             uint16_t disable_int_src)
915 {
916         struct s626_private *devpriv = dev->private;
917         uint16_t cra;
918         uint16_t crb;
919         unsigned cntsrc, clkmult, clkpol;
920 
921         /* Initialize CRA and CRB images. */
922         /* IndexSrc is passed through. */
923         cra = S626_SET_CRA_INDXSRC_B(S626_GET_STD_INDXSRC(setup));
924 
925         /* Reset event captures and disable interrupts. */
926         crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_B(1);
927         /* Clock enable is passed through. */
928         crb |= S626_SET_CRB_CLKENAB_B(S626_GET_STD_CLKENAB(setup));
929         /* Preload trigger source is passed through. */
930         crb |= S626_SET_CRB_LOADSRC_B(S626_GET_STD_LOADSRC(setup));
931 
932         /* Force IntSrc to Disabled if disable_int_src is asserted. */
933         if (!disable_int_src)
934                 crb |= S626_SET_CRB_INTSRC_B(S626_GET_STD_INTSRC(setup));
935 
936         /* Populate all mode-dependent attributes of CRA & CRB images. */
937         clkpol = S626_GET_STD_CLKPOL(setup);
938         switch (S626_GET_STD_ENCMODE(setup)) {
939         case S626_ENCMODE_TIMER:        /* Timer Mode: */
940                 /* CntSrcB<1> selects system clock */
941                 cntsrc = S626_CNTSRC_SYSCLK;
942                 /* with direction (CntSrcB<0>) obtained from ClkPol. */
943                 cntsrc |= clkpol;
944                 /* ClkPolB behaves as always-on clock enable. */
945                 clkpol = 1;
946                 /* ClkMultB must be 1x. */
947                 clkmult = S626_CLKMULT_1X;
948                 break;
949         case S626_ENCMODE_EXTENDER:     /* Extender Mode: */
950                 /* CntSrcB source is OverflowA (same as "timer") */
951                 cntsrc = S626_CNTSRC_SYSCLK;
952                 /* with direction obtained from ClkPol. */
953                 cntsrc |= clkpol;
954                 /* ClkPolB controls IndexB -- always set to active. */
955                 clkpol = 1;
956                 /* ClkMultB selects OverflowA as the clock source. */
957                 clkmult = S626_CLKMULT_SPECIAL;
958                 break;
959         default:                /* Counter Mode: */
960                 /* Select ENC_C and ENC_D as clock/direction inputs. */
961                 cntsrc = S626_CNTSRC_ENCODER;
962                 /* ClkPol is passed through. */
963                 /* Force ClkMult to x1 if not legal, otherwise pass through. */
964                 clkmult = S626_GET_STD_CLKMULT(setup);
965                 if (clkmult == S626_CLKMULT_SPECIAL)
966                         clkmult = S626_CLKMULT_1X;
967                 break;
968         }
969         cra |= S626_SET_CRA_CNTSRC_B(cntsrc);
970         crb |= S626_SET_CRB_CLKPOL_B(clkpol) | S626_SET_CRB_CLKMULT_B(clkmult);
971 
972         /*
973          * Force positive index polarity if IndxSrc is software-driven only,
974          * otherwise pass it through.
975          */
976         if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
977                 crb |= S626_SET_CRB_INDXPOL_B(S626_GET_STD_INDXPOL(setup));
978 
979         /*
980          * If IntSrc has been forced to Disabled, update the MISC2 interrupt
981          * enable mask to indicate the counter interrupt is disabled.
982          */
983         if (disable_int_src)
984                 devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
985                                                 S626_INDXMASK(chan));
986 
987         /*
988          * While retaining CounterA and LatchSrc configurations, program the
989          * new counter operating mode.
990          */
991         s626_debi_replace(dev, S626_LP_CRA(chan),
992                           ~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B), cra);
993         s626_debi_replace(dev, S626_LP_CRB(chan),
994                           S626_CRBMSK_CLKENAB_A | S626_CRBMSK_LATCHSRC, crb);
995 }
996 
997 static void s626_set_mode(struct comedi_device *dev,
998                           unsigned int chan,
999                           uint16_t setup, uint16_t disable_int_src)
1000 {
1001         if (chan < 3)
1002                 s626_set_mode_a(dev, chan, setup, disable_int_src);
1003         else
1004                 s626_set_mode_b(dev, chan, setup, disable_int_src);
1005 }
1006 
1007 /*
1008  * Return/set a counter's enable.  enab: 0=always enabled, 1=enabled by index.
1009  */
1010 static void s626_set_enable(struct comedi_device *dev,
1011                             unsigned int chan, uint16_t enab)
1012 {
1013         unsigned int mask = S626_CRBMSK_INTCTRL;
1014         unsigned int set;
1015 
1016         if (chan < 3) {
1017                 mask |= S626_CRBMSK_CLKENAB_A;
1018                 set = S626_SET_CRB_CLKENAB_A(enab);
1019         } else {
1020                 mask |= S626_CRBMSK_CLKENAB_B;
1021                 set = S626_SET_CRB_CLKENAB_B(enab);
1022         }
1023         s626_debi_replace(dev, S626_LP_CRB(chan), ~mask, set);
1024 }
1025 
1026 #ifdef unused
1027 static uint16_t s626_get_enable(struct comedi_device *dev,
1028                                 unsigned int chan)
1029 {
1030         uint16_t crb = s626_debi_read(dev, S626_LP_CRB(chan));
1031 
1032         return (chan < 3) ? S626_GET_CRB_CLKENAB_A(crb)
1033                           : S626_GET_CRB_CLKENAB_B(crb);
1034 }
1035 #endif
1036 
1037 #ifdef unused
1038 static uint16_t s626_get_latch_source(struct comedi_device *dev,
1039                                       unsigned int chan)
1040 {
1041         return S626_GET_CRB_LATCHSRC(s626_debi_read(dev, S626_LP_CRB(chan)));
1042 }
1043 #endif
1044 
1045 /*
1046  * Return/set the event that will trigger transfer of the preload
1047  * register into the counter.  0=ThisCntr_Index, 1=ThisCntr_Overflow,
1048  * 2=OverflowA (B counters only), 3=disabled.
1049  */
1050 static void s626_set_load_trig(struct comedi_device *dev,
1051                                unsigned int chan, uint16_t trig)
1052 {
1053         uint16_t reg;
1054         uint16_t mask;
1055         uint16_t set;
1056 
1057         if (chan < 3) {
1058                 reg = S626_LP_CRA(chan);
1059                 mask = S626_CRAMSK_LOADSRC_A;
1060                 set = S626_SET_CRA_LOADSRC_A(trig);
1061         } else {
1062                 reg = S626_LP_CRB(chan);
1063                 mask = S626_CRBMSK_LOADSRC_B | S626_CRBMSK_INTCTRL;
1064                 set = S626_SET_CRB_LOADSRC_B(trig);
1065         }
1066         s626_debi_replace(dev, reg, ~mask, set);
1067 }
1068 
1069 #ifdef unused
1070 static uint16_t s626_get_load_trig(struct comedi_device *dev,
1071                                    unsigned int chan)
1072 {
1073         if (chan < 3)
1074                 return S626_GET_CRA_LOADSRC_A(s626_debi_read(dev,
1075                                                         S626_LP_CRA(chan)));
1076         else
1077                 return S626_GET_CRB_LOADSRC_B(s626_debi_read(dev,
1078                                                         S626_LP_CRB(chan)));
1079 }
1080 #endif
1081 
1082 /*
1083  * Return/set counter interrupt source and clear any captured
1084  * index/overflow events.  int_source: 0=Disabled, 1=OverflowOnly,
1085  * 2=IndexOnly, 3=IndexAndOverflow.
1086  */
1087 static void s626_set_int_src(struct comedi_device *dev,
1088                              unsigned int chan, uint16_t int_source)
1089 {
1090         struct s626_private *devpriv = dev->private;
1091         uint16_t cra_reg = S626_LP_CRA(chan);
1092         uint16_t crb_reg = S626_LP_CRB(chan);
1093 
1094         if (chan < 3) {
1095                 /* Reset any pending counter overflow or index captures */
1096                 s626_debi_replace(dev, crb_reg, ~S626_CRBMSK_INTCTRL,
1097                                   S626_SET_CRB_INTRESETCMD(1) |
1098                                   S626_SET_CRB_INTRESET_A(1));
1099 
1100                 /* Program counter interrupt source */
1101                 s626_debi_replace(dev, cra_reg, ~S626_CRAMSK_INTSRC_A,
1102                                   S626_SET_CRA_INTSRC_A(int_source));
1103         } else {
1104                 uint16_t crb;
1105 
1106                 /* Cache writeable CRB register image */
1107                 crb = s626_debi_read(dev, crb_reg);
1108                 crb &= ~S626_CRBMSK_INTCTRL;
1109 
1110                 /* Reset any pending counter overflow or index captures */
1111                 s626_debi_write(dev, crb_reg,
1112                                 crb | S626_SET_CRB_INTRESETCMD(1) |
1113                                 S626_SET_CRB_INTRESET_B(1));
1114 
1115                 /* Program counter interrupt source */
1116                 s626_debi_write(dev, crb_reg,
1117                                 (crb & ~S626_CRBMSK_INTSRC_B) |
1118                                 S626_SET_CRB_INTSRC_B(int_source));
1119         }
1120 
1121         /* Update MISC2 interrupt enable mask. */
1122         devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
1123                                         S626_INDXMASK(chan));
1124         switch (int_source) {
1125         case 0:
1126         default:
1127                 break;
1128         case 1:
1129                 devpriv->counter_int_enabs |= S626_OVERMASK(chan);
1130                 break;
1131         case 2:
1132                 devpriv->counter_int_enabs |= S626_INDXMASK(chan);
1133                 break;
1134         case 3:
1135                 devpriv->counter_int_enabs |= (S626_OVERMASK(chan) |
1136                                                S626_INDXMASK(chan));
1137                 break;
1138         }
1139 }
1140 
1141 #ifdef unused
1142 static uint16_t s626_get_int_src(struct comedi_device *dev,
1143                                  unsigned int chan)
1144 {
1145         if (chan < 3)
1146                 return S626_GET_CRA_INTSRC_A(s626_debi_read(dev,
1147                                                         S626_LP_CRA(chan)));
1148         else
1149                 return S626_GET_CRB_INTSRC_B(s626_debi_read(dev,
1150                                                         S626_LP_CRB(chan)));
1151 }
1152 #endif
1153 
1154 #ifdef unused
1155 /*
1156  * Return/set the clock multiplier.
1157  */
1158 static void s626_set_clk_mult(struct comedi_device *dev,
1159                               unsigned int chan, uint16_t value)
1160 {
1161         uint16_t mode;
1162 
1163         mode = s626_get_mode(dev, chan);
1164         mode &= ~S626_STDMSK_CLKMULT;
1165         mode |= S626_SET_STD_CLKMULT(value);
1166 
1167         s626_set_mode(dev, chan, mode, false);
1168 }
1169 
1170 static uint16_t s626_get_clk_mult(struct comedi_device *dev,
1171                                   unsigned int chan)
1172 {
1173         return S626_GET_STD_CLKMULT(s626_get_mode(dev, chan));
1174 }
1175 
1176 /*
1177  * Return/set the clock polarity.
1178  */
1179 static void s626_set_clk_pol(struct comedi_device *dev,
1180                              unsigned int chan, uint16_t value)
1181 {
1182         uint16_t mode;
1183 
1184         mode = s626_get_mode(dev, chan);
1185         mode &= ~S626_STDMSK_CLKPOL;
1186         mode |= S626_SET_STD_CLKPOL(value);
1187 
1188         s626_set_mode(dev, chan, mode, false);
1189 }
1190 
1191 static uint16_t s626_get_clk_pol(struct comedi_device *dev,
1192                                  unsigned int chan)
1193 {
1194         return S626_GET_STD_CLKPOL(s626_get_mode(dev, chan));
1195 }
1196 
1197 /*
1198  * Return/set the encoder mode.
1199  */
1200 static void s626_set_enc_mode(struct comedi_device *dev,
1201                               unsigned int chan, uint16_t value)
1202 {
1203         uint16_t mode;
1204 
1205         mode = s626_get_mode(dev, chan);
1206         mode &= ~S626_STDMSK_ENCMODE;
1207         mode |= S626_SET_STD_ENCMODE(value);
1208 
1209         s626_set_mode(dev, chan, mode, false);
1210 }
1211 
1212 static uint16_t s626_get_enc_mode(struct comedi_device *dev,
1213                                   unsigned int chan)
1214 {
1215         return S626_GET_STD_ENCMODE(s626_get_mode(dev, chan));
1216 }
1217 
1218 /*
1219  * Return/set the index polarity.
1220  */
1221 static void s626_set_index_pol(struct comedi_device *dev,
1222                                unsigned int chan, uint16_t value)
1223 {
1224         uint16_t mode;
1225 
1226         mode = s626_get_mode(dev, chan);
1227         mode &= ~S626_STDMSK_INDXPOL;
1228         mode |= S626_SET_STD_INDXPOL(value != 0);
1229 
1230         s626_set_mode(dev, chan, mode, false);
1231 }
1232 
1233 static uint16_t s626_get_index_pol(struct comedi_device *dev,
1234                                    unsigned int chan)
1235 {
1236         return S626_GET_STD_INDXPOL(s626_get_mode(dev, chan));
1237 }
1238 
1239 /*
1240  * Return/set the index source.
1241  */
1242 static void s626_set_index_src(struct comedi_device *dev,
1243                                unsigned int chan, uint16_t value)
1244 {
1245         uint16_t mode;
1246 
1247         mode = s626_get_mode(dev, chan);
1248         mode &= ~S626_STDMSK_INDXSRC;
1249         mode |= S626_SET_STD_INDXSRC(value != 0);
1250 
1251         s626_set_mode(dev, chan, mode, false);
1252 }
1253 
1254 static uint16_t s626_get_index_src(struct comedi_device *dev,
1255                                    unsigned int chan)
1256 {
1257         return S626_GET_STD_INDXSRC(s626_get_mode(dev, chan));
1258 }
1259 #endif
1260 
1261 /*
1262  * Generate an index pulse.
1263  */
1264 static void s626_pulse_index(struct comedi_device *dev,
1265                              unsigned int chan)
1266 {
1267         if (chan < 3) {
1268                 uint16_t cra;
1269 
1270                 cra = s626_debi_read(dev, S626_LP_CRA(chan));
1271 
1272                 /* Pulse index */
1273                 s626_debi_write(dev, S626_LP_CRA(chan),
1274                                 (cra ^ S626_CRAMSK_INDXPOL_A));
1275                 s626_debi_write(dev, S626_LP_CRA(chan), cra);
1276         } else {
1277                 uint16_t crb;
1278 
1279                 crb = s626_debi_read(dev, S626_LP_CRB(chan));
1280                 crb &= ~S626_CRBMSK_INTCTRL;
1281 
1282                 /* Pulse index */
1283                 s626_debi_write(dev, S626_LP_CRB(chan),
1284                                 (crb ^ S626_CRBMSK_INDXPOL_B));
1285                 s626_debi_write(dev, S626_LP_CRB(chan), crb);
1286         }
1287 }
1288 
1289 static unsigned int s626_ai_reg_to_uint(unsigned int data)
1290 {
1291         return ((data >> 18) & 0x3fff) ^ 0x2000;
1292 }
1293 
1294 static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
1295 {
1296         unsigned int group = chan / 16;
1297         unsigned int mask = 1 << (chan - (16 * group));
1298         unsigned int status;
1299 
1300         /* set channel to capture positive edge */
1301         status = s626_debi_read(dev, S626_LP_RDEDGSEL(group));
1302         s626_debi_write(dev, S626_LP_WREDGSEL(group), mask | status);
1303 
1304         /* enable interrupt on selected channel */
1305         status = s626_debi_read(dev, S626_LP_RDINTSEL(group));
1306         s626_debi_write(dev, S626_LP_WRINTSEL(group), mask | status);
1307 
1308         /* enable edge capture write command */
1309         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_EDCAP);
1310 
1311         /* enable edge capture on selected channel */
1312         status = s626_debi_read(dev, S626_LP_RDCAPSEL(group));
1313         s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask | status);
1314 
1315         return 0;
1316 }
1317 
1318 static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
1319                               unsigned int mask)
1320 {
1321         /* disable edge capture write command */
1322         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1323 
1324         /* enable edge capture on selected channel */
1325         s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask);
1326 
1327         return 0;
1328 }
1329 
1330 static int s626_dio_clear_irq(struct comedi_device *dev)
1331 {
1332         unsigned int group;
1333 
1334         /* disable edge capture write command */
1335         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1336 
1337         /* clear all dio pending events and interrupt */
1338         for (group = 0; group < S626_DIO_BANKS; group++)
1339                 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
1340 
1341         return 0;
1342 }
1343 
1344 static void s626_handle_dio_interrupt(struct comedi_device *dev,
1345                                       uint16_t irqbit, uint8_t group)
1346 {
1347         struct s626_private *devpriv = dev->private;
1348         struct comedi_subdevice *s = dev->read_subdev;
1349         struct comedi_cmd *cmd = &s->async->cmd;
1350 
1351         s626_dio_reset_irq(dev, group, irqbit);
1352 
1353         if (devpriv->ai_cmd_running) {
1354                 /* check if interrupt is an ai acquisition start trigger */
1355                 if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 &&
1356                     cmd->start_src == TRIG_EXT) {
1357                         /* Start executing the RPS program */
1358                         s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1359 
1360                         if (cmd->scan_begin_src == TRIG_EXT)
1361                                 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1362                 }
1363                 if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 &&
1364                     cmd->scan_begin_src == TRIG_EXT) {
1365                         /* Trigger ADC scan loop start */
1366                         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1367 
1368                         if (cmd->convert_src == TRIG_EXT) {
1369                                 devpriv->ai_convert_count = cmd->chanlist_len;
1370 
1371                                 s626_dio_set_irq(dev, cmd->convert_arg);
1372                         }
1373 
1374                         if (cmd->convert_src == TRIG_TIMER) {
1375                                 devpriv->ai_convert_count = cmd->chanlist_len;
1376                                 s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS);
1377                         }
1378                 }
1379                 if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 &&
1380                     cmd->convert_src == TRIG_EXT) {
1381                         /* Trigger ADC scan loop start */
1382                         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1383 
1384                         devpriv->ai_convert_count--;
1385                         if (devpriv->ai_convert_count > 0)
1386                                 s626_dio_set_irq(dev, cmd->convert_arg);
1387                 }
1388         }
1389 }
1390 
1391 static void s626_check_dio_interrupts(struct comedi_device *dev)
1392 {
1393         uint16_t irqbit;
1394         uint8_t group;
1395 
1396         for (group = 0; group < S626_DIO_BANKS; group++) {
1397                 /* read interrupt type */
1398                 irqbit = s626_debi_read(dev, S626_LP_RDCAPFLG(group));
1399 
1400                 /* check if interrupt is generated from dio channels */
1401                 if (irqbit) {
1402                         s626_handle_dio_interrupt(dev, irqbit, group);
1403                         return;
1404                 }
1405         }
1406 }
1407 
1408 static void s626_check_counter_interrupts(struct comedi_device *dev)
1409 {
1410         struct s626_private *devpriv = dev->private;
1411         struct comedi_subdevice *s = dev->read_subdev;
1412         struct comedi_async *async = s->async;
1413         struct comedi_cmd *cmd = &async->cmd;
1414         uint16_t irqbit;
1415 
1416         /* read interrupt type */
1417         irqbit = s626_debi_read(dev, S626_LP_RDMISC2);
1418 
1419         /* check interrupt on counters */
1420         if (irqbit & S626_IRQ_COINT1A) {
1421                 /* clear interrupt capture flag */
1422                 s626_reset_cap_flags(dev, 0);
1423         }
1424         if (irqbit & S626_IRQ_COINT2A) {
1425                 /* clear interrupt capture flag */
1426                 s626_reset_cap_flags(dev, 1);
1427         }
1428         if (irqbit & S626_IRQ_COINT3A) {
1429                 /* clear interrupt capture flag */
1430                 s626_reset_cap_flags(dev, 2);
1431         }
1432         if (irqbit & S626_IRQ_COINT1B) {
1433                 /* clear interrupt capture flag */
1434                 s626_reset_cap_flags(dev, 3);
1435         }
1436         if (irqbit & S626_IRQ_COINT2B) {
1437                 /* clear interrupt capture flag */
1438                 s626_reset_cap_flags(dev, 4);
1439 
1440                 if (devpriv->ai_convert_count > 0) {
1441                         devpriv->ai_convert_count--;
1442                         if (devpriv->ai_convert_count == 0)
1443                                 s626_set_enable(dev, 4, S626_CLKENAB_INDEX);
1444 
1445                         if (cmd->convert_src == TRIG_TIMER) {
1446                                 /* Trigger ADC scan loop start */
1447                                 s626_mc_enable(dev, S626_MC2_ADC_RPS,
1448                                                S626_P_MC2);
1449                         }
1450                 }
1451         }
1452         if (irqbit & S626_IRQ_COINT3B) {
1453                 /* clear interrupt capture flag */
1454                 s626_reset_cap_flags(dev, 5);
1455 
1456                 if (cmd->scan_begin_src == TRIG_TIMER) {
1457                         /* Trigger ADC scan loop start */
1458                         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1459                 }
1460 
1461                 if (cmd->convert_src == TRIG_TIMER) {
1462                         devpriv->ai_convert_count = cmd->chanlist_len;
1463                         s626_set_enable(dev, 4, S626_CLKENAB_ALWAYS);
1464                 }
1465         }
1466 }
1467 
1468 static bool s626_handle_eos_interrupt(struct comedi_device *dev)
1469 {
1470         struct s626_private *devpriv = dev->private;
1471         struct comedi_subdevice *s = dev->read_subdev;
1472         struct comedi_async *async = s->async;
1473         struct comedi_cmd *cmd = &async->cmd;
1474         /*
1475          * Init ptr to DMA buffer that holds new ADC data.  We skip the
1476          * first uint16_t in the buffer because it contains junk data
1477          * from the final ADC of the previous poll list scan.
1478          */
1479         uint32_t *readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1480         int i;
1481 
1482         /* get the data and hand it over to comedi */
1483         for (i = 0; i < cmd->chanlist_len; i++) {
1484                 unsigned short tempdata;
1485 
1486                 /*
1487                  * Convert ADC data to 16-bit integer values and copy
1488                  * to application buffer.
1489                  */
1490                 tempdata = s626_ai_reg_to_uint(*readaddr);
1491                 readaddr++;
1492 
1493                 comedi_buf_write_samples(s, &tempdata, 1);
1494         }
1495 
1496         if (cmd->stop_src == TRIG_COUNT && async->scans_done >= cmd->stop_arg)
1497                 async->events |= COMEDI_CB_EOA;
1498 
1499         if (async->events & COMEDI_CB_CANCEL_MASK)
1500                 devpriv->ai_cmd_running = 0;
1501 
1502         if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT)
1503                 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1504 
1505         comedi_handle_events(dev, s);
1506 
1507         return !devpriv->ai_cmd_running;
1508 }
1509 
1510 static irqreturn_t s626_irq_handler(int irq, void *d)
1511 {
1512         struct comedi_device *dev = d;
1513         unsigned long flags;
1514         uint32_t irqtype, irqstatus;
1515 
1516         if (!dev->attached)
1517                 return IRQ_NONE;
1518         /* lock to avoid race with comedi_poll */
1519         spin_lock_irqsave(&dev->spinlock, flags);
1520 
1521         /* save interrupt enable register state */
1522         irqstatus = readl(dev->mmio + S626_P_IER);
1523 
1524         /* read interrupt type */
1525         irqtype = readl(dev->mmio + S626_P_ISR);
1526 
1527         /* disable master interrupt */
1528         writel(0, dev->mmio + S626_P_IER);
1529 
1530         /* clear interrupt */
1531         writel(irqtype, dev->mmio + S626_P_ISR);
1532 
1533         switch (irqtype) {
1534         case S626_IRQ_RPS1:     /* end_of_scan occurs */
1535                 if (s626_handle_eos_interrupt(dev))
1536                         irqstatus = 0;
1537                 break;
1538         case S626_IRQ_GPIO3:    /* check dio and counter interrupt */
1539                 /* s626_dio_clear_irq(dev); */
1540                 s626_check_dio_interrupts(dev);
1541                 s626_check_counter_interrupts(dev);
1542                 break;
1543         }
1544 
1545         /* enable interrupt */
1546         writel(irqstatus, dev->mmio + S626_P_IER);
1547 
1548         spin_unlock_irqrestore(&dev->spinlock, flags);
1549         return IRQ_HANDLED;
1550 }
1551 
1552 /*
1553  * This function builds the RPS program for hardware driven acquisition.
1554  */
1555 static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl)
1556 {
1557         struct s626_private *devpriv = dev->private;
1558         struct comedi_subdevice *s = dev->read_subdev;
1559         struct comedi_cmd *cmd = &s->async->cmd;
1560         uint32_t *rps;
1561         uint32_t jmp_adrs;
1562         uint16_t i;
1563         uint16_t n;
1564         uint32_t local_ppl;
1565 
1566         /* Stop RPS program in case it is currently running */
1567         s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1568 
1569         /* Set starting logical address to write RPS commands. */
1570         rps = (uint32_t *)devpriv->rps_buf.logical_base;
1571 
1572         /* Initialize RPS instruction pointer */
1573         writel((uint32_t)devpriv->rps_buf.physical_base,
1574                dev->mmio + S626_P_RPSADDR1);
1575 
1576         /* Construct RPS program in rps_buf DMA buffer */
1577         if (cmd->scan_begin_src != TRIG_FOLLOW) {
1578                 /* Wait for Start trigger. */
1579                 *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1580                 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1581         }
1582 
1583         /*
1584          * SAA7146 BUG WORKAROUND Do a dummy DEBI Write.  This is necessary
1585          * because the first RPS DEBI Write following a non-RPS DEBI write
1586          * seems to always fail.  If we don't do this dummy write, the ADC
1587          * gain might not be set to the value required for the first slot in
1588          * the poll list; the ADC gain would instead remain unchanged from
1589          * the previously programmed value.
1590          */
1591         /* Write DEBI Write command and address to shadow RAM. */
1592         *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1593         *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1594         *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1595         /* Write DEBI immediate data  to shadow RAM: */
1596         *rps++ = S626_GSEL_BIPOLAR5V;   /* arbitrary immediate data  value. */
1597         *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1598         /* Reset "shadow RAM  uploaded" flag. */
1599         /* Invoke shadow RAM upload. */
1600         *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1601         /* Wait for shadow upload to finish. */
1602         *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1603 
1604         /*
1605          * Digitize all slots in the poll list. This is implemented as a
1606          * for loop to limit the slot count to 16 in case the application
1607          * forgot to set the S626_EOPL flag in the final slot.
1608          */
1609         for (devpriv->adc_items = 0; devpriv->adc_items < 16;
1610              devpriv->adc_items++) {
1611                 /*
1612                  * Convert application's poll list item to private board class
1613                  * format.  Each app poll list item is an uint8_t with form
1614                  * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
1615                  * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
1616                  */
1617                 local_ppl = (*ppl << 8) | (*ppl & 0x10 ? S626_GSEL_BIPOLAR5V :
1618                                            S626_GSEL_BIPOLAR10V);
1619 
1620                 /* Switch ADC analog gain. */
1621                 /* Write DEBI command and address to shadow RAM. */
1622                 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1623                 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1624                 /* Write DEBI immediate data to shadow RAM. */
1625                 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1626                 *rps++ = local_ppl;
1627                 /* Reset "shadow RAM uploaded" flag. */
1628                 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1629                 /* Invoke shadow RAM upload. */
1630                 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1631                 /* Wait for shadow upload to finish. */
1632                 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1633                 /* Select ADC analog input channel. */
1634                 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1635                 /* Write DEBI command and address to shadow RAM. */
1636                 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_ISEL;
1637                 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1638                 /* Write DEBI immediate data to shadow RAM. */
1639                 *rps++ = local_ppl;
1640                 /* Reset "shadow RAM uploaded" flag. */
1641                 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1642                 /* Invoke shadow RAM upload. */
1643                 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1644                 /* Wait for shadow upload to finish. */
1645                 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1646 
1647                 /*
1648                  * Delay at least 10 microseconds for analog input settling.
1649                  * Instead of padding with NOPs, we use S626_RPS_JUMP
1650                  * instructions here; this allows us to produce a longer delay
1651                  * than is possible with NOPs because each S626_RPS_JUMP
1652                  * flushes the RPS' instruction prefetch pipeline.
1653                  */
1654                 jmp_adrs =
1655                         (uint32_t)devpriv->rps_buf.physical_base +
1656                         (uint32_t)((unsigned long)rps -
1657                                    (unsigned long)devpriv->
1658                                                   rps_buf.logical_base);
1659                 for (i = 0; i < (10 * S626_RPSCLK_PER_US / 2); i++) {
1660                         jmp_adrs += 8;  /* Repeat to implement time delay: */
1661                         /* Jump to next RPS instruction. */
1662                         *rps++ = S626_RPS_JUMP;
1663                         *rps++ = jmp_adrs;
1664                 }
1665 
1666                 if (cmd->convert_src != TRIG_NOW) {
1667                         /* Wait for Start trigger. */
1668                         *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1669                         *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1670                 }
1671                 /* Start ADC by pulsing GPIO1. */
1672                 /* Begin ADC Start pulse. */
1673                 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1674                 *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1675                 *rps++ = S626_RPS_NOP;
1676                 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1677                 /* End ADC Start pulse. */
1678                 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1679                 *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1680                 /*
1681                  * Wait for ADC to complete (GPIO2 is asserted high when ADC not
1682                  * busy) and for data from previous conversion to shift into FB
1683                  * BUFFER 1 register.
1684                  */
1685                 /* Wait for ADC done. */
1686                 *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;
1687 
1688                 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
1689                 *rps++ = S626_RPS_STREG |
1690                          (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1691                 *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1692                          (devpriv->adc_items << 2);
1693 
1694                 /*
1695                  * If this slot's EndOfPollList flag is set, all channels have
1696                  * now been processed.
1697                  */
1698                 if (*ppl++ & S626_EOPL) {
1699                         devpriv->adc_items++; /* Adjust poll list item count. */
1700                         break;  /* Exit poll list processing loop. */
1701                 }
1702         }
1703 
1704         /*
1705          * VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US.  Allow the
1706          * ADC to stabilize for 2 microseconds before starting the final
1707          * (dummy) conversion.  This delay is necessary to allow sufficient
1708          * time between last conversion finished and the start of the dummy
1709          * conversion.  Without this delay, the last conversion's data value
1710          * is sometimes set to the previous conversion's data value.
1711          */
1712         for (n = 0; n < (2 * S626_RPSCLK_PER_US); n++)
1713                 *rps++ = S626_RPS_NOP;
1714 
1715         /*
1716          * Start a dummy conversion to cause the data from the last
1717          * conversion of interest to be shifted in.
1718          */
1719         /* Begin ADC Start pulse. */
1720         *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1721         *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1722         *rps++ = S626_RPS_NOP;
1723         /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1724         *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); /* End ADC Start pulse. */
1725         *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1726 
1727         /*
1728          * Wait for the data from the last conversion of interest to arrive
1729          * in FB BUFFER 1 register.
1730          */
1731         *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;       /* Wait for ADC done. */
1732 
1733         /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1734         *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1735         *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1736                  (devpriv->adc_items << 2);
1737 
1738         /* Indicate ADC scan loop is finished. */
1739         /* Signal ReadADC() that scan is done. */
1740         /* *rps++= S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; */
1741 
1742         /* invoke interrupt */
1743         if (devpriv->ai_cmd_running == 1)
1744                 *rps++ = S626_RPS_IRQ;
1745 
1746         /* Restart RPS program at its beginning. */
1747         *rps++ = S626_RPS_JUMP; /* Branch to start of RPS program. */
1748         *rps++ = (uint32_t)devpriv->rps_buf.physical_base;
1749 
1750         /* End of RPS program build */
1751 }
1752 
1753 #ifdef unused_code
1754 static int s626_ai_rinsn(struct comedi_device *dev,
1755                          struct comedi_subdevice *s,
1756                          struct comedi_insn *insn,
1757                          unsigned int *data)
1758 {
1759         struct s626_private *devpriv = dev->private;
1760         uint8_t i;
1761         int32_t *readaddr;
1762 
1763         /* Trigger ADC scan loop start */
1764         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1765 
1766         /* Wait until ADC scan loop is finished (RPS Signal 0 reset) */
1767         while (s626_mc_test(dev, S626_MC2_ADC_RPS, S626_P_MC2))
1768                 ;
1769 
1770         /*
1771          * Init ptr to DMA buffer that holds new ADC data.  We skip the
1772          * first uint16_t in the buffer because it contains junk data from
1773          * the final ADC of the previous poll list scan.
1774          */
1775         readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1776 
1777         /*
1778          * Convert ADC data to 16-bit integer values and
1779          * copy to application buffer.
1780          */
1781         for (i = 0; i < devpriv->adc_items; i++) {
1782                 *data = s626_ai_reg_to_uint(*readaddr++);
1783                 data++;
1784         }
1785 
1786         return i;
1787 }
1788 #endif
1789 
1790 static int s626_ai_eoc(struct comedi_device *dev,
1791                        struct comedi_subdevice *s,
1792                        struct comedi_insn *insn,
1793                        unsigned long context)
1794 {
1795         unsigned int status;
1796 
1797         status = readl(dev->mmio + S626_P_PSR);
1798         if (status & S626_PSR_GPIO2)
1799                 return 0;
1800         return -EBUSY;
1801 }
1802 
1803 static int s626_ai_insn_read(struct comedi_device *dev,
1804                              struct comedi_subdevice *s,
1805                              struct comedi_insn *insn,
1806                              unsigned int *data)
1807 {
1808         uint16_t chan = CR_CHAN(insn->chanspec);
1809         uint16_t range = CR_RANGE(insn->chanspec);
1810         uint16_t adc_spec = 0;
1811         uint32_t gpio_image;
1812         uint32_t tmp;
1813         int ret;
1814         int n;
1815 
1816         /*
1817          * Convert application's ADC specification into form
1818          *  appropriate for register programming.
1819          */
1820         if (range == 0)
1821                 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR5V);
1822         else
1823                 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR10V);
1824 
1825         /* Switch ADC analog gain. */
1826         s626_debi_write(dev, S626_LP_GSEL, adc_spec);   /* Set gain. */
1827 
1828         /* Select ADC analog input channel. */
1829         s626_debi_write(dev, S626_LP_ISEL, adc_spec);   /* Select channel. */
1830 
1831         for (n = 0; n < insn->n; n++) {
1832                 /* Delay 10 microseconds for analog input settling. */
1833                 udelay(10);
1834 
1835                 /* Start ADC by pulsing GPIO1 low */
1836                 gpio_image = readl(dev->mmio + S626_P_GPIO);
1837                 /* Assert ADC Start command */
1838                 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1839                 /* and stretch it out */
1840                 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1841                 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1842                 /* Negate ADC Start command */
1843                 writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1844 
1845                 /*
1846                  * Wait for ADC to complete (GPIO2 is asserted high when
1847                  * ADC not busy) and for data from previous conversion to
1848                  * shift into FB BUFFER 1 register.
1849                  */
1850 
1851                 /* Wait for ADC done */
1852                 ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
1853                 if (ret)
1854                         return ret;
1855 
1856                 /* Fetch ADC data */
1857                 if (n != 0) {
1858                         tmp = readl(dev->mmio + S626_P_FB_BUFFER1);
1859                         data[n - 1] = s626_ai_reg_to_uint(tmp);
1860                 }
1861 
1862                 /*
1863                  * Allow the ADC to stabilize for 4 microseconds before
1864                  * starting the next (final) conversion.  This delay is
1865                  * necessary to allow sufficient time between last
1866                  * conversion finished and the start of the next
1867                  * conversion.  Without this delay, the last conversion's
1868                  * data value is sometimes set to the previous
1869                  * conversion's data value.
1870                  */
1871                 udelay(4);
1872         }
1873 
1874         /*
1875          * Start a dummy conversion to cause the data from the
1876          * previous conversion to be shifted in.
1877          */
1878         gpio_image = readl(dev->mmio + S626_P_GPIO);
1879         /* Assert ADC Start command */
1880         writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1881         /* and stretch it out */
1882         writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1883         writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1884         /* Negate ADC Start command */
1885         writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1886 
1887         /* Wait for the data to arrive in FB BUFFER 1 register. */
1888 
1889         /* Wait for ADC done */
1890         ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
1891         if (ret)
1892                 return ret;
1893 
1894         /* Fetch ADC data from audio interface's input shift register. */
1895 
1896         /* Fetch ADC data */
1897         if (n != 0) {
1898                 tmp = readl(dev->mmio + S626_P_FB_BUFFER1);
1899                 data[n - 1] = s626_ai_reg_to_uint(tmp);
1900         }
1901 
1902         return n;
1903 }
1904 
1905 static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd)
1906 {
1907         int n;
1908 
1909         for (n = 0; n < cmd->chanlist_len; n++) {
1910                 if (CR_RANGE(cmd->chanlist[n]) == 0)
1911                         ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_5V;
1912                 else
1913                         ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_10V;
1914         }
1915         if (n != 0)
1916                 ppl[n - 1] |= S626_EOPL;
1917 
1918         return n;
1919 }
1920 
1921 static int s626_ai_inttrig(struct comedi_device *dev,
1922                            struct comedi_subdevice *s,
1923                            unsigned int trig_num)
1924 {
1925         struct comedi_cmd *cmd = &s->async->cmd;
1926 
1927         if (trig_num != cmd->start_arg)
1928                 return -EINVAL;
1929 
1930         /* Start executing the RPS program */
1931         s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1932 
1933         s->async->inttrig = NULL;
1934 
1935         return 1;
1936 }
1937 
1938 /*
1939  * This function doesn't require a particular form, this is just what
1940  * happens to be used in some of the drivers.  It should convert ns
1941  * nanoseconds to a counter value suitable for programming the device.
1942  * Also, it should adjust ns so that it cooresponds to the actual time
1943  * that the device will use.
1944  */
1945 static int s626_ns_to_timer(unsigned int *nanosec, unsigned int flags)
1946 {
1947         int divider, base;
1948 
1949         base = 500;             /* 2MHz internal clock */
1950 
1951         switch (flags & CMDF_ROUND_MASK) {
1952         case CMDF_ROUND_NEAREST:
1953         default:
1954                 divider = DIV_ROUND_CLOSEST(*nanosec, base);
1955                 break;
1956         case CMDF_ROUND_DOWN:
1957                 divider = (*nanosec) / base;
1958                 break;
1959         case CMDF_ROUND_UP:
1960                 divider = DIV_ROUND_UP(*nanosec, base);
1961                 break;
1962         }
1963 
1964         *nanosec = base * divider;
1965         return divider - 1;
1966 }
1967 
1968 static void s626_timer_load(struct comedi_device *dev,
1969                             unsigned int chan, int tick)
1970 {
1971         uint16_t setup =
1972                 /* Preload upon index. */
1973                 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
1974                 /* Disable hardware index. */
1975                 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
1976                 /* Operating mode is Timer. */
1977                 S626_SET_STD_ENCMODE(S626_ENCMODE_TIMER) |
1978                 /* Count direction is Down. */
1979                 S626_SET_STD_CLKPOL(S626_CNTDIR_DOWN) |
1980                 /* Clock multiplier is 1x. */
1981                 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
1982                 /* Enabled by index */
1983                 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
1984         uint16_t value_latchsrc = S626_LATCHSRC_A_INDXA;
1985         /* uint16_t enab = S626_CLKENAB_ALWAYS; */
1986 
1987         s626_set_mode(dev, chan, setup, false);
1988 
1989         /* Set the preload register */
1990         s626_preload(dev, chan, tick);
1991 
1992         /*
1993          * Software index pulse forces the preload register to load
1994          * into the counter
1995          */
1996         s626_set_load_trig(dev, chan, 0);
1997         s626_pulse_index(dev, chan);
1998 
1999         /* set reload on counter overflow */
2000         s626_set_load_trig(dev, chan, 1);
2001 
2002         /* set interrupt on overflow */
2003         s626_set_int_src(dev, chan, S626_INTSRC_OVER);
2004 
2005         s626_set_latch_source(dev, chan, value_latchsrc);
2006         /* s626_set_enable(dev, chan, (uint16_t)(enab != 0)); */
2007 }
2008 
2009 /* TO COMPLETE  */
2010 static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2011 {
2012         struct s626_private *devpriv = dev->private;
2013         uint8_t ppl[16];
2014         struct comedi_cmd *cmd = &s->async->cmd;
2015         int tick;
2016 
2017         if (devpriv->ai_cmd_running) {
2018                 dev_err(dev->class_dev,
2019                         "s626_ai_cmd: Another ai_cmd is running\n");
2020                 return -EBUSY;
2021         }
2022         /* disable interrupt */
2023         writel(0, dev->mmio + S626_P_IER);
2024 
2025         /* clear interrupt request */
2026         writel(S626_IRQ_RPS1 | S626_IRQ_GPIO3, dev->mmio + S626_P_ISR);
2027 
2028         /* clear any pending interrupt */
2029         s626_dio_clear_irq(dev);
2030         /* s626_enc_clear_irq(dev); */
2031 
2032         /* reset ai_cmd_running flag */
2033         devpriv->ai_cmd_running = 0;
2034 
2035         s626_ai_load_polllist(ppl, cmd);
2036         devpriv->ai_cmd_running = 1;
2037         devpriv->ai_convert_count = 0;
2038 
2039         switch (cmd->scan_begin_src) {
2040         case TRIG_FOLLOW:
2041                 break;
2042         case TRIG_TIMER:
2043                 /*
2044                  * set a counter to generate adc trigger at scan_begin_arg
2045                  * interval
2046                  */
2047                 tick = s626_ns_to_timer(&cmd->scan_begin_arg, cmd->flags);
2048 
2049                 /* load timer value and enable interrupt */
2050                 s626_timer_load(dev, 5, tick);
2051                 s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS);
2052                 break;
2053         case TRIG_EXT:
2054                 /* set the digital line and interrupt for scan trigger */
2055                 if (cmd->start_src != TRIG_EXT)
2056                         s626_dio_set_irq(dev, cmd->scan_begin_arg);
2057                 break;
2058         }
2059 
2060         switch (cmd->convert_src) {
2061         case TRIG_NOW:
2062                 break;
2063         case TRIG_TIMER:
2064                 /*
2065                  * set a counter to generate adc trigger at convert_arg
2066                  * interval
2067                  */
2068                 tick = s626_ns_to_timer(&cmd->convert_arg, cmd->flags);
2069 
2070                 /* load timer value and enable interrupt */
2071                 s626_timer_load(dev, 4, tick);
2072                 s626_set_enable(dev, 4, S626_CLKENAB_INDEX);
2073                 break;
2074         case TRIG_EXT:
2075                 /* set the digital line and interrupt for convert trigger */
2076                 if (cmd->scan_begin_src != TRIG_EXT &&
2077                     cmd->start_src == TRIG_EXT)
2078                         s626_dio_set_irq(dev, cmd->convert_arg);
2079                 break;
2080         }
2081 
2082         s626_reset_adc(dev, ppl);
2083 
2084         switch (cmd->start_src) {
2085         case TRIG_NOW:
2086                 /* Trigger ADC scan loop start */
2087                 /* s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); */
2088 
2089                 /* Start executing the RPS program */
2090                 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
2091                 s->async->inttrig = NULL;
2092                 break;
2093         case TRIG_EXT:
2094                 /* configure DIO channel for acquisition trigger */
2095                 s626_dio_set_irq(dev, cmd->start_arg);
2096                 s->async->inttrig = NULL;
2097                 break;
2098         case TRIG_INT:
2099                 s->async->inttrig = s626_ai_inttrig;
2100                 break;
2101         }
2102 
2103         /* enable interrupt */
2104         writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, dev->mmio + S626_P_IER);
2105 
2106         return 0;
2107 }
2108 
2109 static int s626_ai_cmdtest(struct comedi_device *dev,
2110                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
2111 {
2112         int err = 0;
2113         unsigned int arg;
2114 
2115         /* Step 1 : check if triggers are trivially valid */
2116 
2117         err |= comedi_check_trigger_src(&cmd->start_src,
2118                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2119         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2120                                         TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW);
2121         err |= comedi_check_trigger_src(&cmd->convert_src,
2122                                         TRIG_TIMER | TRIG_EXT | TRIG_NOW);
2123         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2124         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2125 
2126         if (err)
2127                 return 1;
2128 
2129         /* Step 2a : make sure trigger sources are unique */
2130 
2131         err |= comedi_check_trigger_is_unique(cmd->start_src);
2132         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2133         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2134         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2135 
2136         /* Step 2b : and mutually compatible */
2137 
2138         if (err)
2139                 return 2;
2140 
2141         /* Step 3: check if arguments are trivially valid */
2142 
2143         switch (cmd->start_src) {
2144         case TRIG_NOW:
2145         case TRIG_INT:
2146                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2147                 break;
2148         case TRIG_EXT:
2149                 err |= comedi_check_trigger_arg_max(&cmd->start_arg, 39);
2150                 break;
2151         }
2152 
2153         if (cmd->scan_begin_src == TRIG_EXT)
2154                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 39);
2155         if (cmd->convert_src == TRIG_EXT)
2156                 err |= comedi_check_trigger_arg_max(&cmd->convert_arg, 39);
2157 
2158 #define S626_MAX_SPEED  200000  /* in nanoseconds */
2159 #define S626_MIN_SPEED  2000000000      /* in nanoseconds */
2160 
2161         if (cmd->scan_begin_src == TRIG_TIMER) {
2162                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2163                                                     S626_MAX_SPEED);
2164                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2165                                                     S626_MIN_SPEED);
2166         } else {
2167                 /*
2168                  * external trigger
2169                  * should be level/edge, hi/lo specification here
2170                  * should specify multiple external triggers
2171                  * err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 9);
2172                  */
2173         }
2174         if (cmd->convert_src == TRIG_TIMER) {
2175                 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2176                                                     S626_MAX_SPEED);
2177                 err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2178                                                     S626_MIN_SPEED);
2179         } else {
2180                 /*
2181                  * external trigger - see above
2182                  * err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 9);
2183                  */
2184         }
2185 
2186         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2187                                            cmd->chanlist_len);
2188 
2189         if (cmd->stop_src == TRIG_COUNT)
2190                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2191         else    /* TRIG_NONE */
2192                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2193 
2194         if (err)
2195                 return 3;
2196 
2197         /* step 4: fix up any arguments */
2198 
2199         if (cmd->scan_begin_src == TRIG_TIMER) {
2200                 arg = cmd->scan_begin_arg;
2201                 s626_ns_to_timer(&arg, cmd->flags);
2202                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
2203         }
2204 
2205         if (cmd->convert_src == TRIG_TIMER) {
2206                 arg = cmd->convert_arg;
2207                 s626_ns_to_timer(&arg, cmd->flags);
2208                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, arg);
2209 
2210                 if (cmd->scan_begin_src == TRIG_TIMER) {
2211                         arg = cmd->convert_arg * cmd->scan_end_arg;
2212                         err |= comedi_check_trigger_arg_min(&cmd->
2213                                                             scan_begin_arg,
2214                                                             arg);
2215                 }
2216         }
2217 
2218         if (err)
2219                 return 4;
2220 
2221         return 0;
2222 }
2223 
2224 static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
2225 {
2226         struct s626_private *devpriv = dev->private;
2227 
2228         /* Stop RPS program in case it is currently running */
2229         s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
2230 
2231         /* disable master interrupt */
2232         writel(0, dev->mmio + S626_P_IER);
2233 
2234         devpriv->ai_cmd_running = 0;
2235 
2236         return 0;
2237 }
2238 
2239 static int s626_ao_insn_write(struct comedi_device *dev,
2240                               struct comedi_subdevice *s,
2241                               struct comedi_insn *insn,
2242                               unsigned int *data)
2243 {
2244         unsigned int chan = CR_CHAN(insn->chanspec);
2245         int i;
2246 
2247         for (i = 0; i < insn->n; i++) {
2248                 int16_t dacdata = (int16_t)data[i];
2249                 int ret;
2250 
2251                 dacdata -= (0x1fff);
2252 
2253                 ret = s626_set_dac(dev, chan, dacdata);
2254                 if (ret)
2255                         return ret;
2256 
2257                 s->readback[chan] = data[i];
2258         }
2259 
2260         return insn->n;
2261 }
2262 
2263 /* *************** DIGITAL I/O FUNCTIONS *************** */
2264 
2265 /*
2266  * All DIO functions address a group of DIO channels by means of
2267  * "group" argument.  group may be 0, 1 or 2, which correspond to DIO
2268  * ports A, B and C, respectively.
2269  */
2270 
2271 static void s626_dio_init(struct comedi_device *dev)
2272 {
2273         uint16_t group;
2274 
2275         /* Prepare to treat writes to WRCapSel as capture disables. */
2276         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
2277 
2278         /* For each group of sixteen channels ... */
2279         for (group = 0; group < S626_DIO_BANKS; group++) {
2280                 /* Disable all interrupts */
2281                 s626_debi_write(dev, S626_LP_WRINTSEL(group), 0);
2282                 /* Disable all event captures */
2283                 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
2284                 /* Init all DIOs to default edge polarity */
2285                 s626_debi_write(dev, S626_LP_WREDGSEL(group), 0);
2286                 /* Program all outputs to inactive state */
2287                 s626_debi_write(dev, S626_LP_WRDOUT(group), 0);
2288         }
2289 }
2290 
2291 static int s626_dio_insn_bits(struct comedi_device *dev,
2292                               struct comedi_subdevice *s,
2293                               struct comedi_insn *insn,
2294                               unsigned int *data)
2295 {
2296         unsigned long group = (unsigned long)s->private;
2297 
2298         if (comedi_dio_update_state(s, data))
2299                 s626_debi_write(dev, S626_LP_WRDOUT(group), s->state);
2300 
2301         data[1] = s626_debi_read(dev, S626_LP_RDDIN(group));
2302 
2303         return insn->n;
2304 }
2305 
2306 static int s626_dio_insn_config(struct comedi_device *dev,
2307                                 struct comedi_subdevice *s,
2308                                 struct comedi_insn *insn,
2309                                 unsigned int *data)
2310 {
2311         unsigned long group = (unsigned long)s->private;
2312         int ret;
2313 
2314         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
2315         if (ret)
2316                 return ret;
2317 
2318         s626_debi_write(dev, S626_LP_WRDOUT(group), s->io_bits);
2319 
2320         return insn->n;
2321 }
2322 
2323 /*
2324  * Now this function initializes the value of the counter (data[0])
2325  * and set the subdevice. To complete with trigger and interrupt
2326  * configuration.
2327  *
2328  * FIXME: data[0] is supposed to be an INSN_CONFIG_xxx constant indicating
2329  * what is being configured, but this function appears to be using data[0]
2330  * as a variable.
2331  */
2332 static int s626_enc_insn_config(struct comedi_device *dev,
2333                                 struct comedi_subdevice *s,
2334                                 struct comedi_insn *insn, unsigned int *data)
2335 {
2336         unsigned int chan = CR_CHAN(insn->chanspec);
2337         uint16_t setup =
2338                 /* Preload upon index. */
2339                 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2340                 /* Disable hardware index. */
2341                 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2342                 /* Operating mode is Counter. */
2343                 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2344                 /* Active high clock. */
2345                 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2346                 /* Clock multiplier is 1x. */
2347                 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2348                 /* Enabled by index */
2349                 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2350         /* uint16_t disable_int_src = true; */
2351         /* uint32_t Preloadvalue;              //Counter initial value */
2352         uint16_t value_latchsrc = S626_LATCHSRC_AB_READ;
2353         uint16_t enab = S626_CLKENAB_ALWAYS;
2354 
2355         /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
2356 
2357         s626_set_mode(dev, chan, setup, true);
2358         s626_preload(dev, chan, data[0]);
2359         s626_pulse_index(dev, chan);
2360         s626_set_latch_source(dev, chan, value_latchsrc);
2361         s626_set_enable(dev, chan, (enab != 0));
2362 
2363         return insn->n;
2364 }
2365 
2366 static int s626_enc_insn_read(struct comedi_device *dev,
2367                               struct comedi_subdevice *s,
2368                               struct comedi_insn *insn,
2369                               unsigned int *data)
2370 {
2371         unsigned int chan = CR_CHAN(insn->chanspec);
2372         uint16_t cntr_latch_reg = S626_LP_CNTR(chan);
2373         int i;
2374 
2375         for (i = 0; i < insn->n; i++) {
2376                 unsigned int val;
2377 
2378                 /*
2379                  * Read the counter's output latch LSW/MSW.
2380                  * Latches on LSW read.
2381                  */
2382                 val = s626_debi_read(dev, cntr_latch_reg);
2383                 val |= (s626_debi_read(dev, cntr_latch_reg + 2) << 16);
2384                 data[i] = val;
2385         }
2386 
2387         return insn->n;
2388 }
2389 
2390 static int s626_enc_insn_write(struct comedi_device *dev,
2391                                struct comedi_subdevice *s,
2392                                struct comedi_insn *insn, unsigned int *data)
2393 {
2394         unsigned int chan = CR_CHAN(insn->chanspec);
2395 
2396         /* Set the preload register */
2397         s626_preload(dev, chan, data[0]);
2398 
2399         /*
2400          * Software index pulse forces the preload register to load
2401          * into the counter
2402          */
2403         s626_set_load_trig(dev, chan, 0);
2404         s626_pulse_index(dev, chan);
2405         s626_set_load_trig(dev, chan, 2);
2406 
2407         return 1;
2408 }
2409 
2410 static void s626_write_misc2(struct comedi_device *dev, uint16_t new_image)
2411 {
2412         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WENABLE);
2413         s626_debi_write(dev, S626_LP_WRMISC2, new_image);
2414         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WDISABLE);
2415 }
2416 
2417 static void s626_counters_init(struct comedi_device *dev)
2418 {
2419         int chan;
2420         uint16_t setup =
2421                 /* Preload upon index. */
2422                 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2423                 /* Disable hardware index. */
2424                 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2425                 /* Operating mode is counter. */
2426                 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2427                 /* Active high clock. */
2428                 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2429                 /* Clock multiplier is 1x. */
2430                 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2431                 /* Enabled by index */
2432                 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2433 
2434         /*
2435          * Disable all counter interrupts and clear any captured counter events.
2436          */
2437         for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
2438                 s626_set_mode(dev, chan, setup, true);
2439                 s626_set_int_src(dev, chan, 0);
2440                 s626_reset_cap_flags(dev, chan);
2441                 s626_set_enable(dev, chan, S626_CLKENAB_ALWAYS);
2442         }
2443 }
2444 
2445 static int s626_allocate_dma_buffers(struct comedi_device *dev)
2446 {
2447         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2448         struct s626_private *devpriv = dev->private;
2449         void *addr;
2450         dma_addr_t appdma;
2451 
2452         addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2453         if (!addr)
2454                 return -ENOMEM;
2455         devpriv->ana_buf.logical_base = addr;
2456         devpriv->ana_buf.physical_base = appdma;
2457 
2458         addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2459         if (!addr)
2460                 return -ENOMEM;
2461         devpriv->rps_buf.logical_base = addr;
2462         devpriv->rps_buf.physical_base = appdma;
2463 
2464         return 0;
2465 }
2466 
2467 static void s626_free_dma_buffers(struct comedi_device *dev)
2468 {
2469         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2470         struct s626_private *devpriv = dev->private;
2471 
2472         if (!devpriv)
2473                 return;
2474 
2475         if (devpriv->rps_buf.logical_base)
2476                 pci_free_consistent(pcidev, S626_DMABUF_SIZE,
2477                                     devpriv->rps_buf.logical_base,
2478                                     devpriv->rps_buf.physical_base);
2479         if (devpriv->ana_buf.logical_base)
2480                 pci_free_consistent(pcidev, S626_DMABUF_SIZE,
2481                                     devpriv->ana_buf.logical_base,
2482                                     devpriv->ana_buf.physical_base);
2483 }
2484 
2485 static int s626_initialize(struct comedi_device *dev)
2486 {
2487         struct s626_private *devpriv = dev->private;
2488         dma_addr_t phys_buf;
2489         uint16_t chan;
2490         int i;
2491         int ret;
2492 
2493         /* Enable DEBI and audio pins, enable I2C interface */
2494         s626_mc_enable(dev, S626_MC1_DEBI | S626_MC1_AUDIO | S626_MC1_I2C,
2495                        S626_P_MC1);
2496 
2497         /*
2498          * Configure DEBI operating mode
2499          *
2500          *  Local bus is 16 bits wide
2501          *  Declare DEBI transfer timeout interval
2502          *  Set up byte lane steering
2503          *  Intel-compatible local bus (DEBI never times out)
2504          */
2505         writel(S626_DEBI_CFG_SLAVE16 |
2506                (S626_DEBI_TOUT << S626_DEBI_CFG_TOUT_BIT) | S626_DEBI_SWAP |
2507                S626_DEBI_CFG_INTEL, dev->mmio + S626_P_DEBICFG);
2508 
2509         /* Disable MMU paging */
2510         writel(S626_DEBI_PAGE_DISABLE, dev->mmio + S626_P_DEBIPAGE);
2511 
2512         /* Init GPIO so that ADC Start* is negated */
2513         writel(S626_GPIO_BASE | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
2514 
2515         /* I2C device address for onboard eeprom (revb) */
2516         devpriv->i2c_adrs = 0xA0;
2517 
2518         /*
2519          * Issue an I2C ABORT command to halt any I2C
2520          * operation in progress and reset BUSY flag.
2521          */
2522         writel(S626_I2C_CLKSEL | S626_I2C_ABORT,
2523                dev->mmio + S626_P_I2CSTAT);
2524         s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2525         ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
2526         if (ret)
2527                 return ret;
2528 
2529         /*
2530          * Per SAA7146 data sheet, write to STATUS
2531          * reg twice to reset all  I2C error flags.
2532          */
2533         for (i = 0; i < 2; i++) {
2534                 writel(S626_I2C_CLKSEL, dev->mmio + S626_P_I2CSTAT);
2535                 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2536                 ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
2537                 if (ret)
2538                         return ret;
2539         }
2540 
2541         /*
2542          * Init audio interface functional attributes: set DAC/ADC
2543          * serial clock rates, invert DAC serial clock so that
2544          * DAC data setup times are satisfied, enable DAC serial
2545          * clock out.
2546          */
2547         writel(S626_ACON2_INIT, dev->mmio + S626_P_ACON2);
2548 
2549         /*
2550          * Set up TSL1 slot list, which is used to control the
2551          * accumulation of ADC data: S626_RSD1 = shift data in on SD1.
2552          * S626_SIB_A1  = store data uint8_t at next available location
2553          * in FB BUFFER1 register.
2554          */
2555         writel(S626_RSD1 | S626_SIB_A1, dev->mmio + S626_P_TSL1);
2556         writel(S626_RSD1 | S626_SIB_A1 | S626_EOS,
2557                dev->mmio + S626_P_TSL1 + 4);
2558 
2559         /* Enable TSL1 slot list so that it executes all the time */
2560         writel(S626_ACON1_ADCSTART, dev->mmio + S626_P_ACON1);
2561 
2562         /*
2563          * Initialize RPS registers used for ADC
2564          */
2565 
2566         /* Physical start of RPS program */
2567         writel((uint32_t)devpriv->rps_buf.physical_base,
2568                dev->mmio + S626_P_RPSADDR1);
2569         /* RPS program performs no explicit mem writes */
2570         writel(0, dev->mmio + S626_P_RPSPAGE1);
2571         /* Disable RPS timeouts */
2572         writel(0, dev->mmio + S626_P_RPS1_TOUT);
2573 
2574 #if 0
2575         /*
2576          * SAA7146 BUG WORKAROUND
2577          *
2578          * Initialize SAA7146 ADC interface to a known state by
2579          * invoking ADCs until FB BUFFER 1 register shows that it
2580          * is correctly receiving ADC data. This is necessary
2581          * because the SAA7146 ADC interface does not start up in
2582          * a defined state after a PCI reset.
2583          */
2584         {
2585                 struct comedi_subdevice *s = dev->read_subdev;
2586                 uint8_t poll_list;
2587                 uint16_t adc_data;
2588                 uint16_t start_val;
2589                 uint16_t index;
2590                 unsigned int data[16];
2591 
2592                 /* Create a simple polling list for analog input channel 0 */
2593                 poll_list = S626_EOPL;
2594                 s626_reset_adc(dev, &poll_list);
2595 
2596                 /* Get initial ADC value */
2597                 s626_ai_rinsn(dev, s, NULL, data);
2598                 start_val = data[0];
2599 
2600                 /*
2601                  * VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED
2602                  * EXECUTION.
2603                  *
2604                  * Invoke ADCs until the new ADC value differs from the initial
2605                  * value or a timeout occurs.  The timeout protects against the
2606                  * possibility that the driver is restarting and the ADC data is
2607                  * a fixed value resulting from the applied ADC analog input
2608                  * being unusually quiet or at the rail.
2609                  */
2610                 for (index = 0; index < 500; index++) {
2611                         s626_ai_rinsn(dev, s, NULL, data);
2612                         adc_data = data[0];
2613                         if (adc_data != start_val)
2614                                 break;
2615                 }
2616         }
2617 #endif  /* SAA7146 BUG WORKAROUND */
2618 
2619         /*
2620          * Initialize the DAC interface
2621          */
2622 
2623         /*
2624          * Init Audio2's output DMAC attributes:
2625          *   burst length = 1 DWORD
2626          *   threshold = 1 DWORD.
2627          */
2628         writel(0, dev->mmio + S626_P_PCI_BT_A);
2629 
2630         /*
2631          * Init Audio2's output DMA physical addresses.  The protection
2632          * address is set to 1 DWORD past the base address so that a
2633          * single DWORD will be transferred each time a DMA transfer is
2634          * enabled.
2635          */
2636         phys_buf = devpriv->ana_buf.physical_base +
2637                    (S626_DAC_WDMABUF_OS * sizeof(uint32_t));
2638         writel((uint32_t)phys_buf, dev->mmio + S626_P_BASEA2_OUT);
2639         writel((uint32_t)(phys_buf + sizeof(uint32_t)),
2640                dev->mmio + S626_P_PROTA2_OUT);
2641 
2642         /*
2643          * Cache Audio2's output DMA buffer logical address.  This is
2644          * where DAC data is buffered for A2 output DMA transfers.
2645          */
2646         devpriv->dac_wbuf = (uint32_t *)devpriv->ana_buf.logical_base +
2647                             S626_DAC_WDMABUF_OS;
2648 
2649         /*
2650          * Audio2's output channels does not use paging.  The
2651          * protection violation handling bit is set so that the
2652          * DMAC will automatically halt and its PCI address pointer
2653          * will be reset when the protection address is reached.
2654          */
2655         writel(8, dev->mmio + S626_P_PAGEA2_OUT);
2656 
2657         /*
2658          * Initialize time slot list 2 (TSL2), which is used to control
2659          * the clock generation for and serialization of data to be sent
2660          * to the DAC devices.  Slot 0 is a NOP that is used to trap TSL
2661          * execution; this permits other slots to be safely modified
2662          * without first turning off the TSL sequencer (which is
2663          * apparently impossible to do).  Also, SD3 (which is driven by a
2664          * pull-up resistor) is shifted in and stored to the MSB of
2665          * FB_BUFFER2 to be used as evidence that the slot sequence has
2666          * not yet finished executing.
2667          */
2668 
2669         /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */
2670         writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2 | S626_EOS,
2671                dev->mmio + S626_VECTPORT(0));
2672 
2673         /*
2674          * Initialize slot 1, which is constant.  Slot 1 causes a
2675          * DWORD to be transferred from audio channel 2's output FIFO
2676          * to the FIFO's output buffer so that it can be serialized
2677          * and sent to the DAC during subsequent slots.  All remaining
2678          * slots are dynamically populated as required by the target
2679          * DAC device.
2680          */
2681 
2682         /* Slot 1: Fetch DWORD from Audio2's output FIFO */
2683         writel(S626_LF_A2, dev->mmio + S626_VECTPORT(1));
2684 
2685         /* Start DAC's audio interface (TSL2) running */
2686         writel(S626_ACON1_DACSTART, dev->mmio + S626_P_ACON1);
2687 
2688         /*
2689          * Init Trim DACs to calibrated values.  Do it twice because the
2690          * SAA7146 audio channel does not always reset properly and
2691          * sometimes causes the first few TrimDAC writes to malfunction.
2692          */
2693         s626_load_trim_dacs(dev);
2694         ret = s626_load_trim_dacs(dev);
2695         if (ret)
2696                 return ret;
2697 
2698         /*
2699          * Manually init all gate array hardware in case this is a soft
2700          * reset (we have no way of determining whether this is a warm
2701          * or cold start).  This is necessary because the gate array will
2702          * reset only in response to a PCI hard reset; there is no soft
2703          * reset function.
2704          */
2705 
2706         /*
2707          * Init all DAC outputs to 0V and init all DAC setpoint and
2708          * polarity images.
2709          */
2710         for (chan = 0; chan < S626_DAC_CHANNELS; chan++) {
2711                 ret = s626_set_dac(dev, chan, 0);
2712                 if (ret)
2713                         return ret;
2714         }
2715 
2716         /* Init counters */
2717         s626_counters_init(dev);
2718 
2719         /*
2720          * Without modifying the state of the Battery Backup enab, disable
2721          * the watchdog timer, set DIO channels 0-5 to operate in the
2722          * standard DIO (vs. counter overflow) mode, disable the battery
2723          * charger, and reset the watchdog interval selector to zero.
2724          */
2725         s626_write_misc2(dev, (s626_debi_read(dev, S626_LP_RDMISC2) &
2726                                S626_MISC2_BATT_ENABLE));
2727 
2728         /* Initialize the digital I/O subsystem */
2729         s626_dio_init(dev);
2730 
2731         return 0;
2732 }
2733 
2734 static int s626_auto_attach(struct comedi_device *dev,
2735                             unsigned long context_unused)
2736 {
2737         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2738         struct s626_private *devpriv;
2739         struct comedi_subdevice *s;
2740         int ret;
2741 
2742         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
2743         if (!devpriv)
2744                 return -ENOMEM;
2745 
2746         ret = comedi_pci_enable(dev);
2747         if (ret)
2748                 return ret;
2749 
2750         dev->mmio = pci_ioremap_bar(pcidev, 0);
2751         if (!dev->mmio)
2752                 return -ENOMEM;
2753 
2754         /* disable master interrupt */
2755         writel(0, dev->mmio + S626_P_IER);
2756 
2757         /* soft reset */
2758         writel(S626_MC1_SOFT_RESET, dev->mmio + S626_P_MC1);
2759 
2760         /* DMA FIXME DMA// */
2761 
2762         ret = s626_allocate_dma_buffers(dev);
2763         if (ret)
2764                 return ret;
2765 
2766         if (pcidev->irq) {
2767                 ret = request_irq(pcidev->irq, s626_irq_handler, IRQF_SHARED,
2768                                   dev->board_name, dev);
2769 
2770                 if (ret == 0)
2771                         dev->irq = pcidev->irq;
2772         }
2773 
2774         ret = comedi_alloc_subdevices(dev, 6);
2775         if (ret)
2776                 return ret;
2777 
2778         s = &dev->subdevices[0];
2779         /* analog input subdevice */
2780         s->type         = COMEDI_SUBD_AI;
2781         s->subdev_flags = SDF_READABLE | SDF_DIFF;
2782         s->n_chan       = S626_ADC_CHANNELS;
2783         s->maxdata      = 0x3fff;
2784         s->range_table  = &s626_range_table;
2785         s->len_chanlist = S626_ADC_CHANNELS;
2786         s->insn_read    = s626_ai_insn_read;
2787         if (dev->irq) {
2788                 dev->read_subdev = s;
2789                 s->subdev_flags |= SDF_CMD_READ;
2790                 s->do_cmd       = s626_ai_cmd;
2791                 s->do_cmdtest   = s626_ai_cmdtest;
2792                 s->cancel       = s626_ai_cancel;
2793         }
2794 
2795         s = &dev->subdevices[1];
2796         /* analog output subdevice */
2797         s->type         = COMEDI_SUBD_AO;
2798         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2799         s->n_chan       = S626_DAC_CHANNELS;
2800         s->maxdata      = 0x3fff;
2801         s->range_table  = &range_bipolar10;
2802         s->insn_write   = s626_ao_insn_write;
2803 
2804         ret = comedi_alloc_subdev_readback(s);
2805         if (ret)
2806                 return ret;
2807 
2808         s = &dev->subdevices[2];
2809         /* digital I/O subdevice */
2810         s->type         = COMEDI_SUBD_DIO;
2811         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2812         s->n_chan       = 16;
2813         s->maxdata      = 1;
2814         s->io_bits      = 0xffff;
2815         s->private      = (void *)0;    /* DIO group 0 */
2816         s->range_table  = &range_digital;
2817         s->insn_config  = s626_dio_insn_config;
2818         s->insn_bits    = s626_dio_insn_bits;
2819 
2820         s = &dev->subdevices[3];
2821         /* digital I/O subdevice */
2822         s->type         = COMEDI_SUBD_DIO;
2823         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2824         s->n_chan       = 16;
2825         s->maxdata      = 1;
2826         s->io_bits      = 0xffff;
2827         s->private      = (void *)1;    /* DIO group 1 */
2828         s->range_table  = &range_digital;
2829         s->insn_config  = s626_dio_insn_config;
2830         s->insn_bits    = s626_dio_insn_bits;
2831 
2832         s = &dev->subdevices[4];
2833         /* digital I/O subdevice */
2834         s->type         = COMEDI_SUBD_DIO;
2835         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2836         s->n_chan       = 16;
2837         s->maxdata      = 1;
2838         s->io_bits      = 0xffff;
2839         s->private      = (void *)2;    /* DIO group 2 */
2840         s->range_table  = &range_digital;
2841         s->insn_config  = s626_dio_insn_config;
2842         s->insn_bits    = s626_dio_insn_bits;
2843 
2844         s = &dev->subdevices[5];
2845         /* encoder (counter) subdevice */
2846         s->type         = COMEDI_SUBD_COUNTER;
2847         s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
2848         s->n_chan       = S626_ENCODER_CHANNELS;
2849         s->maxdata      = 0xffffff;
2850         s->range_table  = &range_unknown;
2851         s->insn_config  = s626_enc_insn_config;
2852         s->insn_read    = s626_enc_insn_read;
2853         s->insn_write   = s626_enc_insn_write;
2854 
2855         ret = s626_initialize(dev);
2856         if (ret)
2857                 return ret;
2858 
2859         return 0;
2860 }
2861 
2862 static void s626_detach(struct comedi_device *dev)
2863 {
2864         struct s626_private *devpriv = dev->private;
2865 
2866         if (devpriv) {
2867                 /* stop ai_command */
2868                 devpriv->ai_cmd_running = 0;
2869 
2870                 if (dev->mmio) {
2871                         /* interrupt mask */
2872                         /* Disable master interrupt */
2873                         writel(0, dev->mmio + S626_P_IER);
2874                         /* Clear board's IRQ status flag */
2875                         writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1,
2876                                dev->mmio + S626_P_ISR);
2877 
2878                         /* Disable the watchdog timer and battery charger. */
2879                         s626_write_misc2(dev, 0);
2880 
2881                         /* Close all interfaces on 7146 device */
2882                         writel(S626_MC1_SHUTDOWN, dev->mmio + S626_P_MC1);
2883                         writel(S626_ACON1_BASE, dev->mmio + S626_P_ACON1);
2884                 }
2885         }
2886         comedi_pci_detach(dev);
2887         s626_free_dma_buffers(dev);
2888 }
2889 
2890 static struct comedi_driver s626_driver = {
2891         .driver_name    = "s626",
2892         .module         = THIS_MODULE,
2893         .auto_attach    = s626_auto_attach,
2894         .detach         = s626_detach,
2895 };
2896 
2897 static int s626_pci_probe(struct pci_dev *dev,
2898                           const struct pci_device_id *id)
2899 {
2900         return comedi_pci_auto_config(dev, &s626_driver, id->driver_data);
2901 }
2902 
2903 /*
2904  * For devices with vendor:device id == 0x1131:0x7146 you must specify
2905  * also subvendor:subdevice ids, because otherwise it will conflict with
2906  * Philips SAA7146 media/dvb based cards.
2907  */
2908 static const struct pci_device_id s626_pci_table[] = {
2909         { PCI_DEVICE_SUB(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA7146,
2910                          0x6000, 0x0272) },
2911         { 0 }
2912 };
2913 MODULE_DEVICE_TABLE(pci, s626_pci_table);
2914 
2915 static struct pci_driver s626_pci_driver = {
2916         .name           = "s626",
2917         .id_table       = s626_pci_table,
2918         .probe          = s626_pci_probe,
2919         .remove         = comedi_pci_auto_unconfig,
2920 };
2921 module_comedi_pci_driver(s626_driver, s626_pci_driver);
2922 
2923 MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
2924 MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
2925 MODULE_LICENSE("GPL");
2926 

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