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Linux/drivers/staging/comedi/drivers/s626.c

  1 /*
  2  * comedi/drivers/s626.c
  3  * Sensoray s626 Comedi driver
  4  *
  5  * COMEDI - Linux Control and Measurement Device Interface
  6  * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
  7  *
  8  * Based on Sensoray Model 626 Linux driver Version 0.2
  9  * Copyright (C) 2002-2004 Sensoray Co., Inc.
 10  *
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License as published by
 13  * the Free Software Foundation; either version 2 of the License, or
 14  * (at your option) any later version.
 15  *
 16  * This program is distributed in the hope that it will be useful,
 17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19  * GNU General Public License for more details.
 20  */
 21 
 22 /*
 23  * Driver: s626
 24  * Description: Sensoray 626 driver
 25  * Devices: [Sensoray] 626 (s626)
 26  * Authors: Gianluca Palli <gpalli@deis.unibo.it>,
 27  * Updated: Fri, 15 Feb 2008 10:28:42 +0000
 28  * Status: experimental
 29 
 30  * Configuration options: not applicable, uses PCI auto config
 31 
 32  * INSN_CONFIG instructions:
 33  *   analog input:
 34  *    none
 35  *
 36  *   analog output:
 37  *    none
 38  *
 39  *   digital channel:
 40  *    s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
 41  *    supported configuration options:
 42  *    INSN_CONFIG_DIO_QUERY
 43  *    COMEDI_INPUT
 44  *    COMEDI_OUTPUT
 45  *
 46  *   encoder:
 47  *    Every channel must be configured before reading.
 48  *
 49  *   Example code
 50  *
 51  *    insn.insn=INSN_CONFIG;   //configuration instruction
 52  *    insn.n=1;                //number of operation (must be 1)
 53  *    insn.data=&initialvalue; //initial value loaded into encoder
 54  *                             //during configuration
 55  *    insn.subdev=5;           //encoder subdevice
 56  *    insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
 57  *                                                         //to configure
 58  *
 59  *    comedi_do_insn(cf,&insn); //executing configuration
 60  */
 61 
 62 #include <linux/module.h>
 63 #include <linux/delay.h>
 64 #include <linux/pci.h>
 65 #include <linux/interrupt.h>
 66 #include <linux/kernel.h>
 67 #include <linux/types.h>
 68 
 69 #include "../comedidev.h"
 70 
 71 #include "comedi_fc.h"
 72 #include "s626.h"
 73 
 74 struct s626_buffer_dma {
 75         dma_addr_t physical_base;
 76         void *logical_base;
 77 };
 78 
 79 struct s626_private {
 80         uint8_t ai_cmd_running;         /* ai_cmd is running */
 81         unsigned int ai_sample_timer;   /* time between samples in
 82                                          * units of the timer */
 83         int ai_convert_count;           /* conversion counter */
 84         unsigned int ai_convert_timer;  /* time between conversion in
 85                                          * units of the timer */
 86         uint16_t counter_int_enabs;     /* counter interrupt enable mask
 87                                          * for MISC2 register */
 88         uint8_t adc_items;              /* number of items in ADC poll list */
 89         struct s626_buffer_dma rps_buf; /* DMA buffer used to hold ADC (RPS1)
 90                                          * program */
 91         struct s626_buffer_dma ana_buf; /* DMA buffer used to receive ADC data
 92                                          * and hold DAC data */
 93         uint32_t *dac_wbuf;             /* pointer to logical adrs of DMA buffer
 94                                          * used to hold DAC data */
 95         uint16_t dacpol;                /* image of DAC polarity register */
 96         uint8_t trim_setpoint[12];      /* images of TrimDAC setpoints */
 97         uint32_t i2c_adrs;              /* I2C device address for onboard EEPROM
 98                                          * (board rev dependent) */
 99 };
100 
101 /* Counter overflow/index event flag masks for RDMISC2. */
102 #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 +  4)))
103 #define S626_OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
104 
105 /*
106  * Enable/disable a function or test status bit(s) that are accessed
107  * through Main Control Registers 1 or 2.
108  */
109 static void s626_mc_enable(struct comedi_device *dev,
110                            unsigned int cmd, unsigned int reg)
111 {
112         unsigned int val = (cmd << 16) | cmd;
113 
114         mmiowb();
115         writel(val, dev->mmio + reg);
116 }
117 
118 static void s626_mc_disable(struct comedi_device *dev,
119                             unsigned int cmd, unsigned int reg)
120 {
121         writel(cmd << 16, dev->mmio + reg);
122         mmiowb();
123 }
124 
125 static bool s626_mc_test(struct comedi_device *dev,
126                          unsigned int cmd, unsigned int reg)
127 {
128         unsigned int val;
129 
130         val = readl(dev->mmio + reg);
131 
132         return (val & cmd) ? true : false;
133 }
134 
135 #define S626_BUGFIX_STREG(REGADRS)   ((REGADRS) - 4)
136 
137 /* Write a time slot control record to TSL2. */
138 #define S626_VECTPORT(VECTNUM)          (S626_P_TSL2 + ((VECTNUM) << 2))
139 
140 static const struct comedi_lrange s626_range_table = {
141         2, {
142                 BIP_RANGE(5),
143                 BIP_RANGE(10)
144         }
145 };
146 
147 /*
148  * Execute a DEBI transfer.  This must be called from within a critical section.
149  */
150 static void s626_debi_transfer(struct comedi_device *dev)
151 {
152         static const int timeout = 10000;
153         int i;
154 
155         /* Initiate upload of shadow RAM to DEBI control register */
156         s626_mc_enable(dev, S626_MC2_UPLD_DEBI, S626_P_MC2);
157 
158         /*
159          * Wait for completion of upload from shadow RAM to
160          * DEBI control register.
161          */
162         for (i = 0; i < timeout; i++) {
163                 if (s626_mc_test(dev, S626_MC2_UPLD_DEBI, S626_P_MC2))
164                         break;
165                 udelay(1);
166         }
167         if (i == timeout)
168                 dev_err(dev->class_dev,
169                         "Timeout while uploading to DEBI control register\n");
170 
171         /* Wait until DEBI transfer is done */
172         for (i = 0; i < timeout; i++) {
173                 if (!(readl(dev->mmio + S626_P_PSR) & S626_PSR_DEBI_S))
174                         break;
175                 udelay(1);
176         }
177         if (i == timeout)
178                 dev_err(dev->class_dev, "DEBI transfer timeout\n");
179 }
180 
181 /*
182  * Read a value from a gate array register.
183  */
184 static uint16_t s626_debi_read(struct comedi_device *dev, uint16_t addr)
185 {
186         /* Set up DEBI control register value in shadow RAM */
187         writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD);
188 
189         /*  Execute the DEBI transfer. */
190         s626_debi_transfer(dev);
191 
192         return readl(dev->mmio + S626_P_DEBIAD);
193 }
194 
195 /*
196  * Write a value to a gate array register.
197  */
198 static void s626_debi_write(struct comedi_device *dev, uint16_t addr,
199                             uint16_t wdata)
200 {
201         /* Set up DEBI control register value in shadow RAM */
202         writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD);
203         writel(wdata, dev->mmio + S626_P_DEBIAD);
204 
205         /*  Execute the DEBI transfer. */
206         s626_debi_transfer(dev);
207 }
208 
209 /*
210  * Replace the specified bits in a gate array register.  Imports: mask
211  * specifies bits that are to be preserved, wdata is new value to be
212  * or'd with the masked original.
213  */
214 static void s626_debi_replace(struct comedi_device *dev, unsigned int addr,
215                               unsigned int mask, unsigned int wdata)
216 {
217         unsigned int val;
218 
219         addr &= 0xffff;
220         writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD);
221         s626_debi_transfer(dev);
222 
223         writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD);
224         val = readl(dev->mmio + S626_P_DEBIAD);
225         val &= mask;
226         val |= wdata;
227         writel(val & 0xffff, dev->mmio + S626_P_DEBIAD);
228         s626_debi_transfer(dev);
229 }
230 
231 /* **************  EEPROM ACCESS FUNCTIONS  ************** */
232 
233 static int s626_i2c_handshake_eoc(struct comedi_device *dev,
234                                  struct comedi_subdevice *s,
235                                  struct comedi_insn *insn,
236                                  unsigned long context)
237 {
238         bool status;
239 
240         status = s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
241         if (status)
242                 return 0;
243         return -EBUSY;
244 }
245 
246 static int s626_i2c_handshake(struct comedi_device *dev, uint32_t val)
247 {
248         unsigned int ctrl;
249         int ret;
250 
251         /* Write I2C command to I2C Transfer Control shadow register */
252         writel(val, dev->mmio + S626_P_I2CCTRL);
253 
254         /*
255          * Upload I2C shadow registers into working registers and
256          * wait for upload confirmation.
257          */
258         s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
259         ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
260         if (ret)
261                 return ret;
262 
263         /* Wait until I2C bus transfer is finished or an error occurs */
264         do {
265                 ctrl = readl(dev->mmio + S626_P_I2CCTRL);
266         } while ((ctrl & (S626_I2C_BUSY | S626_I2C_ERR)) == S626_I2C_BUSY);
267 
268         /* Return non-zero if I2C error occurred */
269         return ctrl & S626_I2C_ERR;
270 }
271 
272 /* Read uint8_t from EEPROM. */
273 static uint8_t s626_i2c_read(struct comedi_device *dev, uint8_t addr)
274 {
275         struct s626_private *devpriv = dev->private;
276 
277         /*
278          * Send EEPROM target address:
279          *  Byte2 = I2C command: write to I2C EEPROM device.
280          *  Byte1 = EEPROM internal target address.
281          *  Byte0 = Not sent.
282          */
283         if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
284                                                 devpriv->i2c_adrs) |
285                                     S626_I2C_B1(S626_I2C_ATTRSTOP, addr) |
286                                     S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
287                 /* Abort function and declare error if handshake failed. */
288                 return 0;
289 
290         /*
291          * Execute EEPROM read:
292          *  Byte2 = I2C command: read from I2C EEPROM device.
293          *  Byte1 receives uint8_t from EEPROM.
294          *  Byte0 = Not sent.
295          */
296         if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
297                                            (devpriv->i2c_adrs | 1)) |
298                                     S626_I2C_B1(S626_I2C_ATTRSTOP, 0) |
299                                     S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
300                 /* Abort function and declare error if handshake failed. */
301                 return 0;
302 
303         return (readl(dev->mmio + S626_P_I2CCTRL) >> 16) & 0xff;
304 }
305 
306 /* ***********  DAC FUNCTIONS *********** */
307 
308 /* TrimDac LogicalChan-to-PhysicalChan mapping table. */
309 static const uint8_t s626_trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
310 
311 /* TrimDac LogicalChan-to-EepromAdrs mapping table. */
312 static const uint8_t s626_trimadrs[] = {
313         0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63
314 };
315 
316 enum {
317         s626_send_dac_wait_not_mc1_a2out,
318         s626_send_dac_wait_ssr_af2_out,
319         s626_send_dac_wait_fb_buffer2_msb_00,
320         s626_send_dac_wait_fb_buffer2_msb_ff
321 };
322 
323 static int s626_send_dac_eoc(struct comedi_device *dev,
324                              struct comedi_subdevice *s,
325                              struct comedi_insn *insn,
326                              unsigned long context)
327 {
328         unsigned int status;
329 
330         switch (context) {
331         case s626_send_dac_wait_not_mc1_a2out:
332                 status = readl(dev->mmio + S626_P_MC1);
333                 if (!(status & S626_MC1_A2OUT))
334                         return 0;
335                 break;
336         case s626_send_dac_wait_ssr_af2_out:
337                 status = readl(dev->mmio + S626_P_SSR);
338                 if (status & S626_SSR_AF2_OUT)
339                         return 0;
340                 break;
341         case s626_send_dac_wait_fb_buffer2_msb_00:
342                 status = readl(dev->mmio + S626_P_FB_BUFFER2);
343                 if (!(status & 0xff000000))
344                         return 0;
345                 break;
346         case s626_send_dac_wait_fb_buffer2_msb_ff:
347                 status = readl(dev->mmio + S626_P_FB_BUFFER2);
348                 if (status & 0xff000000)
349                         return 0;
350                 break;
351         default:
352                 return -EINVAL;
353         }
354         return -EBUSY;
355 }
356 
357 /*
358  * Private helper function: Transmit serial data to DAC via Audio
359  * channel 2.  Assumes: (1) TSL2 slot records initialized, and (2)
360  * dacpol contains valid target image.
361  */
362 static int s626_send_dac(struct comedi_device *dev, uint32_t val)
363 {
364         struct s626_private *devpriv = dev->private;
365         int ret;
366 
367         /* START THE SERIAL CLOCK RUNNING ------------- */
368 
369         /*
370          * Assert DAC polarity control and enable gating of DAC serial clock
371          * and audio bit stream signals.  At this point in time we must be
372          * assured of being in time slot 0.  If we are not in slot 0, the
373          * serial clock and audio stream signals will be disabled; this is
374          * because the following s626_debi_write statement (which enables
375          * signals to be passed through the gate array) would execute before
376          * the trailing edge of WS1/WS3 (which turns off the signals), thus
377          * causing the signals to be inactive during the DAC write.
378          */
379         s626_debi_write(dev, S626_LP_DACPOL, devpriv->dacpol);
380 
381         /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
382 
383         /* Copy DAC setpoint value to DAC's output DMA buffer. */
384         /* writel(val, dev->mmio + (uint32_t)devpriv->dac_wbuf); */
385         *devpriv->dac_wbuf = val;
386 
387         /*
388          * Enable the output DMA transfer. This will cause the DMAC to copy
389          * the DAC's data value to A2's output FIFO. The DMA transfer will
390          * then immediately terminate because the protection address is
391          * reached upon transfer of the first DWORD value.
392          */
393         s626_mc_enable(dev, S626_MC1_A2OUT, S626_P_MC1);
394 
395         /* While the DMA transfer is executing ... */
396 
397         /*
398          * Reset Audio2 output FIFO's underflow flag (along with any
399          * other FIFO underflow/overflow flags). When set, this flag
400          * will indicate that we have emerged from slot 0.
401          */
402         writel(S626_ISR_AFOU, dev->mmio + S626_P_ISR);
403 
404         /*
405          * Wait for the DMA transfer to finish so that there will be data
406          * available in the FIFO when time slot 1 tries to transfer a DWORD
407          * from the FIFO to the output buffer register.  We test for DMA
408          * Done by polling the DMAC enable flag; this flag is automatically
409          * cleared when the transfer has finished.
410          */
411         ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
412                              s626_send_dac_wait_not_mc1_a2out);
413         if (ret) {
414                 dev_err(dev->class_dev, "DMA transfer timeout\n");
415                 return ret;
416         }
417 
418         /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
419 
420         /*
421          * FIFO data is now available, so we enable execution of time slots
422          * 1 and higher by clearing the EOS flag in slot 0.  Note that SD3
423          * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
424          * detection.
425          */
426         writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2,
427                dev->mmio + S626_VECTPORT(0));
428 
429         /*
430          * Wait for slot 1 to execute to ensure that the Packet will be
431          * transmitted.  This is detected by polling the Audio2 output FIFO
432          * underflow flag, which will be set when slot 1 execution has
433          * finished transferring the DAC's data DWORD from the output FIFO
434          * to the output buffer register.
435          */
436         ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
437                              s626_send_dac_wait_ssr_af2_out);
438         if (ret) {
439                 dev_err(dev->class_dev,
440                         "TSL timeout waiting for slot 1 to execute\n");
441                 return ret;
442         }
443 
444         /*
445          * Set up to trap execution at slot 0 when the TSL sequencer cycles
446          * back to slot 0 after executing the EOS in slot 5.  Also,
447          * simultaneously shift out and in the 0x00 that is ALWAYS the value
448          * stored in the last byte to be shifted out of the FIFO's DWORD
449          * buffer register.
450          */
451         writel(S626_XSD2 | S626_XFIFO_2 | S626_RSD2 | S626_SIB_A2 | S626_EOS,
452                dev->mmio + S626_VECTPORT(0));
453 
454         /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
455 
456         /*
457          * Wait for the TSL to finish executing all time slots before
458          * exiting this function.  We must do this so that the next DAC
459          * write doesn't start, thereby enabling clock/chip select signals:
460          *
461          * 1. Before the TSL sequence cycles back to slot 0, which disables
462          *    the clock/cs signal gating and traps slot // list execution.
463          *    we have not yet finished slot 5 then the clock/cs signals are
464          *    still gated and we have not finished transmitting the stream.
465          *
466          * 2. While slots 2-5 are executing due to a late slot 0 trap.  In
467          *    this case, the slot sequence is currently repeating, but with
468          *    clock/cs signals disabled.  We must wait for slot 0 to trap
469          *    execution before setting up the next DAC setpoint DMA transfer
470          *    and enabling the clock/cs signals.  To detect the end of slot 5,
471          *    we test for the FB_BUFFER2 MSB contents to be equal to 0xFF.  If
472          *    the TSL has not yet finished executing slot 5 ...
473          */
474         if (readl(dev->mmio + S626_P_FB_BUFFER2) & 0xff000000) {
475                 /*
476                  * The trap was set on time and we are still executing somewhere
477                  * in slots 2-5, so we now wait for slot 0 to execute and trap
478                  * TSL execution.  This is detected when FB_BUFFER2 MSB changes
479                  * from 0xFF to 0x00, which slot 0 causes to happen by shifting
480                  * out/in on SD2 the 0x00 that is always referenced by slot 5.
481                  */
482                 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
483                                      s626_send_dac_wait_fb_buffer2_msb_00);
484                 if (ret) {
485                         dev_err(dev->class_dev,
486                                 "TSL timeout waiting for slot 0 to execute\n");
487                         return ret;
488                 }
489         }
490         /*
491          * Either (1) we were too late setting the slot 0 trap; the TSL
492          * sequencer restarted slot 0 before we could set the EOS trap flag,
493          * or (2) we were not late and execution is now trapped at slot 0.
494          * In either case, we must now change slot 0 so that it will store
495          * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
496          * In order to do this, we reprogram slot 0 so that it will shift in
497          * SD3, which is driven only by a pull-up resistor.
498          */
499         writel(S626_RSD3 | S626_SIB_A2 | S626_EOS,
500                dev->mmio + S626_VECTPORT(0));
501 
502         /*
503          * Wait for slot 0 to execute, at which time the TSL is setup for
504          * the next DAC write.  This is detected when FB_BUFFER2 MSB changes
505          * from 0x00 to 0xFF.
506          */
507         ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
508                              s626_send_dac_wait_fb_buffer2_msb_ff);
509         if (ret) {
510                 dev_err(dev->class_dev,
511                         "TSL timeout waiting for slot 0 to execute\n");
512                 return ret;
513         }
514         return 0;
515 }
516 
517 /*
518  * Private helper function: Write setpoint to an application DAC channel.
519  */
520 static int s626_set_dac(struct comedi_device *dev, uint16_t chan,
521                          int16_t dacdata)
522 {
523         struct s626_private *devpriv = dev->private;
524         uint16_t signmask;
525         uint32_t ws_image;
526         uint32_t val;
527 
528         /*
529          * Adjust DAC data polarity and set up Polarity Control Register image.
530          */
531         signmask = 1 << chan;
532         if (dacdata < 0) {
533                 dacdata = -dacdata;
534                 devpriv->dacpol |= signmask;
535         } else {
536                 devpriv->dacpol &= ~signmask;
537         }
538 
539         /* Limit DAC setpoint value to valid range. */
540         if ((uint16_t)dacdata > 0x1FFF)
541                 dacdata = 0x1FFF;
542 
543         /*
544          * Set up TSL2 records (aka "vectors") for DAC update.  Vectors V2
545          * and V3 transmit the setpoint to the target DAC.  V4 and V5 send
546          * data to a non-existent TrimDac channel just to keep the clock
547          * running after sending data to the target DAC.  This is necessary
548          * to eliminate the clock glitch that would otherwise occur at the
549          * end of the target DAC's serial data stream.  When the sequence
550          * restarts at V0 (after executing V5), the gate array automatically
551          * disables gating for the DAC clock and all DAC chip selects.
552          */
553 
554         /* Choose DAC chip select to be asserted */
555         ws_image = (chan & 2) ? S626_WS1 : S626_WS2;
556         /* Slot 2: Transmit high data byte to target DAC */
557         writel(S626_XSD2 | S626_XFIFO_1 | ws_image,
558                dev->mmio + S626_VECTPORT(2));
559         /* Slot 3: Transmit low data byte to target DAC */
560         writel(S626_XSD2 | S626_XFIFO_0 | ws_image,
561                dev->mmio + S626_VECTPORT(3));
562         /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
563         writel(S626_XSD2 | S626_XFIFO_3 | S626_WS3,
564                dev->mmio + S626_VECTPORT(4));
565         /* Slot 5: running after writing target DAC's low data byte */
566         writel(S626_XSD2 | S626_XFIFO_2 | S626_WS3 | S626_EOS,
567                dev->mmio + S626_VECTPORT(5));
568 
569         /*
570          * Construct and transmit target DAC's serial packet:
571          * (A10D DDDD), (DDDD DDDD), (0x0F), (0x00) where A is chan<0>,
572          * and D<12:0> is the DAC setpoint.  Append a WORD value (that writes
573          * to a  non-existent TrimDac channel) that serves to keep the clock
574          * running after the packet has been sent to the target DAC.
575          */
576         val = 0x0F000000;       /* Continue clock after target DAC data
577                                  * (write to non-existent trimdac). */
578         val |= 0x00004000;      /* Address the two main dual-DAC devices
579                                  * (TSL's chip select enables target device). */
580         val |= ((uint32_t)(chan & 1) << 15);    /* Address the DAC channel
581                                                  * within the device. */
582         val |= (uint32_t)dacdata;       /* Include DAC setpoint data. */
583         return s626_send_dac(dev, val);
584 }
585 
586 static int s626_write_trim_dac(struct comedi_device *dev, uint8_t logical_chan,
587                                 uint8_t dac_data)
588 {
589         struct s626_private *devpriv = dev->private;
590         uint32_t chan;
591 
592         /*
593          * Save the new setpoint in case the application needs to read it back
594          * later.
595          */
596         devpriv->trim_setpoint[logical_chan] = (uint8_t)dac_data;
597 
598         /* Map logical channel number to physical channel number. */
599         chan = s626_trimchan[logical_chan];
600 
601         /*
602          * Set up TSL2 records for TrimDac write operation.  All slots shift
603          * 0xFF in from pulled-up SD3 so that the end of the slot sequence
604          * can be detected.
605          */
606 
607         /* Slot 2: Send high uint8_t to target TrimDac */
608         writel(S626_XSD2 | S626_XFIFO_1 | S626_WS3,
609                dev->mmio + S626_VECTPORT(2));
610         /* Slot 3: Send low uint8_t to target TrimDac */
611         writel(S626_XSD2 | S626_XFIFO_0 | S626_WS3,
612                dev->mmio + S626_VECTPORT(3));
613         /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */
614         writel(S626_XSD2 | S626_XFIFO_3 | S626_WS1,
615                dev->mmio + S626_VECTPORT(4));
616         /* Slot 5: Send NOP low  uint8_t to DAC0 */
617         writel(S626_XSD2 | S626_XFIFO_2 | S626_WS1 | S626_EOS,
618                dev->mmio + S626_VECTPORT(5));
619 
620         /*
621          * Construct and transmit target DAC's serial packet:
622          * (0000 AAAA), (DDDD DDDD), (0x00), (0x00) where A<3:0> is the
623          * DAC channel's address, and D<7:0> is the DAC setpoint.  Append a
624          * WORD value (that writes a channel 0 NOP command to a non-existent
625          * main DAC channel) that serves to keep the clock running after the
626          * packet has been sent to the target DAC.
627          */
628 
629         /*
630          * Address the DAC channel within the trimdac device.
631          * Include DAC setpoint data.
632          */
633         return s626_send_dac(dev, (chan << 8) | dac_data);
634 }
635 
636 static int s626_load_trim_dacs(struct comedi_device *dev)
637 {
638         uint8_t i;
639         int ret;
640 
641         /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
642         for (i = 0; i < ARRAY_SIZE(s626_trimchan); i++) {
643                 ret = s626_write_trim_dac(dev, i,
644                                     s626_i2c_read(dev, s626_trimadrs[i]));
645                 if (ret)
646                         return ret;
647         }
648         return 0;
649 }
650 
651 /* ******  COUNTER FUNCTIONS  ******* */
652 
653 /*
654  * All counter functions address a specific counter by means of the
655  * "Counter" argument, which is a logical counter number.  The Counter
656  * argument may have any of the following legal values: 0=0A, 1=1A,
657  * 2=2A, 3=0B, 4=1B, 5=2B.
658  */
659 
660 /*
661  * Return/set a counter pair's latch trigger source.  0: On read
662  * access, 1: A index latches A, 2: B index latches B, 3: A overflow
663  * latches B.
664  */
665 static void s626_set_latch_source(struct comedi_device *dev,
666                                   unsigned int chan, uint16_t value)
667 {
668         s626_debi_replace(dev, S626_LP_CRB(chan),
669                           ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_LATCHSRC),
670                           S626_SET_CRB_LATCHSRC(value));
671 }
672 
673 /*
674  * Write value into counter preload register.
675  */
676 static void s626_preload(struct comedi_device *dev,
677                          unsigned int chan, uint32_t value)
678 {
679         s626_debi_write(dev, S626_LP_CNTR(chan), value);
680         s626_debi_write(dev, S626_LP_CNTR(chan) + 2, value >> 16);
681 }
682 
683 /* ******  PRIVATE COUNTER FUNCTIONS ****** */
684 
685 /*
686  * Reset a counter's index and overflow event capture flags.
687  */
688 static void s626_reset_cap_flags(struct comedi_device *dev,
689                                  unsigned int chan)
690 {
691         uint16_t set;
692 
693         set = S626_SET_CRB_INTRESETCMD(1);
694         if (chan < 3)
695                 set |= S626_SET_CRB_INTRESET_A(1);
696         else
697                 set |= S626_SET_CRB_INTRESET_B(1);
698 
699         s626_debi_replace(dev, S626_LP_CRB(chan), ~S626_CRBMSK_INTCTRL, set);
700 }
701 
702 #ifdef unused
703 /*
704  * Return counter setup in a format (COUNTER_SETUP) that is consistent
705  * for both A and B counters.
706  */
707 static uint16_t s626_get_mode_a(struct comedi_device *dev,
708                                 unsigned int chan)
709 {
710         uint16_t cra;
711         uint16_t crb;
712         uint16_t setup;
713         unsigned cntsrc, clkmult, clkpol, encmode;
714 
715         /* Fetch CRA and CRB register images. */
716         cra = s626_debi_read(dev, S626_LP_CRA(chan));
717         crb = s626_debi_read(dev, S626_LP_CRB(chan));
718 
719         /*
720          * Populate the standardized counter setup bit fields.
721          */
722         setup =
723                 /* LoadSrc  = LoadSrcA. */
724                 S626_SET_STD_LOADSRC(S626_GET_CRA_LOADSRC_A(cra)) |
725                 /* LatchSrc = LatchSrcA. */
726                 S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) |
727                 /* IntSrc   = IntSrcA. */
728                 S626_SET_STD_INTSRC(S626_GET_CRA_INTSRC_A(cra)) |
729                 /* IndxSrc  = IndxSrcA. */
730                 S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_A(cra)) |
731                 /* IndxPol  = IndxPolA. */
732                 S626_SET_STD_INDXPOL(S626_GET_CRA_INDXPOL_A(cra)) |
733                 /* ClkEnab  = ClkEnabA. */
734                 S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_A(crb));
735 
736         /* Adjust mode-dependent parameters. */
737         cntsrc = S626_GET_CRA_CNTSRC_A(cra);
738         if (cntsrc & S626_CNTSRC_SYSCLK) {
739                 /* Timer mode (CntSrcA<1> == 1): */
740                 encmode = S626_ENCMODE_TIMER;
741                 /* Set ClkPol to indicate count direction (CntSrcA<0>). */
742                 clkpol = cntsrc & 1;
743                 /* ClkMult must be 1x in Timer mode. */
744                 clkmult = S626_CLKMULT_1X;
745         } else {
746                 /* Counter mode (CntSrcA<1> == 0): */
747                 encmode = S626_ENCMODE_COUNTER;
748                 /* Pass through ClkPol. */
749                 clkpol = S626_GET_CRA_CLKPOL_A(cra);
750                 /* Force ClkMult to 1x if not legal, else pass through. */
751                 clkmult = S626_GET_CRA_CLKMULT_A(cra);
752                 if (clkmult == S626_CLKMULT_SPECIAL)
753                         clkmult = S626_CLKMULT_1X;
754         }
755         setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) |
756                  S626_SET_STD_CLKPOL(clkpol);
757 
758         /* Return adjusted counter setup. */
759         return setup;
760 }
761 
762 static uint16_t s626_get_mode_b(struct comedi_device *dev,
763                                 unsigned int chan)
764 {
765         uint16_t cra;
766         uint16_t crb;
767         uint16_t setup;
768         unsigned cntsrc, clkmult, clkpol, encmode;
769 
770         /* Fetch CRA and CRB register images. */
771         cra = s626_debi_read(dev, S626_LP_CRA(chan));
772         crb = s626_debi_read(dev, S626_LP_CRB(chan));
773 
774         /*
775          * Populate the standardized counter setup bit fields.
776          */
777         setup =
778                 /* IntSrc   = IntSrcB. */
779                 S626_SET_STD_INTSRC(S626_GET_CRB_INTSRC_B(crb)) |
780                 /* LatchSrc = LatchSrcB. */
781                 S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) |
782                 /* LoadSrc  = LoadSrcB. */
783                 S626_SET_STD_LOADSRC(S626_GET_CRB_LOADSRC_B(crb)) |
784                 /* IndxPol  = IndxPolB. */
785                 S626_SET_STD_INDXPOL(S626_GET_CRB_INDXPOL_B(crb)) |
786                 /* ClkEnab  = ClkEnabB. */
787                 S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_B(crb)) |
788                 /* IndxSrc  = IndxSrcB. */
789                 S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_B(cra));
790 
791         /* Adjust mode-dependent parameters. */
792         cntsrc = S626_GET_CRA_CNTSRC_B(cra);
793         clkmult = S626_GET_CRB_CLKMULT_B(crb);
794         if (clkmult == S626_CLKMULT_SPECIAL) {
795                 /* Extender mode (ClkMultB == S626_CLKMULT_SPECIAL): */
796                 encmode = S626_ENCMODE_EXTENDER;
797                 /* Indicate multiplier is 1x. */
798                 clkmult = S626_CLKMULT_1X;
799                 /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
800                 clkpol = cntsrc & 1;
801         } else if (cntsrc & S626_CNTSRC_SYSCLK) {
802                 /* Timer mode (CntSrcB<1> == 1): */
803                 encmode = S626_ENCMODE_TIMER;
804                 /* Indicate multiplier is 1x. */
805                 clkmult = S626_CLKMULT_1X;
806                 /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
807                 clkpol = cntsrc & 1;
808         } else {
809                 /* If Counter mode (CntSrcB<1> == 0): */
810                 encmode = S626_ENCMODE_COUNTER;
811                 /* Clock multiplier is passed through. */
812                 /* Clock polarity is passed through. */
813                 clkpol = S626_GET_CRB_CLKPOL_B(crb);
814         }
815         setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) |
816                  S626_SET_STD_CLKPOL(clkpol);
817 
818         /* Return adjusted counter setup. */
819         return setup;
820 }
821 
822 static uint16_t s626_get_mode(struct comedi_device *dev,
823                               unsigned int chan)
824 {
825         return (chan < 3) ? s626_get_mode_a(dev, chan)
826                           : s626_get_mode_b(dev, chan);
827 }
828 #endif
829 
830 /*
831  * Set the operating mode for the specified counter.  The setup
832  * parameter is treated as a COUNTER_SETUP data type.  The following
833  * parameters are programmable (all other parms are ignored): ClkMult,
834  * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
835  */
836 static void s626_set_mode_a(struct comedi_device *dev,
837                             unsigned int chan, uint16_t setup,
838                             uint16_t disable_int_src)
839 {
840         struct s626_private *devpriv = dev->private;
841         uint16_t cra;
842         uint16_t crb;
843         unsigned cntsrc, clkmult, clkpol;
844 
845         /* Initialize CRA and CRB images. */
846         /* Preload trigger is passed through. */
847         cra = S626_SET_CRA_LOADSRC_A(S626_GET_STD_LOADSRC(setup));
848         /* IndexSrc is passed through. */
849         cra |= S626_SET_CRA_INDXSRC_A(S626_GET_STD_INDXSRC(setup));
850 
851         /* Reset any pending CounterA event captures. */
852         crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_A(1);
853         /* Clock enable is passed through. */
854         crb |= S626_SET_CRB_CLKENAB_A(S626_GET_STD_CLKENAB(setup));
855 
856         /* Force IntSrc to Disabled if disable_int_src is asserted. */
857         if (!disable_int_src)
858                 cra |= S626_SET_CRA_INTSRC_A(S626_GET_STD_INTSRC(setup));
859 
860         /* Populate all mode-dependent attributes of CRA & CRB images. */
861         clkpol = S626_GET_STD_CLKPOL(setup);
862         switch (S626_GET_STD_ENCMODE(setup)) {
863         case S626_ENCMODE_EXTENDER: /* Extender Mode: */
864                 /* Force to Timer mode (Extender valid only for B counters). */
865                 /* Fall through to case S626_ENCMODE_TIMER: */
866         case S626_ENCMODE_TIMER:        /* Timer Mode: */
867                 /* CntSrcA<1> selects system clock */
868                 cntsrc = S626_CNTSRC_SYSCLK;
869                 /* Count direction (CntSrcA<0>) obtained from ClkPol. */
870                 cntsrc |= clkpol;
871                 /* ClkPolA behaves as always-on clock enable. */
872                 clkpol = 1;
873                 /* ClkMult must be 1x. */
874                 clkmult = S626_CLKMULT_1X;
875                 break;
876         default:                /* Counter Mode: */
877                 /* Select ENC_C and ENC_D as clock/direction inputs. */
878                 cntsrc = S626_CNTSRC_ENCODER;
879                 /* Clock polarity is passed through. */
880                 /* Force multiplier to x1 if not legal, else pass through. */
881                 clkmult = S626_GET_STD_CLKMULT(setup);
882                 if (clkmult == S626_CLKMULT_SPECIAL)
883                         clkmult = S626_CLKMULT_1X;
884                 break;
885         }
886         cra |= S626_SET_CRA_CNTSRC_A(cntsrc) | S626_SET_CRA_CLKPOL_A(clkpol) |
887                S626_SET_CRA_CLKMULT_A(clkmult);
888 
889         /*
890          * Force positive index polarity if IndxSrc is software-driven only,
891          * otherwise pass it through.
892          */
893         if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
894                 cra |= S626_SET_CRA_INDXPOL_A(S626_GET_STD_INDXPOL(setup));
895 
896         /*
897          * If IntSrc has been forced to Disabled, update the MISC2 interrupt
898          * enable mask to indicate the counter interrupt is disabled.
899          */
900         if (disable_int_src)
901                 devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
902                                                 S626_INDXMASK(chan));
903 
904         /*
905          * While retaining CounterB and LatchSrc configurations, program the
906          * new counter operating mode.
907          */
908         s626_debi_replace(dev, S626_LP_CRA(chan),
909                           S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B, cra);
910         s626_debi_replace(dev, S626_LP_CRB(chan),
911                           ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), crb);
912 }
913 
914 static void s626_set_mode_b(struct comedi_device *dev,
915                             unsigned int chan, uint16_t setup,
916                             uint16_t disable_int_src)
917 {
918         struct s626_private *devpriv = dev->private;
919         uint16_t cra;
920         uint16_t crb;
921         unsigned cntsrc, clkmult, clkpol;
922 
923         /* Initialize CRA and CRB images. */
924         /* IndexSrc is passed through. */
925         cra = S626_SET_CRA_INDXSRC_B(S626_GET_STD_INDXSRC(setup));
926 
927         /* Reset event captures and disable interrupts. */
928         crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_B(1);
929         /* Clock enable is passed through. */
930         crb |= S626_SET_CRB_CLKENAB_B(S626_GET_STD_CLKENAB(setup));
931         /* Preload trigger source is passed through. */
932         crb |= S626_SET_CRB_LOADSRC_B(S626_GET_STD_LOADSRC(setup));
933 
934         /* Force IntSrc to Disabled if disable_int_src is asserted. */
935         if (!disable_int_src)
936                 crb |= S626_SET_CRB_INTSRC_B(S626_GET_STD_INTSRC(setup));
937 
938         /* Populate all mode-dependent attributes of CRA & CRB images. */
939         clkpol = S626_GET_STD_CLKPOL(setup);
940         switch (S626_GET_STD_ENCMODE(setup)) {
941         case S626_ENCMODE_TIMER:        /* Timer Mode: */
942                 /* CntSrcB<1> selects system clock */
943                 cntsrc = S626_CNTSRC_SYSCLK;
944                 /* with direction (CntSrcB<0>) obtained from ClkPol. */
945                 cntsrc |= clkpol;
946                 /* ClkPolB behaves as always-on clock enable. */
947                 clkpol = 1;
948                 /* ClkMultB must be 1x. */
949                 clkmult = S626_CLKMULT_1X;
950                 break;
951         case S626_ENCMODE_EXTENDER:     /* Extender Mode: */
952                 /* CntSrcB source is OverflowA (same as "timer") */
953                 cntsrc = S626_CNTSRC_SYSCLK;
954                 /* with direction obtained from ClkPol. */
955                 cntsrc |= clkpol;
956                 /* ClkPolB controls IndexB -- always set to active. */
957                 clkpol = 1;
958                 /* ClkMultB selects OverflowA as the clock source. */
959                 clkmult = S626_CLKMULT_SPECIAL;
960                 break;
961         default:                /* Counter Mode: */
962                 /* Select ENC_C and ENC_D as clock/direction inputs. */
963                 cntsrc = S626_CNTSRC_ENCODER;
964                 /* ClkPol is passed through. */
965                 /* Force ClkMult to x1 if not legal, otherwise pass through. */
966                 clkmult = S626_GET_STD_CLKMULT(setup);
967                 if (clkmult == S626_CLKMULT_SPECIAL)
968                         clkmult = S626_CLKMULT_1X;
969                 break;
970         }
971         cra |= S626_SET_CRA_CNTSRC_B(cntsrc);
972         crb |= S626_SET_CRB_CLKPOL_B(clkpol) | S626_SET_CRB_CLKMULT_B(clkmult);
973 
974         /*
975          * Force positive index polarity if IndxSrc is software-driven only,
976          * otherwise pass it through.
977          */
978         if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
979                 crb |= S626_SET_CRB_INDXPOL_B(S626_GET_STD_INDXPOL(setup));
980 
981         /*
982          * If IntSrc has been forced to Disabled, update the MISC2 interrupt
983          * enable mask to indicate the counter interrupt is disabled.
984          */
985         if (disable_int_src)
986                 devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
987                                                 S626_INDXMASK(chan));
988 
989         /*
990          * While retaining CounterA and LatchSrc configurations, program the
991          * new counter operating mode.
992          */
993         s626_debi_replace(dev, S626_LP_CRA(chan),
994                           ~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B), cra);
995         s626_debi_replace(dev, S626_LP_CRB(chan),
996                           S626_CRBMSK_CLKENAB_A | S626_CRBMSK_LATCHSRC, crb);
997 }
998 
999 static void s626_set_mode(struct comedi_device *dev,
1000                           unsigned int chan,
1001                           uint16_t setup, uint16_t disable_int_src)
1002 {
1003         if (chan < 3)
1004                 s626_set_mode_a(dev, chan, setup, disable_int_src);
1005         else
1006                 s626_set_mode_b(dev, chan, setup, disable_int_src);
1007 }
1008 
1009 /*
1010  * Return/set a counter's enable.  enab: 0=always enabled, 1=enabled by index.
1011  */
1012 static void s626_set_enable(struct comedi_device *dev,
1013                             unsigned int chan, uint16_t enab)
1014 {
1015         unsigned int mask = S626_CRBMSK_INTCTRL;
1016         unsigned int set;
1017 
1018         if (chan < 3) {
1019                 mask |= S626_CRBMSK_CLKENAB_A;
1020                 set = S626_SET_CRB_CLKENAB_A(enab);
1021         } else {
1022                 mask |= S626_CRBMSK_CLKENAB_B;
1023                 set = S626_SET_CRB_CLKENAB_B(enab);
1024         }
1025         s626_debi_replace(dev, S626_LP_CRB(chan), ~mask, set);
1026 }
1027 
1028 #ifdef unused
1029 static uint16_t s626_get_enable(struct comedi_device *dev,
1030                                 unsigned int chan)
1031 {
1032         uint16_t crb = s626_debi_read(dev, S626_LP_CRB(chan));
1033 
1034         return (chan < 3) ? S626_GET_CRB_CLKENAB_A(crb)
1035                           : S626_GET_CRB_CLKENAB_B(crb);
1036 }
1037 #endif
1038 
1039 #ifdef unused
1040 static uint16_t s626_get_latch_source(struct comedi_device *dev,
1041                                       unsigned int chan)
1042 {
1043         return S626_GET_CRB_LATCHSRC(s626_debi_read(dev, S626_LP_CRB(chan)));
1044 }
1045 #endif
1046 
1047 /*
1048  * Return/set the event that will trigger transfer of the preload
1049  * register into the counter.  0=ThisCntr_Index, 1=ThisCntr_Overflow,
1050  * 2=OverflowA (B counters only), 3=disabled.
1051  */
1052 static void s626_set_load_trig(struct comedi_device *dev,
1053                                unsigned int chan, uint16_t trig)
1054 {
1055         uint16_t reg;
1056         uint16_t mask;
1057         uint16_t set;
1058 
1059         if (chan < 3) {
1060                 reg = S626_LP_CRA(chan);
1061                 mask = S626_CRAMSK_LOADSRC_A;
1062                 set = S626_SET_CRA_LOADSRC_A(trig);
1063         } else {
1064                 reg = S626_LP_CRB(chan);
1065                 mask = S626_CRBMSK_LOADSRC_B | S626_CRBMSK_INTCTRL;
1066                 set = S626_SET_CRB_LOADSRC_B(trig);
1067         }
1068         s626_debi_replace(dev, reg, ~mask, set);
1069 }
1070 
1071 #ifdef unused
1072 static uint16_t s626_get_load_trig(struct comedi_device *dev,
1073                                    unsigned int chan)
1074 {
1075         if (chan < 3)
1076                 return S626_GET_CRA_LOADSRC_A(s626_debi_read(dev,
1077                                                         S626_LP_CRA(chan)));
1078         else
1079                 return S626_GET_CRB_LOADSRC_B(s626_debi_read(dev,
1080                                                         S626_LP_CRB(chan)));
1081 }
1082 #endif
1083 
1084 /*
1085  * Return/set counter interrupt source and clear any captured
1086  * index/overflow events.  int_source: 0=Disabled, 1=OverflowOnly,
1087  * 2=IndexOnly, 3=IndexAndOverflow.
1088  */
1089 static void s626_set_int_src(struct comedi_device *dev,
1090                              unsigned int chan, uint16_t int_source)
1091 {
1092         struct s626_private *devpriv = dev->private;
1093         uint16_t cra_reg = S626_LP_CRA(chan);
1094         uint16_t crb_reg = S626_LP_CRB(chan);
1095 
1096         if (chan < 3) {
1097                 /* Reset any pending counter overflow or index captures */
1098                 s626_debi_replace(dev, crb_reg, ~S626_CRBMSK_INTCTRL,
1099                                   S626_SET_CRB_INTRESETCMD(1) |
1100                                   S626_SET_CRB_INTRESET_A(1));
1101 
1102                 /* Program counter interrupt source */
1103                 s626_debi_replace(dev, cra_reg, ~S626_CRAMSK_INTSRC_A,
1104                                   S626_SET_CRA_INTSRC_A(int_source));
1105         } else {
1106                 uint16_t crb;
1107 
1108                 /* Cache writeable CRB register image */
1109                 crb = s626_debi_read(dev, crb_reg);
1110                 crb &= ~S626_CRBMSK_INTCTRL;
1111 
1112                 /* Reset any pending counter overflow or index captures */
1113                 s626_debi_write(dev, crb_reg,
1114                                 crb | S626_SET_CRB_INTRESETCMD(1) |
1115                                 S626_SET_CRB_INTRESET_B(1));
1116 
1117                 /* Program counter interrupt source */
1118                 s626_debi_write(dev, crb_reg,
1119                                 (crb & ~S626_CRBMSK_INTSRC_B) |
1120                                 S626_SET_CRB_INTSRC_B(int_source));
1121         }
1122 
1123         /* Update MISC2 interrupt enable mask. */
1124         devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
1125                                         S626_INDXMASK(chan));
1126         switch (int_source) {
1127         case 0:
1128         default:
1129                 break;
1130         case 1:
1131                 devpriv->counter_int_enabs |= S626_OVERMASK(chan);
1132                 break;
1133         case 2:
1134                 devpriv->counter_int_enabs |= S626_INDXMASK(chan);
1135                 break;
1136         case 3:
1137                 devpriv->counter_int_enabs |= (S626_OVERMASK(chan) |
1138                                                S626_INDXMASK(chan));
1139                 break;
1140         }
1141 }
1142 
1143 #ifdef unused
1144 static uint16_t s626_get_int_src(struct comedi_device *dev,
1145                                  unsigned int chan)
1146 {
1147         if (chan < 3)
1148                 return S626_GET_CRA_INTSRC_A(s626_debi_read(dev,
1149                                                         S626_LP_CRA(chan)));
1150         else
1151                 return S626_GET_CRB_INTSRC_B(s626_debi_read(dev,
1152                                                         S626_LP_CRB(chan)));
1153 }
1154 #endif
1155 
1156 #ifdef unused
1157 /*
1158  * Return/set the clock multiplier.
1159  */
1160 static void s626_set_clk_mult(struct comedi_device *dev,
1161                               unsigned int chan, uint16_t value)
1162 {
1163         uint16_t mode;
1164 
1165         mode = s626_get_mode(dev, chan);
1166         mode &= ~S626_STDMSK_CLKMULT;
1167         mode |= S626_SET_STD_CLKMULT(value);
1168 
1169         s626_set_mode(dev, chan, mode, false);
1170 }
1171 
1172 static uint16_t s626_get_clk_mult(struct comedi_device *dev,
1173                                   unsigned int chan)
1174 {
1175         return S626_GET_STD_CLKMULT(s626_get_mode(dev, chan));
1176 }
1177 
1178 /*
1179  * Return/set the clock polarity.
1180  */
1181 static void s626_set_clk_pol(struct comedi_device *dev,
1182                              unsigned int chan, uint16_t value)
1183 {
1184         uint16_t mode;
1185 
1186         mode = s626_get_mode(dev, chan);
1187         mode &= ~S626_STDMSK_CLKPOL;
1188         mode |= S626_SET_STD_CLKPOL(value);
1189 
1190         s626_set_mode(dev, chan, mode, false);
1191 }
1192 
1193 static uint16_t s626_get_clk_pol(struct comedi_device *dev,
1194                                  unsigned int chan)
1195 {
1196         return S626_GET_STD_CLKPOL(s626_get_mode(dev, chan));
1197 }
1198 
1199 /*
1200  * Return/set the encoder mode.
1201  */
1202 static void s626_set_enc_mode(struct comedi_device *dev,
1203                               unsigned int chan, uint16_t value)
1204 {
1205         uint16_t mode;
1206 
1207         mode = s626_get_mode(dev, chan);
1208         mode &= ~S626_STDMSK_ENCMODE;
1209         mode |= S626_SET_STD_ENCMODE(value);
1210 
1211         s626_set_mode(dev, chan, mode, false);
1212 }
1213 
1214 static uint16_t s626_get_enc_mode(struct comedi_device *dev,
1215                                   unsigned int chan)
1216 {
1217         return S626_GET_STD_ENCMODE(s626_get_mode(dev, chan));
1218 }
1219 
1220 /*
1221  * Return/set the index polarity.
1222  */
1223 static void s626_set_index_pol(struct comedi_device *dev,
1224                                unsigned int chan, uint16_t value)
1225 {
1226         uint16_t mode;
1227 
1228         mode = s626_get_mode(dev, chan);
1229         mode &= ~S626_STDMSK_INDXPOL;
1230         mode |= S626_SET_STD_INDXPOL(value != 0);
1231 
1232         s626_set_mode(dev, chan, mode, false);
1233 }
1234 
1235 static uint16_t s626_get_index_pol(struct comedi_device *dev,
1236                                    unsigned int chan)
1237 {
1238         return S626_GET_STD_INDXPOL(s626_get_mode(dev, chan));
1239 }
1240 
1241 /*
1242  * Return/set the index source.
1243  */
1244 static void s626_set_index_src(struct comedi_device *dev,
1245                                unsigned int chan, uint16_t value)
1246 {
1247         uint16_t mode;
1248 
1249         mode = s626_get_mode(dev, chan);
1250         mode &= ~S626_STDMSK_INDXSRC;
1251         mode |= S626_SET_STD_INDXSRC(value != 0);
1252 
1253         s626_set_mode(dev, chan, mode, false);
1254 }
1255 
1256 static uint16_t s626_get_index_src(struct comedi_device *dev,
1257                                    unsigned int chan)
1258 {
1259         return S626_GET_STD_INDXSRC(s626_get_mode(dev, chan));
1260 }
1261 #endif
1262 
1263 /*
1264  * Generate an index pulse.
1265  */
1266 static void s626_pulse_index(struct comedi_device *dev,
1267                              unsigned int chan)
1268 {
1269         if (chan < 3) {
1270                 uint16_t cra;
1271 
1272                 cra = s626_debi_read(dev, S626_LP_CRA(chan));
1273 
1274                 /* Pulse index */
1275                 s626_debi_write(dev, S626_LP_CRA(chan),
1276                                 (cra ^ S626_CRAMSK_INDXPOL_A));
1277                 s626_debi_write(dev, S626_LP_CRA(chan), cra);
1278         } else {
1279                 uint16_t crb;
1280 
1281                 crb = s626_debi_read(dev, S626_LP_CRB(chan));
1282                 crb &= ~S626_CRBMSK_INTCTRL;
1283 
1284                 /* Pulse index */
1285                 s626_debi_write(dev, S626_LP_CRB(chan),
1286                                 (crb ^ S626_CRBMSK_INDXPOL_B));
1287                 s626_debi_write(dev, S626_LP_CRB(chan), crb);
1288         }
1289 }
1290 
1291 static unsigned int s626_ai_reg_to_uint(unsigned int data)
1292 {
1293         return ((data >> 18) & 0x3fff) ^ 0x2000;
1294 }
1295 
1296 static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
1297 {
1298         unsigned int group = chan / 16;
1299         unsigned int mask = 1 << (chan - (16 * group));
1300         unsigned int status;
1301 
1302         /* set channel to capture positive edge */
1303         status = s626_debi_read(dev, S626_LP_RDEDGSEL(group));
1304         s626_debi_write(dev, S626_LP_WREDGSEL(group), mask | status);
1305 
1306         /* enable interrupt on selected channel */
1307         status = s626_debi_read(dev, S626_LP_RDINTSEL(group));
1308         s626_debi_write(dev, S626_LP_WRINTSEL(group), mask | status);
1309 
1310         /* enable edge capture write command */
1311         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_EDCAP);
1312 
1313         /* enable edge capture on selected channel */
1314         status = s626_debi_read(dev, S626_LP_RDCAPSEL(group));
1315         s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask | status);
1316 
1317         return 0;
1318 }
1319 
1320 static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
1321                               unsigned int mask)
1322 {
1323         /* disable edge capture write command */
1324         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1325 
1326         /* enable edge capture on selected channel */
1327         s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask);
1328 
1329         return 0;
1330 }
1331 
1332 static int s626_dio_clear_irq(struct comedi_device *dev)
1333 {
1334         unsigned int group;
1335 
1336         /* disable edge capture write command */
1337         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1338 
1339         /* clear all dio pending events and interrupt */
1340         for (group = 0; group < S626_DIO_BANKS; group++)
1341                 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
1342 
1343         return 0;
1344 }
1345 
1346 static void s626_handle_dio_interrupt(struct comedi_device *dev,
1347                                       uint16_t irqbit, uint8_t group)
1348 {
1349         struct s626_private *devpriv = dev->private;
1350         struct comedi_subdevice *s = dev->read_subdev;
1351         struct comedi_cmd *cmd = &s->async->cmd;
1352 
1353         s626_dio_reset_irq(dev, group, irqbit);
1354 
1355         if (devpriv->ai_cmd_running) {
1356                 /* check if interrupt is an ai acquisition start trigger */
1357                 if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 &&
1358                     cmd->start_src == TRIG_EXT) {
1359                         /* Start executing the RPS program */
1360                         s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1361 
1362                         if (cmd->scan_begin_src == TRIG_EXT)
1363                                 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1364                 }
1365                 if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 &&
1366                     cmd->scan_begin_src == TRIG_EXT) {
1367                         /* Trigger ADC scan loop start */
1368                         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1369 
1370                         if (cmd->convert_src == TRIG_EXT) {
1371                                 devpriv->ai_convert_count = cmd->chanlist_len;
1372 
1373                                 s626_dio_set_irq(dev, cmd->convert_arg);
1374                         }
1375 
1376                         if (cmd->convert_src == TRIG_TIMER) {
1377                                 devpriv->ai_convert_count = cmd->chanlist_len;
1378                                 s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS);
1379                         }
1380                 }
1381                 if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 &&
1382                     cmd->convert_src == TRIG_EXT) {
1383                         /* Trigger ADC scan loop start */
1384                         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1385 
1386                         devpriv->ai_convert_count--;
1387                         if (devpriv->ai_convert_count > 0)
1388                                 s626_dio_set_irq(dev, cmd->convert_arg);
1389                 }
1390         }
1391 }
1392 
1393 static void s626_check_dio_interrupts(struct comedi_device *dev)
1394 {
1395         uint16_t irqbit;
1396         uint8_t group;
1397 
1398         for (group = 0; group < S626_DIO_BANKS; group++) {
1399                 /* read interrupt type */
1400                 irqbit = s626_debi_read(dev, S626_LP_RDCAPFLG(group));
1401 
1402                 /* check if interrupt is generated from dio channels */
1403                 if (irqbit) {
1404                         s626_handle_dio_interrupt(dev, irqbit, group);
1405                         return;
1406                 }
1407         }
1408 }
1409 
1410 static void s626_check_counter_interrupts(struct comedi_device *dev)
1411 {
1412         struct s626_private *devpriv = dev->private;
1413         struct comedi_subdevice *s = dev->read_subdev;
1414         struct comedi_async *async = s->async;
1415         struct comedi_cmd *cmd = &async->cmd;
1416         uint16_t irqbit;
1417 
1418         /* read interrupt type */
1419         irqbit = s626_debi_read(dev, S626_LP_RDMISC2);
1420 
1421         /* check interrupt on counters */
1422         if (irqbit & S626_IRQ_COINT1A) {
1423                 /* clear interrupt capture flag */
1424                 s626_reset_cap_flags(dev, 0);
1425         }
1426         if (irqbit & S626_IRQ_COINT2A) {
1427                 /* clear interrupt capture flag */
1428                 s626_reset_cap_flags(dev, 1);
1429         }
1430         if (irqbit & S626_IRQ_COINT3A) {
1431                 /* clear interrupt capture flag */
1432                 s626_reset_cap_flags(dev, 2);
1433         }
1434         if (irqbit & S626_IRQ_COINT1B) {
1435                 /* clear interrupt capture flag */
1436                 s626_reset_cap_flags(dev, 3);
1437         }
1438         if (irqbit & S626_IRQ_COINT2B) {
1439                 /* clear interrupt capture flag */
1440                 s626_reset_cap_flags(dev, 4);
1441 
1442                 if (devpriv->ai_convert_count > 0) {
1443                         devpriv->ai_convert_count--;
1444                         if (devpriv->ai_convert_count == 0)
1445                                 s626_set_enable(dev, 4, S626_CLKENAB_INDEX);
1446 
1447                         if (cmd->convert_src == TRIG_TIMER) {
1448                                 /* Trigger ADC scan loop start */
1449                                 s626_mc_enable(dev, S626_MC2_ADC_RPS,
1450                                                S626_P_MC2);
1451                         }
1452                 }
1453         }
1454         if (irqbit & S626_IRQ_COINT3B) {
1455                 /* clear interrupt capture flag */
1456                 s626_reset_cap_flags(dev, 5);
1457 
1458                 if (cmd->scan_begin_src == TRIG_TIMER) {
1459                         /* Trigger ADC scan loop start */
1460                         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1461                 }
1462 
1463                 if (cmd->convert_src == TRIG_TIMER) {
1464                         devpriv->ai_convert_count = cmd->chanlist_len;
1465                         s626_set_enable(dev, 4, S626_CLKENAB_ALWAYS);
1466                 }
1467         }
1468 }
1469 
1470 static bool s626_handle_eos_interrupt(struct comedi_device *dev)
1471 {
1472         struct s626_private *devpriv = dev->private;
1473         struct comedi_subdevice *s = dev->read_subdev;
1474         struct comedi_async *async = s->async;
1475         struct comedi_cmd *cmd = &async->cmd;
1476         /*
1477          * Init ptr to DMA buffer that holds new ADC data.  We skip the
1478          * first uint16_t in the buffer because it contains junk data
1479          * from the final ADC of the previous poll list scan.
1480          */
1481         uint32_t *readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1482         int i;
1483 
1484         /* get the data and hand it over to comedi */
1485         for (i = 0; i < cmd->chanlist_len; i++) {
1486                 unsigned short tempdata;
1487 
1488                 /*
1489                  * Convert ADC data to 16-bit integer values and copy
1490                  * to application buffer.
1491                  */
1492                 tempdata = s626_ai_reg_to_uint(*readaddr);
1493                 readaddr++;
1494 
1495                 comedi_buf_write_samples(s, &tempdata, 1);
1496         }
1497 
1498         if (cmd->stop_src == TRIG_COUNT && async->scans_done >= cmd->stop_arg)
1499                 async->events |= COMEDI_CB_EOA;
1500 
1501         if (async->events & COMEDI_CB_CANCEL_MASK)
1502                 devpriv->ai_cmd_running = 0;
1503 
1504         if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT)
1505                 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1506 
1507         comedi_handle_events(dev, s);
1508 
1509         return !devpriv->ai_cmd_running;
1510 }
1511 
1512 static irqreturn_t s626_irq_handler(int irq, void *d)
1513 {
1514         struct comedi_device *dev = d;
1515         unsigned long flags;
1516         uint32_t irqtype, irqstatus;
1517 
1518         if (!dev->attached)
1519                 return IRQ_NONE;
1520         /* lock to avoid race with comedi_poll */
1521         spin_lock_irqsave(&dev->spinlock, flags);
1522 
1523         /* save interrupt enable register state */
1524         irqstatus = readl(dev->mmio + S626_P_IER);
1525 
1526         /* read interrupt type */
1527         irqtype = readl(dev->mmio + S626_P_ISR);
1528 
1529         /* disable master interrupt */
1530         writel(0, dev->mmio + S626_P_IER);
1531 
1532         /* clear interrupt */
1533         writel(irqtype, dev->mmio + S626_P_ISR);
1534 
1535         switch (irqtype) {
1536         case S626_IRQ_RPS1:     /* end_of_scan occurs */
1537                 if (s626_handle_eos_interrupt(dev))
1538                         irqstatus = 0;
1539                 break;
1540         case S626_IRQ_GPIO3:    /* check dio and counter interrupt */
1541                 /* s626_dio_clear_irq(dev); */
1542                 s626_check_dio_interrupts(dev);
1543                 s626_check_counter_interrupts(dev);
1544                 break;
1545         }
1546 
1547         /* enable interrupt */
1548         writel(irqstatus, dev->mmio + S626_P_IER);
1549 
1550         spin_unlock_irqrestore(&dev->spinlock, flags);
1551         return IRQ_HANDLED;
1552 }
1553 
1554 /*
1555  * This function builds the RPS program for hardware driven acquisition.
1556  */
1557 static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl)
1558 {
1559         struct s626_private *devpriv = dev->private;
1560         struct comedi_subdevice *s = dev->read_subdev;
1561         struct comedi_cmd *cmd = &s->async->cmd;
1562         uint32_t *rps;
1563         uint32_t jmp_adrs;
1564         uint16_t i;
1565         uint16_t n;
1566         uint32_t local_ppl;
1567 
1568         /* Stop RPS program in case it is currently running */
1569         s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1570 
1571         /* Set starting logical address to write RPS commands. */
1572         rps = (uint32_t *)devpriv->rps_buf.logical_base;
1573 
1574         /* Initialize RPS instruction pointer */
1575         writel((uint32_t)devpriv->rps_buf.physical_base,
1576                dev->mmio + S626_P_RPSADDR1);
1577 
1578         /* Construct RPS program in rps_buf DMA buffer */
1579         if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
1580                 /* Wait for Start trigger. */
1581                 *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1582                 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1583         }
1584 
1585         /*
1586          * SAA7146 BUG WORKAROUND Do a dummy DEBI Write.  This is necessary
1587          * because the first RPS DEBI Write following a non-RPS DEBI write
1588          * seems to always fail.  If we don't do this dummy write, the ADC
1589          * gain might not be set to the value required for the first slot in
1590          * the poll list; the ADC gain would instead remain unchanged from
1591          * the previously programmed value.
1592          */
1593         /* Write DEBI Write command and address to shadow RAM. */
1594         *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1595         *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1596         *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1597         /* Write DEBI immediate data  to shadow RAM: */
1598         *rps++ = S626_GSEL_BIPOLAR5V;   /* arbitrary immediate data  value. */
1599         *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1600         /* Reset "shadow RAM  uploaded" flag. */
1601         /* Invoke shadow RAM upload. */
1602         *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1603         /* Wait for shadow upload to finish. */
1604         *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1605 
1606         /*
1607          * Digitize all slots in the poll list. This is implemented as a
1608          * for loop to limit the slot count to 16 in case the application
1609          * forgot to set the S626_EOPL flag in the final slot.
1610          */
1611         for (devpriv->adc_items = 0; devpriv->adc_items < 16;
1612              devpriv->adc_items++) {
1613                 /*
1614                  * Convert application's poll list item to private board class
1615                  * format.  Each app poll list item is an uint8_t with form
1616                  * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
1617                  * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
1618                  */
1619                 local_ppl = (*ppl << 8) | (*ppl & 0x10 ? S626_GSEL_BIPOLAR5V :
1620                                            S626_GSEL_BIPOLAR10V);
1621 
1622                 /* Switch ADC analog gain. */
1623                 /* Write DEBI command and address to shadow RAM. */
1624                 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1625                 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1626                 /* Write DEBI immediate data to shadow RAM. */
1627                 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1628                 *rps++ = local_ppl;
1629                 /* Reset "shadow RAM uploaded" flag. */
1630                 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1631                 /* Invoke shadow RAM upload. */
1632                 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1633                 /* Wait for shadow upload to finish. */
1634                 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1635                 /* Select ADC analog input channel. */
1636                 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1637                 /* Write DEBI command and address to shadow RAM. */
1638                 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_ISEL;
1639                 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1640                 /* Write DEBI immediate data to shadow RAM. */
1641                 *rps++ = local_ppl;
1642                 /* Reset "shadow RAM uploaded" flag. */
1643                 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1644                 /* Invoke shadow RAM upload. */
1645                 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1646                 /* Wait for shadow upload to finish. */
1647                 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1648 
1649                 /*
1650                  * Delay at least 10 microseconds for analog input settling.
1651                  * Instead of padding with NOPs, we use S626_RPS_JUMP
1652                  * instructions here; this allows us to produce a longer delay
1653                  * than is possible with NOPs because each S626_RPS_JUMP
1654                  * flushes the RPS' instruction prefetch pipeline.
1655                  */
1656                 jmp_adrs =
1657                         (uint32_t)devpriv->rps_buf.physical_base +
1658                         (uint32_t)((unsigned long)rps -
1659                                    (unsigned long)devpriv->
1660                                                   rps_buf.logical_base);
1661                 for (i = 0; i < (10 * S626_RPSCLK_PER_US / 2); i++) {
1662                         jmp_adrs += 8;  /* Repeat to implement time delay: */
1663                         /* Jump to next RPS instruction. */
1664                         *rps++ = S626_RPS_JUMP;
1665                         *rps++ = jmp_adrs;
1666                 }
1667 
1668                 if (cmd != NULL && cmd->convert_src != TRIG_NOW) {
1669                         /* Wait for Start trigger. */
1670                         *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1671                         *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1672                 }
1673                 /* Start ADC by pulsing GPIO1. */
1674                 /* Begin ADC Start pulse. */
1675                 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1676                 *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1677                 *rps++ = S626_RPS_NOP;
1678                 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1679                 /* End ADC Start pulse. */
1680                 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1681                 *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1682                 /*
1683                  * Wait for ADC to complete (GPIO2 is asserted high when ADC not
1684                  * busy) and for data from previous conversion to shift into FB
1685                  * BUFFER 1 register.
1686                  */
1687                 /* Wait for ADC done. */
1688                 *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;
1689 
1690                 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
1691                 *rps++ = S626_RPS_STREG |
1692                          (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1693                 *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1694                          (devpriv->adc_items << 2);
1695 
1696                 /*
1697                  * If this slot's EndOfPollList flag is set, all channels have
1698                  * now been processed.
1699                  */
1700                 if (*ppl++ & S626_EOPL) {
1701                         devpriv->adc_items++; /* Adjust poll list item count. */
1702                         break;  /* Exit poll list processing loop. */
1703                 }
1704         }
1705 
1706         /*
1707          * VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US.  Allow the
1708          * ADC to stabilize for 2 microseconds before starting the final
1709          * (dummy) conversion.  This delay is necessary to allow sufficient
1710          * time between last conversion finished and the start of the dummy
1711          * conversion.  Without this delay, the last conversion's data value
1712          * is sometimes set to the previous conversion's data value.
1713          */
1714         for (n = 0; n < (2 * S626_RPSCLK_PER_US); n++)
1715                 *rps++ = S626_RPS_NOP;
1716 
1717         /*
1718          * Start a dummy conversion to cause the data from the last
1719          * conversion of interest to be shifted in.
1720          */
1721         /* Begin ADC Start pulse. */
1722         *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1723         *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1724         *rps++ = S626_RPS_NOP;
1725         /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1726         *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); /* End ADC Start pulse. */
1727         *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1728 
1729         /*
1730          * Wait for the data from the last conversion of interest to arrive
1731          * in FB BUFFER 1 register.
1732          */
1733         *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;       /* Wait for ADC done. */
1734 
1735         /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1736         *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1737         *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1738                  (devpriv->adc_items << 2);
1739 
1740         /* Indicate ADC scan loop is finished. */
1741         /* Signal ReadADC() that scan is done. */
1742         /* *rps++= S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; */
1743 
1744         /* invoke interrupt */
1745         if (devpriv->ai_cmd_running == 1)
1746                 *rps++ = S626_RPS_IRQ;
1747 
1748         /* Restart RPS program at its beginning. */
1749         *rps++ = S626_RPS_JUMP; /* Branch to start of RPS program. */
1750         *rps++ = (uint32_t)devpriv->rps_buf.physical_base;
1751 
1752         /* End of RPS program build */
1753 }
1754 
1755 #ifdef unused_code
1756 static int s626_ai_rinsn(struct comedi_device *dev,
1757                          struct comedi_subdevice *s,
1758                          struct comedi_insn *insn,
1759                          unsigned int *data)
1760 {
1761         struct s626_private *devpriv = dev->private;
1762         uint8_t i;
1763         int32_t *readaddr;
1764 
1765         /* Trigger ADC scan loop start */
1766         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1767 
1768         /* Wait until ADC scan loop is finished (RPS Signal 0 reset) */
1769         while (s626_mc_test(dev, S626_MC2_ADC_RPS, S626_P_MC2))
1770                 ;
1771 
1772         /*
1773          * Init ptr to DMA buffer that holds new ADC data.  We skip the
1774          * first uint16_t in the buffer because it contains junk data from
1775          * the final ADC of the previous poll list scan.
1776          */
1777         readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1778 
1779         /*
1780          * Convert ADC data to 16-bit integer values and
1781          * copy to application buffer.
1782          */
1783         for (i = 0; i < devpriv->adc_items; i++) {
1784                 *data = s626_ai_reg_to_uint(*readaddr++);
1785                 data++;
1786         }
1787 
1788         return i;
1789 }
1790 #endif
1791 
1792 static int s626_ai_eoc(struct comedi_device *dev,
1793                        struct comedi_subdevice *s,
1794                        struct comedi_insn *insn,
1795                        unsigned long context)
1796 {
1797         unsigned int status;
1798 
1799         status = readl(dev->mmio + S626_P_PSR);
1800         if (status & S626_PSR_GPIO2)
1801                 return 0;
1802         return -EBUSY;
1803 }
1804 
1805 static int s626_ai_insn_read(struct comedi_device *dev,
1806                              struct comedi_subdevice *s,
1807                              struct comedi_insn *insn,
1808                              unsigned int *data)
1809 {
1810         uint16_t chan = CR_CHAN(insn->chanspec);
1811         uint16_t range = CR_RANGE(insn->chanspec);
1812         uint16_t adc_spec = 0;
1813         uint32_t gpio_image;
1814         uint32_t tmp;
1815         int ret;
1816         int n;
1817 
1818         /*
1819          * Convert application's ADC specification into form
1820          *  appropriate for register programming.
1821          */
1822         if (range == 0)
1823                 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR5V);
1824         else
1825                 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR10V);
1826 
1827         /* Switch ADC analog gain. */
1828         s626_debi_write(dev, S626_LP_GSEL, adc_spec);   /* Set gain. */
1829 
1830         /* Select ADC analog input channel. */
1831         s626_debi_write(dev, S626_LP_ISEL, adc_spec);   /* Select channel. */
1832 
1833         for (n = 0; n < insn->n; n++) {
1834                 /* Delay 10 microseconds for analog input settling. */
1835                 udelay(10);
1836 
1837                 /* Start ADC by pulsing GPIO1 low */
1838                 gpio_image = readl(dev->mmio + S626_P_GPIO);
1839                 /* Assert ADC Start command */
1840                 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1841                 /* and stretch it out */
1842                 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1843                 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1844                 /* Negate ADC Start command */
1845                 writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1846 
1847                 /*
1848                  * Wait for ADC to complete (GPIO2 is asserted high when
1849                  * ADC not busy) and for data from previous conversion to
1850                  * shift into FB BUFFER 1 register.
1851                  */
1852 
1853                 /* Wait for ADC done */
1854                 ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
1855                 if (ret)
1856                         return ret;
1857 
1858                 /* Fetch ADC data */
1859                 if (n != 0) {
1860                         tmp = readl(dev->mmio + S626_P_FB_BUFFER1);
1861                         data[n - 1] = s626_ai_reg_to_uint(tmp);
1862                 }
1863 
1864                 /*
1865                  * Allow the ADC to stabilize for 4 microseconds before
1866                  * starting the next (final) conversion.  This delay is
1867                  * necessary to allow sufficient time between last
1868                  * conversion finished and the start of the next
1869                  * conversion.  Without this delay, the last conversion's
1870                  * data value is sometimes set to the previous
1871                  * conversion's data value.
1872                  */
1873                 udelay(4);
1874         }
1875 
1876         /*
1877          * Start a dummy conversion to cause the data from the
1878          * previous conversion to be shifted in.
1879          */
1880         gpio_image = readl(dev->mmio + S626_P_GPIO);
1881         /* Assert ADC Start command */
1882         writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1883         /* and stretch it out */
1884         writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1885         writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1886         /* Negate ADC Start command */
1887         writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1888 
1889         /* Wait for the data to arrive in FB BUFFER 1 register. */
1890 
1891         /* Wait for ADC done */
1892         ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
1893         if (ret)
1894                 return ret;
1895 
1896         /* Fetch ADC data from audio interface's input shift register. */
1897 
1898         /* Fetch ADC data */
1899         if (n != 0) {
1900                 tmp = readl(dev->mmio + S626_P_FB_BUFFER1);
1901                 data[n - 1] = s626_ai_reg_to_uint(tmp);
1902         }
1903 
1904         return n;
1905 }
1906 
1907 static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd)
1908 {
1909         int n;
1910 
1911         for (n = 0; n < cmd->chanlist_len; n++) {
1912                 if (CR_RANGE(cmd->chanlist[n]) == 0)
1913                         ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_5V;
1914                 else
1915                         ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_10V;
1916         }
1917         if (n != 0)
1918                 ppl[n - 1] |= S626_EOPL;
1919 
1920         return n;
1921 }
1922 
1923 static int s626_ai_inttrig(struct comedi_device *dev,
1924                            struct comedi_subdevice *s,
1925                            unsigned int trig_num)
1926 {
1927         struct comedi_cmd *cmd = &s->async->cmd;
1928 
1929         if (trig_num != cmd->start_arg)
1930                 return -EINVAL;
1931 
1932         /* Start executing the RPS program */
1933         s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1934 
1935         s->async->inttrig = NULL;
1936 
1937         return 1;
1938 }
1939 
1940 /*
1941  * This function doesn't require a particular form, this is just what
1942  * happens to be used in some of the drivers.  It should convert ns
1943  * nanoseconds to a counter value suitable for programming the device.
1944  * Also, it should adjust ns so that it cooresponds to the actual time
1945  * that the device will use.
1946  */
1947 static int s626_ns_to_timer(unsigned int *nanosec, unsigned int flags)
1948 {
1949         int divider, base;
1950 
1951         base = 500;             /* 2MHz internal clock */
1952 
1953         switch (flags & CMDF_ROUND_MASK) {
1954         case CMDF_ROUND_NEAREST:
1955         default:
1956                 divider = DIV_ROUND_CLOSEST(*nanosec, base);
1957                 break;
1958         case CMDF_ROUND_DOWN:
1959                 divider = (*nanosec) / base;
1960                 break;
1961         case CMDF_ROUND_UP:
1962                 divider = DIV_ROUND_UP(*nanosec, base);
1963                 break;
1964         }
1965 
1966         *nanosec = base * divider;
1967         return divider - 1;
1968 }
1969 
1970 static void s626_timer_load(struct comedi_device *dev,
1971                             unsigned int chan, int tick)
1972 {
1973         uint16_t setup =
1974                 /* Preload upon index. */
1975                 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
1976                 /* Disable hardware index. */
1977                 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
1978                 /* Operating mode is Timer. */
1979                 S626_SET_STD_ENCMODE(S626_ENCMODE_TIMER) |
1980                 /* Count direction is Down. */
1981                 S626_SET_STD_CLKPOL(S626_CNTDIR_DOWN) |
1982                 /* Clock multiplier is 1x. */
1983                 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
1984                 /* Enabled by index */
1985                 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
1986         uint16_t value_latchsrc = S626_LATCHSRC_A_INDXA;
1987         /* uint16_t enab = S626_CLKENAB_ALWAYS; */
1988 
1989         s626_set_mode(dev, chan, setup, false);
1990 
1991         /* Set the preload register */
1992         s626_preload(dev, chan, tick);
1993 
1994         /*
1995          * Software index pulse forces the preload register to load
1996          * into the counter
1997          */
1998         s626_set_load_trig(dev, chan, 0);
1999         s626_pulse_index(dev, chan);
2000 
2001         /* set reload on counter overflow */
2002         s626_set_load_trig(dev, chan, 1);
2003 
2004         /* set interrupt on overflow */
2005         s626_set_int_src(dev, chan, S626_INTSRC_OVER);
2006 
2007         s626_set_latch_source(dev, chan, value_latchsrc);
2008         /* s626_set_enable(dev, chan, (uint16_t)(enab != 0)); */
2009 }
2010 
2011 /* TO COMPLETE  */
2012 static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2013 {
2014         struct s626_private *devpriv = dev->private;
2015         uint8_t ppl[16];
2016         struct comedi_cmd *cmd = &s->async->cmd;
2017         int tick;
2018 
2019         if (devpriv->ai_cmd_running) {
2020                 dev_err(dev->class_dev,
2021                         "s626_ai_cmd: Another ai_cmd is running\n");
2022                 return -EBUSY;
2023         }
2024         /* disable interrupt */
2025         writel(0, dev->mmio + S626_P_IER);
2026 
2027         /* clear interrupt request */
2028         writel(S626_IRQ_RPS1 | S626_IRQ_GPIO3, dev->mmio + S626_P_ISR);
2029 
2030         /* clear any pending interrupt */
2031         s626_dio_clear_irq(dev);
2032         /* s626_enc_clear_irq(dev); */
2033 
2034         /* reset ai_cmd_running flag */
2035         devpriv->ai_cmd_running = 0;
2036 
2037         /* test if cmd is valid */
2038         if (cmd == NULL)
2039                 return -EINVAL;
2040 
2041         s626_ai_load_polllist(ppl, cmd);
2042         devpriv->ai_cmd_running = 1;
2043         devpriv->ai_convert_count = 0;
2044 
2045         switch (cmd->scan_begin_src) {
2046         case TRIG_FOLLOW:
2047                 break;
2048         case TRIG_TIMER:
2049                 /*
2050                  * set a counter to generate adc trigger at scan_begin_arg
2051                  * interval
2052                  */
2053                 tick = s626_ns_to_timer(&cmd->scan_begin_arg, cmd->flags);
2054 
2055                 /* load timer value and enable interrupt */
2056                 s626_timer_load(dev, 5, tick);
2057                 s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS);
2058                 break;
2059         case TRIG_EXT:
2060                 /* set the digital line and interrupt for scan trigger */
2061                 if (cmd->start_src != TRIG_EXT)
2062                         s626_dio_set_irq(dev, cmd->scan_begin_arg);
2063                 break;
2064         }
2065 
2066         switch (cmd->convert_src) {
2067         case TRIG_NOW:
2068                 break;
2069         case TRIG_TIMER:
2070                 /*
2071                  * set a counter to generate adc trigger at convert_arg
2072                  * interval
2073                  */
2074                 tick = s626_ns_to_timer(&cmd->convert_arg, cmd->flags);
2075 
2076                 /* load timer value and enable interrupt */
2077                 s626_timer_load(dev, 4, tick);
2078                 s626_set_enable(dev, 4, S626_CLKENAB_INDEX);
2079                 break;
2080         case TRIG_EXT:
2081                 /* set the digital line and interrupt for convert trigger */
2082                 if (cmd->scan_begin_src != TRIG_EXT &&
2083                     cmd->start_src == TRIG_EXT)
2084                         s626_dio_set_irq(dev, cmd->convert_arg);
2085                 break;
2086         }
2087 
2088         s626_reset_adc(dev, ppl);
2089 
2090         switch (cmd->start_src) {
2091         case TRIG_NOW:
2092                 /* Trigger ADC scan loop start */
2093                 /* s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); */
2094 
2095                 /* Start executing the RPS program */
2096                 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
2097                 s->async->inttrig = NULL;
2098                 break;
2099         case TRIG_EXT:
2100                 /* configure DIO channel for acquisition trigger */
2101                 s626_dio_set_irq(dev, cmd->start_arg);
2102                 s->async->inttrig = NULL;
2103                 break;
2104         case TRIG_INT:
2105                 s->async->inttrig = s626_ai_inttrig;
2106                 break;
2107         }
2108 
2109         /* enable interrupt */
2110         writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, dev->mmio + S626_P_IER);
2111 
2112         return 0;
2113 }
2114 
2115 static int s626_ai_cmdtest(struct comedi_device *dev,
2116                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
2117 {
2118         int err = 0;
2119         unsigned int arg;
2120 
2121         /* Step 1 : check if triggers are trivially valid */
2122 
2123         err |= cfc_check_trigger_src(&cmd->start_src,
2124                                      TRIG_NOW | TRIG_INT | TRIG_EXT);
2125         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2126                                      TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW);
2127         err |= cfc_check_trigger_src(&cmd->convert_src,
2128                                      TRIG_TIMER | TRIG_EXT | TRIG_NOW);
2129         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2130         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2131 
2132         if (err)
2133                 return 1;
2134 
2135         /* Step 2a : make sure trigger sources are unique */
2136 
2137         err |= cfc_check_trigger_is_unique(cmd->start_src);
2138         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2139         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2140         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2141 
2142         /* Step 2b : and mutually compatible */
2143 
2144         if (err)
2145                 return 2;
2146 
2147         /* Step 3: check if arguments are trivially valid */
2148 
2149         switch (cmd->start_src) {
2150         case TRIG_NOW:
2151         case TRIG_INT:
2152                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2153                 break;
2154         case TRIG_EXT:
2155                 err |= cfc_check_trigger_arg_max(&cmd->start_arg, 39);
2156                 break;
2157         }
2158 
2159         if (cmd->scan_begin_src == TRIG_EXT)
2160                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 39);
2161         if (cmd->convert_src == TRIG_EXT)
2162                 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 39);
2163 
2164 #define S626_MAX_SPEED  200000  /* in nanoseconds */
2165 #define S626_MIN_SPEED  2000000000      /* in nanoseconds */
2166 
2167         if (cmd->scan_begin_src == TRIG_TIMER) {
2168                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2169                                                  S626_MAX_SPEED);
2170                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2171                                                  S626_MIN_SPEED);
2172         } else {
2173                 /* external trigger */
2174                 /* should be level/edge, hi/lo specification here */
2175                 /* should specify multiple external triggers */
2176                 /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
2177         }
2178         if (cmd->convert_src == TRIG_TIMER) {
2179                 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2180                                                  S626_MAX_SPEED);
2181                 err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2182                                                  S626_MIN_SPEED);
2183         } else {
2184                 /* external trigger */
2185                 /* see above */
2186                 /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
2187         }
2188 
2189         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2190 
2191         if (cmd->stop_src == TRIG_COUNT)
2192                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2193         else    /* TRIG_NONE */
2194                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2195 
2196         if (err)
2197                 return 3;
2198 
2199         /* step 4: fix up any arguments */
2200 
2201         if (cmd->scan_begin_src == TRIG_TIMER) {
2202                 arg = cmd->scan_begin_arg;
2203                 s626_ns_to_timer(&arg, cmd->flags);
2204                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
2205         }
2206 
2207         if (cmd->convert_src == TRIG_TIMER) {
2208                 arg = cmd->convert_arg;
2209                 s626_ns_to_timer(&arg, cmd->flags);
2210                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, arg);
2211 
2212                 if (cmd->scan_begin_src == TRIG_TIMER) {
2213                         arg = cmd->convert_arg * cmd->scan_end_arg;
2214                         err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2215                                                          arg);
2216                 }
2217         }
2218 
2219         if (err)
2220                 return 4;
2221 
2222         return 0;
2223 }
2224 
2225 static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
2226 {
2227         struct s626_private *devpriv = dev->private;
2228 
2229         /* Stop RPS program in case it is currently running */
2230         s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
2231 
2232         /* disable master interrupt */
2233         writel(0, dev->mmio + S626_P_IER);
2234 
2235         devpriv->ai_cmd_running = 0;
2236 
2237         return 0;
2238 }
2239 
2240 static int s626_ao_insn_write(struct comedi_device *dev,
2241                               struct comedi_subdevice *s,
2242                               struct comedi_insn *insn,
2243                               unsigned int *data)
2244 {
2245         unsigned int chan = CR_CHAN(insn->chanspec);
2246         int i;
2247 
2248         for (i = 0; i < insn->n; i++) {
2249                 int16_t dacdata = (int16_t)data[i];
2250                 int ret;
2251 
2252                 dacdata -= (0x1fff);
2253 
2254                 ret = s626_set_dac(dev, chan, dacdata);
2255                 if (ret)
2256                         return ret;
2257 
2258                 s->readback[chan] = data[i];
2259         }
2260 
2261         return insn->n;
2262 }
2263 
2264 /* *************** DIGITAL I/O FUNCTIONS *************** */
2265 
2266 /*
2267  * All DIO functions address a group of DIO channels by means of
2268  * "group" argument.  group may be 0, 1 or 2, which correspond to DIO
2269  * ports A, B and C, respectively.
2270  */
2271 
2272 static void s626_dio_init(struct comedi_device *dev)
2273 {
2274         uint16_t group;
2275 
2276         /* Prepare to treat writes to WRCapSel as capture disables. */
2277         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
2278 
2279         /* For each group of sixteen channels ... */
2280         for (group = 0; group < S626_DIO_BANKS; group++) {
2281                 /* Disable all interrupts */
2282                 s626_debi_write(dev, S626_LP_WRINTSEL(group), 0);
2283                 /* Disable all event captures */
2284                 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
2285                 /* Init all DIOs to default edge polarity */
2286                 s626_debi_write(dev, S626_LP_WREDGSEL(group), 0);
2287                 /* Program all outputs to inactive state */
2288                 s626_debi_write(dev, S626_LP_WRDOUT(group), 0);
2289         }
2290 }
2291 
2292 static int s626_dio_insn_bits(struct comedi_device *dev,
2293                               struct comedi_subdevice *s,
2294                               struct comedi_insn *insn,
2295                               unsigned int *data)
2296 {
2297         unsigned long group = (unsigned long)s->private;
2298 
2299         if (comedi_dio_update_state(s, data))
2300                 s626_debi_write(dev, S626_LP_WRDOUT(group), s->state);
2301 
2302         data[1] = s626_debi_read(dev, S626_LP_RDDIN(group));
2303 
2304         return insn->n;
2305 }
2306 
2307 static int s626_dio_insn_config(struct comedi_device *dev,
2308                                 struct comedi_subdevice *s,
2309                                 struct comedi_insn *insn,
2310                                 unsigned int *data)
2311 {
2312         unsigned long group = (unsigned long)s->private;
2313         int ret;
2314 
2315         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
2316         if (ret)
2317                 return ret;
2318 
2319         s626_debi_write(dev, S626_LP_WRDOUT(group), s->io_bits);
2320 
2321         return insn->n;
2322 }
2323 
2324 /*
2325  * Now this function initializes the value of the counter (data[0])
2326  * and set the subdevice. To complete with trigger and interrupt
2327  * configuration.
2328  *
2329  * FIXME: data[0] is supposed to be an INSN_CONFIG_xxx constant indicating
2330  * what is being configured, but this function appears to be using data[0]
2331  * as a variable.
2332  */
2333 static int s626_enc_insn_config(struct comedi_device *dev,
2334                                 struct comedi_subdevice *s,
2335                                 struct comedi_insn *insn, unsigned int *data)
2336 {
2337         unsigned int chan = CR_CHAN(insn->chanspec);
2338         uint16_t setup =
2339                 /* Preload upon index. */
2340                 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2341                 /* Disable hardware index. */
2342                 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2343                 /* Operating mode is Counter. */
2344                 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2345                 /* Active high clock. */
2346                 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2347                 /* Clock multiplier is 1x. */
2348                 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2349                 /* Enabled by index */
2350                 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2351         /* uint16_t disable_int_src = true; */
2352         /* uint32_t Preloadvalue;              //Counter initial value */
2353         uint16_t value_latchsrc = S626_LATCHSRC_AB_READ;
2354         uint16_t enab = S626_CLKENAB_ALWAYS;
2355 
2356         /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
2357 
2358         s626_set_mode(dev, chan, setup, true);
2359         s626_preload(dev, chan, data[0]);
2360         s626_pulse_index(dev, chan);
2361         s626_set_latch_source(dev, chan, value_latchsrc);
2362         s626_set_enable(dev, chan, (enab != 0));
2363 
2364         return insn->n;
2365 }
2366 
2367 static int s626_enc_insn_read(struct comedi_device *dev,
2368                               struct comedi_subdevice *s,
2369                               struct comedi_insn *insn,
2370                               unsigned int *data)
2371 {
2372         unsigned int chan = CR_CHAN(insn->chanspec);
2373         uint16_t cntr_latch_reg = S626_LP_CNTR(chan);
2374         int i;
2375 
2376         for (i = 0; i < insn->n; i++) {
2377                 unsigned int val;
2378 
2379                 /*
2380                  * Read the counter's output latch LSW/MSW.
2381                  * Latches on LSW read.
2382                  */
2383                 val = s626_debi_read(dev, cntr_latch_reg);
2384                 val |= (s626_debi_read(dev, cntr_latch_reg + 2) << 16);
2385                 data[i] = val;
2386         }
2387 
2388         return insn->n;
2389 }
2390 
2391 static int s626_enc_insn_write(struct comedi_device *dev,
2392                                struct comedi_subdevice *s,
2393                                struct comedi_insn *insn, unsigned int *data)
2394 {
2395         unsigned int chan = CR_CHAN(insn->chanspec);
2396 
2397         /* Set the preload register */
2398         s626_preload(dev, chan, data[0]);
2399 
2400         /*
2401          * Software index pulse forces the preload register to load
2402          * into the counter
2403          */
2404         s626_set_load_trig(dev, chan, 0);
2405         s626_pulse_index(dev, chan);
2406         s626_set_load_trig(dev, chan, 2);
2407 
2408         return 1;
2409 }
2410 
2411 static void s626_write_misc2(struct comedi_device *dev, uint16_t new_image)
2412 {
2413         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WENABLE);
2414         s626_debi_write(dev, S626_LP_WRMISC2, new_image);
2415         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WDISABLE);
2416 }
2417 
2418 static void s626_counters_init(struct comedi_device *dev)
2419 {
2420         int chan;
2421         uint16_t setup =
2422                 /* Preload upon index. */
2423                 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2424                 /* Disable hardware index. */
2425                 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2426                 /* Operating mode is counter. */
2427                 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2428                 /* Active high clock. */
2429                 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2430                 /* Clock multiplier is 1x. */
2431                 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2432                 /* Enabled by index */
2433                 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2434 
2435         /*
2436          * Disable all counter interrupts and clear any captured counter events.
2437          */
2438         for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
2439                 s626_set_mode(dev, chan, setup, true);
2440                 s626_set_int_src(dev, chan, 0);
2441                 s626_reset_cap_flags(dev, chan);
2442                 s626_set_enable(dev, chan, S626_CLKENAB_ALWAYS);
2443         }
2444 }
2445 
2446 static int s626_allocate_dma_buffers(struct comedi_device *dev)
2447 {
2448         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2449         struct s626_private *devpriv = dev->private;
2450         void *addr;
2451         dma_addr_t appdma;
2452 
2453         addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2454         if (!addr)
2455                 return -ENOMEM;
2456         devpriv->ana_buf.logical_base = addr;
2457         devpriv->ana_buf.physical_base = appdma;
2458 
2459         addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2460         if (!addr)
2461                 return -ENOMEM;
2462         devpriv->rps_buf.logical_base = addr;
2463         devpriv->rps_buf.physical_base = appdma;
2464 
2465         return 0;
2466 }
2467 
2468 static void s626_free_dma_buffers(struct comedi_device *dev)
2469 {
2470         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2471         struct s626_private *devpriv = dev->private;
2472 
2473         if (!devpriv)
2474                 return;
2475 
2476         if (devpriv->rps_buf.logical_base)
2477                 pci_free_consistent(pcidev, S626_DMABUF_SIZE,
2478                                     devpriv->rps_buf.logical_base,
2479                                     devpriv->rps_buf.physical_base);
2480         if (devpriv->ana_buf.logical_base)
2481                 pci_free_consistent(pcidev, S626_DMABUF_SIZE,
2482                                     devpriv->ana_buf.logical_base,
2483                                     devpriv->ana_buf.physical_base);
2484 }
2485 
2486 static int s626_initialize(struct comedi_device *dev)
2487 {
2488         struct s626_private *devpriv = dev->private;
2489         dma_addr_t phys_buf;
2490         uint16_t chan;
2491         int i;
2492         int ret;
2493 
2494         /* Enable DEBI and audio pins, enable I2C interface */
2495         s626_mc_enable(dev, S626_MC1_DEBI | S626_MC1_AUDIO | S626_MC1_I2C,
2496                        S626_P_MC1);
2497 
2498         /*
2499          * Configure DEBI operating mode
2500          *
2501          *  Local bus is 16 bits wide
2502          *  Declare DEBI transfer timeout interval
2503          *  Set up byte lane steering
2504          *  Intel-compatible local bus (DEBI never times out)
2505          */
2506         writel(S626_DEBI_CFG_SLAVE16 |
2507                (S626_DEBI_TOUT << S626_DEBI_CFG_TOUT_BIT) | S626_DEBI_SWAP |
2508                S626_DEBI_CFG_INTEL, dev->mmio + S626_P_DEBICFG);
2509 
2510         /* Disable MMU paging */
2511         writel(S626_DEBI_PAGE_DISABLE, dev->mmio + S626_P_DEBIPAGE);
2512 
2513         /* Init GPIO so that ADC Start* is negated */
2514         writel(S626_GPIO_BASE | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
2515 
2516         /* I2C device address for onboard eeprom (revb) */
2517         devpriv->i2c_adrs = 0xA0;
2518 
2519         /*
2520          * Issue an I2C ABORT command to halt any I2C
2521          * operation in progress and reset BUSY flag.
2522          */
2523         writel(S626_I2C_CLKSEL | S626_I2C_ABORT,
2524                dev->mmio + S626_P_I2CSTAT);
2525         s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2526         ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
2527         if (ret)
2528                 return ret;
2529 
2530         /*
2531          * Per SAA7146 data sheet, write to STATUS
2532          * reg twice to reset all  I2C error flags.
2533          */
2534         for (i = 0; i < 2; i++) {
2535                 writel(S626_I2C_CLKSEL, dev->mmio + S626_P_I2CSTAT);
2536                 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2537                 ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
2538                 if (ret)
2539                         return ret;
2540         }
2541 
2542         /*
2543          * Init audio interface functional attributes: set DAC/ADC
2544          * serial clock rates, invert DAC serial clock so that
2545          * DAC data setup times are satisfied, enable DAC serial
2546          * clock out.
2547          */
2548         writel(S626_ACON2_INIT, dev->mmio + S626_P_ACON2);
2549 
2550         /*
2551          * Set up TSL1 slot list, which is used to control the
2552          * accumulation of ADC data: S626_RSD1 = shift data in on SD1.
2553          * S626_SIB_A1  = store data uint8_t at next available location
2554          * in FB BUFFER1 register.
2555          */
2556         writel(S626_RSD1 | S626_SIB_A1, dev->mmio + S626_P_TSL1);
2557         writel(S626_RSD1 | S626_SIB_A1 | S626_EOS,
2558                dev->mmio + S626_P_TSL1 + 4);
2559 
2560         /* Enable TSL1 slot list so that it executes all the time */
2561         writel(S626_ACON1_ADCSTART, dev->mmio + S626_P_ACON1);
2562 
2563         /*
2564          * Initialize RPS registers used for ADC
2565          */
2566 
2567         /* Physical start of RPS program */
2568         writel((uint32_t)devpriv->rps_buf.physical_base,
2569                dev->mmio + S626_P_RPSADDR1);
2570         /* RPS program performs no explicit mem writes */
2571         writel(0, dev->mmio + S626_P_RPSPAGE1);
2572         /* Disable RPS timeouts */
2573         writel(0, dev->mmio + S626_P_RPS1_TOUT);
2574 
2575 #if 0
2576         /*
2577          * SAA7146 BUG WORKAROUND
2578          *
2579          * Initialize SAA7146 ADC interface to a known state by
2580          * invoking ADCs until FB BUFFER 1 register shows that it
2581          * is correctly receiving ADC data. This is necessary
2582          * because the SAA7146 ADC interface does not start up in
2583          * a defined state after a PCI reset.
2584          */
2585         {
2586                 struct comedi_subdevice *s = dev->read_subdev;
2587                 uint8_t poll_list;
2588                 uint16_t adc_data;
2589                 uint16_t start_val;
2590                 uint16_t index;
2591                 unsigned int data[16];
2592 
2593                 /* Create a simple polling list for analog input channel 0 */
2594                 poll_list = S626_EOPL;
2595                 s626_reset_adc(dev, &poll_list);
2596 
2597                 /* Get initial ADC value */
2598                 s626_ai_rinsn(dev, s, NULL, data);
2599                 start_val = data[0];
2600 
2601                 /*
2602                  * VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED
2603                  * EXECUTION.
2604                  *
2605                  * Invoke ADCs until the new ADC value differs from the initial
2606                  * value or a timeout occurs.  The timeout protects against the
2607                  * possibility that the driver is restarting and the ADC data is
2608                  * a fixed value resulting from the applied ADC analog input
2609                  * being unusually quiet or at the rail.
2610                  */
2611                 for (index = 0; index < 500; index++) {
2612                         s626_ai_rinsn(dev, s, NULL, data);
2613                         adc_data = data[0];
2614                         if (adc_data != start_val)
2615                                 break;
2616                 }
2617         }
2618 #endif  /* SAA7146 BUG WORKAROUND */
2619 
2620         /*
2621          * Initialize the DAC interface
2622          */
2623 
2624         /*
2625          * Init Audio2's output DMAC attributes:
2626          *   burst length = 1 DWORD
2627          *   threshold = 1 DWORD.
2628          */
2629         writel(0, dev->mmio + S626_P_PCI_BT_A);
2630 
2631         /*
2632          * Init Audio2's output DMA physical addresses.  The protection
2633          * address is set to 1 DWORD past the base address so that a
2634          * single DWORD will be transferred each time a DMA transfer is
2635          * enabled.
2636          */
2637         phys_buf = devpriv->ana_buf.physical_base +
2638                    (S626_DAC_WDMABUF_OS * sizeof(uint32_t));
2639         writel((uint32_t)phys_buf, dev->mmio + S626_P_BASEA2_OUT);
2640         writel((uint32_t)(phys_buf + sizeof(uint32_t)),
2641                dev->mmio + S626_P_PROTA2_OUT);
2642 
2643         /*
2644          * Cache Audio2's output DMA buffer logical address.  This is
2645          * where DAC data is buffered for A2 output DMA transfers.
2646          */
2647         devpriv->dac_wbuf = (uint32_t *)devpriv->ana_buf.logical_base +
2648                             S626_DAC_WDMABUF_OS;
2649 
2650         /*
2651          * Audio2's output channels does not use paging.  The
2652          * protection violation handling bit is set so that the
2653          * DMAC will automatically halt and its PCI address pointer
2654          * will be reset when the protection address is reached.
2655          */
2656         writel(8, dev->mmio + S626_P_PAGEA2_OUT);
2657 
2658         /*
2659          * Initialize time slot list 2 (TSL2), which is used to control
2660          * the clock generation for and serialization of data to be sent
2661          * to the DAC devices.  Slot 0 is a NOP that is used to trap TSL
2662          * execution; this permits other slots to be safely modified
2663          * without first turning off the TSL sequencer (which is
2664          * apparently impossible to do).  Also, SD3 (which is driven by a
2665          * pull-up resistor) is shifted in and stored to the MSB of
2666          * FB_BUFFER2 to be used as evidence that the slot sequence has
2667          * not yet finished executing.
2668          */
2669 
2670         /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */
2671         writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2 | S626_EOS,
2672                dev->mmio + S626_VECTPORT(0));
2673 
2674         /*
2675          * Initialize slot 1, which is constant.  Slot 1 causes a
2676          * DWORD to be transferred from audio channel 2's output FIFO
2677          * to the FIFO's output buffer so that it can be serialized
2678          * and sent to the DAC during subsequent slots.  All remaining
2679          * slots are dynamically populated as required by the target
2680          * DAC device.
2681          */
2682 
2683         /* Slot 1: Fetch DWORD from Audio2's output FIFO */
2684         writel(S626_LF_A2, dev->mmio + S626_VECTPORT(1));
2685 
2686         /* Start DAC's audio interface (TSL2) running */
2687         writel(S626_ACON1_DACSTART, dev->mmio + S626_P_ACON1);
2688 
2689         /*
2690          * Init Trim DACs to calibrated values.  Do it twice because the
2691          * SAA7146 audio channel does not always reset properly and
2692          * sometimes causes the first few TrimDAC writes to malfunction.
2693          */
2694         s626_load_trim_dacs(dev);
2695         ret = s626_load_trim_dacs(dev);
2696         if (ret)
2697                 return ret;
2698 
2699         /*
2700          * Manually init all gate array hardware in case this is a soft
2701          * reset (we have no way of determining whether this is a warm
2702          * or cold start).  This is necessary because the gate array will
2703          * reset only in response to a PCI hard reset; there is no soft
2704          * reset function.
2705          */
2706 
2707         /*
2708          * Init all DAC outputs to 0V and init all DAC setpoint and
2709          * polarity images.
2710          */
2711         for (chan = 0; chan < S626_DAC_CHANNELS; chan++) {
2712                 ret = s626_set_dac(dev, chan, 0);
2713                 if (ret)
2714                         return ret;
2715         }
2716 
2717         /* Init counters */
2718         s626_counters_init(dev);
2719 
2720         /*
2721          * Without modifying the state of the Battery Backup enab, disable
2722          * the watchdog timer, set DIO channels 0-5 to operate in the
2723          * standard DIO (vs. counter overflow) mode, disable the battery
2724          * charger, and reset the watchdog interval selector to zero.
2725          */
2726         s626_write_misc2(dev, (s626_debi_read(dev, S626_LP_RDMISC2) &
2727                                S626_MISC2_BATT_ENABLE));
2728 
2729         /* Initialize the digital I/O subsystem */
2730         s626_dio_init(dev);
2731 
2732         return 0;
2733 }
2734 
2735 static int s626_auto_attach(struct comedi_device *dev,
2736                                       unsigned long context_unused)
2737 {
2738         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2739         struct s626_private *devpriv;
2740         struct comedi_subdevice *s;
2741         int ret;
2742 
2743         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
2744         if (!devpriv)
2745                 return -ENOMEM;
2746 
2747         ret = comedi_pci_enable(dev);
2748         if (ret)
2749                 return ret;
2750 
2751         dev->mmio = pci_ioremap_bar(pcidev, 0);
2752         if (!dev->mmio)
2753                 return -ENOMEM;
2754 
2755         /* disable master interrupt */
2756         writel(0, dev->mmio + S626_P_IER);
2757 
2758         /* soft reset */
2759         writel(S626_MC1_SOFT_RESET, dev->mmio + S626_P_MC1);
2760 
2761         /* DMA FIXME DMA// */
2762 
2763         ret = s626_allocate_dma_buffers(dev);
2764         if (ret)
2765                 return ret;
2766 
2767         if (pcidev->irq) {
2768                 ret = request_irq(pcidev->irq, s626_irq_handler, IRQF_SHARED,
2769                                   dev->board_name, dev);
2770 
2771                 if (ret == 0)
2772                         dev->irq = pcidev->irq;
2773         }
2774 
2775         ret = comedi_alloc_subdevices(dev, 6);
2776         if (ret)
2777                 return ret;
2778 
2779         s = &dev->subdevices[0];
2780         /* analog input subdevice */
2781         s->type         = COMEDI_SUBD_AI;
2782         s->subdev_flags = SDF_READABLE | SDF_DIFF;
2783         s->n_chan       = S626_ADC_CHANNELS;
2784         s->maxdata      = 0x3fff;
2785         s->range_table  = &s626_range_table;
2786         s->len_chanlist = S626_ADC_CHANNELS;
2787         s->insn_read    = s626_ai_insn_read;
2788         if (dev->irq) {
2789                 dev->read_subdev = s;
2790                 s->subdev_flags |= SDF_CMD_READ;
2791                 s->do_cmd       = s626_ai_cmd;
2792                 s->do_cmdtest   = s626_ai_cmdtest;
2793                 s->cancel       = s626_ai_cancel;
2794         }
2795 
2796         s = &dev->subdevices[1];
2797         /* analog output subdevice */
2798         s->type         = COMEDI_SUBD_AO;
2799         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2800         s->n_chan       = S626_DAC_CHANNELS;
2801         s->maxdata      = 0x3fff;
2802         s->range_table  = &range_bipolar10;
2803         s->insn_write   = s626_ao_insn_write;
2804 
2805         ret = comedi_alloc_subdev_readback(s);
2806         if (ret)
2807                 return ret;
2808 
2809         s = &dev->subdevices[2];
2810         /* digital I/O subdevice */
2811         s->type         = COMEDI_SUBD_DIO;
2812         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2813         s->n_chan       = 16;
2814         s->maxdata      = 1;
2815         s->io_bits      = 0xffff;
2816         s->private      = (void *)0;    /* DIO group 0 */
2817         s->range_table  = &range_digital;
2818         s->insn_config  = s626_dio_insn_config;
2819         s->insn_bits    = s626_dio_insn_bits;
2820 
2821         s = &dev->subdevices[3];
2822         /* digital I/O subdevice */
2823         s->type         = COMEDI_SUBD_DIO;
2824         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2825         s->n_chan       = 16;
2826         s->maxdata      = 1;
2827         s->io_bits      = 0xffff;
2828         s->private      = (void *)1;    /* DIO group 1 */
2829         s->range_table  = &range_digital;
2830         s->insn_config  = s626_dio_insn_config;
2831         s->insn_bits    = s626_dio_insn_bits;
2832 
2833         s = &dev->subdevices[4];
2834         /* digital I/O subdevice */
2835         s->type         = COMEDI_SUBD_DIO;
2836         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2837         s->n_chan       = 16;
2838         s->maxdata      = 1;
2839         s->io_bits      = 0xffff;
2840         s->private      = (void *)2;    /* DIO group 2 */
2841         s->range_table  = &range_digital;
2842         s->insn_config  = s626_dio_insn_config;
2843         s->insn_bits    = s626_dio_insn_bits;
2844 
2845         s = &dev->subdevices[5];
2846         /* encoder (counter) subdevice */
2847         s->type         = COMEDI_SUBD_COUNTER;
2848         s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
2849         s->n_chan       = S626_ENCODER_CHANNELS;
2850         s->maxdata      = 0xffffff;
2851         s->range_table  = &range_unknown;
2852         s->insn_config  = s626_enc_insn_config;
2853         s->insn_read    = s626_enc_insn_read;
2854         s->insn_write   = s626_enc_insn_write;
2855 
2856         ret = s626_initialize(dev);
2857         if (ret)
2858                 return ret;
2859 
2860         return 0;
2861 }
2862 
2863 static void s626_detach(struct comedi_device *dev)
2864 {
2865         struct s626_private *devpriv = dev->private;
2866 
2867         if (devpriv) {
2868                 /* stop ai_command */
2869                 devpriv->ai_cmd_running = 0;
2870 
2871                 if (dev->mmio) {
2872                         /* interrupt mask */
2873                         /* Disable master interrupt */
2874                         writel(0, dev->mmio + S626_P_IER);
2875                         /* Clear board's IRQ status flag */
2876                         writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1,
2877                                dev->mmio + S626_P_ISR);
2878 
2879                         /* Disable the watchdog timer and battery charger. */
2880                         s626_write_misc2(dev, 0);
2881 
2882                         /* Close all interfaces on 7146 device */
2883                         writel(S626_MC1_SHUTDOWN, dev->mmio + S626_P_MC1);
2884                         writel(S626_ACON1_BASE, dev->mmio + S626_P_ACON1);
2885                 }
2886         }
2887         comedi_pci_detach(dev);
2888         s626_free_dma_buffers(dev);
2889 }
2890 
2891 static struct comedi_driver s626_driver = {
2892         .driver_name    = "s626",
2893         .module         = THIS_MODULE,
2894         .auto_attach    = s626_auto_attach,
2895         .detach         = s626_detach,
2896 };
2897 
2898 static int s626_pci_probe(struct pci_dev *dev,
2899                           const struct pci_device_id *id)
2900 {
2901         return comedi_pci_auto_config(dev, &s626_driver, id->driver_data);
2902 }
2903 
2904 /*
2905  * For devices with vendor:device id == 0x1131:0x7146 you must specify
2906  * also subvendor:subdevice ids, because otherwise it will conflict with
2907  * Philips SAA7146 media/dvb based cards.
2908  */
2909 static const struct pci_device_id s626_pci_table[] = {
2910         { PCI_DEVICE_SUB(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA7146,
2911                          0x6000, 0x0272) },
2912         { 0 }
2913 };
2914 MODULE_DEVICE_TABLE(pci, s626_pci_table);
2915 
2916 static struct pci_driver s626_pci_driver = {
2917         .name           = "s626",
2918         .id_table       = s626_pci_table,
2919         .probe          = s626_pci_probe,
2920         .remove         = comedi_pci_auto_unconfig,
2921 };
2922 module_comedi_pci_driver(s626_driver, s626_pci_driver);
2923 
2924 MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
2925 MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
2926 MODULE_LICENSE("GPL");
2927 

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