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Linux/drivers/staging/comedi/drivers/s626.c

  1 /*
  2  * comedi/drivers/s626.c
  3  * Sensoray s626 Comedi driver
  4  *
  5  * COMEDI - Linux Control and Measurement Device Interface
  6  * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
  7  *
  8  * Based on Sensoray Model 626 Linux driver Version 0.2
  9  * Copyright (C) 2002-2004 Sensoray Co., Inc.
 10  *
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License as published by
 13  * the Free Software Foundation; either version 2 of the License, or
 14  * (at your option) any later version.
 15  *
 16  * This program is distributed in the hope that it will be useful,
 17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19  * GNU General Public License for more details.
 20  */
 21 
 22 /*
 23  * Driver: s626
 24  * Description: Sensoray 626 driver
 25  * Devices: [Sensoray] 626 (s626)
 26  * Authors: Gianluca Palli <gpalli@deis.unibo.it>,
 27  * Updated: Fri, 15 Feb 2008 10:28:42 +0000
 28  * Status: experimental
 29 
 30  * Configuration options: not applicable, uses PCI auto config
 31 
 32  * INSN_CONFIG instructions:
 33  *   analog input:
 34  *    none
 35  *
 36  *   analog output:
 37  *    none
 38  *
 39  *   digital channel:
 40  *    s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
 41  *    supported configuration options:
 42  *    INSN_CONFIG_DIO_QUERY
 43  *    COMEDI_INPUT
 44  *    COMEDI_OUTPUT
 45  *
 46  *   encoder:
 47  *    Every channel must be configured before reading.
 48  *
 49  *   Example code
 50  *
 51  *    insn.insn=INSN_CONFIG;   //configuration instruction
 52  *    insn.n=1;                //number of operation (must be 1)
 53  *    insn.data=&initialvalue; //initial value loaded into encoder
 54  *                             //during configuration
 55  *    insn.subdev=5;           //encoder subdevice
 56  *    insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
 57  *                                                         //to configure
 58  *
 59  *    comedi_do_insn(cf,&insn); //executing configuration
 60  */
 61 
 62 #include <linux/module.h>
 63 #include <linux/delay.h>
 64 #include <linux/pci.h>
 65 #include <linux/interrupt.h>
 66 #include <linux/kernel.h>
 67 #include <linux/types.h>
 68 
 69 #include "../comedidev.h"
 70 
 71 #include "comedi_fc.h"
 72 #include "s626.h"
 73 
 74 struct s626_buffer_dma {
 75         dma_addr_t physical_base;
 76         void *logical_base;
 77 };
 78 
 79 struct s626_private {
 80         uint8_t ai_cmd_running;         /* ai_cmd is running */
 81         uint8_t ai_continuous;          /* continuous acquisition */
 82         int ai_sample_count;            /* number of samples to acquire */
 83         unsigned int ai_sample_timer;   /* time between samples in
 84                                          * units of the timer */
 85         int ai_convert_count;           /* conversion counter */
 86         unsigned int ai_convert_timer;  /* time between conversion in
 87                                          * units of the timer */
 88         uint16_t counter_int_enabs;     /* counter interrupt enable mask
 89                                          * for MISC2 register */
 90         uint8_t adc_items;              /* number of items in ADC poll list */
 91         struct s626_buffer_dma rps_buf; /* DMA buffer used to hold ADC (RPS1)
 92                                          * program */
 93         struct s626_buffer_dma ana_buf; /* DMA buffer used to receive ADC data
 94                                          * and hold DAC data */
 95         uint32_t *dac_wbuf;             /* pointer to logical adrs of DMA buffer
 96                                          * used to hold DAC data */
 97         uint16_t dacpol;                /* image of DAC polarity register */
 98         uint8_t trim_setpoint[12];      /* images of TrimDAC setpoints */
 99         uint32_t i2c_adrs;              /* I2C device address for onboard EEPROM
100                                          * (board rev dependent) */
101         unsigned int ao_readback[S626_DAC_CHANNELS];
102 };
103 
104 /* Counter overflow/index event flag masks for RDMISC2. */
105 #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 +  4)))
106 #define S626_OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
107 
108 /*
109  * Enable/disable a function or test status bit(s) that are accessed
110  * through Main Control Registers 1 or 2.
111  */
112 static void s626_mc_enable(struct comedi_device *dev,
113                            unsigned int cmd, unsigned int reg)
114 {
115         unsigned int val = (cmd << 16) | cmd;
116 
117         mmiowb();
118         writel(val, dev->mmio + reg);
119 }
120 
121 static void s626_mc_disable(struct comedi_device *dev,
122                             unsigned int cmd, unsigned int reg)
123 {
124         writel(cmd << 16 , dev->mmio + reg);
125         mmiowb();
126 }
127 
128 static bool s626_mc_test(struct comedi_device *dev,
129                          unsigned int cmd, unsigned int reg)
130 {
131         unsigned int val;
132 
133         val = readl(dev->mmio + reg);
134 
135         return (val & cmd) ? true : false;
136 }
137 
138 #define S626_BUGFIX_STREG(REGADRS)   ((REGADRS) - 4)
139 
140 /* Write a time slot control record to TSL2. */
141 #define S626_VECTPORT(VECTNUM)          (S626_P_TSL2 + ((VECTNUM) << 2))
142 
143 static const struct comedi_lrange s626_range_table = {
144         2, {
145                 BIP_RANGE(5),
146                 BIP_RANGE(10)
147         }
148 };
149 
150 /*
151  * Execute a DEBI transfer.  This must be called from within a critical section.
152  */
153 static void s626_debi_transfer(struct comedi_device *dev)
154 {
155         static const int timeout = 10000;
156         int i;
157 
158         /* Initiate upload of shadow RAM to DEBI control register */
159         s626_mc_enable(dev, S626_MC2_UPLD_DEBI, S626_P_MC2);
160 
161         /*
162          * Wait for completion of upload from shadow RAM to
163          * DEBI control register.
164          */
165         for (i = 0; i < timeout; i++) {
166                 if (s626_mc_test(dev, S626_MC2_UPLD_DEBI, S626_P_MC2))
167                         break;
168                 udelay(1);
169         }
170         if (i == timeout)
171                 dev_err(dev->class_dev,
172                         "Timeout while uploading to DEBI control register\n");
173 
174         /* Wait until DEBI transfer is done */
175         for (i = 0; i < timeout; i++) {
176                 if (!(readl(dev->mmio + S626_P_PSR) & S626_PSR_DEBI_S))
177                         break;
178                 udelay(1);
179         }
180         if (i == timeout)
181                 dev_err(dev->class_dev, "DEBI transfer timeout\n");
182 }
183 
184 /*
185  * Read a value from a gate array register.
186  */
187 static uint16_t s626_debi_read(struct comedi_device *dev, uint16_t addr)
188 {
189         /* Set up DEBI control register value in shadow RAM */
190         writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD);
191 
192         /*  Execute the DEBI transfer. */
193         s626_debi_transfer(dev);
194 
195         return readl(dev->mmio + S626_P_DEBIAD);
196 }
197 
198 /*
199  * Write a value to a gate array register.
200  */
201 static void s626_debi_write(struct comedi_device *dev, uint16_t addr,
202                             uint16_t wdata)
203 {
204         /* Set up DEBI control register value in shadow RAM */
205         writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD);
206         writel(wdata, dev->mmio + S626_P_DEBIAD);
207 
208         /*  Execute the DEBI transfer. */
209         s626_debi_transfer(dev);
210 }
211 
212 /*
213  * Replace the specified bits in a gate array register.  Imports: mask
214  * specifies bits that are to be preserved, wdata is new value to be
215  * or'd with the masked original.
216  */
217 static void s626_debi_replace(struct comedi_device *dev, unsigned int addr,
218                               unsigned int mask, unsigned int wdata)
219 {
220         unsigned int val;
221 
222         addr &= 0xffff;
223         writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD);
224         s626_debi_transfer(dev);
225 
226         writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD);
227         val = readl(dev->mmio + S626_P_DEBIAD);
228         val &= mask;
229         val |= wdata;
230         writel(val & 0xffff, dev->mmio + S626_P_DEBIAD);
231         s626_debi_transfer(dev);
232 }
233 
234 /* **************  EEPROM ACCESS FUNCTIONS  ************** */
235 
236 static int s626_i2c_handshake_eoc(struct comedi_device *dev,
237                                  struct comedi_subdevice *s,
238                                  struct comedi_insn *insn,
239                                  unsigned long context)
240 {
241         bool status;
242 
243         status = s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
244         if (status)
245                 return 0;
246         return -EBUSY;
247 }
248 
249 static int s626_i2c_handshake(struct comedi_device *dev, uint32_t val)
250 {
251         unsigned int ctrl;
252         int ret;
253 
254         /* Write I2C command to I2C Transfer Control shadow register */
255         writel(val, dev->mmio + S626_P_I2CCTRL);
256 
257         /*
258          * Upload I2C shadow registers into working registers and
259          * wait for upload confirmation.
260          */
261         s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
262         ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
263         if (ret)
264                 return ret;
265 
266         /* Wait until I2C bus transfer is finished or an error occurs */
267         do {
268                 ctrl = readl(dev->mmio + S626_P_I2CCTRL);
269         } while ((ctrl & (S626_I2C_BUSY | S626_I2C_ERR)) == S626_I2C_BUSY);
270 
271         /* Return non-zero if I2C error occurred */
272         return ctrl & S626_I2C_ERR;
273 }
274 
275 /* Read uint8_t from EEPROM. */
276 static uint8_t s626_i2c_read(struct comedi_device *dev, uint8_t addr)
277 {
278         struct s626_private *devpriv = dev->private;
279 
280         /*
281          * Send EEPROM target address:
282          *  Byte2 = I2C command: write to I2C EEPROM device.
283          *  Byte1 = EEPROM internal target address.
284          *  Byte0 = Not sent.
285          */
286         if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
287                                                 devpriv->i2c_adrs) |
288                                     S626_I2C_B1(S626_I2C_ATTRSTOP, addr) |
289                                     S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
290                 /* Abort function and declare error if handshake failed. */
291                 return 0;
292 
293         /*
294          * Execute EEPROM read:
295          *  Byte2 = I2C command: read from I2C EEPROM device.
296          *  Byte1 receives uint8_t from EEPROM.
297          *  Byte0 = Not sent.
298          */
299         if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
300                                            (devpriv->i2c_adrs | 1)) |
301                                     S626_I2C_B1(S626_I2C_ATTRSTOP, 0) |
302                                     S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
303                 /* Abort function and declare error if handshake failed. */
304                 return 0;
305 
306         return (readl(dev->mmio + S626_P_I2CCTRL) >> 16) & 0xff;
307 }
308 
309 /* ***********  DAC FUNCTIONS *********** */
310 
311 /* TrimDac LogicalChan-to-PhysicalChan mapping table. */
312 static const uint8_t s626_trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
313 
314 /* TrimDac LogicalChan-to-EepromAdrs mapping table. */
315 static const uint8_t s626_trimadrs[] = {
316         0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63
317 };
318 
319 enum {
320         s626_send_dac_wait_not_mc1_a2out,
321         s626_send_dac_wait_ssr_af2_out,
322         s626_send_dac_wait_fb_buffer2_msb_00,
323         s626_send_dac_wait_fb_buffer2_msb_ff
324 };
325 
326 static int s626_send_dac_eoc(struct comedi_device *dev,
327                              struct comedi_subdevice *s,
328                              struct comedi_insn *insn,
329                              unsigned long context)
330 {
331         unsigned int status;
332 
333         switch (context) {
334         case s626_send_dac_wait_not_mc1_a2out:
335                 status = readl(dev->mmio + S626_P_MC1);
336                 if (!(status & S626_MC1_A2OUT))
337                         return 0;
338                 break;
339         case s626_send_dac_wait_ssr_af2_out:
340                 status = readl(dev->mmio + S626_P_SSR);
341                 if (status & S626_SSR_AF2_OUT)
342                         return 0;
343                 break;
344         case s626_send_dac_wait_fb_buffer2_msb_00:
345                 status = readl(dev->mmio + S626_P_FB_BUFFER2);
346                 if (!(status & 0xff000000))
347                         return 0;
348                 break;
349         case s626_send_dac_wait_fb_buffer2_msb_ff:
350                 status = readl(dev->mmio + S626_P_FB_BUFFER2);
351                 if (status & 0xff000000)
352                         return 0;
353                 break;
354         default:
355                 return -EINVAL;
356         }
357         return -EBUSY;
358 }
359 
360 /*
361  * Private helper function: Transmit serial data to DAC via Audio
362  * channel 2.  Assumes: (1) TSL2 slot records initialized, and (2)
363  * dacpol contains valid target image.
364  */
365 static int s626_send_dac(struct comedi_device *dev, uint32_t val)
366 {
367         struct s626_private *devpriv = dev->private;
368         int ret;
369 
370         /* START THE SERIAL CLOCK RUNNING ------------- */
371 
372         /*
373          * Assert DAC polarity control and enable gating of DAC serial clock
374          * and audio bit stream signals.  At this point in time we must be
375          * assured of being in time slot 0.  If we are not in slot 0, the
376          * serial clock and audio stream signals will be disabled; this is
377          * because the following s626_debi_write statement (which enables
378          * signals to be passed through the gate array) would execute before
379          * the trailing edge of WS1/WS3 (which turns off the signals), thus
380          * causing the signals to be inactive during the DAC write.
381          */
382         s626_debi_write(dev, S626_LP_DACPOL, devpriv->dacpol);
383 
384         /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
385 
386         /* Copy DAC setpoint value to DAC's output DMA buffer. */
387         /* writel(val, dev->mmio + (uint32_t)devpriv->dac_wbuf); */
388         *devpriv->dac_wbuf = val;
389 
390         /*
391          * Enable the output DMA transfer. This will cause the DMAC to copy
392          * the DAC's data value to A2's output FIFO. The DMA transfer will
393          * then immediately terminate because the protection address is
394          * reached upon transfer of the first DWORD value.
395          */
396         s626_mc_enable(dev, S626_MC1_A2OUT, S626_P_MC1);
397 
398         /* While the DMA transfer is executing ... */
399 
400         /*
401          * Reset Audio2 output FIFO's underflow flag (along with any
402          * other FIFO underflow/overflow flags). When set, this flag
403          * will indicate that we have emerged from slot 0.
404          */
405         writel(S626_ISR_AFOU, dev->mmio + S626_P_ISR);
406 
407         /*
408          * Wait for the DMA transfer to finish so that there will be data
409          * available in the FIFO when time slot 1 tries to transfer a DWORD
410          * from the FIFO to the output buffer register.  We test for DMA
411          * Done by polling the DMAC enable flag; this flag is automatically
412          * cleared when the transfer has finished.
413          */
414         ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
415                              s626_send_dac_wait_not_mc1_a2out);
416         if (ret) {
417                 dev_err(dev->class_dev, "DMA transfer timeout\n");
418                 return ret;
419         }
420 
421         /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
422 
423         /*
424          * FIFO data is now available, so we enable execution of time slots
425          * 1 and higher by clearing the EOS flag in slot 0.  Note that SD3
426          * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
427          * detection.
428          */
429         writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2,
430                dev->mmio + S626_VECTPORT(0));
431 
432         /*
433          * Wait for slot 1 to execute to ensure that the Packet will be
434          * transmitted.  This is detected by polling the Audio2 output FIFO
435          * underflow flag, which will be set when slot 1 execution has
436          * finished transferring the DAC's data DWORD from the output FIFO
437          * to the output buffer register.
438          */
439         ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
440                              s626_send_dac_wait_ssr_af2_out);
441         if (ret) {
442                 dev_err(dev->class_dev,
443                         "TSL timeout waiting for slot 1 to execute\n");
444                 return ret;
445         }
446 
447         /*
448          * Set up to trap execution at slot 0 when the TSL sequencer cycles
449          * back to slot 0 after executing the EOS in slot 5.  Also,
450          * simultaneously shift out and in the 0x00 that is ALWAYS the value
451          * stored in the last byte to be shifted out of the FIFO's DWORD
452          * buffer register.
453          */
454         writel(S626_XSD2 | S626_XFIFO_2 | S626_RSD2 | S626_SIB_A2 | S626_EOS,
455                dev->mmio + S626_VECTPORT(0));
456 
457         /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
458 
459         /*
460          * Wait for the TSL to finish executing all time slots before
461          * exiting this function.  We must do this so that the next DAC
462          * write doesn't start, thereby enabling clock/chip select signals:
463          *
464          * 1. Before the TSL sequence cycles back to slot 0, which disables
465          *    the clock/cs signal gating and traps slot // list execution.
466          *    we have not yet finished slot 5 then the clock/cs signals are
467          *    still gated and we have not finished transmitting the stream.
468          *
469          * 2. While slots 2-5 are executing due to a late slot 0 trap.  In
470          *    this case, the slot sequence is currently repeating, but with
471          *    clock/cs signals disabled.  We must wait for slot 0 to trap
472          *    execution before setting up the next DAC setpoint DMA transfer
473          *    and enabling the clock/cs signals.  To detect the end of slot 5,
474          *    we test for the FB_BUFFER2 MSB contents to be equal to 0xFF.  If
475          *    the TSL has not yet finished executing slot 5 ...
476          */
477         if (readl(dev->mmio + S626_P_FB_BUFFER2) & 0xff000000) {
478                 /*
479                  * The trap was set on time and we are still executing somewhere
480                  * in slots 2-5, so we now wait for slot 0 to execute and trap
481                  * TSL execution.  This is detected when FB_BUFFER2 MSB changes
482                  * from 0xFF to 0x00, which slot 0 causes to happen by shifting
483                  * out/in on SD2 the 0x00 that is always referenced by slot 5.
484                  */
485                 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
486                                      s626_send_dac_wait_fb_buffer2_msb_00);
487                 if (ret) {
488                         dev_err(dev->class_dev,
489                                 "TSL timeout waiting for slot 0 to execute\n");
490                         return ret;
491                 }
492         }
493         /*
494          * Either (1) we were too late setting the slot 0 trap; the TSL
495          * sequencer restarted slot 0 before we could set the EOS trap flag,
496          * or (2) we were not late and execution is now trapped at slot 0.
497          * In either case, we must now change slot 0 so that it will store
498          * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
499          * In order to do this, we reprogram slot 0 so that it will shift in
500          * SD3, which is driven only by a pull-up resistor.
501          */
502         writel(S626_RSD3 | S626_SIB_A2 | S626_EOS,
503                dev->mmio + S626_VECTPORT(0));
504 
505         /*
506          * Wait for slot 0 to execute, at which time the TSL is setup for
507          * the next DAC write.  This is detected when FB_BUFFER2 MSB changes
508          * from 0x00 to 0xFF.
509          */
510         ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
511                              s626_send_dac_wait_fb_buffer2_msb_ff);
512         if (ret) {
513                 dev_err(dev->class_dev,
514                         "TSL timeout waiting for slot 0 to execute\n");
515                 return ret;
516         }
517         return 0;
518 }
519 
520 /*
521  * Private helper function: Write setpoint to an application DAC channel.
522  */
523 static int s626_set_dac(struct comedi_device *dev, uint16_t chan,
524                          int16_t dacdata)
525 {
526         struct s626_private *devpriv = dev->private;
527         uint16_t signmask;
528         uint32_t ws_image;
529         uint32_t val;
530 
531         /*
532          * Adjust DAC data polarity and set up Polarity Control Register image.
533          */
534         signmask = 1 << chan;
535         if (dacdata < 0) {
536                 dacdata = -dacdata;
537                 devpriv->dacpol |= signmask;
538         } else {
539                 devpriv->dacpol &= ~signmask;
540         }
541 
542         /* Limit DAC setpoint value to valid range. */
543         if ((uint16_t)dacdata > 0x1FFF)
544                 dacdata = 0x1FFF;
545 
546         /*
547          * Set up TSL2 records (aka "vectors") for DAC update.  Vectors V2
548          * and V3 transmit the setpoint to the target DAC.  V4 and V5 send
549          * data to a non-existent TrimDac channel just to keep the clock
550          * running after sending data to the target DAC.  This is necessary
551          * to eliminate the clock glitch that would otherwise occur at the
552          * end of the target DAC's serial data stream.  When the sequence
553          * restarts at V0 (after executing V5), the gate array automatically
554          * disables gating for the DAC clock and all DAC chip selects.
555          */
556 
557         /* Choose DAC chip select to be asserted */
558         ws_image = (chan & 2) ? S626_WS1 : S626_WS2;
559         /* Slot 2: Transmit high data byte to target DAC */
560         writel(S626_XSD2 | S626_XFIFO_1 | ws_image,
561                dev->mmio + S626_VECTPORT(2));
562         /* Slot 3: Transmit low data byte to target DAC */
563         writel(S626_XSD2 | S626_XFIFO_0 | ws_image,
564                dev->mmio + S626_VECTPORT(3));
565         /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
566         writel(S626_XSD2 | S626_XFIFO_3 | S626_WS3,
567                dev->mmio + S626_VECTPORT(4));
568         /* Slot 5: running after writing target DAC's low data byte */
569         writel(S626_XSD2 | S626_XFIFO_2 | S626_WS3 | S626_EOS,
570                dev->mmio + S626_VECTPORT(5));
571 
572         /*
573          * Construct and transmit target DAC's serial packet:
574          * (A10D DDDD), (DDDD DDDD), (0x0F), (0x00) where A is chan<0>,
575          * and D<12:0> is the DAC setpoint.  Append a WORD value (that writes
576          * to a  non-existent TrimDac channel) that serves to keep the clock
577          * running after the packet has been sent to the target DAC.
578          */
579         val = 0x0F000000;       /* Continue clock after target DAC data
580                                  * (write to non-existent trimdac). */
581         val |= 0x00004000;      /* Address the two main dual-DAC devices
582                                  * (TSL's chip select enables target device). */
583         val |= ((uint32_t)(chan & 1) << 15);    /* Address the DAC channel
584                                                  * within the device. */
585         val |= (uint32_t)dacdata;       /* Include DAC setpoint data. */
586         return s626_send_dac(dev, val);
587 }
588 
589 static int s626_write_trim_dac(struct comedi_device *dev, uint8_t logical_chan,
590                                 uint8_t dac_data)
591 {
592         struct s626_private *devpriv = dev->private;
593         uint32_t chan;
594 
595         /*
596          * Save the new setpoint in case the application needs to read it back
597          * later.
598          */
599         devpriv->trim_setpoint[logical_chan] = (uint8_t)dac_data;
600 
601         /* Map logical channel number to physical channel number. */
602         chan = s626_trimchan[logical_chan];
603 
604         /*
605          * Set up TSL2 records for TrimDac write operation.  All slots shift
606          * 0xFF in from pulled-up SD3 so that the end of the slot sequence
607          * can be detected.
608          */
609 
610         /* Slot 2: Send high uint8_t to target TrimDac */
611         writel(S626_XSD2 | S626_XFIFO_1 | S626_WS3,
612                dev->mmio + S626_VECTPORT(2));
613         /* Slot 3: Send low uint8_t to target TrimDac */
614         writel(S626_XSD2 | S626_XFIFO_0 | S626_WS3,
615                dev->mmio + S626_VECTPORT(3));
616         /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */
617         writel(S626_XSD2 | S626_XFIFO_3 | S626_WS1,
618                dev->mmio + S626_VECTPORT(4));
619         /* Slot 5: Send NOP low  uint8_t to DAC0 */
620         writel(S626_XSD2 | S626_XFIFO_2 | S626_WS1 | S626_EOS,
621                dev->mmio + S626_VECTPORT(5));
622 
623         /*
624          * Construct and transmit target DAC's serial packet:
625          * (0000 AAAA), (DDDD DDDD), (0x00), (0x00) where A<3:0> is the
626          * DAC channel's address, and D<7:0> is the DAC setpoint.  Append a
627          * WORD value (that writes a channel 0 NOP command to a non-existent
628          * main DAC channel) that serves to keep the clock running after the
629          * packet has been sent to the target DAC.
630          */
631 
632         /*
633          * Address the DAC channel within the trimdac device.
634          * Include DAC setpoint data.
635          */
636         return s626_send_dac(dev, (chan << 8) | dac_data);
637 }
638 
639 static int s626_load_trim_dacs(struct comedi_device *dev)
640 {
641         uint8_t i;
642         int ret;
643 
644         /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
645         for (i = 0; i < ARRAY_SIZE(s626_trimchan); i++) {
646                 ret = s626_write_trim_dac(dev, i,
647                                     s626_i2c_read(dev, s626_trimadrs[i]));
648                 if (ret)
649                         return ret;
650         }
651         return 0;
652 }
653 
654 /* ******  COUNTER FUNCTIONS  ******* */
655 
656 /*
657  * All counter functions address a specific counter by means of the
658  * "Counter" argument, which is a logical counter number.  The Counter
659  * argument may have any of the following legal values: 0=0A, 1=1A,
660  * 2=2A, 3=0B, 4=1B, 5=2B.
661  */
662 
663 /*
664  * Return/set a counter pair's latch trigger source.  0: On read
665  * access, 1: A index latches A, 2: B index latches B, 3: A overflow
666  * latches B.
667  */
668 static void s626_set_latch_source(struct comedi_device *dev,
669                                   unsigned int chan, uint16_t value)
670 {
671         s626_debi_replace(dev, S626_LP_CRB(chan),
672                           ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_LATCHSRC),
673                           S626_SET_CRB_LATCHSRC(value));
674 }
675 
676 /*
677  * Write value into counter preload register.
678  */
679 static void s626_preload(struct comedi_device *dev,
680                          unsigned int chan, uint32_t value)
681 {
682         s626_debi_write(dev, S626_LP_CNTR(chan), value);
683         s626_debi_write(dev, S626_LP_CNTR(chan) + 2, value >> 16);
684 }
685 
686 /* ******  PRIVATE COUNTER FUNCTIONS ****** */
687 
688 /*
689  * Reset a counter's index and overflow event capture flags.
690  */
691 static void s626_reset_cap_flags(struct comedi_device *dev,
692                                  unsigned int chan)
693 {
694         uint16_t set;
695 
696         set = S626_SET_CRB_INTRESETCMD(1);
697         if (chan < 3)
698                 set |= S626_SET_CRB_INTRESET_A(1);
699         else
700                 set |= S626_SET_CRB_INTRESET_B(1);
701 
702         s626_debi_replace(dev, S626_LP_CRB(chan), ~S626_CRBMSK_INTCTRL, set);
703 }
704 
705 #ifdef unused
706 /*
707  * Return counter setup in a format (COUNTER_SETUP) that is consistent
708  * for both A and B counters.
709  */
710 static uint16_t s626_get_mode_a(struct comedi_device *dev,
711                                 unsigned int chan)
712 {
713         uint16_t cra;
714         uint16_t crb;
715         uint16_t setup;
716         unsigned cntsrc, clkmult, clkpol, encmode;
717 
718         /* Fetch CRA and CRB register images. */
719         cra = s626_debi_read(dev, S626_LP_CRA(chan));
720         crb = s626_debi_read(dev, S626_LP_CRB(chan));
721 
722         /*
723          * Populate the standardized counter setup bit fields.
724          */
725         setup =
726                 /* LoadSrc  = LoadSrcA. */
727                 S626_SET_STD_LOADSRC(S626_GET_CRA_LOADSRC_A(cra)) |
728                 /* LatchSrc = LatchSrcA. */
729                 S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) |
730                 /* IntSrc   = IntSrcA. */
731                 S626_SET_STD_INTSRC(S626_GET_CRA_INTSRC_A(cra)) |
732                 /* IndxSrc  = IndxSrcA. */
733                 S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_A(cra)) |
734                 /* IndxPol  = IndxPolA. */
735                 S626_SET_STD_INDXPOL(S626_GET_CRA_INDXPOL_A(cra)) |
736                 /* ClkEnab  = ClkEnabA. */
737                 S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_A(crb));
738 
739         /* Adjust mode-dependent parameters. */
740         cntsrc = S626_GET_CRA_CNTSRC_A(cra);
741         if (cntsrc & S626_CNTSRC_SYSCLK) {
742                 /* Timer mode (CntSrcA<1> == 1): */
743                 encmode = S626_ENCMODE_TIMER;
744                 /* Set ClkPol to indicate count direction (CntSrcA<0>). */
745                 clkpol = cntsrc & 1;
746                 /* ClkMult must be 1x in Timer mode. */
747                 clkmult = S626_CLKMULT_1X;
748         } else {
749                 /* Counter mode (CntSrcA<1> == 0): */
750                 encmode = S626_ENCMODE_COUNTER;
751                 /* Pass through ClkPol. */
752                 clkpol = S626_GET_CRA_CLKPOL_A(cra);
753                 /* Force ClkMult to 1x if not legal, else pass through. */
754                 clkmult = S626_GET_CRA_CLKMULT_A(cra);
755                 if (clkmult == S626_CLKMULT_SPECIAL)
756                         clkmult = S626_CLKMULT_1X;
757         }
758         setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) |
759                  S626_SET_STD_CLKPOL(clkpol);
760 
761         /* Return adjusted counter setup. */
762         return setup;
763 }
764 
765 static uint16_t s626_get_mode_b(struct comedi_device *dev,
766                                 unsigned int chan)
767 {
768         uint16_t cra;
769         uint16_t crb;
770         uint16_t setup;
771         unsigned cntsrc, clkmult, clkpol, encmode;
772 
773         /* Fetch CRA and CRB register images. */
774         cra = s626_debi_read(dev, S626_LP_CRA(chan));
775         crb = s626_debi_read(dev, S626_LP_CRB(chan));
776 
777         /*
778          * Populate the standardized counter setup bit fields.
779          */
780         setup =
781                 /* IntSrc   = IntSrcB. */
782                 S626_SET_STD_INTSRC(S626_GET_CRB_INTSRC_B(crb)) |
783                 /* LatchSrc = LatchSrcB. */
784                 S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) |
785                 /* LoadSrc  = LoadSrcB. */
786                 S626_SET_STD_LOADSRC(S626_GET_CRB_LOADSRC_B(crb)) |
787                 /* IndxPol  = IndxPolB. */
788                 S626_SET_STD_INDXPOL(S626_GET_CRB_INDXPOL_B(crb)) |
789                 /* ClkEnab  = ClkEnabB. */
790                 S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_B(crb)) |
791                 /* IndxSrc  = IndxSrcB. */
792                 S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_B(cra));
793 
794         /* Adjust mode-dependent parameters. */
795         cntsrc = S626_GET_CRA_CNTSRC_B(cra);
796         clkmult = S626_GET_CRB_CLKMULT_B(crb);
797         if (clkmult == S626_CLKMULT_SPECIAL) {
798                 /* Extender mode (ClkMultB == S626_CLKMULT_SPECIAL): */
799                 encmode = S626_ENCMODE_EXTENDER;
800                 /* Indicate multiplier is 1x. */
801                 clkmult = S626_CLKMULT_1X;
802                 /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
803                 clkpol = cntsrc & 1;
804         } else if (cntsrc & S626_CNTSRC_SYSCLK) {
805                 /* Timer mode (CntSrcB<1> == 1): */
806                 encmode = S626_ENCMODE_TIMER;
807                 /* Indicate multiplier is 1x. */
808                 clkmult = S626_CLKMULT_1X;
809                 /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
810                 clkpol = cntsrc & 1;
811         } else {
812                 /* If Counter mode (CntSrcB<1> == 0): */
813                 encmode = S626_ENCMODE_COUNTER;
814                 /* Clock multiplier is passed through. */
815                 /* Clock polarity is passed through. */
816                 clkpol = S626_GET_CRB_CLKPOL_B(crb);
817         }
818         setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) |
819                  S626_SET_STD_CLKPOL(clkpol);
820 
821         /* Return adjusted counter setup. */
822         return setup;
823 }
824 
825 static uint16_t s626_get_mode(struct comedi_device *dev,
826                               unsigned int chan)
827 {
828         return (chan < 3) ? s626_get_mode_a(dev, chan)
829                           : s626_get_mode_b(dev, chan);
830 }
831 #endif
832 
833 /*
834  * Set the operating mode for the specified counter.  The setup
835  * parameter is treated as a COUNTER_SETUP data type.  The following
836  * parameters are programmable (all other parms are ignored): ClkMult,
837  * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
838  */
839 static void s626_set_mode_a(struct comedi_device *dev,
840                             unsigned int chan, uint16_t setup,
841                             uint16_t disable_int_src)
842 {
843         struct s626_private *devpriv = dev->private;
844         uint16_t cra;
845         uint16_t crb;
846         unsigned cntsrc, clkmult, clkpol;
847 
848         /* Initialize CRA and CRB images. */
849         /* Preload trigger is passed through. */
850         cra = S626_SET_CRA_LOADSRC_A(S626_GET_STD_LOADSRC(setup));
851         /* IndexSrc is passed through. */
852         cra |= S626_SET_CRA_INDXSRC_A(S626_GET_STD_INDXSRC(setup));
853 
854         /* Reset any pending CounterA event captures. */
855         crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_A(1);
856         /* Clock enable is passed through. */
857         crb |= S626_SET_CRB_CLKENAB_A(S626_GET_STD_CLKENAB(setup));
858 
859         /* Force IntSrc to Disabled if disable_int_src is asserted. */
860         if (!disable_int_src)
861                 cra |= S626_SET_CRA_INTSRC_A(S626_GET_STD_INTSRC(setup));
862 
863         /* Populate all mode-dependent attributes of CRA & CRB images. */
864         clkpol = S626_GET_STD_CLKPOL(setup);
865         switch (S626_GET_STD_ENCMODE(setup)) {
866         case S626_ENCMODE_EXTENDER: /* Extender Mode: */
867                 /* Force to Timer mode (Extender valid only for B counters). */
868                 /* Fall through to case S626_ENCMODE_TIMER: */
869         case S626_ENCMODE_TIMER:        /* Timer Mode: */
870                 /* CntSrcA<1> selects system clock */
871                 cntsrc = S626_CNTSRC_SYSCLK;
872                 /* Count direction (CntSrcA<0>) obtained from ClkPol. */
873                 cntsrc |= clkpol;
874                 /* ClkPolA behaves as always-on clock enable. */
875                 clkpol = 1;
876                 /* ClkMult must be 1x. */
877                 clkmult = S626_CLKMULT_1X;
878                 break;
879         default:                /* Counter Mode: */
880                 /* Select ENC_C and ENC_D as clock/direction inputs. */
881                 cntsrc = S626_CNTSRC_ENCODER;
882                 /* Clock polarity is passed through. */
883                 /* Force multiplier to x1 if not legal, else pass through. */
884                 clkmult = S626_GET_STD_CLKMULT(setup);
885                 if (clkmult == S626_CLKMULT_SPECIAL)
886                         clkmult = S626_CLKMULT_1X;
887                 break;
888         }
889         cra |= S626_SET_CRA_CNTSRC_A(cntsrc) | S626_SET_CRA_CLKPOL_A(clkpol) |
890                S626_SET_CRA_CLKMULT_A(clkmult);
891 
892         /*
893          * Force positive index polarity if IndxSrc is software-driven only,
894          * otherwise pass it through.
895          */
896         if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
897                 cra |= S626_SET_CRA_INDXPOL_A(S626_GET_STD_INDXPOL(setup));
898 
899         /*
900          * If IntSrc has been forced to Disabled, update the MISC2 interrupt
901          * enable mask to indicate the counter interrupt is disabled.
902          */
903         if (disable_int_src)
904                 devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
905                                                 S626_INDXMASK(chan));
906 
907         /*
908          * While retaining CounterB and LatchSrc configurations, program the
909          * new counter operating mode.
910          */
911         s626_debi_replace(dev, S626_LP_CRA(chan),
912                           S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B, cra);
913         s626_debi_replace(dev, S626_LP_CRB(chan),
914                           ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), crb);
915 }
916 
917 static void s626_set_mode_b(struct comedi_device *dev,
918                             unsigned int chan, uint16_t setup,
919                             uint16_t disable_int_src)
920 {
921         struct s626_private *devpriv = dev->private;
922         uint16_t cra;
923         uint16_t crb;
924         unsigned cntsrc, clkmult, clkpol;
925 
926         /* Initialize CRA and CRB images. */
927         /* IndexSrc is passed through. */
928         cra = S626_SET_CRA_INDXSRC_B(S626_GET_STD_INDXSRC(setup));
929 
930         /* Reset event captures and disable interrupts. */
931         crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_B(1);
932         /* Clock enable is passed through. */
933         crb |= S626_SET_CRB_CLKENAB_B(S626_GET_STD_CLKENAB(setup));
934         /* Preload trigger source is passed through. */
935         crb |= S626_SET_CRB_LOADSRC_B(S626_GET_STD_LOADSRC(setup));
936 
937         /* Force IntSrc to Disabled if disable_int_src is asserted. */
938         if (!disable_int_src)
939                 crb |= S626_SET_CRB_INTSRC_B(S626_GET_STD_INTSRC(setup));
940 
941         /* Populate all mode-dependent attributes of CRA & CRB images. */
942         clkpol = S626_GET_STD_CLKPOL(setup);
943         switch (S626_GET_STD_ENCMODE(setup)) {
944         case S626_ENCMODE_TIMER:        /* Timer Mode: */
945                 /* CntSrcB<1> selects system clock */
946                 cntsrc = S626_CNTSRC_SYSCLK;
947                 /* with direction (CntSrcB<0>) obtained from ClkPol. */
948                 cntsrc |= clkpol;
949                 /* ClkPolB behaves as always-on clock enable. */
950                 clkpol = 1;
951                 /* ClkMultB must be 1x. */
952                 clkmult = S626_CLKMULT_1X;
953                 break;
954         case S626_ENCMODE_EXTENDER:     /* Extender Mode: */
955                 /* CntSrcB source is OverflowA (same as "timer") */
956                 cntsrc = S626_CNTSRC_SYSCLK;
957                 /* with direction obtained from ClkPol. */
958                 cntsrc |= clkpol;
959                 /* ClkPolB controls IndexB -- always set to active. */
960                 clkpol = 1;
961                 /* ClkMultB selects OverflowA as the clock source. */
962                 clkmult = S626_CLKMULT_SPECIAL;
963                 break;
964         default:                /* Counter Mode: */
965                 /* Select ENC_C and ENC_D as clock/direction inputs. */
966                 cntsrc = S626_CNTSRC_ENCODER;
967                 /* ClkPol is passed through. */
968                 /* Force ClkMult to x1 if not legal, otherwise pass through. */
969                 clkmult = S626_GET_STD_CLKMULT(setup);
970                 if (clkmult == S626_CLKMULT_SPECIAL)
971                         clkmult = S626_CLKMULT_1X;
972                 break;
973         }
974         cra |= S626_SET_CRA_CNTSRC_B(cntsrc);
975         crb |= S626_SET_CRB_CLKPOL_B(clkpol) | S626_SET_CRB_CLKMULT_B(clkmult);
976 
977         /*
978          * Force positive index polarity if IndxSrc is software-driven only,
979          * otherwise pass it through.
980          */
981         if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
982                 crb |= S626_SET_CRB_INDXPOL_B(S626_GET_STD_INDXPOL(setup));
983 
984         /*
985          * If IntSrc has been forced to Disabled, update the MISC2 interrupt
986          * enable mask to indicate the counter interrupt is disabled.
987          */
988         if (disable_int_src)
989                 devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
990                                                 S626_INDXMASK(chan));
991 
992         /*
993          * While retaining CounterA and LatchSrc configurations, program the
994          * new counter operating mode.
995          */
996         s626_debi_replace(dev, S626_LP_CRA(chan),
997                           ~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B), cra);
998         s626_debi_replace(dev, S626_LP_CRB(chan),
999                           S626_CRBMSK_CLKENAB_A | S626_CRBMSK_LATCHSRC, crb);
1000 }
1001 
1002 static void s626_set_mode(struct comedi_device *dev,
1003                           unsigned int chan,
1004                           uint16_t setup, uint16_t disable_int_src)
1005 {
1006         if (chan < 3)
1007                 s626_set_mode_a(dev, chan, setup, disable_int_src);
1008         else
1009                 s626_set_mode_b(dev, chan, setup, disable_int_src);
1010 }
1011 
1012 /*
1013  * Return/set a counter's enable.  enab: 0=always enabled, 1=enabled by index.
1014  */
1015 static void s626_set_enable(struct comedi_device *dev,
1016                             unsigned int chan, uint16_t enab)
1017 {
1018         unsigned int mask = S626_CRBMSK_INTCTRL;
1019         unsigned int set;
1020 
1021         if (chan < 3) {
1022                 mask |= S626_CRBMSK_CLKENAB_A;
1023                 set = S626_SET_CRB_CLKENAB_A(enab);
1024         } else {
1025                 mask |= S626_CRBMSK_CLKENAB_B;
1026                 set = S626_SET_CRB_CLKENAB_B(enab);
1027         }
1028         s626_debi_replace(dev, S626_LP_CRB(chan), ~mask, set);
1029 }
1030 
1031 #ifdef unused
1032 static uint16_t s626_get_enable(struct comedi_device *dev,
1033                                 unsigned int chan)
1034 {
1035         uint16_t crb = s626_debi_read(dev, S626_LP_CRB(chan));
1036 
1037         return (chan < 3) ? S626_GET_CRB_CLKENAB_A(crb)
1038                           : S626_GET_CRB_CLKENAB_B(crb);
1039 }
1040 #endif
1041 
1042 #ifdef unused
1043 static uint16_t s626_get_latch_source(struct comedi_device *dev,
1044                                       unsigned int chan)
1045 {
1046         return S626_GET_CRB_LATCHSRC(s626_debi_read(dev, S626_LP_CRB(chan)));
1047 }
1048 #endif
1049 
1050 /*
1051  * Return/set the event that will trigger transfer of the preload
1052  * register into the counter.  0=ThisCntr_Index, 1=ThisCntr_Overflow,
1053  * 2=OverflowA (B counters only), 3=disabled.
1054  */
1055 static void s626_set_load_trig(struct comedi_device *dev,
1056                                unsigned int chan, uint16_t trig)
1057 {
1058         uint16_t reg;
1059         uint16_t mask;
1060         uint16_t set;
1061 
1062         if (chan < 3) {
1063                 reg = S626_LP_CRA(chan);
1064                 mask = S626_CRAMSK_LOADSRC_A;
1065                 set = S626_SET_CRA_LOADSRC_A(trig);
1066         } else {
1067                 reg = S626_LP_CRB(chan);
1068                 mask = S626_CRBMSK_LOADSRC_B | S626_CRBMSK_INTCTRL;
1069                 set = S626_SET_CRB_LOADSRC_B(trig);
1070         }
1071         s626_debi_replace(dev, reg, ~mask, set);
1072 }
1073 
1074 #ifdef unused
1075 static uint16_t s626_get_load_trig(struct comedi_device *dev,
1076                                    unsigned int chan)
1077 {
1078         if (chan < 3)
1079                 return S626_GET_CRA_LOADSRC_A(s626_debi_read(dev,
1080                                                         S626_LP_CRA(chan)));
1081         else
1082                 return S626_GET_CRB_LOADSRC_B(s626_debi_read(dev,
1083                                                         S626_LP_CRB(chan)));
1084 }
1085 #endif
1086 
1087 /*
1088  * Return/set counter interrupt source and clear any captured
1089  * index/overflow events.  int_source: 0=Disabled, 1=OverflowOnly,
1090  * 2=IndexOnly, 3=IndexAndOverflow.
1091  */
1092 static void s626_set_int_src(struct comedi_device *dev,
1093                              unsigned int chan, uint16_t int_source)
1094 {
1095         struct s626_private *devpriv = dev->private;
1096         uint16_t cra_reg = S626_LP_CRA(chan);
1097         uint16_t crb_reg = S626_LP_CRB(chan);
1098 
1099         if (chan < 3) {
1100                 /* Reset any pending counter overflow or index captures */
1101                 s626_debi_replace(dev, crb_reg, ~S626_CRBMSK_INTCTRL,
1102                                   S626_SET_CRB_INTRESETCMD(1) |
1103                                   S626_SET_CRB_INTRESET_A(1));
1104 
1105                 /* Program counter interrupt source */
1106                 s626_debi_replace(dev, cra_reg, ~S626_CRAMSK_INTSRC_A,
1107                                   S626_SET_CRA_INTSRC_A(int_source));
1108         } else {
1109                 uint16_t crb;
1110 
1111                 /* Cache writeable CRB register image */
1112                 crb = s626_debi_read(dev, crb_reg);
1113                 crb &= ~S626_CRBMSK_INTCTRL;
1114 
1115                 /* Reset any pending counter overflow or index captures */
1116                 s626_debi_write(dev, crb_reg,
1117                                 crb | S626_SET_CRB_INTRESETCMD(1) |
1118                                 S626_SET_CRB_INTRESET_B(1));
1119 
1120                 /* Program counter interrupt source */
1121                 s626_debi_write(dev, crb_reg,
1122                                 (crb & ~S626_CRBMSK_INTSRC_B) |
1123                                 S626_SET_CRB_INTSRC_B(int_source));
1124         }
1125 
1126         /* Update MISC2 interrupt enable mask. */
1127         devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
1128                                         S626_INDXMASK(chan));
1129         switch (int_source) {
1130         case 0:
1131         default:
1132                 break;
1133         case 1:
1134                 devpriv->counter_int_enabs |= S626_OVERMASK(chan);
1135                 break;
1136         case 2:
1137                 devpriv->counter_int_enabs |= S626_INDXMASK(chan);
1138                 break;
1139         case 3:
1140                 devpriv->counter_int_enabs |= (S626_OVERMASK(chan) |
1141                                                S626_INDXMASK(chan));
1142                 break;
1143         }
1144 }
1145 
1146 #ifdef unused
1147 static uint16_t s626_get_int_src(struct comedi_device *dev,
1148                                  unsigned int chan)
1149 {
1150         if (chan < 3)
1151                 return S626_GET_CRA_INTSRC_A(s626_debi_read(dev,
1152                                                         S626_LP_CRA(chan)));
1153         else
1154                 return S626_GET_CRB_INTSRC_B(s626_debi_read(dev,
1155                                                         S626_LP_CRB(chan)));
1156 }
1157 #endif
1158 
1159 #ifdef unused
1160 /*
1161  * Return/set the clock multiplier.
1162  */
1163 static void s626_set_clk_mult(struct comedi_device *dev,
1164                               unsigned int chan, uint16_t value)
1165 {
1166         uint16_t mode;
1167 
1168         mode = s626_get_mode(dev, chan);
1169         mode &= ~S626_STDMSK_CLKMULT;
1170         mode |= S626_SET_STD_CLKMULT(value);
1171 
1172         s626_set_mode(dev, chan, mode, false);
1173 }
1174 
1175 static uint16_t s626_get_clk_mult(struct comedi_device *dev,
1176                                   unsigned int chan)
1177 {
1178         return S626_GET_STD_CLKMULT(s626_get_mode(dev, chan));
1179 }
1180 
1181 /*
1182  * Return/set the clock polarity.
1183  */
1184 static void s626_set_clk_pol(struct comedi_device *dev,
1185                              unsigned int chan, uint16_t value)
1186 {
1187         uint16_t mode;
1188 
1189         mode = s626_get_mode(dev, chan);
1190         mode &= ~S626_STDMSK_CLKPOL;
1191         mode |= S626_SET_STD_CLKPOL(value);
1192 
1193         s626_set_mode(dev, chan, mode, false);
1194 }
1195 
1196 static uint16_t s626_get_clk_pol(struct comedi_device *dev,
1197                                  unsigned int chan)
1198 {
1199         return S626_GET_STD_CLKPOL(s626_get_mode(dev, chan));
1200 }
1201 
1202 /*
1203  * Return/set the encoder mode.
1204  */
1205 static void s626_set_enc_mode(struct comedi_device *dev,
1206                               unsigned int chan, uint16_t value)
1207 {
1208         uint16_t mode;
1209 
1210         mode = s626_get_mode(dev, chan);
1211         mode &= ~S626_STDMSK_ENCMODE;
1212         mode |= S626_SET_STD_ENCMODE(value);
1213 
1214         s626_set_mode(dev, chan, mode, false);
1215 }
1216 
1217 static uint16_t s626_get_enc_mode(struct comedi_device *dev,
1218                                   unsigned int chan)
1219 {
1220         return S626_GET_STD_ENCMODE(s626_get_mode(dev, chan));
1221 }
1222 
1223 /*
1224  * Return/set the index polarity.
1225  */
1226 static void s626_set_index_pol(struct comedi_device *dev,
1227                                unsigned int chan, uint16_t value)
1228 {
1229         uint16_t mode;
1230 
1231         mode = s626_get_mode(dev, chan);
1232         mode &= ~S626_STDMSK_INDXPOL;
1233         mode |= S626_SET_STD_INDXPOL(value != 0);
1234 
1235         s626_set_mode(dev, chan, mode, false);
1236 }
1237 
1238 static uint16_t s626_get_index_pol(struct comedi_device *dev,
1239                                    unsigned int chan)
1240 {
1241         return S626_GET_STD_INDXPOL(s626_get_mode(dev, chan));
1242 }
1243 
1244 /*
1245  * Return/set the index source.
1246  */
1247 static void s626_set_index_src(struct comedi_device *dev,
1248                                unsigned int chan, uint16_t value)
1249 {
1250         uint16_t mode;
1251 
1252         mode = s626_get_mode(dev, chan);
1253         mode &= ~S626_STDMSK_INDXSRC;
1254         mode |= S626_SET_STD_INDXSRC(value != 0);
1255 
1256         s626_set_mode(dev, chan, mode, false);
1257 }
1258 
1259 static uint16_t s626_get_index_src(struct comedi_device *dev,
1260                                    unsigned int chan)
1261 {
1262         return S626_GET_STD_INDXSRC(s626_get_mode(dev, chan));
1263 }
1264 #endif
1265 
1266 /*
1267  * Generate an index pulse.
1268  */
1269 static void s626_pulse_index(struct comedi_device *dev,
1270                              unsigned int chan)
1271 {
1272         if (chan < 3) {
1273                 uint16_t cra;
1274 
1275                 cra = s626_debi_read(dev, S626_LP_CRA(chan));
1276 
1277                 /* Pulse index */
1278                 s626_debi_write(dev, S626_LP_CRA(chan),
1279                                 (cra ^ S626_CRAMSK_INDXPOL_A));
1280                 s626_debi_write(dev, S626_LP_CRA(chan), cra);
1281         } else {
1282                 uint16_t crb;
1283 
1284                 crb = s626_debi_read(dev, S626_LP_CRB(chan));
1285                 crb &= ~S626_CRBMSK_INTCTRL;
1286 
1287                 /* Pulse index */
1288                 s626_debi_write(dev, S626_LP_CRB(chan),
1289                                 (crb ^ S626_CRBMSK_INDXPOL_B));
1290                 s626_debi_write(dev, S626_LP_CRB(chan), crb);
1291         }
1292 }
1293 
1294 static unsigned int s626_ai_reg_to_uint(unsigned int data)
1295 {
1296         return ((data >> 18) & 0x3fff) ^ 0x2000;
1297 }
1298 
1299 static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
1300 {
1301         unsigned int group = chan / 16;
1302         unsigned int mask = 1 << (chan - (16 * group));
1303         unsigned int status;
1304 
1305         /* set channel to capture positive edge */
1306         status = s626_debi_read(dev, S626_LP_RDEDGSEL(group));
1307         s626_debi_write(dev, S626_LP_WREDGSEL(group), mask | status);
1308 
1309         /* enable interrupt on selected channel */
1310         status = s626_debi_read(dev, S626_LP_RDINTSEL(group));
1311         s626_debi_write(dev, S626_LP_WRINTSEL(group), mask | status);
1312 
1313         /* enable edge capture write command */
1314         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_EDCAP);
1315 
1316         /* enable edge capture on selected channel */
1317         status = s626_debi_read(dev, S626_LP_RDCAPSEL(group));
1318         s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask | status);
1319 
1320         return 0;
1321 }
1322 
1323 static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
1324                               unsigned int mask)
1325 {
1326         /* disable edge capture write command */
1327         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1328 
1329         /* enable edge capture on selected channel */
1330         s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask);
1331 
1332         return 0;
1333 }
1334 
1335 static int s626_dio_clear_irq(struct comedi_device *dev)
1336 {
1337         unsigned int group;
1338 
1339         /* disable edge capture write command */
1340         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1341 
1342         /* clear all dio pending events and interrupt */
1343         for (group = 0; group < S626_DIO_BANKS; group++)
1344                 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
1345 
1346         return 0;
1347 }
1348 
1349 static void s626_handle_dio_interrupt(struct comedi_device *dev,
1350                                       uint16_t irqbit, uint8_t group)
1351 {
1352         struct s626_private *devpriv = dev->private;
1353         struct comedi_subdevice *s = dev->read_subdev;
1354         struct comedi_cmd *cmd = &s->async->cmd;
1355 
1356         s626_dio_reset_irq(dev, group, irqbit);
1357 
1358         if (devpriv->ai_cmd_running) {
1359                 /* check if interrupt is an ai acquisition start trigger */
1360                 if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 &&
1361                     cmd->start_src == TRIG_EXT) {
1362                         /* Start executing the RPS program */
1363                         s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1364 
1365                         if (cmd->scan_begin_src == TRIG_EXT)
1366                                 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1367                 }
1368                 if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 &&
1369                     cmd->scan_begin_src == TRIG_EXT) {
1370                         /* Trigger ADC scan loop start */
1371                         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1372 
1373                         if (cmd->convert_src == TRIG_EXT) {
1374                                 devpriv->ai_convert_count = cmd->chanlist_len;
1375 
1376                                 s626_dio_set_irq(dev, cmd->convert_arg);
1377                         }
1378 
1379                         if (cmd->convert_src == TRIG_TIMER) {
1380                                 devpriv->ai_convert_count = cmd->chanlist_len;
1381                                 s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS);
1382                         }
1383                 }
1384                 if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 &&
1385                     cmd->convert_src == TRIG_EXT) {
1386                         /* Trigger ADC scan loop start */
1387                         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1388 
1389                         devpriv->ai_convert_count--;
1390                         if (devpriv->ai_convert_count > 0)
1391                                 s626_dio_set_irq(dev, cmd->convert_arg);
1392                 }
1393         }
1394 }
1395 
1396 static void s626_check_dio_interrupts(struct comedi_device *dev)
1397 {
1398         uint16_t irqbit;
1399         uint8_t group;
1400 
1401         for (group = 0; group < S626_DIO_BANKS; group++) {
1402                 irqbit = 0;
1403                 /* read interrupt type */
1404                 irqbit = s626_debi_read(dev, S626_LP_RDCAPFLG(group));
1405 
1406                 /* check if interrupt is generated from dio channels */
1407                 if (irqbit) {
1408                         s626_handle_dio_interrupt(dev, irqbit, group);
1409                         return;
1410                 }
1411         }
1412 }
1413 
1414 static void s626_check_counter_interrupts(struct comedi_device *dev)
1415 {
1416         struct s626_private *devpriv = dev->private;
1417         struct comedi_subdevice *s = dev->read_subdev;
1418         struct comedi_async *async = s->async;
1419         struct comedi_cmd *cmd = &async->cmd;
1420         uint16_t irqbit;
1421 
1422         /* read interrupt type */
1423         irqbit = s626_debi_read(dev, S626_LP_RDMISC2);
1424 
1425         /* check interrupt on counters */
1426         if (irqbit & S626_IRQ_COINT1A) {
1427                 /* clear interrupt capture flag */
1428                 s626_reset_cap_flags(dev, 0);
1429         }
1430         if (irqbit & S626_IRQ_COINT2A) {
1431                 /* clear interrupt capture flag */
1432                 s626_reset_cap_flags(dev, 1);
1433         }
1434         if (irqbit & S626_IRQ_COINT3A) {
1435                 /* clear interrupt capture flag */
1436                 s626_reset_cap_flags(dev, 2);
1437         }
1438         if (irqbit & S626_IRQ_COINT1B) {
1439                 /* clear interrupt capture flag */
1440                 s626_reset_cap_flags(dev, 3);
1441         }
1442         if (irqbit & S626_IRQ_COINT2B) {
1443                 /* clear interrupt capture flag */
1444                 s626_reset_cap_flags(dev, 4);
1445 
1446                 if (devpriv->ai_convert_count > 0) {
1447                         devpriv->ai_convert_count--;
1448                         if (devpriv->ai_convert_count == 0)
1449                                 s626_set_enable(dev, 4, S626_CLKENAB_INDEX);
1450 
1451                         if (cmd->convert_src == TRIG_TIMER) {
1452                                 /* Trigger ADC scan loop start */
1453                                 s626_mc_enable(dev, S626_MC2_ADC_RPS,
1454                                                S626_P_MC2);
1455                         }
1456                 }
1457         }
1458         if (irqbit & S626_IRQ_COINT3B) {
1459                 /* clear interrupt capture flag */
1460                 s626_reset_cap_flags(dev, 5);
1461 
1462                 if (cmd->scan_begin_src == TRIG_TIMER) {
1463                         /* Trigger ADC scan loop start */
1464                         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1465                 }
1466 
1467                 if (cmd->convert_src == TRIG_TIMER) {
1468                         devpriv->ai_convert_count = cmd->chanlist_len;
1469                         s626_set_enable(dev, 4, S626_CLKENAB_ALWAYS);
1470                 }
1471         }
1472 }
1473 
1474 static bool s626_handle_eos_interrupt(struct comedi_device *dev)
1475 {
1476         struct s626_private *devpriv = dev->private;
1477         struct comedi_subdevice *s = dev->read_subdev;
1478         struct comedi_async *async = s->async;
1479         struct comedi_cmd *cmd = &async->cmd;
1480         /*
1481          * Init ptr to DMA buffer that holds new ADC data.  We skip the
1482          * first uint16_t in the buffer because it contains junk data
1483          * from the final ADC of the previous poll list scan.
1484          */
1485         uint32_t *readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1486         bool finished = false;
1487         int i;
1488 
1489         /* get the data and hand it over to comedi */
1490         for (i = 0; i < cmd->chanlist_len; i++) {
1491                 unsigned short tempdata;
1492 
1493                 /*
1494                  * Convert ADC data to 16-bit integer values and copy
1495                  * to application buffer.
1496                  */
1497                 tempdata = s626_ai_reg_to_uint(*readaddr);
1498                 readaddr++;
1499 
1500                 /* put data into read buffer */
1501                 cfc_write_to_buffer(s, tempdata);
1502         }
1503 
1504         /* end of scan occurs */
1505         async->events |= COMEDI_CB_EOS;
1506 
1507         if (!devpriv->ai_continuous)
1508                 devpriv->ai_sample_count--;
1509         if (devpriv->ai_sample_count <= 0) {
1510                 devpriv->ai_cmd_running = 0;
1511 
1512                 /* Stop RPS program */
1513                 s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1514 
1515                 /* send end of acquisition */
1516                 async->events |= COMEDI_CB_EOA;
1517 
1518                 /* disable master interrupt */
1519                 finished = true;
1520         }
1521 
1522         if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT)
1523                 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1524 
1525         /* tell comedi that data is there */
1526         comedi_event(dev, s);
1527 
1528         return finished;
1529 }
1530 
1531 static irqreturn_t s626_irq_handler(int irq, void *d)
1532 {
1533         struct comedi_device *dev = d;
1534         unsigned long flags;
1535         uint32_t irqtype, irqstatus;
1536 
1537         if (!dev->attached)
1538                 return IRQ_NONE;
1539         /* lock to avoid race with comedi_poll */
1540         spin_lock_irqsave(&dev->spinlock, flags);
1541 
1542         /* save interrupt enable register state */
1543         irqstatus = readl(dev->mmio + S626_P_IER);
1544 
1545         /* read interrupt type */
1546         irqtype = readl(dev->mmio + S626_P_ISR);
1547 
1548         /* disable master interrupt */
1549         writel(0, dev->mmio + S626_P_IER);
1550 
1551         /* clear interrupt */
1552         writel(irqtype, dev->mmio + S626_P_ISR);
1553 
1554         switch (irqtype) {
1555         case S626_IRQ_RPS1:     /* end_of_scan occurs */
1556                 if (s626_handle_eos_interrupt(dev))
1557                         irqstatus = 0;
1558                 break;
1559         case S626_IRQ_GPIO3:    /* check dio and counter interrupt */
1560                 /* s626_dio_clear_irq(dev); */
1561                 s626_check_dio_interrupts(dev);
1562                 s626_check_counter_interrupts(dev);
1563                 break;
1564         }
1565 
1566         /* enable interrupt */
1567         writel(irqstatus, dev->mmio + S626_P_IER);
1568 
1569         spin_unlock_irqrestore(&dev->spinlock, flags);
1570         return IRQ_HANDLED;
1571 }
1572 
1573 /*
1574  * This function builds the RPS program for hardware driven acquisition.
1575  */
1576 static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl)
1577 {
1578         struct s626_private *devpriv = dev->private;
1579         struct comedi_subdevice *s = dev->read_subdev;
1580         struct comedi_cmd *cmd = &s->async->cmd;
1581         uint32_t *rps;
1582         uint32_t jmp_adrs;
1583         uint16_t i;
1584         uint16_t n;
1585         uint32_t local_ppl;
1586 
1587         /* Stop RPS program in case it is currently running */
1588         s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1589 
1590         /* Set starting logical address to write RPS commands. */
1591         rps = (uint32_t *)devpriv->rps_buf.logical_base;
1592 
1593         /* Initialize RPS instruction pointer */
1594         writel((uint32_t)devpriv->rps_buf.physical_base,
1595                dev->mmio + S626_P_RPSADDR1);
1596 
1597         /* Construct RPS program in rps_buf DMA buffer */
1598         if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
1599                 /* Wait for Start trigger. */
1600                 *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1601                 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1602         }
1603 
1604         /*
1605          * SAA7146 BUG WORKAROUND Do a dummy DEBI Write.  This is necessary
1606          * because the first RPS DEBI Write following a non-RPS DEBI write
1607          * seems to always fail.  If we don't do this dummy write, the ADC
1608          * gain might not be set to the value required for the first slot in
1609          * the poll list; the ADC gain would instead remain unchanged from
1610          * the previously programmed value.
1611          */
1612         /* Write DEBI Write command and address to shadow RAM. */
1613         *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1614         *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1615         *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1616         /* Write DEBI immediate data  to shadow RAM: */
1617         *rps++ = S626_GSEL_BIPOLAR5V;   /* arbitrary immediate data  value. */
1618         *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1619         /* Reset "shadow RAM  uploaded" flag. */
1620         /* Invoke shadow RAM upload. */
1621         *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1622         /* Wait for shadow upload to finish. */
1623         *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1624 
1625         /*
1626          * Digitize all slots in the poll list. This is implemented as a
1627          * for loop to limit the slot count to 16 in case the application
1628          * forgot to set the S626_EOPL flag in the final slot.
1629          */
1630         for (devpriv->adc_items = 0; devpriv->adc_items < 16;
1631              devpriv->adc_items++) {
1632                 /*
1633                  * Convert application's poll list item to private board class
1634                  * format.  Each app poll list item is an uint8_t with form
1635                  * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
1636                  * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
1637                  */
1638                 local_ppl = (*ppl << 8) | (*ppl & 0x10 ? S626_GSEL_BIPOLAR5V :
1639                                            S626_GSEL_BIPOLAR10V);
1640 
1641                 /* Switch ADC analog gain. */
1642                 /* Write DEBI command and address to shadow RAM. */
1643                 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1644                 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1645                 /* Write DEBI immediate data to shadow RAM. */
1646                 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1647                 *rps++ = local_ppl;
1648                 /* Reset "shadow RAM uploaded" flag. */
1649                 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1650                 /* Invoke shadow RAM upload. */
1651                 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1652                 /* Wait for shadow upload to finish. */
1653                 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1654                 /* Select ADC analog input channel. */
1655                 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1656                 /* Write DEBI command and address to shadow RAM. */
1657                 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_ISEL;
1658                 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1659                 /* Write DEBI immediate data to shadow RAM. */
1660                 *rps++ = local_ppl;
1661                 /* Reset "shadow RAM uploaded" flag. */
1662                 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1663                 /* Invoke shadow RAM upload. */
1664                 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1665                 /* Wait for shadow upload to finish. */
1666                 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1667 
1668                 /*
1669                  * Delay at least 10 microseconds for analog input settling.
1670                  * Instead of padding with NOPs, we use S626_RPS_JUMP
1671                  * instructions here; this allows us to produce a longer delay
1672                  * than is possible with NOPs because each S626_RPS_JUMP
1673                  * flushes the RPS' instruction prefetch pipeline.
1674                  */
1675                 jmp_adrs =
1676                         (uint32_t)devpriv->rps_buf.physical_base +
1677                         (uint32_t)((unsigned long)rps -
1678                                    (unsigned long)devpriv->
1679                                                   rps_buf.logical_base);
1680                 for (i = 0; i < (10 * S626_RPSCLK_PER_US / 2); i++) {
1681                         jmp_adrs += 8;  /* Repeat to implement time delay: */
1682                         /* Jump to next RPS instruction. */
1683                         *rps++ = S626_RPS_JUMP;
1684                         *rps++ = jmp_adrs;
1685                 }
1686 
1687                 if (cmd != NULL && cmd->convert_src != TRIG_NOW) {
1688                         /* Wait for Start trigger. */
1689                         *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1690                         *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1691                 }
1692                 /* Start ADC by pulsing GPIO1. */
1693                 /* Begin ADC Start pulse. */
1694                 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1695                 *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1696                 *rps++ = S626_RPS_NOP;
1697                 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1698                 /* End ADC Start pulse. */
1699                 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1700                 *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1701                 /*
1702                  * Wait for ADC to complete (GPIO2 is asserted high when ADC not
1703                  * busy) and for data from previous conversion to shift into FB
1704                  * BUFFER 1 register.
1705                  */
1706                 /* Wait for ADC done. */
1707                 *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;
1708 
1709                 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
1710                 *rps++ = S626_RPS_STREG |
1711                          (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1712                 *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1713                          (devpriv->adc_items << 2);
1714 
1715                 /*
1716                  * If this slot's EndOfPollList flag is set, all channels have
1717                  * now been processed.
1718                  */
1719                 if (*ppl++ & S626_EOPL) {
1720                         devpriv->adc_items++; /* Adjust poll list item count. */
1721                         break;  /* Exit poll list processing loop. */
1722                 }
1723         }
1724 
1725         /*
1726          * VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US.  Allow the
1727          * ADC to stabilize for 2 microseconds before starting the final
1728          * (dummy) conversion.  This delay is necessary to allow sufficient
1729          * time between last conversion finished and the start of the dummy
1730          * conversion.  Without this delay, the last conversion's data value
1731          * is sometimes set to the previous conversion's data value.
1732          */
1733         for (n = 0; n < (2 * S626_RPSCLK_PER_US); n++)
1734                 *rps++ = S626_RPS_NOP;
1735 
1736         /*
1737          * Start a dummy conversion to cause the data from the last
1738          * conversion of interest to be shifted in.
1739          */
1740         /* Begin ADC Start pulse. */
1741         *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1742         *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1743         *rps++ = S626_RPS_NOP;
1744         /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1745         *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); /* End ADC Start pulse. */
1746         *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1747 
1748         /*
1749          * Wait for the data from the last conversion of interest to arrive
1750          * in FB BUFFER 1 register.
1751          */
1752         *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;       /* Wait for ADC done. */
1753 
1754         /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1755         *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1756         *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1757                  (devpriv->adc_items << 2);
1758 
1759         /* Indicate ADC scan loop is finished. */
1760         /* Signal ReadADC() that scan is done. */
1761         /* *rps++= S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; */
1762 
1763         /* invoke interrupt */
1764         if (devpriv->ai_cmd_running == 1)
1765                 *rps++ = S626_RPS_IRQ;
1766 
1767         /* Restart RPS program at its beginning. */
1768         *rps++ = S626_RPS_JUMP; /* Branch to start of RPS program. */
1769         *rps++ = (uint32_t)devpriv->rps_buf.physical_base;
1770 
1771         /* End of RPS program build */
1772 }
1773 
1774 #ifdef unused_code
1775 static int s626_ai_rinsn(struct comedi_device *dev,
1776                          struct comedi_subdevice *s,
1777                          struct comedi_insn *insn,
1778                          unsigned int *data)
1779 {
1780         struct s626_private *devpriv = dev->private;
1781         uint8_t i;
1782         int32_t *readaddr;
1783 
1784         /* Trigger ADC scan loop start */
1785         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1786 
1787         /* Wait until ADC scan loop is finished (RPS Signal 0 reset) */
1788         while (s626_mc_test(dev, S626_MC2_ADC_RPS, S626_P_MC2))
1789                 ;
1790 
1791         /*
1792          * Init ptr to DMA buffer that holds new ADC data.  We skip the
1793          * first uint16_t in the buffer because it contains junk data from
1794          * the final ADC of the previous poll list scan.
1795          */
1796         readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1797 
1798         /*
1799          * Convert ADC data to 16-bit integer values and
1800          * copy to application buffer.
1801          */
1802         for (i = 0; i < devpriv->adc_items; i++) {
1803                 *data = s626_ai_reg_to_uint(*readaddr++);
1804                 data++;
1805         }
1806 
1807         return i;
1808 }
1809 #endif
1810 
1811 static int s626_ai_eoc(struct comedi_device *dev,
1812                        struct comedi_subdevice *s,
1813                        struct comedi_insn *insn,
1814                        unsigned long context)
1815 {
1816         unsigned int status;
1817 
1818         status = readl(dev->mmio + S626_P_PSR);
1819         if (status & S626_PSR_GPIO2)
1820                 return 0;
1821         return -EBUSY;
1822 }
1823 
1824 static int s626_ai_insn_read(struct comedi_device *dev,
1825                              struct comedi_subdevice *s,
1826                              struct comedi_insn *insn,
1827                              unsigned int *data)
1828 {
1829         uint16_t chan = CR_CHAN(insn->chanspec);
1830         uint16_t range = CR_RANGE(insn->chanspec);
1831         uint16_t adc_spec = 0;
1832         uint32_t gpio_image;
1833         uint32_t tmp;
1834         int ret;
1835         int n;
1836 
1837         /*
1838          * Convert application's ADC specification into form
1839          *  appropriate for register programming.
1840          */
1841         if (range == 0)
1842                 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR5V);
1843         else
1844                 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR10V);
1845 
1846         /* Switch ADC analog gain. */
1847         s626_debi_write(dev, S626_LP_GSEL, adc_spec);   /* Set gain. */
1848 
1849         /* Select ADC analog input channel. */
1850         s626_debi_write(dev, S626_LP_ISEL, adc_spec);   /* Select channel. */
1851 
1852         for (n = 0; n < insn->n; n++) {
1853                 /* Delay 10 microseconds for analog input settling. */
1854                 udelay(10);
1855 
1856                 /* Start ADC by pulsing GPIO1 low */
1857                 gpio_image = readl(dev->mmio + S626_P_GPIO);
1858                 /* Assert ADC Start command */
1859                 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1860                 /* and stretch it out */
1861                 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1862                 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1863                 /* Negate ADC Start command */
1864                 writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1865 
1866                 /*
1867                  * Wait for ADC to complete (GPIO2 is asserted high when
1868                  * ADC not busy) and for data from previous conversion to
1869                  * shift into FB BUFFER 1 register.
1870                  */
1871 
1872                 /* Wait for ADC done */
1873                 ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
1874                 if (ret)
1875                         return ret;
1876 
1877                 /* Fetch ADC data */
1878                 if (n != 0) {
1879                         tmp = readl(dev->mmio + S626_P_FB_BUFFER1);
1880                         data[n - 1] = s626_ai_reg_to_uint(tmp);
1881                 }
1882 
1883                 /*
1884                  * Allow the ADC to stabilize for 4 microseconds before
1885                  * starting the next (final) conversion.  This delay is
1886                  * necessary to allow sufficient time between last
1887                  * conversion finished and the start of the next
1888                  * conversion.  Without this delay, the last conversion's
1889                  * data value is sometimes set to the previous
1890                  * conversion's data value.
1891                  */
1892                 udelay(4);
1893         }
1894 
1895         /*
1896          * Start a dummy conversion to cause the data from the
1897          * previous conversion to be shifted in.
1898          */
1899         gpio_image = readl(dev->mmio + S626_P_GPIO);
1900         /* Assert ADC Start command */
1901         writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1902         /* and stretch it out */
1903         writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1904         writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1905         /* Negate ADC Start command */
1906         writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1907 
1908         /* Wait for the data to arrive in FB BUFFER 1 register. */
1909 
1910         /* Wait for ADC done */
1911         ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
1912         if (ret)
1913                 return ret;
1914 
1915         /* Fetch ADC data from audio interface's input shift register. */
1916 
1917         /* Fetch ADC data */
1918         if (n != 0) {
1919                 tmp = readl(dev->mmio + S626_P_FB_BUFFER1);
1920                 data[n - 1] = s626_ai_reg_to_uint(tmp);
1921         }
1922 
1923         return n;
1924 }
1925 
1926 static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd)
1927 {
1928         int n;
1929 
1930         for (n = 0; n < cmd->chanlist_len; n++) {
1931                 if (CR_RANGE(cmd->chanlist[n]) == 0)
1932                         ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_5V;
1933                 else
1934                         ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_10V;
1935         }
1936         if (n != 0)
1937                 ppl[n - 1] |= S626_EOPL;
1938 
1939         return n;
1940 }
1941 
1942 static int s626_ai_inttrig(struct comedi_device *dev,
1943                            struct comedi_subdevice *s,
1944                            unsigned int trig_num)
1945 {
1946         struct comedi_cmd *cmd = &s->async->cmd;
1947 
1948         if (trig_num != cmd->start_arg)
1949                 return -EINVAL;
1950 
1951         /* Start executing the RPS program */
1952         s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1953 
1954         s->async->inttrig = NULL;
1955 
1956         return 1;
1957 }
1958 
1959 /*
1960  * This function doesn't require a particular form, this is just what
1961  * happens to be used in some of the drivers.  It should convert ns
1962  * nanoseconds to a counter value suitable for programming the device.
1963  * Also, it should adjust ns so that it cooresponds to the actual time
1964  * that the device will use.
1965  */
1966 static int s626_ns_to_timer(unsigned int *nanosec, unsigned int flags)
1967 {
1968         int divider, base;
1969 
1970         base = 500;             /* 2MHz internal clock */
1971 
1972         switch (flags & TRIG_ROUND_MASK) {
1973         case TRIG_ROUND_NEAREST:
1974         default:
1975                 divider = (*nanosec + base / 2) / base;
1976                 break;
1977         case TRIG_ROUND_DOWN:
1978                 divider = (*nanosec) / base;
1979                 break;
1980         case TRIG_ROUND_UP:
1981                 divider = (*nanosec + base - 1) / base;
1982                 break;
1983         }
1984 
1985         *nanosec = base * divider;
1986         return divider - 1;
1987 }
1988 
1989 static void s626_timer_load(struct comedi_device *dev,
1990                             unsigned int chan, int tick)
1991 {
1992         uint16_t setup =
1993                 /* Preload upon index. */
1994                 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
1995                 /* Disable hardware index. */
1996                 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
1997                 /* Operating mode is Timer. */
1998                 S626_SET_STD_ENCMODE(S626_ENCMODE_TIMER) |
1999                 /* Count direction is Down. */
2000                 S626_SET_STD_CLKPOL(S626_CNTDIR_DOWN) |
2001                 /* Clock multiplier is 1x. */
2002                 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2003                 /* Enabled by index */
2004                 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2005         uint16_t value_latchsrc = S626_LATCHSRC_A_INDXA;
2006         /* uint16_t enab = S626_CLKENAB_ALWAYS; */
2007 
2008         s626_set_mode(dev, chan, setup, false);
2009 
2010         /* Set the preload register */
2011         s626_preload(dev, chan, tick);
2012 
2013         /*
2014          * Software index pulse forces the preload register to load
2015          * into the counter
2016          */
2017         s626_set_load_trig(dev, chan, 0);
2018         s626_pulse_index(dev, chan);
2019 
2020         /* set reload on counter overflow */
2021         s626_set_load_trig(dev, chan, 1);
2022 
2023         /* set interrupt on overflow */
2024         s626_set_int_src(dev, chan, S626_INTSRC_OVER);
2025 
2026         s626_set_latch_source(dev, chan, value_latchsrc);
2027         /* s626_set_enable(dev, chan, (uint16_t)(enab != 0)); */
2028 }
2029 
2030 /* TO COMPLETE  */
2031 static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2032 {
2033         struct s626_private *devpriv = dev->private;
2034         uint8_t ppl[16];
2035         struct comedi_cmd *cmd = &s->async->cmd;
2036         int tick;
2037 
2038         if (devpriv->ai_cmd_running) {
2039                 dev_err(dev->class_dev,
2040                         "s626_ai_cmd: Another ai_cmd is running\n");
2041                 return -EBUSY;
2042         }
2043         /* disable interrupt */
2044         writel(0, dev->mmio + S626_P_IER);
2045 
2046         /* clear interrupt request */
2047         writel(S626_IRQ_RPS1 | S626_IRQ_GPIO3, dev->mmio + S626_P_ISR);
2048 
2049         /* clear any pending interrupt */
2050         s626_dio_clear_irq(dev);
2051         /* s626_enc_clear_irq(dev); */
2052 
2053         /* reset ai_cmd_running flag */
2054         devpriv->ai_cmd_running = 0;
2055 
2056         /* test if cmd is valid */
2057         if (cmd == NULL)
2058                 return -EINVAL;
2059 
2060         s626_ai_load_polllist(ppl, cmd);
2061         devpriv->ai_cmd_running = 1;
2062         devpriv->ai_convert_count = 0;
2063 
2064         switch (cmd->scan_begin_src) {
2065         case TRIG_FOLLOW:
2066                 break;
2067         case TRIG_TIMER:
2068                 /*
2069                  * set a counter to generate adc trigger at scan_begin_arg
2070                  * interval
2071                  */
2072                 tick = s626_ns_to_timer(&cmd->scan_begin_arg, cmd->flags);
2073 
2074                 /* load timer value and enable interrupt */
2075                 s626_timer_load(dev, 5, tick);
2076                 s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS);
2077                 break;
2078         case TRIG_EXT:
2079                 /* set the digital line and interrupt for scan trigger */
2080                 if (cmd->start_src != TRIG_EXT)
2081                         s626_dio_set_irq(dev, cmd->scan_begin_arg);
2082                 break;
2083         }
2084 
2085         switch (cmd->convert_src) {
2086         case TRIG_NOW:
2087                 break;
2088         case TRIG_TIMER:
2089                 /*
2090                  * set a counter to generate adc trigger at convert_arg
2091                  * interval
2092                  */
2093                 tick = s626_ns_to_timer(&cmd->convert_arg, cmd->flags);
2094 
2095                 /* load timer value and enable interrupt */
2096                 s626_timer_load(dev, 4, tick);
2097                 s626_set_enable(dev, 4, S626_CLKENAB_INDEX);
2098                 break;
2099         case TRIG_EXT:
2100                 /* set the digital line and interrupt for convert trigger */
2101                 if (cmd->scan_begin_src != TRIG_EXT &&
2102                     cmd->start_src == TRIG_EXT)
2103                         s626_dio_set_irq(dev, cmd->convert_arg);
2104                 break;
2105         }
2106 
2107         switch (cmd->stop_src) {
2108         case TRIG_COUNT:
2109                 /* data arrives as one packet */
2110                 devpriv->ai_sample_count = cmd->stop_arg;
2111                 devpriv->ai_continuous = 0;
2112                 break;
2113         case TRIG_NONE:
2114                 /* continuous acquisition */
2115                 devpriv->ai_continuous = 1;
2116                 devpriv->ai_sample_count = 1;
2117                 break;
2118         }
2119 
2120         s626_reset_adc(dev, ppl);
2121 
2122         switch (cmd->start_src) {
2123         case TRIG_NOW:
2124                 /* Trigger ADC scan loop start */
2125                 /* s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); */
2126 
2127                 /* Start executing the RPS program */
2128                 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
2129                 s->async->inttrig = NULL;
2130                 break;
2131         case TRIG_EXT:
2132                 /* configure DIO channel for acquisition trigger */
2133                 s626_dio_set_irq(dev, cmd->start_arg);
2134                 s->async->inttrig = NULL;
2135                 break;
2136         case TRIG_INT:
2137                 s->async->inttrig = s626_ai_inttrig;
2138                 break;
2139         }
2140 
2141         /* enable interrupt */
2142         writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, dev->mmio + S626_P_IER);
2143 
2144         return 0;
2145 }
2146 
2147 static int s626_ai_cmdtest(struct comedi_device *dev,
2148                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
2149 {
2150         int err = 0;
2151         unsigned int arg;
2152 
2153         /* Step 1 : check if triggers are trivially valid */
2154 
2155         err |= cfc_check_trigger_src(&cmd->start_src,
2156                                      TRIG_NOW | TRIG_INT | TRIG_EXT);
2157         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2158                                      TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW);
2159         err |= cfc_check_trigger_src(&cmd->convert_src,
2160                                      TRIG_TIMER | TRIG_EXT | TRIG_NOW);
2161         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2162         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2163 
2164         if (err)
2165                 return 1;
2166 
2167         /* Step 2a : make sure trigger sources are unique */
2168 
2169         err |= cfc_check_trigger_is_unique(cmd->start_src);
2170         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2171         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2172         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2173 
2174         /* Step 2b : and mutually compatible */
2175 
2176         if (err)
2177                 return 2;
2178 
2179         /* Step 3: check if arguments are trivially valid */
2180 
2181         switch (cmd->start_src) {
2182         case TRIG_NOW:
2183         case TRIG_INT:
2184                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2185                 break;
2186         case TRIG_EXT:
2187                 err |= cfc_check_trigger_arg_max(&cmd->start_arg, 39);
2188                 break;
2189         }
2190 
2191         if (cmd->scan_begin_src == TRIG_EXT)
2192                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 39);
2193         if (cmd->convert_src == TRIG_EXT)
2194                 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 39);
2195 
2196 #define S626_MAX_SPEED  200000  /* in nanoseconds */
2197 #define S626_MIN_SPEED  2000000000      /* in nanoseconds */
2198 
2199         if (cmd->scan_begin_src == TRIG_TIMER) {
2200                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2201                                                  S626_MAX_SPEED);
2202                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2203                                                  S626_MIN_SPEED);
2204         } else {
2205                 /* external trigger */
2206                 /* should be level/edge, hi/lo specification here */
2207                 /* should specify multiple external triggers */
2208                 /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
2209         }
2210         if (cmd->convert_src == TRIG_TIMER) {
2211                 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2212                                                  S626_MAX_SPEED);
2213                 err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2214                                                  S626_MIN_SPEED);
2215         } else {
2216                 /* external trigger */
2217                 /* see above */
2218                 /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
2219         }
2220 
2221         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2222 
2223         if (cmd->stop_src == TRIG_COUNT)
2224                 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
2225         else    /* TRIG_NONE */
2226                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2227 
2228         if (err)
2229                 return 3;
2230 
2231         /* step 4: fix up any arguments */
2232 
2233         if (cmd->scan_begin_src == TRIG_TIMER) {
2234                 arg = cmd->scan_begin_arg;
2235                 s626_ns_to_timer(&arg, cmd->flags);
2236                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
2237         }
2238 
2239         if (cmd->convert_src == TRIG_TIMER) {
2240                 arg = cmd->convert_arg;
2241                 s626_ns_to_timer(&arg, cmd->flags);
2242                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, arg);
2243 
2244                 if (cmd->scan_begin_src == TRIG_TIMER) {
2245                         arg = cmd->convert_arg * cmd->scan_end_arg;
2246                         err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2247                                                          arg);
2248                 }
2249         }
2250 
2251         if (err)
2252                 return 4;
2253 
2254         return 0;
2255 }
2256 
2257 static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
2258 {
2259         struct s626_private *devpriv = dev->private;
2260 
2261         /* Stop RPS program in case it is currently running */
2262         s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
2263 
2264         /* disable master interrupt */
2265         writel(0, dev->mmio + S626_P_IER);
2266 
2267         devpriv->ai_cmd_running = 0;
2268 
2269         return 0;
2270 }
2271 
2272 static int s626_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
2273                          struct comedi_insn *insn, unsigned int *data)
2274 {
2275         struct s626_private *devpriv = dev->private;
2276         int i;
2277         int ret;
2278         uint16_t chan = CR_CHAN(insn->chanspec);
2279         int16_t dacdata;
2280 
2281         for (i = 0; i < insn->n; i++) {
2282                 dacdata = (int16_t) data[i];
2283                 devpriv->ao_readback[CR_CHAN(insn->chanspec)] = data[i];
2284                 dacdata -= (0x1fff);
2285 
2286                 ret = s626_set_dac(dev, chan, dacdata);
2287                 if (ret)
2288                         return ret;
2289         }
2290 
2291         return i;
2292 }
2293 
2294 static int s626_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
2295                          struct comedi_insn *insn, unsigned int *data)
2296 {
2297         struct s626_private *devpriv = dev->private;
2298         int i;
2299 
2300         for (i = 0; i < insn->n; i++)
2301                 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
2302 
2303         return i;
2304 }
2305 
2306 /* *************** DIGITAL I/O FUNCTIONS *************** */
2307 
2308 /*
2309  * All DIO functions address a group of DIO channels by means of
2310  * "group" argument.  group may be 0, 1 or 2, which correspond to DIO
2311  * ports A, B and C, respectively.
2312  */
2313 
2314 static void s626_dio_init(struct comedi_device *dev)
2315 {
2316         uint16_t group;
2317 
2318         /* Prepare to treat writes to WRCapSel as capture disables. */
2319         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
2320 
2321         /* For each group of sixteen channels ... */
2322         for (group = 0; group < S626_DIO_BANKS; group++) {
2323                 /* Disable all interrupts */
2324                 s626_debi_write(dev, S626_LP_WRINTSEL(group), 0);
2325                 /* Disable all event captures */
2326                 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
2327                 /* Init all DIOs to default edge polarity */
2328                 s626_debi_write(dev, S626_LP_WREDGSEL(group), 0);
2329                 /* Program all outputs to inactive state */
2330                 s626_debi_write(dev, S626_LP_WRDOUT(group), 0);
2331         }
2332 }
2333 
2334 static int s626_dio_insn_bits(struct comedi_device *dev,
2335                               struct comedi_subdevice *s,
2336                               struct comedi_insn *insn,
2337                               unsigned int *data)
2338 {
2339         unsigned long group = (unsigned long)s->private;
2340 
2341         if (comedi_dio_update_state(s, data))
2342                 s626_debi_write(dev, S626_LP_WRDOUT(group), s->state);
2343 
2344         data[1] = s626_debi_read(dev, S626_LP_RDDIN(group));
2345 
2346         return insn->n;
2347 }
2348 
2349 static int s626_dio_insn_config(struct comedi_device *dev,
2350                                 struct comedi_subdevice *s,
2351                                 struct comedi_insn *insn,
2352                                 unsigned int *data)
2353 {
2354         unsigned long group = (unsigned long)s->private;
2355         int ret;
2356 
2357         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
2358         if (ret)
2359                 return ret;
2360 
2361         s626_debi_write(dev, S626_LP_WRDOUT(group), s->io_bits);
2362 
2363         return insn->n;
2364 }
2365 
2366 /*
2367  * Now this function initializes the value of the counter (data[0])
2368  * and set the subdevice. To complete with trigger and interrupt
2369  * configuration.
2370  *
2371  * FIXME: data[0] is supposed to be an INSN_CONFIG_xxx constant indicating
2372  * what is being configured, but this function appears to be using data[0]
2373  * as a variable.
2374  */
2375 static int s626_enc_insn_config(struct comedi_device *dev,
2376                                 struct comedi_subdevice *s,
2377                                 struct comedi_insn *insn, unsigned int *data)
2378 {
2379         unsigned int chan = CR_CHAN(insn->chanspec);
2380         uint16_t setup =
2381                 /* Preload upon index. */
2382                 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2383                 /* Disable hardware index. */
2384                 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2385                 /* Operating mode is Counter. */
2386                 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2387                 /* Active high clock. */
2388                 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2389                 /* Clock multiplier is 1x. */
2390                 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2391                 /* Enabled by index */
2392                 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2393         /* uint16_t disable_int_src = true; */
2394         /* uint32_t Preloadvalue;              //Counter initial value */
2395         uint16_t value_latchsrc = S626_LATCHSRC_AB_READ;
2396         uint16_t enab = S626_CLKENAB_ALWAYS;
2397 
2398         /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
2399 
2400         s626_set_mode(dev, chan, setup, true);
2401         s626_preload(dev, chan, data[0]);
2402         s626_pulse_index(dev, chan);
2403         s626_set_latch_source(dev, chan, value_latchsrc);
2404         s626_set_enable(dev, chan, (enab != 0));
2405 
2406         return insn->n;
2407 }
2408 
2409 static int s626_enc_insn_read(struct comedi_device *dev,
2410                               struct comedi_subdevice *s,
2411                               struct comedi_insn *insn,
2412                               unsigned int *data)
2413 {
2414         unsigned int chan = CR_CHAN(insn->chanspec);
2415         uint16_t cntr_latch_reg = S626_LP_CNTR(chan);
2416         int i;
2417 
2418         for (i = 0; i < insn->n; i++) {
2419                 unsigned int val;
2420 
2421                 /*
2422                  * Read the counter's output latch LSW/MSW.
2423                  * Latches on LSW read.
2424                  */
2425                 val = s626_debi_read(dev, cntr_latch_reg);
2426                 val |= (s626_debi_read(dev, cntr_latch_reg + 2) << 16);
2427                 data[i] = val;
2428         }
2429 
2430         return insn->n;
2431 }
2432 
2433 static int s626_enc_insn_write(struct comedi_device *dev,
2434                                struct comedi_subdevice *s,
2435                                struct comedi_insn *insn, unsigned int *data)
2436 {
2437         unsigned int chan = CR_CHAN(insn->chanspec);
2438 
2439         /* Set the preload register */
2440         s626_preload(dev, chan, data[0]);
2441 
2442         /*
2443          * Software index pulse forces the preload register to load
2444          * into the counter
2445          */
2446         s626_set_load_trig(dev, chan, 0);
2447         s626_pulse_index(dev, chan);
2448         s626_set_load_trig(dev, chan, 2);
2449 
2450         return 1;
2451 }
2452 
2453 static void s626_write_misc2(struct comedi_device *dev, uint16_t new_image)
2454 {
2455         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WENABLE);
2456         s626_debi_write(dev, S626_LP_WRMISC2, new_image);
2457         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WDISABLE);
2458 }
2459 
2460 static void s626_close_dma_b(struct comedi_device *dev,
2461                              struct s626_buffer_dma *pdma, size_t bsize)
2462 {
2463         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2464         void *vbptr;
2465         dma_addr_t vpptr;
2466 
2467         if (pdma == NULL)
2468                 return;
2469 
2470         /* find the matching allocation from the board struct */
2471         vbptr = pdma->logical_base;
2472         vpptr = pdma->physical_base;
2473         if (vbptr) {
2474                 pci_free_consistent(pcidev, bsize, vbptr, vpptr);
2475                 pdma->logical_base = NULL;
2476                 pdma->physical_base = 0;
2477         }
2478 }
2479 
2480 static void s626_counters_init(struct comedi_device *dev)
2481 {
2482         int chan;
2483         uint16_t setup =
2484                 /* Preload upon index. */
2485                 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2486                 /* Disable hardware index. */
2487                 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2488                 /* Operating mode is counter. */
2489                 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2490                 /* Active high clock. */
2491                 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2492                 /* Clock multiplier is 1x. */
2493                 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2494                 /* Enabled by index */
2495                 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2496 
2497         /*
2498          * Disable all counter interrupts and clear any captured counter events.
2499          */
2500         for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
2501                 s626_set_mode(dev, chan, setup, true);
2502                 s626_set_int_src(dev, chan, 0);
2503                 s626_reset_cap_flags(dev, chan);
2504                 s626_set_enable(dev, chan, S626_CLKENAB_ALWAYS);
2505         }
2506 }
2507 
2508 static int s626_allocate_dma_buffers(struct comedi_device *dev)
2509 {
2510         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2511         struct s626_private *devpriv = dev->private;
2512         void *addr;
2513         dma_addr_t appdma;
2514 
2515         addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2516         if (!addr)
2517                 return -ENOMEM;
2518         devpriv->ana_buf.logical_base = addr;
2519         devpriv->ana_buf.physical_base = appdma;
2520 
2521         addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2522         if (!addr)
2523                 return -ENOMEM;
2524         devpriv->rps_buf.logical_base = addr;
2525         devpriv->rps_buf.physical_base = appdma;
2526 
2527         return 0;
2528 }
2529 
2530 static int s626_initialize(struct comedi_device *dev)
2531 {
2532         struct s626_private *devpriv = dev->private;
2533         dma_addr_t phys_buf;
2534         uint16_t chan;
2535         int i;
2536         int ret;
2537 
2538         /* Enable DEBI and audio pins, enable I2C interface */
2539         s626_mc_enable(dev, S626_MC1_DEBI | S626_MC1_AUDIO | S626_MC1_I2C,
2540                        S626_P_MC1);
2541 
2542         /*
2543          * Configure DEBI operating mode
2544          *
2545          *  Local bus is 16 bits wide
2546          *  Declare DEBI transfer timeout interval
2547          *  Set up byte lane steering
2548          *  Intel-compatible local bus (DEBI never times out)
2549          */
2550         writel(S626_DEBI_CFG_SLAVE16 |
2551                (S626_DEBI_TOUT << S626_DEBI_CFG_TOUT_BIT) | S626_DEBI_SWAP |
2552                S626_DEBI_CFG_INTEL, dev->mmio + S626_P_DEBICFG);
2553 
2554         /* Disable MMU paging */
2555         writel(S626_DEBI_PAGE_DISABLE, dev->mmio + S626_P_DEBIPAGE);
2556 
2557         /* Init GPIO so that ADC Start* is negated */
2558         writel(S626_GPIO_BASE | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
2559 
2560         /* I2C device address for onboard eeprom (revb) */
2561         devpriv->i2c_adrs = 0xA0;
2562 
2563         /*
2564          * Issue an I2C ABORT command to halt any I2C
2565          * operation in progress and reset BUSY flag.
2566          */
2567         writel(S626_I2C_CLKSEL | S626_I2C_ABORT,
2568                dev->mmio + S626_P_I2CSTAT);
2569         s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2570         ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
2571         if (ret)
2572                 return ret;
2573 
2574         /*
2575          * Per SAA7146 data sheet, write to STATUS
2576          * reg twice to reset all  I2C error flags.
2577          */
2578         for (i = 0; i < 2; i++) {
2579                 writel(S626_I2C_CLKSEL, dev->mmio + S626_P_I2CSTAT);
2580                 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2581                 ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
2582                 if (ret)
2583                         return ret;
2584         }
2585 
2586         /*
2587          * Init audio interface functional attributes: set DAC/ADC
2588          * serial clock rates, invert DAC serial clock so that
2589          * DAC data setup times are satisfied, enable DAC serial
2590          * clock out.
2591          */
2592         writel(S626_ACON2_INIT, dev->mmio + S626_P_ACON2);
2593 
2594         /*
2595          * Set up TSL1 slot list, which is used to control the
2596          * accumulation of ADC data: S626_RSD1 = shift data in on SD1.
2597          * S626_SIB_A1  = store data uint8_t at next available location
2598          * in FB BUFFER1 register.
2599          */
2600         writel(S626_RSD1 | S626_SIB_A1, dev->mmio + S626_P_TSL1);
2601         writel(S626_RSD1 | S626_SIB_A1 | S626_EOS,
2602                dev->mmio + S626_P_TSL1 + 4);
2603 
2604         /* Enable TSL1 slot list so that it executes all the time */
2605         writel(S626_ACON1_ADCSTART, dev->mmio + S626_P_ACON1);
2606 
2607         /*
2608          * Initialize RPS registers used for ADC
2609          */
2610 
2611         /* Physical start of RPS program */
2612         writel((uint32_t)devpriv->rps_buf.physical_base,
2613                dev->mmio + S626_P_RPSADDR1);
2614         /* RPS program performs no explicit mem writes */
2615         writel(0, dev->mmio + S626_P_RPSPAGE1);
2616         /* Disable RPS timeouts */
2617         writel(0, dev->mmio + S626_P_RPS1_TOUT);
2618 
2619 #if 0
2620         /*
2621          * SAA7146 BUG WORKAROUND
2622          *
2623          * Initialize SAA7146 ADC interface to a known state by
2624          * invoking ADCs until FB BUFFER 1 register shows that it
2625          * is correctly receiving ADC data. This is necessary
2626          * because the SAA7146 ADC interface does not start up in
2627          * a defined state after a PCI reset.
2628          */
2629         {
2630                 struct comedi_subdevice *s = dev->read_subdev;
2631                 uint8_t poll_list;
2632                 uint16_t adc_data;
2633                 uint16_t start_val;
2634                 uint16_t index;
2635                 unsigned int data[16];
2636 
2637                 /* Create a simple polling list for analog input channel 0 */
2638                 poll_list = S626_EOPL;
2639                 s626_reset_adc(dev, &poll_list);
2640 
2641                 /* Get initial ADC value */
2642                 s626_ai_rinsn(dev, s, NULL, data);
2643                 start_val = data[0];
2644 
2645                 /*
2646                  * VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED
2647                  * EXECUTION.
2648                  *
2649                  * Invoke ADCs until the new ADC value differs from the initial
2650                  * value or a timeout occurs.  The timeout protects against the
2651                  * possibility that the driver is restarting and the ADC data is
2652                  * a fixed value resulting from the applied ADC analog input
2653                  * being unusually quiet or at the rail.
2654                  */
2655                 for (index = 0; index < 500; index++) {
2656                         s626_ai_rinsn(dev, s, NULL, data);
2657                         adc_data = data[0];
2658                         if (adc_data != start_val)
2659                                 break;
2660                 }
2661         }
2662 #endif  /* SAA7146 BUG WORKAROUND */
2663 
2664         /*
2665          * Initialize the DAC interface
2666          */
2667 
2668         /*
2669          * Init Audio2's output DMAC attributes:
2670          *   burst length = 1 DWORD
2671          *   threshold = 1 DWORD.
2672          */
2673         writel(0, dev->mmio + S626_P_PCI_BT_A);
2674 
2675         /*
2676          * Init Audio2's output DMA physical addresses.  The protection
2677          * address is set to 1 DWORD past the base address so that a
2678          * single DWORD will be transferred each time a DMA transfer is
2679          * enabled.
2680          */
2681         phys_buf = devpriv->ana_buf.physical_base +
2682                    (S626_DAC_WDMABUF_OS * sizeof(uint32_t));
2683         writel((uint32_t)phys_buf, dev->mmio + S626_P_BASEA2_OUT);
2684         writel((uint32_t)(phys_buf + sizeof(uint32_t)),
2685                dev->mmio + S626_P_PROTA2_OUT);
2686 
2687         /*
2688          * Cache Audio2's output DMA buffer logical address.  This is
2689          * where DAC data is buffered for A2 output DMA transfers.
2690          */
2691         devpriv->dac_wbuf = (uint32_t *)devpriv->ana_buf.logical_base +
2692                             S626_DAC_WDMABUF_OS;
2693 
2694         /*
2695          * Audio2's output channels does not use paging.  The
2696          * protection violation handling bit is set so that the
2697          * DMAC will automatically halt and its PCI address pointer
2698          * will be reset when the protection address is reached.
2699          */
2700         writel(8, dev->mmio + S626_P_PAGEA2_OUT);
2701 
2702         /*
2703          * Initialize time slot list 2 (TSL2), which is used to control
2704          * the clock generation for and serialization of data to be sent
2705          * to the DAC devices.  Slot 0 is a NOP that is used to trap TSL
2706          * execution; this permits other slots to be safely modified
2707          * without first turning off the TSL sequencer (which is
2708          * apparently impossible to do).  Also, SD3 (which is driven by a
2709          * pull-up resistor) is shifted in and stored to the MSB of
2710          * FB_BUFFER2 to be used as evidence that the slot sequence has
2711          * not yet finished executing.
2712          */
2713 
2714         /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */
2715         writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2 | S626_EOS,
2716                dev->mmio + S626_VECTPORT(0));
2717 
2718         /*
2719          * Initialize slot 1, which is constant.  Slot 1 causes a
2720          * DWORD to be transferred from audio channel 2's output FIFO
2721          * to the FIFO's output buffer so that it can be serialized
2722          * and sent to the DAC during subsequent slots.  All remaining
2723          * slots are dynamically populated as required by the target
2724          * DAC device.
2725          */
2726 
2727         /* Slot 1: Fetch DWORD from Audio2's output FIFO */
2728         writel(S626_LF_A2, dev->mmio + S626_VECTPORT(1));
2729 
2730         /* Start DAC's audio interface (TSL2) running */
2731         writel(S626_ACON1_DACSTART, dev->mmio + S626_P_ACON1);
2732 
2733         /*
2734          * Init Trim DACs to calibrated values.  Do it twice because the
2735          * SAA7146 audio channel does not always reset properly and
2736          * sometimes causes the first few TrimDAC writes to malfunction.
2737          */
2738         s626_load_trim_dacs(dev);
2739         ret = s626_load_trim_dacs(dev);
2740         if (ret)
2741                 return ret;
2742 
2743         /*
2744          * Manually init all gate array hardware in case this is a soft
2745          * reset (we have no way of determining whether this is a warm
2746          * or cold start).  This is necessary because the gate array will
2747          * reset only in response to a PCI hard reset; there is no soft
2748          * reset function.
2749          */
2750 
2751         /*
2752          * Init all DAC outputs to 0V and init all DAC setpoint and
2753          * polarity images.
2754          */
2755         for (chan = 0; chan < S626_DAC_CHANNELS; chan++) {
2756                 ret = s626_set_dac(dev, chan, 0);
2757                 if (ret)
2758                         return ret;
2759         }
2760 
2761         /* Init counters */
2762         s626_counters_init(dev);
2763 
2764         /*
2765          * Without modifying the state of the Battery Backup enab, disable
2766          * the watchdog timer, set DIO channels 0-5 to operate in the
2767          * standard DIO (vs. counter overflow) mode, disable the battery
2768          * charger, and reset the watchdog interval selector to zero.
2769          */
2770         s626_write_misc2(dev, (s626_debi_read(dev, S626_LP_RDMISC2) &
2771                                S626_MISC2_BATT_ENABLE));
2772 
2773         /* Initialize the digital I/O subsystem */
2774         s626_dio_init(dev);
2775 
2776         return 0;
2777 }
2778 
2779 static int s626_auto_attach(struct comedi_device *dev,
2780                                       unsigned long context_unused)
2781 {
2782         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2783         struct s626_private *devpriv;
2784         struct comedi_subdevice *s;
2785         int ret;
2786 
2787         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
2788         if (!devpriv)
2789                 return -ENOMEM;
2790 
2791         ret = comedi_pci_enable(dev);
2792         if (ret)
2793                 return ret;
2794 
2795         dev->mmio = pci_ioremap_bar(pcidev, 0);
2796         if (!dev->mmio)
2797                 return -ENOMEM;
2798 
2799         /* disable master interrupt */
2800         writel(0, dev->mmio + S626_P_IER);
2801 
2802         /* soft reset */
2803         writel(S626_MC1_SOFT_RESET, dev->mmio + S626_P_MC1);
2804 
2805         /* DMA FIXME DMA// */
2806 
2807         ret = s626_allocate_dma_buffers(dev);
2808         if (ret)
2809                 return ret;
2810 
2811         if (pcidev->irq) {
2812                 ret = request_irq(pcidev->irq, s626_irq_handler, IRQF_SHARED,
2813                                   dev->board_name, dev);
2814 
2815                 if (ret == 0)
2816                         dev->irq = pcidev->irq;
2817         }
2818 
2819         ret = comedi_alloc_subdevices(dev, 6);
2820         if (ret)
2821                 return ret;
2822 
2823         s = &dev->subdevices[0];
2824         /* analog input subdevice */
2825         s->type         = COMEDI_SUBD_AI;
2826         s->subdev_flags = SDF_READABLE | SDF_DIFF;
2827         s->n_chan       = S626_ADC_CHANNELS;
2828         s->maxdata      = 0x3fff;
2829         s->range_table  = &s626_range_table;
2830         s->len_chanlist = S626_ADC_CHANNELS;
2831         s->insn_read    = s626_ai_insn_read;
2832         if (dev->irq) {
2833                 dev->read_subdev = s;
2834                 s->subdev_flags |= SDF_CMD_READ;
2835                 s->do_cmd       = s626_ai_cmd;
2836                 s->do_cmdtest   = s626_ai_cmdtest;
2837                 s->cancel       = s626_ai_cancel;
2838         }
2839 
2840         s = &dev->subdevices[1];
2841         /* analog output subdevice */
2842         s->type         = COMEDI_SUBD_AO;
2843         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2844         s->n_chan       = S626_DAC_CHANNELS;
2845         s->maxdata      = 0x3fff;
2846         s->range_table  = &range_bipolar10;
2847         s->insn_write   = s626_ao_winsn;
2848         s->insn_read    = s626_ao_rinsn;
2849 
2850         s = &dev->subdevices[2];
2851         /* digital I/O subdevice */
2852         s->type         = COMEDI_SUBD_DIO;
2853         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2854         s->n_chan       = 16;
2855         s->maxdata      = 1;
2856         s->io_bits      = 0xffff;
2857         s->private      = (void *)0;    /* DIO group 0 */
2858         s->range_table  = &range_digital;
2859         s->insn_config  = s626_dio_insn_config;
2860         s->insn_bits    = s626_dio_insn_bits;
2861 
2862         s = &dev->subdevices[3];
2863         /* digital I/O subdevice */
2864         s->type         = COMEDI_SUBD_DIO;
2865         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2866         s->n_chan       = 16;
2867         s->maxdata      = 1;
2868         s->io_bits      = 0xffff;
2869         s->private      = (void *)1;    /* DIO group 1 */
2870         s->range_table  = &range_digital;
2871         s->insn_config  = s626_dio_insn_config;
2872         s->insn_bits    = s626_dio_insn_bits;
2873 
2874         s = &dev->subdevices[4];
2875         /* digital I/O subdevice */
2876         s->type         = COMEDI_SUBD_DIO;
2877         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2878         s->n_chan       = 16;
2879         s->maxdata      = 1;
2880         s->io_bits      = 0xffff;
2881         s->private      = (void *)2;    /* DIO group 2 */
2882         s->range_table  = &range_digital;
2883         s->insn_config  = s626_dio_insn_config;
2884         s->insn_bits    = s626_dio_insn_bits;
2885 
2886         s = &dev->subdevices[5];
2887         /* encoder (counter) subdevice */
2888         s->type         = COMEDI_SUBD_COUNTER;
2889         s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
2890         s->n_chan       = S626_ENCODER_CHANNELS;
2891         s->maxdata      = 0xffffff;
2892         s->range_table  = &range_unknown;
2893         s->insn_config  = s626_enc_insn_config;
2894         s->insn_read    = s626_enc_insn_read;
2895         s->insn_write   = s626_enc_insn_write;
2896 
2897         ret = s626_initialize(dev);
2898         if (ret)
2899                 return ret;
2900 
2901         return 0;
2902 }
2903 
2904 static void s626_detach(struct comedi_device *dev)
2905 {
2906         struct s626_private *devpriv = dev->private;
2907 
2908         if (devpriv) {
2909                 /* stop ai_command */
2910                 devpriv->ai_cmd_running = 0;
2911 
2912                 if (dev->mmio) {
2913                         /* interrupt mask */
2914                         /* Disable master interrupt */
2915                         writel(0, dev->mmio + S626_P_IER);
2916                         /* Clear board's IRQ status flag */
2917                         writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1,
2918                                dev->mmio + S626_P_ISR);
2919 
2920                         /* Disable the watchdog timer and battery charger. */
2921                         s626_write_misc2(dev, 0);
2922 
2923                         /* Close all interfaces on 7146 device */
2924                         writel(S626_MC1_SHUTDOWN, dev->mmio + S626_P_MC1);
2925                         writel(S626_ACON1_BASE, dev->mmio + S626_P_ACON1);
2926 
2927                         s626_close_dma_b(dev, &devpriv->rps_buf,
2928                                          S626_DMABUF_SIZE);
2929                         s626_close_dma_b(dev, &devpriv->ana_buf,
2930                                          S626_DMABUF_SIZE);
2931                 }
2932 
2933                 if (dev->irq)
2934                         free_irq(dev->irq, dev);
2935                 if (dev->mmio)
2936                         iounmap(dev->mmio);
2937         }
2938         comedi_pci_disable(dev);
2939 }
2940 
2941 static struct comedi_driver s626_driver = {
2942         .driver_name    = "s626",
2943         .module         = THIS_MODULE,
2944         .auto_attach    = s626_auto_attach,
2945         .detach         = s626_detach,
2946 };
2947 
2948 static int s626_pci_probe(struct pci_dev *dev,
2949                           const struct pci_device_id *id)
2950 {
2951         return comedi_pci_auto_config(dev, &s626_driver, id->driver_data);
2952 }
2953 
2954 /*
2955  * For devices with vendor:device id == 0x1131:0x7146 you must specify
2956  * also subvendor:subdevice ids, because otherwise it will conflict with
2957  * Philips SAA7146 media/dvb based cards.
2958  */
2959 static const struct pci_device_id s626_pci_table[] = {
2960         { PCI_DEVICE_SUB(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA7146,
2961                          0x6000, 0x0272) },
2962         { 0 }
2963 };
2964 MODULE_DEVICE_TABLE(pci, s626_pci_table);
2965 
2966 static struct pci_driver s626_pci_driver = {
2967         .name           = "s626",
2968         .id_table       = s626_pci_table,
2969         .probe          = s626_pci_probe,
2970         .remove         = comedi_pci_auto_unconfig,
2971 };
2972 module_comedi_pci_driver(s626_driver, s626_pci_driver);
2973 
2974 MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
2975 MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
2976 MODULE_LICENSE("GPL");
2977 

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