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Linux/drivers/staging/comedi/drivers/s626.c

  1 /*
  2  * comedi/drivers/s626.c
  3  * Sensoray s626 Comedi driver
  4  *
  5  * COMEDI - Linux Control and Measurement Device Interface
  6  * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
  7  *
  8  * Based on Sensoray Model 626 Linux driver Version 0.2
  9  * Copyright (C) 2002-2004 Sensoray Co., Inc.
 10  *
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License as published by
 13  * the Free Software Foundation; either version 2 of the License, or
 14  * (at your option) any later version.
 15  *
 16  * This program is distributed in the hope that it will be useful,
 17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19  * GNU General Public License for more details.
 20  */
 21 
 22 /*
 23  * Driver: s626
 24  * Description: Sensoray 626 driver
 25  * Devices: [Sensoray] 626 (s626)
 26  * Authors: Gianluca Palli <gpalli@deis.unibo.it>,
 27  * Updated: Fri, 15 Feb 2008 10:28:42 +0000
 28  * Status: experimental
 29 
 30  * Configuration options: not applicable, uses PCI auto config
 31 
 32  * INSN_CONFIG instructions:
 33  *   analog input:
 34  *    none
 35  *
 36  *   analog output:
 37  *    none
 38  *
 39  *   digital channel:
 40  *    s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
 41  *    supported configuration options:
 42  *    INSN_CONFIG_DIO_QUERY
 43  *    COMEDI_INPUT
 44  *    COMEDI_OUTPUT
 45  *
 46  *   encoder:
 47  *    Every channel must be configured before reading.
 48  *
 49  *   Example code
 50  *
 51  *    insn.insn=INSN_CONFIG;   //configuration instruction
 52  *    insn.n=1;                //number of operation (must be 1)
 53  *    insn.data=&initialvalue; //initial value loaded into encoder
 54  *                             //during configuration
 55  *    insn.subdev=5;           //encoder subdevice
 56  *    insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
 57  *                                                         //to configure
 58  *
 59  *    comedi_do_insn(cf,&insn); //executing configuration
 60  */
 61 
 62 #include <linux/module.h>
 63 #include <linux/delay.h>
 64 #include <linux/pci.h>
 65 #include <linux/interrupt.h>
 66 #include <linux/kernel.h>
 67 #include <linux/types.h>
 68 
 69 #include "../comedidev.h"
 70 
 71 #include "comedi_fc.h"
 72 #include "s626.h"
 73 
 74 struct s626_buffer_dma {
 75         dma_addr_t physical_base;
 76         void *logical_base;
 77 };
 78 
 79 struct s626_private {
 80         void __iomem *mmio;
 81         uint8_t ai_cmd_running;         /* ai_cmd is running */
 82         uint8_t ai_continuous;          /* continuous acquisition */
 83         int ai_sample_count;            /* number of samples to acquire */
 84         unsigned int ai_sample_timer;   /* time between samples in
 85                                          * units of the timer */
 86         int ai_convert_count;           /* conversion counter */
 87         unsigned int ai_convert_timer;  /* time between conversion in
 88                                          * units of the timer */
 89         uint16_t counter_int_enabs;     /* counter interrupt enable mask
 90                                          * for MISC2 register */
 91         uint8_t adc_items;              /* number of items in ADC poll list */
 92         struct s626_buffer_dma rps_buf; /* DMA buffer used to hold ADC (RPS1)
 93                                          * program */
 94         struct s626_buffer_dma ana_buf; /* DMA buffer used to receive ADC data
 95                                          * and hold DAC data */
 96         uint32_t *dac_wbuf;             /* pointer to logical adrs of DMA buffer
 97                                          * used to hold DAC data */
 98         uint16_t dacpol;                /* image of DAC polarity register */
 99         uint8_t trim_setpoint[12];      /* images of TrimDAC setpoints */
100         uint32_t i2c_adrs;              /* I2C device address for onboard EEPROM
101                                          * (board rev dependent) */
102         unsigned int ao_readback[S626_DAC_CHANNELS];
103 };
104 
105 /* COUNTER OBJECT ------------------------------------------------ */
106 struct s626_enc_info {
107         /* Pointers to functions that differ for A and B counters: */
108         /* Return clock enable. */
109         uint16_t (*get_enable)(struct comedi_device *dev,
110                               const struct s626_enc_info *k);
111         /* Return interrupt source. */
112         uint16_t (*get_int_src)(struct comedi_device *dev,
113                                const struct s626_enc_info *k);
114         /* Return preload trigger source. */
115         uint16_t (*get_load_trig)(struct comedi_device *dev,
116                                  const struct s626_enc_info *k);
117         /* Return standardized operating mode. */
118         uint16_t (*get_mode)(struct comedi_device *dev,
119                             const struct s626_enc_info *k);
120         /* Generate soft index strobe. */
121         void (*pulse_index)(struct comedi_device *dev,
122                             const struct s626_enc_info *k);
123         /* Program clock enable. */
124         void (*set_enable)(struct comedi_device *dev,
125                            const struct s626_enc_info *k, uint16_t enab);
126         /* Program interrupt source. */
127         void (*set_int_src)(struct comedi_device *dev,
128                             const struct s626_enc_info *k, uint16_t int_source);
129         /* Program preload trigger source. */
130         void (*set_load_trig)(struct comedi_device *dev,
131                               const struct s626_enc_info *k, uint16_t trig);
132         /* Program standardized operating mode. */
133         void (*set_mode)(struct comedi_device *dev,
134                          const struct s626_enc_info *k, uint16_t setup,
135                          uint16_t disable_int_src);
136         /* Reset event capture flags. */
137         void (*reset_cap_flags)(struct comedi_device *dev,
138                                 const struct s626_enc_info *k);
139 
140         uint16_t my_cra;        /* address of CRA register */
141         uint16_t my_crb;        /* address of CRB register */
142         uint16_t my_latch_lsw;  /* address of Latch least-significant-word
143                                  * register */
144         uint16_t my_event_bits[4]; /* bit translations for IntSrc -->RDMISC2 */
145 };
146 
147 /* Counter overflow/index event flag masks for RDMISC2. */
148 #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 +  4)))
149 #define S626_OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
150 #define S626_EVBITS(C)  { 0, S626_OVERMASK(C), S626_INDXMASK(C), \
151                           S626_OVERMASK(C) | S626_INDXMASK(C) }
152 
153 /*
154  * Translation table to map IntSrc into equivalent RDMISC2 event flag  bits.
155  * static const uint16_t s626_event_bits[][4] =
156  *     { S626_EVBITS(0), S626_EVBITS(1), S626_EVBITS(2), S626_EVBITS(3),
157  *       S626_EVBITS(4), S626_EVBITS(5) };
158  */
159 
160 /*
161  * Enable/disable a function or test status bit(s) that are accessed
162  * through Main Control Registers 1 or 2.
163  */
164 static void s626_mc_enable(struct comedi_device *dev,
165                            unsigned int cmd, unsigned int reg)
166 {
167         struct s626_private *devpriv = dev->private;
168         unsigned int val = (cmd << 16) | cmd;
169 
170         mmiowb();
171         writel(val, devpriv->mmio + reg);
172 }
173 
174 static void s626_mc_disable(struct comedi_device *dev,
175                             unsigned int cmd, unsigned int reg)
176 {
177         struct s626_private *devpriv = dev->private;
178 
179         writel(cmd << 16 , devpriv->mmio + reg);
180         mmiowb();
181 }
182 
183 static bool s626_mc_test(struct comedi_device *dev,
184                          unsigned int cmd, unsigned int reg)
185 {
186         struct s626_private *devpriv = dev->private;
187         unsigned int val;
188 
189         val = readl(devpriv->mmio + reg);
190 
191         return (val & cmd) ? true : false;
192 }
193 
194 #define S626_BUGFIX_STREG(REGADRS)   ((REGADRS) - 4)
195 
196 /* Write a time slot control record to TSL2. */
197 #define S626_VECTPORT(VECTNUM)          (S626_P_TSL2 + ((VECTNUM) << 2))
198 
199 static const struct comedi_lrange s626_range_table = {
200         2, {
201                 BIP_RANGE(5),
202                 BIP_RANGE(10)
203         }
204 };
205 
206 /*
207  * Execute a DEBI transfer.  This must be called from within a critical section.
208  */
209 static void s626_debi_transfer(struct comedi_device *dev)
210 {
211         struct s626_private *devpriv = dev->private;
212         static const int timeout = 10000;
213         int i;
214 
215         /* Initiate upload of shadow RAM to DEBI control register */
216         s626_mc_enable(dev, S626_MC2_UPLD_DEBI, S626_P_MC2);
217 
218         /*
219          * Wait for completion of upload from shadow RAM to
220          * DEBI control register.
221          */
222         for (i = 0; i < timeout; i++) {
223                 if (s626_mc_test(dev, S626_MC2_UPLD_DEBI, S626_P_MC2))
224                         break;
225                 udelay(1);
226         }
227         if (i == timeout)
228                 comedi_error(dev,
229                         "Timeout while uploading to DEBI control register.");
230 
231         /* Wait until DEBI transfer is done */
232         for (i = 0; i < timeout; i++) {
233                 if (!(readl(devpriv->mmio + S626_P_PSR) & S626_PSR_DEBI_S))
234                         break;
235                 udelay(1);
236         }
237         if (i == timeout)
238                 comedi_error(dev, "DEBI transfer timeout.");
239 }
240 
241 /*
242  * Read a value from a gate array register.
243  */
244 static uint16_t s626_debi_read(struct comedi_device *dev, uint16_t addr)
245 {
246         struct s626_private *devpriv = dev->private;
247 
248         /* Set up DEBI control register value in shadow RAM */
249         writel(S626_DEBI_CMD_RDWORD | addr, devpriv->mmio + S626_P_DEBICMD);
250 
251         /*  Execute the DEBI transfer. */
252         s626_debi_transfer(dev);
253 
254         return readl(devpriv->mmio + S626_P_DEBIAD);
255 }
256 
257 /*
258  * Write a value to a gate array register.
259  */
260 static void s626_debi_write(struct comedi_device *dev, uint16_t addr,
261                             uint16_t wdata)
262 {
263         struct s626_private *devpriv = dev->private;
264 
265         /* Set up DEBI control register value in shadow RAM */
266         writel(S626_DEBI_CMD_WRWORD | addr, devpriv->mmio + S626_P_DEBICMD);
267         writel(wdata, devpriv->mmio + S626_P_DEBIAD);
268 
269         /*  Execute the DEBI transfer. */
270         s626_debi_transfer(dev);
271 }
272 
273 /*
274  * Replace the specified bits in a gate array register.  Imports: mask
275  * specifies bits that are to be preserved, wdata is new value to be
276  * or'd with the masked original.
277  */
278 static void s626_debi_replace(struct comedi_device *dev, unsigned int addr,
279                               unsigned int mask, unsigned int wdata)
280 {
281         struct s626_private *devpriv = dev->private;
282         unsigned int val;
283 
284         addr &= 0xffff;
285         writel(S626_DEBI_CMD_RDWORD | addr, devpriv->mmio + S626_P_DEBICMD);
286         s626_debi_transfer(dev);
287 
288         writel(S626_DEBI_CMD_WRWORD | addr, devpriv->mmio + S626_P_DEBICMD);
289         val = readl(devpriv->mmio + S626_P_DEBIAD);
290         val &= mask;
291         val |= wdata;
292         writel(val & 0xffff, devpriv->mmio + S626_P_DEBIAD);
293         s626_debi_transfer(dev);
294 }
295 
296 /* **************  EEPROM ACCESS FUNCTIONS  ************** */
297 
298 static int s626_i2c_handshake_eoc(struct comedi_device *dev,
299                                  struct comedi_subdevice *s,
300                                  struct comedi_insn *insn,
301                                  unsigned long context)
302 {
303         bool status;
304 
305         status = s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
306         if (status)
307                 return 0;
308         return -EBUSY;
309 }
310 
311 static int s626_i2c_handshake(struct comedi_device *dev, uint32_t val)
312 {
313         struct s626_private *devpriv = dev->private;
314         unsigned int ctrl;
315         int ret;
316 
317         /* Write I2C command to I2C Transfer Control shadow register */
318         writel(val, devpriv->mmio + S626_P_I2CCTRL);
319 
320         /*
321          * Upload I2C shadow registers into working registers and
322          * wait for upload confirmation.
323          */
324         s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
325         ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
326         if (ret)
327                 return ret;
328 
329         /* Wait until I2C bus transfer is finished or an error occurs */
330         do {
331                 ctrl = readl(devpriv->mmio + S626_P_I2CCTRL);
332         } while ((ctrl & (S626_I2C_BUSY | S626_I2C_ERR)) == S626_I2C_BUSY);
333 
334         /* Return non-zero if I2C error occurred */
335         return ctrl & S626_I2C_ERR;
336 }
337 
338 /* Read uint8_t from EEPROM. */
339 static uint8_t s626_i2c_read(struct comedi_device *dev, uint8_t addr)
340 {
341         struct s626_private *devpriv = dev->private;
342 
343         /*
344          * Send EEPROM target address:
345          *  Byte2 = I2C command: write to I2C EEPROM device.
346          *  Byte1 = EEPROM internal target address.
347          *  Byte0 = Not sent.
348          */
349         if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
350                                                 devpriv->i2c_adrs) |
351                                     S626_I2C_B1(S626_I2C_ATTRSTOP, addr) |
352                                     S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
353                 /* Abort function and declare error if handshake failed. */
354                 return 0;
355 
356         /*
357          * Execute EEPROM read:
358          *  Byte2 = I2C command: read from I2C EEPROM device.
359          *  Byte1 receives uint8_t from EEPROM.
360          *  Byte0 = Not sent.
361          */
362         if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
363                                            (devpriv->i2c_adrs | 1)) |
364                                     S626_I2C_B1(S626_I2C_ATTRSTOP, 0) |
365                                     S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
366                 /* Abort function and declare error if handshake failed. */
367                 return 0;
368 
369         return (readl(devpriv->mmio + S626_P_I2CCTRL) >> 16) & 0xff;
370 }
371 
372 /* ***********  DAC FUNCTIONS *********** */
373 
374 /* TrimDac LogicalChan-to-PhysicalChan mapping table. */
375 static const uint8_t s626_trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
376 
377 /* TrimDac LogicalChan-to-EepromAdrs mapping table. */
378 static const uint8_t s626_trimadrs[] = {
379         0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63
380 };
381 
382 enum {
383         s626_send_dac_wait_not_mc1_a2out,
384         s626_send_dac_wait_ssr_af2_out,
385         s626_send_dac_wait_fb_buffer2_msb_00,
386         s626_send_dac_wait_fb_buffer2_msb_ff
387 };
388 
389 static int s626_send_dac_eoc(struct comedi_device *dev,
390                              struct comedi_subdevice *s,
391                              struct comedi_insn *insn,
392                              unsigned long context)
393 {
394         struct s626_private *devpriv = dev->private;
395         unsigned int status;
396 
397         switch (context) {
398         case s626_send_dac_wait_not_mc1_a2out:
399                 status = readl(devpriv->mmio + S626_P_MC1);
400                 if (!(status & S626_MC1_A2OUT))
401                         return 0;
402                 break;
403         case s626_send_dac_wait_ssr_af2_out:
404                 status = readl(devpriv->mmio + S626_P_SSR);
405                 if (status & S626_SSR_AF2_OUT)
406                         return 0;
407                 break;
408         case s626_send_dac_wait_fb_buffer2_msb_00:
409                 status = readl(devpriv->mmio + S626_P_FB_BUFFER2);
410                 if (!(status & 0xff000000))
411                         return 0;
412                 break;
413         case s626_send_dac_wait_fb_buffer2_msb_ff:
414                 status = readl(devpriv->mmio + S626_P_FB_BUFFER2);
415                 if (status & 0xff000000)
416                         return 0;
417                 break;
418         default:
419                 return -EINVAL;
420         }
421         return -EBUSY;
422 }
423 
424 /*
425  * Private helper function: Transmit serial data to DAC via Audio
426  * channel 2.  Assumes: (1) TSL2 slot records initialized, and (2)
427  * dacpol contains valid target image.
428  */
429 static int s626_send_dac(struct comedi_device *dev, uint32_t val)
430 {
431         struct s626_private *devpriv = dev->private;
432         int ret;
433 
434         /* START THE SERIAL CLOCK RUNNING ------------- */
435 
436         /*
437          * Assert DAC polarity control and enable gating of DAC serial clock
438          * and audio bit stream signals.  At this point in time we must be
439          * assured of being in time slot 0.  If we are not in slot 0, the
440          * serial clock and audio stream signals will be disabled; this is
441          * because the following s626_debi_write statement (which enables
442          * signals to be passed through the gate array) would execute before
443          * the trailing edge of WS1/WS3 (which turns off the signals), thus
444          * causing the signals to be inactive during the DAC write.
445          */
446         s626_debi_write(dev, S626_LP_DACPOL, devpriv->dacpol);
447 
448         /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
449 
450         /* Copy DAC setpoint value to DAC's output DMA buffer. */
451         /* writel(val, devpriv->mmio + (uint32_t)devpriv->dac_wbuf); */
452         *devpriv->dac_wbuf = val;
453 
454         /*
455          * Enable the output DMA transfer. This will cause the DMAC to copy
456          * the DAC's data value to A2's output FIFO. The DMA transfer will
457          * then immediately terminate because the protection address is
458          * reached upon transfer of the first DWORD value.
459          */
460         s626_mc_enable(dev, S626_MC1_A2OUT, S626_P_MC1);
461 
462         /* While the DMA transfer is executing ... */
463 
464         /*
465          * Reset Audio2 output FIFO's underflow flag (along with any
466          * other FIFO underflow/overflow flags). When set, this flag
467          * will indicate that we have emerged from slot 0.
468          */
469         writel(S626_ISR_AFOU, devpriv->mmio + S626_P_ISR);
470 
471         /*
472          * Wait for the DMA transfer to finish so that there will be data
473          * available in the FIFO when time slot 1 tries to transfer a DWORD
474          * from the FIFO to the output buffer register.  We test for DMA
475          * Done by polling the DMAC enable flag; this flag is automatically
476          * cleared when the transfer has finished.
477          */
478         ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
479                              s626_send_dac_wait_not_mc1_a2out);
480         if (ret) {
481                 comedi_error(dev, "DMA transfer timeout.");
482                 return ret;
483         }
484 
485         /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
486 
487         /*
488          * FIFO data is now available, so we enable execution of time slots
489          * 1 and higher by clearing the EOS flag in slot 0.  Note that SD3
490          * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
491          * detection.
492          */
493         writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2,
494                devpriv->mmio + S626_VECTPORT(0));
495 
496         /*
497          * Wait for slot 1 to execute to ensure that the Packet will be
498          * transmitted.  This is detected by polling the Audio2 output FIFO
499          * underflow flag, which will be set when slot 1 execution has
500          * finished transferring the DAC's data DWORD from the output FIFO
501          * to the output buffer register.
502          */
503         ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
504                              s626_send_dac_wait_ssr_af2_out);
505         if (ret) {
506                 comedi_error(dev, "TSL timeout waiting for slot 1 to execute.");
507                 return ret;
508         }
509 
510         /*
511          * Set up to trap execution at slot 0 when the TSL sequencer cycles
512          * back to slot 0 after executing the EOS in slot 5.  Also,
513          * simultaneously shift out and in the 0x00 that is ALWAYS the value
514          * stored in the last byte to be shifted out of the FIFO's DWORD
515          * buffer register.
516          */
517         writel(S626_XSD2 | S626_XFIFO_2 | S626_RSD2 | S626_SIB_A2 | S626_EOS,
518                devpriv->mmio + S626_VECTPORT(0));
519 
520         /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
521 
522         /*
523          * Wait for the TSL to finish executing all time slots before
524          * exiting this function.  We must do this so that the next DAC
525          * write doesn't start, thereby enabling clock/chip select signals:
526          *
527          * 1. Before the TSL sequence cycles back to slot 0, which disables
528          *    the clock/cs signal gating and traps slot // list execution.
529          *    we have not yet finished slot 5 then the clock/cs signals are
530          *    still gated and we have not finished transmitting the stream.
531          *
532          * 2. While slots 2-5 are executing due to a late slot 0 trap.  In
533          *    this case, the slot sequence is currently repeating, but with
534          *    clock/cs signals disabled.  We must wait for slot 0 to trap
535          *    execution before setting up the next DAC setpoint DMA transfer
536          *    and enabling the clock/cs signals.  To detect the end of slot 5,
537          *    we test for the FB_BUFFER2 MSB contents to be equal to 0xFF.  If
538          *    the TSL has not yet finished executing slot 5 ...
539          */
540         if (readl(devpriv->mmio + S626_P_FB_BUFFER2) & 0xff000000) {
541                 /*
542                  * The trap was set on time and we are still executing somewhere
543                  * in slots 2-5, so we now wait for slot 0 to execute and trap
544                  * TSL execution.  This is detected when FB_BUFFER2 MSB changes
545                  * from 0xFF to 0x00, which slot 0 causes to happen by shifting
546                  * out/in on SD2 the 0x00 that is always referenced by slot 5.
547                  */
548                 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
549                                      s626_send_dac_wait_fb_buffer2_msb_00);
550                 if (ret) {
551                         comedi_error(dev,
552                                 "TSL timeout waiting for slot 0 to execute.");
553                         return ret;
554                 }
555         }
556         /*
557          * Either (1) we were too late setting the slot 0 trap; the TSL
558          * sequencer restarted slot 0 before we could set the EOS trap flag,
559          * or (2) we were not late and execution is now trapped at slot 0.
560          * In either case, we must now change slot 0 so that it will store
561          * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
562          * In order to do this, we reprogram slot 0 so that it will shift in
563          * SD3, which is driven only by a pull-up resistor.
564          */
565         writel(S626_RSD3 | S626_SIB_A2 | S626_EOS,
566                devpriv->mmio + S626_VECTPORT(0));
567 
568         /*
569          * Wait for slot 0 to execute, at which time the TSL is setup for
570          * the next DAC write.  This is detected when FB_BUFFER2 MSB changes
571          * from 0x00 to 0xFF.
572          */
573         ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
574                              s626_send_dac_wait_fb_buffer2_msb_ff);
575         if (ret) {
576                 comedi_error(dev, "TSL timeout waiting for slot 0 to execute.");
577                 return ret;
578         }
579         return 0;
580 }
581 
582 /*
583  * Private helper function: Write setpoint to an application DAC channel.
584  */
585 static int s626_set_dac(struct comedi_device *dev, uint16_t chan,
586                          int16_t dacdata)
587 {
588         struct s626_private *devpriv = dev->private;
589         uint16_t signmask;
590         uint32_t ws_image;
591         uint32_t val;
592 
593         /*
594          * Adjust DAC data polarity and set up Polarity Control Register image.
595          */
596         signmask = 1 << chan;
597         if (dacdata < 0) {
598                 dacdata = -dacdata;
599                 devpriv->dacpol |= signmask;
600         } else {
601                 devpriv->dacpol &= ~signmask;
602         }
603 
604         /* Limit DAC setpoint value to valid range. */
605         if ((uint16_t)dacdata > 0x1FFF)
606                 dacdata = 0x1FFF;
607 
608         /*
609          * Set up TSL2 records (aka "vectors") for DAC update.  Vectors V2
610          * and V3 transmit the setpoint to the target DAC.  V4 and V5 send
611          * data to a non-existent TrimDac channel just to keep the clock
612          * running after sending data to the target DAC.  This is necessary
613          * to eliminate the clock glitch that would otherwise occur at the
614          * end of the target DAC's serial data stream.  When the sequence
615          * restarts at V0 (after executing V5), the gate array automatically
616          * disables gating for the DAC clock and all DAC chip selects.
617          */
618 
619         /* Choose DAC chip select to be asserted */
620         ws_image = (chan & 2) ? S626_WS1 : S626_WS2;
621         /* Slot 2: Transmit high data byte to target DAC */
622         writel(S626_XSD2 | S626_XFIFO_1 | ws_image,
623                devpriv->mmio + S626_VECTPORT(2));
624         /* Slot 3: Transmit low data byte to target DAC */
625         writel(S626_XSD2 | S626_XFIFO_0 | ws_image,
626                devpriv->mmio + S626_VECTPORT(3));
627         /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
628         writel(S626_XSD2 | S626_XFIFO_3 | S626_WS3,
629                devpriv->mmio + S626_VECTPORT(4));
630         /* Slot 5: running after writing target DAC's low data byte */
631         writel(S626_XSD2 | S626_XFIFO_2 | S626_WS3 | S626_EOS,
632                devpriv->mmio + S626_VECTPORT(5));
633 
634         /*
635          * Construct and transmit target DAC's serial packet:
636          * (A10D DDDD), (DDDD DDDD), (0x0F), (0x00) where A is chan<0>,
637          * and D<12:0> is the DAC setpoint.  Append a WORD value (that writes
638          * to a  non-existent TrimDac channel) that serves to keep the clock
639          * running after the packet has been sent to the target DAC.
640          */
641         val = 0x0F000000;       /* Continue clock after target DAC data
642                                  * (write to non-existent trimdac). */
643         val |= 0x00004000;      /* Address the two main dual-DAC devices
644                                  * (TSL's chip select enables target device). */
645         val |= ((uint32_t)(chan & 1) << 15);    /* Address the DAC channel
646                                                  * within the device. */
647         val |= (uint32_t)dacdata;       /* Include DAC setpoint data. */
648         return s626_send_dac(dev, val);
649 }
650 
651 static int s626_write_trim_dac(struct comedi_device *dev, uint8_t logical_chan,
652                                 uint8_t dac_data)
653 {
654         struct s626_private *devpriv = dev->private;
655         uint32_t chan;
656 
657         /*
658          * Save the new setpoint in case the application needs to read it back
659          * later.
660          */
661         devpriv->trim_setpoint[logical_chan] = (uint8_t)dac_data;
662 
663         /* Map logical channel number to physical channel number. */
664         chan = s626_trimchan[logical_chan];
665 
666         /*
667          * Set up TSL2 records for TrimDac write operation.  All slots shift
668          * 0xFF in from pulled-up SD3 so that the end of the slot sequence
669          * can be detected.
670          */
671 
672         /* Slot 2: Send high uint8_t to target TrimDac */
673         writel(S626_XSD2 | S626_XFIFO_1 | S626_WS3,
674                devpriv->mmio + S626_VECTPORT(2));
675         /* Slot 3: Send low uint8_t to target TrimDac */
676         writel(S626_XSD2 | S626_XFIFO_0 | S626_WS3,
677                devpriv->mmio + S626_VECTPORT(3));
678         /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */
679         writel(S626_XSD2 | S626_XFIFO_3 | S626_WS1,
680                devpriv->mmio + S626_VECTPORT(4));
681         /* Slot 5: Send NOP low  uint8_t to DAC0 */
682         writel(S626_XSD2 | S626_XFIFO_2 | S626_WS1 | S626_EOS,
683                devpriv->mmio + S626_VECTPORT(5));
684 
685         /*
686          * Construct and transmit target DAC's serial packet:
687          * (0000 AAAA), (DDDD DDDD), (0x00), (0x00) where A<3:0> is the
688          * DAC channel's address, and D<7:0> is the DAC setpoint.  Append a
689          * WORD value (that writes a channel 0 NOP command to a non-existent
690          * main DAC channel) that serves to keep the clock running after the
691          * packet has been sent to the target DAC.
692          */
693 
694         /*
695          * Address the DAC channel within the trimdac device.
696          * Include DAC setpoint data.
697          */
698         return s626_send_dac(dev, (chan << 8) | dac_data);
699 }
700 
701 static int s626_load_trim_dacs(struct comedi_device *dev)
702 {
703         uint8_t i;
704         int ret;
705 
706         /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
707         for (i = 0; i < ARRAY_SIZE(s626_trimchan); i++) {
708                 ret = s626_write_trim_dac(dev, i,
709                                     s626_i2c_read(dev, s626_trimadrs[i]));
710                 if (ret)
711                         return ret;
712         }
713         return 0;
714 }
715 
716 /* ******  COUNTER FUNCTIONS  ******* */
717 
718 /*
719  * All counter functions address a specific counter by means of the
720  * "Counter" argument, which is a logical counter number.  The Counter
721  * argument may have any of the following legal values: 0=0A, 1=1A,
722  * 2=2A, 3=0B, 4=1B, 5=2B.
723  */
724 
725 /*
726  * Read a counter's output latch.
727  */
728 static uint32_t s626_read_latch(struct comedi_device *dev,
729                                 const struct s626_enc_info *k)
730 {
731         uint32_t value;
732 
733         /* Latch counts and fetch LSW of latched counts value. */
734         value = s626_debi_read(dev, k->my_latch_lsw);
735 
736         /* Fetch MSW of latched counts and combine with LSW. */
737         value |= ((uint32_t)s626_debi_read(dev, k->my_latch_lsw + 2) << 16);
738 
739         /* Return latched counts. */
740         return value;
741 }
742 
743 /*
744  * Return/set a counter pair's latch trigger source.  0: On read
745  * access, 1: A index latches A, 2: B index latches B, 3: A overflow
746  * latches B.
747  */
748 static void s626_set_latch_source(struct comedi_device *dev,
749                                   const struct s626_enc_info *k, uint16_t value)
750 {
751         s626_debi_replace(dev, k->my_crb,
752                           ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_LATCHSRC),
753                           S626_SET_CRB_LATCHSRC(value));
754 }
755 
756 /*
757  * Write value into counter preload register.
758  */
759 static void s626_preload(struct comedi_device *dev,
760                          const struct s626_enc_info *k, uint32_t value)
761 {
762         s626_debi_write(dev, k->my_latch_lsw, value);
763         s626_debi_write(dev, k->my_latch_lsw + 2, value >> 16);
764 }
765 
766 /* ******  PRIVATE COUNTER FUNCTIONS ****** */
767 
768 /*
769  * Reset a counter's index and overflow event capture flags.
770  */
771 static void s626_reset_cap_flags_a(struct comedi_device *dev,
772                                    const struct s626_enc_info *k)
773 {
774         s626_debi_replace(dev, k->my_crb, ~S626_CRBMSK_INTCTRL,
775                           (S626_SET_CRB_INTRESETCMD(1) |
776                            S626_SET_CRB_INTRESET_A(1)));
777 }
778 
779 static void s626_reset_cap_flags_b(struct comedi_device *dev,
780                                    const struct s626_enc_info *k)
781 {
782         s626_debi_replace(dev, k->my_crb, ~S626_CRBMSK_INTCTRL,
783                           (S626_SET_CRB_INTRESETCMD(1) |
784                            S626_SET_CRB_INTRESET_B(1)));
785 }
786 
787 /*
788  * Return counter setup in a format (COUNTER_SETUP) that is consistent
789  * for both A and B counters.
790  */
791 static uint16_t s626_get_mode_a(struct comedi_device *dev,
792                                 const struct s626_enc_info *k)
793 {
794         uint16_t cra;
795         uint16_t crb;
796         uint16_t setup;
797         unsigned cntsrc, clkmult, clkpol, encmode;
798 
799         /* Fetch CRA and CRB register images. */
800         cra = s626_debi_read(dev, k->my_cra);
801         crb = s626_debi_read(dev, k->my_crb);
802 
803         /*
804          * Populate the standardized counter setup bit fields.
805          */
806         setup =
807                 /* LoadSrc  = LoadSrcA. */
808                 S626_SET_STD_LOADSRC(S626_GET_CRA_LOADSRC_A(cra)) |
809                 /* LatchSrc = LatchSrcA. */
810                 S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) |
811                 /* IntSrc   = IntSrcA. */
812                 S626_SET_STD_INTSRC(S626_GET_CRA_INTSRC_A(cra)) |
813                 /* IndxSrc  = IndxSrcA. */
814                 S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_A(cra)) |
815                 /* IndxPol  = IndxPolA. */
816                 S626_SET_STD_INDXPOL(S626_GET_CRA_INDXPOL_A(cra)) |
817                 /* ClkEnab  = ClkEnabA. */
818                 S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_A(crb));
819 
820         /* Adjust mode-dependent parameters. */
821         cntsrc = S626_GET_CRA_CNTSRC_A(cra);
822         if (cntsrc & S626_CNTSRC_SYSCLK) {
823                 /* Timer mode (CntSrcA<1> == 1): */
824                 encmode = S626_ENCMODE_TIMER;
825                 /* Set ClkPol to indicate count direction (CntSrcA<0>). */
826                 clkpol = cntsrc & 1;
827                 /* ClkMult must be 1x in Timer mode. */
828                 clkmult = S626_CLKMULT_1X;
829         } else {
830                 /* Counter mode (CntSrcA<1> == 0): */
831                 encmode = S626_ENCMODE_COUNTER;
832                 /* Pass through ClkPol. */
833                 clkpol = S626_GET_CRA_CLKPOL_A(cra);
834                 /* Force ClkMult to 1x if not legal, else pass through. */
835                 clkmult = S626_GET_CRA_CLKMULT_A(cra);
836                 if (clkmult == S626_CLKMULT_SPECIAL)
837                         clkmult = S626_CLKMULT_1X;
838         }
839         setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) |
840                  S626_SET_STD_CLKPOL(clkpol);
841 
842         /* Return adjusted counter setup. */
843         return setup;
844 }
845 
846 static uint16_t s626_get_mode_b(struct comedi_device *dev,
847                                 const struct s626_enc_info *k)
848 {
849         uint16_t cra;
850         uint16_t crb;
851         uint16_t setup;
852         unsigned cntsrc, clkmult, clkpol, encmode;
853 
854         /* Fetch CRA and CRB register images. */
855         cra = s626_debi_read(dev, k->my_cra);
856         crb = s626_debi_read(dev, k->my_crb);
857 
858         /*
859          * Populate the standardized counter setup bit fields.
860          */
861         setup =
862                 /* IntSrc   = IntSrcB. */
863                 S626_SET_STD_INTSRC(S626_GET_CRB_INTSRC_B(crb)) |
864                 /* LatchSrc = LatchSrcB. */
865                 S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) |
866                 /* LoadSrc  = LoadSrcB. */
867                 S626_SET_STD_LOADSRC(S626_GET_CRB_LOADSRC_B(crb)) |
868                 /* IndxPol  = IndxPolB. */
869                 S626_SET_STD_INDXPOL(S626_GET_CRB_INDXPOL_B(crb)) |
870                 /* ClkEnab  = ClkEnabB. */
871                 S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_B(crb)) |
872                 /* IndxSrc  = IndxSrcB. */
873                 S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_B(cra));
874 
875         /* Adjust mode-dependent parameters. */
876         cntsrc = S626_GET_CRA_CNTSRC_B(cra);
877         clkmult = S626_GET_CRB_CLKMULT_B(crb);
878         if (clkmult == S626_CLKMULT_SPECIAL) {
879                 /* Extender mode (ClkMultB == S626_CLKMULT_SPECIAL): */
880                 encmode = S626_ENCMODE_EXTENDER;
881                 /* Indicate multiplier is 1x. */
882                 clkmult = S626_CLKMULT_1X;
883                 /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
884                 clkpol = cntsrc & 1;
885         } else if (cntsrc & S626_CNTSRC_SYSCLK) {
886                 /* Timer mode (CntSrcB<1> == 1): */
887                 encmode = S626_ENCMODE_TIMER;
888                 /* Indicate multiplier is 1x. */
889                 clkmult = S626_CLKMULT_1X;
890                 /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
891                 clkpol = cntsrc & 1;
892         } else {
893                 /* If Counter mode (CntSrcB<1> == 0): */
894                 encmode = S626_ENCMODE_COUNTER;
895                 /* Clock multiplier is passed through. */
896                 /* Clock polarity is passed through. */
897                 clkpol = S626_GET_CRB_CLKPOL_B(crb);
898         }
899         setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) |
900                  S626_SET_STD_CLKPOL(clkpol);
901 
902         /* Return adjusted counter setup. */
903         return setup;
904 }
905 
906 /*
907  * Set the operating mode for the specified counter.  The setup
908  * parameter is treated as a COUNTER_SETUP data type.  The following
909  * parameters are programmable (all other parms are ignored): ClkMult,
910  * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
911  */
912 static void s626_set_mode_a(struct comedi_device *dev,
913                             const struct s626_enc_info *k, uint16_t setup,
914                             uint16_t disable_int_src)
915 {
916         struct s626_private *devpriv = dev->private;
917         uint16_t cra;
918         uint16_t crb;
919         unsigned cntsrc, clkmult, clkpol;
920 
921         /* Initialize CRA and CRB images. */
922         /* Preload trigger is passed through. */
923         cra = S626_SET_CRA_LOADSRC_A(S626_GET_STD_LOADSRC(setup));
924         /* IndexSrc is passed through. */
925         cra |= S626_SET_CRA_INDXSRC_A(S626_GET_STD_INDXSRC(setup));
926 
927         /* Reset any pending CounterA event captures. */
928         crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_A(1);
929         /* Clock enable is passed through. */
930         crb |= S626_SET_CRB_CLKENAB_A(S626_GET_STD_CLKENAB(setup));
931 
932         /* Force IntSrc to Disabled if disable_int_src is asserted. */
933         if (!disable_int_src)
934                 cra |= S626_SET_CRA_INTSRC_A(S626_GET_STD_INTSRC(setup));
935 
936         /* Populate all mode-dependent attributes of CRA & CRB images. */
937         clkpol = S626_GET_STD_CLKPOL(setup);
938         switch (S626_GET_STD_ENCMODE(setup)) {
939         case S626_ENCMODE_EXTENDER: /* Extender Mode: */
940                 /* Force to Timer mode (Extender valid only for B counters). */
941                 /* Fall through to case S626_ENCMODE_TIMER: */
942         case S626_ENCMODE_TIMER:        /* Timer Mode: */
943                 /* CntSrcA<1> selects system clock */
944                 cntsrc = S626_CNTSRC_SYSCLK;
945                 /* Count direction (CntSrcA<0>) obtained from ClkPol. */
946                 cntsrc |= clkpol;
947                 /* ClkPolA behaves as always-on clock enable. */
948                 clkpol = 1;
949                 /* ClkMult must be 1x. */
950                 clkmult = S626_CLKMULT_1X;
951                 break;
952         default:                /* Counter Mode: */
953                 /* Select ENC_C and ENC_D as clock/direction inputs. */
954                 cntsrc = S626_CNTSRC_ENCODER;
955                 /* Clock polarity is passed through. */
956                 /* Force multiplier to x1 if not legal, else pass through. */
957                 clkmult = S626_GET_STD_CLKMULT(setup);
958                 if (clkmult == S626_CLKMULT_SPECIAL)
959                         clkmult = S626_CLKMULT_1X;
960                 break;
961         }
962         cra |= S626_SET_CRA_CNTSRC_A(cntsrc) | S626_SET_CRA_CLKPOL_A(clkpol) |
963                S626_SET_CRA_CLKMULT_A(clkmult);
964 
965         /*
966          * Force positive index polarity if IndxSrc is software-driven only,
967          * otherwise pass it through.
968          */
969         if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
970                 cra |= S626_SET_CRA_INDXPOL_A(S626_GET_STD_INDXPOL(setup));
971 
972         /*
973          * If IntSrc has been forced to Disabled, update the MISC2 interrupt
974          * enable mask to indicate the counter interrupt is disabled.
975          */
976         if (disable_int_src)
977                 devpriv->counter_int_enabs &= ~k->my_event_bits[3];
978 
979         /*
980          * While retaining CounterB and LatchSrc configurations, program the
981          * new counter operating mode.
982          */
983         s626_debi_replace(dev, k->my_cra,
984                           S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B, cra);
985         s626_debi_replace(dev, k->my_crb,
986                           ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), crb);
987 }
988 
989 static void s626_set_mode_b(struct comedi_device *dev,
990                             const struct s626_enc_info *k, uint16_t setup,
991                             uint16_t disable_int_src)
992 {
993         struct s626_private *devpriv = dev->private;
994         uint16_t cra;
995         uint16_t crb;
996         unsigned cntsrc, clkmult, clkpol;
997 
998         /* Initialize CRA and CRB images. */
999         /* IndexSrc is passed through. */
1000         cra = S626_SET_CRA_INDXSRC_B(S626_GET_STD_INDXSRC(setup));
1001 
1002         /* Reset event captures and disable interrupts. */
1003         crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_B(1);
1004         /* Clock enable is passed through. */
1005         crb |= S626_SET_CRB_CLKENAB_B(S626_GET_STD_CLKENAB(setup));
1006         /* Preload trigger source is passed through. */
1007         crb |= S626_SET_CRB_LOADSRC_B(S626_GET_STD_LOADSRC(setup));
1008 
1009         /* Force IntSrc to Disabled if disable_int_src is asserted. */
1010         if (!disable_int_src)
1011                 crb |= S626_SET_CRB_INTSRC_B(S626_GET_STD_INTSRC(setup));
1012 
1013         /* Populate all mode-dependent attributes of CRA & CRB images. */
1014         clkpol = S626_GET_STD_CLKPOL(setup);
1015         switch (S626_GET_STD_ENCMODE(setup)) {
1016         case S626_ENCMODE_TIMER:        /* Timer Mode: */
1017                 /* CntSrcB<1> selects system clock */
1018                 cntsrc = S626_CNTSRC_SYSCLK;
1019                 /* with direction (CntSrcB<0>) obtained from ClkPol. */
1020                 cntsrc |= clkpol;
1021                 /* ClkPolB behaves as always-on clock enable. */
1022                 clkpol = 1;
1023                 /* ClkMultB must be 1x. */
1024                 clkmult = S626_CLKMULT_1X;
1025                 break;
1026         case S626_ENCMODE_EXTENDER:     /* Extender Mode: */
1027                 /* CntSrcB source is OverflowA (same as "timer") */
1028                 cntsrc = S626_CNTSRC_SYSCLK;
1029                 /* with direction obtained from ClkPol. */
1030                 cntsrc |= clkpol;
1031                 /* ClkPolB controls IndexB -- always set to active. */
1032                 clkpol = 1;
1033                 /* ClkMultB selects OverflowA as the clock source. */
1034                 clkmult = S626_CLKMULT_SPECIAL;
1035                 break;
1036         default:                /* Counter Mode: */
1037                 /* Select ENC_C and ENC_D as clock/direction inputs. */
1038                 cntsrc = S626_CNTSRC_ENCODER;
1039                 /* ClkPol is passed through. */
1040                 /* Force ClkMult to x1 if not legal, otherwise pass through. */
1041                 clkmult = S626_GET_STD_CLKMULT(setup);
1042                 if (clkmult == S626_CLKMULT_SPECIAL)
1043                         clkmult = S626_CLKMULT_1X;
1044                 break;
1045         }
1046         cra |= S626_SET_CRA_CNTSRC_B(cntsrc);
1047         crb |= S626_SET_CRB_CLKPOL_B(clkpol) | S626_SET_CRB_CLKMULT_B(clkmult);
1048 
1049         /*
1050          * Force positive index polarity if IndxSrc is software-driven only,
1051          * otherwise pass it through.
1052          */
1053         if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
1054                 crb |= S626_SET_CRB_INDXPOL_B(S626_GET_STD_INDXPOL(setup));
1055 
1056         /*
1057          * If IntSrc has been forced to Disabled, update the MISC2 interrupt
1058          * enable mask to indicate the counter interrupt is disabled.
1059          */
1060         if (disable_int_src)
1061                 devpriv->counter_int_enabs &= ~k->my_event_bits[3];
1062 
1063         /*
1064          * While retaining CounterA and LatchSrc configurations, program the
1065          * new counter operating mode.
1066          */
1067         s626_debi_replace(dev, k->my_cra,
1068                           ~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B), cra);
1069         s626_debi_replace(dev, k->my_crb,
1070                           S626_CRBMSK_CLKENAB_A | S626_CRBMSK_LATCHSRC, crb);
1071 }
1072 
1073 /*
1074  * Return/set a counter's enable.  enab: 0=always enabled, 1=enabled by index.
1075  */
1076 static void s626_set_enable_a(struct comedi_device *dev,
1077                               const struct s626_enc_info *k, uint16_t enab)
1078 {
1079         s626_debi_replace(dev, k->my_crb,
1080                           ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A),
1081                           S626_SET_CRB_CLKENAB_A(enab));
1082 }
1083 
1084 static void s626_set_enable_b(struct comedi_device *dev,
1085                               const struct s626_enc_info *k, uint16_t enab)
1086 {
1087         s626_debi_replace(dev, k->my_crb,
1088                           ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_B),
1089                           S626_SET_CRB_CLKENAB_B(enab));
1090 }
1091 
1092 static uint16_t s626_get_enable_a(struct comedi_device *dev,
1093                                   const struct s626_enc_info *k)
1094 {
1095         return S626_GET_CRB_CLKENAB_A(s626_debi_read(dev, k->my_crb));
1096 }
1097 
1098 static uint16_t s626_get_enable_b(struct comedi_device *dev,
1099                                   const struct s626_enc_info *k)
1100 {
1101         return S626_GET_CRB_CLKENAB_B(s626_debi_read(dev, k->my_crb));
1102 }
1103 
1104 #ifdef unused
1105 static uint16_t s626_get_latch_source(struct comedi_device *dev,
1106                                       const struct s626_enc_info *k)
1107 {
1108         return S626_GET_CRB_LATCHSRC(s626_debi_read(dev, k->my_crb));
1109 }
1110 #endif
1111 
1112 /*
1113  * Return/set the event that will trigger transfer of the preload
1114  * register into the counter.  0=ThisCntr_Index, 1=ThisCntr_Overflow,
1115  * 2=OverflowA (B counters only), 3=disabled.
1116  */
1117 static void s626_set_load_trig_a(struct comedi_device *dev,
1118                                  const struct s626_enc_info *k, uint16_t trig)
1119 {
1120         s626_debi_replace(dev, k->my_cra, ~S626_CRAMSK_LOADSRC_A,
1121                           S626_SET_CRA_LOADSRC_A(trig));
1122 }
1123 
1124 static void s626_set_load_trig_b(struct comedi_device *dev,
1125                                  const struct s626_enc_info *k, uint16_t trig)
1126 {
1127         s626_debi_replace(dev, k->my_crb,
1128                           ~(S626_CRBMSK_LOADSRC_B | S626_CRBMSK_INTCTRL),
1129                           S626_SET_CRB_LOADSRC_B(trig));
1130 }
1131 
1132 static uint16_t s626_get_load_trig_a(struct comedi_device *dev,
1133                                      const struct s626_enc_info *k)
1134 {
1135         return S626_GET_CRA_LOADSRC_A(s626_debi_read(dev, k->my_cra));
1136 }
1137 
1138 static uint16_t s626_get_load_trig_b(struct comedi_device *dev,
1139                                      const struct s626_enc_info *k)
1140 {
1141         return S626_GET_CRB_LOADSRC_B(s626_debi_read(dev, k->my_crb));
1142 }
1143 
1144 /*
1145  * Return/set counter interrupt source and clear any captured
1146  * index/overflow events.  int_source: 0=Disabled, 1=OverflowOnly,
1147  * 2=IndexOnly, 3=IndexAndOverflow.
1148  */
1149 static void s626_set_int_src_a(struct comedi_device *dev,
1150                                const struct s626_enc_info *k,
1151                                uint16_t int_source)
1152 {
1153         struct s626_private *devpriv = dev->private;
1154 
1155         /* Reset any pending counter overflow or index captures. */
1156         s626_debi_replace(dev, k->my_crb, ~S626_CRBMSK_INTCTRL,
1157                           (S626_SET_CRB_INTRESETCMD(1) |
1158                            S626_SET_CRB_INTRESET_A(1)));
1159 
1160         /* Program counter interrupt source. */
1161         s626_debi_replace(dev, k->my_cra, ~S626_CRAMSK_INTSRC_A,
1162                           S626_SET_CRA_INTSRC_A(int_source));
1163 
1164         /* Update MISC2 interrupt enable mask. */
1165         devpriv->counter_int_enabs =
1166             (devpriv->counter_int_enabs & ~k->my_event_bits[3]) |
1167             k->my_event_bits[int_source];
1168 }
1169 
1170 static void s626_set_int_src_b(struct comedi_device *dev,
1171                                const struct s626_enc_info *k,
1172                                uint16_t int_source)
1173 {
1174         struct s626_private *devpriv = dev->private;
1175         uint16_t crb;
1176 
1177         /* Cache writeable CRB register image. */
1178         crb = s626_debi_read(dev, k->my_crb) & ~S626_CRBMSK_INTCTRL;
1179 
1180         /* Reset any pending counter overflow or index captures. */
1181         s626_debi_write(dev, k->my_crb, (crb | S626_SET_CRB_INTRESETCMD(1) |
1182                                          S626_SET_CRB_INTRESET_B(1)));
1183 
1184         /* Program counter interrupt source. */
1185         s626_debi_write(dev, k->my_crb, ((crb & ~S626_CRBMSK_INTSRC_B) |
1186                                          S626_SET_CRB_INTSRC_B(int_source)));
1187 
1188         /* Update MISC2 interrupt enable mask. */
1189         devpriv->counter_int_enabs =
1190                 (devpriv->counter_int_enabs & ~k->my_event_bits[3]) |
1191                 k->my_event_bits[int_source];
1192 }
1193 
1194 static uint16_t s626_get_int_src_a(struct comedi_device *dev,
1195                                    const struct s626_enc_info *k)
1196 {
1197         return S626_GET_CRA_INTSRC_A(s626_debi_read(dev, k->my_cra));
1198 }
1199 
1200 static uint16_t s626_get_int_src_b(struct comedi_device *dev,
1201                                    const struct s626_enc_info *k)
1202 {
1203         return S626_GET_CRB_INTSRC_B(s626_debi_read(dev, k->my_crb));
1204 }
1205 
1206 #ifdef unused
1207 /*
1208  * Return/set the clock multiplier.
1209  */
1210 static void s626_set_clk_mult(struct comedi_device *dev,
1211                               const struct s626_enc_info *k, uint16_t value)
1212 {
1213         k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_CLKMULT) |
1214                              S626_SET_STD_CLKMULT(value)), false);
1215 }
1216 
1217 static uint16_t s626_get_clk_mult(struct comedi_device *dev,
1218                                   const struct s626_enc_info *k)
1219 {
1220         return S626_GET_STD_CLKMULT(k->get_mode(dev, k));
1221 }
1222 
1223 /*
1224  * Return/set the clock polarity.
1225  */
1226 static void s626_set_clk_pol(struct comedi_device *dev,
1227                              const struct s626_enc_info *k, uint16_t value)
1228 {
1229         k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_CLKPOL) |
1230                              S626_SET_STD_CLKPOL(value)), false);
1231 }
1232 
1233 static uint16_t s626_get_clk_pol(struct comedi_device *dev,
1234                                  const struct s626_enc_info *k)
1235 {
1236         return S626_GET_STD_CLKPOL(k->get_mode(dev, k));
1237 }
1238 
1239 /*
1240  * Return/set the encoder mode.
1241  */
1242 static void s626_set_enc_mode(struct comedi_device *dev,
1243                               const struct s626_enc_info *k, uint16_t value)
1244 {
1245         k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_ENCMODE) |
1246                              S626_SET_STD_ENCMODE(value)), false);
1247 }
1248 
1249 static uint16_t s626_get_enc_mode(struct comedi_device *dev,
1250                                   const struct s626_enc_info *k)
1251 {
1252         return S626_GET_STD_ENCMODE(k->get_mode(dev, k));
1253 }
1254 
1255 /*
1256  * Return/set the index polarity.
1257  */
1258 static void s626_set_index_pol(struct comedi_device *dev,
1259                                const struct s626_enc_info *k, uint16_t value)
1260 {
1261         k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_INDXPOL) |
1262                              S626_SET_STD_INDXPOL(value != 0)), false);
1263 }
1264 
1265 static uint16_t s626_get_index_pol(struct comedi_device *dev,
1266                                    const struct s626_enc_info *k)
1267 {
1268         return S626_GET_STD_INDXPOL(k->get_mode(dev, k));
1269 }
1270 
1271 /*
1272  * Return/set the index source.
1273  */
1274 static void s626_set_index_src(struct comedi_device *dev,
1275                                const struct s626_enc_info *k, uint16_t value)
1276 {
1277         k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_INDXSRC) |
1278                              S626_SET_STD_INDXSRC(value != 0)), false);
1279 }
1280 
1281 static uint16_t s626_get_index_src(struct comedi_device *dev,
1282                                    const struct s626_enc_info *k)
1283 {
1284         return S626_GET_STD_INDXSRC(k->get_mode(dev, k));
1285 }
1286 #endif
1287 
1288 /*
1289  * Generate an index pulse.
1290  */
1291 static void s626_pulse_index_a(struct comedi_device *dev,
1292                                const struct s626_enc_info *k)
1293 {
1294         uint16_t cra;
1295 
1296         cra = s626_debi_read(dev, k->my_cra);
1297         /* Pulse index. */
1298         s626_debi_write(dev, k->my_cra, (cra ^ S626_CRAMSK_INDXPOL_A));
1299         s626_debi_write(dev, k->my_cra, cra);
1300 }
1301 
1302 static void s626_pulse_index_b(struct comedi_device *dev,
1303                                const struct s626_enc_info *k)
1304 {
1305         uint16_t crb;
1306 
1307         crb = s626_debi_read(dev, k->my_crb) & ~S626_CRBMSK_INTCTRL;
1308         /* Pulse index. */
1309         s626_debi_write(dev, k->my_crb, (crb ^ S626_CRBMSK_INDXPOL_B));
1310         s626_debi_write(dev, k->my_crb, crb);
1311 }
1312 
1313 static const struct s626_enc_info s626_enc_chan_info[] = {
1314         {
1315                 .get_enable             = s626_get_enable_a,
1316                 .get_int_src            = s626_get_int_src_a,
1317                 .get_load_trig          = s626_get_load_trig_a,
1318                 .get_mode               = s626_get_mode_a,
1319                 .pulse_index            = s626_pulse_index_a,
1320                 .set_enable             = s626_set_enable_a,
1321                 .set_int_src            = s626_set_int_src_a,
1322                 .set_load_trig          = s626_set_load_trig_a,
1323                 .set_mode               = s626_set_mode_a,
1324                 .reset_cap_flags        = s626_reset_cap_flags_a,
1325                 .my_cra                 = S626_LP_CR0A,
1326                 .my_crb                 = S626_LP_CR0B,
1327                 .my_latch_lsw           = S626_LP_CNTR0ALSW,
1328                 .my_event_bits          = S626_EVBITS(0),
1329         }, {
1330                 .get_enable             = s626_get_enable_a,
1331                 .get_int_src            = s626_get_int_src_a,
1332                 .get_load_trig          = s626_get_load_trig_a,
1333                 .get_mode               = s626_get_mode_a,
1334                 .pulse_index            = s626_pulse_index_a,
1335                 .set_enable             = s626_set_enable_a,
1336                 .set_int_src            = s626_set_int_src_a,
1337                 .set_load_trig          = s626_set_load_trig_a,
1338                 .set_mode               = s626_set_mode_a,
1339                 .reset_cap_flags        = s626_reset_cap_flags_a,
1340                 .my_cra                 = S626_LP_CR1A,
1341                 .my_crb                 = S626_LP_CR1B,
1342                 .my_latch_lsw           = S626_LP_CNTR1ALSW,
1343                 .my_event_bits          = S626_EVBITS(1),
1344         }, {
1345                 .get_enable             = s626_get_enable_a,
1346                 .get_int_src            = s626_get_int_src_a,
1347                 .get_load_trig          = s626_get_load_trig_a,
1348                 .get_mode               = s626_get_mode_a,
1349                 .pulse_index            = s626_pulse_index_a,
1350                 .set_enable             = s626_set_enable_a,
1351                 .set_int_src            = s626_set_int_src_a,
1352                 .set_load_trig          = s626_set_load_trig_a,
1353                 .set_mode               = s626_set_mode_a,
1354                 .reset_cap_flags        = s626_reset_cap_flags_a,
1355                 .my_cra                 = S626_LP_CR2A,
1356                 .my_crb                 = S626_LP_CR2B,
1357                 .my_latch_lsw           = S626_LP_CNTR2ALSW,
1358                 .my_event_bits          = S626_EVBITS(2),
1359         }, {
1360                 .get_enable             = s626_get_enable_b,
1361                 .get_int_src            = s626_get_int_src_b,
1362                 .get_load_trig          = s626_get_load_trig_b,
1363                 .get_mode               = s626_get_mode_b,
1364                 .pulse_index            = s626_pulse_index_b,
1365                 .set_enable             = s626_set_enable_b,
1366                 .set_int_src            = s626_set_int_src_b,
1367                 .set_load_trig          = s626_set_load_trig_b,
1368                 .set_mode               = s626_set_mode_b,
1369                 .reset_cap_flags        = s626_reset_cap_flags_b,
1370                 .my_cra                 = S626_LP_CR0A,
1371                 .my_crb                 = S626_LP_CR0B,
1372                 .my_latch_lsw           = S626_LP_CNTR0BLSW,
1373                 .my_event_bits          = S626_EVBITS(3),
1374         }, {
1375                 .get_enable             = s626_get_enable_b,
1376                 .get_int_src            = s626_get_int_src_b,
1377                 .get_load_trig          = s626_get_load_trig_b,
1378                 .get_mode               = s626_get_mode_b,
1379                 .pulse_index            = s626_pulse_index_b,
1380                 .set_enable             = s626_set_enable_b,
1381                 .set_int_src            = s626_set_int_src_b,
1382                 .set_load_trig          = s626_set_load_trig_b,
1383                 .set_mode               = s626_set_mode_b,
1384                 .reset_cap_flags        = s626_reset_cap_flags_b,
1385                 .my_cra                 = S626_LP_CR1A,
1386                 .my_crb                 = S626_LP_CR1B,
1387                 .my_latch_lsw           = S626_LP_CNTR1BLSW,
1388                 .my_event_bits          = S626_EVBITS(4),
1389         }, {
1390                 .get_enable             = s626_get_enable_b,
1391                 .get_int_src            = s626_get_int_src_b,
1392                 .get_load_trig          = s626_get_load_trig_b,
1393                 .get_mode               = s626_get_mode_b,
1394                 .pulse_index            = s626_pulse_index_b,
1395                 .set_enable             = s626_set_enable_b,
1396                 .set_int_src            = s626_set_int_src_b,
1397                 .set_load_trig          = s626_set_load_trig_b,
1398                 .set_mode               = s626_set_mode_b,
1399                 .reset_cap_flags        = s626_reset_cap_flags_b,
1400                 .my_cra                 = S626_LP_CR2A,
1401                 .my_crb                 = S626_LP_CR2B,
1402                 .my_latch_lsw           = S626_LP_CNTR2BLSW,
1403                 .my_event_bits          = S626_EVBITS(5),
1404         },
1405 };
1406 
1407 static unsigned int s626_ai_reg_to_uint(unsigned int data)
1408 {
1409         return ((data >> 18) & 0x3fff) ^ 0x2000;
1410 }
1411 
1412 static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
1413 {
1414         unsigned int group = chan / 16;
1415         unsigned int mask = 1 << (chan - (16 * group));
1416         unsigned int status;
1417 
1418         /* set channel to capture positive edge */
1419         status = s626_debi_read(dev, S626_LP_RDEDGSEL(group));
1420         s626_debi_write(dev, S626_LP_WREDGSEL(group), mask | status);
1421 
1422         /* enable interrupt on selected channel */
1423         status = s626_debi_read(dev, S626_LP_RDINTSEL(group));
1424         s626_debi_write(dev, S626_LP_WRINTSEL(group), mask | status);
1425 
1426         /* enable edge capture write command */
1427         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_EDCAP);
1428 
1429         /* enable edge capture on selected channel */
1430         status = s626_debi_read(dev, S626_LP_RDCAPSEL(group));
1431         s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask | status);
1432 
1433         return 0;
1434 }
1435 
1436 static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
1437                               unsigned int mask)
1438 {
1439         /* disable edge capture write command */
1440         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1441 
1442         /* enable edge capture on selected channel */
1443         s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask);
1444 
1445         return 0;
1446 }
1447 
1448 static int s626_dio_clear_irq(struct comedi_device *dev)
1449 {
1450         unsigned int group;
1451 
1452         /* disable edge capture write command */
1453         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1454 
1455         /* clear all dio pending events and interrupt */
1456         for (group = 0; group < S626_DIO_BANKS; group++)
1457                 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
1458 
1459         return 0;
1460 }
1461 
1462 static void s626_handle_dio_interrupt(struct comedi_device *dev,
1463                                       uint16_t irqbit, uint8_t group)
1464 {
1465         struct s626_private *devpriv = dev->private;
1466         struct comedi_subdevice *s = dev->read_subdev;
1467         struct comedi_cmd *cmd = &s->async->cmd;
1468 
1469         s626_dio_reset_irq(dev, group, irqbit);
1470 
1471         if (devpriv->ai_cmd_running) {
1472                 /* check if interrupt is an ai acquisition start trigger */
1473                 if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 &&
1474                     cmd->start_src == TRIG_EXT) {
1475                         /* Start executing the RPS program */
1476                         s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1477 
1478                         if (cmd->scan_begin_src == TRIG_EXT)
1479                                 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1480                 }
1481                 if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 &&
1482                     cmd->scan_begin_src == TRIG_EXT) {
1483                         /* Trigger ADC scan loop start */
1484                         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1485 
1486                         if (cmd->convert_src == TRIG_EXT) {
1487                                 devpriv->ai_convert_count = cmd->chanlist_len;
1488 
1489                                 s626_dio_set_irq(dev, cmd->convert_arg);
1490                         }
1491 
1492                         if (cmd->convert_src == TRIG_TIMER) {
1493                                 const struct s626_enc_info *k =
1494                                         &s626_enc_chan_info[5];
1495 
1496                                 devpriv->ai_convert_count = cmd->chanlist_len;
1497                                 k->set_enable(dev, k, S626_CLKENAB_ALWAYS);
1498                         }
1499                 }
1500                 if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 &&
1501                     cmd->convert_src == TRIG_EXT) {
1502                         /* Trigger ADC scan loop start */
1503                         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1504 
1505                         devpriv->ai_convert_count--;
1506                         if (devpriv->ai_convert_count > 0)
1507                                 s626_dio_set_irq(dev, cmd->convert_arg);
1508                 }
1509         }
1510 }
1511 
1512 static void s626_check_dio_interrupts(struct comedi_device *dev)
1513 {
1514         uint16_t irqbit;
1515         uint8_t group;
1516 
1517         for (group = 0; group < S626_DIO_BANKS; group++) {
1518                 irqbit = 0;
1519                 /* read interrupt type */
1520                 irqbit = s626_debi_read(dev, S626_LP_RDCAPFLG(group));
1521 
1522                 /* check if interrupt is generated from dio channels */
1523                 if (irqbit) {
1524                         s626_handle_dio_interrupt(dev, irqbit, group);
1525                         return;
1526                 }
1527         }
1528 }
1529 
1530 static void s626_check_counter_interrupts(struct comedi_device *dev)
1531 {
1532         struct s626_private *devpriv = dev->private;
1533         struct comedi_subdevice *s = dev->read_subdev;
1534         struct comedi_async *async = s->async;
1535         struct comedi_cmd *cmd = &async->cmd;
1536         const struct s626_enc_info *k;
1537         uint16_t irqbit;
1538 
1539         /* read interrupt type */
1540         irqbit = s626_debi_read(dev, S626_LP_RDMISC2);
1541 
1542         /* check interrupt on counters */
1543         if (irqbit & S626_IRQ_COINT1A) {
1544                 k = &s626_enc_chan_info[0];
1545 
1546                 /* clear interrupt capture flag */
1547                 k->reset_cap_flags(dev, k);
1548         }
1549         if (irqbit & S626_IRQ_COINT2A) {
1550                 k = &s626_enc_chan_info[1];
1551 
1552                 /* clear interrupt capture flag */
1553                 k->reset_cap_flags(dev, k);
1554         }
1555         if (irqbit & S626_IRQ_COINT3A) {
1556                 k = &s626_enc_chan_info[2];
1557 
1558                 /* clear interrupt capture flag */
1559                 k->reset_cap_flags(dev, k);
1560         }
1561         if (irqbit & S626_IRQ_COINT1B) {
1562                 k = &s626_enc_chan_info[3];
1563 
1564                 /* clear interrupt capture flag */
1565                 k->reset_cap_flags(dev, k);
1566         }
1567         if (irqbit & S626_IRQ_COINT2B) {
1568                 k = &s626_enc_chan_info[4];
1569 
1570                 /* clear interrupt capture flag */
1571                 k->reset_cap_flags(dev, k);
1572 
1573                 if (devpriv->ai_convert_count > 0) {
1574                         devpriv->ai_convert_count--;
1575                         if (devpriv->ai_convert_count == 0)
1576                                 k->set_enable(dev, k, S626_CLKENAB_INDEX);
1577 
1578                         if (cmd->convert_src == TRIG_TIMER) {
1579                                 /* Trigger ADC scan loop start */
1580                                 s626_mc_enable(dev, S626_MC2_ADC_RPS,
1581                                                S626_P_MC2);
1582                         }
1583                 }
1584         }
1585         if (irqbit & S626_IRQ_COINT3B) {
1586                 k = &s626_enc_chan_info[5];
1587 
1588                 /* clear interrupt capture flag */
1589                 k->reset_cap_flags(dev, k);
1590 
1591                 if (cmd->scan_begin_src == TRIG_TIMER) {
1592                         /* Trigger ADC scan loop start */
1593                         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1594                 }
1595 
1596                 if (cmd->convert_src == TRIG_TIMER) {
1597                         k = &s626_enc_chan_info[4];
1598                         devpriv->ai_convert_count = cmd->chanlist_len;
1599                         k->set_enable(dev, k, S626_CLKENAB_ALWAYS);
1600                 }
1601         }
1602 }
1603 
1604 static bool s626_handle_eos_interrupt(struct comedi_device *dev)
1605 {
1606         struct s626_private *devpriv = dev->private;
1607         struct comedi_subdevice *s = dev->read_subdev;
1608         struct comedi_async *async = s->async;
1609         struct comedi_cmd *cmd = &async->cmd;
1610         /*
1611          * Init ptr to DMA buffer that holds new ADC data.  We skip the
1612          * first uint16_t in the buffer because it contains junk data
1613          * from the final ADC of the previous poll list scan.
1614          */
1615         uint32_t *readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1616         bool finished = false;
1617         int i;
1618 
1619         /* get the data and hand it over to comedi */
1620         for (i = 0; i < cmd->chanlist_len; i++) {
1621                 unsigned short tempdata;
1622 
1623                 /*
1624                  * Convert ADC data to 16-bit integer values and copy
1625                  * to application buffer.
1626                  */
1627                 tempdata = s626_ai_reg_to_uint(*readaddr);
1628                 readaddr++;
1629 
1630                 /* put data into read buffer */
1631                 cfc_write_to_buffer(s, tempdata);
1632         }
1633 
1634         /* end of scan occurs */
1635         async->events |= COMEDI_CB_EOS;
1636 
1637         if (!devpriv->ai_continuous)
1638                 devpriv->ai_sample_count--;
1639         if (devpriv->ai_sample_count <= 0) {
1640                 devpriv->ai_cmd_running = 0;
1641 
1642                 /* Stop RPS program */
1643                 s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1644 
1645                 /* send end of acquisition */
1646                 async->events |= COMEDI_CB_EOA;
1647 
1648                 /* disable master interrupt */
1649                 finished = true;
1650         }
1651 
1652         if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT)
1653                 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1654 
1655         /* tell comedi that data is there */
1656         comedi_event(dev, s);
1657 
1658         return finished;
1659 }
1660 
1661 static irqreturn_t s626_irq_handler(int irq, void *d)
1662 {
1663         struct comedi_device *dev = d;
1664         struct s626_private *devpriv = dev->private;
1665         unsigned long flags;
1666         uint32_t irqtype, irqstatus;
1667 
1668         if (!dev->attached)
1669                 return IRQ_NONE;
1670         /* lock to avoid race with comedi_poll */
1671         spin_lock_irqsave(&dev->spinlock, flags);
1672 
1673         /* save interrupt enable register state */
1674         irqstatus = readl(devpriv->mmio + S626_P_IER);
1675 
1676         /* read interrupt type */
1677         irqtype = readl(devpriv->mmio + S626_P_ISR);
1678 
1679         /* disable master interrupt */
1680         writel(0, devpriv->mmio + S626_P_IER);
1681 
1682         /* clear interrupt */
1683         writel(irqtype, devpriv->mmio + S626_P_ISR);
1684 
1685         switch (irqtype) {
1686         case S626_IRQ_RPS1:     /* end_of_scan occurs */
1687                 if (s626_handle_eos_interrupt(dev))
1688                         irqstatus = 0;
1689                 break;
1690         case S626_IRQ_GPIO3:    /* check dio and counter interrupt */
1691                 /* s626_dio_clear_irq(dev); */
1692                 s626_check_dio_interrupts(dev);
1693                 s626_check_counter_interrupts(dev);
1694                 break;
1695         }
1696 
1697         /* enable interrupt */
1698         writel(irqstatus, devpriv->mmio + S626_P_IER);
1699 
1700         spin_unlock_irqrestore(&dev->spinlock, flags);
1701         return IRQ_HANDLED;
1702 }
1703 
1704 /*
1705  * This function builds the RPS program for hardware driven acquisition.
1706  */
1707 static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl)
1708 {
1709         struct s626_private *devpriv = dev->private;
1710         struct comedi_subdevice *s = dev->read_subdev;
1711         struct comedi_cmd *cmd = &s->async->cmd;
1712         uint32_t *rps;
1713         uint32_t jmp_adrs;
1714         uint16_t i;
1715         uint16_t n;
1716         uint32_t local_ppl;
1717 
1718         /* Stop RPS program in case it is currently running */
1719         s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1720 
1721         /* Set starting logical address to write RPS commands. */
1722         rps = (uint32_t *)devpriv->rps_buf.logical_base;
1723 
1724         /* Initialize RPS instruction pointer */
1725         writel((uint32_t)devpriv->rps_buf.physical_base,
1726                devpriv->mmio + S626_P_RPSADDR1);
1727 
1728         /* Construct RPS program in rps_buf DMA buffer */
1729         if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
1730                 /* Wait for Start trigger. */
1731                 *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1732                 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1733         }
1734 
1735         /*
1736          * SAA7146 BUG WORKAROUND Do a dummy DEBI Write.  This is necessary
1737          * because the first RPS DEBI Write following a non-RPS DEBI write
1738          * seems to always fail.  If we don't do this dummy write, the ADC
1739          * gain might not be set to the value required for the first slot in
1740          * the poll list; the ADC gain would instead remain unchanged from
1741          * the previously programmed value.
1742          */
1743         /* Write DEBI Write command and address to shadow RAM. */
1744         *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1745         *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1746         *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1747         /* Write DEBI immediate data  to shadow RAM: */
1748         *rps++ = S626_GSEL_BIPOLAR5V;   /* arbitrary immediate data  value. */
1749         *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1750         /* Reset "shadow RAM  uploaded" flag. */
1751         /* Invoke shadow RAM upload. */
1752         *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1753         /* Wait for shadow upload to finish. */
1754         *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1755 
1756         /*
1757          * Digitize all slots in the poll list. This is implemented as a
1758          * for loop to limit the slot count to 16 in case the application
1759          * forgot to set the S626_EOPL flag in the final slot.
1760          */
1761         for (devpriv->adc_items = 0; devpriv->adc_items < 16;
1762              devpriv->adc_items++) {
1763                 /*
1764                  * Convert application's poll list item to private board class
1765                  * format.  Each app poll list item is an uint8_t with form
1766                  * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
1767                  * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
1768                  */
1769                 local_ppl = (*ppl << 8) | (*ppl & 0x10 ? S626_GSEL_BIPOLAR5V :
1770                                            S626_GSEL_BIPOLAR10V);
1771 
1772                 /* Switch ADC analog gain. */
1773                 /* Write DEBI command and address to shadow RAM. */
1774                 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1775                 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1776                 /* Write DEBI immediate data to shadow RAM. */
1777                 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1778                 *rps++ = local_ppl;
1779                 /* Reset "shadow RAM uploaded" flag. */
1780                 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1781                 /* Invoke shadow RAM upload. */
1782                 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1783                 /* Wait for shadow upload to finish. */
1784                 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1785                 /* Select ADC analog input channel. */
1786                 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1787                 /* Write DEBI command and address to shadow RAM. */
1788                 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_ISEL;
1789                 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1790                 /* Write DEBI immediate data to shadow RAM. */
1791                 *rps++ = local_ppl;
1792                 /* Reset "shadow RAM uploaded" flag. */
1793                 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1794                 /* Invoke shadow RAM upload. */
1795                 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1796                 /* Wait for shadow upload to finish. */
1797                 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1798 
1799                 /*
1800                  * Delay at least 10 microseconds for analog input settling.
1801                  * Instead of padding with NOPs, we use S626_RPS_JUMP
1802                  * instructions here; this allows us to produce a longer delay
1803                  * than is possible with NOPs because each S626_RPS_JUMP
1804                  * flushes the RPS' instruction prefetch pipeline.
1805                  */
1806                 jmp_adrs =
1807                         (uint32_t)devpriv->rps_buf.physical_base +
1808                         (uint32_t)((unsigned long)rps -
1809                                    (unsigned long)devpriv->
1810                                                   rps_buf.logical_base);
1811                 for (i = 0; i < (10 * S626_RPSCLK_PER_US / 2); i++) {
1812                         jmp_adrs += 8;  /* Repeat to implement time delay: */
1813                         /* Jump to next RPS instruction. */
1814                         *rps++ = S626_RPS_JUMP;
1815                         *rps++ = jmp_adrs;
1816                 }
1817 
1818                 if (cmd != NULL && cmd->convert_src != TRIG_NOW) {
1819                         /* Wait for Start trigger. */
1820                         *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1821                         *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1822                 }
1823                 /* Start ADC by pulsing GPIO1. */
1824                 /* Begin ADC Start pulse. */
1825                 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1826                 *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1827                 *rps++ = S626_RPS_NOP;
1828                 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1829                 /* End ADC Start pulse. */
1830                 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1831                 *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1832                 /*
1833                  * Wait for ADC to complete (GPIO2 is asserted high when ADC not
1834                  * busy) and for data from previous conversion to shift into FB
1835                  * BUFFER 1 register.
1836                  */
1837                 /* Wait for ADC done. */
1838                 *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;
1839 
1840                 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
1841                 *rps++ = S626_RPS_STREG |
1842                          (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1843                 *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1844                          (devpriv->adc_items << 2);
1845 
1846                 /*
1847                  * If this slot's EndOfPollList flag is set, all channels have
1848                  * now been processed.
1849                  */
1850                 if (*ppl++ & S626_EOPL) {
1851                         devpriv->adc_items++; /* Adjust poll list item count. */
1852                         break;  /* Exit poll list processing loop. */
1853                 }
1854         }
1855 
1856         /*
1857          * VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US.  Allow the
1858          * ADC to stabilize for 2 microseconds before starting the final
1859          * (dummy) conversion.  This delay is necessary to allow sufficient
1860          * time between last conversion finished and the start of the dummy
1861          * conversion.  Without this delay, the last conversion's data value
1862          * is sometimes set to the previous conversion's data value.
1863          */
1864         for (n = 0; n < (2 * S626_RPSCLK_PER_US); n++)
1865                 *rps++ = S626_RPS_NOP;
1866 
1867         /*
1868          * Start a dummy conversion to cause the data from the last
1869          * conversion of interest to be shifted in.
1870          */
1871         /* Begin ADC Start pulse. */
1872         *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1873         *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1874         *rps++ = S626_RPS_NOP;
1875         /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1876         *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); /* End ADC Start pulse. */
1877         *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1878 
1879         /*
1880          * Wait for the data from the last conversion of interest to arrive
1881          * in FB BUFFER 1 register.
1882          */
1883         *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;       /* Wait for ADC done. */
1884 
1885         /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1886         *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1887         *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1888                  (devpriv->adc_items << 2);
1889 
1890         /* Indicate ADC scan loop is finished. */
1891         /* Signal ReadADC() that scan is done. */
1892         /* *rps++= S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; */
1893 
1894         /* invoke interrupt */
1895         if (devpriv->ai_cmd_running == 1)
1896                 *rps++ = S626_RPS_IRQ;
1897 
1898         /* Restart RPS program at its beginning. */
1899         *rps++ = S626_RPS_JUMP; /* Branch to start of RPS program. */
1900         *rps++ = (uint32_t)devpriv->rps_buf.physical_base;
1901 
1902         /* End of RPS program build */
1903 }
1904 
1905 #ifdef unused_code
1906 static int s626_ai_rinsn(struct comedi_device *dev,
1907                          struct comedi_subdevice *s,
1908                          struct comedi_insn *insn,
1909                          unsigned int *data)
1910 {
1911         struct s626_private *devpriv = dev->private;
1912         uint8_t i;
1913         int32_t *readaddr;
1914 
1915         /* Trigger ADC scan loop start */
1916         s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1917 
1918         /* Wait until ADC scan loop is finished (RPS Signal 0 reset) */
1919         while (s626_mc_test(dev, S626_MC2_ADC_RPS, S626_P_MC2))
1920                 ;
1921 
1922         /*
1923          * Init ptr to DMA buffer that holds new ADC data.  We skip the
1924          * first uint16_t in the buffer because it contains junk data from
1925          * the final ADC of the previous poll list scan.
1926          */
1927         readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1928 
1929         /*
1930          * Convert ADC data to 16-bit integer values and
1931          * copy to application buffer.
1932          */
1933         for (i = 0; i < devpriv->adc_items; i++) {
1934                 *data = s626_ai_reg_to_uint(*readaddr++);
1935                 data++;
1936         }
1937 
1938         return i;
1939 }
1940 #endif
1941 
1942 static int s626_ai_eoc(struct comedi_device *dev,
1943                        struct comedi_subdevice *s,
1944                        struct comedi_insn *insn,
1945                        unsigned long context)
1946 {
1947         struct s626_private *devpriv = dev->private;
1948         unsigned int status;
1949 
1950         status = readl(devpriv->mmio + S626_P_PSR);
1951         if (status & S626_PSR_GPIO2)
1952                 return 0;
1953         return -EBUSY;
1954 }
1955 
1956 static int s626_ai_insn_read(struct comedi_device *dev,
1957                              struct comedi_subdevice *s,
1958                              struct comedi_insn *insn, unsigned int *data)
1959 {
1960         struct s626_private *devpriv = dev->private;
1961         uint16_t chan = CR_CHAN(insn->chanspec);
1962         uint16_t range = CR_RANGE(insn->chanspec);
1963         uint16_t adc_spec = 0;
1964         uint32_t gpio_image;
1965         uint32_t tmp;
1966         int ret;
1967         int n;
1968 
1969         /*
1970          * Convert application's ADC specification into form
1971          *  appropriate for register programming.
1972          */
1973         if (range == 0)
1974                 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR5V);
1975         else
1976                 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR10V);
1977 
1978         /* Switch ADC analog gain. */
1979         s626_debi_write(dev, S626_LP_GSEL, adc_spec);   /* Set gain. */
1980 
1981         /* Select ADC analog input channel. */
1982         s626_debi_write(dev, S626_LP_ISEL, adc_spec);   /* Select channel. */
1983 
1984         for (n = 0; n < insn->n; n++) {
1985                 /* Delay 10 microseconds for analog input settling. */
1986                 udelay(10);
1987 
1988                 /* Start ADC by pulsing GPIO1 low */
1989                 gpio_image = readl(devpriv->mmio + S626_P_GPIO);
1990                 /* Assert ADC Start command */
1991                 writel(gpio_image & ~S626_GPIO1_HI,
1992                        devpriv->mmio + S626_P_GPIO);
1993                 /* and stretch it out */
1994                 writel(gpio_image & ~S626_GPIO1_HI,
1995                        devpriv->mmio + S626_P_GPIO);
1996                 writel(gpio_image & ~S626_GPIO1_HI,
1997                        devpriv->mmio + S626_P_GPIO);
1998                 /* Negate ADC Start command */
1999                 writel(gpio_image | S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
2000 
2001                 /*
2002                  * Wait for ADC to complete (GPIO2 is asserted high when
2003                  * ADC not busy) and for data from previous conversion to
2004                  * shift into FB BUFFER 1 register.
2005                  */
2006 
2007                 /* Wait for ADC done */
2008                 ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
2009                 if (ret)
2010                         return ret;
2011 
2012                 /* Fetch ADC data */
2013                 if (n != 0) {
2014                         tmp = readl(devpriv->mmio + S626_P_FB_BUFFER1);
2015                         data[n - 1] = s626_ai_reg_to_uint(tmp);
2016                 }
2017 
2018                 /*
2019                  * Allow the ADC to stabilize for 4 microseconds before
2020                  * starting the next (final) conversion.  This delay is
2021                  * necessary to allow sufficient time between last
2022                  * conversion finished and the start of the next
2023                  * conversion.  Without this delay, the last conversion's
2024                  * data value is sometimes set to the previous
2025                  * conversion's data value.
2026                  */
2027                 udelay(4);
2028         }
2029 
2030         /*
2031          * Start a dummy conversion to cause the data from the
2032          * previous conversion to be shifted in.
2033          */
2034         gpio_image = readl(devpriv->mmio + S626_P_GPIO);
2035         /* Assert ADC Start command */
2036         writel(gpio_image & ~S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
2037         /* and stretch it out */
2038         writel(gpio_image & ~S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
2039         writel(gpio_image & ~S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
2040         /* Negate ADC Start command */
2041         writel(gpio_image | S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
2042 
2043         /* Wait for the data to arrive in FB BUFFER 1 register. */
2044 
2045         /* Wait for ADC done */
2046         ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
2047         if (ret)
2048                 return ret;
2049 
2050         /* Fetch ADC data from audio interface's input shift register. */
2051 
2052         /* Fetch ADC data */
2053         if (n != 0) {
2054                 tmp = readl(devpriv->mmio + S626_P_FB_BUFFER1);
2055                 data[n - 1] = s626_ai_reg_to_uint(tmp);
2056         }
2057 
2058         return n;
2059 }
2060 
2061 static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd)
2062 {
2063         int n;
2064 
2065         for (n = 0; n < cmd->chanlist_len; n++) {
2066                 if (CR_RANGE(cmd->chanlist[n]) == 0)
2067                         ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_5V;
2068                 else
2069                         ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_10V;
2070         }
2071         if (n != 0)
2072                 ppl[n - 1] |= S626_EOPL;
2073 
2074         return n;
2075 }
2076 
2077 static int s626_ai_inttrig(struct comedi_device *dev,
2078                            struct comedi_subdevice *s,
2079                            unsigned int trig_num)
2080 {
2081         struct comedi_cmd *cmd = &s->async->cmd;
2082 
2083         if (trig_num != cmd->start_arg)
2084                 return -EINVAL;
2085 
2086         /* Start executing the RPS program */
2087         s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
2088 
2089         s->async->inttrig = NULL;
2090 
2091         return 1;
2092 }
2093 
2094 /*
2095  * This function doesn't require a particular form, this is just what
2096  * happens to be used in some of the drivers.  It should convert ns
2097  * nanoseconds to a counter value suitable for programming the device.
2098  * Also, it should adjust ns so that it cooresponds to the actual time
2099  * that the device will use.
2100  */
2101 static int s626_ns_to_timer(unsigned int *nanosec, int round_mode)
2102 {
2103         int divider, base;
2104 
2105         base = 500;             /* 2MHz internal clock */
2106 
2107         switch (round_mode) {
2108         case TRIG_ROUND_NEAREST:
2109         default:
2110                 divider = (*nanosec + base / 2) / base;
2111                 break;
2112         case TRIG_ROUND_DOWN:
2113                 divider = (*nanosec) / base;
2114                 break;
2115         case TRIG_ROUND_UP:
2116                 divider = (*nanosec + base - 1) / base;
2117                 break;
2118         }
2119 
2120         *nanosec = base * divider;
2121         return divider - 1;
2122 }
2123 
2124 static void s626_timer_load(struct comedi_device *dev,
2125                             const struct s626_enc_info *k, int tick)
2126 {
2127         uint16_t setup =
2128                 /* Preload upon index. */
2129                 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2130                 /* Disable hardware index. */
2131                 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2132                 /* Operating mode is Timer. */
2133                 S626_SET_STD_ENCMODE(S626_ENCMODE_TIMER) |
2134                 /* Count direction is Down. */
2135                 S626_SET_STD_CLKPOL(S626_CNTDIR_DOWN) |
2136                 /* Clock multiplier is 1x. */
2137                 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2138                 /* Enabled by index */
2139                 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2140         uint16_t value_latchsrc = S626_LATCHSRC_A_INDXA;
2141         /* uint16_t enab = S626_CLKENAB_ALWAYS; */
2142 
2143         k->set_mode(dev, k, setup, false);
2144 
2145         /* Set the preload register */
2146         s626_preload(dev, k, tick);
2147 
2148         /*
2149          * Software index pulse forces the preload register to load
2150          * into the counter
2151          */
2152         k->set_load_trig(dev, k, 0);
2153         k->pulse_index(dev, k);
2154 
2155         /* set reload on counter overflow */
2156         k->set_load_trig(dev, k, 1);
2157 
2158         /* set interrupt on overflow */
2159         k->set_int_src(dev, k, S626_INTSRC_OVER);
2160 
2161         s626_set_latch_source(dev, k, value_latchsrc);
2162         /* k->set_enable(dev, k, (uint16_t)(enab != 0)); */
2163 }
2164 
2165 /* TO COMPLETE  */
2166 static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2167 {
2168         struct s626_private *devpriv = dev->private;
2169         uint8_t ppl[16];
2170         struct comedi_cmd *cmd = &s->async->cmd;
2171         const struct s626_enc_info *k;
2172         int tick;
2173 
2174         if (devpriv->ai_cmd_running) {
2175                 dev_err(dev->class_dev,
2176                         "s626_ai_cmd: Another ai_cmd is running\n");
2177                 return -EBUSY;
2178         }
2179         /* disable interrupt */
2180         writel(0, devpriv->mmio + S626_P_IER);
2181 
2182         /* clear interrupt request */
2183         writel(S626_IRQ_RPS1 | S626_IRQ_GPIO3, devpriv->mmio + S626_P_ISR);
2184 
2185         /* clear any pending interrupt */
2186         s626_dio_clear_irq(dev);
2187         /* s626_enc_clear_irq(dev); */
2188 
2189         /* reset ai_cmd_running flag */
2190         devpriv->ai_cmd_running = 0;
2191 
2192         /* test if cmd is valid */
2193         if (cmd == NULL)
2194                 return -EINVAL;
2195 
2196         s626_ai_load_polllist(ppl, cmd);
2197         devpriv->ai_cmd_running = 1;
2198         devpriv->ai_convert_count = 0;
2199 
2200         switch (cmd->scan_begin_src) {
2201         case TRIG_FOLLOW:
2202                 break;
2203         case TRIG_TIMER:
2204                 /*
2205                  * set a counter to generate adc trigger at scan_begin_arg
2206                  * interval
2207                  */
2208                 k = &s626_enc_chan_info[5];
2209                 tick = s626_ns_to_timer(&cmd->scan_begin_arg,
2210                                         cmd->flags & TRIG_ROUND_MASK);
2211 
2212                 /* load timer value and enable interrupt */
2213                 s626_timer_load(dev, k, tick);
2214                 k->set_enable(dev, k, S626_CLKENAB_ALWAYS);
2215                 break;
2216         case TRIG_EXT:
2217                 /* set the digital line and interrupt for scan trigger */
2218                 if (cmd->start_src != TRIG_EXT)
2219                         s626_dio_set_irq(dev, cmd->scan_begin_arg);
2220                 break;
2221         }
2222 
2223         switch (cmd->convert_src) {
2224         case TRIG_NOW:
2225                 break;
2226         case TRIG_TIMER:
2227                 /*
2228                  * set a counter to generate adc trigger at convert_arg
2229                  * interval
2230                  */
2231                 k = &s626_enc_chan_info[4];
2232                 tick = s626_ns_to_timer(&cmd->convert_arg,
2233                                         cmd->flags & TRIG_ROUND_MASK);
2234 
2235                 /* load timer value and enable interrupt */
2236                 s626_timer_load(dev, k, tick);
2237                 k->set_enable(dev, k, S626_CLKENAB_INDEX);
2238                 break;
2239         case TRIG_EXT:
2240                 /* set the digital line and interrupt for convert trigger */
2241                 if (cmd->scan_begin_src != TRIG_EXT &&
2242                     cmd->start_src == TRIG_EXT)
2243                         s626_dio_set_irq(dev, cmd->convert_arg);
2244                 break;
2245         }
2246 
2247         switch (cmd->stop_src) {
2248         case TRIG_COUNT:
2249                 /* data arrives as one packet */
2250                 devpriv->ai_sample_count = cmd->stop_arg;
2251                 devpriv->ai_continuous = 0;
2252                 break;
2253         case TRIG_NONE:
2254                 /* continuous acquisition */
2255                 devpriv->ai_continuous = 1;
2256                 devpriv->ai_sample_count = 1;
2257                 break;
2258         }
2259 
2260         s626_reset_adc(dev, ppl);
2261 
2262         switch (cmd->start_src) {
2263         case TRIG_NOW:
2264                 /* Trigger ADC scan loop start */
2265                 /* s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); */
2266 
2267                 /* Start executing the RPS program */
2268                 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
2269                 s->async->inttrig = NULL;
2270                 break;
2271         case TRIG_EXT:
2272                 /* configure DIO channel for acquisition trigger */
2273                 s626_dio_set_irq(dev, cmd->start_arg);
2274                 s->async->inttrig = NULL;
2275                 break;
2276         case TRIG_INT:
2277                 s->async->inttrig = s626_ai_inttrig;
2278                 break;
2279         }
2280 
2281         /* enable interrupt */
2282         writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, devpriv->mmio + S626_P_IER);
2283 
2284         return 0;
2285 }
2286 
2287 static int s626_ai_cmdtest(struct comedi_device *dev,
2288                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
2289 {
2290         int err = 0;
2291         unsigned int arg;
2292 
2293         /* Step 1 : check if triggers are trivially valid */
2294 
2295         err |= cfc_check_trigger_src(&cmd->start_src,
2296                                      TRIG_NOW | TRIG_INT | TRIG_EXT);
2297         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2298                                      TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW);
2299         err |= cfc_check_trigger_src(&cmd->convert_src,
2300                                      TRIG_TIMER | TRIG_EXT | TRIG_NOW);
2301         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2302         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2303 
2304         if (err)
2305                 return 1;
2306 
2307         /* Step 2a : make sure trigger sources are unique */
2308 
2309         err |= cfc_check_trigger_is_unique(cmd->start_src);
2310         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2311         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2312         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2313 
2314         /* Step 2b : and mutually compatible */
2315 
2316         if (err)
2317                 return 2;
2318 
2319         /* Step 3: check if arguments are trivially valid */
2320 
2321         switch (cmd->start_src) {
2322         case TRIG_NOW:
2323         case TRIG_INT:
2324                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2325                 break;
2326         case TRIG_EXT:
2327                 err |= cfc_check_trigger_arg_max(&cmd->start_arg, 39);
2328                 break;
2329         }
2330 
2331         if (cmd->scan_begin_src == TRIG_EXT)
2332                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 39);
2333         if (cmd->convert_src == TRIG_EXT)
2334                 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 39);
2335 
2336 #define S626_MAX_SPEED  200000  /* in nanoseconds */
2337 #define S626_MIN_SPEED  2000000000      /* in nanoseconds */
2338 
2339         if (cmd->scan_begin_src == TRIG_TIMER) {
2340                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2341                                                  S626_MAX_SPEED);
2342                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2343                                                  S626_MIN_SPEED);
2344         } else {
2345                 /* external trigger */
2346                 /* should be level/edge, hi/lo specification here */
2347                 /* should specify multiple external triggers */
2348                 /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
2349         }
2350         if (cmd->convert_src == TRIG_TIMER) {
2351                 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2352                                                  S626_MAX_SPEED);
2353                 err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2354                                                  S626_MIN_SPEED);
2355         } else {
2356                 /* external trigger */
2357                 /* see above */
2358                 /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
2359         }
2360 
2361         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2362 
2363         if (cmd->stop_src == TRIG_COUNT)
2364                 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
2365         else    /* TRIG_NONE */
2366                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2367 
2368         if (err)
2369                 return 3;
2370 
2371         /* step 4: fix up any arguments */
2372 
2373         if (cmd->scan_begin_src == TRIG_TIMER) {
2374                 arg = cmd->scan_begin_arg;
2375                 s626_ns_to_timer(&arg, cmd->flags & TRIG_ROUND_MASK);
2376                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
2377         }
2378 
2379         if (cmd->convert_src == TRIG_TIMER) {
2380                 arg = cmd->convert_arg;
2381                 s626_ns_to_timer(&arg, cmd->flags & TRIG_ROUND_MASK);
2382                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, arg);
2383 
2384                 if (cmd->scan_begin_src == TRIG_TIMER) {
2385                         arg = cmd->convert_arg * cmd->scan_end_arg;
2386                         err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2387                                                          arg);
2388                 }
2389         }
2390 
2391         if (err)
2392                 return 4;
2393 
2394         return 0;
2395 }
2396 
2397 static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
2398 {
2399         struct s626_private *devpriv = dev->private;
2400 
2401         /* Stop RPS program in case it is currently running */
2402         s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
2403 
2404         /* disable master interrupt */
2405         writel(0, devpriv->mmio + S626_P_IER);
2406 
2407         devpriv->ai_cmd_running = 0;
2408 
2409         return 0;
2410 }
2411 
2412 static int s626_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
2413                          struct comedi_insn *insn, unsigned int *data)
2414 {
2415         struct s626_private *devpriv = dev->private;
2416         int i;
2417         int ret;
2418         uint16_t chan = CR_CHAN(insn->chanspec);
2419         int16_t dacdata;
2420 
2421         for (i = 0; i < insn->n; i++) {
2422                 dacdata = (int16_t) data[i];
2423                 devpriv->ao_readback[CR_CHAN(insn->chanspec)] = data[i];
2424                 dacdata -= (0x1fff);
2425 
2426                 ret = s626_set_dac(dev, chan, dacdata);
2427                 if (ret)
2428                         return ret;
2429         }
2430 
2431         return i;
2432 }
2433 
2434 static int s626_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
2435                          struct comedi_insn *insn, unsigned int *data)
2436 {
2437         struct s626_private *devpriv = dev->private;
2438         int i;
2439 
2440         for (i = 0; i < insn->n; i++)
2441                 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
2442 
2443         return i;
2444 }
2445 
2446 /* *************** DIGITAL I/O FUNCTIONS *************** */
2447 
2448 /*
2449  * All DIO functions address a group of DIO channels by means of
2450  * "group" argument.  group may be 0, 1 or 2, which correspond to DIO
2451  * ports A, B and C, respectively.
2452  */
2453 
2454 static void s626_dio_init(struct comedi_device *dev)
2455 {
2456         uint16_t group;
2457 
2458         /* Prepare to treat writes to WRCapSel as capture disables. */
2459         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
2460 
2461         /* For each group of sixteen channels ... */
2462         for (group = 0; group < S626_DIO_BANKS; group++) {
2463                 /* Disable all interrupts */
2464                 s626_debi_write(dev, S626_LP_WRINTSEL(group), 0);
2465                 /* Disable all event captures */
2466                 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
2467                 /* Init all DIOs to default edge polarity */
2468                 s626_debi_write(dev, S626_LP_WREDGSEL(group), 0);
2469                 /* Program all outputs to inactive state */
2470                 s626_debi_write(dev, S626_LP_WRDOUT(group), 0);
2471         }
2472 }
2473 
2474 static int s626_dio_insn_bits(struct comedi_device *dev,
2475                               struct comedi_subdevice *s,
2476                               struct comedi_insn *insn,
2477                               unsigned int *data)
2478 {
2479         unsigned long group = (unsigned long)s->private;
2480 
2481         if (comedi_dio_update_state(s, data))
2482                 s626_debi_write(dev, S626_LP_WRDOUT(group), s->state);
2483 
2484         data[1] = s626_debi_read(dev, S626_LP_RDDIN(group));
2485 
2486         return insn->n;
2487 }
2488 
2489 static int s626_dio_insn_config(struct comedi_device *dev,
2490                                 struct comedi_subdevice *s,
2491                                 struct comedi_insn *insn,
2492                                 unsigned int *data)
2493 {
2494         unsigned long group = (unsigned long)s->private;
2495         int ret;
2496 
2497         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
2498         if (ret)
2499                 return ret;
2500 
2501         s626_debi_write(dev, S626_LP_WRDOUT(group), s->io_bits);
2502 
2503         return insn->n;
2504 }
2505 
2506 /*
2507  * Now this function initializes the value of the counter (data[0])
2508  * and set the subdevice. To complete with trigger and interrupt
2509  * configuration.
2510  *
2511  * FIXME: data[0] is supposed to be an INSN_CONFIG_xxx constant indicating
2512  * what is being configured, but this function appears to be using data[0]
2513  * as a variable.
2514  */
2515 static int s626_enc_insn_config(struct comedi_device *dev,
2516                                 struct comedi_subdevice *s,
2517                                 struct comedi_insn *insn, unsigned int *data)
2518 {
2519         uint16_t setup =
2520                 /* Preload upon index. */
2521                 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2522                 /* Disable hardware index. */
2523                 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2524                 /* Operating mode is Counter. */
2525                 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2526                 /* Active high clock. */
2527                 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2528                 /* Clock multiplier is 1x. */
2529                 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2530                 /* Enabled by index */
2531                 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2532         /* uint16_t disable_int_src = true; */
2533         /* uint32_t Preloadvalue;              //Counter initial value */
2534         uint16_t value_latchsrc = S626_LATCHSRC_AB_READ;
2535         uint16_t enab = S626_CLKENAB_ALWAYS;
2536         const struct s626_enc_info *k =
2537                 &s626_enc_chan_info[CR_CHAN(insn->chanspec)];
2538 
2539         /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
2540 
2541         k->set_mode(dev, k, setup, true);
2542         s626_preload(dev, k, data[0]);
2543         k->pulse_index(dev, k);
2544         s626_set_latch_source(dev, k, value_latchsrc);
2545         k->set_enable(dev, k, (enab != 0));
2546 
2547         return insn->n;
2548 }
2549 
2550 static int s626_enc_insn_read(struct comedi_device *dev,
2551                               struct comedi_subdevice *s,
2552                               struct comedi_insn *insn, unsigned int *data)
2553 {
2554         int n;
2555         const struct s626_enc_info *k =
2556                 &s626_enc_chan_info[CR_CHAN(insn->chanspec)];
2557 
2558         for (n = 0; n < insn->n; n++)
2559                 data[n] = s626_read_latch(dev, k);
2560 
2561         return n;
2562 }
2563 
2564 static int s626_enc_insn_write(struct comedi_device *dev,
2565                                struct comedi_subdevice *s,
2566                                struct comedi_insn *insn, unsigned int *data)
2567 {
2568         const struct s626_enc_info *k =
2569                 &s626_enc_chan_info[CR_CHAN(insn->chanspec)];
2570 
2571         /* Set the preload register */
2572         s626_preload(dev, k, data[0]);
2573 
2574         /*
2575          * Software index pulse forces the preload register to load
2576          * into the counter
2577          */
2578         k->set_load_trig(dev, k, 0);
2579         k->pulse_index(dev, k);
2580         k->set_load_trig(dev, k, 2);
2581 
2582         return 1;
2583 }
2584 
2585 static void s626_write_misc2(struct comedi_device *dev, uint16_t new_image)
2586 {
2587         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WENABLE);
2588         s626_debi_write(dev, S626_LP_WRMISC2, new_image);
2589         s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WDISABLE);
2590 }
2591 
2592 static void s626_close_dma_b(struct comedi_device *dev,
2593                              struct s626_buffer_dma *pdma, size_t bsize)
2594 {
2595         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2596         void *vbptr;
2597         dma_addr_t vpptr;
2598 
2599         if (pdma == NULL)
2600                 return;
2601 
2602         /* find the matching allocation from the board struct */
2603         vbptr = pdma->logical_base;
2604         vpptr = pdma->physical_base;
2605         if (vbptr) {
2606                 pci_free_consistent(pcidev, bsize, vbptr, vpptr);
2607                 pdma->logical_base = NULL;
2608                 pdma->physical_base = 0;
2609         }
2610 }
2611 
2612 static void s626_counters_init(struct comedi_device *dev)
2613 {
2614         int chan;
2615         const struct s626_enc_info *k;
2616         uint16_t setup =
2617                 /* Preload upon index. */
2618                 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2619                 /* Disable hardware index. */
2620                 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2621                 /* Operating mode is counter. */
2622                 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2623                 /* Active high clock. */
2624                 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2625                 /* Clock multiplier is 1x. */
2626                 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2627                 /* Enabled by index */
2628                 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2629 
2630         /*
2631          * Disable all counter interrupts and clear any captured counter events.
2632          */
2633         for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
2634                 k = &s626_enc_chan_info[chan];
2635                 k->set_mode(dev, k, setup, true);
2636                 k->set_int_src(dev, k, 0);
2637                 k->reset_cap_flags(dev, k);
2638                 k->set_enable(dev, k, S626_CLKENAB_ALWAYS);
2639         }
2640 }
2641 
2642 static int s626_allocate_dma_buffers(struct comedi_device *dev)
2643 {
2644         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2645         struct s626_private *devpriv = dev->private;
2646         void *addr;
2647         dma_addr_t appdma;
2648 
2649         addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2650         if (!addr)
2651                 return -ENOMEM;
2652         devpriv->ana_buf.logical_base = addr;
2653         devpriv->ana_buf.physical_base = appdma;
2654 
2655         addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2656         if (!addr)
2657                 return -ENOMEM;
2658         devpriv->rps_buf.logical_base = addr;
2659         devpriv->rps_buf.physical_base = appdma;
2660 
2661         return 0;
2662 }
2663 
2664 static int s626_initialize(struct comedi_device *dev)
2665 {
2666         struct s626_private *devpriv = dev->private;
2667         dma_addr_t phys_buf;
2668         uint16_t chan;
2669         int i;
2670         int ret;
2671 
2672         /* Enable DEBI and audio pins, enable I2C interface */
2673         s626_mc_enable(dev, S626_MC1_DEBI | S626_MC1_AUDIO | S626_MC1_I2C,
2674                        S626_P_MC1);
2675 
2676         /*
2677          * Configure DEBI operating mode
2678          *
2679          *  Local bus is 16 bits wide
2680          *  Declare DEBI transfer timeout interval
2681          *  Set up byte lane steering
2682          *  Intel-compatible local bus (DEBI never times out)
2683          */
2684         writel(S626_DEBI_CFG_SLAVE16 |
2685                (S626_DEBI_TOUT << S626_DEBI_CFG_TOUT_BIT) | S626_DEBI_SWAP |
2686                S626_DEBI_CFG_INTEL, devpriv->mmio + S626_P_DEBICFG);
2687 
2688         /* Disable MMU paging */
2689         writel(S626_DEBI_PAGE_DISABLE, devpriv->mmio + S626_P_DEBIPAGE);
2690 
2691         /* Init GPIO so that ADC Start* is negated */
2692         writel(S626_GPIO_BASE | S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
2693 
2694         /* I2C device address for onboard eeprom (revb) */
2695         devpriv->i2c_adrs = 0xA0;
2696 
2697         /*
2698          * Issue an I2C ABORT command to halt any I2C
2699          * operation in progress and reset BUSY flag.
2700          */
2701         writel(S626_I2C_CLKSEL | S626_I2C_ABORT,
2702                devpriv->mmio + S626_P_I2CSTAT);
2703         s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2704         ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
2705         if (ret)
2706                 return ret;
2707 
2708         /*
2709          * Per SAA7146 data sheet, write to STATUS
2710          * reg twice to reset all  I2C error flags.
2711          */
2712         for (i = 0; i < 2; i++) {
2713                 writel(S626_I2C_CLKSEL, devpriv->mmio + S626_P_I2CSTAT);
2714                 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2715                 ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
2716                 if (ret)
2717                         return ret;
2718         }
2719 
2720         /*
2721          * Init audio interface functional attributes: set DAC/ADC
2722          * serial clock rates, invert DAC serial clock so that
2723          * DAC data setup times are satisfied, enable DAC serial
2724          * clock out.
2725          */
2726         writel(S626_ACON2_INIT, devpriv->mmio + S626_P_ACON2);
2727 
2728         /*
2729          * Set up TSL1 slot list, which is used to control the
2730          * accumulation of ADC data: S626_RSD1 = shift data in on SD1.
2731          * S626_SIB_A1  = store data uint8_t at next available location
2732          * in FB BUFFER1 register.
2733          */
2734         writel(S626_RSD1 | S626_SIB_A1, devpriv->mmio + S626_P_TSL1);
2735         writel(S626_RSD1 | S626_SIB_A1 | S626_EOS,
2736                devpriv->mmio + S626_P_TSL1 + 4);
2737 
2738         /* Enable TSL1 slot list so that it executes all the time */
2739         writel(S626_ACON1_ADCSTART, devpriv->mmio + S626_P_ACON1);
2740 
2741         /*
2742          * Initialize RPS registers used for ADC
2743          */
2744 
2745         /* Physical start of RPS program */
2746         writel((uint32_t)devpriv->rps_buf.physical_base,
2747                devpriv->mmio + S626_P_RPSADDR1);
2748         /* RPS program performs no explicit mem writes */
2749         writel(0, devpriv->mmio + S626_P_RPSPAGE1);
2750         /* Disable RPS timeouts */
2751         writel(0, devpriv->mmio + S626_P_RPS1_TOUT);
2752 
2753 #if 0
2754         /*
2755          * SAA7146 BUG WORKAROUND
2756          *
2757          * Initialize SAA7146 ADC interface to a known state by
2758          * invoking ADCs until FB BUFFER 1 register shows that it
2759          * is correctly receiving ADC data. This is necessary
2760          * because the SAA7146 ADC interface does not start up in
2761          * a defined state after a PCI reset.
2762          */
2763         {
2764                 struct comedi_subdevice *s = dev->read_subdev;
2765                 uint8_t poll_list;
2766                 uint16_t adc_data;
2767                 uint16_t start_val;
2768                 uint16_t index;
2769                 unsigned int data[16];
2770 
2771                 /* Create a simple polling list for analog input channel 0 */
2772                 poll_list = S626_EOPL;
2773                 s626_reset_adc(dev, &poll_list);
2774 
2775                 /* Get initial ADC value */
2776                 s626_ai_rinsn(dev, s, NULL, data);
2777                 start_val = data[0];
2778 
2779                 /*
2780                  * VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED
2781                  * EXECUTION.
2782                  *
2783                  * Invoke ADCs until the new ADC value differs from the initial
2784                  * value or a timeout occurs.  The timeout protects against the
2785                  * possibility that the driver is restarting and the ADC data is
2786                  * a fixed value resulting from the applied ADC analog input
2787                  * being unusually quiet or at the rail.
2788                  */
2789                 for (index = 0; index < 500; index++) {
2790                         s626_ai_rinsn(dev, s, NULL, data);
2791                         adc_data = data[0];
2792                         if (adc_data != start_val)
2793                                 break;
2794                 }
2795         }
2796 #endif  /* SAA7146 BUG WORKAROUND */
2797 
2798         /*
2799          * Initialize the DAC interface
2800          */
2801 
2802         /*
2803          * Init Audio2's output DMAC attributes:
2804          *   burst length = 1 DWORD
2805          *   threshold = 1 DWORD.
2806          */
2807         writel(0, devpriv->mmio + S626_P_PCI_BT_A);
2808 
2809         /*
2810          * Init Audio2's output DMA physical addresses.  The protection
2811          * address is set to 1 DWORD past the base address so that a
2812          * single DWORD will be transferred each time a DMA transfer is
2813          * enabled.
2814          */
2815         phys_buf = devpriv->ana_buf.physical_base +
2816                    (S626_DAC_WDMABUF_OS * sizeof(uint32_t));
2817         writel((uint32_t)phys_buf, devpriv->mmio + S626_P_BASEA2_OUT);
2818         writel((uint32_t)(phys_buf + sizeof(uint32_t)),
2819                devpriv->mmio + S626_P_PROTA2_OUT);
2820 
2821         /*
2822          * Cache Audio2's output DMA buffer logical address.  This is
2823          * where DAC data is buffered for A2 output DMA transfers.
2824          */
2825         devpriv->dac_wbuf = (uint32_t *)devpriv->ana_buf.logical_base +
2826                             S626_DAC_WDMABUF_OS;
2827 
2828         /*
2829          * Audio2's output channels does not use paging.  The
2830          * protection violation handling bit is set so that the
2831          * DMAC will automatically halt and its PCI address pointer
2832          * will be reset when the protection address is reached.
2833          */
2834         writel(8, devpriv->mmio + S626_P_PAGEA2_OUT);
2835 
2836         /*
2837          * Initialize time slot list 2 (TSL2), which is used to control
2838          * the clock generation for and serialization of data to be sent
2839          * to the DAC devices.  Slot 0 is a NOP that is used to trap TSL
2840          * execution; this permits other slots to be safely modified
2841          * without first turning off the TSL sequencer (which is
2842          * apparently impossible to do).  Also, SD3 (which is driven by a
2843          * pull-up resistor) is shifted in and stored to the MSB of
2844          * FB_BUFFER2 to be used as evidence that the slot sequence has
2845          * not yet finished executing.
2846          */
2847 
2848         /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */
2849         writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2 | S626_EOS,
2850                devpriv->mmio + S626_VECTPORT(0));
2851 
2852         /*
2853          * Initialize slot 1, which is constant.  Slot 1 causes a
2854          * DWORD to be transferred from audio channel 2's output FIFO
2855          * to the FIFO's output buffer so that it can be serialized
2856          * and sent to the DAC during subsequent slots.  All remaining
2857          * slots are dynamically populated as required by the target
2858          * DAC device.
2859          */
2860 
2861         /* Slot 1: Fetch DWORD from Audio2's output FIFO */
2862         writel(S626_LF_A2, devpriv->mmio + S626_VECTPORT(1));
2863 
2864         /* Start DAC's audio interface (TSL2) running */
2865         writel(S626_ACON1_DACSTART, devpriv->mmio + S626_P_ACON1);
2866 
2867         /*
2868          * Init Trim DACs to calibrated values.  Do it twice because the
2869          * SAA7146 audio channel does not always reset properly and
2870          * sometimes causes the first few TrimDAC writes to malfunction.
2871          */
2872         s626_load_trim_dacs(dev);
2873         ret = s626_load_trim_dacs(dev);
2874         if (ret)
2875                 return ret;
2876 
2877         /*
2878          * Manually init all gate array hardware in case this is a soft
2879          * reset (we have no way of determining whether this is a warm
2880          * or cold start).  This is necessary because the gate array will
2881          * reset only in response to a PCI hard reset; there is no soft
2882          * reset function.
2883          */
2884 
2885         /*
2886          * Init all DAC outputs to 0V and init all DAC setpoint and
2887          * polarity images.
2888          */
2889         for (chan = 0; chan < S626_DAC_CHANNELS; chan++) {
2890                 ret = s626_set_dac(dev, chan, 0);
2891                 if (ret)
2892                         return ret;
2893         }
2894 
2895         /* Init counters */
2896         s626_counters_init(dev);
2897 
2898         /*
2899          * Without modifying the state of the Battery Backup enab, disable
2900          * the watchdog timer, set DIO channels 0-5 to operate in the
2901          * standard DIO (vs. counter overflow) mode, disable the battery
2902          * charger, and reset the watchdog interval selector to zero.
2903          */
2904         s626_write_misc2(dev, (s626_debi_read(dev, S626_LP_RDMISC2) &
2905                                S626_MISC2_BATT_ENABLE));
2906 
2907         /* Initialize the digital I/O subsystem */
2908         s626_dio_init(dev);
2909 
2910         return 0;
2911 }
2912 
2913 static int s626_auto_attach(struct comedi_device *dev,
2914                                       unsigned long context_unused)
2915 {
2916         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2917         struct s626_private *devpriv;
2918         struct comedi_subdevice *s;
2919         int ret;
2920 
2921         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
2922         if (!devpriv)
2923                 return -ENOMEM;
2924 
2925         ret = comedi_pci_enable(dev);
2926         if (ret)
2927                 return ret;
2928 
2929         devpriv->mmio = pci_ioremap_bar(pcidev, 0);
2930         if (!devpriv->mmio)
2931                 return -ENOMEM;
2932 
2933         /* disable master interrupt */
2934         writel(0, devpriv->mmio + S626_P_IER);
2935 
2936         /* soft reset */
2937         writel(S626_MC1_SOFT_RESET, devpriv->mmio + S626_P_MC1);
2938 
2939         /* DMA FIXME DMA// */
2940 
2941         ret = s626_allocate_dma_buffers(dev);
2942         if (ret)
2943                 return ret;
2944 
2945         if (pcidev->irq) {
2946                 ret = request_irq(pcidev->irq, s626_irq_handler, IRQF_SHARED,
2947                                   dev->board_name, dev);
2948 
2949                 if (ret == 0)
2950                         dev->irq = pcidev->irq;
2951         }
2952 
2953         ret = comedi_alloc_subdevices(dev, 6);
2954         if (ret)
2955                 return ret;
2956 
2957         s = &dev->subdevices[0];
2958         /* analog input subdevice */
2959         s->type         = COMEDI_SUBD_AI;
2960         s->subdev_flags = SDF_READABLE | SDF_DIFF;
2961         s->n_chan       = S626_ADC_CHANNELS;
2962         s->maxdata      = 0x3fff;
2963         s->range_table  = &s626_range_table;
2964         s->len_chanlist = S626_ADC_CHANNELS;
2965         s->insn_read    = s626_ai_insn_read;
2966         if (dev->irq) {
2967                 dev->read_subdev = s;
2968                 s->subdev_flags |= SDF_CMD_READ;
2969                 s->do_cmd       = s626_ai_cmd;
2970                 s->do_cmdtest   = s626_ai_cmdtest;
2971                 s->cancel       = s626_ai_cancel;
2972         }
2973 
2974         s = &dev->subdevices[1];
2975         /* analog output subdevice */
2976         s->type         = COMEDI_SUBD_AO;
2977         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2978         s->n_chan       = S626_DAC_CHANNELS;
2979         s->maxdata      = 0x3fff;
2980         s->range_table  = &range_bipolar10;
2981         s->insn_write   = s626_ao_winsn;
2982         s->insn_read    = s626_ao_rinsn;
2983 
2984         s = &dev->subdevices[2];
2985         /* digital I/O subdevice */
2986         s->type         = COMEDI_SUBD_DIO;
2987         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2988         s->n_chan       = 16;
2989         s->maxdata      = 1;
2990         s->io_bits      = 0xffff;
2991         s->private      = (void *)0;    /* DIO group 0 */
2992         s->range_table  = &range_digital;
2993         s->insn_config  = s626_dio_insn_config;
2994         s->insn_bits    = s626_dio_insn_bits;
2995 
2996         s = &dev->subdevices[3];
2997         /* digital I/O subdevice */
2998         s->type         = COMEDI_SUBD_DIO;
2999         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3000         s->n_chan       = 16;
3001         s->maxdata      = 1;
3002         s->io_bits      = 0xffff;
3003         s->private      = (void *)1;    /* DIO group 1 */
3004         s->range_table  = &range_digital;
3005         s->insn_config  = s626_dio_insn_config;
3006         s->insn_bits    = s626_dio_insn_bits;
3007 
3008         s = &dev->subdevices[4];
3009         /* digital I/O subdevice */
3010         s->type         = COMEDI_SUBD_DIO;
3011         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3012         s->n_chan       = 16;
3013         s->maxdata      = 1;
3014         s->io_bits      = 0xffff;
3015         s->private      = (void *)2;    /* DIO group 2 */
3016         s->range_table  = &range_digital;
3017         s->insn_config  = s626_dio_insn_config;
3018         s->insn_bits    = s626_dio_insn_bits;
3019 
3020         s = &dev->subdevices[5];
3021         /* encoder (counter) subdevice */
3022         s->type         = COMEDI_SUBD_COUNTER;
3023         s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
3024         s->n_chan       = S626_ENCODER_CHANNELS;
3025         s->maxdata      = 0xffffff;
3026         s->range_table  = &range_unknown;
3027         s->insn_config  = s626_enc_insn_config;
3028         s->insn_read    = s626_enc_insn_read;
3029         s->insn_write   = s626_enc_insn_write;
3030 
3031         ret = s626_initialize(dev);
3032         if (ret)
3033                 return ret;
3034 
3035         return 0;
3036 }
3037 
3038 static void s626_detach(struct comedi_device *dev)
3039 {
3040         struct s626_private *devpriv = dev->private;
3041 
3042         if (devpriv) {
3043                 /* stop ai_command */
3044                 devpriv->ai_cmd_running = 0;
3045 
3046                 if (devpriv->mmio) {
3047                         /* interrupt mask */
3048                         /* Disable master interrupt */
3049                         writel(0, devpriv->mmio + S626_P_IER);
3050                         /* Clear board's IRQ status flag */
3051                         writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1,
3052                                devpriv->mmio + S626_P_ISR);
3053 
3054                         /* Disable the watchdog timer and battery charger. */
3055                         s626_write_misc2(dev, 0);
3056 
3057                         /* Close all interfaces on 7146 device */
3058                         writel(S626_MC1_SHUTDOWN, devpriv->mmio + S626_P_MC1);
3059                         writel(S626_ACON1_BASE, devpriv->mmio + S626_P_ACON1);
3060 
3061                         s626_close_dma_b(dev, &devpriv->rps_buf,
3062                                          S626_DMABUF_SIZE);
3063                         s626_close_dma_b(dev, &devpriv->ana_buf,
3064                                          S626_DMABUF_SIZE);
3065                 }
3066 
3067                 if (dev->irq)
3068                         free_irq(dev->irq, dev);
3069                 if (devpriv->mmio)
3070                         iounmap(devpriv->mmio);
3071         }
3072         comedi_pci_disable(dev);
3073 }
3074 
3075 static struct comedi_driver s626_driver = {
3076         .driver_name    = "s626",
3077         .module         = THIS_MODULE,
3078         .auto_attach    = s626_auto_attach,
3079         .detach         = s626_detach,
3080 };
3081 
3082 static int s626_pci_probe(struct pci_dev *dev,
3083                           const struct pci_device_id *id)
3084 {
3085         return comedi_pci_auto_config(dev, &s626_driver, id->driver_data);
3086 }
3087 
3088 /*
3089  * For devices with vendor:device id == 0x1131:0x7146 you must specify
3090  * also subvendor:subdevice ids, because otherwise it will conflict with
3091  * Philips SAA7146 media/dvb based cards.
3092  */
3093 static const struct pci_device_id s626_pci_table[] = {
3094         { PCI_DEVICE_SUB(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA7146,
3095                          0x6000, 0x0272) },
3096         { 0 }
3097 };
3098 MODULE_DEVICE_TABLE(pci, s626_pci_table);
3099 
3100 static struct pci_driver s626_pci_driver = {
3101         .name           = "s626",
3102         .id_table       = s626_pci_table,
3103         .probe          = s626_pci_probe,
3104         .remove         = comedi_pci_auto_unconfig,
3105 };
3106 module_comedi_pci_driver(s626_driver, s626_pci_driver);
3107 
3108 MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
3109 MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
3110 MODULE_LICENSE("GPL");
3111 

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