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Linux/drivers/staging/comedi/drivers/rtd520.c

  1 /*
  2  * comedi/drivers/rtd520.c
  3  * Comedi driver for Real Time Devices (RTD) PCI4520/DM7520
  4  *
  5  * COMEDI - Linux Control and Measurement Device Interface
  6  * Copyright (C) 2001 David A. Schleef <ds@schleef.org>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 16  * GNU General Public License for more details.
 17  */
 18 
 19 /*
 20  * Driver: rtd520
 21  * Description: Real Time Devices PCI4520/DM7520
 22  * Devices: (Real Time Devices) DM7520HR-1 [DM7520]
 23  *          (Real Time Devices) DM7520HR-8 [DM7520]
 24  *          (Real Time Devices) PCI4520 [PCI4520]
 25  *          (Real Time Devices) PCI4520-8 [PCI4520]
 26  * Author: Dan Christian
 27  * Status: Works. Only tested on DM7520-8. Not SMP safe.
 28  *
 29  * Configuration options: not applicable, uses PCI auto config
 30  */
 31 
 32 /*
 33  * Created by Dan Christian, NASA Ames Research Center.
 34  *
 35  * The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
 36  * Both have:
 37  *   8/16 12 bit ADC with FIFO and channel gain table
 38  *   8 bits high speed digital out (for external MUX) (or 8 in or 8 out)
 39  *   8 bits high speed digital in with FIFO and interrupt on change (or 8 IO)
 40  *   2 12 bit DACs with FIFOs
 41  *   2 bits output
 42  *   2 bits input
 43  *   bus mastering DMA
 44  *   timers: ADC sample, pacer, burst, about, delay, DA1, DA2
 45  *   sample counter
 46  *   3 user timer/counters (8254)
 47  *   external interrupt
 48  *
 49  * The DM7520 has slightly fewer features (fewer gain steps).
 50  *
 51  * These boards can support external multiplexors and multi-board
 52  * synchronization, but this driver doesn't support that.
 53  *
 54  * Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm
 55  * Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf
 56  * Example source: http://www.rtdusa.com/examples/dm/dm7520.zip
 57  * Call them and ask for the register level manual.
 58  * PCI chip: http://www.plxtech.com/products/io/pci9080
 59  *
 60  * Notes:
 61  * This board is memory mapped. There is some IO stuff, but it isn't needed.
 62  *
 63  * I use a pretty loose naming style within the driver (rtd_blah).
 64  * All externally visible names should be rtd520_blah.
 65  * I use camelCase for structures (and inside them).
 66  * I may also use upper CamelCase for function names (old habit).
 67  *
 68  * This board is somewhat related to the RTD PCI4400 board.
 69  *
 70  * I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and
 71  * das1800, since they have the best documented code. Driver cb_pcidas64.c
 72  * uses the same DMA controller.
 73  *
 74  * As far as I can tell, the About interrupt doesn't work if Sample is
 75  * also enabled. It turns out that About really isn't needed, since
 76  * we always count down samples read.
 77  *
 78  * There was some timer/counter code, but it didn't follow the right API.
 79  */
 80 
 81 /*
 82  * driver status:
 83  *
 84  * Analog-In supports instruction and command mode.
 85  *
 86  * With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
 87  * (single channel, 64K read buffer). I get random system lockups when
 88  * using DMA with ALI-15xx based systems. I haven't been able to test
 89  * any other chipsets. The lockups happen soon after the start of an
 90  * acquistion, not in the middle of a long run.
 91  *
 92  * Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2
 93  * (with a 256K read buffer).
 94  *
 95  * Digital-IO and Analog-Out only support instruction mode.
 96  */
 97 
 98 #include <linux/module.h>
 99 #include <linux/pci.h>
100 #include <linux/delay.h>
101 #include <linux/interrupt.h>
102 
103 #include "../comedidev.h"
104 
105 #include "comedi_fc.h"
106 #include "plx9080.h"
107 
108 /*
109  * Local Address Space 0 Offsets
110  */
111 #define LAS0_USER_IO            0x0008  /* User I/O */
112 #define LAS0_ADC                0x0010  /* FIFO Status/Software A/D Start */
113 #define FS_DAC1_NOT_EMPTY       (1 << 0)        /* DAC1 FIFO not empty */
114 #define FS_DAC1_HEMPTY          (1 << 1)        /* DAC1 FIFO half empty */
115 #define FS_DAC1_NOT_FULL        (1 << 2)        /* DAC1 FIFO not full */
116 #define FS_DAC2_NOT_EMPTY       (1 << 4)        /* DAC2 FIFO not empty */
117 #define FS_DAC2_HEMPTY          (1 << 5)        /* DAC2 FIFO half empty */
118 #define FS_DAC2_NOT_FULL        (1 << 6)        /* DAC2 FIFO not full */
119 #define FS_ADC_NOT_EMPTY        (1 << 8)        /* ADC FIFO not empty */
120 #define FS_ADC_HEMPTY           (1 << 9)        /* ADC FIFO half empty */
121 #define FS_ADC_NOT_FULL         (1 << 10)       /* ADC FIFO not full */
122 #define FS_DIN_NOT_EMPTY        (1 << 12)       /* DIN FIFO not empty */
123 #define FS_DIN_HEMPTY           (1 << 13)       /* DIN FIFO half empty */
124 #define FS_DIN_NOT_FULL         (1 << 14)       /* DIN FIFO not full */
125 #define LAS0_DAC1               0x0014  /* Software D/A1 Update (w) */
126 #define LAS0_DAC2               0x0018  /* Software D/A2 Update (w) */
127 #define LAS0_DAC                0x0024  /* Software Simultaneous Update (w) */
128 #define LAS0_PACER              0x0028  /* Software Pacer Start/Stop */
129 #define LAS0_TIMER              0x002c  /* Timer Status/HDIN Software Trig. */
130 #define LAS0_IT                 0x0030  /* Interrupt Status/Enable */
131 #define IRQM_ADC_FIFO_WRITE     (1 << 0)        /* ADC FIFO Write */
132 #define IRQM_CGT_RESET          (1 << 1)        /* Reset CGT */
133 #define IRQM_CGT_PAUSE          (1 << 3)        /* Pause CGT */
134 #define IRQM_ADC_ABOUT_CNT      (1 << 4)        /* About Counter out */
135 #define IRQM_ADC_DELAY_CNT      (1 << 5)        /* Delay Counter out */
136 #define IRQM_ADC_SAMPLE_CNT     (1 << 6)        /* ADC Sample Counter */
137 #define IRQM_DAC1_UCNT          (1 << 7)        /* DAC1 Update Counter */
138 #define IRQM_DAC2_UCNT          (1 << 8)        /* DAC2 Update Counter */
139 #define IRQM_UTC1               (1 << 9)        /* User TC1 out */
140 #define IRQM_UTC1_INV           (1 << 10)       /* User TC1 out, inverted */
141 #define IRQM_UTC2               (1 << 11)       /* User TC2 out */
142 #define IRQM_DIGITAL_IT         (1 << 12)       /* Digital Interrupt */
143 #define IRQM_EXTERNAL_IT        (1 << 13)       /* External Interrupt */
144 #define IRQM_ETRIG_RISING       (1 << 14)       /* Ext Trigger rising-edge */
145 #define IRQM_ETRIG_FALLING      (1 << 15)       /* Ext Trigger falling-edge */
146 #define LAS0_CLEAR              0x0034  /* Clear/Set Interrupt Clear Mask */
147 #define LAS0_OVERRUN            0x0038  /* Pending interrupts/Clear Overrun */
148 #define LAS0_PCLK               0x0040  /* Pacer Clock (24bit) */
149 #define LAS0_BCLK               0x0044  /* Burst Clock (10bit) */
150 #define LAS0_ADC_SCNT           0x0048  /* A/D Sample counter (10bit) */
151 #define LAS0_DAC1_UCNT          0x004c  /* D/A1 Update counter (10 bit) */
152 #define LAS0_DAC2_UCNT          0x0050  /* D/A2 Update counter (10 bit) */
153 #define LAS0_DCNT               0x0054  /* Delay counter (16 bit) */
154 #define LAS0_ACNT               0x0058  /* About counter (16 bit) */
155 #define LAS0_DAC_CLK            0x005c  /* DAC clock (16bit) */
156 #define LAS0_UTC0               0x0060  /* 8254 TC Counter 0 */
157 #define LAS0_UTC1               0x0064  /* 8254 TC Counter 1 */
158 #define LAS0_UTC2               0x0068  /* 8254 TC Counter 2 */
159 #define LAS0_UTC_CTRL           0x006c  /* 8254 TC Control */
160 #define LAS0_DIO0               0x0070  /* Digital I/O Port 0 */
161 #define LAS0_DIO1               0x0074  /* Digital I/O Port 1 */
162 #define LAS0_DIO0_CTRL          0x0078  /* Digital I/O Control */
163 #define LAS0_DIO_STATUS         0x007c  /* Digital I/O Status */
164 #define LAS0_BOARD_RESET        0x0100  /* Board reset */
165 #define LAS0_DMA0_SRC           0x0104  /* DMA 0 Sources select */
166 #define LAS0_DMA1_SRC           0x0108  /* DMA 1 Sources select */
167 #define LAS0_ADC_CONVERSION     0x010c  /* A/D Conversion Signal select */
168 #define LAS0_BURST_START        0x0110  /* Burst Clock Start Trigger select */
169 #define LAS0_PACER_START        0x0114  /* Pacer Clock Start Trigger select */
170 #define LAS0_PACER_STOP         0x0118  /* Pacer Clock Stop Trigger select */
171 #define LAS0_ACNT_STOP_ENABLE   0x011c  /* About Counter Stop Enable */
172 #define LAS0_PACER_REPEAT       0x0120  /* Pacer Start Trigger Mode select */
173 #define LAS0_DIN_START          0x0124  /* HiSpd DI Sampling Signal select */
174 #define LAS0_DIN_FIFO_CLEAR     0x0128  /* Digital Input FIFO Clear */
175 #define LAS0_ADC_FIFO_CLEAR     0x012c  /* A/D FIFO Clear */
176 #define LAS0_CGT_WRITE          0x0130  /* Channel Gain Table Write */
177 #define LAS0_CGL_WRITE          0x0134  /* Channel Gain Latch Write */
178 #define LAS0_CG_DATA            0x0138  /* Digital Table Write */
179 #define LAS0_CGT_ENABLE         0x013c  /* Channel Gain Table Enable */
180 #define LAS0_CG_ENABLE          0x0140  /* Digital Table Enable */
181 #define LAS0_CGT_PAUSE          0x0144  /* Table Pause Enable */
182 #define LAS0_CGT_RESET          0x0148  /* Reset Channel Gain Table */
183 #define LAS0_CGT_CLEAR          0x014c  /* Clear Channel Gain Table */
184 #define LAS0_DAC1_CTRL          0x0150  /* D/A1 output type/range */
185 #define LAS0_DAC1_SRC           0x0154  /* D/A1 update source */
186 #define LAS0_DAC1_CYCLE         0x0158  /* D/A1 cycle mode */
187 #define LAS0_DAC1_RESET         0x015c  /* D/A1 FIFO reset */
188 #define LAS0_DAC1_FIFO_CLEAR    0x0160  /* D/A1 FIFO clear */
189 #define LAS0_DAC2_CTRL          0x0164  /* D/A2 output type/range */
190 #define LAS0_DAC2_SRC           0x0168  /* D/A2 update source */
191 #define LAS0_DAC2_CYCLE         0x016c  /* D/A2 cycle mode */
192 #define LAS0_DAC2_RESET         0x0170  /* D/A2 FIFO reset */
193 #define LAS0_DAC2_FIFO_CLEAR    0x0174  /* D/A2 FIFO clear */
194 #define LAS0_ADC_SCNT_SRC       0x0178  /* A/D Sample Counter Source select */
195 #define LAS0_PACER_SELECT       0x0180  /* Pacer Clock select */
196 #define LAS0_SBUS0_SRC          0x0184  /* SyncBus 0 Source select */
197 #define LAS0_SBUS0_ENABLE       0x0188  /* SyncBus 0 enable */
198 #define LAS0_SBUS1_SRC          0x018c  /* SyncBus 1 Source select */
199 #define LAS0_SBUS1_ENABLE       0x0190  /* SyncBus 1 enable */
200 #define LAS0_SBUS2_SRC          0x0198  /* SyncBus 2 Source select */
201 #define LAS0_SBUS2_ENABLE       0x019c  /* SyncBus 2 enable */
202 #define LAS0_ETRG_POLARITY      0x01a4  /* Ext. Trigger polarity select */
203 #define LAS0_EINT_POLARITY      0x01a8  /* Ext. Interrupt polarity select */
204 #define LAS0_UTC0_CLOCK         0x01ac  /* UTC0 Clock select */
205 #define LAS0_UTC0_GATE          0x01b0  /* UTC0 Gate select */
206 #define LAS0_UTC1_CLOCK         0x01b4  /* UTC1 Clock select */
207 #define LAS0_UTC1_GATE          0x01b8  /* UTC1 Gate select */
208 #define LAS0_UTC2_CLOCK         0x01bc  /* UTC2 Clock select */
209 #define LAS0_UTC2_GATE          0x01c0  /* UTC2 Gate select */
210 #define LAS0_UOUT0_SELECT       0x01c4  /* User Output 0 source select */
211 #define LAS0_UOUT1_SELECT       0x01c8  /* User Output 1 source select */
212 #define LAS0_DMA0_RESET         0x01cc  /* DMA0 Request state machine reset */
213 #define LAS0_DMA1_RESET         0x01d0  /* DMA1 Request state machine reset */
214 
215 /*
216  * Local Address Space 1 Offsets
217  */
218 #define LAS1_ADC_FIFO           0x0000  /* A/D FIFO (16bit) */
219 #define LAS1_HDIO_FIFO          0x0004  /* HiSpd DI FIFO (16bit) */
220 #define LAS1_DAC1_FIFO          0x0008  /* D/A1 FIFO (16bit) */
221 #define LAS1_DAC2_FIFO          0x000c  /* D/A2 FIFO (16bit) */
222 
223 /*======================================================================
224   Driver specific stuff (tunable)
225 ======================================================================*/
226 
227 /* We really only need 2 buffers.  More than that means being much
228    smarter about knowing which ones are full. */
229 #define DMA_CHAIN_COUNT 2       /* max DMA segments/buffers in a ring (min 2) */
230 
231 /* Target period for periodic transfers.  This sets the user read latency. */
232 /* Note: There are certain rates where we give this up and transfer 1/2 FIFO */
233 /* If this is too low, efficiency is poor */
234 #define TRANS_TARGET_PERIOD 10000000    /* 10 ms (in nanoseconds) */
235 
236 /* Set a practical limit on how long a list to support (affects memory use) */
237 /* The board support a channel list up to the FIFO length (1K or 8K) */
238 #define RTD_MAX_CHANLIST        128     /* max channel list that we allow */
239 
240 /*======================================================================
241   Board specific stuff
242 ======================================================================*/
243 
244 #define RTD_CLOCK_RATE  8000000 /* 8Mhz onboard clock */
245 #define RTD_CLOCK_BASE  125     /* clock period in ns */
246 
247 /* Note: these speed are slower than the spec, but fit the counter resolution*/
248 #define RTD_MAX_SPEED   1625    /* when sampling, in nanoseconds */
249 /* max speed if we don't have to wait for settling */
250 #define RTD_MAX_SPEED_1 875     /* if single channel, in nanoseconds */
251 
252 #define RTD_MIN_SPEED   2097151875      /* (24bit counter) in nanoseconds */
253 /* min speed when only 1 channel (no burst counter) */
254 #define RTD_MIN_SPEED_1 5000000 /* 200Hz, in nanoseconds */
255 
256 /* Setup continuous ring of 1/2 FIFO transfers.  See RTD manual p91 */
257 #define DMA_MODE_BITS (\
258                        PLX_LOCAL_BUS_16_WIDE_BITS \
259                        | PLX_DMA_EN_READYIN_BIT \
260                        | PLX_DMA_LOCAL_BURST_EN_BIT \
261                        | PLX_EN_CHAIN_BIT \
262                        | PLX_DMA_INTR_PCI_BIT \
263                        | PLX_LOCAL_ADDR_CONST_BIT \
264                        | PLX_DEMAND_MODE_BIT)
265 
266 #define DMA_TRANSFER_BITS (\
267 /* descriptors in PCI memory*/  PLX_DESC_IN_PCI_BIT \
268 /* interrupt at end of block */ | PLX_INTR_TERM_COUNT \
269 /* from board to PCI */         | PLX_XFER_LOCAL_TO_PCI)
270 
271 /*======================================================================
272   Comedi specific stuff
273 ======================================================================*/
274 
275 /*
276  * The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128)
277  */
278 static const struct comedi_lrange rtd_ai_7520_range = {
279         18, {
280                 /* +-5V input range gain steps */
281                 BIP_RANGE(5.0),
282                 BIP_RANGE(5.0 / 2),
283                 BIP_RANGE(5.0 / 4),
284                 BIP_RANGE(5.0 / 8),
285                 BIP_RANGE(5.0 / 16),
286                 BIP_RANGE(5.0 / 32),
287                 /* +-10V input range gain steps */
288                 BIP_RANGE(10.0),
289                 BIP_RANGE(10.0 / 2),
290                 BIP_RANGE(10.0 / 4),
291                 BIP_RANGE(10.0 / 8),
292                 BIP_RANGE(10.0 / 16),
293                 BIP_RANGE(10.0 / 32),
294                 /* +10V input range gain steps */
295                 UNI_RANGE(10.0),
296                 UNI_RANGE(10.0 / 2),
297                 UNI_RANGE(10.0 / 4),
298                 UNI_RANGE(10.0 / 8),
299                 UNI_RANGE(10.0 / 16),
300                 UNI_RANGE(10.0 / 32),
301         }
302 };
303 
304 /* PCI4520 has two more gains (6 more entries) */
305 static const struct comedi_lrange rtd_ai_4520_range = {
306         24, {
307                 /* +-5V input range gain steps */
308                 BIP_RANGE(5.0),
309                 BIP_RANGE(5.0 / 2),
310                 BIP_RANGE(5.0 / 4),
311                 BIP_RANGE(5.0 / 8),
312                 BIP_RANGE(5.0 / 16),
313                 BIP_RANGE(5.0 / 32),
314                 BIP_RANGE(5.0 / 64),
315                 BIP_RANGE(5.0 / 128),
316                 /* +-10V input range gain steps */
317                 BIP_RANGE(10.0),
318                 BIP_RANGE(10.0 / 2),
319                 BIP_RANGE(10.0 / 4),
320                 BIP_RANGE(10.0 / 8),
321                 BIP_RANGE(10.0 / 16),
322                 BIP_RANGE(10.0 / 32),
323                 BIP_RANGE(10.0 / 64),
324                 BIP_RANGE(10.0 / 128),
325                 /* +10V input range gain steps */
326                 UNI_RANGE(10.0),
327                 UNI_RANGE(10.0 / 2),
328                 UNI_RANGE(10.0 / 4),
329                 UNI_RANGE(10.0 / 8),
330                 UNI_RANGE(10.0 / 16),
331                 UNI_RANGE(10.0 / 32),
332                 UNI_RANGE(10.0 / 64),
333                 UNI_RANGE(10.0 / 128),
334         }
335 };
336 
337 /* Table order matches range values */
338 static const struct comedi_lrange rtd_ao_range = {
339         4, {
340                 UNI_RANGE(5),
341                 UNI_RANGE(10),
342                 BIP_RANGE(5),
343                 BIP_RANGE(10),
344         }
345 };
346 
347 enum rtd_boardid {
348         BOARD_DM7520,
349         BOARD_PCI4520,
350 };
351 
352 struct rtd_boardinfo {
353         const char *name;
354         int range_bip10;        /* start of +-10V range */
355         int range_uni10;        /* start of +10V range */
356         const struct comedi_lrange *ai_range;
357 };
358 
359 static const struct rtd_boardinfo rtd520Boards[] = {
360         [BOARD_DM7520] = {
361                 .name           = "DM7520",
362                 .range_bip10    = 6,
363                 .range_uni10    = 12,
364                 .ai_range       = &rtd_ai_7520_range,
365         },
366         [BOARD_PCI4520] = {
367                 .name           = "PCI4520",
368                 .range_bip10    = 8,
369                 .range_uni10    = 16,
370                 .ai_range       = &rtd_ai_4520_range,
371         },
372 };
373 
374 struct rtd_private {
375         /* memory mapped board structures */
376         void __iomem *las1;
377         void __iomem *lcfg;
378 
379         long ai_count;          /* total transfer size (samples) */
380         int xfer_count;         /* # to transfer data. 0->1/2FIFO */
381         int flags;              /* flag event modes */
382         DECLARE_BITMAP(chan_is_bipolar, RTD_MAX_CHANLIST);
383         unsigned int ao_readback[2];
384         unsigned fifosz;
385 };
386 
387 /* bit defines for "flags" */
388 #define SEND_EOS        0x01    /* send End Of Scan events */
389 #define DMA0_ACTIVE     0x02    /* DMA0 is active */
390 #define DMA1_ACTIVE     0x04    /* DMA1 is active */
391 
392 /*
393   Given a desired period and the clock period (both in ns),
394   return the proper counter value (divider-1).
395   Sets the original period to be the true value.
396   Note: you have to check if the value is larger than the counter range!
397 */
398 static int rtd_ns_to_timer_base(unsigned int *nanosec,
399                                 unsigned int flags, int base)
400 {
401         int divider;
402 
403         switch (flags & TRIG_ROUND_MASK) {
404         case TRIG_ROUND_NEAREST:
405         default:
406                 divider = (*nanosec + base / 2) / base;
407                 break;
408         case TRIG_ROUND_DOWN:
409                 divider = (*nanosec) / base;
410                 break;
411         case TRIG_ROUND_UP:
412                 divider = (*nanosec + base - 1) / base;
413                 break;
414         }
415         if (divider < 2)
416                 divider = 2;    /* min is divide by 2 */
417 
418         /* Note: we don't check for max, because different timers
419            have different ranges */
420 
421         *nanosec = base * divider;
422         return divider - 1;     /* countdown is divisor+1 */
423 }
424 
425 /*
426   Given a desired period (in ns),
427   return the proper counter value (divider-1) for the internal clock.
428   Sets the original period to be the true value.
429 */
430 static int rtd_ns_to_timer(unsigned int *ns, unsigned int flags)
431 {
432         return rtd_ns_to_timer_base(ns, flags, RTD_CLOCK_BASE);
433 }
434 
435 /*
436   Convert a single comedi channel-gain entry to a RTD520 table entry
437 */
438 static unsigned short rtd_convert_chan_gain(struct comedi_device *dev,
439                                             unsigned int chanspec, int index)
440 {
441         const struct rtd_boardinfo *board = comedi_board(dev);
442         struct rtd_private *devpriv = dev->private;
443         unsigned int chan = CR_CHAN(chanspec);
444         unsigned int range = CR_RANGE(chanspec);
445         unsigned int aref = CR_AREF(chanspec);
446         unsigned short r = 0;
447 
448         r |= chan & 0xf;
449 
450         /* Note: we also setup the channel list bipolar flag array */
451         if (range < board->range_bip10) {
452                 /* +-5 range */
453                 r |= 0x000;
454                 r |= (range & 0x7) << 4;
455                 __set_bit(index, devpriv->chan_is_bipolar);
456         } else if (range < board->range_uni10) {
457                 /* +-10 range */
458                 r |= 0x100;
459                 r |= ((range - board->range_bip10) & 0x7) << 4;
460                 __set_bit(index, devpriv->chan_is_bipolar);
461         } else {
462                 /* +10 range */
463                 r |= 0x200;
464                 r |= ((range - board->range_uni10) & 0x7) << 4;
465                 __clear_bit(index, devpriv->chan_is_bipolar);
466         }
467 
468         switch (aref) {
469         case AREF_GROUND:       /* on-board ground */
470                 break;
471 
472         case AREF_COMMON:
473                 r |= 0x80;      /* ref external analog common */
474                 break;
475 
476         case AREF_DIFF:
477                 r |= 0x400;     /* differential inputs */
478                 break;
479 
480         case AREF_OTHER:        /* ??? */
481                 break;
482         }
483         return r;
484 }
485 
486 /*
487   Setup the channel-gain table from a comedi list
488 */
489 static void rtd_load_channelgain_list(struct comedi_device *dev,
490                                       unsigned int n_chan, unsigned int *list)
491 {
492         if (n_chan > 1) {       /* setup channel gain table */
493                 int ii;
494 
495                 writel(0, dev->mmio + LAS0_CGT_CLEAR);
496                 writel(1, dev->mmio + LAS0_CGT_ENABLE);
497                 for (ii = 0; ii < n_chan; ii++) {
498                         writel(rtd_convert_chan_gain(dev, list[ii], ii),
499                                dev->mmio + LAS0_CGT_WRITE);
500                 }
501         } else {                /* just use the channel gain latch */
502                 writel(0, dev->mmio + LAS0_CGT_ENABLE);
503                 writel(rtd_convert_chan_gain(dev, list[0], 0),
504                        dev->mmio + LAS0_CGL_WRITE);
505         }
506 }
507 
508 /* determine fifo size by doing adc conversions until the fifo half
509 empty status flag clears */
510 static int rtd520_probe_fifo_depth(struct comedi_device *dev)
511 {
512         unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND);
513         unsigned i;
514         static const unsigned limit = 0x2000;
515         unsigned fifo_size = 0;
516 
517         writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
518         rtd_load_channelgain_list(dev, 1, &chanspec);
519         /* ADC conversion trigger source: SOFTWARE */
520         writel(0, dev->mmio + LAS0_ADC_CONVERSION);
521         /* convert  samples */
522         for (i = 0; i < limit; ++i) {
523                 unsigned fifo_status;
524                 /* trigger conversion */
525                 writew(0, dev->mmio + LAS0_ADC);
526                 udelay(1);
527                 fifo_status = readl(dev->mmio + LAS0_ADC);
528                 if ((fifo_status & FS_ADC_HEMPTY) == 0) {
529                         fifo_size = 2 * i;
530                         break;
531                 }
532         }
533         if (i == limit) {
534                 dev_info(dev->class_dev, "failed to probe fifo size.\n");
535                 return -EIO;
536         }
537         writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
538         if (fifo_size != 0x400 && fifo_size != 0x2000) {
539                 dev_info(dev->class_dev,
540                          "unexpected fifo size of %i, expected 1024 or 8192.\n",
541                          fifo_size);
542                 return -EIO;
543         }
544         return fifo_size;
545 }
546 
547 static int rtd_ai_eoc(struct comedi_device *dev,
548                       struct comedi_subdevice *s,
549                       struct comedi_insn *insn,
550                       unsigned long context)
551 {
552         unsigned int status;
553 
554         status = readl(dev->mmio + LAS0_ADC);
555         if (status & FS_ADC_NOT_EMPTY)
556                 return 0;
557         return -EBUSY;
558 }
559 
560 static int rtd_ai_rinsn(struct comedi_device *dev,
561                         struct comedi_subdevice *s, struct comedi_insn *insn,
562                         unsigned int *data)
563 {
564         struct rtd_private *devpriv = dev->private;
565         int ret;
566         int n;
567 
568         /* clear any old fifo data */
569         writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
570 
571         /* write channel to multiplexer and clear channel gain table */
572         rtd_load_channelgain_list(dev, 1, &insn->chanspec);
573 
574         /* ADC conversion trigger source: SOFTWARE */
575         writel(0, dev->mmio + LAS0_ADC_CONVERSION);
576 
577         /* convert n samples */
578         for (n = 0; n < insn->n; n++) {
579                 unsigned short d;
580                 /* trigger conversion */
581                 writew(0, dev->mmio + LAS0_ADC);
582 
583                 ret = comedi_timeout(dev, s, insn, rtd_ai_eoc, 0);
584                 if (ret)
585                         return ret;
586 
587                 /* read data */
588                 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
589                 d = d >> 3;     /* low 3 bits are marker lines */
590                 if (test_bit(0, devpriv->chan_is_bipolar))
591                         /* convert to comedi unsigned data */
592                         d = comedi_offset_munge(s, d);
593                 data[n] = d & s->maxdata;
594         }
595 
596         /* return the number of samples read/written */
597         return n;
598 }
599 
600 /*
601   Get what we know is there.... Fast!
602   This uses 1/2 the bus cycles of read_dregs (below).
603 
604   The manual claims that we can do a lword read, but it doesn't work here.
605 */
606 static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s,
607                      int count)
608 {
609         struct rtd_private *devpriv = dev->private;
610         int ii;
611 
612         for (ii = 0; ii < count; ii++) {
613                 unsigned short d;
614 
615                 if (0 == devpriv->ai_count) {   /* done */
616                         d = readw(devpriv->las1 + LAS1_ADC_FIFO);
617                         continue;
618                 }
619 
620                 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
621                 d = d >> 3;     /* low 3 bits are marker lines */
622                 if (test_bit(s->async->cur_chan, devpriv->chan_is_bipolar))
623                         /* convert to comedi unsigned data */
624                         d = comedi_offset_munge(s, d);
625                 d &= s->maxdata;
626 
627                 if (!comedi_buf_put(s, d))
628                         return -1;
629 
630                 if (devpriv->ai_count > 0)      /* < 0, means read forever */
631                         devpriv->ai_count--;
632         }
633         return 0;
634 }
635 
636 /*
637   unknown amout of data is waiting in fifo.
638 */
639 static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
640 {
641         struct rtd_private *devpriv = dev->private;
642 
643         while (readl(dev->mmio + LAS0_ADC) & FS_ADC_NOT_EMPTY) {
644                 unsigned short d = readw(devpriv->las1 + LAS1_ADC_FIFO);
645 
646                 if (0 == devpriv->ai_count) {   /* done */
647                         continue;       /* read rest */
648                 }
649 
650                 d = d >> 3;     /* low 3 bits are marker lines */
651                 if (test_bit(s->async->cur_chan, devpriv->chan_is_bipolar))
652                         /* convert to comedi unsigned data */
653                         d = comedi_offset_munge(s, d);
654                 d &= s->maxdata;
655 
656                 if (!comedi_buf_put(s, d))
657                         return -1;
658 
659                 if (devpriv->ai_count > 0)      /* < 0, means read forever */
660                         devpriv->ai_count--;
661         }
662         return 0;
663 }
664 
665 /*
666   Handle all rtd520 interrupts.
667   Runs atomically and is never re-entered.
668   This is a "slow handler";  other interrupts may be active.
669   The data conversion may someday happen in a "bottom half".
670 */
671 static irqreturn_t rtd_interrupt(int irq, void *d)
672 {
673         struct comedi_device *dev = d;
674         struct comedi_subdevice *s = dev->read_subdev;
675         struct rtd_private *devpriv = dev->private;
676         u32 overrun;
677         u16 status;
678         u16 fifo_status;
679 
680         if (!dev->attached)
681                 return IRQ_NONE;
682 
683         fifo_status = readl(dev->mmio + LAS0_ADC);
684         /* check for FIFO full, this automatically halts the ADC! */
685         if (!(fifo_status & FS_ADC_NOT_FULL))   /* 0 -> full */
686                 goto xfer_abort;
687 
688         status = readw(dev->mmio + LAS0_IT);
689         /* if interrupt was not caused by our board, or handled above */
690         if (0 == status)
691                 return IRQ_HANDLED;
692 
693         if (status & IRQM_ADC_ABOUT_CNT) {      /* sample count -> read FIFO */
694                 /*
695                  * since the priority interrupt controller may have queued
696                  * a sample counter interrupt, even though we have already
697                  * finished, we must handle the possibility that there is
698                  * no data here
699                  */
700                 if (!(fifo_status & FS_ADC_HEMPTY)) {
701                         /* FIFO half full */
702                         if (ai_read_n(dev, s, devpriv->fifosz / 2) < 0)
703                                 goto xfer_abort;
704 
705                         if (0 == devpriv->ai_count)
706                                 goto xfer_done;
707 
708                         comedi_event(dev, s);
709                 } else if (devpriv->xfer_count > 0) {
710                         if (fifo_status & FS_ADC_NOT_EMPTY) {
711                                 /* FIFO not empty */
712                                 if (ai_read_n(dev, s, devpriv->xfer_count) < 0)
713                                         goto xfer_abort;
714 
715                                 if (0 == devpriv->ai_count)
716                                         goto xfer_done;
717 
718                                 comedi_event(dev, s);
719                         }
720                 }
721         }
722 
723         overrun = readl(dev->mmio + LAS0_OVERRUN) & 0xffff;
724         if (overrun)
725                 goto xfer_abort;
726 
727         /* clear the interrupt */
728         writew(status, dev->mmio + LAS0_CLEAR);
729         readw(dev->mmio + LAS0_CLEAR);
730         return IRQ_HANDLED;
731 
732 xfer_abort:
733         writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
734         s->async->events |= COMEDI_CB_ERROR;
735         devpriv->ai_count = 0;  /* stop and don't transfer any more */
736         /* fall into xfer_done */
737 
738 xfer_done:
739         /* pacer stop source: SOFTWARE */
740         writel(0, dev->mmio + LAS0_PACER_STOP);
741         writel(0, dev->mmio + LAS0_PACER);      /* stop pacer */
742         writel(0, dev->mmio + LAS0_ADC_CONVERSION);
743         writew(0, dev->mmio + LAS0_IT);
744 
745         if (devpriv->ai_count > 0) {    /* there shouldn't be anything left */
746                 fifo_status = readl(dev->mmio + LAS0_ADC);
747                 ai_read_dregs(dev, s);  /* read anything left in FIFO */
748         }
749 
750         s->async->events |= COMEDI_CB_EOA;      /* signal end to comedi */
751         comedi_event(dev, s);
752 
753         /* clear the interrupt */
754         status = readw(dev->mmio + LAS0_IT);
755         writew(status, dev->mmio + LAS0_CLEAR);
756         readw(dev->mmio + LAS0_CLEAR);
757 
758         fifo_status = readl(dev->mmio + LAS0_ADC);
759         overrun = readl(dev->mmio + LAS0_OVERRUN) & 0xffff;
760 
761         return IRQ_HANDLED;
762 }
763 
764 /*
765   cmdtest tests a particular command to see if it is valid.
766   Using the cmdtest ioctl, a user can create a valid cmd
767   and then have it executed by the cmd ioctl (asynchronously).
768 
769   cmdtest returns 1,2,3,4 or 0, depending on which tests
770   the command passes.
771 */
772 
773 static int rtd_ai_cmdtest(struct comedi_device *dev,
774                           struct comedi_subdevice *s, struct comedi_cmd *cmd)
775 {
776         int err = 0;
777         unsigned int arg;
778 
779         /* Step 1 : check if triggers are trivially valid */
780 
781         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
782         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
783                                         TRIG_TIMER | TRIG_EXT);
784         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
785         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
786         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
787 
788         if (err)
789                 return 1;
790 
791         /* Step 2a : make sure trigger sources are unique */
792 
793         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
794         err |= cfc_check_trigger_is_unique(cmd->convert_src);
795         err |= cfc_check_trigger_is_unique(cmd->stop_src);
796 
797         /* Step 2b : and mutually compatible */
798 
799         if (err)
800                 return 2;
801 
802         /* Step 3: check if arguments are trivially valid */
803 
804         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
805 
806         if (cmd->scan_begin_src == TRIG_TIMER) {
807                 /* Note: these are time periods, not actual rates */
808                 if (1 == cmd->chanlist_len) {   /* no scanning */
809                         if (cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
810                                                       RTD_MAX_SPEED_1)) {
811                                 rtd_ns_to_timer(&cmd->scan_begin_arg,
812                                                 TRIG_ROUND_UP);
813                                 err |= -EINVAL;
814                         }
815                         if (cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
816                                                       RTD_MIN_SPEED_1)) {
817                                 rtd_ns_to_timer(&cmd->scan_begin_arg,
818                                                 TRIG_ROUND_DOWN);
819                                 err |= -EINVAL;
820                         }
821                 } else {
822                         if (cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
823                                                       RTD_MAX_SPEED)) {
824                                 rtd_ns_to_timer(&cmd->scan_begin_arg,
825                                                 TRIG_ROUND_UP);
826                                 err |= -EINVAL;
827                         }
828                         if (cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
829                                                       RTD_MIN_SPEED)) {
830                                 rtd_ns_to_timer(&cmd->scan_begin_arg,
831                                                 TRIG_ROUND_DOWN);
832                                 err |= -EINVAL;
833                         }
834                 }
835         } else {
836                 /* external trigger */
837                 /* should be level/edge, hi/lo specification here */
838                 /* should specify multiple external triggers */
839                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9);
840         }
841 
842         if (cmd->convert_src == TRIG_TIMER) {
843                 if (1 == cmd->chanlist_len) {   /* no scanning */
844                         if (cfc_check_trigger_arg_min(&cmd->convert_arg,
845                                                       RTD_MAX_SPEED_1)) {
846                                 rtd_ns_to_timer(&cmd->convert_arg,
847                                                 TRIG_ROUND_UP);
848                                 err |= -EINVAL;
849                         }
850                         if (cfc_check_trigger_arg_max(&cmd->convert_arg,
851                                                       RTD_MIN_SPEED_1)) {
852                                 rtd_ns_to_timer(&cmd->convert_arg,
853                                                 TRIG_ROUND_DOWN);
854                                 err |= -EINVAL;
855                         }
856                 } else {
857                         if (cfc_check_trigger_arg_min(&cmd->convert_arg,
858                                                       RTD_MAX_SPEED)) {
859                                 rtd_ns_to_timer(&cmd->convert_arg,
860                                                 TRIG_ROUND_UP);
861                                 err |= -EINVAL;
862                         }
863                         if (cfc_check_trigger_arg_max(&cmd->convert_arg,
864                                                       RTD_MIN_SPEED)) {
865                                 rtd_ns_to_timer(&cmd->convert_arg,
866                                                 TRIG_ROUND_DOWN);
867                                 err |= -EINVAL;
868                         }
869                 }
870         } else {
871                 /* external trigger */
872                 /* see above */
873                 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 9);
874         }
875 
876         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
877 
878         if (cmd->stop_src == TRIG_COUNT) {
879                 /* TODO check for rounding error due to counter wrap */
880         } else {
881                 /* TRIG_NONE */
882                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
883         }
884 
885         if (err)
886                 return 3;
887 
888 
889         /* step 4: fix up any arguments */
890 
891         if (cmd->scan_begin_src == TRIG_TIMER) {
892                 arg = cmd->scan_begin_arg;
893                 rtd_ns_to_timer(&arg, cmd->flags);
894                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
895         }
896 
897         if (cmd->convert_src == TRIG_TIMER) {
898                 arg = cmd->convert_arg;
899                 rtd_ns_to_timer(&arg, cmd->flags);
900                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, arg);
901 
902                 if (cmd->scan_begin_src == TRIG_TIMER) {
903                         arg = cmd->convert_arg * cmd->scan_end_arg;
904                         err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
905                                                          arg);
906                 }
907         }
908 
909         if (err)
910                 return 4;
911 
912         return 0;
913 }
914 
915 /*
916   Execute a analog in command with many possible triggering options.
917   The data get stored in the async structure of the subdevice.
918   This is usually done by an interrupt handler.
919   Userland gets to the data using read calls.
920 */
921 static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
922 {
923         struct rtd_private *devpriv = dev->private;
924         struct comedi_cmd *cmd = &s->async->cmd;
925         int timer;
926 
927         /* stop anything currently running */
928         /* pacer stop source: SOFTWARE */
929         writel(0, dev->mmio + LAS0_PACER_STOP);
930         writel(0, dev->mmio + LAS0_PACER);      /* stop pacer */
931         writel(0, dev->mmio + LAS0_ADC_CONVERSION);
932         writew(0, dev->mmio + LAS0_IT);
933         writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
934         writel(0, dev->mmio + LAS0_OVERRUN);
935 
936         /* start configuration */
937         /* load channel list and reset CGT */
938         rtd_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
939 
940         /* setup the common case and override if needed */
941         if (cmd->chanlist_len > 1) {
942                 /* pacer start source: SOFTWARE */
943                 writel(0, dev->mmio + LAS0_PACER_START);
944                 /* burst trigger source: PACER */
945                 writel(1, dev->mmio + LAS0_BURST_START);
946                 /* ADC conversion trigger source: BURST */
947                 writel(2, dev->mmio + LAS0_ADC_CONVERSION);
948         } else {                /* single channel */
949                 /* pacer start source: SOFTWARE */
950                 writel(0, dev->mmio + LAS0_PACER_START);
951                 /* ADC conversion trigger source: PACER */
952                 writel(1, dev->mmio + LAS0_ADC_CONVERSION);
953         }
954         writel((devpriv->fifosz / 2 - 1) & 0xffff, dev->mmio + LAS0_ACNT);
955 
956         if (TRIG_TIMER == cmd->scan_begin_src) {
957                 /* scan_begin_arg is in nanoseconds */
958                 /* find out how many samples to wait before transferring */
959                 if (cmd->flags & TRIG_WAKE_EOS) {
960                         /*
961                          * this may generate un-sustainable interrupt rates
962                          * the application is responsible for doing the
963                          * right thing
964                          */
965                         devpriv->xfer_count = cmd->chanlist_len;
966                         devpriv->flags |= SEND_EOS;
967                 } else {
968                         /* arrange to transfer data periodically */
969                         devpriv->xfer_count =
970                             (TRANS_TARGET_PERIOD * cmd->chanlist_len) /
971                             cmd->scan_begin_arg;
972                         if (devpriv->xfer_count < cmd->chanlist_len) {
973                                 /* transfer after each scan (and avoid 0) */
974                                 devpriv->xfer_count = cmd->chanlist_len;
975                         } else {        /* make a multiple of scan length */
976                                 devpriv->xfer_count =
977                                     (devpriv->xfer_count +
978                                      cmd->chanlist_len - 1)
979                                     / cmd->chanlist_len;
980                                 devpriv->xfer_count *= cmd->chanlist_len;
981                         }
982                         devpriv->flags |= SEND_EOS;
983                 }
984                 if (devpriv->xfer_count >= (devpriv->fifosz / 2)) {
985                         /* out of counter range, use 1/2 fifo instead */
986                         devpriv->xfer_count = 0;
987                         devpriv->flags &= ~SEND_EOS;
988                 } else {
989                         /* interrupt for each transfer */
990                         writel((devpriv->xfer_count - 1) & 0xffff,
991                                dev->mmio + LAS0_ACNT);
992                 }
993         } else {                /* unknown timing, just use 1/2 FIFO */
994                 devpriv->xfer_count = 0;
995                 devpriv->flags &= ~SEND_EOS;
996         }
997         /* pacer clock source: INTERNAL 8MHz */
998         writel(1, dev->mmio + LAS0_PACER_SELECT);
999         /* just interrupt, don't stop */
1000         writel(1, dev->mmio + LAS0_ACNT_STOP_ENABLE);
1001 
1002         /* BUG??? these look like enumerated values, but they are bit fields */
1003 
1004         /* First, setup when to stop */
1005         switch (cmd->stop_src) {
1006         case TRIG_COUNT:        /* stop after N scans */
1007                 devpriv->ai_count = cmd->stop_arg * cmd->chanlist_len;
1008                 if ((devpriv->xfer_count > 0)
1009                     && (devpriv->xfer_count > devpriv->ai_count)) {
1010                         devpriv->xfer_count = devpriv->ai_count;
1011                 }
1012                 break;
1013 
1014         case TRIG_NONE: /* stop when cancel is called */
1015                 devpriv->ai_count = -1; /* read forever */
1016                 break;
1017         }
1018 
1019         /* Scan timing */
1020         switch (cmd->scan_begin_src) {
1021         case TRIG_TIMER:        /* periodic scanning */
1022                 timer = rtd_ns_to_timer(&cmd->scan_begin_arg,
1023                                         TRIG_ROUND_NEAREST);
1024                 /* set PACER clock */
1025                 writel(timer & 0xffffff, dev->mmio + LAS0_PCLK);
1026 
1027                 break;
1028 
1029         case TRIG_EXT:
1030                 /* pacer start source: EXTERNAL */
1031                 writel(1, dev->mmio + LAS0_PACER_START);
1032                 break;
1033         }
1034 
1035         /* Sample timing within a scan */
1036         switch (cmd->convert_src) {
1037         case TRIG_TIMER:        /* periodic */
1038                 if (cmd->chanlist_len > 1) {
1039                         /* only needed for multi-channel */
1040                         timer = rtd_ns_to_timer(&cmd->convert_arg,
1041                                                 TRIG_ROUND_NEAREST);
1042                         /* setup BURST clock */
1043                         writel(timer & 0x3ff, dev->mmio + LAS0_BCLK);
1044                 }
1045 
1046                 break;
1047 
1048         case TRIG_EXT:          /* external */
1049                 /* burst trigger source: EXTERNAL */
1050                 writel(2, dev->mmio + LAS0_BURST_START);
1051                 break;
1052         }
1053         /* end configuration */
1054 
1055         /* This doesn't seem to work.  There is no way to clear an interrupt
1056            that the priority controller has queued! */
1057         writew(~0, dev->mmio + LAS0_CLEAR);
1058         readw(dev->mmio + LAS0_CLEAR);
1059 
1060         /* TODO: allow multiple interrupt sources */
1061         if (devpriv->xfer_count > 0)    /* transfer every N samples */
1062                 writew(IRQM_ADC_ABOUT_CNT, dev->mmio + LAS0_IT);
1063         else                            /* 1/2 FIFO transfers */
1064                 writew(IRQM_ADC_ABOUT_CNT, dev->mmio + LAS0_IT);
1065 
1066         /* BUG: start_src is ASSUMED to be TRIG_NOW */
1067         /* BUG? it seems like things are running before the "start" */
1068         readl(dev->mmio + LAS0_PACER);  /* start pacer */
1069         return 0;
1070 }
1071 
1072 /*
1073   Stop a running data acquisition.
1074 */
1075 static int rtd_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1076 {
1077         struct rtd_private *devpriv = dev->private;
1078         u32 overrun;
1079         u16 status;
1080 
1081         /* pacer stop source: SOFTWARE */
1082         writel(0, dev->mmio + LAS0_PACER_STOP);
1083         writel(0, dev->mmio + LAS0_PACER);      /* stop pacer */
1084         writel(0, dev->mmio + LAS0_ADC_CONVERSION);
1085         writew(0, dev->mmio + LAS0_IT);
1086         devpriv->ai_count = 0;  /* stop and don't transfer any more */
1087         status = readw(dev->mmio + LAS0_IT);
1088         overrun = readl(dev->mmio + LAS0_OVERRUN) & 0xffff;
1089         return 0;
1090 }
1091 
1092 static int rtd_ao_eoc(struct comedi_device *dev,
1093                       struct comedi_subdevice *s,
1094                       struct comedi_insn *insn,
1095                       unsigned long context)
1096 {
1097         unsigned int chan = CR_CHAN(insn->chanspec);
1098         unsigned int bit = (chan == 0) ? FS_DAC1_NOT_EMPTY : FS_DAC2_NOT_EMPTY;
1099         unsigned int status;
1100 
1101         status = readl(dev->mmio + LAS0_ADC);
1102         if (status & bit)
1103                 return 0;
1104         return -EBUSY;
1105 }
1106 
1107 static int rtd_ao_winsn(struct comedi_device *dev,
1108                         struct comedi_subdevice *s, struct comedi_insn *insn,
1109                         unsigned int *data)
1110 {
1111         struct rtd_private *devpriv = dev->private;
1112         int i;
1113         int chan = CR_CHAN(insn->chanspec);
1114         int range = CR_RANGE(insn->chanspec);
1115         int ret;
1116 
1117         /* Configure the output range (table index matches the range values) */
1118         writew(range & 7,
1119                dev->mmio + ((chan == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL));
1120 
1121         /* Writing a list of values to an AO channel is probably not
1122          * very useful, but that's how the interface is defined. */
1123         for (i = 0; i < insn->n; ++i) {
1124                 int val = data[i] << 3;
1125 
1126                 /* VERIFY: comedi range and offset conversions */
1127 
1128                 if ((range > 1) /* bipolar */
1129                     && (data[i] < 2048)) {
1130                         /* offset and sign extend */
1131                         val = (((int)data[i]) - 2048) << 3;
1132                 } else {        /* unipolor */
1133                         val = data[i] << 3;
1134                 }
1135 
1136                 /* a typical programming sequence */
1137                 writew(val, devpriv->las1 +
1138                         ((chan == 0) ? LAS1_DAC1_FIFO : LAS1_DAC2_FIFO));
1139                 writew(0, dev->mmio + ((chan == 0) ? LAS0_DAC1 : LAS0_DAC2));
1140 
1141                 devpriv->ao_readback[chan] = data[i];
1142 
1143                 ret = comedi_timeout(dev, s, insn, rtd_ao_eoc, 0);
1144                 if (ret)
1145                         return ret;
1146         }
1147 
1148         /* return the number of samples read/written */
1149         return i;
1150 }
1151 
1152 /* AO subdevices should have a read insn as well as a write insn.
1153  * Usually this means copying a value stored in devpriv. */
1154 static int rtd_ao_rinsn(struct comedi_device *dev,
1155                         struct comedi_subdevice *s, struct comedi_insn *insn,
1156                         unsigned int *data)
1157 {
1158         struct rtd_private *devpriv = dev->private;
1159         int i;
1160         int chan = CR_CHAN(insn->chanspec);
1161 
1162         for (i = 0; i < insn->n; i++)
1163                 data[i] = devpriv->ao_readback[chan];
1164 
1165 
1166         return i;
1167 }
1168 
1169 static int rtd_dio_insn_bits(struct comedi_device *dev,
1170                              struct comedi_subdevice *s,
1171                              struct comedi_insn *insn,
1172                              unsigned int *data)
1173 {
1174         if (comedi_dio_update_state(s, data))
1175                 writew(s->state & 0xff, dev->mmio + LAS0_DIO0);
1176 
1177         data[1] = readw(dev->mmio + LAS0_DIO0) & 0xff;
1178 
1179         return insn->n;
1180 }
1181 
1182 static int rtd_dio_insn_config(struct comedi_device *dev,
1183                                struct comedi_subdevice *s,
1184                                struct comedi_insn *insn,
1185                                unsigned int *data)
1186 {
1187         int ret;
1188 
1189         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
1190         if (ret)
1191                 return ret;
1192 
1193         /* TODO support digital match interrupts and strobes */
1194 
1195         /* set direction */
1196         writew(0x01, dev->mmio + LAS0_DIO_STATUS);
1197         writew(s->io_bits & 0xff, dev->mmio + LAS0_DIO0_CTRL);
1198 
1199         /* clear interrupts */
1200         writew(0x00, dev->mmio + LAS0_DIO_STATUS);
1201 
1202         /* port1 can only be all input or all output */
1203 
1204         /* there are also 2 user input lines and 2 user output lines */
1205 
1206         return insn->n;
1207 }
1208 
1209 static void rtd_reset(struct comedi_device *dev)
1210 {
1211         struct rtd_private *devpriv = dev->private;
1212 
1213         writel(0, dev->mmio + LAS0_BOARD_RESET);
1214         udelay(100);            /* needed? */
1215         writel(0, devpriv->lcfg + PLX_INTRCS_REG);
1216         writew(0, dev->mmio + LAS0_IT);
1217         writew(~0, dev->mmio + LAS0_CLEAR);
1218         readw(dev->mmio + LAS0_CLEAR);
1219 }
1220 
1221 /*
1222  * initialize board, per RTD spec
1223  * also, initialize shadow registers
1224  */
1225 static void rtd_init_board(struct comedi_device *dev)
1226 {
1227         rtd_reset(dev);
1228 
1229         writel(0, dev->mmio + LAS0_OVERRUN);
1230         writel(0, dev->mmio + LAS0_CGT_CLEAR);
1231         writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
1232         writel(0, dev->mmio + LAS0_DAC1_RESET);
1233         writel(0, dev->mmio + LAS0_DAC2_RESET);
1234         /* clear digital IO fifo */
1235         writew(0, dev->mmio + LAS0_DIO_STATUS);
1236         writeb((0 << 6) | 0x30, dev->mmio + LAS0_UTC_CTRL);
1237         writeb((1 << 6) | 0x30, dev->mmio + LAS0_UTC_CTRL);
1238         writeb((2 << 6) | 0x30, dev->mmio + LAS0_UTC_CTRL);
1239         writeb((3 << 6) | 0x00, dev->mmio + LAS0_UTC_CTRL);
1240         /* TODO: set user out source ??? */
1241 }
1242 
1243 /* The RTD driver does this */
1244 static void rtd_pci_latency_quirk(struct comedi_device *dev,
1245                                   struct pci_dev *pcidev)
1246 {
1247         unsigned char pci_latency;
1248 
1249         pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency);
1250         if (pci_latency < 32) {
1251                 dev_info(dev->class_dev,
1252                         "PCI latency changed from %d to %d\n",
1253                         pci_latency, 32);
1254                 pci_write_config_byte(pcidev, PCI_LATENCY_TIMER, 32);
1255         }
1256 }
1257 
1258 static int rtd_auto_attach(struct comedi_device *dev,
1259                            unsigned long context)
1260 {
1261         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1262         const struct rtd_boardinfo *board = NULL;
1263         struct rtd_private *devpriv;
1264         struct comedi_subdevice *s;
1265         int ret;
1266 
1267         if (context < ARRAY_SIZE(rtd520Boards))
1268                 board = &rtd520Boards[context];
1269         if (!board)
1270                 return -ENODEV;
1271         dev->board_ptr = board;
1272         dev->board_name = board->name;
1273 
1274         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
1275         if (!devpriv)
1276                 return -ENOMEM;
1277 
1278         ret = comedi_pci_enable(dev);
1279         if (ret)
1280                 return ret;
1281 
1282         dev->mmio = pci_ioremap_bar(pcidev, 2);
1283         devpriv->las1 = pci_ioremap_bar(pcidev, 3);
1284         devpriv->lcfg = pci_ioremap_bar(pcidev, 0);
1285         if (!dev->mmio || !devpriv->las1 || !devpriv->lcfg)
1286                 return -ENOMEM;
1287 
1288         rtd_pci_latency_quirk(dev, pcidev);
1289 
1290         if (pcidev->irq) {
1291                 ret = request_irq(pcidev->irq, rtd_interrupt, IRQF_SHARED,
1292                                   dev->board_name, dev);
1293                 if (ret == 0)
1294                         dev->irq = pcidev->irq;
1295         }
1296 
1297         ret = comedi_alloc_subdevices(dev, 4);
1298         if (ret)
1299                 return ret;
1300 
1301         s = &dev->subdevices[0];
1302         /* analog input subdevice */
1303         s->type         = COMEDI_SUBD_AI;
1304         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF;
1305         s->n_chan       = 16;
1306         s->maxdata      = 0x0fff;
1307         s->range_table  = board->ai_range;
1308         s->len_chanlist = RTD_MAX_CHANLIST;
1309         s->insn_read    = rtd_ai_rinsn;
1310         if (dev->irq) {
1311                 dev->read_subdev = s;
1312                 s->subdev_flags |= SDF_CMD_READ;
1313                 s->do_cmd       = rtd_ai_cmd;
1314                 s->do_cmdtest   = rtd_ai_cmdtest;
1315                 s->cancel       = rtd_ai_cancel;
1316         }
1317 
1318         s = &dev->subdevices[1];
1319         /* analog output subdevice */
1320         s->type         = COMEDI_SUBD_AO;
1321         s->subdev_flags = SDF_WRITABLE;
1322         s->n_chan       = 2;
1323         s->maxdata      = 0x0fff;
1324         s->range_table  = &rtd_ao_range;
1325         s->insn_write   = rtd_ao_winsn;
1326         s->insn_read    = rtd_ao_rinsn;
1327 
1328         s = &dev->subdevices[2];
1329         /* digital i/o subdevice */
1330         s->type         = COMEDI_SUBD_DIO;
1331         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1332         /* we only support port 0 right now.  Ignoring port 1 and user IO */
1333         s->n_chan       = 8;
1334         s->maxdata      = 1;
1335         s->range_table  = &range_digital;
1336         s->insn_bits    = rtd_dio_insn_bits;
1337         s->insn_config  = rtd_dio_insn_config;
1338 
1339         /* timer/counter subdevices (not currently supported) */
1340         s = &dev->subdevices[3];
1341         s->type         = COMEDI_SUBD_COUNTER;
1342         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1343         s->n_chan       = 3;
1344         s->maxdata      = 0xffff;
1345 
1346         rtd_init_board(dev);
1347 
1348         ret = rtd520_probe_fifo_depth(dev);
1349         if (ret < 0)
1350                 return ret;
1351         devpriv->fifosz = ret;
1352 
1353         if (dev->irq)
1354                 writel(ICS_PIE | ICS_PLIE, devpriv->lcfg + PLX_INTRCS_REG);
1355 
1356         return 0;
1357 }
1358 
1359 static void rtd_detach(struct comedi_device *dev)
1360 {
1361         struct rtd_private *devpriv = dev->private;
1362 
1363         if (devpriv) {
1364                 /* Shut down any board ops by resetting it */
1365                 if (dev->mmio && devpriv->lcfg)
1366                         rtd_reset(dev);
1367                 if (dev->irq) {
1368                         writel(readl(devpriv->lcfg + PLX_INTRCS_REG) &
1369                                 ~(ICS_PLIE | ICS_DMA0_E | ICS_DMA1_E),
1370                                 devpriv->lcfg + PLX_INTRCS_REG);
1371                         free_irq(dev->irq, dev);
1372                 }
1373                 if (dev->mmio)
1374                         iounmap(dev->mmio);
1375                 if (devpriv->las1)
1376                         iounmap(devpriv->las1);
1377                 if (devpriv->lcfg)
1378                         iounmap(devpriv->lcfg);
1379         }
1380         comedi_pci_disable(dev);
1381 }
1382 
1383 static struct comedi_driver rtd520_driver = {
1384         .driver_name    = "rtd520",
1385         .module         = THIS_MODULE,
1386         .auto_attach    = rtd_auto_attach,
1387         .detach         = rtd_detach,
1388 };
1389 
1390 static int rtd520_pci_probe(struct pci_dev *dev,
1391                             const struct pci_device_id *id)
1392 {
1393         return comedi_pci_auto_config(dev, &rtd520_driver, id->driver_data);
1394 }
1395 
1396 static const struct pci_device_id rtd520_pci_table[] = {
1397         { PCI_VDEVICE(RTD, 0x7520), BOARD_DM7520 },
1398         { PCI_VDEVICE(RTD, 0x4520), BOARD_PCI4520 },
1399         { 0 }
1400 };
1401 MODULE_DEVICE_TABLE(pci, rtd520_pci_table);
1402 
1403 static struct pci_driver rtd520_pci_driver = {
1404         .name           = "rtd520",
1405         .id_table       = rtd520_pci_table,
1406         .probe          = rtd520_pci_probe,
1407         .remove         = comedi_pci_auto_unconfig,
1408 };
1409 module_comedi_pci_driver(rtd520_driver, rtd520_pci_driver);
1410 
1411 MODULE_AUTHOR("Comedi http://www.comedi.org");
1412 MODULE_DESCRIPTION("Comedi low-level driver");
1413 MODULE_LICENSE("GPL");
1414 

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