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Linux/drivers/staging/comedi/drivers/rtd520.c

  1 /*
  2  * comedi/drivers/rtd520.c
  3  * Comedi driver for Real Time Devices (RTD) PCI4520/DM7520
  4  *
  5  * COMEDI - Linux Control and Measurement Device Interface
  6  * Copyright (C) 2001 David A. Schleef <ds@schleef.org>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 16  * GNU General Public License for more details.
 17  */
 18 
 19 /*
 20  * Driver: rtd520
 21  * Description: Real Time Devices PCI4520/DM7520
 22  * Devices: (Real Time Devices) DM7520HR-1 [DM7520]
 23  *          (Real Time Devices) DM7520HR-8 [DM7520]
 24  *          (Real Time Devices) PCI4520 [PCI4520]
 25  *          (Real Time Devices) PCI4520-8 [PCI4520]
 26  * Author: Dan Christian
 27  * Status: Works. Only tested on DM7520-8. Not SMP safe.
 28  *
 29  * Configuration options: not applicable, uses PCI auto config
 30  */
 31 
 32 /*
 33  * Created by Dan Christian, NASA Ames Research Center.
 34  *
 35  * The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
 36  * Both have:
 37  *   8/16 12 bit ADC with FIFO and channel gain table
 38  *   8 bits high speed digital out (for external MUX) (or 8 in or 8 out)
 39  *   8 bits high speed digital in with FIFO and interrupt on change (or 8 IO)
 40  *   2 12 bit DACs with FIFOs
 41  *   2 bits output
 42  *   2 bits input
 43  *   bus mastering DMA
 44  *   timers: ADC sample, pacer, burst, about, delay, DA1, DA2
 45  *   sample counter
 46  *   3 user timer/counters (8254)
 47  *   external interrupt
 48  *
 49  * The DM7520 has slightly fewer features (fewer gain steps).
 50  *
 51  * These boards can support external multiplexors and multi-board
 52  * synchronization, but this driver doesn't support that.
 53  *
 54  * Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm
 55  * Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf
 56  * Example source: http://www.rtdusa.com/examples/dm/dm7520.zip
 57  * Call them and ask for the register level manual.
 58  * PCI chip: http://www.plxtech.com/products/io/pci9080
 59  *
 60  * Notes:
 61  * This board is memory mapped. There is some IO stuff, but it isn't needed.
 62  *
 63  * I use a pretty loose naming style within the driver (rtd_blah).
 64  * All externally visible names should be rtd520_blah.
 65  * I use camelCase for structures (and inside them).
 66  * I may also use upper CamelCase for function names (old habit).
 67  *
 68  * This board is somewhat related to the RTD PCI4400 board.
 69  *
 70  * I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and
 71  * das1800, since they have the best documented code. Driver cb_pcidas64.c
 72  * uses the same DMA controller.
 73  *
 74  * As far as I can tell, the About interrupt doesn't work if Sample is
 75  * also enabled. It turns out that About really isn't needed, since
 76  * we always count down samples read.
 77  *
 78  * There was some timer/counter code, but it didn't follow the right API.
 79  */
 80 
 81 /*
 82  * driver status:
 83  *
 84  * Analog-In supports instruction and command mode.
 85  *
 86  * With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
 87  * (single channel, 64K read buffer). I get random system lockups when
 88  * using DMA with ALI-15xx based systems. I haven't been able to test
 89  * any other chipsets. The lockups happen soon after the start of an
 90  * acquistion, not in the middle of a long run.
 91  *
 92  * Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2
 93  * (with a 256K read buffer).
 94  *
 95  * Digital-IO and Analog-Out only support instruction mode.
 96  */
 97 
 98 #include <linux/module.h>
 99 #include <linux/pci.h>
100 #include <linux/delay.h>
101 #include <linux/interrupt.h>
102 
103 #include "../comedidev.h"
104 
105 #include "comedi_fc.h"
106 #include "plx9080.h"
107 
108 /*
109  * Local Address Space 0 Offsets
110  */
111 #define LAS0_USER_IO            0x0008  /* User I/O */
112 #define LAS0_ADC                0x0010  /* FIFO Status/Software A/D Start */
113 #define FS_DAC1_NOT_EMPTY       (1 << 0)        /* DAC1 FIFO not empty */
114 #define FS_DAC1_HEMPTY          (1 << 1)        /* DAC1 FIFO half empty */
115 #define FS_DAC1_NOT_FULL        (1 << 2)        /* DAC1 FIFO not full */
116 #define FS_DAC2_NOT_EMPTY       (1 << 4)        /* DAC2 FIFO not empty */
117 #define FS_DAC2_HEMPTY          (1 << 5)        /* DAC2 FIFO half empty */
118 #define FS_DAC2_NOT_FULL        (1 << 6)        /* DAC2 FIFO not full */
119 #define FS_ADC_NOT_EMPTY        (1 << 8)        /* ADC FIFO not empty */
120 #define FS_ADC_HEMPTY           (1 << 9)        /* ADC FIFO half empty */
121 #define FS_ADC_NOT_FULL         (1 << 10)       /* ADC FIFO not full */
122 #define FS_DIN_NOT_EMPTY        (1 << 12)       /* DIN FIFO not empty */
123 #define FS_DIN_HEMPTY           (1 << 13)       /* DIN FIFO half empty */
124 #define FS_DIN_NOT_FULL         (1 << 14)       /* DIN FIFO not full */
125 #define LAS0_DAC1               0x0014  /* Software D/A1 Update (w) */
126 #define LAS0_DAC2               0x0018  /* Software D/A2 Update (w) */
127 #define LAS0_DAC                0x0024  /* Software Simultaneous Update (w) */
128 #define LAS0_PACER              0x0028  /* Software Pacer Start/Stop */
129 #define LAS0_TIMER              0x002c  /* Timer Status/HDIN Software Trig. */
130 #define LAS0_IT                 0x0030  /* Interrupt Status/Enable */
131 #define IRQM_ADC_FIFO_WRITE     (1 << 0)        /* ADC FIFO Write */
132 #define IRQM_CGT_RESET          (1 << 1)        /* Reset CGT */
133 #define IRQM_CGT_PAUSE          (1 << 3)        /* Pause CGT */
134 #define IRQM_ADC_ABOUT_CNT      (1 << 4)        /* About Counter out */
135 #define IRQM_ADC_DELAY_CNT      (1 << 5)        /* Delay Counter out */
136 #define IRQM_ADC_SAMPLE_CNT     (1 << 6)        /* ADC Sample Counter */
137 #define IRQM_DAC1_UCNT          (1 << 7)        /* DAC1 Update Counter */
138 #define IRQM_DAC2_UCNT          (1 << 8)        /* DAC2 Update Counter */
139 #define IRQM_UTC1               (1 << 9)        /* User TC1 out */
140 #define IRQM_UTC1_INV           (1 << 10)       /* User TC1 out, inverted */
141 #define IRQM_UTC2               (1 << 11)       /* User TC2 out */
142 #define IRQM_DIGITAL_IT         (1 << 12)       /* Digital Interrupt */
143 #define IRQM_EXTERNAL_IT        (1 << 13)       /* External Interrupt */
144 #define IRQM_ETRIG_RISING       (1 << 14)       /* Ext Trigger rising-edge */
145 #define IRQM_ETRIG_FALLING      (1 << 15)       /* Ext Trigger falling-edge */
146 #define LAS0_CLEAR              0x0034  /* Clear/Set Interrupt Clear Mask */
147 #define LAS0_OVERRUN            0x0038  /* Pending interrupts/Clear Overrun */
148 #define LAS0_PCLK               0x0040  /* Pacer Clock (24bit) */
149 #define LAS0_BCLK               0x0044  /* Burst Clock (10bit) */
150 #define LAS0_ADC_SCNT           0x0048  /* A/D Sample counter (10bit) */
151 #define LAS0_DAC1_UCNT          0x004c  /* D/A1 Update counter (10 bit) */
152 #define LAS0_DAC2_UCNT          0x0050  /* D/A2 Update counter (10 bit) */
153 #define LAS0_DCNT               0x0054  /* Delay counter (16 bit) */
154 #define LAS0_ACNT               0x0058  /* About counter (16 bit) */
155 #define LAS0_DAC_CLK            0x005c  /* DAC clock (16bit) */
156 #define LAS0_UTC0               0x0060  /* 8254 TC Counter 0 */
157 #define LAS0_UTC1               0x0064  /* 8254 TC Counter 1 */
158 #define LAS0_UTC2               0x0068  /* 8254 TC Counter 2 */
159 #define LAS0_UTC_CTRL           0x006c  /* 8254 TC Control */
160 #define LAS0_DIO0               0x0070  /* Digital I/O Port 0 */
161 #define LAS0_DIO1               0x0074  /* Digital I/O Port 1 */
162 #define LAS0_DIO0_CTRL          0x0078  /* Digital I/O Control */
163 #define LAS0_DIO_STATUS         0x007c  /* Digital I/O Status */
164 #define LAS0_BOARD_RESET        0x0100  /* Board reset */
165 #define LAS0_DMA0_SRC           0x0104  /* DMA 0 Sources select */
166 #define LAS0_DMA1_SRC           0x0108  /* DMA 1 Sources select */
167 #define LAS0_ADC_CONVERSION     0x010c  /* A/D Conversion Signal select */
168 #define LAS0_BURST_START        0x0110  /* Burst Clock Start Trigger select */
169 #define LAS0_PACER_START        0x0114  /* Pacer Clock Start Trigger select */
170 #define LAS0_PACER_STOP         0x0118  /* Pacer Clock Stop Trigger select */
171 #define LAS0_ACNT_STOP_ENABLE   0x011c  /* About Counter Stop Enable */
172 #define LAS0_PACER_REPEAT       0x0120  /* Pacer Start Trigger Mode select */
173 #define LAS0_DIN_START          0x0124  /* HiSpd DI Sampling Signal select */
174 #define LAS0_DIN_FIFO_CLEAR     0x0128  /* Digital Input FIFO Clear */
175 #define LAS0_ADC_FIFO_CLEAR     0x012c  /* A/D FIFO Clear */
176 #define LAS0_CGT_WRITE          0x0130  /* Channel Gain Table Write */
177 #define LAS0_CGL_WRITE          0x0134  /* Channel Gain Latch Write */
178 #define LAS0_CG_DATA            0x0138  /* Digital Table Write */
179 #define LAS0_CGT_ENABLE         0x013c  /* Channel Gain Table Enable */
180 #define LAS0_CG_ENABLE          0x0140  /* Digital Table Enable */
181 #define LAS0_CGT_PAUSE          0x0144  /* Table Pause Enable */
182 #define LAS0_CGT_RESET          0x0148  /* Reset Channel Gain Table */
183 #define LAS0_CGT_CLEAR          0x014c  /* Clear Channel Gain Table */
184 #define LAS0_DAC1_CTRL          0x0150  /* D/A1 output type/range */
185 #define LAS0_DAC1_SRC           0x0154  /* D/A1 update source */
186 #define LAS0_DAC1_CYCLE         0x0158  /* D/A1 cycle mode */
187 #define LAS0_DAC1_RESET         0x015c  /* D/A1 FIFO reset */
188 #define LAS0_DAC1_FIFO_CLEAR    0x0160  /* D/A1 FIFO clear */
189 #define LAS0_DAC2_CTRL          0x0164  /* D/A2 output type/range */
190 #define LAS0_DAC2_SRC           0x0168  /* D/A2 update source */
191 #define LAS0_DAC2_CYCLE         0x016c  /* D/A2 cycle mode */
192 #define LAS0_DAC2_RESET         0x0170  /* D/A2 FIFO reset */
193 #define LAS0_DAC2_FIFO_CLEAR    0x0174  /* D/A2 FIFO clear */
194 #define LAS0_ADC_SCNT_SRC       0x0178  /* A/D Sample Counter Source select */
195 #define LAS0_PACER_SELECT       0x0180  /* Pacer Clock select */
196 #define LAS0_SBUS0_SRC          0x0184  /* SyncBus 0 Source select */
197 #define LAS0_SBUS0_ENABLE       0x0188  /* SyncBus 0 enable */
198 #define LAS0_SBUS1_SRC          0x018c  /* SyncBus 1 Source select */
199 #define LAS0_SBUS1_ENABLE       0x0190  /* SyncBus 1 enable */
200 #define LAS0_SBUS2_SRC          0x0198  /* SyncBus 2 Source select */
201 #define LAS0_SBUS2_ENABLE       0x019c  /* SyncBus 2 enable */
202 #define LAS0_ETRG_POLARITY      0x01a4  /* Ext. Trigger polarity select */
203 #define LAS0_EINT_POLARITY      0x01a8  /* Ext. Interrupt polarity select */
204 #define LAS0_UTC0_CLOCK         0x01ac  /* UTC0 Clock select */
205 #define LAS0_UTC0_GATE          0x01b0  /* UTC0 Gate select */
206 #define LAS0_UTC1_CLOCK         0x01b4  /* UTC1 Clock select */
207 #define LAS0_UTC1_GATE          0x01b8  /* UTC1 Gate select */
208 #define LAS0_UTC2_CLOCK         0x01bc  /* UTC2 Clock select */
209 #define LAS0_UTC2_GATE          0x01c0  /* UTC2 Gate select */
210 #define LAS0_UOUT0_SELECT       0x01c4  /* User Output 0 source select */
211 #define LAS0_UOUT1_SELECT       0x01c8  /* User Output 1 source select */
212 #define LAS0_DMA0_RESET         0x01cc  /* DMA0 Request state machine reset */
213 #define LAS0_DMA1_RESET         0x01d0  /* DMA1 Request state machine reset */
214 
215 /*
216  * Local Address Space 1 Offsets
217  */
218 #define LAS1_ADC_FIFO           0x0000  /* A/D FIFO (16bit) */
219 #define LAS1_HDIO_FIFO          0x0004  /* HiSpd DI FIFO (16bit) */
220 #define LAS1_DAC1_FIFO          0x0008  /* D/A1 FIFO (16bit) */
221 #define LAS1_DAC2_FIFO          0x000c  /* D/A2 FIFO (16bit) */
222 
223 /*======================================================================
224   Driver specific stuff (tunable)
225 ======================================================================*/
226 
227 /* We really only need 2 buffers.  More than that means being much
228    smarter about knowing which ones are full. */
229 #define DMA_CHAIN_COUNT 2       /* max DMA segments/buffers in a ring (min 2) */
230 
231 /* Target period for periodic transfers.  This sets the user read latency. */
232 /* Note: There are certain rates where we give this up and transfer 1/2 FIFO */
233 /* If this is too low, efficiency is poor */
234 #define TRANS_TARGET_PERIOD 10000000    /* 10 ms (in nanoseconds) */
235 
236 /* Set a practical limit on how long a list to support (affects memory use) */
237 /* The board support a channel list up to the FIFO length (1K or 8K) */
238 #define RTD_MAX_CHANLIST        128     /* max channel list that we allow */
239 
240 /*======================================================================
241   Board specific stuff
242 ======================================================================*/
243 
244 #define RTD_CLOCK_RATE  8000000 /* 8Mhz onboard clock */
245 #define RTD_CLOCK_BASE  125     /* clock period in ns */
246 
247 /* Note: these speed are slower than the spec, but fit the counter resolution*/
248 #define RTD_MAX_SPEED   1625    /* when sampling, in nanoseconds */
249 /* max speed if we don't have to wait for settling */
250 #define RTD_MAX_SPEED_1 875     /* if single channel, in nanoseconds */
251 
252 #define RTD_MIN_SPEED   2097151875      /* (24bit counter) in nanoseconds */
253 /* min speed when only 1 channel (no burst counter) */
254 #define RTD_MIN_SPEED_1 5000000 /* 200Hz, in nanoseconds */
255 
256 /* Setup continuous ring of 1/2 FIFO transfers.  See RTD manual p91 */
257 #define DMA_MODE_BITS (\
258                        PLX_LOCAL_BUS_16_WIDE_BITS \
259                        | PLX_DMA_EN_READYIN_BIT \
260                        | PLX_DMA_LOCAL_BURST_EN_BIT \
261                        | PLX_EN_CHAIN_BIT \
262                        | PLX_DMA_INTR_PCI_BIT \
263                        | PLX_LOCAL_ADDR_CONST_BIT \
264                        | PLX_DEMAND_MODE_BIT)
265 
266 #define DMA_TRANSFER_BITS (\
267 /* descriptors in PCI memory*/  PLX_DESC_IN_PCI_BIT \
268 /* interrupt at end of block */ | PLX_INTR_TERM_COUNT \
269 /* from board to PCI */         | PLX_XFER_LOCAL_TO_PCI)
270 
271 /*======================================================================
272   Comedi specific stuff
273 ======================================================================*/
274 
275 /*
276  * The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128)
277  */
278 static const struct comedi_lrange rtd_ai_7520_range = {
279         18, {
280                 /* +-5V input range gain steps */
281                 BIP_RANGE(5.0),
282                 BIP_RANGE(5.0 / 2),
283                 BIP_RANGE(5.0 / 4),
284                 BIP_RANGE(5.0 / 8),
285                 BIP_RANGE(5.0 / 16),
286                 BIP_RANGE(5.0 / 32),
287                 /* +-10V input range gain steps */
288                 BIP_RANGE(10.0),
289                 BIP_RANGE(10.0 / 2),
290                 BIP_RANGE(10.0 / 4),
291                 BIP_RANGE(10.0 / 8),
292                 BIP_RANGE(10.0 / 16),
293                 BIP_RANGE(10.0 / 32),
294                 /* +10V input range gain steps */
295                 UNI_RANGE(10.0),
296                 UNI_RANGE(10.0 / 2),
297                 UNI_RANGE(10.0 / 4),
298                 UNI_RANGE(10.0 / 8),
299                 UNI_RANGE(10.0 / 16),
300                 UNI_RANGE(10.0 / 32),
301         }
302 };
303 
304 /* PCI4520 has two more gains (6 more entries) */
305 static const struct comedi_lrange rtd_ai_4520_range = {
306         24, {
307                 /* +-5V input range gain steps */
308                 BIP_RANGE(5.0),
309                 BIP_RANGE(5.0 / 2),
310                 BIP_RANGE(5.0 / 4),
311                 BIP_RANGE(5.0 / 8),
312                 BIP_RANGE(5.0 / 16),
313                 BIP_RANGE(5.0 / 32),
314                 BIP_RANGE(5.0 / 64),
315                 BIP_RANGE(5.0 / 128),
316                 /* +-10V input range gain steps */
317                 BIP_RANGE(10.0),
318                 BIP_RANGE(10.0 / 2),
319                 BIP_RANGE(10.0 / 4),
320                 BIP_RANGE(10.0 / 8),
321                 BIP_RANGE(10.0 / 16),
322                 BIP_RANGE(10.0 / 32),
323                 BIP_RANGE(10.0 / 64),
324                 BIP_RANGE(10.0 / 128),
325                 /* +10V input range gain steps */
326                 UNI_RANGE(10.0),
327                 UNI_RANGE(10.0 / 2),
328                 UNI_RANGE(10.0 / 4),
329                 UNI_RANGE(10.0 / 8),
330                 UNI_RANGE(10.0 / 16),
331                 UNI_RANGE(10.0 / 32),
332                 UNI_RANGE(10.0 / 64),
333                 UNI_RANGE(10.0 / 128),
334         }
335 };
336 
337 /* Table order matches range values */
338 static const struct comedi_lrange rtd_ao_range = {
339         4, {
340                 UNI_RANGE(5),
341                 UNI_RANGE(10),
342                 BIP_RANGE(5),
343                 BIP_RANGE(10),
344         }
345 };
346 
347 enum rtd_boardid {
348         BOARD_DM7520,
349         BOARD_PCI4520,
350 };
351 
352 struct rtd_boardinfo {
353         const char *name;
354         int range_bip10;        /* start of +-10V range */
355         int range_uni10;        /* start of +10V range */
356         const struct comedi_lrange *ai_range;
357 };
358 
359 static const struct rtd_boardinfo rtd520Boards[] = {
360         [BOARD_DM7520] = {
361                 .name           = "DM7520",
362                 .range_bip10    = 6,
363                 .range_uni10    = 12,
364                 .ai_range       = &rtd_ai_7520_range,
365         },
366         [BOARD_PCI4520] = {
367                 .name           = "PCI4520",
368                 .range_bip10    = 8,
369                 .range_uni10    = 16,
370                 .ai_range       = &rtd_ai_4520_range,
371         },
372 };
373 
374 struct rtd_private {
375         /* memory mapped board structures */
376         void __iomem *las0;
377         void __iomem *las1;
378         void __iomem *lcfg;
379 
380         long ai_count;          /* total transfer size (samples) */
381         int xfer_count;         /* # to transfer data. 0->1/2FIFO */
382         int flags;              /* flag event modes */
383         DECLARE_BITMAP(chan_is_bipolar, RTD_MAX_CHANLIST);
384         unsigned int ao_readback[2];
385         unsigned fifosz;
386 };
387 
388 /* bit defines for "flags" */
389 #define SEND_EOS        0x01    /* send End Of Scan events */
390 #define DMA0_ACTIVE     0x02    /* DMA0 is active */
391 #define DMA1_ACTIVE     0x04    /* DMA1 is active */
392 
393 /*
394   Given a desired period and the clock period (both in ns),
395   return the proper counter value (divider-1).
396   Sets the original period to be the true value.
397   Note: you have to check if the value is larger than the counter range!
398 */
399 static int rtd_ns_to_timer_base(unsigned int *nanosec,
400                                 int round_mode, int base)
401 {
402         int divider;
403 
404         switch (round_mode) {
405         case TRIG_ROUND_NEAREST:
406         default:
407                 divider = (*nanosec + base / 2) / base;
408                 break;
409         case TRIG_ROUND_DOWN:
410                 divider = (*nanosec) / base;
411                 break;
412         case TRIG_ROUND_UP:
413                 divider = (*nanosec + base - 1) / base;
414                 break;
415         }
416         if (divider < 2)
417                 divider = 2;    /* min is divide by 2 */
418 
419         /* Note: we don't check for max, because different timers
420            have different ranges */
421 
422         *nanosec = base * divider;
423         return divider - 1;     /* countdown is divisor+1 */
424 }
425 
426 /*
427   Given a desired period (in ns),
428   return the proper counter value (divider-1) for the internal clock.
429   Sets the original period to be the true value.
430 */
431 static int rtd_ns_to_timer(unsigned int *ns, int round_mode)
432 {
433         return rtd_ns_to_timer_base(ns, round_mode, RTD_CLOCK_BASE);
434 }
435 
436 /*
437   Convert a single comedi channel-gain entry to a RTD520 table entry
438 */
439 static unsigned short rtd_convert_chan_gain(struct comedi_device *dev,
440                                             unsigned int chanspec, int index)
441 {
442         const struct rtd_boardinfo *board = comedi_board(dev);
443         struct rtd_private *devpriv = dev->private;
444         unsigned int chan = CR_CHAN(chanspec);
445         unsigned int range = CR_RANGE(chanspec);
446         unsigned int aref = CR_AREF(chanspec);
447         unsigned short r = 0;
448 
449         r |= chan & 0xf;
450 
451         /* Note: we also setup the channel list bipolar flag array */
452         if (range < board->range_bip10) {
453                 /* +-5 range */
454                 r |= 0x000;
455                 r |= (range & 0x7) << 4;
456                 __set_bit(index, devpriv->chan_is_bipolar);
457         } else if (range < board->range_uni10) {
458                 /* +-10 range */
459                 r |= 0x100;
460                 r |= ((range - board->range_bip10) & 0x7) << 4;
461                 __set_bit(index, devpriv->chan_is_bipolar);
462         } else {
463                 /* +10 range */
464                 r |= 0x200;
465                 r |= ((range - board->range_uni10) & 0x7) << 4;
466                 __clear_bit(index, devpriv->chan_is_bipolar);
467         }
468 
469         switch (aref) {
470         case AREF_GROUND:       /* on-board ground */
471                 break;
472 
473         case AREF_COMMON:
474                 r |= 0x80;      /* ref external analog common */
475                 break;
476 
477         case AREF_DIFF:
478                 r |= 0x400;     /* differential inputs */
479                 break;
480 
481         case AREF_OTHER:        /* ??? */
482                 break;
483         }
484         return r;
485 }
486 
487 /*
488   Setup the channel-gain table from a comedi list
489 */
490 static void rtd_load_channelgain_list(struct comedi_device *dev,
491                                       unsigned int n_chan, unsigned int *list)
492 {
493         struct rtd_private *devpriv = dev->private;
494 
495         if (n_chan > 1) {       /* setup channel gain table */
496                 int ii;
497 
498                 writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
499                 writel(1, devpriv->las0 + LAS0_CGT_ENABLE);
500                 for (ii = 0; ii < n_chan; ii++) {
501                         writel(rtd_convert_chan_gain(dev, list[ii], ii),
502                                 devpriv->las0 + LAS0_CGT_WRITE);
503                 }
504         } else {                /* just use the channel gain latch */
505                 writel(0, devpriv->las0 + LAS0_CGT_ENABLE);
506                 writel(rtd_convert_chan_gain(dev, list[0], 0),
507                         devpriv->las0 + LAS0_CGL_WRITE);
508         }
509 }
510 
511 /* determine fifo size by doing adc conversions until the fifo half
512 empty status flag clears */
513 static int rtd520_probe_fifo_depth(struct comedi_device *dev)
514 {
515         struct rtd_private *devpriv = dev->private;
516         unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND);
517         unsigned i;
518         static const unsigned limit = 0x2000;
519         unsigned fifo_size = 0;
520 
521         writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
522         rtd_load_channelgain_list(dev, 1, &chanspec);
523         /* ADC conversion trigger source: SOFTWARE */
524         writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
525         /* convert  samples */
526         for (i = 0; i < limit; ++i) {
527                 unsigned fifo_status;
528                 /* trigger conversion */
529                 writew(0, devpriv->las0 + LAS0_ADC);
530                 udelay(1);
531                 fifo_status = readl(devpriv->las0 + LAS0_ADC);
532                 if ((fifo_status & FS_ADC_HEMPTY) == 0) {
533                         fifo_size = 2 * i;
534                         break;
535                 }
536         }
537         if (i == limit) {
538                 dev_info(dev->class_dev, "failed to probe fifo size.\n");
539                 return -EIO;
540         }
541         writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
542         if (fifo_size != 0x400 && fifo_size != 0x2000) {
543                 dev_info(dev->class_dev,
544                          "unexpected fifo size of %i, expected 1024 or 8192.\n",
545                          fifo_size);
546                 return -EIO;
547         }
548         return fifo_size;
549 }
550 
551 static int rtd_ai_eoc(struct comedi_device *dev,
552                       struct comedi_subdevice *s,
553                       struct comedi_insn *insn,
554                       unsigned long context)
555 {
556         struct rtd_private *devpriv = dev->private;
557         unsigned int status;
558 
559         status = readl(devpriv->las0 + LAS0_ADC);
560         if (status & FS_ADC_NOT_EMPTY)
561                 return 0;
562         return -EBUSY;
563 }
564 
565 static int rtd_ai_rinsn(struct comedi_device *dev,
566                         struct comedi_subdevice *s, struct comedi_insn *insn,
567                         unsigned int *data)
568 {
569         struct rtd_private *devpriv = dev->private;
570         int ret;
571         int n;
572 
573         /* clear any old fifo data */
574         writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
575 
576         /* write channel to multiplexer and clear channel gain table */
577         rtd_load_channelgain_list(dev, 1, &insn->chanspec);
578 
579         /* ADC conversion trigger source: SOFTWARE */
580         writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
581 
582         /* convert n samples */
583         for (n = 0; n < insn->n; n++) {
584                 unsigned short d;
585                 /* trigger conversion */
586                 writew(0, devpriv->las0 + LAS0_ADC);
587 
588                 ret = comedi_timeout(dev, s, insn, rtd_ai_eoc, 0);
589                 if (ret)
590                         return ret;
591 
592                 /* read data */
593                 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
594                 d = d >> 3;     /* low 3 bits are marker lines */
595                 if (test_bit(0, devpriv->chan_is_bipolar))
596                         /* convert to comedi unsigned data */
597                         d = comedi_offset_munge(s, d);
598                 data[n] = d & s->maxdata;
599         }
600 
601         /* return the number of samples read/written */
602         return n;
603 }
604 
605 /*
606   Get what we know is there.... Fast!
607   This uses 1/2 the bus cycles of read_dregs (below).
608 
609   The manual claims that we can do a lword read, but it doesn't work here.
610 */
611 static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s,
612                      int count)
613 {
614         struct rtd_private *devpriv = dev->private;
615         int ii;
616 
617         for (ii = 0; ii < count; ii++) {
618                 unsigned short d;
619 
620                 if (0 == devpriv->ai_count) {   /* done */
621                         d = readw(devpriv->las1 + LAS1_ADC_FIFO);
622                         continue;
623                 }
624 
625                 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
626                 d = d >> 3;     /* low 3 bits are marker lines */
627                 if (test_bit(s->async->cur_chan, devpriv->chan_is_bipolar))
628                         /* convert to comedi unsigned data */
629                         d = comedi_offset_munge(s, d);
630                 d &= s->maxdata;
631 
632                 if (!comedi_buf_put(s->async, d))
633                         return -1;
634 
635                 if (devpriv->ai_count > 0)      /* < 0, means read forever */
636                         devpriv->ai_count--;
637         }
638         return 0;
639 }
640 
641 /*
642   unknown amout of data is waiting in fifo.
643 */
644 static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
645 {
646         struct rtd_private *devpriv = dev->private;
647 
648         while (readl(devpriv->las0 + LAS0_ADC) & FS_ADC_NOT_EMPTY) {
649                 unsigned short d = readw(devpriv->las1 + LAS1_ADC_FIFO);
650 
651                 if (0 == devpriv->ai_count) {   /* done */
652                         continue;       /* read rest */
653                 }
654 
655                 d = d >> 3;     /* low 3 bits are marker lines */
656                 if (test_bit(s->async->cur_chan, devpriv->chan_is_bipolar))
657                         /* convert to comedi unsigned data */
658                         d = comedi_offset_munge(s, d);
659                 d &= s->maxdata;
660 
661                 if (!comedi_buf_put(s->async, d))
662                         return -1;
663 
664                 if (devpriv->ai_count > 0)      /* < 0, means read forever */
665                         devpriv->ai_count--;
666         }
667         return 0;
668 }
669 
670 /*
671   Handle all rtd520 interrupts.
672   Runs atomically and is never re-entered.
673   This is a "slow handler";  other interrupts may be active.
674   The data conversion may someday happen in a "bottom half".
675 */
676 static irqreturn_t rtd_interrupt(int irq, void *d)
677 {
678         struct comedi_device *dev = d;
679         struct comedi_subdevice *s = dev->read_subdev;
680         struct rtd_private *devpriv = dev->private;
681         u32 overrun;
682         u16 status;
683         u16 fifo_status;
684 
685         if (!dev->attached)
686                 return IRQ_NONE;
687 
688         fifo_status = readl(devpriv->las0 + LAS0_ADC);
689         /* check for FIFO full, this automatically halts the ADC! */
690         if (!(fifo_status & FS_ADC_NOT_FULL))   /* 0 -> full */
691                 goto xfer_abort;
692 
693         status = readw(devpriv->las0 + LAS0_IT);
694         /* if interrupt was not caused by our board, or handled above */
695         if (0 == status)
696                 return IRQ_HANDLED;
697 
698         if (status & IRQM_ADC_ABOUT_CNT) {      /* sample count -> read FIFO */
699                 /*
700                  * since the priority interrupt controller may have queued
701                  * a sample counter interrupt, even though we have already
702                  * finished, we must handle the possibility that there is
703                  * no data here
704                  */
705                 if (!(fifo_status & FS_ADC_HEMPTY)) {
706                         /* FIFO half full */
707                         if (ai_read_n(dev, s, devpriv->fifosz / 2) < 0)
708                                 goto xfer_abort;
709 
710                         if (0 == devpriv->ai_count)
711                                 goto xfer_done;
712 
713                         comedi_event(dev, s);
714                 } else if (devpriv->xfer_count > 0) {
715                         if (fifo_status & FS_ADC_NOT_EMPTY) {
716                                 /* FIFO not empty */
717                                 if (ai_read_n(dev, s, devpriv->xfer_count) < 0)
718                                         goto xfer_abort;
719 
720                                 if (0 == devpriv->ai_count)
721                                         goto xfer_done;
722 
723                                 comedi_event(dev, s);
724                         }
725                 }
726         }
727 
728         overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
729         if (overrun)
730                 goto xfer_abort;
731 
732         /* clear the interrupt */
733         writew(status, devpriv->las0 + LAS0_CLEAR);
734         readw(devpriv->las0 + LAS0_CLEAR);
735         return IRQ_HANDLED;
736 
737 xfer_abort:
738         writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
739         s->async->events |= COMEDI_CB_ERROR;
740         devpriv->ai_count = 0;  /* stop and don't transfer any more */
741         /* fall into xfer_done */
742 
743 xfer_done:
744         /* pacer stop source: SOFTWARE */
745         writel(0, devpriv->las0 + LAS0_PACER_STOP);
746         writel(0, devpriv->las0 + LAS0_PACER);  /* stop pacer */
747         writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
748         writew(0, devpriv->las0 + LAS0_IT);
749 
750         if (devpriv->ai_count > 0) {    /* there shouldn't be anything left */
751                 fifo_status = readl(devpriv->las0 + LAS0_ADC);
752                 ai_read_dregs(dev, s);  /* read anything left in FIFO */
753         }
754 
755         s->async->events |= COMEDI_CB_EOA;      /* signal end to comedi */
756         comedi_event(dev, s);
757 
758         /* clear the interrupt */
759         status = readw(devpriv->las0 + LAS0_IT);
760         writew(status, devpriv->las0 + LAS0_CLEAR);
761         readw(devpriv->las0 + LAS0_CLEAR);
762 
763         fifo_status = readl(devpriv->las0 + LAS0_ADC);
764         overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
765 
766         return IRQ_HANDLED;
767 }
768 
769 /*
770   cmdtest tests a particular command to see if it is valid.
771   Using the cmdtest ioctl, a user can create a valid cmd
772   and then have it executed by the cmd ioctl (asynchronously).
773 
774   cmdtest returns 1,2,3,4 or 0, depending on which tests
775   the command passes.
776 */
777 
778 static int rtd_ai_cmdtest(struct comedi_device *dev,
779                           struct comedi_subdevice *s, struct comedi_cmd *cmd)
780 {
781         int err = 0;
782         int tmp;
783 
784         /* Step 1 : check if triggers are trivially valid */
785 
786         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
787         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
788                                         TRIG_TIMER | TRIG_EXT);
789         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
790         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
791         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
792 
793         if (err)
794                 return 1;
795 
796         /* Step 2a : make sure trigger sources are unique */
797 
798         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
799         err |= cfc_check_trigger_is_unique(cmd->convert_src);
800         err |= cfc_check_trigger_is_unique(cmd->stop_src);
801 
802         /* Step 2b : and mutually compatible */
803 
804         if (err)
805                 return 2;
806 
807         /* Step 3: check if arguments are trivially valid */
808 
809         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
810 
811         if (cmd->scan_begin_src == TRIG_TIMER) {
812                 /* Note: these are time periods, not actual rates */
813                 if (1 == cmd->chanlist_len) {   /* no scanning */
814                         if (cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
815                                                       RTD_MAX_SPEED_1)) {
816                                 rtd_ns_to_timer(&cmd->scan_begin_arg,
817                                                 TRIG_ROUND_UP);
818                                 err |= -EINVAL;
819                         }
820                         if (cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
821                                                       RTD_MIN_SPEED_1)) {
822                                 rtd_ns_to_timer(&cmd->scan_begin_arg,
823                                                 TRIG_ROUND_DOWN);
824                                 err |= -EINVAL;
825                         }
826                 } else {
827                         if (cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
828                                                       RTD_MAX_SPEED)) {
829                                 rtd_ns_to_timer(&cmd->scan_begin_arg,
830                                                 TRIG_ROUND_UP);
831                                 err |= -EINVAL;
832                         }
833                         if (cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
834                                                       RTD_MIN_SPEED)) {
835                                 rtd_ns_to_timer(&cmd->scan_begin_arg,
836                                                 TRIG_ROUND_DOWN);
837                                 err |= -EINVAL;
838                         }
839                 }
840         } else {
841                 /* external trigger */
842                 /* should be level/edge, hi/lo specification here */
843                 /* should specify multiple external triggers */
844                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9);
845         }
846 
847         if (cmd->convert_src == TRIG_TIMER) {
848                 if (1 == cmd->chanlist_len) {   /* no scanning */
849                         if (cfc_check_trigger_arg_min(&cmd->convert_arg,
850                                                       RTD_MAX_SPEED_1)) {
851                                 rtd_ns_to_timer(&cmd->convert_arg,
852                                                 TRIG_ROUND_UP);
853                                 err |= -EINVAL;
854                         }
855                         if (cfc_check_trigger_arg_max(&cmd->convert_arg,
856                                                       RTD_MIN_SPEED_1)) {
857                                 rtd_ns_to_timer(&cmd->convert_arg,
858                                                 TRIG_ROUND_DOWN);
859                                 err |= -EINVAL;
860                         }
861                 } else {
862                         if (cfc_check_trigger_arg_min(&cmd->convert_arg,
863                                                       RTD_MAX_SPEED)) {
864                                 rtd_ns_to_timer(&cmd->convert_arg,
865                                                 TRIG_ROUND_UP);
866                                 err |= -EINVAL;
867                         }
868                         if (cfc_check_trigger_arg_max(&cmd->convert_arg,
869                                                       RTD_MIN_SPEED)) {
870                                 rtd_ns_to_timer(&cmd->convert_arg,
871                                                 TRIG_ROUND_DOWN);
872                                 err |= -EINVAL;
873                         }
874                 }
875         } else {
876                 /* external trigger */
877                 /* see above */
878                 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 9);
879         }
880 
881         if (cmd->stop_src == TRIG_COUNT) {
882                 /* TODO check for rounding error due to counter wrap */
883         } else {
884                 /* TRIG_NONE */
885                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
886         }
887 
888         if (err)
889                 return 3;
890 
891 
892         /* step 4: fix up any arguments */
893 
894         if (cmd->chanlist_len > RTD_MAX_CHANLIST) {
895                 cmd->chanlist_len = RTD_MAX_CHANLIST;
896                 err++;
897         }
898         if (cmd->scan_begin_src == TRIG_TIMER) {
899                 tmp = cmd->scan_begin_arg;
900                 rtd_ns_to_timer(&cmd->scan_begin_arg,
901                                 cmd->flags & TRIG_ROUND_MASK);
902                 if (tmp != cmd->scan_begin_arg)
903                         err++;
904 
905         }
906         if (cmd->convert_src == TRIG_TIMER) {
907                 tmp = cmd->convert_arg;
908                 rtd_ns_to_timer(&cmd->convert_arg,
909                                 cmd->flags & TRIG_ROUND_MASK);
910                 if (tmp != cmd->convert_arg)
911                         err++;
912 
913                 if (cmd->scan_begin_src == TRIG_TIMER
914                     && (cmd->scan_begin_arg
915                         < (cmd->convert_arg * cmd->scan_end_arg))) {
916                         cmd->scan_begin_arg =
917                             cmd->convert_arg * cmd->scan_end_arg;
918                         err++;
919                 }
920         }
921 
922         if (err)
923                 return 4;
924 
925         return 0;
926 }
927 
928 /*
929   Execute a analog in command with many possible triggering options.
930   The data get stored in the async structure of the subdevice.
931   This is usually done by an interrupt handler.
932   Userland gets to the data using read calls.
933 */
934 static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
935 {
936         struct rtd_private *devpriv = dev->private;
937         struct comedi_cmd *cmd = &s->async->cmd;
938         int timer;
939 
940         /* stop anything currently running */
941         /* pacer stop source: SOFTWARE */
942         writel(0, devpriv->las0 + LAS0_PACER_STOP);
943         writel(0, devpriv->las0 + LAS0_PACER);  /* stop pacer */
944         writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
945         writew(0, devpriv->las0 + LAS0_IT);
946         writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
947         writel(0, devpriv->las0 + LAS0_OVERRUN);
948 
949         /* start configuration */
950         /* load channel list and reset CGT */
951         rtd_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
952 
953         /* setup the common case and override if needed */
954         if (cmd->chanlist_len > 1) {
955                 /* pacer start source: SOFTWARE */
956                 writel(0, devpriv->las0 + LAS0_PACER_START);
957                 /* burst trigger source: PACER */
958                 writel(1, devpriv->las0 + LAS0_BURST_START);
959                 /* ADC conversion trigger source: BURST */
960                 writel(2, devpriv->las0 + LAS0_ADC_CONVERSION);
961         } else {                /* single channel */
962                 /* pacer start source: SOFTWARE */
963                 writel(0, devpriv->las0 + LAS0_PACER_START);
964                 /* ADC conversion trigger source: PACER */
965                 writel(1, devpriv->las0 + LAS0_ADC_CONVERSION);
966         }
967         writel((devpriv->fifosz / 2 - 1) & 0xffff, devpriv->las0 + LAS0_ACNT);
968 
969         if (TRIG_TIMER == cmd->scan_begin_src) {
970                 /* scan_begin_arg is in nanoseconds */
971                 /* find out how many samples to wait before transferring */
972                 if (cmd->flags & TRIG_WAKE_EOS) {
973                         /*
974                          * this may generate un-sustainable interrupt rates
975                          * the application is responsible for doing the
976                          * right thing
977                          */
978                         devpriv->xfer_count = cmd->chanlist_len;
979                         devpriv->flags |= SEND_EOS;
980                 } else {
981                         /* arrange to transfer data periodically */
982                         devpriv->xfer_count =
983                             (TRANS_TARGET_PERIOD * cmd->chanlist_len) /
984                             cmd->scan_begin_arg;
985                         if (devpriv->xfer_count < cmd->chanlist_len) {
986                                 /* transfer after each scan (and avoid 0) */
987                                 devpriv->xfer_count = cmd->chanlist_len;
988                         } else {        /* make a multiple of scan length */
989                                 devpriv->xfer_count =
990                                     (devpriv->xfer_count +
991                                      cmd->chanlist_len - 1)
992                                     / cmd->chanlist_len;
993                                 devpriv->xfer_count *= cmd->chanlist_len;
994                         }
995                         devpriv->flags |= SEND_EOS;
996                 }
997                 if (devpriv->xfer_count >= (devpriv->fifosz / 2)) {
998                         /* out of counter range, use 1/2 fifo instead */
999                         devpriv->xfer_count = 0;
1000                         devpriv->flags &= ~SEND_EOS;
1001                 } else {
1002                         /* interrupt for each transfer */
1003                         writel((devpriv->xfer_count - 1) & 0xffff,
1004                                 devpriv->las0 + LAS0_ACNT);
1005                 }
1006         } else {                /* unknown timing, just use 1/2 FIFO */
1007                 devpriv->xfer_count = 0;
1008                 devpriv->flags &= ~SEND_EOS;
1009         }
1010         /* pacer clock source: INTERNAL 8MHz */
1011         writel(1, devpriv->las0 + LAS0_PACER_SELECT);
1012         /* just interrupt, don't stop */
1013         writel(1, devpriv->las0 + LAS0_ACNT_STOP_ENABLE);
1014 
1015         /* BUG??? these look like enumerated values, but they are bit fields */
1016 
1017         /* First, setup when to stop */
1018         switch (cmd->stop_src) {
1019         case TRIG_COUNT:        /* stop after N scans */
1020                 devpriv->ai_count = cmd->stop_arg * cmd->chanlist_len;
1021                 if ((devpriv->xfer_count > 0)
1022                     && (devpriv->xfer_count > devpriv->ai_count)) {
1023                         devpriv->xfer_count = devpriv->ai_count;
1024                 }
1025                 break;
1026 
1027         case TRIG_NONE: /* stop when cancel is called */
1028                 devpriv->ai_count = -1; /* read forever */
1029                 break;
1030         }
1031 
1032         /* Scan timing */
1033         switch (cmd->scan_begin_src) {
1034         case TRIG_TIMER:        /* periodic scanning */
1035                 timer = rtd_ns_to_timer(&cmd->scan_begin_arg,
1036                                         TRIG_ROUND_NEAREST);
1037                 /* set PACER clock */
1038                 writel(timer & 0xffffff, devpriv->las0 + LAS0_PCLK);
1039 
1040                 break;
1041 
1042         case TRIG_EXT:
1043                 /* pacer start source: EXTERNAL */
1044                 writel(1, devpriv->las0 + LAS0_PACER_START);
1045                 break;
1046         }
1047 
1048         /* Sample timing within a scan */
1049         switch (cmd->convert_src) {
1050         case TRIG_TIMER:        /* periodic */
1051                 if (cmd->chanlist_len > 1) {
1052                         /* only needed for multi-channel */
1053                         timer = rtd_ns_to_timer(&cmd->convert_arg,
1054                                                 TRIG_ROUND_NEAREST);
1055                         /* setup BURST clock */
1056                         writel(timer & 0x3ff, devpriv->las0 + LAS0_BCLK);
1057                 }
1058 
1059                 break;
1060 
1061         case TRIG_EXT:          /* external */
1062                 /* burst trigger source: EXTERNAL */
1063                 writel(2, devpriv->las0 + LAS0_BURST_START);
1064                 break;
1065         }
1066         /* end configuration */
1067 
1068         /* This doesn't seem to work.  There is no way to clear an interrupt
1069            that the priority controller has queued! */
1070         writew(~0, devpriv->las0 + LAS0_CLEAR);
1071         readw(devpriv->las0 + LAS0_CLEAR);
1072 
1073         /* TODO: allow multiple interrupt sources */
1074         if (devpriv->xfer_count > 0) {  /* transfer every N samples */
1075                 writew(IRQM_ADC_ABOUT_CNT, devpriv->las0 + LAS0_IT);
1076         } else {                /* 1/2 FIFO transfers */
1077                 writew(IRQM_ADC_ABOUT_CNT, devpriv->las0 + LAS0_IT);
1078         }
1079 
1080         /* BUG: start_src is ASSUMED to be TRIG_NOW */
1081         /* BUG? it seems like things are running before the "start" */
1082         readl(devpriv->las0 + LAS0_PACER);      /* start pacer */
1083         return 0;
1084 }
1085 
1086 /*
1087   Stop a running data acquisition.
1088 */
1089 static int rtd_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1090 {
1091         struct rtd_private *devpriv = dev->private;
1092         u32 overrun;
1093         u16 status;
1094 
1095         /* pacer stop source: SOFTWARE */
1096         writel(0, devpriv->las0 + LAS0_PACER_STOP);
1097         writel(0, devpriv->las0 + LAS0_PACER);  /* stop pacer */
1098         writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
1099         writew(0, devpriv->las0 + LAS0_IT);
1100         devpriv->ai_count = 0;  /* stop and don't transfer any more */
1101         status = readw(devpriv->las0 + LAS0_IT);
1102         overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
1103         return 0;
1104 }
1105 
1106 static int rtd_ao_eoc(struct comedi_device *dev,
1107                       struct comedi_subdevice *s,
1108                       struct comedi_insn *insn,
1109                       unsigned long context)
1110 {
1111         struct rtd_private *devpriv = dev->private;
1112         unsigned int chan = CR_CHAN(insn->chanspec);
1113         unsigned int bit = (chan == 0) ? FS_DAC1_NOT_EMPTY : FS_DAC2_NOT_EMPTY;
1114         unsigned int status;
1115 
1116         status = readl(devpriv->las0 + LAS0_ADC);
1117         if (status & bit)
1118                 return 0;
1119         return -EBUSY;
1120 }
1121 
1122 static int rtd_ao_winsn(struct comedi_device *dev,
1123                         struct comedi_subdevice *s, struct comedi_insn *insn,
1124                         unsigned int *data)
1125 {
1126         struct rtd_private *devpriv = dev->private;
1127         int i;
1128         int chan = CR_CHAN(insn->chanspec);
1129         int range = CR_RANGE(insn->chanspec);
1130         int ret;
1131 
1132         /* Configure the output range (table index matches the range values) */
1133         writew(range & 7, devpriv->las0 +
1134                 ((chan == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL));
1135 
1136         /* Writing a list of values to an AO channel is probably not
1137          * very useful, but that's how the interface is defined. */
1138         for (i = 0; i < insn->n; ++i) {
1139                 int val = data[i] << 3;
1140 
1141                 /* VERIFY: comedi range and offset conversions */
1142 
1143                 if ((range > 1) /* bipolar */
1144                     && (data[i] < 2048)) {
1145                         /* offset and sign extend */
1146                         val = (((int)data[i]) - 2048) << 3;
1147                 } else {        /* unipolor */
1148                         val = data[i] << 3;
1149                 }
1150 
1151                 /* a typical programming sequence */
1152                 writew(val, devpriv->las1 +
1153                         ((chan == 0) ? LAS1_DAC1_FIFO : LAS1_DAC2_FIFO));
1154                 writew(0, devpriv->las0 +
1155                         ((chan == 0) ? LAS0_DAC1 : LAS0_DAC2));
1156 
1157                 devpriv->ao_readback[chan] = data[i];
1158 
1159                 ret = comedi_timeout(dev, s, insn, rtd_ao_eoc, 0);
1160                 if (ret)
1161                         return ret;
1162         }
1163 
1164         /* return the number of samples read/written */
1165         return i;
1166 }
1167 
1168 /* AO subdevices should have a read insn as well as a write insn.
1169  * Usually this means copying a value stored in devpriv. */
1170 static int rtd_ao_rinsn(struct comedi_device *dev,
1171                         struct comedi_subdevice *s, struct comedi_insn *insn,
1172                         unsigned int *data)
1173 {
1174         struct rtd_private *devpriv = dev->private;
1175         int i;
1176         int chan = CR_CHAN(insn->chanspec);
1177 
1178         for (i = 0; i < insn->n; i++)
1179                 data[i] = devpriv->ao_readback[chan];
1180 
1181 
1182         return i;
1183 }
1184 
1185 static int rtd_dio_insn_bits(struct comedi_device *dev,
1186                              struct comedi_subdevice *s,
1187                              struct comedi_insn *insn,
1188                              unsigned int *data)
1189 {
1190         struct rtd_private *devpriv = dev->private;
1191 
1192         if (comedi_dio_update_state(s, data))
1193                 writew(s->state & 0xff, devpriv->las0 + LAS0_DIO0);
1194 
1195         data[1] = readw(devpriv->las0 + LAS0_DIO0) & 0xff;
1196 
1197         return insn->n;
1198 }
1199 
1200 static int rtd_dio_insn_config(struct comedi_device *dev,
1201                                struct comedi_subdevice *s,
1202                                struct comedi_insn *insn,
1203                                unsigned int *data)
1204 {
1205         struct rtd_private *devpriv = dev->private;
1206         int ret;
1207 
1208         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
1209         if (ret)
1210                 return ret;
1211 
1212         /* TODO support digital match interrupts and strobes */
1213 
1214         /* set direction */
1215         writew(0x01, devpriv->las0 + LAS0_DIO_STATUS);
1216         writew(s->io_bits & 0xff, devpriv->las0 + LAS0_DIO0_CTRL);
1217 
1218         /* clear interrupts */
1219         writew(0x00, devpriv->las0 + LAS0_DIO_STATUS);
1220 
1221         /* port1 can only be all input or all output */
1222 
1223         /* there are also 2 user input lines and 2 user output lines */
1224 
1225         return insn->n;
1226 }
1227 
1228 static void rtd_reset(struct comedi_device *dev)
1229 {
1230         struct rtd_private *devpriv = dev->private;
1231 
1232         writel(0, devpriv->las0 + LAS0_BOARD_RESET);
1233         udelay(100);            /* needed? */
1234         writel(0, devpriv->lcfg + PLX_INTRCS_REG);
1235         writew(0, devpriv->las0 + LAS0_IT);
1236         writew(~0, devpriv->las0 + LAS0_CLEAR);
1237         readw(devpriv->las0 + LAS0_CLEAR);
1238 }
1239 
1240 /*
1241  * initialize board, per RTD spec
1242  * also, initialize shadow registers
1243  */
1244 static void rtd_init_board(struct comedi_device *dev)
1245 {
1246         struct rtd_private *devpriv = dev->private;
1247 
1248         rtd_reset(dev);
1249 
1250         writel(0, devpriv->las0 + LAS0_OVERRUN);
1251         writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
1252         writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
1253         writel(0, devpriv->las0 + LAS0_DAC1_RESET);
1254         writel(0, devpriv->las0 + LAS0_DAC2_RESET);
1255         /* clear digital IO fifo */
1256         writew(0, devpriv->las0 + LAS0_DIO_STATUS);
1257         writeb((0 << 6) | 0x30, devpriv->las0 + LAS0_UTC_CTRL);
1258         writeb((1 << 6) | 0x30, devpriv->las0 + LAS0_UTC_CTRL);
1259         writeb((2 << 6) | 0x30, devpriv->las0 + LAS0_UTC_CTRL);
1260         writeb((3 << 6) | 0x00, devpriv->las0 + LAS0_UTC_CTRL);
1261         /* TODO: set user out source ??? */
1262 }
1263 
1264 /* The RTD driver does this */
1265 static void rtd_pci_latency_quirk(struct comedi_device *dev,
1266                                   struct pci_dev *pcidev)
1267 {
1268         unsigned char pci_latency;
1269 
1270         pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency);
1271         if (pci_latency < 32) {
1272                 dev_info(dev->class_dev,
1273                         "PCI latency changed from %d to %d\n",
1274                         pci_latency, 32);
1275                 pci_write_config_byte(pcidev, PCI_LATENCY_TIMER, 32);
1276         }
1277 }
1278 
1279 static int rtd_auto_attach(struct comedi_device *dev,
1280                            unsigned long context)
1281 {
1282         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1283         const struct rtd_boardinfo *board = NULL;
1284         struct rtd_private *devpriv;
1285         struct comedi_subdevice *s;
1286         int ret;
1287 
1288         if (context < ARRAY_SIZE(rtd520Boards))
1289                 board = &rtd520Boards[context];
1290         if (!board)
1291                 return -ENODEV;
1292         dev->board_ptr = board;
1293         dev->board_name = board->name;
1294 
1295         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
1296         if (!devpriv)
1297                 return -ENOMEM;
1298 
1299         ret = comedi_pci_enable(dev);
1300         if (ret)
1301                 return ret;
1302 
1303         devpriv->las0 = pci_ioremap_bar(pcidev, 2);
1304         devpriv->las1 = pci_ioremap_bar(pcidev, 3);
1305         devpriv->lcfg = pci_ioremap_bar(pcidev, 0);
1306         if (!devpriv->las0 || !devpriv->las1 || !devpriv->lcfg)
1307                 return -ENOMEM;
1308 
1309         rtd_pci_latency_quirk(dev, pcidev);
1310 
1311         if (pcidev->irq) {
1312                 ret = request_irq(pcidev->irq, rtd_interrupt, IRQF_SHARED,
1313                                   dev->board_name, dev);
1314                 if (ret == 0)
1315                         dev->irq = pcidev->irq;
1316         }
1317 
1318         ret = comedi_alloc_subdevices(dev, 4);
1319         if (ret)
1320                 return ret;
1321 
1322         s = &dev->subdevices[0];
1323         /* analog input subdevice */
1324         s->type         = COMEDI_SUBD_AI;
1325         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF;
1326         s->n_chan       = 16;
1327         s->maxdata      = 0x0fff;
1328         s->range_table  = board->ai_range;
1329         s->len_chanlist = RTD_MAX_CHANLIST;
1330         s->insn_read    = rtd_ai_rinsn;
1331         if (dev->irq) {
1332                 dev->read_subdev = s;
1333                 s->subdev_flags |= SDF_CMD_READ;
1334                 s->do_cmd       = rtd_ai_cmd;
1335                 s->do_cmdtest   = rtd_ai_cmdtest;
1336                 s->cancel       = rtd_ai_cancel;
1337         }
1338 
1339         s = &dev->subdevices[1];
1340         /* analog output subdevice */
1341         s->type         = COMEDI_SUBD_AO;
1342         s->subdev_flags = SDF_WRITABLE;
1343         s->n_chan       = 2;
1344         s->maxdata      = 0x0fff;
1345         s->range_table  = &rtd_ao_range;
1346         s->insn_write   = rtd_ao_winsn;
1347         s->insn_read    = rtd_ao_rinsn;
1348 
1349         s = &dev->subdevices[2];
1350         /* digital i/o subdevice */
1351         s->type         = COMEDI_SUBD_DIO;
1352         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1353         /* we only support port 0 right now.  Ignoring port 1 and user IO */
1354         s->n_chan       = 8;
1355         s->maxdata      = 1;
1356         s->range_table  = &range_digital;
1357         s->insn_bits    = rtd_dio_insn_bits;
1358         s->insn_config  = rtd_dio_insn_config;
1359 
1360         /* timer/counter subdevices (not currently supported) */
1361         s = &dev->subdevices[3];
1362         s->type         = COMEDI_SUBD_COUNTER;
1363         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1364         s->n_chan       = 3;
1365         s->maxdata      = 0xffff;
1366 
1367         rtd_init_board(dev);
1368 
1369         ret = rtd520_probe_fifo_depth(dev);
1370         if (ret < 0)
1371                 return ret;
1372         devpriv->fifosz = ret;
1373 
1374         if (dev->irq)
1375                 writel(ICS_PIE | ICS_PLIE, devpriv->lcfg + PLX_INTRCS_REG);
1376 
1377         return 0;
1378 }
1379 
1380 static void rtd_detach(struct comedi_device *dev)
1381 {
1382         struct rtd_private *devpriv = dev->private;
1383 
1384         if (devpriv) {
1385                 /* Shut down any board ops by resetting it */
1386                 if (devpriv->las0 && devpriv->lcfg)
1387                         rtd_reset(dev);
1388                 if (dev->irq) {
1389                         writel(readl(devpriv->lcfg + PLX_INTRCS_REG) &
1390                                 ~(ICS_PLIE | ICS_DMA0_E | ICS_DMA1_E),
1391                                 devpriv->lcfg + PLX_INTRCS_REG);
1392                         free_irq(dev->irq, dev);
1393                 }
1394                 if (devpriv->las0)
1395                         iounmap(devpriv->las0);
1396                 if (devpriv->las1)
1397                         iounmap(devpriv->las1);
1398                 if (devpriv->lcfg)
1399                         iounmap(devpriv->lcfg);
1400         }
1401         comedi_pci_disable(dev);
1402 }
1403 
1404 static struct comedi_driver rtd520_driver = {
1405         .driver_name    = "rtd520",
1406         .module         = THIS_MODULE,
1407         .auto_attach    = rtd_auto_attach,
1408         .detach         = rtd_detach,
1409 };
1410 
1411 static int rtd520_pci_probe(struct pci_dev *dev,
1412                             const struct pci_device_id *id)
1413 {
1414         return comedi_pci_auto_config(dev, &rtd520_driver, id->driver_data);
1415 }
1416 
1417 static const struct pci_device_id rtd520_pci_table[] = {
1418         { PCI_VDEVICE(RTD, 0x7520), BOARD_DM7520 },
1419         { PCI_VDEVICE(RTD, 0x4520), BOARD_PCI4520 },
1420         { 0 }
1421 };
1422 MODULE_DEVICE_TABLE(pci, rtd520_pci_table);
1423 
1424 static struct pci_driver rtd520_pci_driver = {
1425         .name           = "rtd520",
1426         .id_table       = rtd520_pci_table,
1427         .probe          = rtd520_pci_probe,
1428         .remove         = comedi_pci_auto_unconfig,
1429 };
1430 module_comedi_pci_driver(rtd520_driver, rtd520_pci_driver);
1431 
1432 MODULE_AUTHOR("Comedi http://www.comedi.org");
1433 MODULE_DESCRIPTION("Comedi low-level driver");
1434 MODULE_LICENSE("GPL");
1435 

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