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Linux/drivers/staging/comedi/drivers/ni_pcimio.c

  1 /*
  2     comedi/drivers/ni_pcimio.c
  3     Hardware driver for NI PCI-MIO E series cards
  4 
  5     COMEDI - Linux Control and Measurement Device Interface
  6     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  7 
  8     This program is free software; you can redistribute it and/or modify
  9     it under the terms of the GNU General Public License as published by
 10     the Free Software Foundation; either version 2 of the License, or
 11     (at your option) any later version.
 12 
 13     This program is distributed in the hope that it will be useful,
 14     but WITHOUT ANY WARRANTY; without even the implied warranty of
 15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16     GNU General Public License for more details.
 17 */
 18 /*
 19 Driver: ni_pcimio
 20 Description: National Instruments PCI-MIO-E series and M series (all boards)
 21 Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
 22   Herman Bruyninckx, Terry Barnaby
 23 Status: works
 24 Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
 25   PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
 26   PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
 27   PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
 28   PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224,
 29   PCI-6225, PXI-6225, PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PXIe-6251,
 30   PCI-6254, PCI-6259, PCIe-6259,
 31   PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
 32   PCI-6711, PXI-6711, PCI-6713, PXI-6713,
 33   PXI-6071E, PCI-6070E, PXI-6070E,
 34   PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
 35   PCI-6143, PXI-6143
 36 Updated: Mon, 09 Jan 2012 14:52:48 +0000
 37 
 38 These boards are almost identical to the AT-MIO E series, except that
 39 they use the PCI bus instead of ISA (i.e., AT).  See the notes for
 40 the ni_atmio.o driver for additional information about these boards.
 41 
 42 Autocalibration is supported on many of the devices, using the
 43 comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
 44 M-Series boards do analog input and analog output calibration entirely
 45 in software. The software calibration corrects
 46 the analog input for offset, gain and
 47 nonlinearity.  The analog outputs are corrected for offset and gain.
 48 See the comedilib documentation on comedi_get_softcal_converter() for
 49 more information.
 50 
 51 By default, the driver uses DMA to transfer analog input data to
 52 memory.  When DMA is enabled, not all triggering features are
 53 supported.
 54 
 55 Digital I/O may not work on 673x.
 56 
 57 Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
 58 With this board all of the convertors perform one simultaineous sample during
 59 a scan interval. The period for a scan is used for the convert time in a
 60 Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
 61 
 62 The RTSI trigger bus is supported on these cards on
 63 subdevice 10. See the comedilib documentation for details.
 64 
 65 Information (number of channels, bits, etc.) for some devices may be
 66 incorrect.  Please check this and submit a bug if there are problems
 67 for your device.
 68 
 69 SCXI is probably broken for m-series boards.
 70 
 71 Bugs:
 72  - When DMA is enabled, COMEDI_EV_CONVERT does
 73    not work correctly.
 74 
 75 */
 76 /*
 77         The PCI-MIO E series driver was originally written by
 78         Tomasz Motylewski <...>, and ported to comedi by ds.
 79 
 80         References:
 81 
 82            341079b.pdf  PCI E Series Register-Level Programmer Manual
 83            340934b.pdf  DAQ-STC reference manual
 84 
 85            322080b.pdf  6711/6713/6715 User Manual
 86 
 87            320945c.pdf  PCI E Series User Manual
 88            322138a.pdf  PCI-6052E and DAQPad-6052E User Manual
 89 
 90         ISSUES:
 91 
 92         need to deal with external reference for DAC, and other DAC
 93         properties in board properties
 94 
 95         deal with at-mio-16de-10 revision D to N changes, etc.
 96 
 97         need to add other CALDAC type
 98 
 99         need to slow down DAC loading.  I don't trust NI's claim that
100         two writes to the PCI bus slows IO enough.  I would prefer to
101         use udelay().  Timing specs: (clock)
102                 AD8522          30ns
103                 DAC8043         120ns
104                 DAC8800         60ns
105                 MB88341         ?
106 
107 */
108 
109 #include <linux/module.h>
110 #include <linux/delay.h>
111 
112 #include "../comedidev.h"
113 
114 #include <asm/byteorder.h>
115 
116 #include "ni_stc.h"
117 #include "mite.h"
118 
119 #define PCIDMA
120 
121 #define PCIMIO 1
122 #undef ATMIO
123 
124 #define MAX_N_CALDACS (16+16+2)
125 
126 #define DRV_NAME "ni_pcimio"
127 
128 /* These are not all the possible ao ranges for 628x boards.
129  They can do OFFSET +- REFERENCE where OFFSET can be
130  0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
131  be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>.  That's
132  63 different possibilities.  An AO channel
133  can not act as it's own OFFSET or REFERENCE.
134 */
135 static const struct comedi_lrange range_ni_M_628x_ao = {
136         8, {
137                 BIP_RANGE(10),
138                 BIP_RANGE(5),
139                 BIP_RANGE(2),
140                 BIP_RANGE(1),
141                 RANGE(-5, 15),
142                 UNI_RANGE(10),
143                 RANGE(3, 7),
144                 RANGE(4, 6),
145                 RANGE_ext(-1, 1)
146         }
147 };
148 
149 static const struct comedi_lrange range_ni_M_625x_ao = {
150         3, {
151                 BIP_RANGE(10),
152                 BIP_RANGE(5),
153                 RANGE_ext(-1, 1)
154         }
155 };
156 
157 enum ni_pcimio_boardid {
158         BOARD_PCIMIO_16XE_50,
159         BOARD_PCIMIO_16XE_10,
160         BOARD_PCI6014,
161         BOARD_PXI6030E,
162         BOARD_PCIMIO_16E_1,
163         BOARD_PCIMIO_16E_4,
164         BOARD_PXI6040E,
165         BOARD_PCI6031E,
166         BOARD_PCI6032E,
167         BOARD_PCI6033E,
168         BOARD_PCI6071E,
169         BOARD_PCI6023E,
170         BOARD_PCI6024E,
171         BOARD_PCI6025E,
172         BOARD_PXI6025E,
173         BOARD_PCI6034E,
174         BOARD_PCI6035E,
175         BOARD_PCI6052E,
176         BOARD_PCI6110,
177         BOARD_PCI6111,
178         /* BOARD_PCI6115, */
179         /* BOARD_PXI6115, */
180         BOARD_PCI6711,
181         BOARD_PXI6711,
182         BOARD_PCI6713,
183         BOARD_PXI6713,
184         BOARD_PCI6731,
185         /* BOARD_PXI6731, */
186         BOARD_PCI6733,
187         BOARD_PXI6733,
188         BOARD_PXI6071E,
189         BOARD_PXI6070E,
190         BOARD_PXI6052E,
191         BOARD_PXI6031E,
192         BOARD_PCI6036E,
193         BOARD_PCI6220,
194         BOARD_PCI6221,
195         BOARD_PCI6221_37PIN,
196         BOARD_PCI6224,
197         BOARD_PXI6224,
198         BOARD_PCI6225,
199         BOARD_PXI6225,
200         BOARD_PCI6229,
201         BOARD_PCI6250,
202         BOARD_PCI6251,
203         BOARD_PCIE6251,
204         BOARD_PXIE6251,
205         BOARD_PCI6254,
206         BOARD_PCI6259,
207         BOARD_PCIE6259,
208         BOARD_PCI6280,
209         BOARD_PCI6281,
210         BOARD_PXI6281,
211         BOARD_PCI6284,
212         BOARD_PCI6289,
213         BOARD_PCI6143,
214         BOARD_PXI6143,
215 };
216 
217 static const struct ni_board_struct ni_boards[] = {
218         [BOARD_PCIMIO_16XE_50] = {
219                 .name           = "pci-mio-16xe-50",
220                 .n_adchan       = 16,
221                 .adbits         = 16,
222                 .ai_fifo_depth  = 2048,
223                 .alwaysdither   = 1,
224                 .gainlkup       = ai_gain_8,
225                 .ai_speed       = 50000,
226                 .n_aochan       = 2,
227                 .aobits         = 12,
228                 .ao_range_table = &range_bipolar10,
229                 .ao_speed       = 50000,
230                 .num_p0_dio_channels = 8,
231                 .caldac         = { dac8800, dac8043 },
232         },
233         [BOARD_PCIMIO_16XE_10] = {
234                 .name           = "pci-mio-16xe-10",    /*  aka pci-6030E */
235                 .n_adchan       = 16,
236                 .adbits         = 16,
237                 .ai_fifo_depth  = 512,
238                 .alwaysdither   = 1,
239                 .gainlkup       = ai_gain_14,
240                 .ai_speed       = 10000,
241                 .n_aochan       = 2,
242                 .aobits         = 16,
243                 .ao_fifo_depth  = 2048,
244                 .ao_range_table = &range_ni_E_ao_ext,
245                 .ao_unipolar    = 1,
246                 .ao_speed       = 10000,
247                 .num_p0_dio_channels = 8,
248                 .caldac         = { dac8800, dac8043, ad8522 },
249         },
250         [BOARD_PCI6014] = {
251                 .name           = "pci-6014",
252                 .n_adchan       = 16,
253                 .adbits         = 16,
254                 .ai_fifo_depth  = 512,
255                 .alwaysdither   = 1,
256                 .gainlkup       = ai_gain_4,
257                 .ai_speed       = 5000,
258                 .n_aochan       = 2,
259                 .aobits         = 16,
260                 .ao_range_table = &range_bipolar10,
261                 .ao_speed       = 100000,
262                 .num_p0_dio_channels = 8,
263                 .caldac         = { ad8804_debug },
264         },
265         [BOARD_PXI6030E] = {
266                 .name           = "pxi-6030e",
267                 .n_adchan       = 16,
268                 .adbits         = 16,
269                 .ai_fifo_depth  = 512,
270                 .alwaysdither   = 1,
271                 .gainlkup       = ai_gain_14,
272                 .ai_speed       = 10000,
273                 .n_aochan       = 2,
274                 .aobits         = 16,
275                 .ao_fifo_depth  = 2048,
276                 .ao_range_table = &range_ni_E_ao_ext,
277                 .ao_unipolar    = 1,
278                 .ao_speed       = 10000,
279                 .num_p0_dio_channels = 8,
280                 .caldac         = { dac8800, dac8043, ad8522 },
281         },
282         [BOARD_PCIMIO_16E_1] = {
283                 .name           = "pci-mio-16e-1",      /* aka pci-6070e */
284                 .n_adchan       = 16,
285                 .adbits         = 12,
286                 .ai_fifo_depth  = 512,
287                 .gainlkup       = ai_gain_16,
288                 .ai_speed       = 800,
289                 .n_aochan       = 2,
290                 .aobits         = 12,
291                 .ao_fifo_depth  = 2048,
292                 .ao_range_table = &range_ni_E_ao_ext,
293                 .ao_unipolar    = 1,
294                 .ao_speed       = 1000,
295                 .num_p0_dio_channels = 8,
296                 .caldac         = { mb88341 },
297         },
298         [BOARD_PCIMIO_16E_4] = {
299                 .name           = "pci-mio-16e-4",      /* aka pci-6040e */
300                 .n_adchan       = 16,
301                 .adbits         = 12,
302                 .ai_fifo_depth  = 512,
303                 .gainlkup       = ai_gain_16,
304                 /*
305                  * there have been reported problems with
306                  * full speed on this board
307                  */
308                 .ai_speed       = 2000,
309                 .n_aochan       = 2,
310                 .aobits         = 12,
311                 .ao_fifo_depth  = 512,
312                 .ao_range_table = &range_ni_E_ao_ext,
313                 .ao_unipolar    = 1,
314                 .ao_speed       = 1000,
315                 .num_p0_dio_channels = 8,
316                 .caldac         = { ad8804_debug },     /* doc says mb88341 */
317         },
318         [BOARD_PXI6040E] = {
319                 .name           = "pxi-6040e",
320                 .n_adchan       = 16,
321                 .adbits         = 12,
322                 .ai_fifo_depth  = 512,
323                 .gainlkup       = ai_gain_16,
324                 .ai_speed       = 2000,
325                 .n_aochan       = 2,
326                 .aobits         = 12,
327                 .ao_fifo_depth  = 512,
328                 .ao_range_table = &range_ni_E_ao_ext,
329                 .ao_unipolar    = 1,
330                 .ao_speed       = 1000,
331                 .num_p0_dio_channels = 8,
332                 .caldac         = { mb88341 },
333         },
334         [BOARD_PCI6031E] = {
335                 .name           = "pci-6031e",
336                 .n_adchan       = 64,
337                 .adbits         = 16,
338                 .ai_fifo_depth  = 512,
339                 .alwaysdither   = 1,
340                 .gainlkup       = ai_gain_14,
341                 .ai_speed       = 10000,
342                 .n_aochan       = 2,
343                 .aobits         = 16,
344                 .ao_fifo_depth  = 2048,
345                 .ao_range_table = &range_ni_E_ao_ext,
346                 .ao_unipolar    = 1,
347                 .ao_speed       = 10000,
348                 .num_p0_dio_channels = 8,
349                 .caldac         = { dac8800, dac8043, ad8522 },
350         },
351         [BOARD_PCI6032E] = {
352                 .name           = "pci-6032e",
353                 .n_adchan       = 16,
354                 .adbits         = 16,
355                 .ai_fifo_depth  = 512,
356                 .alwaysdither   = 1,
357                 .gainlkup       = ai_gain_14,
358                 .ai_speed       = 10000,
359                 .num_p0_dio_channels = 8,
360                 .caldac         = { dac8800, dac8043, ad8522 },
361         },
362         [BOARD_PCI6033E] = {
363                 .name           = "pci-6033e",
364                 .n_adchan       = 64,
365                 .adbits         = 16,
366                 .ai_fifo_depth  = 512,
367                 .alwaysdither   = 1,
368                 .gainlkup       = ai_gain_14,
369                 .ai_speed       = 10000,
370                 .num_p0_dio_channels = 8,
371                 .caldac         = { dac8800, dac8043, ad8522 },
372         },
373         [BOARD_PCI6071E] = {
374                 .name           = "pci-6071e",
375                 .n_adchan       = 64,
376                 .adbits         = 12,
377                 .ai_fifo_depth  = 512,
378                 .alwaysdither   = 1,
379                 .gainlkup       = ai_gain_16,
380                 .ai_speed       = 800,
381                 .n_aochan       = 2,
382                 .aobits         = 12,
383                 .ao_fifo_depth  = 2048,
384                 .ao_range_table = &range_ni_E_ao_ext,
385                 .ao_unipolar    = 1,
386                 .ao_speed       = 1000,
387                 .num_p0_dio_channels = 8,
388                 .caldac         = { ad8804_debug },
389         },
390         [BOARD_PCI6023E] = {
391                 .name           = "pci-6023e",
392                 .n_adchan       = 16,
393                 .adbits         = 12,
394                 .ai_fifo_depth  = 512,
395                 .gainlkup       = ai_gain_4,
396                 .ai_speed       = 5000,
397                 .num_p0_dio_channels = 8,
398                 .caldac         = { ad8804_debug },     /* manual is wrong */
399         },
400         [BOARD_PCI6024E] = {
401                 .name           = "pci-6024e",
402                 .n_adchan       = 16,
403                 .adbits         = 12,
404                 .ai_fifo_depth  = 512,
405                 .gainlkup       = ai_gain_4,
406                 .ai_speed       = 5000,
407                 .n_aochan       = 2,
408                 .aobits         = 12,
409                 .ao_range_table = &range_bipolar10,
410                 .ao_speed       = 100000,
411                 .num_p0_dio_channels = 8,
412                 .caldac         = { ad8804_debug },     /* manual is wrong */
413         },
414         [BOARD_PCI6025E] = {
415                 .name           = "pci-6025e",
416                 .n_adchan       = 16,
417                 .adbits         = 12,
418                 .ai_fifo_depth  = 512,
419                 .gainlkup       = ai_gain_4,
420                 .ai_speed       = 5000,
421                 .n_aochan       = 2,
422                 .aobits         = 12,
423                 .ao_range_table = &range_bipolar10,
424                 .ao_speed       = 100000,
425                 .num_p0_dio_channels = 8,
426                 .caldac         = { ad8804_debug },     /* manual is wrong */
427                 .has_8255       = 1,
428         },
429         [BOARD_PXI6025E] = {
430                 .name           = "pxi-6025e",
431                 .n_adchan       = 16,
432                 .adbits         = 12,
433                 .ai_fifo_depth  = 512,
434                 .gainlkup       = ai_gain_4,
435                 .ai_speed       = 5000,
436                 .n_aochan       = 2,
437                 .aobits         = 12,
438                 .ao_range_table = &range_ni_E_ao_ext,
439                 .ao_unipolar    = 1,
440                 .ao_speed       = 100000,
441                 .num_p0_dio_channels = 8,
442                 .caldac         = { ad8804_debug },     /* manual is wrong */
443                 .has_8255       = 1,
444         },
445         [BOARD_PCI6034E] = {
446                 .name           = "pci-6034e",
447                 .n_adchan       = 16,
448                 .adbits         = 16,
449                 .ai_fifo_depth  = 512,
450                 .alwaysdither   = 1,
451                 .gainlkup       = ai_gain_4,
452                 .ai_speed       = 5000,
453                 .num_p0_dio_channels = 8,
454                 .caldac         = { ad8804_debug },
455         },
456         [BOARD_PCI6035E] = {
457                 .name           = "pci-6035e",
458                 .n_adchan       = 16,
459                 .adbits         = 16,
460                 .ai_fifo_depth  = 512,
461                 .alwaysdither   = 1,
462                 .gainlkup       = ai_gain_4,
463                 .ai_speed       = 5000,
464                 .n_aochan       = 2,
465                 .aobits         = 12,
466                 .ao_range_table = &range_bipolar10,
467                 .ao_speed       = 100000,
468                 .num_p0_dio_channels = 8,
469                 .caldac         = { ad8804_debug },
470         },
471         [BOARD_PCI6052E] = {
472                 .name           = "pci-6052e",
473                 .n_adchan       = 16,
474                 .adbits         = 16,
475                 .ai_fifo_depth  = 512,
476                 .alwaysdither   = 1,
477                 .gainlkup       = ai_gain_16,
478                 .ai_speed       = 3000,
479                 .n_aochan       = 2,
480                 .aobits         = 16,
481                 .ao_unipolar    = 1,
482                 .ao_fifo_depth  = 2048,
483                 .ao_range_table = &range_ni_E_ao_ext,
484                 .ao_speed       = 3000,
485                 .num_p0_dio_channels = 8,
486                 /* manual is wrong */
487                 .caldac         = { ad8804_debug, ad8804_debug, ad8522 },
488         },
489         [BOARD_PCI6110] = {
490                 .name           = "pci-6110",
491                 .n_adchan       = 4,
492                 .adbits         = 12,
493                 .ai_fifo_depth  = 8192,
494                 .alwaysdither   = 0,
495                 .gainlkup       = ai_gain_611x,
496                 .ai_speed       = 200,
497                 .n_aochan       = 2,
498                 .aobits         = 16,
499                 .reg_type       = ni_reg_611x,
500                 .ao_range_table = &range_bipolar10,
501                 .ao_fifo_depth  = 2048,
502                 .ao_speed       = 250,
503                 .num_p0_dio_channels = 8,
504                 .caldac         = { ad8804, ad8804 },
505         },
506         [BOARD_PCI6111] = {
507                 .name           = "pci-6111",
508                 .n_adchan       = 2,
509                 .adbits         = 12,
510                 .ai_fifo_depth  = 8192,
511                 .gainlkup       = ai_gain_611x,
512                 .ai_speed       = 200,
513                 .n_aochan       = 2,
514                 .aobits         = 16,
515                 .reg_type       = ni_reg_611x,
516                 .ao_range_table = &range_bipolar10,
517                 .ao_fifo_depth  = 2048,
518                 .ao_speed       = 250,
519                 .num_p0_dio_channels = 8,
520                 .caldac         = { ad8804, ad8804 },
521         },
522 #if 0
523         /* The 6115 boards probably need their own driver */
524         [BOARD_PCI6115] = {     /* .device_id = 0x2ed0, */
525                 .name           = "pci-6115",
526                 .n_adchan       = 4,
527                 .adbits         = 12,
528                 .ai_fifo_depth  = 8192,
529                 .gainlkup       = ai_gain_611x,
530                 .ai_speed       = 100,
531                 .n_aochan       = 2,
532                 .aobits         = 16,
533                 .ao_671x        = 1,
534                 .ao_fifo_depth  = 2048,
535                 .ao_speed       = 250,
536                 .num_p0_dio_channels = 8,
537                 .reg_611x       = 1,
538                 /* XXX */
539                 .caldac         = { ad8804_debug, ad8804_debug, ad8804_debug },
540         },
541 #endif
542 #if 0
543         [BOARD_PXI6115] = {     /* .device_id = ????, */
544                 .name           = "pxi-6115",
545                 .n_adchan       = 4,
546                 .adbits         = 12,
547                 .ai_fifo_depth  = 8192,
548                 .gainlkup       = ai_gain_611x,
549                 .ai_speed       = 100,
550                 .n_aochan       = 2,
551                 .aobits         = 16,
552                 .ao_671x        = 1,
553                 .ao_fifo_depth  = 2048,
554                 .ao_speed       = 250,
555                 .reg_611x       = 1,
556                 .num_p0_dio_channels = 8,
557                 /* XXX */
558                 .caldac         = { ad8804_debug, ad8804_debug, ad8804_debug },
559         },
560 #endif
561         [BOARD_PCI6711] = {
562                 .name = "pci-6711",
563                 .n_aochan       = 4,
564                 .aobits         = 12,
565                 /* data sheet says 8192, but fifo really holds 16384 samples */
566                 .ao_fifo_depth  = 16384,
567                 .ao_range_table = &range_bipolar10,
568                 .ao_speed       = 1000,
569                 .num_p0_dio_channels = 8,
570                 .reg_type       = ni_reg_6711,
571                 .caldac         = { ad8804_debug },
572         },
573         [BOARD_PXI6711] = {
574                 .name           = "pxi-6711",
575                 .n_aochan       = 4,
576                 .aobits         = 12,
577                 .ao_fifo_depth  = 16384,
578                 .ao_range_table = &range_bipolar10,
579                 .ao_speed       = 1000,
580                 .num_p0_dio_channels = 8,
581                 .reg_type       = ni_reg_6711,
582                 .caldac         = { ad8804_debug },
583         },
584         [BOARD_PCI6713] = {
585                 .name           = "pci-6713",
586                 .n_aochan       = 8,
587                 .aobits         = 12,
588                 .ao_fifo_depth  = 16384,
589                 .ao_range_table = &range_bipolar10,
590                 .ao_speed       = 1000,
591                 .num_p0_dio_channels = 8,
592                 .reg_type       = ni_reg_6713,
593                 .caldac         = { ad8804_debug, ad8804_debug },
594         },
595         [BOARD_PXI6713] = {
596                 .name           = "pxi-6713",
597                 .n_aochan       = 8,
598                 .aobits         = 12,
599                 .ao_fifo_depth  = 16384,
600                 .ao_range_table = &range_bipolar10,
601                 .ao_speed       = 1000,
602                 .num_p0_dio_channels = 8,
603                 .reg_type       = ni_reg_6713,
604                 .caldac         = { ad8804_debug, ad8804_debug },
605         },
606         [BOARD_PCI6731] = {
607                 .name           = "pci-6731",
608                 .n_aochan       = 4,
609                 .aobits         = 16,
610                 .ao_fifo_depth  = 8192,
611                 .ao_range_table = &range_bipolar10,
612                 .ao_speed       = 1000,
613                 .num_p0_dio_channels = 8,
614                 .reg_type       = ni_reg_6711,
615                 .caldac         = { ad8804_debug },
616         },
617 #if 0
618         [BOARD_PXI6731] = {     /* .device_id = ????, */
619                 .name           = "pxi-6731",
620                 .n_aochan       = 4,
621                 .aobits         = 16,
622                 .ao_fifo_depth  = 8192,
623                 .ao_range_table = &range_bipolar10,
624                 .num_p0_dio_channels = 8,
625                 .reg_type       = ni_reg_6711,
626                 .caldac         = { ad8804_debug },
627         },
628 #endif
629         [BOARD_PCI6733] = {
630                 .name           = "pci-6733",
631                 .n_aochan       = 8,
632                 .aobits         = 16,
633                 .ao_fifo_depth  = 16384,
634                 .ao_range_table = &range_bipolar10,
635                 .ao_speed       = 1000,
636                 .num_p0_dio_channels = 8,
637                 .reg_type       = ni_reg_6713,
638                 .caldac         = { ad8804_debug, ad8804_debug },
639         },
640         [BOARD_PXI6733] = {
641                 .name           = "pxi-6733",
642                 .n_aochan       = 8,
643                 .aobits         = 16,
644                 .ao_fifo_depth  = 16384,
645                 .ao_range_table = &range_bipolar10,
646                 .ao_speed       = 1000,
647                 .num_p0_dio_channels = 8,
648                 .reg_type       = ni_reg_6713,
649                 .caldac         = { ad8804_debug, ad8804_debug },
650         },
651         [BOARD_PXI6071E] = {
652                 .name           = "pxi-6071e",
653                 .n_adchan       = 64,
654                 .adbits         = 12,
655                 .ai_fifo_depth  = 512,
656                 .alwaysdither   = 1,
657                 .gainlkup       = ai_gain_16,
658                 .ai_speed       = 800,
659                 .n_aochan       = 2,
660                 .aobits         = 12,
661                 .ao_fifo_depth  = 2048,
662                 .ao_range_table = &range_ni_E_ao_ext,
663                 .ao_unipolar    = 1,
664                 .ao_speed       = 1000,
665                 .num_p0_dio_channels = 8,
666                 .caldac         = { ad8804_debug },
667         },
668         [BOARD_PXI6070E] = {
669                 .name           = "pxi-6070e",
670                 .n_adchan       = 16,
671                 .adbits         = 12,
672                 .ai_fifo_depth  = 512,
673                 .alwaysdither   = 1,
674                 .gainlkup       = ai_gain_16,
675                 .ai_speed       = 800,
676                 .n_aochan       = 2,
677                 .aobits         = 12,
678                 .ao_fifo_depth  = 2048,
679                 .ao_range_table = &range_ni_E_ao_ext,
680                 .ao_unipolar    = 1,
681                 .ao_speed       = 1000,
682                 .num_p0_dio_channels = 8,
683                 .caldac         = { ad8804_debug },
684         },
685         [BOARD_PXI6052E] = {
686                 .name           = "pxi-6052e",
687                 .n_adchan       = 16,
688                 .adbits         = 16,
689                 .ai_fifo_depth  = 512,
690                 .alwaysdither   = 1,
691                 .gainlkup       = ai_gain_16,
692                 .ai_speed       = 3000,
693                 .n_aochan       = 2,
694                 .aobits         = 16,
695                 .ao_unipolar    = 1,
696                 .ao_fifo_depth  = 2048,
697                 .ao_range_table = &range_ni_E_ao_ext,
698                 .ao_speed       = 3000,
699                 .num_p0_dio_channels = 8,
700                 .caldac         = { mb88341, mb88341, ad8522 },
701         },
702         [BOARD_PXI6031E] = {
703                 .name           = "pxi-6031e",
704                 .n_adchan       = 64,
705                 .adbits         = 16,
706                 .ai_fifo_depth  = 512,
707                 .alwaysdither   = 1,
708                 .gainlkup       = ai_gain_14,
709                 .ai_speed       = 10000,
710                 .n_aochan       = 2,
711                 .aobits         = 16,
712                 .ao_fifo_depth  = 2048,
713                 .ao_range_table = &range_ni_E_ao_ext,
714                 .ao_unipolar    = 1,
715                 .ao_speed       = 10000,
716                 .num_p0_dio_channels = 8,
717                 .caldac         = { dac8800, dac8043, ad8522 },
718         },
719         [BOARD_PCI6036E] = {
720                 .name = "pci-6036e",
721                 .n_adchan       = 16,
722                 .adbits         = 16,
723                 .ai_fifo_depth  = 512,
724                 .alwaysdither   = 1,
725                 .gainlkup       = ai_gain_4,
726                 .ai_speed       = 5000,
727                 .n_aochan       = 2,
728                 .aobits         = 16,
729                 .ao_range_table = &range_bipolar10,
730                 .ao_speed       = 100000,
731                 .num_p0_dio_channels = 8,
732                 .caldac         = { ad8804_debug },
733         },
734         [BOARD_PCI6220] = {
735                 .name           = "pci-6220",
736                 .n_adchan       = 16,
737                 .adbits         = 16,
738                 .ai_fifo_depth  = 512,          /* FIXME: guess */
739                 .gainlkup       = ai_gain_622x,
740                 .ai_speed       = 4000,
741                 .num_p0_dio_channels = 8,
742                 .reg_type       = ni_reg_622x,
743                 .caldac         = { caldac_none },
744         },
745         [BOARD_PCI6221] = {
746                 .name           = "pci-6221",
747                 .n_adchan       = 16,
748                 .adbits         = 16,
749                 .ai_fifo_depth  = 4095,
750                 .gainlkup       = ai_gain_622x,
751                 .ai_speed       = 4000,
752                 .n_aochan       = 2,
753                 .aobits         = 16,
754                 .ao_fifo_depth  = 8191,
755                 .ao_range_table = &range_bipolar10,
756                 .reg_type       = ni_reg_622x,
757                 .ao_speed       = 1200,
758                 .num_p0_dio_channels = 8,
759                 .caldac         = { caldac_none },
760         },
761         [BOARD_PCI6221_37PIN] = {
762                 .name           = "pci-6221_37pin",
763                 .n_adchan       = 16,
764                 .adbits         = 16,
765                 .ai_fifo_depth  = 4095,
766                 .gainlkup       = ai_gain_622x,
767                 .ai_speed       = 4000,
768                 .n_aochan       = 2,
769                 .aobits         = 16,
770                 .ao_fifo_depth  = 8191,
771                 .ao_range_table = &range_bipolar10,
772                 .reg_type       = ni_reg_622x,
773                 .ao_speed       = 1200,
774                 .num_p0_dio_channels = 8,
775                 .caldac         = { caldac_none },
776         },
777         [BOARD_PCI6224] = {
778                 .name           = "pci-6224",
779                 .n_adchan       = 32,
780                 .adbits         = 16,
781                 .ai_fifo_depth  = 4095,
782                 .gainlkup       = ai_gain_622x,
783                 .ai_speed       = 4000,
784                 .reg_type       = ni_reg_622x,
785                 .num_p0_dio_channels = 32,
786                 .caldac         = { caldac_none },
787         },
788         [BOARD_PXI6224] = {
789                 .name           = "pxi-6224",
790                 .n_adchan       = 32,
791                 .adbits         = 16,
792                 .ai_fifo_depth  = 4095,
793                 .gainlkup       = ai_gain_622x,
794                 .ai_speed       = 4000,
795                 .reg_type       = ni_reg_622x,
796                 .num_p0_dio_channels = 32,
797                 .caldac         = { caldac_none },
798         },
799         [BOARD_PCI6225] = {
800                 .name           = "pci-6225",
801                 .n_adchan       = 80,
802                 .adbits         = 16,
803                 .ai_fifo_depth  = 4095,
804                 .gainlkup       = ai_gain_622x,
805                 .ai_speed       = 4000,
806                 .n_aochan       = 2,
807                 .aobits         = 16,
808                 .ao_fifo_depth  = 8191,
809                 .ao_range_table = &range_bipolar10,
810                 .reg_type       = ni_reg_622x,
811                 .ao_speed       = 1200,
812                 .num_p0_dio_channels = 32,
813                 .caldac         = { caldac_none },
814         },
815         [BOARD_PXI6225] = {
816                 .name           = "pxi-6225",
817                 .n_adchan       = 80,
818                 .adbits         = 16,
819                 .ai_fifo_depth  = 4095,
820                 .gainlkup       = ai_gain_622x,
821                 .ai_speed       = 4000,
822                 .n_aochan       = 2,
823                 .aobits         = 16,
824                 .ao_fifo_depth  = 8191,
825                 .ao_range_table = &range_bipolar10,
826                 .reg_type       = ni_reg_622x,
827                 .ao_speed       = 1200,
828                 .num_p0_dio_channels = 32,
829                 .caldac         = { caldac_none },
830         },
831         [BOARD_PCI6229] = {
832                 .name           = "pci-6229",
833                 .n_adchan       = 32,
834                 .adbits         = 16,
835                 .ai_fifo_depth  = 4095,
836                 .gainlkup       = ai_gain_622x,
837                 .ai_speed       = 4000,
838                 .n_aochan       = 4,
839                 .aobits         = 16,
840                 .ao_fifo_depth  = 8191,
841                 .ao_range_table = &range_bipolar10,
842                 .reg_type       = ni_reg_622x,
843                 .ao_speed       = 1200,
844                 .num_p0_dio_channels = 32,
845                 .caldac         = { caldac_none },
846         },
847         [BOARD_PCI6250] = {
848                 .name           = "pci-6250",
849                 .n_adchan       = 16,
850                 .adbits         = 16,
851                 .ai_fifo_depth  = 4095,
852                 .gainlkup       = ai_gain_628x,
853                 .ai_speed       = 800,
854                 .reg_type       = ni_reg_625x,
855                 .num_p0_dio_channels = 8,
856                 .caldac         = { caldac_none },
857         },
858         [BOARD_PCI6251] = {
859                 .name           = "pci-6251",
860                 .n_adchan       = 16,
861                 .adbits         = 16,
862                 .ai_fifo_depth  = 4095,
863                 .gainlkup       = ai_gain_628x,
864                 .ai_speed       = 800,
865                 .n_aochan       = 2,
866                 .aobits         = 16,
867                 .ao_fifo_depth  = 8191,
868                 .ao_range_table = &range_ni_M_625x_ao,
869                 .reg_type       = ni_reg_625x,
870                 .ao_speed       = 350,
871                 .num_p0_dio_channels = 8,
872                 .caldac         = { caldac_none },
873         },
874         [BOARD_PCIE6251] = {
875                 .name           = "pcie-6251",
876                 .n_adchan       = 16,
877                 .adbits         = 16,
878                 .ai_fifo_depth  = 4095,
879                 .gainlkup       = ai_gain_628x,
880                 .ai_speed       = 800,
881                 .n_aochan       = 2,
882                 .aobits         = 16,
883                 .ao_fifo_depth  = 8191,
884                 .ao_range_table = &range_ni_M_625x_ao,
885                 .reg_type       = ni_reg_625x,
886                 .ao_speed       = 350,
887                 .num_p0_dio_channels = 8,
888                 .caldac         = { caldac_none },
889         },
890         [BOARD_PXIE6251] = {
891                 .name           = "pxie-6251",
892                 .n_adchan       = 16,
893                 .adbits         = 16,
894                 .ai_fifo_depth  = 4095,
895                 .gainlkup       = ai_gain_628x,
896                 .ai_speed       = 800,
897                 .n_aochan       = 2,
898                 .aobits         = 16,
899                 .ao_fifo_depth  = 8191,
900                 .ao_range_table = &range_ni_M_625x_ao,
901                 .reg_type       = ni_reg_625x,
902                 .ao_speed       = 350,
903                 .num_p0_dio_channels = 8,
904                 .caldac         = { caldac_none },
905         },
906         [BOARD_PCI6254] = {
907                 .name           = "pci-6254",
908                 .n_adchan       = 32,
909                 .adbits         = 16,
910                 .ai_fifo_depth  = 4095,
911                 .gainlkup       = ai_gain_628x,
912                 .ai_speed       = 800,
913                 .reg_type       = ni_reg_625x,
914                 .num_p0_dio_channels = 32,
915                 .caldac         = { caldac_none },
916         },
917         [BOARD_PCI6259] = {
918                 .name           = "pci-6259",
919                 .n_adchan       = 32,
920                 .adbits         = 16,
921                 .ai_fifo_depth  = 4095,
922                 .gainlkup       = ai_gain_628x,
923                 .ai_speed       = 800,
924                 .n_aochan       = 4,
925                 .aobits         = 16,
926                 .ao_fifo_depth  = 8191,
927                 .ao_range_table = &range_ni_M_625x_ao,
928                 .reg_type       = ni_reg_625x,
929                 .ao_speed       = 350,
930                 .num_p0_dio_channels = 32,
931                 .caldac         = { caldac_none },
932         },
933         [BOARD_PCIE6259] = {
934                 .name           = "pcie-6259",
935                 .n_adchan       = 32,
936                 .adbits         = 16,
937                 .ai_fifo_depth  = 4095,
938                 .gainlkup       = ai_gain_628x,
939                 .ai_speed       = 800,
940                 .n_aochan       = 4,
941                 .aobits         = 16,
942                 .ao_fifo_depth  = 8191,
943                 .ao_range_table = &range_ni_M_625x_ao,
944                 .reg_type       = ni_reg_625x,
945                 .ao_speed       = 350,
946                 .num_p0_dio_channels = 32,
947                 .caldac         = { caldac_none },
948         },
949         [BOARD_PCI6280] = {
950                 .name           = "pci-6280",
951                 .n_adchan       = 16,
952                 .adbits         = 18,
953                 .ai_fifo_depth  = 2047,
954                 .gainlkup       = ai_gain_628x,
955                 .ai_speed       = 1600,
956                 .ao_fifo_depth  = 8191,
957                 .reg_type       = ni_reg_628x,
958                 .num_p0_dio_channels = 8,
959                 .caldac         = { caldac_none },
960         },
961         [BOARD_PCI6281] = {
962                 .name           = "pci-6281",
963                 .n_adchan       = 16,
964                 .adbits         = 18,
965                 .ai_fifo_depth  = 2047,
966                 .gainlkup       = ai_gain_628x,
967                 .ai_speed       = 1600,
968                 .n_aochan       = 2,
969                 .aobits         = 16,
970                 .ao_fifo_depth  = 8191,
971                 .ao_range_table = &range_ni_M_628x_ao,
972                 .reg_type       = ni_reg_628x,
973                 .ao_unipolar    = 1,
974                 .ao_speed       = 350,
975                 .num_p0_dio_channels = 8,
976                 .caldac         = { caldac_none },
977         },
978         [BOARD_PXI6281] = {
979                 .name           = "pxi-6281",
980                 .n_adchan       = 16,
981                 .adbits         = 18,
982                 .ai_fifo_depth  = 2047,
983                 .gainlkup       = ai_gain_628x,
984                 .ai_speed       = 1600,
985                 .n_aochan       = 2,
986                 .aobits         = 16,
987                 .ao_fifo_depth  = 8191,
988                 .ao_range_table = &range_ni_M_628x_ao,
989                 .reg_type       = ni_reg_628x,
990                 .ao_unipolar    = 1,
991                 .ao_speed       = 350,
992                 .num_p0_dio_channels = 8,
993                 .caldac         = { caldac_none },
994         },
995         [BOARD_PCI6284] = {
996                 .name           = "pci-6284",
997                 .n_adchan       = 32,
998                 .adbits         = 18,
999                 .ai_fifo_depth  = 2047,
1000                 .gainlkup       = ai_gain_628x,
1001                 .ai_speed       = 1600,
1002                 .reg_type       = ni_reg_628x,
1003                 .num_p0_dio_channels = 32,
1004                 .caldac         = { caldac_none },
1005         },
1006         [BOARD_PCI6289] = {
1007                 .name           = "pci-6289",
1008                 .n_adchan       = 32,
1009                 .adbits         = 18,
1010                 .ai_fifo_depth  = 2047,
1011                 .gainlkup       = ai_gain_628x,
1012                 .ai_speed       = 1600,
1013                 .n_aochan       = 4,
1014                 .aobits         = 16,
1015                 .ao_fifo_depth  = 8191,
1016                 .ao_range_table = &range_ni_M_628x_ao,
1017                 .reg_type       = ni_reg_628x,
1018                 .ao_unipolar    = 1,
1019                 .ao_speed       = 350,
1020                 .num_p0_dio_channels = 32,
1021                 .caldac         = { caldac_none },
1022         },
1023         [BOARD_PCI6143] = {
1024                 .name           = "pci-6143",
1025                 .n_adchan       = 8,
1026                 .adbits         = 16,
1027                 .ai_fifo_depth  = 1024,
1028                 .gainlkup       = ai_gain_6143,
1029                 .ai_speed       = 4000,
1030                 .reg_type       = ni_reg_6143,
1031                 .num_p0_dio_channels = 8,
1032                 .caldac         = { ad8804_debug, ad8804_debug },
1033         },
1034         [BOARD_PXI6143] = {
1035                 .name           = "pxi-6143",
1036                 .n_adchan       = 8,
1037                 .adbits         = 16,
1038                 .ai_fifo_depth  = 1024,
1039                 .gainlkup       = ai_gain_6143,
1040                 .ai_speed       = 4000,
1041                 .reg_type       = ni_reg_6143,
1042                 .num_p0_dio_channels = 8,
1043                 .caldac         = { ad8804_debug, ad8804_debug },
1044         },
1045 };
1046 
1047 struct ni_private {
1048 NI_PRIVATE_COMMON};
1049 
1050 /* How we access registers */
1051 
1052 #define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b)))
1053 #define ni_readl(a)     (readl(devpriv->mite->daq_io_addr + (a)))
1054 #define ni_writew(a, b) (writew((a), devpriv->mite->daq_io_addr + (b)))
1055 #define ni_readw(a)     (readw(devpriv->mite->daq_io_addr + (a)))
1056 #define ni_writeb(a, b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
1057 #define ni_readb(a)     (readb(devpriv->mite->daq_io_addr + (a)))
1058 
1059 /* How we access STC registers */
1060 
1061 /* We automatically take advantage of STC registers that can be
1062  * read/written directly in the I/O space of the board.  Most
1063  * PCIMIO devices map the low 8 STC registers to iobase+addr*2.
1064  * The 611x devices map the write registers to iobase+addr*2, and
1065  * the read registers to iobase+(addr-1)*2. */
1066 /* However, the 611x boards still aren't working, so I'm disabling
1067  * non-windowed STC access temporarily */
1068 
1069 static void e_series_win_out(struct comedi_device *dev, uint16_t data, int reg)
1070 {
1071         struct ni_private *devpriv = dev->private;
1072         unsigned long flags;
1073 
1074         spin_lock_irqsave(&devpriv->window_lock, flags);
1075         ni_writew(reg, Window_Address);
1076         ni_writew(data, Window_Data);
1077         spin_unlock_irqrestore(&devpriv->window_lock, flags);
1078 }
1079 
1080 static uint16_t e_series_win_in(struct comedi_device *dev, int reg)
1081 {
1082         struct ni_private *devpriv = dev->private;
1083         unsigned long flags;
1084         uint16_t ret;
1085 
1086         spin_lock_irqsave(&devpriv->window_lock, flags);
1087         ni_writew(reg, Window_Address);
1088         ret = ni_readw(Window_Data);
1089         spin_unlock_irqrestore(&devpriv->window_lock, flags);
1090 
1091         return ret;
1092 }
1093 
1094 static void m_series_stc_writew(struct comedi_device *dev, uint16_t data,
1095                                 int reg)
1096 {
1097         struct ni_private *devpriv = dev->private;
1098         unsigned offset;
1099 
1100         switch (reg) {
1101         case ADC_FIFO_Clear:
1102                 offset = M_Offset_AI_FIFO_Clear;
1103                 break;
1104         case AI_Command_1_Register:
1105                 offset = M_Offset_AI_Command_1;
1106                 break;
1107         case AI_Command_2_Register:
1108                 offset = M_Offset_AI_Command_2;
1109                 break;
1110         case AI_Mode_1_Register:
1111                 offset = M_Offset_AI_Mode_1;
1112                 break;
1113         case AI_Mode_2_Register:
1114                 offset = M_Offset_AI_Mode_2;
1115                 break;
1116         case AI_Mode_3_Register:
1117                 offset = M_Offset_AI_Mode_3;
1118                 break;
1119         case AI_Output_Control_Register:
1120                 offset = M_Offset_AI_Output_Control;
1121                 break;
1122         case AI_Personal_Register:
1123                 offset = M_Offset_AI_Personal;
1124                 break;
1125         case AI_SI2_Load_A_Register:
1126                 /*  this is actually a 32 bit register on m series boards */
1127                 ni_writel(data, M_Offset_AI_SI2_Load_A);
1128                 return;
1129                 break;
1130         case AI_SI2_Load_B_Register:
1131                 /*  this is actually a 32 bit register on m series boards */
1132                 ni_writel(data, M_Offset_AI_SI2_Load_B);
1133                 return;
1134                 break;
1135         case AI_START_STOP_Select_Register:
1136                 offset = M_Offset_AI_START_STOP_Select;
1137                 break;
1138         case AI_Trigger_Select_Register:
1139                 offset = M_Offset_AI_Trigger_Select;
1140                 break;
1141         case Analog_Trigger_Etc_Register:
1142                 offset = M_Offset_Analog_Trigger_Etc;
1143                 break;
1144         case AO_Command_1_Register:
1145                 offset = M_Offset_AO_Command_1;
1146                 break;
1147         case AO_Command_2_Register:
1148                 offset = M_Offset_AO_Command_2;
1149                 break;
1150         case AO_Mode_1_Register:
1151                 offset = M_Offset_AO_Mode_1;
1152                 break;
1153         case AO_Mode_2_Register:
1154                 offset = M_Offset_AO_Mode_2;
1155                 break;
1156         case AO_Mode_3_Register:
1157                 offset = M_Offset_AO_Mode_3;
1158                 break;
1159         case AO_Output_Control_Register:
1160                 offset = M_Offset_AO_Output_Control;
1161                 break;
1162         case AO_Personal_Register:
1163                 offset = M_Offset_AO_Personal;
1164                 break;
1165         case AO_Start_Select_Register:
1166                 offset = M_Offset_AO_Start_Select;
1167                 break;
1168         case AO_Trigger_Select_Register:
1169                 offset = M_Offset_AO_Trigger_Select;
1170                 break;
1171         case Clock_and_FOUT_Register:
1172                 offset = M_Offset_Clock_and_FOUT;
1173                 break;
1174         case Configuration_Memory_Clear:
1175                 offset = M_Offset_Configuration_Memory_Clear;
1176                 break;
1177         case DAC_FIFO_Clear:
1178                 offset = M_Offset_AO_FIFO_Clear;
1179                 break;
1180         case DIO_Control_Register:
1181                 dev_dbg(dev->class_dev,
1182                         "%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n",
1183                         __func__, reg);
1184                 return;
1185                 break;
1186         case G_Autoincrement_Register(0):
1187                 offset = M_Offset_G0_Autoincrement;
1188                 break;
1189         case G_Autoincrement_Register(1):
1190                 offset = M_Offset_G1_Autoincrement;
1191                 break;
1192         case G_Command_Register(0):
1193                 offset = M_Offset_G0_Command;
1194                 break;
1195         case G_Command_Register(1):
1196                 offset = M_Offset_G1_Command;
1197                 break;
1198         case G_Input_Select_Register(0):
1199                 offset = M_Offset_G0_Input_Select;
1200                 break;
1201         case G_Input_Select_Register(1):
1202                 offset = M_Offset_G1_Input_Select;
1203                 break;
1204         case G_Mode_Register(0):
1205                 offset = M_Offset_G0_Mode;
1206                 break;
1207         case G_Mode_Register(1):
1208                 offset = M_Offset_G1_Mode;
1209                 break;
1210         case Interrupt_A_Ack_Register:
1211                 offset = M_Offset_Interrupt_A_Ack;
1212                 break;
1213         case Interrupt_A_Enable_Register:
1214                 offset = M_Offset_Interrupt_A_Enable;
1215                 break;
1216         case Interrupt_B_Ack_Register:
1217                 offset = M_Offset_Interrupt_B_Ack;
1218                 break;
1219         case Interrupt_B_Enable_Register:
1220                 offset = M_Offset_Interrupt_B_Enable;
1221                 break;
1222         case Interrupt_Control_Register:
1223                 offset = M_Offset_Interrupt_Control;
1224                 break;
1225         case IO_Bidirection_Pin_Register:
1226                 offset = M_Offset_IO_Bidirection_Pin;
1227                 break;
1228         case Joint_Reset_Register:
1229                 offset = M_Offset_Joint_Reset;
1230                 break;
1231         case RTSI_Trig_A_Output_Register:
1232                 offset = M_Offset_RTSI_Trig_A_Output;
1233                 break;
1234         case RTSI_Trig_B_Output_Register:
1235                 offset = M_Offset_RTSI_Trig_B_Output;
1236                 break;
1237         case RTSI_Trig_Direction_Register:
1238                 offset = M_Offset_RTSI_Trig_Direction;
1239                 break;
1240                 /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit)
1241                    and M_Offset_SCXI_Serial_Data_Out (8 bit) */
1242         default:
1243                 dev_warn(dev->class_dev,
1244                          "%s: bug! unhandled register=0x%x in switch.\n",
1245                          __func__, reg);
1246                 BUG();
1247                 return;
1248                 break;
1249         }
1250         ni_writew(data, offset);
1251 }
1252 
1253 static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
1254 {
1255         struct ni_private *devpriv = dev->private;
1256         unsigned offset;
1257 
1258         switch (reg) {
1259         case AI_Status_1_Register:
1260                 offset = M_Offset_AI_Status_1;
1261                 break;
1262         case AO_Status_1_Register:
1263                 offset = M_Offset_AO_Status_1;
1264                 break;
1265         case AO_Status_2_Register:
1266                 offset = M_Offset_AO_Status_2;
1267                 break;
1268         case DIO_Serial_Input_Register:
1269                 return ni_readb(M_Offset_SCXI_Serial_Data_In);
1270                 break;
1271         case Joint_Status_1_Register:
1272                 offset = M_Offset_Joint_Status_1;
1273                 break;
1274         case Joint_Status_2_Register:
1275                 offset = M_Offset_Joint_Status_2;
1276                 break;
1277         case G_Status_Register:
1278                 offset = M_Offset_G01_Status;
1279                 break;
1280         default:
1281                 dev_warn(dev->class_dev,
1282                          "%s: bug! unhandled register=0x%x in switch.\n",
1283                          __func__, reg);
1284                 BUG();
1285                 return 0;
1286                 break;
1287         }
1288         return ni_readw(offset);
1289 }
1290 
1291 static void m_series_stc_writel(struct comedi_device *dev, uint32_t data,
1292                                 int reg)
1293 {
1294         struct ni_private *devpriv = dev->private;
1295         unsigned offset;
1296 
1297         switch (reg) {
1298         case AI_SC_Load_A_Registers:
1299                 offset = M_Offset_AI_SC_Load_A;
1300                 break;
1301         case AI_SI_Load_A_Registers:
1302                 offset = M_Offset_AI_SI_Load_A;
1303                 break;
1304         case AO_BC_Load_A_Register:
1305                 offset = M_Offset_AO_BC_Load_A;
1306                 break;
1307         case AO_UC_Load_A_Register:
1308                 offset = M_Offset_AO_UC_Load_A;
1309                 break;
1310         case AO_UI_Load_A_Register:
1311                 offset = M_Offset_AO_UI_Load_A;
1312                 break;
1313         case G_Load_A_Register(0):
1314                 offset = M_Offset_G0_Load_A;
1315                 break;
1316         case G_Load_A_Register(1):
1317                 offset = M_Offset_G1_Load_A;
1318                 break;
1319         case G_Load_B_Register(0):
1320                 offset = M_Offset_G0_Load_B;
1321                 break;
1322         case G_Load_B_Register(1):
1323                 offset = M_Offset_G1_Load_B;
1324                 break;
1325         default:
1326                 dev_warn(dev->class_dev,
1327                          "%s: bug! unhandled register=0x%x in switch.\n",
1328                          __func__, reg);
1329                 BUG();
1330                 return;
1331                 break;
1332         }
1333         ni_writel(data, offset);
1334 }
1335 
1336 static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
1337 {
1338         struct ni_private *devpriv = dev->private;
1339         unsigned offset;
1340 
1341         switch (reg) {
1342         case G_HW_Save_Register(0):
1343                 offset = M_Offset_G0_HW_Save;
1344                 break;
1345         case G_HW_Save_Register(1):
1346                 offset = M_Offset_G1_HW_Save;
1347                 break;
1348         case G_Save_Register(0):
1349                 offset = M_Offset_G0_Save;
1350                 break;
1351         case G_Save_Register(1):
1352                 offset = M_Offset_G1_Save;
1353                 break;
1354         default:
1355                 dev_warn(dev->class_dev,
1356                          "%s: bug! unhandled register=0x%x in switch.\n",
1357                          __func__, reg);
1358                 BUG();
1359                 return 0;
1360                 break;
1361         }
1362         return ni_readl(offset);
1363 }
1364 
1365 #define interrupt_pin(a)        0
1366 #define IRQ_POLARITY 1
1367 
1368 #define NI_E_IRQ_FLAGS          IRQF_SHARED
1369 
1370 #include "ni_mio_common.c"
1371 
1372 static int pcimio_ai_change(struct comedi_device *dev,
1373                             struct comedi_subdevice *s, unsigned long new_size);
1374 static int pcimio_ao_change(struct comedi_device *dev,
1375                             struct comedi_subdevice *s, unsigned long new_size);
1376 static int pcimio_gpct0_change(struct comedi_device *dev,
1377                                struct comedi_subdevice *s,
1378                                unsigned long new_size);
1379 static int pcimio_gpct1_change(struct comedi_device *dev,
1380                                struct comedi_subdevice *s,
1381                                unsigned long new_size);
1382 static int pcimio_dio_change(struct comedi_device *dev,
1383                              struct comedi_subdevice *s,
1384                              unsigned long new_size);
1385 
1386 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1387 {
1388         struct ni_private *devpriv = dev->private;
1389         static const int Start_Cal_EEPROM = 0x400;
1390         static const unsigned window_size = 10;
1391         static const int serial_number_eeprom_offset = 0x4;
1392         static const int serial_number_eeprom_length = 0x4;
1393         unsigned old_iodwbsr_bits;
1394         unsigned old_iodwbsr1_bits;
1395         unsigned old_iodwcr1_bits;
1396         int i;
1397 
1398         old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR);
1399         old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1400         old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1401         writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1402         writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr),
1403                devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1404         writel(0x1 | old_iodwcr1_bits,
1405                devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1406         writel(0xf, devpriv->mite->mite_io_addr + 0x30);
1407 
1408         BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1409         for (i = 0; i < serial_number_eeprom_length; ++i) {
1410                 char *byte_ptr = (char *)&devpriv->serial_number + i;
1411                 *byte_ptr = ni_readb(serial_number_eeprom_offset + i);
1412         }
1413         devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1414 
1415         for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1416                 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i);
1417 
1418         writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1419         writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1420         writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1421         writel(0x0, devpriv->mite->mite_io_addr + 0x30);
1422 }
1423 
1424 static void init_6143(struct comedi_device *dev)
1425 {
1426         const struct ni_board_struct *board = comedi_board(dev);
1427         struct ni_private *devpriv = dev->private;
1428 
1429         /*  Disable interrupts */
1430         devpriv->stc_writew(dev, 0, Interrupt_Control_Register);
1431 
1432         /*  Initialise 6143 AI specific bits */
1433         ni_writeb(0x00, Magic_6143);    /*  Set G0,G1 DMA mode to E series version */
1434         ni_writeb(0x80, PipelineDelay_6143);    /*  Set EOCMode, ADCMode and pipelinedelay */
1435         ni_writeb(0x00, EOC_Set_6143);  /*  Set EOC Delay */
1436 
1437         /* Set the FIFO half full level */
1438         ni_writel(board->ai_fifo_depth / 2, AIFIFO_Flag_6143);
1439 
1440         /*  Strobe Relay disable bit */
1441         devpriv->ai_calib_source_enabled = 0;
1442         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff,
1443                   Calibration_Channel_6143);
1444         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1445 }
1446 
1447 static void pcimio_detach(struct comedi_device *dev)
1448 {
1449         struct ni_private *devpriv = dev->private;
1450 
1451         mio_common_detach(dev);
1452         if (dev->irq)
1453                 free_irq(dev->irq, dev);
1454         if (devpriv) {
1455                 mite_free_ring(devpriv->ai_mite_ring);
1456                 mite_free_ring(devpriv->ao_mite_ring);
1457                 mite_free_ring(devpriv->cdo_mite_ring);
1458                 mite_free_ring(devpriv->gpct_mite_ring[0]);
1459                 mite_free_ring(devpriv->gpct_mite_ring[1]);
1460                 if (devpriv->mite) {
1461                         mite_unsetup(devpriv->mite);
1462                         mite_free(devpriv->mite);
1463                 }
1464         }
1465         comedi_pci_disable(dev);
1466 }
1467 
1468 static int pcimio_auto_attach(struct comedi_device *dev,
1469                               unsigned long context)
1470 {
1471         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1472         const struct ni_board_struct *board = NULL;
1473         struct ni_private *devpriv;
1474         unsigned int irq;
1475         int ret;
1476 
1477         if (context < ARRAY_SIZE(ni_boards))
1478                 board = &ni_boards[context];
1479         if (!board)
1480                 return -ENODEV;
1481         dev->board_ptr = board;
1482         dev->board_name = board->name;
1483 
1484         ret = comedi_pci_enable(dev);
1485         if (ret)
1486                 return ret;
1487 
1488         ret = ni_alloc_private(dev);
1489         if (ret)
1490                 return ret;
1491         devpriv = dev->private;
1492 
1493         devpriv->mite = mite_alloc(pcidev);
1494         if (!devpriv->mite)
1495                 return -ENOMEM;
1496 
1497         if (board->reg_type & ni_reg_m_series_mask) {
1498                 devpriv->stc_writew = &m_series_stc_writew;
1499                 devpriv->stc_readw = &m_series_stc_readw;
1500                 devpriv->stc_writel = &m_series_stc_writel;
1501                 devpriv->stc_readl = &m_series_stc_readl;
1502         } else {
1503                 devpriv->stc_writew = &e_series_win_out;
1504                 devpriv->stc_readw = &e_series_win_in;
1505                 devpriv->stc_writel = &win_out2;
1506                 devpriv->stc_readl = &win_in2;
1507         }
1508 
1509         ret = mite_setup(devpriv->mite);
1510         if (ret < 0) {
1511                 pr_warn("error setting up mite\n");
1512                 return ret;
1513         }
1514 
1515         devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1516         if (devpriv->ai_mite_ring == NULL)
1517                 return -ENOMEM;
1518         devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1519         if (devpriv->ao_mite_ring == NULL)
1520                 return -ENOMEM;
1521         devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1522         if (devpriv->cdo_mite_ring == NULL)
1523                 return -ENOMEM;
1524         devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1525         if (devpriv->gpct_mite_ring[0] == NULL)
1526                 return -ENOMEM;
1527         devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1528         if (devpriv->gpct_mite_ring[1] == NULL)
1529                 return -ENOMEM;
1530 
1531         if (board->reg_type & ni_reg_m_series_mask)
1532                 m_series_init_eeprom_buffer(dev);
1533         if (board->reg_type == ni_reg_6143)
1534                 init_6143(dev);
1535 
1536         irq = mite_irq(devpriv->mite);
1537         if (irq) {
1538                 ret = request_irq(irq, ni_E_interrupt, NI_E_IRQ_FLAGS,
1539                                   dev->board_name, dev);
1540                 if (ret == 0)
1541                         dev->irq = irq;
1542         }
1543 
1544         ret = ni_E_init(dev);
1545         if (ret < 0)
1546                 return ret;
1547 
1548         dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1549         dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1550         dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1551         dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1552         dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1553 
1554         return 0;
1555 }
1556 
1557 static int pcimio_ai_change(struct comedi_device *dev,
1558                             struct comedi_subdevice *s, unsigned long new_size)
1559 {
1560         struct ni_private *devpriv = dev->private;
1561         int ret;
1562 
1563         ret = mite_buf_change(devpriv->ai_mite_ring, s->async);
1564         if (ret < 0)
1565                 return ret;
1566 
1567         return 0;
1568 }
1569 
1570 static int pcimio_ao_change(struct comedi_device *dev,
1571                             struct comedi_subdevice *s, unsigned long new_size)
1572 {
1573         struct ni_private *devpriv = dev->private;
1574         int ret;
1575 
1576         ret = mite_buf_change(devpriv->ao_mite_ring, s->async);
1577         if (ret < 0)
1578                 return ret;
1579 
1580         return 0;
1581 }
1582 
1583 static int pcimio_gpct0_change(struct comedi_device *dev,
1584                                struct comedi_subdevice *s,
1585                                unsigned long new_size)
1586 {
1587         struct ni_private *devpriv = dev->private;
1588         int ret;
1589 
1590         ret = mite_buf_change(devpriv->gpct_mite_ring[0], s->async);
1591         if (ret < 0)
1592                 return ret;
1593 
1594         return 0;
1595 }
1596 
1597 static int pcimio_gpct1_change(struct comedi_device *dev,
1598                                struct comedi_subdevice *s,
1599                                unsigned long new_size)
1600 {
1601         struct ni_private *devpriv = dev->private;
1602         int ret;
1603 
1604         ret = mite_buf_change(devpriv->gpct_mite_ring[1], s->async);
1605         if (ret < 0)
1606                 return ret;
1607 
1608         return 0;
1609 }
1610 
1611 static int pcimio_dio_change(struct comedi_device *dev,
1612                              struct comedi_subdevice *s, unsigned long new_size)
1613 {
1614         struct ni_private *devpriv = dev->private;
1615         int ret;
1616 
1617         ret = mite_buf_change(devpriv->cdo_mite_ring, s->async);
1618         if (ret < 0)
1619                 return ret;
1620 
1621         return 0;
1622 }
1623 
1624 static struct comedi_driver ni_pcimio_driver = {
1625         .driver_name    = "ni_pcimio",
1626         .module         = THIS_MODULE,
1627         .auto_attach    = pcimio_auto_attach,
1628         .detach         = pcimio_detach,
1629 };
1630 
1631 static int ni_pcimio_pci_probe(struct pci_dev *dev,
1632                                const struct pci_device_id *id)
1633 {
1634         return comedi_pci_auto_config(dev, &ni_pcimio_driver, id->driver_data);
1635 }
1636 
1637 static const struct pci_device_id ni_pcimio_pci_table[] = {
1638         { PCI_VDEVICE(NI, 0x0162), BOARD_PCIMIO_16XE_50 },      /* 0x1620? */
1639         { PCI_VDEVICE(NI, 0x1170), BOARD_PCIMIO_16XE_10 },
1640         { PCI_VDEVICE(NI, 0x1180), BOARD_PCIMIO_16E_1 },
1641         { PCI_VDEVICE(NI, 0x1190), BOARD_PCIMIO_16E_4 },
1642         { PCI_VDEVICE(NI, 0x11b0), BOARD_PXI6070E },
1643         { PCI_VDEVICE(NI, 0x11c0), BOARD_PXI6040E },
1644         { PCI_VDEVICE(NI, 0x11d0), BOARD_PXI6030E },
1645         { PCI_VDEVICE(NI, 0x1270), BOARD_PCI6032E },
1646         { PCI_VDEVICE(NI, 0x1330), BOARD_PCI6031E },
1647         { PCI_VDEVICE(NI, 0x1340), BOARD_PCI6033E },
1648         { PCI_VDEVICE(NI, 0x1350), BOARD_PCI6071E },
1649         { PCI_VDEVICE(NI, 0x14e0), BOARD_PCI6110 },
1650         { PCI_VDEVICE(NI, 0x14f0), BOARD_PCI6111 },
1651         { PCI_VDEVICE(NI, 0x1580), BOARD_PXI6031E },
1652         { PCI_VDEVICE(NI, 0x15b0), BOARD_PXI6071E },
1653         { PCI_VDEVICE(NI, 0x1880), BOARD_PCI6711 },
1654         { PCI_VDEVICE(NI, 0x1870), BOARD_PCI6713 },
1655         { PCI_VDEVICE(NI, 0x18b0), BOARD_PCI6052E },
1656         { PCI_VDEVICE(NI, 0x18c0), BOARD_PXI6052E },
1657         { PCI_VDEVICE(NI, 0x2410), BOARD_PCI6733 },
1658         { PCI_VDEVICE(NI, 0x2420), BOARD_PXI6733 },
1659         { PCI_VDEVICE(NI, 0x2430), BOARD_PCI6731 },
1660         { PCI_VDEVICE(NI, 0x2890), BOARD_PCI6036E },
1661         { PCI_VDEVICE(NI, 0x28c0), BOARD_PCI6014 },
1662         { PCI_VDEVICE(NI, 0x2a60), BOARD_PCI6023E },
1663         { PCI_VDEVICE(NI, 0x2a70), BOARD_PCI6024E },
1664         { PCI_VDEVICE(NI, 0x2a80), BOARD_PCI6025E },
1665         { PCI_VDEVICE(NI, 0x2ab0), BOARD_PXI6025E },
1666         { PCI_VDEVICE(NI, 0x2b80), BOARD_PXI6713 },
1667         { PCI_VDEVICE(NI, 0x2b90), BOARD_PXI6711 },
1668         { PCI_VDEVICE(NI, 0x2c80), BOARD_PCI6035E },
1669         { PCI_VDEVICE(NI, 0x2ca0), BOARD_PCI6034E },
1670         { PCI_VDEVICE(NI, 0x70aa), BOARD_PCI6229 },
1671         { PCI_VDEVICE(NI, 0x70ab), BOARD_PCI6259 },
1672         { PCI_VDEVICE(NI, 0x70ac), BOARD_PCI6289 },
1673         { PCI_VDEVICE(NI, 0x70af), BOARD_PCI6221 },
1674         { PCI_VDEVICE(NI, 0x70b0), BOARD_PCI6220 },
1675         { PCI_VDEVICE(NI, 0x70b4), BOARD_PCI6250 },
1676         { PCI_VDEVICE(NI, 0x70b6), BOARD_PCI6280 },
1677         { PCI_VDEVICE(NI, 0x70b7), BOARD_PCI6254 },
1678         { PCI_VDEVICE(NI, 0x70b8), BOARD_PCI6251 },
1679         { PCI_VDEVICE(NI, 0x70bc), BOARD_PCI6284 },
1680         { PCI_VDEVICE(NI, 0x70bd), BOARD_PCI6281 },
1681         { PCI_VDEVICE(NI, 0x70bf), BOARD_PXI6281 },
1682         { PCI_VDEVICE(NI, 0x70c0), BOARD_PCI6143 },
1683         { PCI_VDEVICE(NI, 0x70f2), BOARD_PCI6224 },
1684         { PCI_VDEVICE(NI, 0x70f3), BOARD_PXI6224 },
1685         { PCI_VDEVICE(NI, 0x710d), BOARD_PXI6143 },
1686         { PCI_VDEVICE(NI, 0x716c), BOARD_PCI6225 },
1687         { PCI_VDEVICE(NI, 0x716d), BOARD_PXI6225 },
1688         { PCI_VDEVICE(NI, 0x717f), BOARD_PCIE6259 },
1689         { PCI_VDEVICE(NI, 0x71bc), BOARD_PCI6221_37PIN },
1690         { PCI_VDEVICE(NI, 0x717d), BOARD_PCIE6251 },
1691         { PCI_VDEVICE(NI, 0x72e8), BOARD_PXIE6251 },
1692         { 0 }
1693 };
1694 MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1695 
1696 static struct pci_driver ni_pcimio_pci_driver = {
1697         .name           = "ni_pcimio",
1698         .id_table       = ni_pcimio_pci_table,
1699         .probe          = ni_pcimio_pci_probe,
1700         .remove         = comedi_pci_auto_unconfig,
1701 };
1702 module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1703 
1704 MODULE_AUTHOR("Comedi http://www.comedi.org");
1705 MODULE_DESCRIPTION("Comedi low-level driver");
1706 MODULE_LICENSE("GPL");
1707 

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