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Linux/drivers/staging/comedi/drivers/ni_pcidio.c

  1 /*
  2     comedi/drivers/ni_pcidio.c
  3     driver for National Instruments PCI-DIO-32HS
  4 
  5     COMEDI - Linux Control and Measurement Device Interface
  6     Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org>
  7 
  8     This program is free software; you can redistribute it and/or modify
  9     it under the terms of the GNU General Public License as published by
 10     the Free Software Foundation; either version 2 of the License, or
 11     (at your option) any later version.
 12 
 13     This program is distributed in the hope that it will be useful,
 14     but WITHOUT ANY WARRANTY; without even the implied warranty of
 15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16     GNU General Public License for more details.
 17 */
 18 /*
 19 Driver: ni_pcidio
 20 Description: National Instruments PCI-DIO32HS, PCI-6533
 21 Author: ds
 22 Status: works
 23 Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio)
 24          [National Instruments] PXI-6533, PCI-6533 (pxi-6533)
 25          [National Instruments] PCI-6534 (pci-6534)
 26 Updated: Mon, 09 Jan 2012 14:27:23 +0000
 27 
 28 The DIO32HS board appears as one subdevice, with 32 channels.
 29 Each channel is individually I/O configurable.  The channel order
 30 is 0=A0, 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0.  The driver only
 31 supports simple digital I/O; no handshaking is supported.
 32 
 33 DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
 34 
 35 The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
 36 scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
 37 scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
 38 trailing edge.
 39 
 40 This driver could be easily modified to support AT-MIO32HS and
 41 AT-MIO96.
 42 
 43 The PCI-6534 requires a firmware upload after power-up to work, the
 44 firmware data and instructions for loading it with comedi_config
 45 it are contained in the
 46 comedi_nonfree_firmware tarball available from http://www.comedi.org
 47 */
 48 
 49 #define USE_DMA
 50 
 51 #include <linux/module.h>
 52 #include <linux/delay.h>
 53 #include <linux/interrupt.h>
 54 #include <linux/sched.h>
 55 
 56 #include "../comedidev.h"
 57 
 58 #include "comedi_fc.h"
 59 #include "mite.h"
 60 
 61 #define PCI_DIO_SIZE 4096
 62 #define PCI_MITE_SIZE 4096
 63 
 64 /* defines for the PCI-DIO-32HS */
 65 
 66 #define Window_Address                  4       /* W */
 67 #define Interrupt_And_Window_Status     4       /* R */
 68 #define IntStatus1                              (1<<0)
 69 #define IntStatus2                              (1<<1)
 70 #define WindowAddressStatus_mask                0x7c
 71 
 72 #define Master_DMA_And_Interrupt_Control 5      /* W */
 73 #define InterruptLine(x)                        ((x)&3)
 74 #define OpenInt                         (1<<2)
 75 #define Group_Status                    5       /* R */
 76 #define DataLeft                                (1<<0)
 77 #define Req                                     (1<<2)
 78 #define StopTrig                                (1<<3)
 79 
 80 #define Group_1_Flags                   6       /* R */
 81 #define Group_2_Flags                   7       /* R */
 82 #define TransferReady                           (1<<0)
 83 #define CountExpired                            (1<<1)
 84 #define Waited                          (1<<5)
 85 #define PrimaryTC                               (1<<6)
 86 #define SecondaryTC                             (1<<7)
 87   /* #define SerialRose */
 88   /* #define ReqRose */
 89   /* #define Paused */
 90 
 91 #define Group_1_First_Clear             6       /* W */
 92 #define Group_2_First_Clear             7       /* W */
 93 #define ClearWaited                             (1<<3)
 94 #define ClearPrimaryTC                  (1<<4)
 95 #define ClearSecondaryTC                        (1<<5)
 96 #define DMAReset                                (1<<6)
 97 #define FIFOReset                               (1<<7)
 98 #define ClearAll                                0xf8
 99 
100 #define Group_1_FIFO                    8       /* W */
101 #define Group_2_FIFO                    12      /* W */
102 
103 #define Transfer_Count                  20
104 #define Chip_ID_D                       24
105 #define Chip_ID_I                       25
106 #define Chip_ID_O                       26
107 #define Chip_Version                    27
108 #define Port_IO(x)                      (28+(x))
109 #define Port_Pin_Directions(x)          (32+(x))
110 #define Port_Pin_Mask(x)                (36+(x))
111 #define Port_Pin_Polarities(x)          (40+(x))
112 
113 #define Master_Clock_Routing            45
114 #define RTSIClocking(x)                 (((x)&3)<<4)
115 
116 #define Group_1_Second_Clear            46      /* W */
117 #define Group_2_Second_Clear            47      /* W */
118 #define ClearExpired                            (1<<0)
119 
120 #define Port_Pattern(x)                 (48+(x))
121 
122 #define Data_Path                       64
123 #define FIFOEnableA             (1<<0)
124 #define FIFOEnableB             (1<<1)
125 #define FIFOEnableC             (1<<2)
126 #define FIFOEnableD             (1<<3)
127 #define Funneling(x)            (((x)&3)<<4)
128 #define GroupDirection  (1<<7)
129 
130 #define Protocol_Register_1             65
131 #define OpMode                          Protocol_Register_1
132 #define RunMode(x)              ((x)&7)
133 #define Numbered                (1<<3)
134 
135 #define Protocol_Register_2             66
136 #define ClockReg                        Protocol_Register_2
137 #define ClockLine(x)            (((x)&3)<<5)
138 #define InvertStopTrig  (1<<7)
139 #define DataLatching(x)       (((x)&3)<<5)
140 
141 #define Protocol_Register_3             67
142 #define Sequence                        Protocol_Register_3
143 
144 #define Protocol_Register_14            68      /* 16 bit */
145 #define ClockSpeed                      Protocol_Register_14
146 
147 #define Protocol_Register_4             70
148 #define ReqReg                          Protocol_Register_4
149 #define ReqConditioning(x)      (((x)&7)<<3)
150 
151 #define Protocol_Register_5             71
152 #define BlockMode                       Protocol_Register_5
153 
154 #define FIFO_Control                    72
155 #define ReadyLevel(x)           ((x)&7)
156 
157 #define Protocol_Register_6             73
158 #define LinePolarities                  Protocol_Register_6
159 #define InvertAck               (1<<0)
160 #define InvertReq               (1<<1)
161 #define InvertClock             (1<<2)
162 #define InvertSerial            (1<<3)
163 #define OpenAck         (1<<4)
164 #define OpenClock               (1<<5)
165 
166 #define Protocol_Register_7             74
167 #define AckSer                          Protocol_Register_7
168 #define AckLine(x)              (((x)&3)<<2)
169 #define ExchangePins            (1<<7)
170 
171 #define Interrupt_Control               75
172   /* bits same as flags */
173 
174 #define DMA_Line_Control_Group1         76
175 #define DMA_Line_Control_Group2         108
176 /* channel zero is none */
177 static inline unsigned primary_DMAChannel_bits(unsigned channel)
178 {
179         return channel & 0x3;
180 }
181 
182 static inline unsigned secondary_DMAChannel_bits(unsigned channel)
183 {
184         return (channel << 2) & 0xc;
185 }
186 
187 #define Transfer_Size_Control           77
188 #define TransferWidth(x)        ((x)&3)
189 #define TransferLength(x)       (((x)&3)<<3)
190 #define RequireRLevel           (1<<5)
191 
192 #define Protocol_Register_15            79
193 #define DAQOptions                      Protocol_Register_15
194 #define StartSource(x)                  ((x)&0x3)
195 #define InvertStart                             (1<<2)
196 #define StopSource(x)                           (((x)&0x3)<<3)
197 #define ReqStart                                (1<<6)
198 #define PreStart                                (1<<7)
199 
200 #define Pattern_Detection               81
201 #define DetectionMethod                 (1<<0)
202 #define InvertMatch                             (1<<1)
203 #define IE_Pattern_Detection                    (1<<2)
204 
205 #define Protocol_Register_9             82
206 #define ReqDelay                        Protocol_Register_9
207 
208 #define Protocol_Register_10            83
209 #define ReqNotDelay                     Protocol_Register_10
210 
211 #define Protocol_Register_11            84
212 #define AckDelay                        Protocol_Register_11
213 
214 #define Protocol_Register_12            85
215 #define AckNotDelay                     Protocol_Register_12
216 
217 #define Protocol_Register_13            86
218 #define Data1Delay                      Protocol_Register_13
219 
220 #define Protocol_Register_8             88      /* 32 bit */
221 #define StartDelay                      Protocol_Register_8
222 
223 /* Firmware files for PCI-6524 */
224 #define FW_PCI_6534_MAIN                "ni6534a.bin"
225 #define FW_PCI_6534_SCARAB_DI           "niscrb01.bin"
226 #define FW_PCI_6534_SCARAB_DO           "niscrb02.bin"
227 MODULE_FIRMWARE(FW_PCI_6534_MAIN);
228 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DI);
229 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DO);
230 
231 enum pci_6534_firmware_registers {      /* 16 bit */
232         Firmware_Control_Register = 0x100,
233         Firmware_Status_Register = 0x104,
234         Firmware_Data_Register = 0x108,
235         Firmware_Mask_Register = 0x10c,
236         Firmware_Debug_Register = 0x110,
237 };
238 /* main fpga registers (32 bit)*/
239 enum pci_6534_fpga_registers {
240         FPGA_Control1_Register = 0x200,
241         FPGA_Control2_Register = 0x204,
242         FPGA_Irq_Mask_Register = 0x208,
243         FPGA_Status_Register = 0x20c,
244         FPGA_Signature_Register = 0x210,
245         FPGA_SCALS_Counter_Register = 0x280,    /*write-clear */
246         FPGA_SCAMS_Counter_Register = 0x284,    /*write-clear */
247         FPGA_SCBLS_Counter_Register = 0x288,    /*write-clear */
248         FPGA_SCBMS_Counter_Register = 0x28c,    /*write-clear */
249         FPGA_Temp_Control_Register = 0x2a0,
250         FPGA_DAR_Register = 0x2a8,
251         FPGA_ELC_Read_Register = 0x2b8,
252         FPGA_ELC_Write_Register = 0x2bc,
253 };
254 enum FPGA_Control_Bits {
255         FPGA_Enable_Bit = 0x8000,
256 };
257 
258 #define TIMER_BASE 50           /* nanoseconds */
259 
260 #ifdef USE_DMA
261 #define IntEn (CountExpired|Waited|PrimaryTC|SecondaryTC)
262 #else
263 #define IntEn (TransferReady|CountExpired|Waited|PrimaryTC|SecondaryTC)
264 #endif
265 
266 enum nidio_boardid {
267         BOARD_PCIDIO_32HS,
268         BOARD_PXI6533,
269         BOARD_PCI6534,
270 };
271 
272 struct nidio_board {
273         const char *name;
274         unsigned int uses_firmware:1;
275 };
276 
277 static const struct nidio_board nidio_boards[] = {
278         [BOARD_PCIDIO_32HS] = {
279                 .name           = "pci-dio-32hs",
280         },
281         [BOARD_PXI6533] = {
282                 .name           = "pxi-6533",
283         },
284         [BOARD_PCI6534] = {
285                 .name           = "pci-6534",
286                 .uses_firmware  = 1,
287         },
288 };
289 
290 struct nidio96_private {
291         struct mite_struct *mite;
292         int boardtype;
293         int dio;
294         unsigned short OpModeBits;
295         struct mite_channel *di_mite_chan;
296         struct mite_dma_descriptor_ring *di_mite_ring;
297         spinlock_t mite_channel_lock;
298 };
299 
300 static int ni_pcidio_cmdtest(struct comedi_device *dev,
301                              struct comedi_subdevice *s,
302                              struct comedi_cmd *cmd);
303 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
304 static int ni_pcidio_inttrig(struct comedi_device *dev,
305                              struct comedi_subdevice *s, unsigned int trignum);
306 static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode);
307 static int setup_mite_dma(struct comedi_device *dev,
308                           struct comedi_subdevice *s);
309 
310 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
311 {
312         struct nidio96_private *devpriv = dev->private;
313         unsigned long flags;
314 
315         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
316         BUG_ON(devpriv->di_mite_chan);
317         devpriv->di_mite_chan =
318             mite_request_channel_in_range(devpriv->mite,
319                                           devpriv->di_mite_ring, 1, 2);
320         if (devpriv->di_mite_chan == NULL) {
321                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
322                 comedi_error(dev, "failed to reserve mite dma channel.");
323                 return -EBUSY;
324         }
325         devpriv->di_mite_chan->dir = COMEDI_INPUT;
326         writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
327                secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
328                devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
329         mmiowb();
330         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
331         return 0;
332 }
333 
334 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
335 {
336         struct nidio96_private *devpriv = dev->private;
337         unsigned long flags;
338 
339         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
340         if (devpriv->di_mite_chan) {
341                 mite_dma_disarm(devpriv->di_mite_chan);
342                 mite_dma_reset(devpriv->di_mite_chan);
343                 mite_release_channel(devpriv->di_mite_chan);
344                 devpriv->di_mite_chan = NULL;
345                 writeb(primary_DMAChannel_bits(0) |
346                        secondary_DMAChannel_bits(0),
347                        devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
348                 mmiowb();
349         }
350         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
351 }
352 
353 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
354 {
355         struct nidio96_private *devpriv = dev->private;
356         unsigned long irq_flags;
357         int count;
358 
359         spin_lock_irqsave(&dev->spinlock, irq_flags);
360         spin_lock(&devpriv->mite_channel_lock);
361         if (devpriv->di_mite_chan)
362                 mite_sync_input_dma(devpriv->di_mite_chan, s->async);
363         spin_unlock(&devpriv->mite_channel_lock);
364         count = s->async->buf_write_count - s->async->buf_read_count;
365         spin_unlock_irqrestore(&dev->spinlock, irq_flags);
366         return count;
367 }
368 
369 static irqreturn_t nidio_interrupt(int irq, void *d)
370 {
371         struct comedi_device *dev = d;
372         struct nidio96_private *devpriv = dev->private;
373         struct comedi_subdevice *s = dev->read_subdev;
374         struct comedi_async *async = s->async;
375         struct mite_struct *mite = devpriv->mite;
376 
377         /* int i, j; */
378         unsigned int auxdata = 0;
379         unsigned short data1 = 0;
380         unsigned short data2 = 0;
381         int flags;
382         int status;
383         int work = 0;
384         unsigned int m_status = 0;
385 
386         /* interrupcions parasites */
387         if (!dev->attached) {
388                 /* assume it's from another card */
389                 return IRQ_NONE;
390         }
391 
392         /* Lock to avoid race with comedi_poll */
393         spin_lock(&dev->spinlock);
394 
395         status = readb(devpriv->mite->daq_io_addr +
396                        Interrupt_And_Window_Status);
397         flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
398 
399         spin_lock(&devpriv->mite_channel_lock);
400         if (devpriv->di_mite_chan)
401                 m_status = mite_get_status(devpriv->di_mite_chan);
402 
403         if (m_status & CHSR_INT) {
404                 if (m_status & CHSR_LINKC) {
405                         writel(CHOR_CLRLC,
406                                mite->mite_io_addr +
407                                MITE_CHOR(devpriv->di_mite_chan->channel));
408                         mite_sync_input_dma(devpriv->di_mite_chan, s->async);
409                         /* XXX need to byteswap */
410                 }
411                 if (m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_DRDY |
412                                  CHSR_DRQ1 | CHSR_MRDY)) {
413                         dev_dbg(dev->class_dev,
414                                 "unknown mite interrupt, disabling IRQ\n");
415                         async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
416                         disable_irq(dev->irq);
417                 }
418         }
419         spin_unlock(&devpriv->mite_channel_lock);
420 
421         while (status & DataLeft) {
422                 work++;
423                 if (work > 20) {
424                         dev_dbg(dev->class_dev, "too much work in interrupt\n");
425                         writeb(0x00,
426                                devpriv->mite->daq_io_addr +
427                                Master_DMA_And_Interrupt_Control);
428                         break;
429                 }
430 
431                 flags &= IntEn;
432 
433                 if (flags & TransferReady) {
434                         while (flags & TransferReady) {
435                                 work++;
436                                 if (work > 100) {
437                                         dev_dbg(dev->class_dev,
438                                                 "too much work in interrupt\n");
439                                         writeb(0x00,
440                                                devpriv->mite->daq_io_addr +
441                                                Master_DMA_And_Interrupt_Control
442                                               );
443                                         goto out;
444                                 }
445                                 auxdata =
446                                     readl(devpriv->mite->daq_io_addr +
447                                           Group_1_FIFO);
448                                 data1 = auxdata & 0xffff;
449                                 data2 = (auxdata & 0xffff0000) >> 16;
450                                 comedi_buf_put(async, data1);
451                                 comedi_buf_put(async, data2);
452                                 flags = readb(devpriv->mite->daq_io_addr +
453                                               Group_1_Flags);
454                         }
455                         async->events |= COMEDI_CB_BLOCK;
456                 }
457 
458                 if (flags & CountExpired) {
459                         writeb(ClearExpired,
460                                devpriv->mite->daq_io_addr +
461                                Group_1_Second_Clear);
462                         async->events |= COMEDI_CB_EOA;
463 
464                         writeb(0x00, devpriv->mite->daq_io_addr + OpMode);
465                         break;
466                 } else if (flags & Waited) {
467                         writeb(ClearWaited,
468                                devpriv->mite->daq_io_addr +
469                                Group_1_First_Clear);
470                         async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
471                         break;
472                 } else if (flags & PrimaryTC) {
473                         writeb(ClearPrimaryTC,
474                                devpriv->mite->daq_io_addr +
475                                Group_1_First_Clear);
476                         async->events |= COMEDI_CB_EOA;
477                 } else if (flags & SecondaryTC) {
478                         writeb(ClearSecondaryTC,
479                                devpriv->mite->daq_io_addr +
480                                Group_1_First_Clear);
481                         async->events |= COMEDI_CB_EOA;
482                 }
483 
484                 flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
485                 status = readb(devpriv->mite->daq_io_addr +
486                                Interrupt_And_Window_Status);
487         }
488 
489 out:
490         cfc_handle_events(dev, s);
491 #if 0
492         if (!tag) {
493                 writeb(0x03,
494                        devpriv->mite->daq_io_addr +
495                        Master_DMA_And_Interrupt_Control);
496         }
497 #endif
498 
499         spin_unlock(&dev->spinlock);
500         return IRQ_HANDLED;
501 }
502 
503 static int ni_pcidio_insn_config(struct comedi_device *dev,
504                                  struct comedi_subdevice *s,
505                                  struct comedi_insn *insn,
506                                  unsigned int *data)
507 {
508         struct nidio96_private *devpriv = dev->private;
509         int ret;
510 
511         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
512         if (ret)
513                 return ret;
514 
515         writel(s->io_bits, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
516 
517         return insn->n;
518 }
519 
520 static int ni_pcidio_insn_bits(struct comedi_device *dev,
521                                struct comedi_subdevice *s,
522                                struct comedi_insn *insn,
523                                unsigned int *data)
524 {
525         struct nidio96_private *devpriv = dev->private;
526 
527         if (comedi_dio_update_state(s, data))
528                 writel(s->state, devpriv->mite->daq_io_addr + Port_IO(0));
529 
530         data[1] = readl(devpriv->mite->daq_io_addr + Port_IO(0));
531 
532         return insn->n;
533 }
534 
535 static int ni_pcidio_cmdtest(struct comedi_device *dev,
536                              struct comedi_subdevice *s, struct comedi_cmd *cmd)
537 {
538         int err = 0;
539         int tmp;
540 
541         /* Step 1 : check if triggers are trivially valid */
542 
543         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
544         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
545                                         TRIG_TIMER | TRIG_EXT);
546         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
547         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
548         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
549 
550         if (err)
551                 return 1;
552 
553         /* Step 2a : make sure trigger sources are unique */
554 
555         err |= cfc_check_trigger_is_unique(cmd->start_src);
556         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
557         err |= cfc_check_trigger_is_unique(cmd->stop_src);
558 
559         /* Step 2b : and mutually compatible */
560 
561         if (err)
562                 return 2;
563 
564         /* Step 3: check if arguments are trivially valid */
565 
566         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
567 
568 #define MAX_SPEED       (TIMER_BASE)    /* in nanoseconds */
569 
570         if (cmd->scan_begin_src == TRIG_TIMER) {
571                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
572                                                  MAX_SPEED);
573                 /* no minimum speed */
574         } else {
575                 /* TRIG_EXT */
576                 /* should be level/edge, hi/lo specification here */
577                 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
578                         cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
579                         err |= -EINVAL;
580                 }
581         }
582 
583         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
584         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
585 
586         if (cmd->stop_src == TRIG_COUNT) {
587                 /* no limit */
588         } else {        /* TRIG_NONE */
589                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
590         }
591 
592         if (err)
593                 return 3;
594 
595         /* step 4: fix up any arguments */
596 
597         if (cmd->scan_begin_src == TRIG_TIMER) {
598                 tmp = cmd->scan_begin_arg;
599                 ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
600                                       cmd->flags & TRIG_ROUND_MASK);
601                 if (tmp != cmd->scan_begin_arg)
602                         err++;
603         }
604 
605         if (err)
606                 return 4;
607 
608         return 0;
609 }
610 
611 static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode)
612 {
613         int divider, base;
614 
615         base = TIMER_BASE;
616 
617         switch (round_mode) {
618         case TRIG_ROUND_NEAREST:
619         default:
620                 divider = (*nanosec + base / 2) / base;
621                 break;
622         case TRIG_ROUND_DOWN:
623                 divider = (*nanosec) / base;
624                 break;
625         case TRIG_ROUND_UP:
626                 divider = (*nanosec + base - 1) / base;
627                 break;
628         }
629 
630         *nanosec = base * divider;
631         return divider;
632 }
633 
634 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
635 {
636         struct nidio96_private *devpriv = dev->private;
637         struct comedi_cmd *cmd = &s->async->cmd;
638 
639         /* XXX configure ports for input */
640         writel(0x0000, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
641 
642         if (1) {
643                 /* enable fifos A B C D */
644                 writeb(0x0f, devpriv->mite->daq_io_addr + Data_Path);
645 
646                 /* set transfer width a 32 bits */
647                 writeb(TransferWidth(0) | TransferLength(0),
648                        devpriv->mite->daq_io_addr + Transfer_Size_Control);
649         } else {
650                 writeb(0x03, devpriv->mite->daq_io_addr + Data_Path);
651                 writeb(TransferWidth(3) | TransferLength(0),
652                        devpriv->mite->daq_io_addr + Transfer_Size_Control);
653         }
654 
655         /* protocol configuration */
656         if (cmd->scan_begin_src == TRIG_TIMER) {
657                 /* page 4-5, "input with internal REQs" */
658                 writeb(0, devpriv->mite->daq_io_addr + OpMode);
659                 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg);
660                 writeb(1, devpriv->mite->daq_io_addr + Sequence);
661                 writeb(0x04, devpriv->mite->daq_io_addr + ReqReg);
662                 writeb(4, devpriv->mite->daq_io_addr + BlockMode);
663                 writeb(3, devpriv->mite->daq_io_addr + LinePolarities);
664                 writeb(0xc0, devpriv->mite->daq_io_addr + AckSer);
665                 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
666                                              TRIG_ROUND_NEAREST),
667                        devpriv->mite->daq_io_addr + StartDelay);
668                 writeb(1, devpriv->mite->daq_io_addr + ReqDelay);
669                 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay);
670                 writeb(1, devpriv->mite->daq_io_addr + AckDelay);
671                 writeb(0x0b, devpriv->mite->daq_io_addr + AckNotDelay);
672                 writeb(0x01, devpriv->mite->daq_io_addr + Data1Delay);
673                 /* manual, page 4-5: ClockSpeed comment is incorrectly listed
674                  * on DAQOptions */
675                 writew(0, devpriv->mite->daq_io_addr + ClockSpeed);
676                 writeb(0, devpriv->mite->daq_io_addr + DAQOptions);
677         } else {
678                 /* TRIG_EXT */
679                 /* page 4-5, "input with external REQs" */
680                 writeb(0, devpriv->mite->daq_io_addr + OpMode);
681                 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg);
682                 writeb(0, devpriv->mite->daq_io_addr + Sequence);
683                 writeb(0x00, devpriv->mite->daq_io_addr + ReqReg);
684                 writeb(4, devpriv->mite->daq_io_addr + BlockMode);
685                 if (!(cmd->scan_begin_arg & CR_INVERT)) {
686                         /* Leading Edge pulse mode */
687                         writeb(0, devpriv->mite->daq_io_addr + LinePolarities);
688                 } else {
689                         /* Trailing Edge pulse mode */
690                         writeb(2, devpriv->mite->daq_io_addr + LinePolarities);
691                 }
692                 writeb(0x00, devpriv->mite->daq_io_addr + AckSer);
693                 writel(1, devpriv->mite->daq_io_addr + StartDelay);
694                 writeb(1, devpriv->mite->daq_io_addr + ReqDelay);
695                 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay);
696                 writeb(1, devpriv->mite->daq_io_addr + AckDelay);
697                 writeb(0x0C, devpriv->mite->daq_io_addr + AckNotDelay);
698                 writeb(0x10, devpriv->mite->daq_io_addr + Data1Delay);
699                 writew(0, devpriv->mite->daq_io_addr + ClockSpeed);
700                 writeb(0x60, devpriv->mite->daq_io_addr + DAQOptions);
701         }
702 
703         if (cmd->stop_src == TRIG_COUNT) {
704                 writel(cmd->stop_arg,
705                        devpriv->mite->daq_io_addr + Transfer_Count);
706         } else {
707                 /* XXX */
708         }
709 
710 #ifdef USE_DMA
711         writeb(ClearPrimaryTC | ClearSecondaryTC,
712                devpriv->mite->daq_io_addr + Group_1_First_Clear);
713 
714         {
715                 int retval = setup_mite_dma(dev, s);
716                 if (retval)
717                         return retval;
718         }
719 #else
720         writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
721 #endif
722         writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group2);
723 
724         /* clear and enable interrupts */
725         writeb(0xff, devpriv->mite->daq_io_addr + Group_1_First_Clear);
726         /* writeb(ClearExpired,
727                devpriv->mite->daq_io_addr+Group_1_Second_Clear); */
728 
729         writeb(IntEn, devpriv->mite->daq_io_addr + Interrupt_Control);
730         writeb(0x03,
731                devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control);
732 
733         if (cmd->stop_src == TRIG_NONE) {
734                 devpriv->OpModeBits = DataLatching(0) | RunMode(7);
735         } else {                /* TRIG_TIMER */
736                 devpriv->OpModeBits = Numbered | RunMode(7);
737         }
738         if (cmd->start_src == TRIG_NOW) {
739                 /* start */
740                 writeb(devpriv->OpModeBits,
741                        devpriv->mite->daq_io_addr + OpMode);
742                 s->async->inttrig = NULL;
743         } else {
744                 /* TRIG_INT */
745                 s->async->inttrig = ni_pcidio_inttrig;
746         }
747 
748         return 0;
749 }
750 
751 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
752 {
753         struct nidio96_private *devpriv = dev->private;
754         int retval;
755         unsigned long flags;
756 
757         retval = ni_pcidio_request_di_mite_channel(dev);
758         if (retval)
759                 return retval;
760 
761         /* write alloc the entire buffer */
762         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
763 
764         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
765         if (devpriv->di_mite_chan) {
766                 mite_prep_dma(devpriv->di_mite_chan, 32, 32);
767                 mite_dma_arm(devpriv->di_mite_chan);
768         } else
769                 retval = -EIO;
770         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
771 
772         return retval;
773 }
774 
775 static int ni_pcidio_inttrig(struct comedi_device *dev,
776                              struct comedi_subdevice *s, unsigned int trignum)
777 {
778         struct nidio96_private *devpriv = dev->private;
779 
780         if (trignum != 0)
781                 return -EINVAL;
782 
783         writeb(devpriv->OpModeBits, devpriv->mite->daq_io_addr + OpMode);
784         s->async->inttrig = NULL;
785 
786         return 1;
787 }
788 
789 static int ni_pcidio_cancel(struct comedi_device *dev,
790                             struct comedi_subdevice *s)
791 {
792         struct nidio96_private *devpriv = dev->private;
793 
794         writeb(0x00,
795                devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control);
796         ni_pcidio_release_di_mite_channel(dev);
797 
798         return 0;
799 }
800 
801 static int ni_pcidio_change(struct comedi_device *dev,
802                             struct comedi_subdevice *s, unsigned long new_size)
803 {
804         struct nidio96_private *devpriv = dev->private;
805         int ret;
806 
807         ret = mite_buf_change(devpriv->di_mite_ring, s->async);
808         if (ret < 0)
809                 return ret;
810 
811         memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
812 
813         return 0;
814 }
815 
816 static int pci_6534_load_fpga(struct comedi_device *dev,
817                               const u8 *data, size_t data_len,
818                               unsigned long context)
819 {
820         struct nidio96_private *devpriv = dev->private;
821         static const int timeout = 1000;
822         int fpga_index = context;
823         int i;
824         size_t j;
825 
826         writew(0x80 | fpga_index,
827                devpriv->mite->daq_io_addr + Firmware_Control_Register);
828         writew(0xc0 | fpga_index,
829                devpriv->mite->daq_io_addr + Firmware_Control_Register);
830         for (i = 0;
831              (readw(devpriv->mite->daq_io_addr +
832                     Firmware_Status_Register) & 0x2) == 0 && i < timeout; ++i) {
833                 udelay(1);
834         }
835         if (i == timeout) {
836                 dev_warn(dev->class_dev,
837                          "ni_pcidio: failed to load fpga %i, waiting for status 0x2\n",
838                          fpga_index);
839                 return -EIO;
840         }
841         writew(0x80 | fpga_index,
842                devpriv->mite->daq_io_addr + Firmware_Control_Register);
843         for (i = 0;
844              readw(devpriv->mite->daq_io_addr + Firmware_Status_Register) !=
845              0x3 && i < timeout; ++i) {
846                 udelay(1);
847         }
848         if (i == timeout) {
849                 dev_warn(dev->class_dev,
850                          "ni_pcidio: failed to load fpga %i, waiting for status 0x3\n",
851                          fpga_index);
852                 return -EIO;
853         }
854         for (j = 0; j + 1 < data_len;) {
855                 unsigned int value = data[j++];
856                 value |= data[j++] << 8;
857                 writew(value,
858                        devpriv->mite->daq_io_addr + Firmware_Data_Register);
859                 for (i = 0;
860                      (readw(devpriv->mite->daq_io_addr +
861                             Firmware_Status_Register) & 0x2) == 0
862                      && i < timeout; ++i) {
863                         udelay(1);
864                 }
865                 if (i == timeout) {
866                         dev_warn(dev->class_dev,
867                                  "ni_pcidio: failed to load word into fpga %i\n",
868                                  fpga_index);
869                         return -EIO;
870                 }
871                 if (need_resched())
872                         schedule();
873         }
874         writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register);
875         return 0;
876 }
877 
878 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
879 {
880         return pci_6534_load_fpga(dev, NULL, 0, fpga_index);
881 }
882 
883 static int pci_6534_reset_fpgas(struct comedi_device *dev)
884 {
885         struct nidio96_private *devpriv = dev->private;
886         int ret;
887         int i;
888 
889         writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register);
890         for (i = 0; i < 3; ++i) {
891                 ret = pci_6534_reset_fpga(dev, i);
892                 if (ret < 0)
893                         break;
894         }
895         writew(0x0, devpriv->mite->daq_io_addr + Firmware_Mask_Register);
896         return ret;
897 }
898 
899 static void pci_6534_init_main_fpga(struct comedi_device *dev)
900 {
901         struct nidio96_private *devpriv = dev->private;
902 
903         writel(0, devpriv->mite->daq_io_addr + FPGA_Control1_Register);
904         writel(0, devpriv->mite->daq_io_addr + FPGA_Control2_Register);
905         writel(0, devpriv->mite->daq_io_addr + FPGA_SCALS_Counter_Register);
906         writel(0, devpriv->mite->daq_io_addr + FPGA_SCAMS_Counter_Register);
907         writel(0, devpriv->mite->daq_io_addr + FPGA_SCBLS_Counter_Register);
908         writel(0, devpriv->mite->daq_io_addr + FPGA_SCBMS_Counter_Register);
909 }
910 
911 static int pci_6534_upload_firmware(struct comedi_device *dev)
912 {
913         struct nidio96_private *devpriv = dev->private;
914         static const char *const fw_file[3] = {
915                 FW_PCI_6534_SCARAB_DI,  /* loaded into scarab A for DI */
916                 FW_PCI_6534_SCARAB_DO,  /* loaded into scarab B for DO */
917                 FW_PCI_6534_MAIN,       /* loaded into main FPGA */
918         };
919         int ret;
920         int n;
921 
922         ret = pci_6534_reset_fpgas(dev);
923         if (ret < 0)
924                 return ret;
925         /* load main FPGA first, then the two scarabs */
926         for (n = 2; n >= 0; n--) {
927                 ret = comedi_load_firmware(dev, &devpriv->mite->pcidev->dev,
928                                            fw_file[n],
929                                            pci_6534_load_fpga, n);
930                 if (ret == 0 && n == 2)
931                         pci_6534_init_main_fpga(dev);
932                 if (ret < 0)
933                         break;
934         }
935         return ret;
936 }
937 
938 static void nidio_reset_board(struct comedi_device *dev)
939 {
940         struct nidio96_private *devpriv = dev->private;
941         void __iomem *daq_mmio = devpriv->mite->daq_io_addr;
942 
943         writel(0, daq_mmio + Port_IO(0));
944         writel(0, daq_mmio + Port_Pin_Directions(0));
945         writel(0, daq_mmio + Port_Pin_Mask(0));
946 
947         /* disable interrupts on board */
948         writeb(0, daq_mmio + Master_DMA_And_Interrupt_Control);
949 }
950 
951 static int nidio_auto_attach(struct comedi_device *dev,
952                              unsigned long context)
953 {
954         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
955         const struct nidio_board *board = NULL;
956         struct nidio96_private *devpriv;
957         struct comedi_subdevice *s;
958         int ret;
959         unsigned int irq;
960 
961         if (context < ARRAY_SIZE(nidio_boards))
962                 board = &nidio_boards[context];
963         if (!board)
964                 return -ENODEV;
965         dev->board_ptr = board;
966         dev->board_name = board->name;
967 
968         ret = comedi_pci_enable(dev);
969         if (ret)
970                 return ret;
971 
972         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
973         if (!devpriv)
974                 return -ENOMEM;
975 
976         spin_lock_init(&devpriv->mite_channel_lock);
977 
978         devpriv->mite = mite_alloc(pcidev);
979         if (!devpriv->mite)
980                 return -ENOMEM;
981 
982         ret = mite_setup(devpriv->mite);
983         if (ret < 0) {
984                 dev_warn(dev->class_dev, "error setting up mite\n");
985                 return ret;
986         }
987 
988         devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
989         if (devpriv->di_mite_ring == NULL)
990                 return -ENOMEM;
991 
992         if (board->uses_firmware) {
993                 ret = pci_6534_upload_firmware(dev);
994                 if (ret < 0)
995                         return ret;
996         }
997 
998         nidio_reset_board(dev);
999 
1000         ret = comedi_alloc_subdevices(dev, 1);
1001         if (ret)
1002                 return ret;
1003 
1004         dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
1005                  readb(devpriv->mite->daq_io_addr + Chip_Version));
1006 
1007         s = &dev->subdevices[0];
1008 
1009         dev->read_subdev = s;
1010         s->type = COMEDI_SUBD_DIO;
1011         s->subdev_flags =
1012                 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
1013                 SDF_CMD_READ;
1014         s->n_chan = 32;
1015         s->range_table = &range_digital;
1016         s->maxdata = 1;
1017         s->insn_config = &ni_pcidio_insn_config;
1018         s->insn_bits = &ni_pcidio_insn_bits;
1019         s->do_cmd = &ni_pcidio_cmd;
1020         s->do_cmdtest = &ni_pcidio_cmdtest;
1021         s->cancel = &ni_pcidio_cancel;
1022         s->len_chanlist = 32;   /* XXX */
1023         s->buf_change = &ni_pcidio_change;
1024         s->async_dma_dir = DMA_BIDIRECTIONAL;
1025         s->poll = &ni_pcidio_poll;
1026 
1027         irq = mite_irq(devpriv->mite);
1028         if (irq) {
1029                 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
1030                                   dev->board_name, dev);
1031                 if (ret == 0)
1032                         dev->irq = irq;
1033         }
1034 
1035         return 0;
1036 }
1037 
1038 static void nidio_detach(struct comedi_device *dev)
1039 {
1040         struct nidio96_private *devpriv = dev->private;
1041 
1042         if (dev->irq)
1043                 free_irq(dev->irq, dev);
1044         if (devpriv) {
1045                 if (devpriv->di_mite_ring) {
1046                         mite_free_ring(devpriv->di_mite_ring);
1047                         devpriv->di_mite_ring = NULL;
1048                 }
1049                 if (devpriv->mite) {
1050                         mite_unsetup(devpriv->mite);
1051                         mite_free(devpriv->mite);
1052                 }
1053         }
1054         comedi_pci_disable(dev);
1055 }
1056 
1057 static struct comedi_driver ni_pcidio_driver = {
1058         .driver_name    = "ni_pcidio",
1059         .module         = THIS_MODULE,
1060         .auto_attach    = nidio_auto_attach,
1061         .detach         = nidio_detach,
1062 };
1063 
1064 static int ni_pcidio_pci_probe(struct pci_dev *dev,
1065                                const struct pci_device_id *id)
1066 {
1067         return comedi_pci_auto_config(dev, &ni_pcidio_driver, id->driver_data);
1068 }
1069 
1070 static const struct pci_device_id ni_pcidio_pci_table[] = {
1071         { PCI_VDEVICE(NI, 0x1150), BOARD_PCIDIO_32HS },
1072         { PCI_VDEVICE(NI, 0x12b0), BOARD_PCI6534 },
1073         { PCI_VDEVICE(NI, 0x1320), BOARD_PXI6533 },
1074         { 0 }
1075 };
1076 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
1077 
1078 static struct pci_driver ni_pcidio_pci_driver = {
1079         .name           = "ni_pcidio",
1080         .id_table       = ni_pcidio_pci_table,
1081         .probe          = ni_pcidio_pci_probe,
1082         .remove         = comedi_pci_auto_unconfig,
1083 };
1084 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
1085 
1086 MODULE_AUTHOR("Comedi http://www.comedi.org");
1087 MODULE_DESCRIPTION("Comedi low-level driver");
1088 MODULE_LICENSE("GPL");
1089 

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