Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/staging/comedi/drivers/ni_660x.c

  1 /*
  2   comedi/drivers/ni_660x.c
  3   Hardware driver for NI 660x devices
  4 
  5   This program is free software; you can redistribute it and/or modify
  6   it under the terms of the GNU General Public License as published by
  7   the Free Software Foundation; either version 2 of the License, or
  8   (at your option) any later version.
  9 
 10   This program is distributed in the hope that it will be useful,
 11   but WITHOUT ANY WARRANTY; without even the implied warranty of
 12   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13   GNU General Public License for more details.
 14 */
 15 
 16 /*
 17  * Driver: ni_660x
 18  * Description: National Instruments 660x counter/timer boards
 19  * Devices: [National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602,
 20  *   PXI-6608, PXI-6624
 21  * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
 22  *   Herman.Bruyninckx@mech.kuleuven.ac.be,
 23  *   Wim.Meeussen@mech.kuleuven.ac.be,
 24  *   Klaas.Gadeyne@mech.kuleuven.ac.be,
 25  *   Frank Mori Hess <fmhess@users.sourceforge.net>
 26  * Updated: Fri, 15 Mar 2013 10:47:56 +0000
 27  * Status: experimental
 28  *
 29  * Encoders work.  PulseGeneration (both single pulse and pulse train)
 30  * works.  Buffered commands work for input but not output.
 31  * 
 32  * References:
 33  * DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
 34  * DAQ 6601/6602 User Manual (NI 322137B-01)
 35  */
 36 
 37 #include <linux/module.h>
 38 #include <linux/pci.h>
 39 #include <linux/interrupt.h>
 40 
 41 #include "../comedidev.h"
 42 
 43 #include "comedi_fc.h"
 44 #include "mite.h"
 45 #include "ni_tio.h"
 46 
 47 enum ni_660x_constants {
 48         min_counter_pfi_chan = 8,
 49         max_dio_pfi_chan = 31,
 50         counters_per_chip = 4
 51 };
 52 
 53 #define NUM_PFI_CHANNELS 40
 54 /* really there are only up to 3 dma channels, but the register layout allows
 55 for 4 */
 56 #define MAX_DMA_CHANNEL 4
 57 
 58 /* See Register-Level Programmer Manual page 3.1 */
 59 enum ni_660x_register {
 60         NI660X_G0_INT_ACK,
 61         NI660X_G0_STATUS,
 62         NI660X_G1_INT_ACK,
 63         NI660X_G1_STATUS,
 64         NI660X_G01_STATUS,
 65         NI660X_G0_CMD,
 66         NI660X_STC_DIO_PARALLEL_INPUT,
 67         NI660X_G1_CMD,
 68         NI660X_G0_HW_SAVE,
 69         NI660X_G1_HW_SAVE,
 70         NI660X_STC_DIO_OUTPUT,
 71         NI660X_STC_DIO_CONTROL,
 72         NI660X_G0_SW_SAVE,
 73         NI660X_G1_SW_SAVE,
 74         NI660X_G0_MODE,
 75         NI660X_G01_STATUS1,
 76         NI660X_G1_MODE,
 77         NI660X_STC_DIO_SERIAL_INPUT,
 78         NI660X_G0_LOADA,
 79         NI660X_G01_STATUS2,
 80         NI660X_G0_LOADB,
 81         NI660X_G1_LOADA,
 82         NI660X_G1_LOADB,
 83         NI660X_G0_INPUT_SEL,
 84         NI660X_G1_INPUT_SEL,
 85         NI660X_G0_AUTO_INC,
 86         NI660X_G1_AUTO_INC,
 87         NI660X_G01_RESET,
 88         NI660X_G0_INT_ENA,
 89         NI660X_G1_INT_ENA,
 90         NI660X_G0_CNT_MODE,
 91         NI660X_G1_CNT_MODE,
 92         NI660X_G0_GATE2,
 93         NI660X_G1_GATE2,
 94         NI660X_G0_DMA_CFG,
 95         NI660X_G0_DMA_STATUS,
 96         NI660X_G1_DMA_CFG,
 97         NI660X_G1_DMA_STATUS,
 98         NI660X_G2_INT_ACK,
 99         NI660X_G2_STATUS,
100         NI660X_G3_INT_ACK,
101         NI660X_G3_STATUS,
102         NI660X_G23_STATUS,
103         NI660X_G2_CMD,
104         NI660X_G3_CMD,
105         NI660X_G2_HW_SAVE,
106         NI660X_G3_HW_SAVE,
107         NI660X_G2_SW_SAVE,
108         NI660X_G3_SW_SAVE,
109         NI660X_G2_MODE,
110         NI660X_G23_STATUS1,
111         NI660X_G3_MODE,
112         NI660X_G2_LOADA,
113         NI660X_G23_STATUS2,
114         NI660X_G2_LOADB,
115         NI660X_G3_LOADA,
116         NI660X_G3_LOADB,
117         NI660X_G2_INPUT_SEL,
118         NI660X_G3_INPUT_SEL,
119         NI660X_G2_AUTO_INC,
120         NI660X_G3_AUTO_INC,
121         NI660X_G23_RESET,
122         NI660X_G2_INT_ENA,
123         NI660X_G3_INT_ENA,
124         NI660X_G2_CNT_MODE,
125         NI660X_G3_CNT_MODE,
126         NI660X_G3_GATE2,
127         NI660X_G2_GATE2,
128         NI660X_G2_DMA_CFG,
129         NI660X_G2_DMA_STATUS,
130         NI660X_G3_DMA_CFG,
131         NI660X_G3_DMA_STATUS,
132         NI660X_DIO32_INPUT,
133         NI660X_DIO32_OUTPUT,
134         NI660X_CLK_CFG,
135         NI660X_GLOBAL_INT_STATUS,
136         NI660X_DMA_CFG,
137         NI660X_GLOBAL_INT_CFG,
138         NI660X_IO_CFG_0_1,
139         NI660X_IO_CFG_2_3,
140         NI660X_IO_CFG_4_5,
141         NI660X_IO_CFG_6_7,
142         NI660X_IO_CFG_8_9,
143         NI660X_IO_CFG_10_11,
144         NI660X_IO_CFG_12_13,
145         NI660X_IO_CFG_14_15,
146         NI660X_IO_CFG_16_17,
147         NI660X_IO_CFG_18_19,
148         NI660X_IO_CFG_20_21,
149         NI660X_IO_CFG_22_23,
150         NI660X_IO_CFG_24_25,
151         NI660X_IO_CFG_26_27,
152         NI660X_IO_CFG_28_29,
153         NI660X_IO_CFG_30_31,
154         NI660X_IO_CFG_32_33,
155         NI660X_IO_CFG_34_35,
156         NI660X_IO_CFG_36_37,
157         NI660X_IO_CFG_38_39,
158         NI660X_NUM_REGS,
159 };
160 
161 static inline unsigned IOConfigReg(unsigned pfi_channel)
162 {
163         unsigned reg = NI660X_IO_CFG_0_1 + pfi_channel / 2;
164         BUG_ON(reg > NI660X_IO_CFG_38_39);
165         return reg;
166 }
167 
168 enum ni_660x_register_width {
169         DATA_1B,
170         DATA_2B,
171         DATA_4B
172 };
173 
174 enum ni_660x_register_direction {
175         NI_660x_READ,
176         NI_660x_WRITE,
177         NI_660x_READ_WRITE
178 };
179 
180 enum ni_660x_pfi_output_select {
181         pfi_output_select_high_Z = 0,
182         pfi_output_select_counter = 1,
183         pfi_output_select_do = 2,
184         num_pfi_output_selects
185 };
186 
187 enum ni_660x_subdevices {
188         NI_660X_DIO_SUBDEV = 1,
189         NI_660X_GPCT_SUBDEV_0 = 2
190 };
191 static inline unsigned NI_660X_GPCT_SUBDEV(unsigned index)
192 {
193         return NI_660X_GPCT_SUBDEV_0 + index;
194 }
195 
196 struct NI_660xRegisterData {
197 
198         const char *name;       /*  Register Name */
199         int offset;             /*  Offset from base address from GPCT chip */
200         enum ni_660x_register_direction direction;
201         enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */
202 };
203 
204 static const struct NI_660xRegisterData registerData[NI660X_NUM_REGS] = {
205         {"G0 Interrupt Acknowledge", 0x004, NI_660x_WRITE, DATA_2B},
206         {"G0 Status Register", 0x004, NI_660x_READ, DATA_2B},
207         {"G1 Interrupt Acknowledge", 0x006, NI_660x_WRITE, DATA_2B},
208         {"G1 Status Register", 0x006, NI_660x_READ, DATA_2B},
209         {"G01 Status Register ", 0x008, NI_660x_READ, DATA_2B},
210         {"G0 Command Register", 0x00C, NI_660x_WRITE, DATA_2B},
211         {"STC DIO Parallel Input", 0x00E, NI_660x_READ, DATA_2B},
212         {"G1 Command Register", 0x00E, NI_660x_WRITE, DATA_2B},
213         {"G0 HW Save Register", 0x010, NI_660x_READ, DATA_4B},
214         {"G1 HW Save Register", 0x014, NI_660x_READ, DATA_4B},
215         {"STC DIO Output", 0x014, NI_660x_WRITE, DATA_2B},
216         {"STC DIO Control", 0x016, NI_660x_WRITE, DATA_2B},
217         {"G0 SW Save Register", 0x018, NI_660x_READ, DATA_4B},
218         {"G1 SW Save Register", 0x01C, NI_660x_READ, DATA_4B},
219         {"G0 Mode Register", 0x034, NI_660x_WRITE, DATA_2B},
220         {"G01 Joint Status 1 Register", 0x036, NI_660x_READ, DATA_2B},
221         {"G1 Mode Register", 0x036, NI_660x_WRITE, DATA_2B},
222         {"STC DIO Serial Input", 0x038, NI_660x_READ, DATA_2B},
223         {"G0 Load A Register", 0x038, NI_660x_WRITE, DATA_4B},
224         {"G01 Joint Status 2 Register", 0x03A, NI_660x_READ, DATA_2B},
225         {"G0 Load B Register", 0x03C, NI_660x_WRITE, DATA_4B},
226         {"G1 Load A Register", 0x040, NI_660x_WRITE, DATA_4B},
227         {"G1 Load B Register", 0x044, NI_660x_WRITE, DATA_4B},
228         {"G0 Input Select Register", 0x048, NI_660x_WRITE, DATA_2B},
229         {"G1 Input Select Register", 0x04A, NI_660x_WRITE, DATA_2B},
230         {"G0 Autoincrement Register", 0x088, NI_660x_WRITE, DATA_2B},
231         {"G1 Autoincrement Register", 0x08A, NI_660x_WRITE, DATA_2B},
232         {"G01 Joint Reset Register", 0x090, NI_660x_WRITE, DATA_2B},
233         {"G0 Interrupt Enable", 0x092, NI_660x_WRITE, DATA_2B},
234         {"G1 Interrupt Enable", 0x096, NI_660x_WRITE, DATA_2B},
235         {"G0 Counting Mode Register", 0x0B0, NI_660x_WRITE, DATA_2B},
236         {"G1 Counting Mode Register", 0x0B2, NI_660x_WRITE, DATA_2B},
237         {"G0 Second Gate Register", 0x0B4, NI_660x_WRITE, DATA_2B},
238         {"G1 Second Gate Register", 0x0B6, NI_660x_WRITE, DATA_2B},
239         {"G0 DMA Config Register", 0x0B8, NI_660x_WRITE, DATA_2B},
240         {"G0 DMA Status Register", 0x0B8, NI_660x_READ, DATA_2B},
241         {"G1 DMA Config Register", 0x0BA, NI_660x_WRITE, DATA_2B},
242         {"G1 DMA Status Register", 0x0BA, NI_660x_READ, DATA_2B},
243         {"G2 Interrupt Acknowledge", 0x104, NI_660x_WRITE, DATA_2B},
244         {"G2 Status Register", 0x104, NI_660x_READ, DATA_2B},
245         {"G3 Interrupt Acknowledge", 0x106, NI_660x_WRITE, DATA_2B},
246         {"G3 Status Register", 0x106, NI_660x_READ, DATA_2B},
247         {"G23 Status Register", 0x108, NI_660x_READ, DATA_2B},
248         {"G2 Command Register", 0x10C, NI_660x_WRITE, DATA_2B},
249         {"G3 Command Register", 0x10E, NI_660x_WRITE, DATA_2B},
250         {"G2 HW Save Register", 0x110, NI_660x_READ, DATA_4B},
251         {"G3 HW Save Register", 0x114, NI_660x_READ, DATA_4B},
252         {"G2 SW Save Register", 0x118, NI_660x_READ, DATA_4B},
253         {"G3 SW Save Register", 0x11C, NI_660x_READ, DATA_4B},
254         {"G2 Mode Register", 0x134, NI_660x_WRITE, DATA_2B},
255         {"G23 Joint Status 1 Register", 0x136, NI_660x_READ, DATA_2B},
256         {"G3 Mode Register", 0x136, NI_660x_WRITE, DATA_2B},
257         {"G2 Load A Register", 0x138, NI_660x_WRITE, DATA_4B},
258         {"G23 Joint Status 2 Register", 0x13A, NI_660x_READ, DATA_2B},
259         {"G2 Load B Register", 0x13C, NI_660x_WRITE, DATA_4B},
260         {"G3 Load A Register", 0x140, NI_660x_WRITE, DATA_4B},
261         {"G3 Load B Register", 0x144, NI_660x_WRITE, DATA_4B},
262         {"G2 Input Select Register", 0x148, NI_660x_WRITE, DATA_2B},
263         {"G3 Input Select Register", 0x14A, NI_660x_WRITE, DATA_2B},
264         {"G2 Autoincrement Register", 0x188, NI_660x_WRITE, DATA_2B},
265         {"G3 Autoincrement Register", 0x18A, NI_660x_WRITE, DATA_2B},
266         {"G23 Joint Reset Register", 0x190, NI_660x_WRITE, DATA_2B},
267         {"G2 Interrupt Enable", 0x192, NI_660x_WRITE, DATA_2B},
268         {"G3 Interrupt Enable", 0x196, NI_660x_WRITE, DATA_2B},
269         {"G2 Counting Mode Register", 0x1B0, NI_660x_WRITE, DATA_2B},
270         {"G3 Counting Mode Register", 0x1B2, NI_660x_WRITE, DATA_2B},
271         {"G3 Second Gate Register", 0x1B6, NI_660x_WRITE, DATA_2B},
272         {"G2 Second Gate Register", 0x1B4, NI_660x_WRITE, DATA_2B},
273         {"G2 DMA Config Register", 0x1B8, NI_660x_WRITE, DATA_2B},
274         {"G2 DMA Status Register", 0x1B8, NI_660x_READ, DATA_2B},
275         {"G3 DMA Config Register", 0x1BA, NI_660x_WRITE, DATA_2B},
276         {"G3 DMA Status Register", 0x1BA, NI_660x_READ, DATA_2B},
277         {"32 bit Digital Input", 0x414, NI_660x_READ, DATA_4B},
278         {"32 bit Digital Output", 0x510, NI_660x_WRITE, DATA_4B},
279         {"Clock Config Register", 0x73C, NI_660x_WRITE, DATA_4B},
280         {"Global Interrupt Status Register", 0x754, NI_660x_READ, DATA_4B},
281         {"DMA Configuration Register", 0x76C, NI_660x_WRITE, DATA_4B},
282         {"Global Interrupt Config Register", 0x770, NI_660x_WRITE, DATA_4B},
283         {"IO Config Register 0-1", 0x77C, NI_660x_READ_WRITE, DATA_2B},
284         {"IO Config Register 2-3", 0x77E, NI_660x_READ_WRITE, DATA_2B},
285         {"IO Config Register 4-5", 0x780, NI_660x_READ_WRITE, DATA_2B},
286         {"IO Config Register 6-7", 0x782, NI_660x_READ_WRITE, DATA_2B},
287         {"IO Config Register 8-9", 0x784, NI_660x_READ_WRITE, DATA_2B},
288         {"IO Config Register 10-11", 0x786, NI_660x_READ_WRITE, DATA_2B},
289         {"IO Config Register 12-13", 0x788, NI_660x_READ_WRITE, DATA_2B},
290         {"IO Config Register 14-15", 0x78A, NI_660x_READ_WRITE, DATA_2B},
291         {"IO Config Register 16-17", 0x78C, NI_660x_READ_WRITE, DATA_2B},
292         {"IO Config Register 18-19", 0x78E, NI_660x_READ_WRITE, DATA_2B},
293         {"IO Config Register 20-21", 0x790, NI_660x_READ_WRITE, DATA_2B},
294         {"IO Config Register 22-23", 0x792, NI_660x_READ_WRITE, DATA_2B},
295         {"IO Config Register 24-25", 0x794, NI_660x_READ_WRITE, DATA_2B},
296         {"IO Config Register 26-27", 0x796, NI_660x_READ_WRITE, DATA_2B},
297         {"IO Config Register 28-29", 0x798, NI_660x_READ_WRITE, DATA_2B},
298         {"IO Config Register 30-31", 0x79A, NI_660x_READ_WRITE, DATA_2B},
299         {"IO Config Register 32-33", 0x79C, NI_660x_READ_WRITE, DATA_2B},
300         {"IO Config Register 34-35", 0x79E, NI_660x_READ_WRITE, DATA_2B},
301         {"IO Config Register 36-37", 0x7A0, NI_660x_READ_WRITE, DATA_2B},
302         {"IO Config Register 38-39", 0x7A2, NI_660x_READ_WRITE, DATA_2B}
303 };
304 
305 /* kind of ENABLE for the second counter */
306 enum clock_config_register_bits {
307         CounterSwap = 0x1 << 21
308 };
309 
310 /* ioconfigreg */
311 static inline unsigned ioconfig_bitshift(unsigned pfi_channel)
312 {
313         if (pfi_channel % 2)
314                 return 0;
315         else
316                 return 8;
317 }
318 
319 static inline unsigned pfi_output_select_mask(unsigned pfi_channel)
320 {
321         return 0x3 << ioconfig_bitshift(pfi_channel);
322 }
323 
324 static inline unsigned pfi_output_select_bits(unsigned pfi_channel,
325                                               unsigned output_select)
326 {
327         return (output_select & 0x3) << ioconfig_bitshift(pfi_channel);
328 }
329 
330 static inline unsigned pfi_input_select_mask(unsigned pfi_channel)
331 {
332         return 0x7 << (4 + ioconfig_bitshift(pfi_channel));
333 }
334 
335 static inline unsigned pfi_input_select_bits(unsigned pfi_channel,
336                                              unsigned input_select)
337 {
338         return (input_select & 0x7) << (4 + ioconfig_bitshift(pfi_channel));
339 }
340 
341 /* dma configuration register bits */
342 static inline unsigned dma_select_mask(unsigned dma_channel)
343 {
344         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
345         return 0x1f << (8 * dma_channel);
346 }
347 
348 enum dma_selection {
349         dma_selection_none = 0x1f,
350 };
351 
352 static inline unsigned dma_select_bits(unsigned dma_channel, unsigned selection)
353 {
354         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
355         return (selection << (8 * dma_channel)) & dma_select_mask(dma_channel);
356 }
357 
358 static inline unsigned dma_reset_bit(unsigned dma_channel)
359 {
360         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
361         return 0x80 << (8 * dma_channel);
362 }
363 
364 enum global_interrupt_status_register_bits {
365         Counter_0_Int_Bit = 0x100,
366         Counter_1_Int_Bit = 0x200,
367         Counter_2_Int_Bit = 0x400,
368         Counter_3_Int_Bit = 0x800,
369         Cascade_Int_Bit = 0x20000000,
370         Global_Int_Bit = 0x80000000
371 };
372 
373 enum global_interrupt_config_register_bits {
374         Cascade_Int_Enable_Bit = 0x20000000,
375         Global_Int_Polarity_Bit = 0x40000000,
376         Global_Int_Enable_Bit = 0x80000000
377 };
378 
379 /* Offset of the GPCT chips from the base-address of the card */
380 /* First chip is at base-address + 0x00, etc. */
381 static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 };
382 
383 enum ni_660x_boardid {
384         BOARD_PCI6601,
385         BOARD_PCI6602,
386         BOARD_PXI6602,
387         BOARD_PXI6608,
388         BOARD_PXI6624
389 };
390 
391 struct ni_660x_board {
392         const char *name;
393         unsigned n_chips;       /* total number of TIO chips */
394 };
395 
396 static const struct ni_660x_board ni_660x_boards[] = {
397         [BOARD_PCI6601] = {
398                 .name           = "PCI-6601",
399                 .n_chips        = 1,
400         },
401         [BOARD_PCI6602] = {
402                 .name           = "PCI-6602",
403                 .n_chips        = 2,
404         },
405         [BOARD_PXI6602] = {
406                 .name           = "PXI-6602",
407                 .n_chips        = 2,
408         },
409         [BOARD_PXI6608] = {
410                 .name           = "PXI-6608",
411                 .n_chips        = 2,
412         },
413         [BOARD_PXI6624] = {
414                 .name           = "PXI-6624",
415                 .n_chips        = 2,
416         },
417 };
418 
419 #define NI_660X_MAX_NUM_CHIPS 2
420 #define NI_660X_MAX_NUM_COUNTERS (NI_660X_MAX_NUM_CHIPS * counters_per_chip)
421 
422 struct ni_660x_private {
423         struct mite_struct *mite;
424         struct ni_gpct_device *counter_dev;
425         uint64_t pfi_direction_bits;
426         struct mite_dma_descriptor_ring
427         *mite_rings[NI_660X_MAX_NUM_CHIPS][counters_per_chip];
428         spinlock_t mite_channel_lock;
429         /* interrupt_lock prevents races between interrupt and comedi_poll */
430         spinlock_t interrupt_lock;
431         unsigned dma_configuration_soft_copies[NI_660X_MAX_NUM_CHIPS];
432         spinlock_t soft_reg_copy_lock;
433         unsigned short pfi_output_selects[NUM_PFI_CHANNELS];
434 };
435 
436 static inline unsigned ni_660x_num_counters(struct comedi_device *dev)
437 {
438         const struct ni_660x_board *board = comedi_board(dev);
439 
440         return board->n_chips * counters_per_chip;
441 }
442 
443 static enum ni_660x_register ni_gpct_to_660x_register(enum ni_gpct_register reg)
444 {
445         switch (reg) {
446         case NITIO_G0_AUTO_INC:
447                 return NI660X_G0_AUTO_INC;
448         case NITIO_G1_AUTO_INC:
449                 return NI660X_G1_AUTO_INC;
450         case NITIO_G2_AUTO_INC:
451                 return NI660X_G2_AUTO_INC;
452         case NITIO_G3_AUTO_INC:
453                 return NI660X_G3_AUTO_INC;
454         case NITIO_G0_CMD:
455                 return NI660X_G0_CMD;
456         case NITIO_G1_CMD:
457                 return NI660X_G1_CMD;
458         case NITIO_G2_CMD:
459                 return NI660X_G2_CMD;
460         case NITIO_G3_CMD:
461                 return NI660X_G3_CMD;
462         case NITIO_G0_HW_SAVE:
463                 return NI660X_G0_HW_SAVE;
464         case NITIO_G1_HW_SAVE:
465                 return NI660X_G1_HW_SAVE;
466         case NITIO_G2_HW_SAVE:
467                 return NI660X_G2_HW_SAVE;
468         case NITIO_G3_HW_SAVE:
469                 return NI660X_G3_HW_SAVE;
470         case NITIO_G0_SW_SAVE:
471                 return NI660X_G0_SW_SAVE;
472         case NITIO_G1_SW_SAVE:
473                 return NI660X_G1_SW_SAVE;
474         case NITIO_G2_SW_SAVE:
475                 return NI660X_G2_SW_SAVE;
476         case NITIO_G3_SW_SAVE:
477                 return NI660X_G3_SW_SAVE;
478         case NITIO_G0_MODE:
479                 return NI660X_G0_MODE;
480         case NITIO_G1_MODE:
481                 return NI660X_G1_MODE;
482         case NITIO_G2_MODE:
483                 return NI660X_G2_MODE;
484         case NITIO_G3_MODE:
485                 return NI660X_G3_MODE;
486         case NITIO_G0_LOADA:
487                 return NI660X_G0_LOADA;
488         case NITIO_G1_LOADA:
489                 return NI660X_G1_LOADA;
490         case NITIO_G2_LOADA:
491                 return NI660X_G2_LOADA;
492         case NITIO_G3_LOADA:
493                 return NI660X_G3_LOADA;
494         case NITIO_G0_LOADB:
495                 return NI660X_G0_LOADB;
496         case NITIO_G1_LOADB:
497                 return NI660X_G1_LOADB;
498         case NITIO_G2_LOADB:
499                 return NI660X_G2_LOADB;
500         case NITIO_G3_LOADB:
501                 return NI660X_G3_LOADB;
502         case NITIO_G0_INPUT_SEL:
503                 return NI660X_G0_INPUT_SEL;
504         case NITIO_G1_INPUT_SEL:
505                 return NI660X_G1_INPUT_SEL;
506         case NITIO_G2_INPUT_SEL:
507                 return NI660X_G2_INPUT_SEL;
508         case NITIO_G3_INPUT_SEL:
509                 return NI660X_G3_INPUT_SEL;
510         case NITIO_G01_STATUS:
511                 return NI660X_G01_STATUS;
512         case NITIO_G23_STATUS:
513                 return NI660X_G23_STATUS;
514         case NITIO_G01_RESET:
515                 return NI660X_G01_RESET;
516         case NITIO_G23_RESET:
517                 return NI660X_G23_RESET;
518         case NITIO_G01_STATUS1:
519                 return NI660X_G01_STATUS1;
520         case NITIO_G23_STATUS1:
521                 return NI660X_G23_STATUS1;
522         case NITIO_G01_STATUS2:
523                 return NI660X_G01_STATUS2;
524         case NITIO_G23_STATUS2:
525                 return NI660X_G23_STATUS2;
526         case NITIO_G0_CNT_MODE:
527                 return NI660X_G0_CNT_MODE;
528         case NITIO_G1_CNT_MODE:
529                 return NI660X_G1_CNT_MODE;
530         case NITIO_G2_CNT_MODE:
531                 return NI660X_G2_CNT_MODE;
532         case NITIO_G3_CNT_MODE:
533                 return NI660X_G3_CNT_MODE;
534         case NITIO_G0_GATE2:
535                 return NI660X_G0_GATE2;
536         case NITIO_G1_GATE2:
537                 return NI660X_G1_GATE2;
538         case NITIO_G2_GATE2:
539                 return NI660X_G2_GATE2;
540         case NITIO_G3_GATE2:
541                 return NI660X_G3_GATE2;
542         case NITIO_G0_DMA_CFG:
543                 return NI660X_G0_DMA_CFG;
544         case NITIO_G0_DMA_STATUS:
545                 return NI660X_G0_DMA_STATUS;
546         case NITIO_G1_DMA_CFG:
547                 return NI660X_G1_DMA_CFG;
548         case NITIO_G1_DMA_STATUS:
549                 return NI660X_G1_DMA_STATUS;
550         case NITIO_G2_DMA_CFG:
551                 return NI660X_G2_DMA_CFG;
552         case NITIO_G2_DMA_STATUS:
553                 return NI660X_G2_DMA_STATUS;
554         case NITIO_G3_DMA_CFG:
555                 return NI660X_G3_DMA_CFG;
556         case NITIO_G3_DMA_STATUS:
557                 return NI660X_G3_DMA_STATUS;
558         case NITIO_G0_INT_ACK:
559                 return NI660X_G0_INT_ACK;
560         case NITIO_G1_INT_ACK:
561                 return NI660X_G1_INT_ACK;
562         case NITIO_G2_INT_ACK:
563                 return NI660X_G2_INT_ACK;
564         case NITIO_G3_INT_ACK:
565                 return NI660X_G3_INT_ACK;
566         case NITIO_G0_STATUS:
567                 return NI660X_G0_STATUS;
568         case NITIO_G1_STATUS:
569                 return NI660X_G1_STATUS;
570         case NITIO_G2_STATUS:
571                 return NI660X_G2_STATUS;
572         case NITIO_G3_STATUS:
573                 return NI660X_G3_STATUS;
574         case NITIO_G0_INT_ENA:
575                 return NI660X_G0_INT_ENA;
576         case NITIO_G1_INT_ENA:
577                 return NI660X_G1_INT_ENA;
578         case NITIO_G2_INT_ENA:
579                 return NI660X_G2_INT_ENA;
580         case NITIO_G3_INT_ENA:
581                 return NI660X_G3_INT_ENA;
582         default:
583                 BUG();
584                 return 0;
585         }
586 }
587 
588 static inline void ni_660x_write_register(struct comedi_device *dev,
589                                           unsigned chip, unsigned bits,
590                                           enum ni_660x_register reg)
591 {
592         struct ni_660x_private *devpriv = dev->private;
593         void __iomem *write_address =
594             devpriv->mite->daq_io_addr + GPCT_OFFSET[chip] +
595             registerData[reg].offset;
596 
597         switch (registerData[reg].size) {
598         case DATA_2B:
599                 writew(bits, write_address);
600                 break;
601         case DATA_4B:
602                 writel(bits, write_address);
603                 break;
604         default:
605                 BUG();
606                 break;
607         }
608 }
609 
610 static inline unsigned ni_660x_read_register(struct comedi_device *dev,
611                                              unsigned chip,
612                                              enum ni_660x_register reg)
613 {
614         struct ni_660x_private *devpriv = dev->private;
615         void __iomem *read_address =
616             devpriv->mite->daq_io_addr + GPCT_OFFSET[chip] +
617             registerData[reg].offset;
618 
619         switch (registerData[reg].size) {
620         case DATA_2B:
621                 return readw(read_address);
622                 break;
623         case DATA_4B:
624                 return readl(read_address);
625                 break;
626         default:
627                 BUG();
628                 break;
629         }
630         return 0;
631 }
632 
633 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
634                                    enum ni_gpct_register reg)
635 {
636         struct comedi_device *dev = counter->counter_dev->dev;
637         enum ni_660x_register ni_660x_register = ni_gpct_to_660x_register(reg);
638         unsigned chip = counter->chip_index;
639 
640         ni_660x_write_register(dev, chip, bits, ni_660x_register);
641 }
642 
643 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
644                                       enum ni_gpct_register reg)
645 {
646         struct comedi_device *dev = counter->counter_dev->dev;
647         enum ni_660x_register ni_660x_register = ni_gpct_to_660x_register(reg);
648         unsigned chip = counter->chip_index;
649 
650         return ni_660x_read_register(dev, chip, ni_660x_register);
651 }
652 
653 static inline struct mite_dma_descriptor_ring *mite_ring(struct ni_660x_private
654                                                          *priv,
655                                                          struct ni_gpct
656                                                          *counter)
657 {
658         unsigned chip = counter->chip_index;
659 
660         return priv->mite_rings[chip][counter->counter_index];
661 }
662 
663 static inline void ni_660x_set_dma_channel(struct comedi_device *dev,
664                                            unsigned mite_channel,
665                                            struct ni_gpct *counter)
666 {
667         struct ni_660x_private *devpriv = dev->private;
668         unsigned chip = counter->chip_index;
669         unsigned long flags;
670 
671         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
672         devpriv->dma_configuration_soft_copies[chip] &=
673                 ~dma_select_mask(mite_channel);
674         devpriv->dma_configuration_soft_copies[chip] |=
675                 dma_select_bits(mite_channel, counter->counter_index);
676         ni_660x_write_register(dev, chip,
677                                devpriv->dma_configuration_soft_copies[chip] |
678                                dma_reset_bit(mite_channel), NI660X_DMA_CFG);
679         mmiowb();
680         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
681 }
682 
683 static inline void ni_660x_unset_dma_channel(struct comedi_device *dev,
684                                              unsigned mite_channel,
685                                              struct ni_gpct *counter)
686 {
687         struct ni_660x_private *devpriv = dev->private;
688         unsigned chip = counter->chip_index;
689         unsigned long flags;
690 
691         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
692         devpriv->dma_configuration_soft_copies[chip] &=
693             ~dma_select_mask(mite_channel);
694         devpriv->dma_configuration_soft_copies[chip] |=
695             dma_select_bits(mite_channel, dma_selection_none);
696         ni_660x_write_register(dev, chip,
697                                devpriv->dma_configuration_soft_copies[chip],
698                                NI660X_DMA_CFG);
699         mmiowb();
700         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
701 }
702 
703 static int ni_660x_request_mite_channel(struct comedi_device *dev,
704                                         struct ni_gpct *counter,
705                                         enum comedi_io_direction direction)
706 {
707         struct ni_660x_private *devpriv = dev->private;
708         unsigned long flags;
709         struct mite_channel *mite_chan;
710 
711         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
712         BUG_ON(counter->mite_chan);
713         mite_chan = mite_request_channel(devpriv->mite,
714                                          mite_ring(devpriv, counter));
715         if (mite_chan == NULL) {
716                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
717                 comedi_error(dev,
718                              "failed to reserve mite dma channel for counter.");
719                 return -EBUSY;
720         }
721         mite_chan->dir = direction;
722         ni_tio_set_mite_channel(counter, mite_chan);
723         ni_660x_set_dma_channel(dev, mite_chan->channel, counter);
724         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
725         return 0;
726 }
727 
728 static void ni_660x_release_mite_channel(struct comedi_device *dev,
729                                          struct ni_gpct *counter)
730 {
731         struct ni_660x_private *devpriv = dev->private;
732         unsigned long flags;
733 
734         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
735         if (counter->mite_chan) {
736                 struct mite_channel *mite_chan = counter->mite_chan;
737 
738                 ni_660x_unset_dma_channel(dev, mite_chan->channel, counter);
739                 ni_tio_set_mite_channel(counter, NULL);
740                 mite_release_channel(mite_chan);
741         }
742         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
743 }
744 
745 static int ni_660x_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
746 {
747         struct ni_gpct *counter = s->private;
748         int retval;
749 
750         retval = ni_660x_request_mite_channel(dev, counter, COMEDI_INPUT);
751         if (retval) {
752                 comedi_error(dev,
753                              "no dma channel available for use by counter");
754                 return retval;
755         }
756         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
757 
758         return ni_tio_cmd(dev, s);
759 }
760 
761 static int ni_660x_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
762 {
763         struct ni_gpct *counter = s->private;
764         int retval;
765 
766         retval = ni_tio_cancel(counter);
767         ni_660x_release_mite_channel(dev, counter);
768         return retval;
769 }
770 
771 static void set_tio_counterswap(struct comedi_device *dev, int chip)
772 {
773         unsigned bits = 0;
774 
775         /*
776          * See P. 3.5 of the Register-Level Programming manual.
777          * The CounterSwap bit has to be set on the second chip,
778          * otherwise it will try to use the same pins as the
779          * first chip.
780          */
781         if (chip)
782                 bits = CounterSwap;
783 
784         ni_660x_write_register(dev, chip, bits, NI660X_CLK_CFG);
785 }
786 
787 static void ni_660x_handle_gpct_interrupt(struct comedi_device *dev,
788                                           struct comedi_subdevice *s)
789 {
790         struct ni_gpct *counter = s->private;
791 
792         ni_tio_handle_interrupt(counter, s);
793         cfc_handle_events(dev, s);
794 }
795 
796 static irqreturn_t ni_660x_interrupt(int irq, void *d)
797 {
798         struct comedi_device *dev = d;
799         struct ni_660x_private *devpriv = dev->private;
800         struct comedi_subdevice *s;
801         unsigned i;
802         unsigned long flags;
803 
804         if (!dev->attached)
805                 return IRQ_NONE;
806         /* lock to avoid race with comedi_poll */
807         spin_lock_irqsave(&devpriv->interrupt_lock, flags);
808         smp_mb();
809         for (i = 0; i < ni_660x_num_counters(dev); ++i) {
810                 s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)];
811                 ni_660x_handle_gpct_interrupt(dev, s);
812         }
813         spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
814         return IRQ_HANDLED;
815 }
816 
817 static int ni_660x_input_poll(struct comedi_device *dev,
818                               struct comedi_subdevice *s)
819 {
820         struct ni_660x_private *devpriv = dev->private;
821         struct ni_gpct *counter = s->private;
822         unsigned long flags;
823 
824         /* lock to avoid race with comedi_poll */
825         spin_lock_irqsave(&devpriv->interrupt_lock, flags);
826         mite_sync_input_dma(counter->mite_chan, s);
827         spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
828         return comedi_buf_read_n_available(s);
829 }
830 
831 static int ni_660x_buf_change(struct comedi_device *dev,
832                               struct comedi_subdevice *s,
833                               unsigned long new_size)
834 {
835         struct ni_660x_private *devpriv = dev->private;
836         struct ni_gpct *counter = s->private;
837         int ret;
838 
839         ret = mite_buf_change(mite_ring(devpriv, counter), s);
840         if (ret < 0)
841                 return ret;
842 
843         return 0;
844 }
845 
846 static int ni_660x_allocate_private(struct comedi_device *dev)
847 {
848         struct ni_660x_private *devpriv;
849         unsigned i;
850 
851         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
852         if (!devpriv)
853                 return -ENOMEM;
854 
855         spin_lock_init(&devpriv->mite_channel_lock);
856         spin_lock_init(&devpriv->interrupt_lock);
857         spin_lock_init(&devpriv->soft_reg_copy_lock);
858         for (i = 0; i < NUM_PFI_CHANNELS; ++i)
859                 devpriv->pfi_output_selects[i] = pfi_output_select_counter;
860 
861         return 0;
862 }
863 
864 static int ni_660x_alloc_mite_rings(struct comedi_device *dev)
865 {
866         const struct ni_660x_board *board = comedi_board(dev);
867         struct ni_660x_private *devpriv = dev->private;
868         unsigned i;
869         unsigned j;
870 
871         for (i = 0; i < board->n_chips; ++i) {
872                 for (j = 0; j < counters_per_chip; ++j) {
873                         devpriv->mite_rings[i][j] =
874                             mite_alloc_ring(devpriv->mite);
875                         if (devpriv->mite_rings[i][j] == NULL)
876                                 return -ENOMEM;
877                 }
878         }
879         return 0;
880 }
881 
882 static void ni_660x_free_mite_rings(struct comedi_device *dev)
883 {
884         const struct ni_660x_board *board = comedi_board(dev);
885         struct ni_660x_private *devpriv = dev->private;
886         unsigned i;
887         unsigned j;
888 
889         for (i = 0; i < board->n_chips; ++i) {
890                 for (j = 0; j < counters_per_chip; ++j)
891                         mite_free_ring(devpriv->mite_rings[i][j]);
892         }
893 }
894 
895 static void init_tio_chip(struct comedi_device *dev, int chipset)
896 {
897         struct ni_660x_private *devpriv = dev->private;
898         unsigned i;
899 
900         /*  init dma configuration register */
901         devpriv->dma_configuration_soft_copies[chipset] = 0;
902         for (i = 0; i < MAX_DMA_CHANNEL; ++i) {
903                 devpriv->dma_configuration_soft_copies[chipset] |=
904                     dma_select_bits(i, dma_selection_none) & dma_select_mask(i);
905         }
906         ni_660x_write_register(dev, chipset,
907                                devpriv->dma_configuration_soft_copies[chipset],
908                                NI660X_DMA_CFG);
909         for (i = 0; i < NUM_PFI_CHANNELS; ++i)
910                 ni_660x_write_register(dev, chipset, 0, IOConfigReg(i));
911 }
912 
913 static int ni_660x_dio_insn_bits(struct comedi_device *dev,
914                                  struct comedi_subdevice *s,
915                                  struct comedi_insn *insn, unsigned int *data)
916 {
917         unsigned base_bitfield_channel = CR_CHAN(insn->chanspec);
918 
919         /*  Check if we have to write some bits */
920         if (data[0]) {
921                 s->state &= ~(data[0] << base_bitfield_channel);
922                 s->state |= (data[0] & data[1]) << base_bitfield_channel;
923                 /* Write out the new digital output lines */
924                 ni_660x_write_register(dev, 0, s->state, NI660X_DIO32_OUTPUT);
925         }
926         /* on return, data[1] contains the value of the digital
927          * input and output lines. */
928         data[1] = (ni_660x_read_register(dev, 0, NI660X_DIO32_INPUT) >>
929                         base_bitfield_channel);
930 
931         return insn->n;
932 }
933 
934 static void ni_660x_select_pfi_output(struct comedi_device *dev,
935                                       unsigned pfi_channel,
936                                       unsigned output_select)
937 {
938         const struct ni_660x_board *board = comedi_board(dev);
939         static const unsigned counter_4_7_first_pfi = 8;
940         static const unsigned counter_4_7_last_pfi = 23;
941         unsigned active_chipset = 0;
942         unsigned idle_chipset = 0;
943         unsigned active_bits;
944         unsigned idle_bits;
945 
946         if (board->n_chips > 1) {
947                 if (output_select == pfi_output_select_counter &&
948                     pfi_channel >= counter_4_7_first_pfi &&
949                     pfi_channel <= counter_4_7_last_pfi) {
950                         active_chipset = 1;
951                         idle_chipset = 0;
952                 } else {
953                         active_chipset = 0;
954                         idle_chipset = 1;
955                 }
956         }
957 
958         if (idle_chipset != active_chipset) {
959                 idle_bits =
960                     ni_660x_read_register(dev, idle_chipset,
961                                           IOConfigReg(pfi_channel));
962                 idle_bits &= ~pfi_output_select_mask(pfi_channel);
963                 idle_bits |=
964                     pfi_output_select_bits(pfi_channel,
965                                            pfi_output_select_high_Z);
966                 ni_660x_write_register(dev, idle_chipset, idle_bits,
967                                        IOConfigReg(pfi_channel));
968         }
969 
970         active_bits =
971             ni_660x_read_register(dev, active_chipset,
972                                   IOConfigReg(pfi_channel));
973         active_bits &= ~pfi_output_select_mask(pfi_channel);
974         active_bits |= pfi_output_select_bits(pfi_channel, output_select);
975         ni_660x_write_register(dev, active_chipset, active_bits,
976                                IOConfigReg(pfi_channel));
977 }
978 
979 static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan,
980                                    unsigned source)
981 {
982         struct ni_660x_private *devpriv = dev->private;
983 
984         if (source > num_pfi_output_selects)
985                 return -EINVAL;
986         if (source == pfi_output_select_high_Z)
987                 return -EINVAL;
988         if (chan < min_counter_pfi_chan) {
989                 if (source == pfi_output_select_counter)
990                         return -EINVAL;
991         } else if (chan > max_dio_pfi_chan) {
992                 if (source == pfi_output_select_do)
993                         return -EINVAL;
994         }
995 
996         devpriv->pfi_output_selects[chan] = source;
997         if (devpriv->pfi_direction_bits & (((uint64_t) 1) << chan))
998                 ni_660x_select_pfi_output(dev, chan,
999                                           devpriv->pfi_output_selects[chan]);
1000         return 0;
1001 }
1002 
1003 static int ni_660x_dio_insn_config(struct comedi_device *dev,
1004                                    struct comedi_subdevice *s,
1005                                    struct comedi_insn *insn,
1006                                    unsigned int *data)
1007 {
1008         struct ni_660x_private *devpriv = dev->private;
1009         unsigned int chan = CR_CHAN(insn->chanspec);
1010         uint64_t bit = 1ULL << chan;
1011         unsigned int val;
1012         int ret;
1013 
1014         switch (data[0]) {
1015         case INSN_CONFIG_DIO_OUTPUT:
1016                 devpriv->pfi_direction_bits |= bit;
1017                 ni_660x_select_pfi_output(dev, chan,
1018                                           devpriv->pfi_output_selects[chan]);
1019                 break;
1020 
1021         case INSN_CONFIG_DIO_INPUT:
1022                 devpriv->pfi_direction_bits &= ~bit;
1023                 ni_660x_select_pfi_output(dev, chan, pfi_output_select_high_Z);
1024                 break;
1025 
1026         case INSN_CONFIG_DIO_QUERY:
1027                 data[1] = (devpriv->pfi_direction_bits & bit) ? COMEDI_OUTPUT
1028                                                               : COMEDI_INPUT;
1029                 break;
1030 
1031         case INSN_CONFIG_SET_ROUTING:
1032                 ret = ni_660x_set_pfi_routing(dev, chan, data[1]);
1033                 if (ret)
1034                         return ret;
1035                 break;
1036 
1037         case INSN_CONFIG_GET_ROUTING:
1038                 data[1] = devpriv->pfi_output_selects[chan];
1039                 break;
1040 
1041         case INSN_CONFIG_FILTER:
1042                 val = ni_660x_read_register(dev, 0, IOConfigReg(chan));
1043                 val &= ~pfi_input_select_mask(chan);
1044                 val |= pfi_input_select_bits(chan, data[1]);
1045                 ni_660x_write_register(dev, 0, val, IOConfigReg(chan));
1046                 break;
1047 
1048         default:
1049                 return -EINVAL;
1050         }
1051 
1052         return insn->n;
1053 }
1054 
1055 static int ni_660x_auto_attach(struct comedi_device *dev,
1056                                unsigned long context)
1057 {
1058         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1059         const struct ni_660x_board *board = NULL;
1060         struct ni_660x_private *devpriv;
1061         struct comedi_subdevice *s;
1062         int ret;
1063         unsigned i;
1064         unsigned global_interrupt_config_bits;
1065 
1066         if (context < ARRAY_SIZE(ni_660x_boards))
1067                 board = &ni_660x_boards[context];
1068         if (!board)
1069                 return -ENODEV;
1070         dev->board_ptr = board;
1071         dev->board_name = board->name;
1072 
1073         ret = comedi_pci_enable(dev);
1074         if (ret)
1075                 return ret;
1076 
1077         ret = ni_660x_allocate_private(dev);
1078         if (ret < 0)
1079                 return ret;
1080         devpriv = dev->private;
1081 
1082         devpriv->mite = mite_alloc(pcidev);
1083         if (!devpriv->mite)
1084                 return -ENOMEM;
1085 
1086         ret = mite_setup2(devpriv->mite, 1);
1087         if (ret < 0) {
1088                 dev_warn(dev->class_dev, "error setting up mite\n");
1089                 return ret;
1090         }
1091 
1092         ret = ni_660x_alloc_mite_rings(dev);
1093         if (ret < 0)
1094                 return ret;
1095 
1096         ret = comedi_alloc_subdevices(dev, 2 + NI_660X_MAX_NUM_COUNTERS);
1097         if (ret)
1098                 return ret;
1099 
1100         s = &dev->subdevices[0];
1101         /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */
1102         s->type = COMEDI_SUBD_UNUSED;
1103 
1104         s = &dev->subdevices[NI_660X_DIO_SUBDEV];
1105         /* DIGITAL I/O SUBDEVICE */
1106         s->type = COMEDI_SUBD_DIO;
1107         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1108         s->n_chan = NUM_PFI_CHANNELS;
1109         s->maxdata = 1;
1110         s->range_table = &range_digital;
1111         s->insn_bits = ni_660x_dio_insn_bits;
1112         s->insn_config = ni_660x_dio_insn_config;
1113         /*  we use the ioconfig registers to control dio direction, so zero
1114         output enables in stc dio control reg */
1115         ni_660x_write_register(dev, 0, 0, NI660X_STC_DIO_CONTROL);
1116 
1117         devpriv->counter_dev = ni_gpct_device_construct(dev,
1118                                                      &ni_gpct_write_register,
1119                                                      &ni_gpct_read_register,
1120                                                      ni_gpct_variant_660x,
1121                                                      ni_660x_num_counters
1122                                                      (dev));
1123         if (devpriv->counter_dev == NULL)
1124                 return -ENOMEM;
1125         for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) {
1126                 s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)];
1127                 if (i < ni_660x_num_counters(dev)) {
1128                         s->type = COMEDI_SUBD_COUNTER;
1129                         s->subdev_flags =
1130                             SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL |
1131                             SDF_CMD_READ /* | SDF_CMD_WRITE */ ;
1132                         s->n_chan = 3;
1133                         s->maxdata = 0xffffffff;
1134                         s->insn_read = ni_tio_insn_read;
1135                         s->insn_write = ni_tio_insn_write;
1136                         s->insn_config = ni_tio_insn_config;
1137                         s->do_cmd = &ni_660x_cmd;
1138                         s->len_chanlist = 1;
1139                         s->do_cmdtest = ni_tio_cmdtest;
1140                         s->cancel = &ni_660x_cancel;
1141                         s->poll = &ni_660x_input_poll;
1142                         s->async_dma_dir = DMA_BIDIRECTIONAL;
1143                         s->buf_change = &ni_660x_buf_change;
1144                         s->private = &devpriv->counter_dev->counters[i];
1145 
1146                         devpriv->counter_dev->counters[i].chip_index =
1147                             i / counters_per_chip;
1148                         devpriv->counter_dev->counters[i].counter_index =
1149                             i % counters_per_chip;
1150                 } else {
1151                         s->type = COMEDI_SUBD_UNUSED;
1152                 }
1153         }
1154         for (i = 0; i < board->n_chips; ++i)
1155                 init_tio_chip(dev, i);
1156 
1157         for (i = 0; i < ni_660x_num_counters(dev); ++i)
1158                 ni_tio_init_counter(&devpriv->counter_dev->counters[i]);
1159 
1160         for (i = 0; i < NUM_PFI_CHANNELS; ++i) {
1161                 if (i < min_counter_pfi_chan)
1162                         ni_660x_set_pfi_routing(dev, i, pfi_output_select_do);
1163                 else
1164                         ni_660x_set_pfi_routing(dev, i,
1165                                                 pfi_output_select_counter);
1166                 ni_660x_select_pfi_output(dev, i, pfi_output_select_high_Z);
1167         }
1168         /* to be safe, set counterswap bits on tio chips after all the counter
1169            outputs have been set to high impedance mode */
1170         for (i = 0; i < board->n_chips; ++i)
1171                 set_tio_counterswap(dev, i);
1172 
1173         ret = request_irq(mite_irq(devpriv->mite), ni_660x_interrupt,
1174                           IRQF_SHARED, "ni_660x", dev);
1175         if (ret < 0) {
1176                 dev_warn(dev->class_dev, " irq not available\n");
1177                 return ret;
1178         }
1179         dev->irq = mite_irq(devpriv->mite);
1180         global_interrupt_config_bits = Global_Int_Enable_Bit;
1181         if (board->n_chips > 1)
1182                 global_interrupt_config_bits |= Cascade_Int_Enable_Bit;
1183         ni_660x_write_register(dev, 0, global_interrupt_config_bits,
1184                                NI660X_GLOBAL_INT_CFG);
1185 
1186         return 0;
1187 }
1188 
1189 static void ni_660x_detach(struct comedi_device *dev)
1190 {
1191         struct ni_660x_private *devpriv = dev->private;
1192 
1193         if (dev->irq)
1194                 free_irq(dev->irq, dev);
1195         if (devpriv) {
1196                 if (devpriv->counter_dev)
1197                         ni_gpct_device_destroy(devpriv->counter_dev);
1198                 if (devpriv->mite) {
1199                         ni_660x_free_mite_rings(dev);
1200                         mite_unsetup(devpriv->mite);
1201                         mite_free(devpriv->mite);
1202                 }
1203         }
1204         comedi_pci_disable(dev);
1205 }
1206 
1207 static struct comedi_driver ni_660x_driver = {
1208         .driver_name    = "ni_660x",
1209         .module         = THIS_MODULE,
1210         .auto_attach    = ni_660x_auto_attach,
1211         .detach         = ni_660x_detach,
1212 };
1213 
1214 static int ni_660x_pci_probe(struct pci_dev *dev,
1215                              const struct pci_device_id *id)
1216 {
1217         return comedi_pci_auto_config(dev, &ni_660x_driver, id->driver_data);
1218 }
1219 
1220 static const struct pci_device_id ni_660x_pci_table[] = {
1221         { PCI_VDEVICE(NI, 0x1310), BOARD_PCI6602 },
1222         { PCI_VDEVICE(NI, 0x1360), BOARD_PXI6602 },
1223         { PCI_VDEVICE(NI, 0x2c60), BOARD_PCI6601 },
1224         { PCI_VDEVICE(NI, 0x2cc0), BOARD_PXI6608 },
1225         { PCI_VDEVICE(NI, 0x1e40), BOARD_PXI6624 },
1226         { 0 }
1227 };
1228 MODULE_DEVICE_TABLE(pci, ni_660x_pci_table);
1229 
1230 static struct pci_driver ni_660x_pci_driver = {
1231         .name           = "ni_660x",
1232         .id_table       = ni_660x_pci_table,
1233         .probe          = ni_660x_pci_probe,
1234         .remove         = comedi_pci_auto_unconfig,
1235 };
1236 module_comedi_pci_driver(ni_660x_driver, ni_660x_pci_driver);
1237 
1238 MODULE_AUTHOR("Comedi http://www.comedi.org");
1239 MODULE_DESCRIPTION("Comedi low-level driver");
1240 MODULE_LICENSE("GPL");
1241 

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