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Linux/drivers/staging/comedi/drivers/ni_65xx.c

  1 /*
  2     comedi/drivers/ni_6514.c
  3     driver for National Instruments PCI-6514
  4 
  5     Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
  6     Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
  7 
  8     COMEDI - Linux Control and Measurement Device Interface
  9     Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
 10 
 11     This program is free software; you can redistribute it and/or modify
 12     it under the terms of the GNU General Public License as published by
 13     the Free Software Foundation; either version 2 of the License, or
 14     (at your option) any later version.
 15 
 16     This program is distributed in the hope that it will be useful,
 17     but WITHOUT ANY WARRANTY; without even the implied warranty of
 18     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19     GNU General Public License for more details.
 20 */
 21 /*
 22 Driver: ni_65xx
 23 Description: National Instruments 65xx static dio boards
 24 Author: Jon Grierson <jd@renko.co.uk>,
 25         Frank Mori Hess <fmhess@users.sourceforge.net>
 26 Status: testing
 27 Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510,
 28   PCI-6511, PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514,
 29   PXI-6514, PCI-6515, PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519,
 30   PCI-6520, PCI-6521, PXI-6521, PCI-6528, PXI-6528
 31 Updated: Wed Oct 18 08:59:11 EDT 2006
 32 
 33 Based on the PCI-6527 driver by ds.
 34 The interrupt subdevice (subdevice 3) is probably broken for all boards
 35 except maybe the 6514.
 36 
 37 */
 38 
 39 /*
 40    Manuals (available from ftp://ftp.natinst.com/support/manuals)
 41 
 42         370106b.pdf     6514 Register Level Programmer Manual
 43 
 44  */
 45 
 46 #include <linux/module.h>
 47 #include <linux/pci.h>
 48 #include <linux/interrupt.h>
 49 
 50 #include "../comedidev.h"
 51 
 52 #include "comedi_fc.h"
 53 #include "mite.h"
 54 
 55 #define NI6514_DIO_SIZE 4096
 56 #define NI6514_MITE_SIZE 4096
 57 
 58 #define NI_65XX_MAX_NUM_PORTS 12
 59 static const unsigned ni_65xx_channels_per_port = 8;
 60 static const unsigned ni_65xx_port_offset = 0x10;
 61 
 62 static inline unsigned Port_Data(unsigned port)
 63 {
 64         return 0x40 + port * ni_65xx_port_offset;
 65 }
 66 
 67 static inline unsigned Port_Select(unsigned port)
 68 {
 69         return 0x41 + port * ni_65xx_port_offset;
 70 }
 71 
 72 static inline unsigned Rising_Edge_Detection_Enable(unsigned port)
 73 {
 74         return 0x42 + port * ni_65xx_port_offset;
 75 }
 76 
 77 static inline unsigned Falling_Edge_Detection_Enable(unsigned port)
 78 {
 79         return 0x43 + port * ni_65xx_port_offset;
 80 }
 81 
 82 static inline unsigned Filter_Enable(unsigned port)
 83 {
 84         return 0x44 + port * ni_65xx_port_offset;
 85 }
 86 
 87 #define ID_Register                             0x00
 88 
 89 #define Clear_Register                          0x01
 90 #define ClrEdge                         0x08
 91 #define ClrOverflow                     0x04
 92 
 93 #define Filter_Interval                 0x08
 94 
 95 #define Change_Status                           0x02
 96 #define MasterInterruptStatus           0x04
 97 #define Overflow                        0x02
 98 #define EdgeStatus                      0x01
 99 
100 #define Master_Interrupt_Control                0x03
101 #define FallingEdgeIntEnable            0x10
102 #define RisingEdgeIntEnable             0x08
103 #define MasterInterruptEnable           0x04
104 #define OverflowIntEnable               0x02
105 #define EdgeIntEnable                   0x01
106 
107 enum ni_65xx_boardid {
108         BOARD_PCI6509,
109         BOARD_PXI6509,
110         BOARD_PCI6510,
111         BOARD_PCI6511,
112         BOARD_PXI6511,
113         BOARD_PCI6512,
114         BOARD_PXI6512,
115         BOARD_PCI6513,
116         BOARD_PXI6513,
117         BOARD_PCI6514,
118         BOARD_PXI6514,
119         BOARD_PCI6515,
120         BOARD_PXI6515,
121         BOARD_PCI6516,
122         BOARD_PCI6517,
123         BOARD_PCI6518,
124         BOARD_PCI6519,
125         BOARD_PCI6520,
126         BOARD_PCI6521,
127         BOARD_PXI6521,
128         BOARD_PCI6528,
129         BOARD_PXI6528,
130 };
131 
132 struct ni_65xx_board {
133         const char *name;
134         unsigned num_dio_ports;
135         unsigned num_di_ports;
136         unsigned num_do_ports;
137         unsigned invert_outputs:1;
138 };
139 
140 static const struct ni_65xx_board ni_65xx_boards[] = {
141         [BOARD_PCI6509] = {
142                 .name           = "pci-6509",
143                 .num_dio_ports  = 12,
144         },
145         [BOARD_PXI6509] = {
146                 .name           = "pxi-6509",
147                 .num_dio_ports  = 12,
148         },
149         [BOARD_PCI6510] = {
150                 .name           = "pci-6510",
151                 .num_di_ports   = 4,
152         },
153         [BOARD_PCI6511] = {
154                 .name           = "pci-6511",
155                 .num_di_ports   = 8,
156         },
157         [BOARD_PXI6511] = {
158                 .name           = "pxi-6511",
159                 .num_di_ports   = 8,
160         },
161         [BOARD_PCI6512] = {
162                 .name           = "pci-6512",
163                 .num_do_ports   = 8,
164         },
165         [BOARD_PXI6512] = {
166                 .name           = "pxi-6512",
167                 .num_do_ports   = 8,
168         },
169         [BOARD_PCI6513] = {
170                 .name           = "pci-6513",
171                 .num_do_ports   = 8,
172                 .invert_outputs = 1,
173         },
174         [BOARD_PXI6513] = {
175                 .name           = "pxi-6513",
176                 .num_do_ports   = 8,
177                 .invert_outputs = 1,
178         },
179         [BOARD_PCI6514] = {
180                 .name           = "pci-6514",
181                 .num_di_ports   = 4,
182                 .num_do_ports   = 4,
183                 .invert_outputs = 1,
184         },
185         [BOARD_PXI6514] = {
186                 .name           = "pxi-6514",
187                 .num_di_ports   = 4,
188                 .num_do_ports   = 4,
189                 .invert_outputs = 1,
190         },
191         [BOARD_PCI6515] = {
192                 .name           = "pci-6515",
193                 .num_di_ports   = 4,
194                 .num_do_ports   = 4,
195                 .invert_outputs = 1,
196         },
197         [BOARD_PXI6515] = {
198                 .name           = "pxi-6515",
199                 .num_di_ports   = 4,
200                 .num_do_ports   = 4,
201                 .invert_outputs = 1,
202         },
203         [BOARD_PCI6516] = {
204                 .name           = "pci-6516",
205                 .num_do_ports   = 4,
206                 .invert_outputs = 1,
207         },
208         [BOARD_PCI6517] = {
209                 .name           = "pci-6517",
210                 .num_do_ports   = 4,
211                 .invert_outputs = 1,
212         },
213         [BOARD_PCI6518] = {
214                 .name           = "pci-6518",
215                 .num_di_ports   = 2,
216                 .num_do_ports   = 2,
217                 .invert_outputs = 1,
218         },
219         [BOARD_PCI6519] = {
220                 .name           = "pci-6519",
221                 .num_di_ports   = 2,
222                 .num_do_ports   = 2,
223                 .invert_outputs = 1,
224         },
225         [BOARD_PCI6520] = {
226                 .name           = "pci-6520",
227                 .num_di_ports   = 1,
228                 .num_do_ports   = 1,
229         },
230         [BOARD_PCI6521] = {
231                 .name           = "pci-6521",
232                 .num_di_ports   = 1,
233                 .num_do_ports   = 1,
234         },
235         [BOARD_PXI6521] = {
236                 .name           = "pxi-6521",
237                 .num_di_ports   = 1,
238                 .num_do_ports   = 1,
239         },
240         [BOARD_PCI6528] = {
241                 .name           = "pci-6528",
242                 .num_di_ports   = 3,
243                 .num_do_ports   = 3,
244         },
245         [BOARD_PXI6528] = {
246                 .name           = "pxi-6528",
247                 .num_di_ports   = 3,
248                 .num_do_ports   = 3,
249         },
250 };
251 
252 static inline unsigned ni_65xx_port_by_channel(unsigned channel)
253 {
254         return channel / ni_65xx_channels_per_port;
255 }
256 
257 static inline unsigned ni_65xx_total_num_ports(const struct ni_65xx_board
258                                                *board)
259 {
260         return board->num_dio_ports + board->num_di_ports + board->num_do_ports;
261 }
262 
263 struct ni_65xx_private {
264         struct mite_struct *mite;
265         unsigned int filter_interval;
266         unsigned short filter_enable[NI_65XX_MAX_NUM_PORTS];
267         unsigned short output_bits[NI_65XX_MAX_NUM_PORTS];
268         unsigned short dio_direction[NI_65XX_MAX_NUM_PORTS];
269 };
270 
271 struct ni_65xx_subdevice_private {
272         unsigned base_port;
273 };
274 
275 static inline struct ni_65xx_subdevice_private *sprivate(struct comedi_subdevice
276                                                          *subdev)
277 {
278         return subdev->private;
279 }
280 
281 static int ni_65xx_config_filter(struct comedi_device *dev,
282                                  struct comedi_subdevice *s,
283                                  struct comedi_insn *insn, unsigned int *data)
284 {
285         struct ni_65xx_private *devpriv = dev->private;
286         const unsigned chan = CR_CHAN(insn->chanspec);
287         const unsigned port =
288             sprivate(s)->base_port + ni_65xx_port_by_channel(chan);
289 
290         if (data[0] != INSN_CONFIG_FILTER)
291                 return -EINVAL;
292         if (data[1]) {
293                 static const unsigned filter_resolution_ns = 200;
294                 static const unsigned max_filter_interval = 0xfffff;
295                 unsigned interval =
296                     (data[1] +
297                      (filter_resolution_ns / 2)) / filter_resolution_ns;
298                 if (interval > max_filter_interval)
299                         interval = max_filter_interval;
300                 data[1] = interval * filter_resolution_ns;
301 
302                 if (interval != devpriv->filter_interval) {
303                         writeb(interval,
304                                devpriv->mite->daq_io_addr +
305                                Filter_Interval);
306                         devpriv->filter_interval = interval;
307                 }
308 
309                 devpriv->filter_enable[port] |=
310                     1 << (chan % ni_65xx_channels_per_port);
311         } else {
312                 devpriv->filter_enable[port] &=
313                     ~(1 << (chan % ni_65xx_channels_per_port));
314         }
315 
316         writeb(devpriv->filter_enable[port],
317                devpriv->mite->daq_io_addr + Filter_Enable(port));
318 
319         return 2;
320 }
321 
322 static int ni_65xx_dio_insn_config(struct comedi_device *dev,
323                                    struct comedi_subdevice *s,
324                                    struct comedi_insn *insn, unsigned int *data)
325 {
326         struct ni_65xx_private *devpriv = dev->private;
327         unsigned port;
328 
329         if (insn->n < 1)
330                 return -EINVAL;
331         port = sprivate(s)->base_port +
332             ni_65xx_port_by_channel(CR_CHAN(insn->chanspec));
333         switch (data[0]) {
334         case INSN_CONFIG_FILTER:
335                 return ni_65xx_config_filter(dev, s, insn, data);
336                 break;
337         case INSN_CONFIG_DIO_OUTPUT:
338                 if (s->type != COMEDI_SUBD_DIO)
339                         return -EINVAL;
340                 devpriv->dio_direction[port] = COMEDI_OUTPUT;
341                 writeb(0, devpriv->mite->daq_io_addr + Port_Select(port));
342                 return 1;
343                 break;
344         case INSN_CONFIG_DIO_INPUT:
345                 if (s->type != COMEDI_SUBD_DIO)
346                         return -EINVAL;
347                 devpriv->dio_direction[port] = COMEDI_INPUT;
348                 writeb(1, devpriv->mite->daq_io_addr + Port_Select(port));
349                 return 1;
350                 break;
351         case INSN_CONFIG_DIO_QUERY:
352                 if (s->type != COMEDI_SUBD_DIO)
353                         return -EINVAL;
354                 data[1] = devpriv->dio_direction[port];
355                 return insn->n;
356                 break;
357         default:
358                 break;
359         }
360         return -EINVAL;
361 }
362 
363 static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
364                                  struct comedi_subdevice *s,
365                                  struct comedi_insn *insn, unsigned int *data)
366 {
367         const struct ni_65xx_board *board = comedi_board(dev);
368         struct ni_65xx_private *devpriv = dev->private;
369         int base_bitfield_channel;
370         unsigned read_bits = 0;
371         int last_port_offset = ni_65xx_port_by_channel(s->n_chan - 1);
372         int port_offset;
373 
374         base_bitfield_channel = CR_CHAN(insn->chanspec);
375         for (port_offset = ni_65xx_port_by_channel(base_bitfield_channel);
376              port_offset <= last_port_offset; port_offset++) {
377                 unsigned port = sprivate(s)->base_port + port_offset;
378                 int base_port_channel = port_offset * ni_65xx_channels_per_port;
379                 unsigned port_mask, port_data, port_read_bits;
380                 int bitshift = base_port_channel - base_bitfield_channel;
381 
382                 if (bitshift >= 32)
383                         break;
384                 port_mask = data[0];
385                 port_data = data[1];
386                 if (bitshift > 0) {
387                         port_mask >>= bitshift;
388                         port_data >>= bitshift;
389                 } else {
390                         port_mask <<= -bitshift;
391                         port_data <<= -bitshift;
392                 }
393                 port_mask &= 0xff;
394                 port_data &= 0xff;
395                 if (port_mask) {
396                         unsigned bits;
397                         devpriv->output_bits[port] &= ~port_mask;
398                         devpriv->output_bits[port] |=
399                             port_data & port_mask;
400                         bits = devpriv->output_bits[port];
401                         if (board->invert_outputs)
402                                 bits = ~bits;
403                         writeb(bits,
404                                devpriv->mite->daq_io_addr +
405                                Port_Data(port));
406                 }
407                 port_read_bits =
408                     readb(devpriv->mite->daq_io_addr + Port_Data(port));
409                 if (s->type == COMEDI_SUBD_DO && board->invert_outputs) {
410                         /* Outputs inverted, so invert value read back from
411                          * DO subdevice.  (Does not apply to boards with DIO
412                          * subdevice.) */
413                         port_read_bits ^= 0xFF;
414                 }
415                 if (bitshift > 0)
416                         port_read_bits <<= bitshift;
417                 else
418                         port_read_bits >>= -bitshift;
419 
420                 read_bits |= port_read_bits;
421         }
422         data[1] = read_bits;
423         return insn->n;
424 }
425 
426 static irqreturn_t ni_65xx_interrupt(int irq, void *d)
427 {
428         struct comedi_device *dev = d;
429         struct ni_65xx_private *devpriv = dev->private;
430         struct comedi_subdevice *s = dev->read_subdev;
431         unsigned int status;
432 
433         status = readb(devpriv->mite->daq_io_addr + Change_Status);
434         if ((status & MasterInterruptStatus) == 0)
435                 return IRQ_NONE;
436         if ((status & EdgeStatus) == 0)
437                 return IRQ_NONE;
438 
439         writeb(ClrEdge | ClrOverflow,
440                devpriv->mite->daq_io_addr + Clear_Register);
441 
442         comedi_buf_put(s, 0);
443         s->async->events |= COMEDI_CB_EOS;
444         comedi_event(dev, s);
445         return IRQ_HANDLED;
446 }
447 
448 static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
449                                 struct comedi_subdevice *s,
450                                 struct comedi_cmd *cmd)
451 {
452         int err = 0;
453 
454         /* Step 1 : check if triggers are trivially valid */
455 
456         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
457         err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
458         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
459         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
460         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
461 
462         if (err)
463                 return 1;
464 
465         /* Step 2a : make sure trigger sources are unique */
466         /* Step 2b : and mutually compatible */
467 
468         if (err)
469                 return 2;
470 
471         /* Step 3: check if arguments are trivially valid */
472 
473         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
474         err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
475         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
476         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
477         err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
478 
479         if (err)
480                 return 3;
481 
482         /* step 4: fix up any arguments */
483 
484         if (err)
485                 return 4;
486 
487         return 0;
488 }
489 
490 static int ni_65xx_intr_cmd(struct comedi_device *dev,
491                             struct comedi_subdevice *s)
492 {
493         struct ni_65xx_private *devpriv = dev->private;
494 
495         writeb(ClrEdge | ClrOverflow,
496                devpriv->mite->daq_io_addr + Clear_Register);
497         writeb(FallingEdgeIntEnable | RisingEdgeIntEnable |
498                MasterInterruptEnable | EdgeIntEnable,
499                devpriv->mite->daq_io_addr + Master_Interrupt_Control);
500 
501         return 0;
502 }
503 
504 static int ni_65xx_intr_cancel(struct comedi_device *dev,
505                                struct comedi_subdevice *s)
506 {
507         struct ni_65xx_private *devpriv = dev->private;
508 
509         writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
510 
511         return 0;
512 }
513 
514 static int ni_65xx_intr_insn_bits(struct comedi_device *dev,
515                                   struct comedi_subdevice *s,
516                                   struct comedi_insn *insn, unsigned int *data)
517 {
518         data[1] = 0;
519         return insn->n;
520 }
521 
522 static int ni_65xx_intr_insn_config(struct comedi_device *dev,
523                                     struct comedi_subdevice *s,
524                                     struct comedi_insn *insn,
525                                     unsigned int *data)
526 {
527         struct ni_65xx_private *devpriv = dev->private;
528 
529         if (insn->n < 1)
530                 return -EINVAL;
531         if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
532                 return -EINVAL;
533 
534         writeb(data[1],
535                devpriv->mite->daq_io_addr +
536                Rising_Edge_Detection_Enable(0));
537         writeb(data[1] >> 8,
538                devpriv->mite->daq_io_addr +
539                Rising_Edge_Detection_Enable(0x10));
540         writeb(data[1] >> 16,
541                devpriv->mite->daq_io_addr +
542                Rising_Edge_Detection_Enable(0x20));
543         writeb(data[1] >> 24,
544                devpriv->mite->daq_io_addr +
545                Rising_Edge_Detection_Enable(0x30));
546 
547         writeb(data[2],
548                devpriv->mite->daq_io_addr +
549                Falling_Edge_Detection_Enable(0));
550         writeb(data[2] >> 8,
551                devpriv->mite->daq_io_addr +
552                Falling_Edge_Detection_Enable(0x10));
553         writeb(data[2] >> 16,
554                devpriv->mite->daq_io_addr +
555                Falling_Edge_Detection_Enable(0x20));
556         writeb(data[2] >> 24,
557                devpriv->mite->daq_io_addr +
558                Falling_Edge_Detection_Enable(0x30));
559 
560         return 2;
561 }
562 
563 static int ni_65xx_auto_attach(struct comedi_device *dev,
564                                unsigned long context)
565 {
566         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
567         const struct ni_65xx_board *board = NULL;
568         struct ni_65xx_private *devpriv;
569         struct ni_65xx_subdevice_private *spriv;
570         struct comedi_subdevice *s;
571         unsigned i;
572         int ret;
573 
574         if (context < ARRAY_SIZE(ni_65xx_boards))
575                 board = &ni_65xx_boards[context];
576         if (!board)
577                 return -ENODEV;
578         dev->board_ptr = board;
579         dev->board_name = board->name;
580 
581         ret = comedi_pci_enable(dev);
582         if (ret)
583                 return ret;
584 
585         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
586         if (!devpriv)
587                 return -ENOMEM;
588 
589         devpriv->mite = mite_alloc(pcidev);
590         if (!devpriv->mite)
591                 return -ENOMEM;
592 
593         ret = mite_setup(devpriv->mite);
594         if (ret < 0) {
595                 dev_warn(dev->class_dev, "error setting up mite\n");
596                 return ret;
597         }
598 
599         dev->irq = mite_irq(devpriv->mite);
600         dev_info(dev->class_dev, "board: %s, ID=0x%02x", dev->board_name,
601                readb(devpriv->mite->daq_io_addr + ID_Register));
602 
603         ret = comedi_alloc_subdevices(dev, 4);
604         if (ret)
605                 return ret;
606 
607         s = &dev->subdevices[0];
608         if (board->num_di_ports) {
609                 s->type = COMEDI_SUBD_DI;
610                 s->subdev_flags = SDF_READABLE;
611                 s->n_chan =
612                     board->num_di_ports * ni_65xx_channels_per_port;
613                 s->range_table = &range_digital;
614                 s->maxdata = 1;
615                 s->insn_config = ni_65xx_dio_insn_config;
616                 s->insn_bits = ni_65xx_dio_insn_bits;
617                 spriv = comedi_alloc_spriv(s, sizeof(*spriv));
618                 if (!spriv)
619                         return -ENOMEM;
620                 spriv->base_port = 0;
621         } else {
622                 s->type = COMEDI_SUBD_UNUSED;
623         }
624 
625         s = &dev->subdevices[1];
626         if (board->num_do_ports) {
627                 s->type = COMEDI_SUBD_DO;
628                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
629                 s->n_chan =
630                     board->num_do_ports * ni_65xx_channels_per_port;
631                 s->range_table = &range_digital;
632                 s->maxdata = 1;
633                 s->insn_bits = ni_65xx_dio_insn_bits;
634                 spriv = comedi_alloc_spriv(s, sizeof(*spriv));
635                 if (!spriv)
636                         return -ENOMEM;
637                 spriv->base_port = board->num_di_ports;
638         } else {
639                 s->type = COMEDI_SUBD_UNUSED;
640         }
641 
642         s = &dev->subdevices[2];
643         if (board->num_dio_ports) {
644                 s->type = COMEDI_SUBD_DIO;
645                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
646                 s->n_chan =
647                     board->num_dio_ports * ni_65xx_channels_per_port;
648                 s->range_table = &range_digital;
649                 s->maxdata = 1;
650                 s->insn_config = ni_65xx_dio_insn_config;
651                 s->insn_bits = ni_65xx_dio_insn_bits;
652                 spriv = comedi_alloc_spriv(s, sizeof(*spriv));
653                 if (!spriv)
654                         return -ENOMEM;
655                 spriv->base_port = 0;
656                 for (i = 0; i < board->num_dio_ports; ++i) {
657                         /*  configure all ports for input */
658                         writeb(0x1,
659                                devpriv->mite->daq_io_addr +
660                                Port_Select(i));
661                 }
662         } else {
663                 s->type = COMEDI_SUBD_UNUSED;
664         }
665 
666         s = &dev->subdevices[3];
667         dev->read_subdev = s;
668         s->type = COMEDI_SUBD_DI;
669         s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
670         s->n_chan = 1;
671         s->range_table = &range_unknown;
672         s->maxdata = 1;
673         s->len_chanlist = 1;
674         s->do_cmdtest = ni_65xx_intr_cmdtest;
675         s->do_cmd = ni_65xx_intr_cmd;
676         s->cancel = ni_65xx_intr_cancel;
677         s->insn_bits = ni_65xx_intr_insn_bits;
678         s->insn_config = ni_65xx_intr_insn_config;
679 
680         for (i = 0; i < ni_65xx_total_num_ports(board); ++i) {
681                 writeb(0x00,
682                        devpriv->mite->daq_io_addr + Filter_Enable(i));
683                 if (board->invert_outputs)
684                         writeb(0x01,
685                                devpriv->mite->daq_io_addr + Port_Data(i));
686                 else
687                         writeb(0x00,
688                                devpriv->mite->daq_io_addr + Port_Data(i));
689         }
690         writeb(ClrEdge | ClrOverflow,
691                devpriv->mite->daq_io_addr + Clear_Register);
692         writeb(0x00,
693                devpriv->mite->daq_io_addr + Master_Interrupt_Control);
694 
695         /* Set filter interval to 0  (32bit reg) */
696         writeb(0x00000000, devpriv->mite->daq_io_addr + Filter_Interval);
697 
698         ret = request_irq(dev->irq, ni_65xx_interrupt, IRQF_SHARED,
699                           "ni_65xx", dev);
700         if (ret < 0) {
701                 dev->irq = 0;
702                 dev_warn(dev->class_dev, "irq not available\n");
703         }
704 
705         return 0;
706 }
707 
708 static void ni_65xx_detach(struct comedi_device *dev)
709 {
710         struct ni_65xx_private *devpriv = dev->private;
711 
712         if (devpriv && devpriv->mite && devpriv->mite->daq_io_addr) {
713                 writeb(0x00,
714                        devpriv->mite->daq_io_addr +
715                        Master_Interrupt_Control);
716         }
717         if (dev->irq)
718                 free_irq(dev->irq, dev);
719         if (devpriv) {
720                 if (devpriv->mite) {
721                         mite_unsetup(devpriv->mite);
722                         mite_free(devpriv->mite);
723                 }
724         }
725         comedi_pci_disable(dev);
726 }
727 
728 static struct comedi_driver ni_65xx_driver = {
729         .driver_name = "ni_65xx",
730         .module = THIS_MODULE,
731         .auto_attach = ni_65xx_auto_attach,
732         .detach = ni_65xx_detach,
733 };
734 
735 static int ni_65xx_pci_probe(struct pci_dev *dev,
736                              const struct pci_device_id *id)
737 {
738         return comedi_pci_auto_config(dev, &ni_65xx_driver, id->driver_data);
739 }
740 
741 static const struct pci_device_id ni_65xx_pci_table[] = {
742         { PCI_VDEVICE(NI, 0x1710), BOARD_PXI6509 },
743         { PCI_VDEVICE(NI, 0x7085), BOARD_PCI6509 },
744         { PCI_VDEVICE(NI, 0x7086), BOARD_PXI6528 },
745         { PCI_VDEVICE(NI, 0x7087), BOARD_PCI6515 },
746         { PCI_VDEVICE(NI, 0x7088), BOARD_PCI6514 },
747         { PCI_VDEVICE(NI, 0x70a9), BOARD_PCI6528 },
748         { PCI_VDEVICE(NI, 0x70c3), BOARD_PCI6511 },
749         { PCI_VDEVICE(NI, 0x70c8), BOARD_PCI6513 },
750         { PCI_VDEVICE(NI, 0x70c9), BOARD_PXI6515 },
751         { PCI_VDEVICE(NI, 0x70cc), BOARD_PCI6512 },
752         { PCI_VDEVICE(NI, 0x70cd), BOARD_PXI6514 },
753         { PCI_VDEVICE(NI, 0x70d1), BOARD_PXI6513 },
754         { PCI_VDEVICE(NI, 0x70d2), BOARD_PXI6512 },
755         { PCI_VDEVICE(NI, 0x70d3), BOARD_PXI6511 },
756         { PCI_VDEVICE(NI, 0x7124), BOARD_PCI6510 },
757         { PCI_VDEVICE(NI, 0x7125), BOARD_PCI6516 },
758         { PCI_VDEVICE(NI, 0x7126), BOARD_PCI6517 },
759         { PCI_VDEVICE(NI, 0x7127), BOARD_PCI6518 },
760         { PCI_VDEVICE(NI, 0x7128), BOARD_PCI6519 },
761         { PCI_VDEVICE(NI, 0x718b), BOARD_PCI6521 },
762         { PCI_VDEVICE(NI, 0x718c), BOARD_PXI6521 },
763         { PCI_VDEVICE(NI, 0x71c5), BOARD_PCI6520 },
764         { 0 }
765 };
766 MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
767 
768 static struct pci_driver ni_65xx_pci_driver = {
769         .name           = "ni_65xx",
770         .id_table       = ni_65xx_pci_table,
771         .probe          = ni_65xx_pci_probe,
772         .remove         = comedi_pci_auto_unconfig,
773 };
774 module_comedi_pci_driver(ni_65xx_driver, ni_65xx_pci_driver);
775 
776 MODULE_AUTHOR("Comedi http://www.comedi.org");
777 MODULE_DESCRIPTION("Comedi low-level driver");
778 MODULE_LICENSE("GPL");
779 

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