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Linux/drivers/staging/comedi/drivers/ni_65xx.c

  1 /*
  2  * ni_65xx.c
  3  * Comedi driver for National Instruments PCI-65xx static dio boards
  4  *
  5  * Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
  6  * Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
  7  *
  8  * COMEDI - Linux Control and Measurement Device Interface
  9  * Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
 10  *
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License as published by
 13  * the Free Software Foundation; either version 2 of the License, or
 14  * (at your option) any later version.
 15  *
 16  * This program is distributed in the hope that it will be useful,
 17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19  * GNU General Public License for more details.
 20  */
 21 
 22 /*
 23  * Driver: ni_65xx
 24  * Description: National Instruments 65xx static dio boards
 25  * Author: Jon Grierson <jd@renko.co.uk>,
 26  *         Frank Mori Hess <fmhess@users.sourceforge.net>
 27  * Status: testing
 28  * Devices: [National Instruments] PCI-6509 (pci-6509), PXI-6509 (pxi-6509),
 29  *   PCI-6510 (pci-6510), PCI-6511 (pci-6511), PXI-6511 (pxi-6511),
 30  *   PCI-6512 (pci-6512), PXI-6512 (pxi-6512), PCI-6513 (pci-6513),
 31  *   PXI-6513 (pxi-6513), PCI-6514 (pci-6514), PXI-6514 (pxi-6514),
 32  *   PCI-6515 (pxi-6515), PXI-6515 (pxi-6515), PCI-6516 (pci-6516),
 33  *   PCI-6517 (pci-6517), PCI-6518 (pci-6518), PCI-6519 (pci-6519),
 34  *   PCI-6520 (pci-6520), PCI-6521 (pci-6521), PXI-6521 (pxi-6521),
 35  *   PCI-6528 (pci-6528), PXI-6528 (pxi-6528)
 36  * Updated: Mon, 21 Jul 2014 12:49:58 +0000
 37  *
 38  * Configuration Options: not applicable, uses PCI auto config
 39  *
 40  * Based on the PCI-6527 driver by ds.
 41  * The interrupt subdevice (subdevice 3) is probably broken for all
 42  * boards except maybe the 6514.
 43  *
 44  * This driver previously inverted the outputs on PCI-6513 through to
 45  * PCI-6519 and on PXI-6513 through to PXI-6515.  It no longer inverts
 46  * outputs on those cards by default as it didn't make much sense.  If
 47  * you require the outputs to be inverted on those cards for legacy
 48  * reasons, set the module parameter "legacy_invert_outputs=true" when
 49  * loading the module, or set "ni_65xx.legacy_invert_outputs=true" on
 50  * the kernel command line if the driver is built in to the kernel.
 51  */
 52 
 53 /*
 54  * Manuals (available from ftp://ftp.natinst.com/support/manuals)
 55  *
 56  *      370106b.pdf     6514 Register Level Programmer Manual
 57  */
 58 
 59 #include <linux/module.h>
 60 #include <linux/pci.h>
 61 #include <linux/interrupt.h>
 62 
 63 #include "../comedidev.h"
 64 
 65 #include "comedi_fc.h"
 66 
 67 /*
 68  * PCI BAR1 Register Map
 69  */
 70 
 71 /* Non-recurring Registers (8-bit except where noted) */
 72 #define NI_65XX_ID_REG                  0x00
 73 #define NI_65XX_CLR_REG                 0x01
 74 #define NI_65XX_CLR_WDOG_INT            (1 << 6)
 75 #define NI_65XX_CLR_WDOG_PING           (1 << 5)
 76 #define NI_65XX_CLR_WDOG_EXP            (1 << 4)
 77 #define NI_65XX_CLR_EDGE_INT            (1 << 3)
 78 #define NI_65XX_CLR_OVERFLOW_INT        (1 << 2)
 79 #define NI_65XX_STATUS_REG              0x02
 80 #define NI_65XX_STATUS_WDOG_INT         (1 << 5)
 81 #define NI_65XX_STATUS_FALL_EDGE        (1 << 4)
 82 #define NI_65XX_STATUS_RISE_EDGE        (1 << 3)
 83 #define NI_65XX_STATUS_INT              (1 << 2)
 84 #define NI_65XX_STATUS_OVERFLOW_INT     (1 << 1)
 85 #define NI_65XX_STATUS_EDGE_INT         (1 << 0)
 86 #define NI_65XX_CTRL_REG                0x03
 87 #define NI_65XX_CTRL_WDOG_ENA           (1 << 5)
 88 #define NI_65XX_CTRL_FALL_EDGE_ENA      (1 << 4)
 89 #define NI_65XX_CTRL_RISE_EDGE_ENA      (1 << 3)
 90 #define NI_65XX_CTRL_INT_ENA            (1 << 2)
 91 #define NI_65XX_CTRL_OVERFLOW_ENA       (1 << 1)
 92 #define NI_65XX_CTRL_EDGE_ENA           (1 << 0)
 93 #define NI_65XX_REV_REG                 0x04 /* 32-bit */
 94 #define NI_65XX_FILTER_REG              0x08 /* 32-bit */
 95 #define NI_65XX_RTSI_ROUTE_REG          0x0c /* 16-bit */
 96 #define NI_65XX_RTSI_EDGE_REG           0x0e /* 16-bit */
 97 #define NI_65XX_RTSI_WDOG_REG           0x10 /* 16-bit */
 98 #define NI_65XX_RTSI_TRIG_REG           0x12 /* 16-bit */
 99 #define NI_65XX_AUTO_CLK_SEL_REG        0x14 /* PXI-6528 only */
100 #define NI_65XX_AUTO_CLK_SEL_STATUS     (1 << 1)
101 #define NI_65XX_AUTO_CLK_SEL_DISABLE    (1 << 0)
102 #define NI_65XX_WDOG_CTRL_REG           0x15
103 #define NI_65XX_WDOG_CTRL_ENA           (1 << 0)
104 #define NI_65XX_RTSI_CFG_REG            0x16
105 #define NI_65XX_RTSI_CFG_RISE_SENSE     (1 << 2)
106 #define NI_65XX_RTSI_CFG_FALL_SENSE     (1 << 1)
107 #define NI_65XX_RTSI_CFG_SYNC_DETECT    (1 << 0)
108 #define NI_65XX_WDOG_STATUS_REG         0x17
109 #define NI_65XX_WDOG_STATUS_EXP         (1 << 0)
110 #define NI_65XX_WDOG_INTERVAL_REG       0x18 /* 32-bit */
111 
112 /* Recurring port registers (8-bit) */
113 #define NI_65XX_PORT(x)                 ((x) * 0x10)
114 #define NI_65XX_IO_DATA_REG(x)          (0x40 + NI_65XX_PORT(x))
115 #define NI_65XX_IO_SEL_REG(x)           (0x41 + NI_65XX_PORT(x))
116 #define NI_65XX_IO_SEL_OUTPUT           (0 << 0)
117 #define NI_65XX_IO_SEL_INPUT            (1 << 0)
118 #define NI_65XX_RISE_EDGE_ENA_REG(x)    (0x42 + NI_65XX_PORT(x))
119 #define NI_65XX_FALL_EDGE_ENA_REG(x)    (0x43 + NI_65XX_PORT(x))
120 #define NI_65XX_FILTER_ENA(x)           (0x44 + NI_65XX_PORT(x))
121 #define NI_65XX_WDOG_HIZ_REG(x)         (0x46 + NI_65XX_PORT(x))
122 #define NI_65XX_WDOG_ENA(x)             (0x47 + NI_65XX_PORT(x))
123 #define NI_65XX_WDOG_HI_LO_REG(x)       (0x48 + NI_65XX_PORT(x))
124 #define NI_65XX_RTSI_ENA(x)             (0x49 + NI_65XX_PORT(x))
125 
126 #define NI_65XX_PORT_TO_CHAN(x)         ((x) * 8)
127 #define NI_65XX_CHAN_TO_PORT(x)         ((x) / 8)
128 #define NI_65XX_CHAN_TO_MASK(x)         (1 << ((x) % 8))
129 
130 enum ni_65xx_boardid {
131         BOARD_PCI6509,
132         BOARD_PXI6509,
133         BOARD_PCI6510,
134         BOARD_PCI6511,
135         BOARD_PXI6511,
136         BOARD_PCI6512,
137         BOARD_PXI6512,
138         BOARD_PCI6513,
139         BOARD_PXI6513,
140         BOARD_PCI6514,
141         BOARD_PXI6514,
142         BOARD_PCI6515,
143         BOARD_PXI6515,
144         BOARD_PCI6516,
145         BOARD_PCI6517,
146         BOARD_PCI6518,
147         BOARD_PCI6519,
148         BOARD_PCI6520,
149         BOARD_PCI6521,
150         BOARD_PXI6521,
151         BOARD_PCI6528,
152         BOARD_PXI6528,
153 };
154 
155 struct ni_65xx_board {
156         const char *name;
157         unsigned num_dio_ports;
158         unsigned num_di_ports;
159         unsigned num_do_ports;
160         unsigned legacy_invert:1;
161 };
162 
163 static const struct ni_65xx_board ni_65xx_boards[] = {
164         [BOARD_PCI6509] = {
165                 .name           = "pci-6509",
166                 .num_dio_ports  = 12,
167         },
168         [BOARD_PXI6509] = {
169                 .name           = "pxi-6509",
170                 .num_dio_ports  = 12,
171         },
172         [BOARD_PCI6510] = {
173                 .name           = "pci-6510",
174                 .num_di_ports   = 4,
175         },
176         [BOARD_PCI6511] = {
177                 .name           = "pci-6511",
178                 .num_di_ports   = 8,
179         },
180         [BOARD_PXI6511] = {
181                 .name           = "pxi-6511",
182                 .num_di_ports   = 8,
183         },
184         [BOARD_PCI6512] = {
185                 .name           = "pci-6512",
186                 .num_do_ports   = 8,
187         },
188         [BOARD_PXI6512] = {
189                 .name           = "pxi-6512",
190                 .num_do_ports   = 8,
191         },
192         [BOARD_PCI6513] = {
193                 .name           = "pci-6513",
194                 .num_do_ports   = 8,
195                 .legacy_invert  = 1,
196         },
197         [BOARD_PXI6513] = {
198                 .name           = "pxi-6513",
199                 .num_do_ports   = 8,
200                 .legacy_invert  = 1,
201         },
202         [BOARD_PCI6514] = {
203                 .name           = "pci-6514",
204                 .num_di_ports   = 4,
205                 .num_do_ports   = 4,
206                 .legacy_invert  = 1,
207         },
208         [BOARD_PXI6514] = {
209                 .name           = "pxi-6514",
210                 .num_di_ports   = 4,
211                 .num_do_ports   = 4,
212                 .legacy_invert  = 1,
213         },
214         [BOARD_PCI6515] = {
215                 .name           = "pci-6515",
216                 .num_di_ports   = 4,
217                 .num_do_ports   = 4,
218                 .legacy_invert  = 1,
219         },
220         [BOARD_PXI6515] = {
221                 .name           = "pxi-6515",
222                 .num_di_ports   = 4,
223                 .num_do_ports   = 4,
224                 .legacy_invert  = 1,
225         },
226         [BOARD_PCI6516] = {
227                 .name           = "pci-6516",
228                 .num_do_ports   = 4,
229                 .legacy_invert  = 1,
230         },
231         [BOARD_PCI6517] = {
232                 .name           = "pci-6517",
233                 .num_do_ports   = 4,
234                 .legacy_invert  = 1,
235         },
236         [BOARD_PCI6518] = {
237                 .name           = "pci-6518",
238                 .num_di_ports   = 2,
239                 .num_do_ports   = 2,
240                 .legacy_invert  = 1,
241         },
242         [BOARD_PCI6519] = {
243                 .name           = "pci-6519",
244                 .num_di_ports   = 2,
245                 .num_do_ports   = 2,
246                 .legacy_invert  = 1,
247         },
248         [BOARD_PCI6520] = {
249                 .name           = "pci-6520",
250                 .num_di_ports   = 1,
251                 .num_do_ports   = 1,
252         },
253         [BOARD_PCI6521] = {
254                 .name           = "pci-6521",
255                 .num_di_ports   = 1,
256                 .num_do_ports   = 1,
257         },
258         [BOARD_PXI6521] = {
259                 .name           = "pxi-6521",
260                 .num_di_ports   = 1,
261                 .num_do_ports   = 1,
262         },
263         [BOARD_PCI6528] = {
264                 .name           = "pci-6528",
265                 .num_di_ports   = 3,
266                 .num_do_ports   = 3,
267         },
268         [BOARD_PXI6528] = {
269                 .name           = "pxi-6528",
270                 .num_di_ports   = 3,
271                 .num_do_ports   = 3,
272         },
273 };
274 
275 static bool ni_65xx_legacy_invert_outputs;
276 module_param_named(legacy_invert_outputs, ni_65xx_legacy_invert_outputs,
277                    bool, 0444);
278 MODULE_PARM_DESC(legacy_invert_outputs,
279                  "invert outputs of PCI/PXI-6513/6514/6515/6516/6517/6518/6519 for compatibility with old user code");
280 
281 static unsigned int ni_65xx_num_ports(struct comedi_device *dev)
282 {
283         const struct ni_65xx_board *board = dev->board_ptr;
284 
285         return board->num_dio_ports + board->num_di_ports + board->num_do_ports;
286 }
287 
288 static void ni_65xx_disable_input_filters(struct comedi_device *dev)
289 {
290         unsigned int num_ports = ni_65xx_num_ports(dev);
291         int i;
292 
293         /* disable input filtering on all ports */
294         for (i = 0; i < num_ports; ++i)
295                 writeb(0x00, dev->mmio + NI_65XX_FILTER_ENA(i));
296 
297         /* set filter interval to 0 (32bit reg) */
298         writel(0x00000000, dev->mmio + NI_65XX_FILTER_REG);
299 }
300 
301 /* updates edge detection for base_chan to base_chan+31 */
302 static void ni_65xx_update_edge_detection(struct comedi_device *dev,
303                                           unsigned int base_chan,
304                                           unsigned int rising,
305                                           unsigned int falling)
306 {
307         unsigned int num_ports = ni_65xx_num_ports(dev);
308         unsigned int port;
309 
310         if (base_chan >= NI_65XX_PORT_TO_CHAN(num_ports))
311                 return;
312 
313         for (port = NI_65XX_CHAN_TO_PORT(base_chan); port < num_ports; port++) {
314                 int bitshift = (int)(NI_65XX_PORT_TO_CHAN(port) - base_chan);
315                 unsigned int port_mask, port_rising, port_falling;
316 
317                 if (bitshift >= 32)
318                         break;
319 
320                 if (bitshift >= 0) {
321                         port_mask = ~0U >> bitshift;
322                         port_rising = rising >> bitshift;
323                         port_falling = falling >> bitshift;
324                 } else {
325                         port_mask = ~0U << -bitshift;
326                         port_rising = rising << -bitshift;
327                         port_falling = falling << -bitshift;
328                 }
329                 if (port_mask & 0xff) {
330                         if (~port_mask & 0xff) {
331                                 port_rising |=
332                                     readb(dev->mmio +
333                                           NI_65XX_RISE_EDGE_ENA_REG(port)) &
334                                     ~port_mask;
335                                 port_falling |=
336                                     readb(dev->mmio +
337                                           NI_65XX_FALL_EDGE_ENA_REG(port)) &
338                                     ~port_mask;
339                         }
340                         writeb(port_rising & 0xff,
341                                dev->mmio + NI_65XX_RISE_EDGE_ENA_REG(port));
342                         writeb(port_falling & 0xff,
343                                dev->mmio + NI_65XX_FALL_EDGE_ENA_REG(port));
344                 }
345         }
346 }
347 
348 static void ni_65xx_disable_edge_detection(struct comedi_device *dev)
349 {
350         /* clear edge detection for channels 0 to 31 */
351         ni_65xx_update_edge_detection(dev, 0, 0, 0);
352         /* clear edge detection for channels 32 to 63 */
353         ni_65xx_update_edge_detection(dev, 32, 0, 0);
354         /* clear edge detection for channels 64 to 95 */
355         ni_65xx_update_edge_detection(dev, 64, 0, 0);
356 }
357 
358 static int ni_65xx_dio_insn_config(struct comedi_device *dev,
359                                    struct comedi_subdevice *s,
360                                    struct comedi_insn *insn,
361                                    unsigned int *data)
362 {
363         unsigned long base_port = (unsigned long)s->private;
364         unsigned int chan = CR_CHAN(insn->chanspec);
365         unsigned int chan_mask = NI_65XX_CHAN_TO_MASK(chan);
366         unsigned port = base_port + NI_65XX_CHAN_TO_PORT(chan);
367         unsigned int interval;
368         unsigned int val;
369 
370         switch (data[0]) {
371         case INSN_CONFIG_FILTER:
372                 /*
373                  * The deglitch filter interval is specified in nanoseconds.
374                  * The hardware supports intervals in 200ns increments. Round
375                  * the user values up and return the actual interval.
376                  */
377                 interval = (data[1] + 100) / 200;
378                 if (interval > 0xfffff)
379                         interval = 0xfffff;
380                 data[1] = interval * 200;
381 
382                 /*
383                  * Enable/disable the channel for deglitch filtering. Note
384                  * that the filter interval is never set to ''. This is done
385                  * because other channels might still be enabled for filtering.
386                  */
387                 val = readb(dev->mmio + NI_65XX_FILTER_ENA(port));
388                 if (interval) {
389                         writel(interval, dev->mmio + NI_65XX_FILTER_REG);
390                         val |= chan_mask;
391                 } else {
392                         val &= ~chan_mask;
393                 }
394                 writeb(val, dev->mmio + NI_65XX_FILTER_ENA(port));
395                 break;
396 
397         case INSN_CONFIG_DIO_OUTPUT:
398                 if (s->type != COMEDI_SUBD_DIO)
399                         return -EINVAL;
400                 writeb(NI_65XX_IO_SEL_OUTPUT,
401                        dev->mmio + NI_65XX_IO_SEL_REG(port));
402                 break;
403 
404         case INSN_CONFIG_DIO_INPUT:
405                 if (s->type != COMEDI_SUBD_DIO)
406                         return -EINVAL;
407                 writeb(NI_65XX_IO_SEL_INPUT,
408                        dev->mmio + NI_65XX_IO_SEL_REG(port));
409                 break;
410 
411         case INSN_CONFIG_DIO_QUERY:
412                 if (s->type != COMEDI_SUBD_DIO)
413                         return -EINVAL;
414                 val = readb(dev->mmio + NI_65XX_IO_SEL_REG(port));
415                 data[1] = (val == NI_65XX_IO_SEL_INPUT) ? COMEDI_INPUT
416                                                         : COMEDI_OUTPUT;
417                 break;
418 
419         default:
420                 return -EINVAL;
421         }
422 
423         return insn->n;
424 }
425 
426 static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
427                                  struct comedi_subdevice *s,
428                                  struct comedi_insn *insn,
429                                  unsigned int *data)
430 {
431         unsigned long base_port = (unsigned long)s->private;
432         unsigned int base_chan = CR_CHAN(insn->chanspec);
433         int last_port_offset = NI_65XX_CHAN_TO_PORT(s->n_chan - 1);
434         unsigned read_bits = 0;
435         int port_offset;
436 
437         for (port_offset = NI_65XX_CHAN_TO_PORT(base_chan);
438              port_offset <= last_port_offset; port_offset++) {
439                 unsigned port = base_port + port_offset;
440                 int base_port_channel = NI_65XX_PORT_TO_CHAN(port_offset);
441                 unsigned port_mask, port_data, bits;
442                 int bitshift = base_port_channel - base_chan;
443 
444                 if (bitshift >= 32)
445                         break;
446                 port_mask = data[0];
447                 port_data = data[1];
448                 if (bitshift > 0) {
449                         port_mask >>= bitshift;
450                         port_data >>= bitshift;
451                 } else {
452                         port_mask <<= -bitshift;
453                         port_data <<= -bitshift;
454                 }
455                 port_mask &= 0xff;
456                 port_data &= 0xff;
457 
458                 /* update the outputs */
459                 if (port_mask) {
460                         bits = readb(dev->mmio + NI_65XX_IO_DATA_REG(port));
461                         bits ^= s->io_bits;     /* invert if necessary */
462                         bits &= ~port_mask;
463                         bits |= (port_data & port_mask);
464                         bits ^= s->io_bits;     /* invert back */
465                         writeb(bits, dev->mmio + NI_65XX_IO_DATA_REG(port));
466                 }
467 
468                 /* read back the actual state */
469                 bits = readb(dev->mmio + NI_65XX_IO_DATA_REG(port));
470                 bits ^= s->io_bits;     /* invert if necessary */
471                 if (bitshift > 0)
472                         bits <<= bitshift;
473                 else
474                         bits >>= -bitshift;
475 
476                 read_bits |= bits;
477         }
478         data[1] = read_bits;
479         return insn->n;
480 }
481 
482 static irqreturn_t ni_65xx_interrupt(int irq, void *d)
483 {
484         struct comedi_device *dev = d;
485         struct comedi_subdevice *s = dev->read_subdev;
486         unsigned int status;
487 
488         status = readb(dev->mmio + NI_65XX_STATUS_REG);
489         if ((status & NI_65XX_STATUS_INT) == 0)
490                 return IRQ_NONE;
491         if ((status & NI_65XX_STATUS_EDGE_INT) == 0)
492                 return IRQ_NONE;
493 
494         writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
495                dev->mmio + NI_65XX_CLR_REG);
496 
497         comedi_buf_write_samples(s, &s->state, 1);
498         comedi_handle_events(dev, s);
499 
500         return IRQ_HANDLED;
501 }
502 
503 static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
504                                 struct comedi_subdevice *s,
505                                 struct comedi_cmd *cmd)
506 {
507         int err = 0;
508 
509         /* Step 1 : check if triggers are trivially valid */
510 
511         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
512         err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
513         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
514         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
515         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
516 
517         if (err)
518                 return 1;
519 
520         /* Step 2a : make sure trigger sources are unique */
521         /* Step 2b : and mutually compatible */
522 
523         /* Step 3: check if arguments are trivially valid */
524 
525         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
526         err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
527         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
528         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
529         err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
530 
531         if (err)
532                 return 3;
533 
534         /* Step 4: fix up any arguments */
535 
536         /* Step 5: check channel list if it exists */
537 
538         return 0;
539 }
540 
541 static int ni_65xx_intr_cmd(struct comedi_device *dev,
542                             struct comedi_subdevice *s)
543 {
544         writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
545                dev->mmio + NI_65XX_CLR_REG);
546         writeb(NI_65XX_CTRL_FALL_EDGE_ENA | NI_65XX_CTRL_RISE_EDGE_ENA |
547                NI_65XX_CTRL_INT_ENA | NI_65XX_CTRL_EDGE_ENA,
548                dev->mmio + NI_65XX_CTRL_REG);
549 
550         return 0;
551 }
552 
553 static int ni_65xx_intr_cancel(struct comedi_device *dev,
554                                struct comedi_subdevice *s)
555 {
556         writeb(0x00, dev->mmio + NI_65XX_CTRL_REG);
557 
558         return 0;
559 }
560 
561 static int ni_65xx_intr_insn_bits(struct comedi_device *dev,
562                                   struct comedi_subdevice *s,
563                                   struct comedi_insn *insn,
564                                   unsigned int *data)
565 {
566         data[1] = 0;
567         return insn->n;
568 }
569 
570 static int ni_65xx_intr_insn_config(struct comedi_device *dev,
571                                     struct comedi_subdevice *s,
572                                     struct comedi_insn *insn,
573                                     unsigned int *data)
574 {
575         switch (data[0]) {
576         case INSN_CONFIG_CHANGE_NOTIFY:
577                 /* add instruction to check_insn_config_length() */
578                 if (insn->n != 3)
579                         return -EINVAL;
580 
581                 /* update edge detection for channels 0 to 31 */
582                 ni_65xx_update_edge_detection(dev, 0, data[1], data[2]);
583                 /* clear edge detection for channels 32 to 63 */
584                 ni_65xx_update_edge_detection(dev, 32, 0, 0);
585                 /* clear edge detection for channels 64 to 95 */
586                 ni_65xx_update_edge_detection(dev, 64, 0, 0);
587                 break;
588         case INSN_CONFIG_DIGITAL_TRIG:
589                 /* check trigger number */
590                 if (data[1] != 0)
591                         return -EINVAL;
592                 /* check digital trigger operation */
593                 switch (data[2]) {
594                 case COMEDI_DIGITAL_TRIG_DISABLE:
595                         ni_65xx_disable_edge_detection(dev);
596                         break;
597                 case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
598                         /*
599                          * update edge detection for channels data[3]
600                          * to (data[3] + 31)
601                          */
602                         ni_65xx_update_edge_detection(dev, data[3],
603                                                       data[4], data[5]);
604                         break;
605                 default:
606                         return -EINVAL;
607                 }
608                 break;
609         default:
610                 return -EINVAL;
611         }
612 
613         return insn->n;
614 }
615 
616 /* ripped from mite.h and mite_setup2() to avoid mite dependancy */
617 #define MITE_IODWBSR    0xc0     /* IO Device Window Base Size Register */
618 #define WENAB           (1 << 7) /* window enable */
619 
620 static int ni_65xx_mite_init(struct pci_dev *pcidev)
621 {
622         void __iomem *mite_base;
623         u32 main_phys_addr;
624 
625         /* ioremap the MITE registers (BAR 0) temporarily */
626         mite_base = pci_ioremap_bar(pcidev, 0);
627         if (!mite_base)
628                 return -ENOMEM;
629 
630         /* set data window to main registers (BAR 1) */
631         main_phys_addr = pci_resource_start(pcidev, 1);
632         writel(main_phys_addr | WENAB, mite_base + MITE_IODWBSR);
633 
634         /* finished with MITE registers */
635         iounmap(mite_base);
636         return 0;
637 }
638 
639 static int ni_65xx_auto_attach(struct comedi_device *dev,
640                                unsigned long context)
641 {
642         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
643         const struct ni_65xx_board *board = NULL;
644         struct comedi_subdevice *s;
645         unsigned i;
646         int ret;
647 
648         if (context < ARRAY_SIZE(ni_65xx_boards))
649                 board = &ni_65xx_boards[context];
650         if (!board)
651                 return -ENODEV;
652         dev->board_ptr = board;
653         dev->board_name = board->name;
654 
655         ret = comedi_pci_enable(dev);
656         if (ret)
657                 return ret;
658 
659         ret = ni_65xx_mite_init(pcidev);
660         if (ret)
661                 return ret;
662 
663         dev->mmio = pci_ioremap_bar(pcidev, 1);
664         if (!dev->mmio)
665                 return -ENOMEM;
666 
667         writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
668                dev->mmio + NI_65XX_CLR_REG);
669         writeb(0x00, dev->mmio + NI_65XX_CTRL_REG);
670 
671         if (pcidev->irq) {
672                 ret = request_irq(pcidev->irq, ni_65xx_interrupt, IRQF_SHARED,
673                                   dev->board_name, dev);
674                 if (ret == 0)
675                         dev->irq = pcidev->irq;
676         }
677 
678         dev_info(dev->class_dev, "board: %s, ID=0x%02x", dev->board_name,
679                readb(dev->mmio + NI_65XX_ID_REG));
680 
681         ret = comedi_alloc_subdevices(dev, 4);
682         if (ret)
683                 return ret;
684 
685         s = &dev->subdevices[0];
686         if (board->num_di_ports) {
687                 s->type         = COMEDI_SUBD_DI;
688                 s->subdev_flags = SDF_READABLE;
689                 s->n_chan       = NI_65XX_PORT_TO_CHAN(board->num_di_ports);
690                 s->maxdata      = 1;
691                 s->range_table  = &range_digital;
692                 s->insn_bits    = ni_65xx_dio_insn_bits;
693                 s->insn_config  = ni_65xx_dio_insn_config;
694 
695                 /* the input ports always start at port 0 */
696                 s->private = (void *)0;
697         } else {
698                 s->type         = COMEDI_SUBD_UNUSED;
699         }
700 
701         s = &dev->subdevices[1];
702         if (board->num_do_ports) {
703                 s->type         = COMEDI_SUBD_DO;
704                 s->subdev_flags = SDF_WRITABLE;
705                 s->n_chan       = NI_65XX_PORT_TO_CHAN(board->num_do_ports);
706                 s->maxdata      = 1;
707                 s->range_table  = &range_digital;
708                 s->insn_bits    = ni_65xx_dio_insn_bits;
709 
710                 /* the output ports always start after the input ports */
711                 s->private = (void *)(unsigned long)board->num_di_ports;
712 
713                 /*
714                  * Use the io_bits to handle the inverted outputs.  Inverted
715                  * outputs are only supported if the "legacy_invert_outputs"
716                  * module parameter is set to "true".
717                  */
718                 if (ni_65xx_legacy_invert_outputs && board->legacy_invert)
719                         s->io_bits = 0xff;
720 
721                 /* reset all output ports to comedi '' */
722                 for (i = 0; i < board->num_do_ports; ++i) {
723                         writeb(s->io_bits,      /* inverted if necessary */
724                                dev->mmio +
725                                NI_65XX_IO_DATA_REG(board->num_di_ports + i));
726                 }
727         } else {
728                 s->type         = COMEDI_SUBD_UNUSED;
729         }
730 
731         s = &dev->subdevices[2];
732         if (board->num_dio_ports) {
733                 s->type         = COMEDI_SUBD_DIO;
734                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
735                 s->n_chan       = NI_65XX_PORT_TO_CHAN(board->num_dio_ports);
736                 s->maxdata      = 1;
737                 s->range_table  = &range_digital;
738                 s->insn_bits    = ni_65xx_dio_insn_bits;
739                 s->insn_config  = ni_65xx_dio_insn_config;
740 
741                 /* the input/output ports always start at port 0 */
742                 s->private = (void *)0;
743 
744                 /* configure all ports for input */
745                 for (i = 0; i < board->num_dio_ports; ++i) {
746                         writeb(NI_65XX_IO_SEL_INPUT,
747                                dev->mmio + NI_65XX_IO_SEL_REG(i));
748                 }
749         } else {
750                 s->type         = COMEDI_SUBD_UNUSED;
751         }
752 
753         s = &dev->subdevices[3];
754         s->type         = COMEDI_SUBD_DI;
755         s->subdev_flags = SDF_READABLE;
756         s->n_chan       = 1;
757         s->maxdata      = 1;
758         s->range_table  = &range_digital;
759         s->insn_bits    = ni_65xx_intr_insn_bits;
760         if (dev->irq) {
761                 dev->read_subdev = s;
762                 s->subdev_flags |= SDF_CMD_READ;
763                 s->len_chanlist = 1;
764                 s->insn_config  = ni_65xx_intr_insn_config;
765                 s->do_cmdtest   = ni_65xx_intr_cmdtest;
766                 s->do_cmd       = ni_65xx_intr_cmd;
767                 s->cancel       = ni_65xx_intr_cancel;
768         }
769 
770         ni_65xx_disable_input_filters(dev);
771         ni_65xx_disable_edge_detection(dev);
772 
773         return 0;
774 }
775 
776 static void ni_65xx_detach(struct comedi_device *dev)
777 {
778         if (dev->mmio)
779                 writeb(0x00, dev->mmio + NI_65XX_CTRL_REG);
780         comedi_pci_detach(dev);
781 }
782 
783 static struct comedi_driver ni_65xx_driver = {
784         .driver_name    = "ni_65xx",
785         .module         = THIS_MODULE,
786         .auto_attach    = ni_65xx_auto_attach,
787         .detach         = ni_65xx_detach,
788 };
789 
790 static int ni_65xx_pci_probe(struct pci_dev *dev,
791                              const struct pci_device_id *id)
792 {
793         return comedi_pci_auto_config(dev, &ni_65xx_driver, id->driver_data);
794 }
795 
796 static const struct pci_device_id ni_65xx_pci_table[] = {
797         { PCI_VDEVICE(NI, 0x1710), BOARD_PXI6509 },
798         { PCI_VDEVICE(NI, 0x7085), BOARD_PCI6509 },
799         { PCI_VDEVICE(NI, 0x7086), BOARD_PXI6528 },
800         { PCI_VDEVICE(NI, 0x7087), BOARD_PCI6515 },
801         { PCI_VDEVICE(NI, 0x7088), BOARD_PCI6514 },
802         { PCI_VDEVICE(NI, 0x70a9), BOARD_PCI6528 },
803         { PCI_VDEVICE(NI, 0x70c3), BOARD_PCI6511 },
804         { PCI_VDEVICE(NI, 0x70c8), BOARD_PCI6513 },
805         { PCI_VDEVICE(NI, 0x70c9), BOARD_PXI6515 },
806         { PCI_VDEVICE(NI, 0x70cc), BOARD_PCI6512 },
807         { PCI_VDEVICE(NI, 0x70cd), BOARD_PXI6514 },
808         { PCI_VDEVICE(NI, 0x70d1), BOARD_PXI6513 },
809         { PCI_VDEVICE(NI, 0x70d2), BOARD_PXI6512 },
810         { PCI_VDEVICE(NI, 0x70d3), BOARD_PXI6511 },
811         { PCI_VDEVICE(NI, 0x7124), BOARD_PCI6510 },
812         { PCI_VDEVICE(NI, 0x7125), BOARD_PCI6516 },
813         { PCI_VDEVICE(NI, 0x7126), BOARD_PCI6517 },
814         { PCI_VDEVICE(NI, 0x7127), BOARD_PCI6518 },
815         { PCI_VDEVICE(NI, 0x7128), BOARD_PCI6519 },
816         { PCI_VDEVICE(NI, 0x718b), BOARD_PCI6521 },
817         { PCI_VDEVICE(NI, 0x718c), BOARD_PXI6521 },
818         { PCI_VDEVICE(NI, 0x71c5), BOARD_PCI6520 },
819         { 0 }
820 };
821 MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
822 
823 static struct pci_driver ni_65xx_pci_driver = {
824         .name           = "ni_65xx",
825         .id_table       = ni_65xx_pci_table,
826         .probe          = ni_65xx_pci_probe,
827         .remove         = comedi_pci_auto_unconfig,
828 };
829 module_comedi_pci_driver(ni_65xx_driver, ni_65xx_pci_driver);
830 
831 MODULE_AUTHOR("Comedi http://www.comedi.org");
832 MODULE_DESCRIPTION("Comedi driver for NI PCI-65xx static dio boards");
833 MODULE_LICENSE("GPL");
834 

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