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Linux/drivers/staging/comedi/drivers/ni_6527.c

  1 /*
  2  * ni_6527.c
  3  * Comedi driver for National Instruments PCI-6527
  4  *
  5  * COMEDI - Linux Control and Measurement Device Interface
  6  * Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  */
 18 
 19 /*
 20  * Driver: ni_6527
 21  * Description: National Instruments 6527
 22  * Devices: (National Instruments) PCI-6527 [pci-6527]
 23  *          (National Instruments) PXI-6527 [pxi-6527]
 24  * Author: David A. Schleef <ds@schleef.org>
 25  * Updated: Sat, 25 Jan 2003 13:24:40 -0800
 26  * Status: works
 27  *
 28  * Configuration Options: not applicable, uses PCI auto config
 29  */
 30 
 31 #include <linux/module.h>
 32 #include <linux/pci.h>
 33 #include <linux/interrupt.h>
 34 
 35 #include "../comedidev.h"
 36 
 37 #include "comedi_fc.h"
 38 
 39 /*
 40  * PCI BAR1 - Register memory map
 41  *
 42  * Manuals (available from ftp://ftp.natinst.com/support/manuals)
 43  *      370106b.pdf     6527 Register Level Programmer Manual
 44  */
 45 #define NI6527_DI_REG(x)                (0x00 + (x))
 46 #define NI6527_DO_REG(x)                (0x03 + (x))
 47 #define NI6527_ID_REG                   0x06
 48 #define NI6527_CLR_REG                  0x07
 49 #define NI6527_CLR_EDGE                 (1 << 3)
 50 #define NI6527_CLR_OVERFLOW             (1 << 2)
 51 #define NI6527_CLR_FILT                 (1 << 1)
 52 #define NI6527_CLR_INTERVAL             (1 << 0)
 53 #define NI6527_CLR_IRQS                 (NI6527_CLR_EDGE | NI6527_CLR_OVERFLOW)
 54 #define NI6527_CLR_RESET_FILT           (NI6527_CLR_FILT | NI6527_CLR_INTERVAL)
 55 #define NI6527_FILT_INTERVAL_REG(x)     (0x08 + (x))
 56 #define NI6527_FILT_ENA_REG(x)          (0x0c + (x))
 57 #define NI6527_STATUS_REG               0x14
 58 #define NI6527_STATUS_IRQ               (1 << 2)
 59 #define NI6527_STATUS_OVERFLOW          (1 << 1)
 60 #define NI6527_STATUS_EDGE              (1 << 0)
 61 #define NI6527_CTRL_REG                 0x15
 62 #define NI6527_CTRL_FALLING             (1 << 4)
 63 #define NI6527_CTRL_RISING              (1 << 3)
 64 #define NI6527_CTRL_IRQ                 (1 << 2)
 65 #define NI6527_CTRL_OVERFLOW            (1 << 1)
 66 #define NI6527_CTRL_EDGE                (1 << 0)
 67 #define NI6527_CTRL_DISABLE_IRQS        0
 68 #define NI6527_CTRL_ENABLE_IRQS         (NI6527_CTRL_FALLING | \
 69                                          NI6527_CTRL_RISING | \
 70                                          NI6527_CTRL_IRQ | NI6527_CTRL_EDGE)
 71 #define NI6527_RISING_EDGE_REG(x)       (0x18 + (x))
 72 #define NI6527_FALLING_EDGE_REG(x)      (0x20 + (x))
 73 
 74 enum ni6527_boardid {
 75         BOARD_PCI6527,
 76         BOARD_PXI6527,
 77 };
 78 
 79 struct ni6527_board {
 80         const char *name;
 81 };
 82 
 83 static const struct ni6527_board ni6527_boards[] = {
 84         [BOARD_PCI6527] = {
 85                 .name           = "pci-6527",
 86         },
 87         [BOARD_PXI6527] = {
 88                 .name           = "pxi-6527",
 89         },
 90 };
 91 
 92 struct ni6527_private {
 93         void __iomem *mmio_base;
 94         unsigned int filter_interval;
 95         unsigned int filter_enable;
 96 };
 97 
 98 static void ni6527_set_filter_interval(struct comedi_device *dev,
 99                                        unsigned int val)
100 {
101         struct ni6527_private *devpriv = dev->private;
102         void __iomem *mmio = devpriv->mmio_base;
103 
104         if (val != devpriv->filter_interval) {
105                 writeb(val & 0xff, mmio + NI6527_FILT_INTERVAL_REG(0));
106                 writeb((val >> 8) & 0xff, mmio + NI6527_FILT_INTERVAL_REG(1));
107                 writeb((val >> 16) & 0x0f, mmio + NI6527_FILT_INTERVAL_REG(2));
108 
109                 writeb(NI6527_CLR_INTERVAL, mmio + NI6527_CLR_REG);
110 
111                 devpriv->filter_interval = val;
112         }
113 }
114 
115 static void ni6527_set_filter_enable(struct comedi_device *dev,
116                                      unsigned int val)
117 {
118         struct ni6527_private *devpriv = dev->private;
119         void __iomem *mmio = devpriv->mmio_base;
120 
121         writeb(val & 0xff, mmio + NI6527_FILT_ENA_REG(0));
122         writeb((val >> 8) & 0xff, mmio + NI6527_FILT_ENA_REG(1));
123         writeb((val >> 16) & 0xff, mmio + NI6527_FILT_ENA_REG(2));
124 }
125 
126 static int ni6527_di_insn_config(struct comedi_device *dev,
127                                  struct comedi_subdevice *s,
128                                  struct comedi_insn *insn,
129                                  unsigned int *data)
130 {
131         struct ni6527_private *devpriv = dev->private;
132         unsigned int chan = CR_CHAN(insn->chanspec);
133         unsigned int interval;
134 
135         switch (data[0]) {
136         case INSN_CONFIG_FILTER:
137                 /*
138                  * The deglitch filter interval is specified in nanoseconds.
139                  * The hardware supports intervals in 200ns increments. Round
140                  * the user values up and return the actual interval.
141                  */
142                 interval = (data[1] + 100) / 200;
143                 data[1] = interval * 200;
144 
145                 if (interval) {
146                         ni6527_set_filter_interval(dev, interval);
147                         devpriv->filter_enable |= 1 << chan;
148                 } else {
149                         devpriv->filter_enable &= ~(1 << chan);
150                 }
151                 ni6527_set_filter_enable(dev, devpriv->filter_enable);
152                 break;
153         default:
154                 return -EINVAL;
155         }
156 
157         return insn->n;
158 }
159 
160 static int ni6527_di_insn_bits(struct comedi_device *dev,
161                                struct comedi_subdevice *s,
162                                struct comedi_insn *insn,
163                                unsigned int *data)
164 {
165         struct ni6527_private *devpriv = dev->private;
166         void __iomem *mmio = devpriv->mmio_base;
167         unsigned int val;
168 
169         val = readb(mmio + NI6527_DI_REG(0));
170         val |= (readb(mmio + NI6527_DI_REG(1)) << 8);
171         val |= (readb(mmio + NI6527_DI_REG(2)) << 16);
172 
173         data[1] = val;
174 
175         return insn->n;
176 }
177 
178 static int ni6527_do_insn_bits(struct comedi_device *dev,
179                                struct comedi_subdevice *s,
180                                struct comedi_insn *insn,
181                                unsigned int *data)
182 {
183         struct ni6527_private *devpriv = dev->private;
184         void __iomem *mmio = devpriv->mmio_base;
185         unsigned int mask;
186 
187         mask = comedi_dio_update_state(s, data);
188         if (mask) {
189                 /* Outputs are inverted */
190                 unsigned int val = s->state ^ 0xffffff;
191 
192                 if (mask & 0x0000ff)
193                         writeb(val & 0xff, mmio + NI6527_DO_REG(0));
194                 if (mask & 0x00ff00)
195                         writeb((val >> 8) & 0xff, mmio + NI6527_DO_REG(1));
196                 if (mask & 0xff0000)
197                         writeb((val >> 16) & 0xff, mmio + NI6527_DO_REG(2));
198         }
199 
200         data[1] = s->state;
201 
202         return insn->n;
203 }
204 
205 static irqreturn_t ni6527_interrupt(int irq, void *d)
206 {
207         struct comedi_device *dev = d;
208         struct ni6527_private *devpriv = dev->private;
209         struct comedi_subdevice *s = dev->read_subdev;
210         void __iomem *mmio = devpriv->mmio_base;
211         unsigned int status;
212 
213         status = readb(mmio + NI6527_STATUS_REG);
214         if (!(status & NI6527_STATUS_IRQ))
215                 return IRQ_NONE;
216 
217         if (status & NI6527_STATUS_EDGE) {
218                 comedi_buf_put(s, 0);
219                 s->async->events |= COMEDI_CB_EOS;
220                 comedi_event(dev, s);
221         }
222 
223         writeb(NI6527_CLR_IRQS, mmio + NI6527_CLR_REG);
224 
225         return IRQ_HANDLED;
226 }
227 
228 static int ni6527_intr_cmdtest(struct comedi_device *dev,
229                                struct comedi_subdevice *s,
230                                struct comedi_cmd *cmd)
231 {
232         int err = 0;
233 
234         /* Step 1 : check if triggers are trivially valid */
235 
236         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
237         err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
238         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
239         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
240         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
241 
242         if (err)
243                 return 1;
244 
245         /* Step 2a : make sure trigger sources are unique */
246         /* Step 2b : and mutually compatible */
247 
248         if (err)
249                 return 2;
250 
251         /* Step 3: check if arguments are trivially valid */
252 
253         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
254         err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
255         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
256         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
257         err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
258 
259         if (err)
260                 return 3;
261 
262         /* step 4: fix up any arguments */
263 
264         if (err)
265                 return 4;
266 
267         return 0;
268 }
269 
270 static int ni6527_intr_cmd(struct comedi_device *dev,
271                            struct comedi_subdevice *s)
272 {
273         struct ni6527_private *devpriv = dev->private;
274         void __iomem *mmio = devpriv->mmio_base;
275 
276         writeb(NI6527_CLR_IRQS, mmio + NI6527_CLR_REG);
277         writeb(NI6527_CTRL_ENABLE_IRQS, mmio + NI6527_CTRL_REG);
278 
279         return 0;
280 }
281 
282 static int ni6527_intr_cancel(struct comedi_device *dev,
283                               struct comedi_subdevice *s)
284 {
285         struct ni6527_private *devpriv = dev->private;
286         void __iomem *mmio = devpriv->mmio_base;
287 
288         writeb(NI6527_CTRL_DISABLE_IRQS, mmio + NI6527_CTRL_REG);
289 
290         return 0;
291 }
292 
293 static int ni6527_intr_insn_bits(struct comedi_device *dev,
294                                  struct comedi_subdevice *s,
295                                  struct comedi_insn *insn, unsigned int *data)
296 {
297         data[1] = 0;
298         return insn->n;
299 }
300 
301 static void ni6527_set_edge_detection(struct comedi_device *dev,
302                                       unsigned int rising,
303                                       unsigned int falling)
304 {
305         struct ni6527_private *devpriv = dev->private;
306         void __iomem *mmio = devpriv->mmio_base;
307 
308         /* enable rising-edge detection channels */
309         writeb(rising & 0xff, mmio + NI6527_RISING_EDGE_REG(0));
310         writeb((rising >> 8) & 0xff, mmio + NI6527_RISING_EDGE_REG(1));
311         writeb((rising >> 16) & 0xff, mmio + NI6527_RISING_EDGE_REG(2));
312 
313         /* enable falling-edge detection channels */
314         writeb(falling & 0xff, mmio + NI6527_FALLING_EDGE_REG(0));
315         writeb((falling >> 8) & 0xff, mmio + NI6527_FALLING_EDGE_REG(1));
316         writeb((falling >> 16) & 0xff, mmio + NI6527_FALLING_EDGE_REG(2));
317 }
318 
319 static int ni6527_intr_insn_config(struct comedi_device *dev,
320                                    struct comedi_subdevice *s,
321                                    struct comedi_insn *insn,
322                                    unsigned int *data)
323 {
324         switch (data[0]) {
325         case INSN_CONFIG_CHANGE_NOTIFY:
326                 /* check_insn_config_length() does not check this instruction */
327                 if (insn->n != 3)
328                         return -EINVAL;
329                 ni6527_set_edge_detection(dev, data[1], data[2]);
330                 break;
331         default:
332                 return -EINVAL;
333         }
334 
335         return insn->n;
336 }
337 
338 static void ni6527_reset(struct comedi_device *dev)
339 {
340         struct ni6527_private *devpriv = dev->private;
341         void __iomem *mmio = devpriv->mmio_base;
342 
343         /* disable deglitch filters on all channels */
344         ni6527_set_filter_enable(dev, 0);
345 
346         writeb(NI6527_CLR_IRQS | NI6527_CLR_RESET_FILT,
347                mmio + NI6527_CLR_REG);
348         writeb(NI6527_CTRL_DISABLE_IRQS, mmio + NI6527_CTRL_REG);
349 }
350 
351 static int ni6527_auto_attach(struct comedi_device *dev,
352                               unsigned long context)
353 {
354         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
355         const struct ni6527_board *board = NULL;
356         struct ni6527_private *devpriv;
357         struct comedi_subdevice *s;
358         int ret;
359 
360         if (context < ARRAY_SIZE(ni6527_boards))
361                 board = &ni6527_boards[context];
362         if (!board)
363                 return -ENODEV;
364         dev->board_ptr = board;
365         dev->board_name = board->name;
366 
367         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
368         if (!devpriv)
369                 return -ENOMEM;
370 
371         ret = comedi_pci_enable(dev);
372         if (ret)
373                 return ret;
374 
375         devpriv->mmio_base = pci_ioremap_bar(pcidev, 1);
376         if (!devpriv->mmio_base)
377                 return -ENOMEM;
378 
379         /* make sure this is actually a 6527 device */
380         if (readb(devpriv->mmio_base + NI6527_ID_REG) != 0x27)
381                 return -ENODEV;
382 
383         ni6527_reset(dev);
384 
385         ret = request_irq(pcidev->irq, ni6527_interrupt, IRQF_SHARED,
386                           dev->board_name, dev);
387         if (ret == 0)
388                 dev->irq = pcidev->irq;
389 
390         ret = comedi_alloc_subdevices(dev, 3);
391         if (ret)
392                 return ret;
393 
394         /* Digital Input subdevice */
395         s = &dev->subdevices[0];
396         s->type         = COMEDI_SUBD_DI;
397         s->subdev_flags = SDF_READABLE;
398         s->n_chan       = 24;
399         s->maxdata      = 1;
400         s->range_table  = &range_digital;
401         s->insn_config  = ni6527_di_insn_config;
402         s->insn_bits    = ni6527_di_insn_bits;
403 
404         /* Digital Output subdevice */
405         s = &dev->subdevices[1];
406         s->type         = COMEDI_SUBD_DO;
407         s->subdev_flags = SDF_WRITABLE;
408         s->n_chan       = 24;
409         s->maxdata      = 1;
410         s->range_table  = &range_digital;
411         s->insn_bits    = ni6527_do_insn_bits;
412 
413         /* Edge detection interrupt subdevice */
414         s = &dev->subdevices[2];
415         if (dev->irq) {
416                 dev->read_subdev = s;
417                 s->type         = COMEDI_SUBD_DI;
418                 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
419                 s->n_chan       = 1;
420                 s->maxdata      = 1;
421                 s->range_table  = &range_digital;
422                 s->insn_config  = ni6527_intr_insn_config;
423                 s->insn_bits    = ni6527_intr_insn_bits;
424                 s->len_chanlist = 1;
425                 s->do_cmdtest   = ni6527_intr_cmdtest;
426                 s->do_cmd       = ni6527_intr_cmd;
427                 s->cancel       = ni6527_intr_cancel;
428         } else {
429                 s->type = COMEDI_SUBD_UNUSED;
430         }
431 
432         return 0;
433 }
434 
435 static void ni6527_detach(struct comedi_device *dev)
436 {
437         struct ni6527_private *devpriv = dev->private;
438 
439         if (devpriv && devpriv->mmio_base)
440                 ni6527_reset(dev);
441         if (dev->irq)
442                 free_irq(dev->irq, dev);
443         comedi_pci_disable(dev);
444 }
445 
446 static struct comedi_driver ni6527_driver = {
447         .driver_name    = "ni_6527",
448         .module         = THIS_MODULE,
449         .auto_attach    = ni6527_auto_attach,
450         .detach         = ni6527_detach,
451 };
452 
453 static int ni6527_pci_probe(struct pci_dev *dev,
454                             const struct pci_device_id *id)
455 {
456         return comedi_pci_auto_config(dev, &ni6527_driver, id->driver_data);
457 }
458 
459 static const struct pci_device_id ni6527_pci_table[] = {
460         { PCI_VDEVICE(NI, 0x2b10), BOARD_PXI6527 },
461         { PCI_VDEVICE(NI, 0x2b20), BOARD_PCI6527 },
462         { 0 }
463 };
464 MODULE_DEVICE_TABLE(pci, ni6527_pci_table);
465 
466 static struct pci_driver ni6527_pci_driver = {
467         .name           = "ni_6527",
468         .id_table       = ni6527_pci_table,
469         .probe          = ni6527_pci_probe,
470         .remove         = comedi_pci_auto_unconfig,
471 };
472 module_comedi_pci_driver(ni6527_driver, ni6527_pci_driver);
473 
474 MODULE_AUTHOR("Comedi http://www.comedi.org");
475 MODULE_DESCRIPTION("Comedi driver for National Instruments PCI-6527");
476 MODULE_LICENSE("GPL");
477 

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