Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/staging/comedi/drivers/me_daq.c

  1 /*
  2  * comedi/drivers/me_daq.c
  3  * Hardware driver for Meilhaus data acquisition cards:
  4  *   ME-2000i, ME-2600i, ME-3000vm1
  5  *
  6  * Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  */
 18 
 19 /*
 20  * Driver: me_daq
 21  * Description: Meilhaus PCI data acquisition cards
 22  * Devices: (Meilhaus) ME-2600i [me-2600i]
 23  *          (Meilhaus) ME-2000i [me-2000i]
 24  * Author: Michael Hillmann <hillmann@syscongroup.de>
 25  * Status: experimental
 26  *
 27  * Configuration options: not applicable, uses PCI auto config
 28  *
 29  * Supports:
 30  *    Analog Input, Analog Output, Digital I/O
 31  */
 32 
 33 #include <linux/module.h>
 34 #include <linux/pci.h>
 35 #include <linux/interrupt.h>
 36 #include <linux/sched.h>
 37 
 38 #include "../comedidev.h"
 39 
 40 #include "plx9052.h"
 41 
 42 #define ME2600_FIRMWARE         "me2600_firmware.bin"
 43 
 44 #define XILINX_DOWNLOAD_RESET   0x42    /* Xilinx registers */
 45 
 46 #define ME_CONTROL_1                    0x0000  /* - | W */
 47 #define   INTERRUPT_ENABLE              (1<<15)
 48 #define   COUNTER_B_IRQ                 (1<<12)
 49 #define   COUNTER_A_IRQ                 (1<<11)
 50 #define   CHANLIST_READY_IRQ            (1<<10)
 51 #define   EXT_IRQ                       (1<<9)
 52 #define   ADFIFO_HALFFULL_IRQ           (1<<8)
 53 #define   SCAN_COUNT_ENABLE             (1<<5)
 54 #define   SIMULTANEOUS_ENABLE           (1<<4)
 55 #define   TRIGGER_FALLING_EDGE          (1<<3)
 56 #define   CONTINUOUS_MODE               (1<<2)
 57 #define   DISABLE_ADC                   (0<<0)
 58 #define   SOFTWARE_TRIGGERED_ADC        (1<<0)
 59 #define   SCAN_TRIGGERED_ADC            (2<<0)
 60 #define   EXT_TRIGGERED_ADC             (3<<0)
 61 #define ME_ADC_START                    0x0000  /* R | - */
 62 #define ME_CONTROL_2                    0x0002  /* - | W */
 63 #define   ENABLE_ADFIFO                 (1<<10)
 64 #define   ENABLE_CHANLIST               (1<<9)
 65 #define   ENABLE_PORT_B                 (1<<7)
 66 #define   ENABLE_PORT_A                 (1<<6)
 67 #define   ENABLE_COUNTER_B              (1<<4)
 68 #define   ENABLE_COUNTER_A              (1<<3)
 69 #define   ENABLE_DAC                    (1<<1)
 70 #define   BUFFERED_DAC                  (1<<0)
 71 #define ME_DAC_UPDATE                   0x0002  /* R | - */
 72 #define ME_STATUS                       0x0004  /* R | - */
 73 #define   COUNTER_B_IRQ_PENDING         (1<<12)
 74 #define   COUNTER_A_IRQ_PENDING         (1<<11)
 75 #define   CHANLIST_READY_IRQ_PENDING    (1<<10)
 76 #define   EXT_IRQ_PENDING               (1<<9)
 77 #define   ADFIFO_HALFFULL_IRQ_PENDING   (1<<8)
 78 #define   ADFIFO_FULL                   (1<<4)
 79 #define   ADFIFO_HALFFULL               (1<<3)
 80 #define   ADFIFO_EMPTY                  (1<<2)
 81 #define   CHANLIST_FULL                 (1<<1)
 82 #define   FST_ACTIVE                    (1<<0)
 83 #define ME_RESET_INTERRUPT              0x0004  /* - | W */
 84 #define ME_DIO_PORT_A                   0x0006  /* R | W */
 85 #define ME_DIO_PORT_B                   0x0008  /* R | W */
 86 #define ME_TIMER_DATA_0                 0x000A  /* - | W */
 87 #define ME_TIMER_DATA_1                 0x000C  /* - | W */
 88 #define ME_TIMER_DATA_2                 0x000E  /* - | W */
 89 #define ME_CHANNEL_LIST                 0x0010  /* - | W */
 90 #define   ADC_UNIPOLAR                  (1<<6)
 91 #define   ADC_GAIN_0                    (0<<4)
 92 #define   ADC_GAIN_1                    (1<<4)
 93 #define   ADC_GAIN_2                    (2<<4)
 94 #define   ADC_GAIN_3                    (3<<4)
 95 #define ME_READ_AD_FIFO                 0x0010  /* R | - */
 96 #define ME_DAC_CONTROL                  0x0012  /* - | W */
 97 #define   DAC_UNIPOLAR_D                (0<<4)
 98 #define   DAC_BIPOLAR_D                 (1<<4)
 99 #define   DAC_UNIPOLAR_C                (0<<5)
100 #define   DAC_BIPOLAR_C                 (1<<5)
101 #define   DAC_UNIPOLAR_B                (0<<6)
102 #define   DAC_BIPOLAR_B                 (1<<6)
103 #define   DAC_UNIPOLAR_A                (0<<7)
104 #define   DAC_BIPOLAR_A                 (1<<7)
105 #define   DAC_GAIN_0_D                  (0<<8)
106 #define   DAC_GAIN_1_D                  (1<<8)
107 #define   DAC_GAIN_0_C                  (0<<9)
108 #define   DAC_GAIN_1_C                  (1<<9)
109 #define   DAC_GAIN_0_B                  (0<<10)
110 #define   DAC_GAIN_1_B                  (1<<10)
111 #define   DAC_GAIN_0_A                  (0<<11)
112 #define   DAC_GAIN_1_A                  (1<<11)
113 #define ME_DAC_CONTROL_UPDATE           0x0012  /* R | - */
114 #define ME_DAC_DATA_A                   0x0014  /* - | W */
115 #define ME_DAC_DATA_B                   0x0016  /* - | W */
116 #define ME_DAC_DATA_C                   0x0018  /* - | W */
117 #define ME_DAC_DATA_D                   0x001A  /* - | W */
118 #define ME_COUNTER_ENDDATA_A            0x001C  /* - | W */
119 #define ME_COUNTER_ENDDATA_B            0x001E  /* - | W */
120 #define ME_COUNTER_STARTDATA_A          0x0020  /* - | W */
121 #define ME_COUNTER_VALUE_A              0x0020  /* R | - */
122 #define ME_COUNTER_STARTDATA_B          0x0022  /* - | W */
123 #define ME_COUNTER_VALUE_B              0x0022  /* R | - */
124 
125 static const struct comedi_lrange me_ai_range = {
126         8, {
127                 BIP_RANGE(10),
128                 BIP_RANGE(5),
129                 BIP_RANGE(2.5),
130                 BIP_RANGE(1.25),
131                 UNI_RANGE(10),
132                 UNI_RANGE(5),
133                 UNI_RANGE(2.5),
134                 UNI_RANGE(1.25)
135         }
136 };
137 
138 static const struct comedi_lrange me_ao_range = {
139         3, {
140                 BIP_RANGE(10),
141                 BIP_RANGE(5),
142                 UNI_RANGE(10)
143         }
144 };
145 
146 enum me_boardid {
147         BOARD_ME2600,
148         BOARD_ME2000,
149 };
150 
151 struct me_board {
152         const char *name;
153         int needs_firmware;
154         int has_ao;
155 };
156 
157 static const struct me_board me_boards[] = {
158         [BOARD_ME2600] = {
159                 .name           = "me-2600i",
160                 .needs_firmware = 1,
161                 .has_ao         = 1,
162         },
163         [BOARD_ME2000] = {
164                 .name           = "me-2000i",
165         },
166 };
167 
168 struct me_private_data {
169         void __iomem *plx_regbase;      /* PLX configuration base address */
170 
171         unsigned short control_1;       /* Mirror of CONTROL_1 register */
172         unsigned short control_2;       /* Mirror of CONTROL_2 register */
173         unsigned short dac_control;     /* Mirror of the DAC_CONTROL register */
174         int ao_readback[4];     /* Mirror of analog output data */
175 };
176 
177 static inline void sleep(unsigned sec)
178 {
179         current->state = TASK_INTERRUPTIBLE;
180         schedule_timeout(sec * HZ);
181 }
182 
183 static int me_dio_insn_config(struct comedi_device *dev,
184                               struct comedi_subdevice *s,
185                               struct comedi_insn *insn,
186                               unsigned int *data)
187 {
188         struct me_private_data *devpriv = dev->private;
189         unsigned int chan = CR_CHAN(insn->chanspec);
190         unsigned int mask;
191         int ret;
192 
193         if (chan < 16)
194                 mask = 0x0000ffff;
195         else
196                 mask = 0xffff0000;
197 
198         ret = comedi_dio_insn_config(dev, s, insn, data, mask);
199         if (ret)
200                 return ret;
201 
202         if (s->io_bits & 0x0000ffff)
203                 devpriv->control_2 |= ENABLE_PORT_A;
204         else
205                 devpriv->control_2 &= ~ENABLE_PORT_A;
206         if (s->io_bits & 0xffff0000)
207                 devpriv->control_2 |= ENABLE_PORT_B;
208         else
209                 devpriv->control_2 &= ~ENABLE_PORT_B;
210 
211         writew(devpriv->control_2, dev->mmio + ME_CONTROL_2);
212 
213         return insn->n;
214 }
215 
216 static int me_dio_insn_bits(struct comedi_device *dev,
217                             struct comedi_subdevice *s,
218                             struct comedi_insn *insn,
219                             unsigned int *data)
220 {
221         void __iomem *mmio_porta = dev->mmio + ME_DIO_PORT_A;
222         void __iomem *mmio_portb = dev->mmio + ME_DIO_PORT_B;
223         unsigned int mask;
224         unsigned int val;
225 
226         mask = comedi_dio_update_state(s, data);
227         if (mask) {
228                 if (mask & 0x0000ffff)
229                         writew((s->state & 0xffff), mmio_porta);
230                 if (mask & 0xffff0000)
231                         writew(((s->state >> 16) & 0xffff), mmio_portb);
232         }
233 
234         if (s->io_bits & 0x0000ffff)
235                 val = s->state & 0xffff;
236         else
237                 val = readw(mmio_porta);
238 
239         if (s->io_bits & 0xffff0000)
240                 val |= (s->state & 0xffff0000);
241         else
242                 val |= (readw(mmio_portb) << 16);
243 
244         data[1] = val;
245 
246         return insn->n;
247 }
248 
249 static int me_ai_eoc(struct comedi_device *dev,
250                      struct comedi_subdevice *s,
251                      struct comedi_insn *insn,
252                      unsigned long context)
253 {
254         unsigned int status;
255 
256         status = readw(dev->mmio + ME_STATUS);
257         if ((status & 0x0004) == 0)
258                 return 0;
259         return -EBUSY;
260 }
261 
262 static int me_ai_insn_read(struct comedi_device *dev,
263                            struct comedi_subdevice *s,
264                            struct comedi_insn *insn,
265                            unsigned int *data)
266 {
267         struct me_private_data *dev_private = dev->private;
268         unsigned int chan = CR_CHAN(insn->chanspec);
269         unsigned int rang = CR_RANGE(insn->chanspec);
270         unsigned int aref = CR_AREF(insn->chanspec);
271         unsigned short val;
272         int ret;
273 
274         /* stop any running conversion */
275         dev_private->control_1 &= 0xFFFC;
276         writew(dev_private->control_1, dev->mmio + ME_CONTROL_1);
277 
278         /* clear chanlist and ad fifo */
279         dev_private->control_2 &= ~(ENABLE_ADFIFO | ENABLE_CHANLIST);
280         writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
281 
282         /* reset any pending interrupt */
283         writew(0x00, dev->mmio + ME_RESET_INTERRUPT);
284 
285         /* enable the chanlist and ADC fifo */
286         dev_private->control_2 |= (ENABLE_ADFIFO | ENABLE_CHANLIST);
287         writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
288 
289         /* write to channel list fifo */
290         val = chan & 0x0f;                      /* b3:b0 channel */
291         val |= (rang & 0x03) << 4;              /* b5:b4 gain */
292         val |= (rang & 0x04) << 4;              /* b6 polarity */
293         val |= ((aref & AREF_DIFF) ? 0x80 : 0); /* b7 differential */
294         writew(val & 0xff, dev->mmio + ME_CHANNEL_LIST);
295 
296         /* set ADC mode to software trigger */
297         dev_private->control_1 |= SOFTWARE_TRIGGERED_ADC;
298         writew(dev_private->control_1, dev->mmio + ME_CONTROL_1);
299 
300         /* start conversion by reading from ADC_START */
301         readw(dev->mmio + ME_ADC_START);
302 
303         /* wait for ADC fifo not empty flag */
304         ret = comedi_timeout(dev, s, insn, me_ai_eoc, 0);
305         if (ret)
306                 return ret;
307 
308         /* get value from ADC fifo */
309         val = readw(dev->mmio + ME_READ_AD_FIFO);
310         val = (val ^ 0x800) & 0x0fff;
311         data[0] = val;
312 
313         /* stop any running conversion */
314         dev_private->control_1 &= 0xFFFC;
315         writew(dev_private->control_1, dev->mmio + ME_CONTROL_1);
316 
317         return 1;
318 }
319 
320 static int me_ao_insn_write(struct comedi_device *dev,
321                             struct comedi_subdevice *s,
322                             struct comedi_insn *insn,
323                             unsigned int *data)
324 {
325         struct me_private_data *dev_private = dev->private;
326         unsigned int chan = CR_CHAN(insn->chanspec);
327         unsigned int rang = CR_RANGE(insn->chanspec);
328         int i;
329 
330         /* Enable all DAC */
331         dev_private->control_2 |= ENABLE_DAC;
332         writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
333 
334         /* and set DAC to "buffered" mode */
335         dev_private->control_2 |= BUFFERED_DAC;
336         writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
337 
338         /* Set dac-control register */
339         for (i = 0; i < insn->n; i++) {
340                 /* clear bits for this channel */
341                 dev_private->dac_control &= ~(0x0880 >> chan);
342                 if (rang == 0)
343                         dev_private->dac_control |=
344                             ((DAC_BIPOLAR_A | DAC_GAIN_1_A) >> chan);
345                 else if (rang == 1)
346                         dev_private->dac_control |=
347                             ((DAC_BIPOLAR_A | DAC_GAIN_0_A) >> chan);
348         }
349         writew(dev_private->dac_control, dev->mmio + ME_DAC_CONTROL);
350 
351         /* Update dac-control register */
352         readw(dev->mmio + ME_DAC_CONTROL_UPDATE);
353 
354         /* Set data register */
355         for (i = 0; i < insn->n; i++) {
356                 writew((data[0] & s->maxdata),
357                        dev->mmio + ME_DAC_DATA_A + (chan << 1));
358                 dev_private->ao_readback[chan] = (data[0] & s->maxdata);
359         }
360 
361         /* Update dac with data registers */
362         readw(dev->mmio + ME_DAC_UPDATE);
363 
364         return insn->n;
365 }
366 
367 static int me_ao_insn_read(struct comedi_device *dev,
368                            struct comedi_subdevice *s,
369                            struct comedi_insn *insn,
370                            unsigned int *data)
371 {
372         struct me_private_data *dev_private = dev->private;
373         unsigned int chan = CR_CHAN(insn->chanspec);
374         int i;
375 
376         for (i = 0; i < insn->n; i++)
377                 data[i] = dev_private->ao_readback[chan];
378 
379         return insn->n;
380 }
381 
382 static int me2600_xilinx_download(struct comedi_device *dev,
383                                   const u8 *data, size_t size,
384                                   unsigned long context)
385 {
386         struct me_private_data *dev_private = dev->private;
387         unsigned int value;
388         unsigned int file_length;
389         unsigned int i;
390 
391         /* disable irq's on PLX */
392         writel(0x00, dev_private->plx_regbase + PLX9052_INTCSR);
393 
394         /* First, make a dummy read to reset xilinx */
395         value = readw(dev->mmio + XILINX_DOWNLOAD_RESET);
396 
397         /* Wait until reset is over */
398         sleep(1);
399 
400         /* Write a dummy value to Xilinx */
401         writeb(0x00, dev->mmio + 0x0);
402         sleep(1);
403 
404         /*
405          * Format of the firmware
406          * Build longs from the byte-wise coded header
407          * Byte 1-3:   length of the array
408          * Byte 4-7:   version
409          * Byte 8-11:  date
410          * Byte 12-15: reserved
411          */
412         if (size < 16)
413                 return -EINVAL;
414 
415         file_length = (((unsigned int)data[0] & 0xff) << 24) +
416             (((unsigned int)data[1] & 0xff) << 16) +
417             (((unsigned int)data[2] & 0xff) << 8) +
418             ((unsigned int)data[3] & 0xff);
419 
420         /*
421          * Loop for writing firmware byte by byte to xilinx
422          * Firmware data start at offset 16
423          */
424         for (i = 0; i < file_length; i++)
425                 writeb((data[16 + i] & 0xff), dev->mmio + 0x0);
426 
427         /* Write 5 dummy values to xilinx */
428         for (i = 0; i < 5; i++)
429                 writeb(0x00, dev->mmio + 0x0);
430 
431         /* Test if there was an error during download -> INTB was thrown */
432         value = readl(dev_private->plx_regbase + PLX9052_INTCSR);
433         if (value & PLX9052_INTCSR_LI2STAT) {
434                 /* Disable interrupt */
435                 writel(0x00, dev_private->plx_regbase + PLX9052_INTCSR);
436                 dev_err(dev->class_dev, "Xilinx download failed\n");
437                 return -EIO;
438         }
439 
440         /* Wait until the Xilinx is ready for real work */
441         sleep(1);
442 
443         /* Enable PLX-Interrupts */
444         writel(PLX9052_INTCSR_LI1ENAB |
445                PLX9052_INTCSR_LI1POL |
446                PLX9052_INTCSR_PCIENAB,
447                dev_private->plx_regbase + PLX9052_INTCSR);
448 
449         return 0;
450 }
451 
452 static int me_reset(struct comedi_device *dev)
453 {
454         struct me_private_data *dev_private = dev->private;
455 
456         /* Reset board */
457         writew(0x00, dev->mmio + ME_CONTROL_1);
458         writew(0x00, dev->mmio + ME_CONTROL_2);
459         writew(0x00, dev->mmio + ME_RESET_INTERRUPT);
460         writew(0x00, dev->mmio + ME_DAC_CONTROL);
461 
462         /* Save values in the board context */
463         dev_private->dac_control = 0;
464         dev_private->control_1 = 0;
465         dev_private->control_2 = 0;
466 
467         return 0;
468 }
469 
470 static int me_auto_attach(struct comedi_device *dev,
471                           unsigned long context)
472 {
473         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
474         const struct me_board *board = NULL;
475         struct me_private_data *dev_private;
476         struct comedi_subdevice *s;
477         int ret;
478 
479         if (context < ARRAY_SIZE(me_boards))
480                 board = &me_boards[context];
481         if (!board)
482                 return -ENODEV;
483         dev->board_ptr = board;
484         dev->board_name = board->name;
485 
486         dev_private = comedi_alloc_devpriv(dev, sizeof(*dev_private));
487         if (!dev_private)
488                 return -ENOMEM;
489 
490         ret = comedi_pci_enable(dev);
491         if (ret)
492                 return ret;
493 
494         dev_private->plx_regbase = pci_ioremap_bar(pcidev, 0);
495         if (!dev_private->plx_regbase)
496                 return -ENOMEM;
497 
498         dev->mmio = pci_ioremap_bar(pcidev, 2);
499         if (!dev->mmio)
500                 return -ENOMEM;
501 
502         /* Download firmware and reset card */
503         if (board->needs_firmware) {
504                 ret = comedi_load_firmware(dev, &comedi_to_pci_dev(dev)->dev,
505                                            ME2600_FIRMWARE,
506                                            me2600_xilinx_download, 0);
507                 if (ret < 0)
508                         return ret;
509         }
510         me_reset(dev);
511 
512         ret = comedi_alloc_subdevices(dev, 3);
513         if (ret)
514                 return ret;
515 
516         s = &dev->subdevices[0];
517         s->type         = COMEDI_SUBD_AI;
518         s->subdev_flags = SDF_READABLE | SDF_COMMON;
519         s->n_chan       = 16;
520         s->maxdata      = 0x0fff;
521         s->len_chanlist = 16;
522         s->range_table  = &me_ai_range;
523         s->insn_read    = me_ai_insn_read;
524 
525         s = &dev->subdevices[1];
526         if (board->has_ao) {
527                 s->type         = COMEDI_SUBD_AO;
528                 s->subdev_flags = SDF_WRITEABLE | SDF_COMMON;
529                 s->n_chan       = 4;
530                 s->maxdata      = 0x0fff;
531                 s->len_chanlist = 4;
532                 s->range_table  = &me_ao_range;
533                 s->insn_read    = me_ao_insn_read;
534                 s->insn_write   = me_ao_insn_write;
535         } else {
536                 s->type = COMEDI_SUBD_UNUSED;
537         }
538 
539         s = &dev->subdevices[2];
540         s->type         = COMEDI_SUBD_DIO;
541         s->subdev_flags = SDF_READABLE | SDF_WRITEABLE;
542         s->n_chan       = 32;
543         s->maxdata      = 1;
544         s->len_chanlist = 32;
545         s->range_table  = &range_digital;
546         s->insn_bits    = me_dio_insn_bits;
547         s->insn_config  = me_dio_insn_config;
548 
549         return 0;
550 }
551 
552 static void me_detach(struct comedi_device *dev)
553 {
554         struct me_private_data *dev_private = dev->private;
555 
556         if (dev_private) {
557                 if (dev->mmio) {
558                         me_reset(dev);
559                         iounmap(dev->mmio);
560                 }
561                 if (dev_private->plx_regbase)
562                         iounmap(dev_private->plx_regbase);
563         }
564         comedi_pci_disable(dev);
565 }
566 
567 static struct comedi_driver me_daq_driver = {
568         .driver_name    = "me_daq",
569         .module         = THIS_MODULE,
570         .auto_attach    = me_auto_attach,
571         .detach         = me_detach,
572 };
573 
574 static int me_daq_pci_probe(struct pci_dev *dev,
575                             const struct pci_device_id *id)
576 {
577         return comedi_pci_auto_config(dev, &me_daq_driver, id->driver_data);
578 }
579 
580 static const struct pci_device_id me_daq_pci_table[] = {
581         { PCI_VDEVICE(MEILHAUS, 0x2600), BOARD_ME2600 },
582         { PCI_VDEVICE(MEILHAUS, 0x2000), BOARD_ME2000 },
583         { 0 }
584 };
585 MODULE_DEVICE_TABLE(pci, me_daq_pci_table);
586 
587 static struct pci_driver me_daq_pci_driver = {
588         .name           = "me_daq",
589         .id_table       = me_daq_pci_table,
590         .probe          = me_daq_pci_probe,
591         .remove         = comedi_pci_auto_unconfig,
592 };
593 module_comedi_pci_driver(me_daq_driver, me_daq_pci_driver);
594 
595 MODULE_AUTHOR("Comedi http://www.comedi.org");
596 MODULE_DESCRIPTION("Comedi low-level driver");
597 MODULE_LICENSE("GPL");
598 MODULE_FIRMWARE(ME2600_FIRMWARE);
599 

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