Version:  2.0.40 2.2.26 2.4.37 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7

Linux/drivers/staging/comedi/drivers/me_daq.c

  1 /*
  2  * comedi/drivers/me_daq.c
  3  * Hardware driver for Meilhaus data acquisition cards:
  4  *   ME-2000i, ME-2600i, ME-3000vm1
  5  *
  6  * Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  */
 18 
 19 /*
 20  * Driver: me_daq
 21  * Description: Meilhaus PCI data acquisition cards
 22  * Devices: [Meilhaus] ME-2600i (me-2600i), ME-2000i (me-2000i)
 23  * Author: Michael Hillmann <hillmann@syscongroup.de>
 24  * Status: experimental
 25  *
 26  * Configuration options: not applicable, uses PCI auto config
 27  *
 28  * Supports:
 29  *    Analog Input, Analog Output, Digital I/O
 30  */
 31 
 32 #include <linux/module.h>
 33 #include <linux/interrupt.h>
 34 #include <linux/sched.h>
 35 
 36 #include "../comedi_pci.h"
 37 
 38 #include "plx9052.h"
 39 
 40 #define ME2600_FIRMWARE         "me2600_firmware.bin"
 41 
 42 #define XILINX_DOWNLOAD_RESET   0x42    /* Xilinx registers */
 43 
 44 /*
 45  * PCI BAR2 Memory map (dev->mmio)
 46  */
 47 #define ME_CTRL1_REG                    0x00    /* R (ai start) | W */
 48 #define   ME_CTRL1_INT_ENA              BIT(15)
 49 #define   ME_CTRL1_COUNTER_B_IRQ        BIT(12)
 50 #define   ME_CTRL1_COUNTER_A_IRQ        BIT(11)
 51 #define   ME_CTRL1_CHANLIST_READY_IRQ   BIT(10)
 52 #define   ME_CTRL1_EXT_IRQ              BIT(9)
 53 #define   ME_CTRL1_ADFIFO_HALFFULL_IRQ  BIT(8)
 54 #define   ME_CTRL1_SCAN_COUNT_ENA       BIT(5)
 55 #define   ME_CTRL1_SIMULTANEOUS_ENA     BIT(4)
 56 #define   ME_CTRL1_TRIGGER_FALLING_EDGE BIT(3)
 57 #define   ME_CTRL1_CONTINUOUS_MODE      BIT(2)
 58 #define   ME_CTRL1_ADC_MODE(x)          (((x) & 0x3) << 0)
 59 #define   ME_CTRL1_ADC_MODE_DISABLE     ME_CTRL1_ADC_MODE(0)
 60 #define   ME_CTRL1_ADC_MODE_SOFT_TRIG   ME_CTRL1_ADC_MODE(1)
 61 #define   ME_CTRL1_ADC_MODE_SCAN_TRIG   ME_CTRL1_ADC_MODE(2)
 62 #define   ME_CTRL1_ADC_MODE_EXT_TRIG    ME_CTRL1_ADC_MODE(3)
 63 #define   ME_CTRL1_ADC_MODE_MASK        ME_CTRL1_ADC_MODE(3)
 64 #define ME_CTRL2_REG                    0x02    /* R (dac update) | W */
 65 #define   ME_CTRL2_ADFIFO_ENA           BIT(10)
 66 #define   ME_CTRL2_CHANLIST_ENA         BIT(9)
 67 #define   ME_CTRL2_PORT_B_ENA           BIT(7)
 68 #define   ME_CTRL2_PORT_A_ENA           BIT(6)
 69 #define   ME_CTRL2_COUNTER_B_ENA        BIT(4)
 70 #define   ME_CTRL2_COUNTER_A_ENA        BIT(3)
 71 #define   ME_CTRL2_DAC_ENA              BIT(1)
 72 #define   ME_CTRL2_BUFFERED_DAC         BIT(0)
 73 #define ME_STATUS_REG                   0x04    /* R | W (clears interrupts) */
 74 #define   ME_STATUS_COUNTER_B_IRQ       BIT(12)
 75 #define   ME_STATUS_COUNTER_A_IRQ       BIT(11)
 76 #define   ME_STATUS_CHANLIST_READY_IRQ  BIT(10)
 77 #define   ME_STATUS_EXT_IRQ             BIT(9)
 78 #define   ME_STATUS_ADFIFO_HALFFULL_IRQ BIT(8)
 79 #define   ME_STATUS_ADFIFO_FULL         BIT(4)
 80 #define   ME_STATUS_ADFIFO_HALFFULL     BIT(3)
 81 #define   ME_STATUS_ADFIFO_EMPTY        BIT(2)
 82 #define   ME_STATUS_CHANLIST_FULL       BIT(1)
 83 #define   ME_STATUS_FST_ACTIVE          BIT(0)
 84 #define ME_DIO_PORT_A_REG               0x06    /* R | W */
 85 #define ME_DIO_PORT_B_REG               0x08    /* R | W */
 86 #define ME_TIMER_DATA_REG(x)            (0x0a + ((x) * 2))      /* - | W */
 87 #define ME_AI_FIFO_REG                  0x10    /* R (fifo) | W (chanlist) */
 88 #define   ME_AI_FIFO_CHANLIST_DIFF      BIT(7)
 89 #define   ME_AI_FIFO_CHANLIST_UNIPOLAR  BIT(6)
 90 #define   ME_AI_FIFO_CHANLIST_GAIN(x)   (((x) & 0x3) << 4)
 91 #define   ME_AI_FIFO_CHANLIST_CHAN(x)   (((x) & 0xf) << 0)
 92 #define ME_DAC_CTRL_REG                 0x12    /* R (updates) | W */
 93 #define   ME_DAC_CTRL_BIPOLAR(x)        BIT(7 - ((x) & 0x3))
 94 #define   ME_DAC_CTRL_GAIN(x)           BIT(11 - ((x) & 0x3))
 95 #define   ME_DAC_CTRL_MASK(x)           (ME_DAC_CTRL_BIPOLAR(x) |       \
 96                                          ME_DAC_CTRL_GAIN(x))
 97 #define ME_AO_DATA_REG(x)               (0x14 + ((x) * 2))      /* - | W */
 98 #define ME_COUNTER_ENDDATA_REG(x)       (0x1c + ((x) * 2))      /* - | W */
 99 #define ME_COUNTER_STARTDATA_REG(x)     (0x20 + ((x) * 2))      /* - | W */
100 #define ME_COUNTER_VALUE_REG(x)         (0x20 + ((x) * 2))      /* R | - */
101 
102 static const struct comedi_lrange me_ai_range = {
103         8, {
104                 BIP_RANGE(10),
105                 BIP_RANGE(5),
106                 BIP_RANGE(2.5),
107                 BIP_RANGE(1.25),
108                 UNI_RANGE(10),
109                 UNI_RANGE(5),
110                 UNI_RANGE(2.5),
111                 UNI_RANGE(1.25)
112         }
113 };
114 
115 static const struct comedi_lrange me_ao_range = {
116         3, {
117                 BIP_RANGE(10),
118                 BIP_RANGE(5),
119                 UNI_RANGE(10)
120         }
121 };
122 
123 enum me_boardid {
124         BOARD_ME2600,
125         BOARD_ME2000,
126 };
127 
128 struct me_board {
129         const char *name;
130         int needs_firmware;
131         int has_ao;
132 };
133 
134 static const struct me_board me_boards[] = {
135         [BOARD_ME2600] = {
136                 .name           = "me-2600i",
137                 .needs_firmware = 1,
138                 .has_ao         = 1,
139         },
140         [BOARD_ME2000] = {
141                 .name           = "me-2000i",
142         },
143 };
144 
145 struct me_private_data {
146         void __iomem *plx_regbase;      /* PLX configuration base address */
147 
148         unsigned short ctrl1;           /* Mirror of CONTROL_1 register */
149         unsigned short ctrl2;           /* Mirror of CONTROL_2 register */
150         unsigned short dac_ctrl;        /* Mirror of the DAC_CONTROL register */
151 };
152 
153 static inline void sleep(unsigned sec)
154 {
155         schedule_timeout_interruptible(sec * HZ);
156 }
157 
158 static int me_dio_insn_config(struct comedi_device *dev,
159                               struct comedi_subdevice *s,
160                               struct comedi_insn *insn,
161                               unsigned int *data)
162 {
163         struct me_private_data *devpriv = dev->private;
164         unsigned int chan = CR_CHAN(insn->chanspec);
165         unsigned int mask;
166         int ret;
167 
168         if (chan < 16)
169                 mask = 0x0000ffff;
170         else
171                 mask = 0xffff0000;
172 
173         ret = comedi_dio_insn_config(dev, s, insn, data, mask);
174         if (ret)
175                 return ret;
176 
177         if (s->io_bits & 0x0000ffff)
178                 devpriv->ctrl2 |= ME_CTRL2_PORT_A_ENA;
179         else
180                 devpriv->ctrl2 &= ~ME_CTRL2_PORT_A_ENA;
181         if (s->io_bits & 0xffff0000)
182                 devpriv->ctrl2 |= ME_CTRL2_PORT_B_ENA;
183         else
184                 devpriv->ctrl2 &= ~ME_CTRL2_PORT_B_ENA;
185 
186         writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
187 
188         return insn->n;
189 }
190 
191 static int me_dio_insn_bits(struct comedi_device *dev,
192                             struct comedi_subdevice *s,
193                             struct comedi_insn *insn,
194                             unsigned int *data)
195 {
196         void __iomem *mmio_porta = dev->mmio + ME_DIO_PORT_A_REG;
197         void __iomem *mmio_portb = dev->mmio + ME_DIO_PORT_B_REG;
198         unsigned int mask;
199         unsigned int val;
200 
201         mask = comedi_dio_update_state(s, data);
202         if (mask) {
203                 if (mask & 0x0000ffff)
204                         writew((s->state & 0xffff), mmio_porta);
205                 if (mask & 0xffff0000)
206                         writew(((s->state >> 16) & 0xffff), mmio_portb);
207         }
208 
209         if (s->io_bits & 0x0000ffff)
210                 val = s->state & 0xffff;
211         else
212                 val = readw(mmio_porta);
213 
214         if (s->io_bits & 0xffff0000)
215                 val |= (s->state & 0xffff0000);
216         else
217                 val |= (readw(mmio_portb) << 16);
218 
219         data[1] = val;
220 
221         return insn->n;
222 }
223 
224 static int me_ai_eoc(struct comedi_device *dev,
225                      struct comedi_subdevice *s,
226                      struct comedi_insn *insn,
227                      unsigned long context)
228 {
229         unsigned int status;
230 
231         status = readw(dev->mmio + ME_STATUS_REG);
232         if ((status & ME_STATUS_ADFIFO_EMPTY) == 0)
233                 return 0;
234         return -EBUSY;
235 }
236 
237 static int me_ai_insn_read(struct comedi_device *dev,
238                            struct comedi_subdevice *s,
239                            struct comedi_insn *insn,
240                            unsigned int *data)
241 {
242         struct me_private_data *devpriv = dev->private;
243         unsigned int chan = CR_CHAN(insn->chanspec);
244         unsigned int range = CR_RANGE(insn->chanspec);
245         unsigned int aref = CR_AREF(insn->chanspec);
246         unsigned int val;
247         int ret = 0;
248         int i;
249 
250         /*
251          * For differential operation, there are only 8 input channels
252          * and only bipolar ranges are available.
253          */
254         if (aref & AREF_DIFF) {
255                 if (chan > 7 || comedi_range_is_unipolar(s, range))
256                         return -EINVAL;
257         }
258 
259         /* clear chanlist and ad fifo */
260         devpriv->ctrl2 &= ~(ME_CTRL2_ADFIFO_ENA | ME_CTRL2_CHANLIST_ENA);
261         writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
262 
263         writew(0x00, dev->mmio + ME_STATUS_REG);        /* clear interrupts */
264 
265         /* enable the chanlist and ADC fifo */
266         devpriv->ctrl2 |= (ME_CTRL2_ADFIFO_ENA | ME_CTRL2_CHANLIST_ENA);
267         writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
268 
269         /* write to channel list fifo */
270         val = ME_AI_FIFO_CHANLIST_CHAN(chan) | ME_AI_FIFO_CHANLIST_GAIN(range);
271         if (comedi_range_is_unipolar(s, range))
272                 val |= ME_AI_FIFO_CHANLIST_UNIPOLAR;
273         if (aref & AREF_DIFF)
274                 val |= ME_AI_FIFO_CHANLIST_DIFF;
275         writew(val, dev->mmio + ME_AI_FIFO_REG);
276 
277         /* set ADC mode to software trigger */
278         devpriv->ctrl1 |= ME_CTRL1_ADC_MODE_SOFT_TRIG;
279         writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG);
280 
281         for (i = 0; i < insn->n; i++) {
282                 /* start ai conversion */
283                 readw(dev->mmio + ME_CTRL1_REG);
284 
285                 /* wait for ADC fifo not empty flag */
286                 ret = comedi_timeout(dev, s, insn, me_ai_eoc, 0);
287                 if (ret)
288                         break;
289 
290                 /* get value from ADC fifo */
291                 val = readw(dev->mmio + ME_AI_FIFO_REG) & s->maxdata;
292 
293                 /* munge 2's complement value to offset binary */
294                 data[i] = comedi_offset_munge(s, val);
295         }
296 
297         /* stop any running conversion */
298         devpriv->ctrl1 &= ~ME_CTRL1_ADC_MODE_MASK;
299         writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG);
300 
301         return ret ? ret : insn->n;
302 }
303 
304 static int me_ao_insn_write(struct comedi_device *dev,
305                             struct comedi_subdevice *s,
306                             struct comedi_insn *insn,
307                             unsigned int *data)
308 {
309         struct me_private_data *devpriv = dev->private;
310         unsigned int chan = CR_CHAN(insn->chanspec);
311         unsigned int range = CR_RANGE(insn->chanspec);
312         unsigned int val = s->readback[chan];
313         int i;
314 
315         /* Enable all DAC */
316         devpriv->ctrl2 |= ME_CTRL2_DAC_ENA;
317         writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
318 
319         /* and set DAC to "buffered" mode */
320         devpriv->ctrl2 |= ME_CTRL2_BUFFERED_DAC;
321         writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
322 
323         /* Set dac-control register */
324         devpriv->dac_ctrl &= ~ME_DAC_CTRL_MASK(chan);
325         if (range == 0)
326                 devpriv->dac_ctrl |= ME_DAC_CTRL_GAIN(chan);
327         if (comedi_range_is_bipolar(s, range))
328                 devpriv->dac_ctrl |= ME_DAC_CTRL_BIPOLAR(chan);
329         writew(devpriv->dac_ctrl, dev->mmio + ME_DAC_CTRL_REG);
330 
331         /* Update dac-control register */
332         readw(dev->mmio + ME_DAC_CTRL_REG);
333 
334         /* Set data register */
335         for (i = 0; i < insn->n; i++) {
336                 val = data[i];
337 
338                 writew(val, dev->mmio + ME_AO_DATA_REG(chan));
339         }
340         s->readback[chan] = val;
341 
342         /* Update dac with data registers */
343         readw(dev->mmio + ME_CTRL2_REG);
344 
345         return insn->n;
346 }
347 
348 static int me2600_xilinx_download(struct comedi_device *dev,
349                                   const u8 *data, size_t size,
350                                   unsigned long context)
351 {
352         struct me_private_data *devpriv = dev->private;
353         unsigned int value;
354         unsigned int file_length;
355         unsigned int i;
356 
357         /* disable irq's on PLX */
358         writel(0x00, devpriv->plx_regbase + PLX9052_INTCSR);
359 
360         /* First, make a dummy read to reset xilinx */
361         value = readw(dev->mmio + XILINX_DOWNLOAD_RESET);
362 
363         /* Wait until reset is over */
364         sleep(1);
365 
366         /* Write a dummy value to Xilinx */
367         writeb(0x00, dev->mmio + 0x0);
368         sleep(1);
369 
370         /*
371          * Format of the firmware
372          * Build longs from the byte-wise coded header
373          * Byte 1-3:   length of the array
374          * Byte 4-7:   version
375          * Byte 8-11:  date
376          * Byte 12-15: reserved
377          */
378         if (size < 16)
379                 return -EINVAL;
380 
381         file_length = (((unsigned int)data[0] & 0xff) << 24) +
382             (((unsigned int)data[1] & 0xff) << 16) +
383             (((unsigned int)data[2] & 0xff) << 8) +
384             ((unsigned int)data[3] & 0xff);
385 
386         /*
387          * Loop for writing firmware byte by byte to xilinx
388          * Firmware data start at offset 16
389          */
390         for (i = 0; i < file_length; i++)
391                 writeb((data[16 + i] & 0xff), dev->mmio + 0x0);
392 
393         /* Write 5 dummy values to xilinx */
394         for (i = 0; i < 5; i++)
395                 writeb(0x00, dev->mmio + 0x0);
396 
397         /* Test if there was an error during download -> INTB was thrown */
398         value = readl(devpriv->plx_regbase + PLX9052_INTCSR);
399         if (value & PLX9052_INTCSR_LI2STAT) {
400                 /* Disable interrupt */
401                 writel(0x00, devpriv->plx_regbase + PLX9052_INTCSR);
402                 dev_err(dev->class_dev, "Xilinx download failed\n");
403                 return -EIO;
404         }
405 
406         /* Wait until the Xilinx is ready for real work */
407         sleep(1);
408 
409         /* Enable PLX-Interrupts */
410         writel(PLX9052_INTCSR_LI1ENAB |
411                PLX9052_INTCSR_LI1POL |
412                PLX9052_INTCSR_PCIENAB,
413                devpriv->plx_regbase + PLX9052_INTCSR);
414 
415         return 0;
416 }
417 
418 static int me_reset(struct comedi_device *dev)
419 {
420         struct me_private_data *devpriv = dev->private;
421 
422         /* Reset board */
423         writew(0x00, dev->mmio + ME_CTRL1_REG);
424         writew(0x00, dev->mmio + ME_CTRL2_REG);
425         writew(0x00, dev->mmio + ME_STATUS_REG);        /* clear interrupts */
426         writew(0x00, dev->mmio + ME_DAC_CTRL_REG);
427 
428         /* Save values in the board context */
429         devpriv->dac_ctrl = 0;
430         devpriv->ctrl1 = 0;
431         devpriv->ctrl2 = 0;
432 
433         return 0;
434 }
435 
436 static int me_auto_attach(struct comedi_device *dev,
437                           unsigned long context)
438 {
439         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
440         const struct me_board *board = NULL;
441         struct me_private_data *devpriv;
442         struct comedi_subdevice *s;
443         int ret;
444 
445         if (context < ARRAY_SIZE(me_boards))
446                 board = &me_boards[context];
447         if (!board)
448                 return -ENODEV;
449         dev->board_ptr = board;
450         dev->board_name = board->name;
451 
452         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
453         if (!devpriv)
454                 return -ENOMEM;
455 
456         ret = comedi_pci_enable(dev);
457         if (ret)
458                 return ret;
459 
460         devpriv->plx_regbase = pci_ioremap_bar(pcidev, 0);
461         if (!devpriv->plx_regbase)
462                 return -ENOMEM;
463 
464         dev->mmio = pci_ioremap_bar(pcidev, 2);
465         if (!dev->mmio)
466                 return -ENOMEM;
467 
468         /* Download firmware and reset card */
469         if (board->needs_firmware) {
470                 ret = comedi_load_firmware(dev, &comedi_to_pci_dev(dev)->dev,
471                                            ME2600_FIRMWARE,
472                                            me2600_xilinx_download, 0);
473                 if (ret < 0)
474                         return ret;
475         }
476         me_reset(dev);
477 
478         ret = comedi_alloc_subdevices(dev, 3);
479         if (ret)
480                 return ret;
481 
482         s = &dev->subdevices[0];
483         s->type         = COMEDI_SUBD_AI;
484         s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_DIFF;
485         s->n_chan       = 16;
486         s->maxdata      = 0x0fff;
487         s->len_chanlist = 16;
488         s->range_table  = &me_ai_range;
489         s->insn_read    = me_ai_insn_read;
490 
491         s = &dev->subdevices[1];
492         if (board->has_ao) {
493                 s->type         = COMEDI_SUBD_AO;
494                 s->subdev_flags = SDF_WRITABLE | SDF_COMMON;
495                 s->n_chan       = 4;
496                 s->maxdata      = 0x0fff;
497                 s->len_chanlist = 4;
498                 s->range_table  = &me_ao_range;
499                 s->insn_write   = me_ao_insn_write;
500 
501                 ret = comedi_alloc_subdev_readback(s);
502                 if (ret)
503                         return ret;
504         } else {
505                 s->type = COMEDI_SUBD_UNUSED;
506         }
507 
508         s = &dev->subdevices[2];
509         s->type         = COMEDI_SUBD_DIO;
510         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
511         s->n_chan       = 32;
512         s->maxdata      = 1;
513         s->len_chanlist = 32;
514         s->range_table  = &range_digital;
515         s->insn_bits    = me_dio_insn_bits;
516         s->insn_config  = me_dio_insn_config;
517 
518         return 0;
519 }
520 
521 static void me_detach(struct comedi_device *dev)
522 {
523         struct me_private_data *devpriv = dev->private;
524 
525         if (devpriv) {
526                 if (dev->mmio)
527                         me_reset(dev);
528                 if (devpriv->plx_regbase)
529                         iounmap(devpriv->plx_regbase);
530         }
531         comedi_pci_detach(dev);
532 }
533 
534 static struct comedi_driver me_daq_driver = {
535         .driver_name    = "me_daq",
536         .module         = THIS_MODULE,
537         .auto_attach    = me_auto_attach,
538         .detach         = me_detach,
539 };
540 
541 static int me_daq_pci_probe(struct pci_dev *dev,
542                             const struct pci_device_id *id)
543 {
544         return comedi_pci_auto_config(dev, &me_daq_driver, id->driver_data);
545 }
546 
547 static const struct pci_device_id me_daq_pci_table[] = {
548         { PCI_VDEVICE(MEILHAUS, 0x2600), BOARD_ME2600 },
549         { PCI_VDEVICE(MEILHAUS, 0x2000), BOARD_ME2000 },
550         { 0 }
551 };
552 MODULE_DEVICE_TABLE(pci, me_daq_pci_table);
553 
554 static struct pci_driver me_daq_pci_driver = {
555         .name           = "me_daq",
556         .id_table       = me_daq_pci_table,
557         .probe          = me_daq_pci_probe,
558         .remove         = comedi_pci_auto_unconfig,
559 };
560 module_comedi_pci_driver(me_daq_driver, me_daq_pci_driver);
561 
562 MODULE_AUTHOR("Comedi http://www.comedi.org");
563 MODULE_DESCRIPTION("Comedi low-level driver");
564 MODULE_LICENSE("GPL");
565 MODULE_FIRMWARE(ME2600_FIRMWARE);
566 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us