Version:  2.0.40 2.2.26 2.4.37 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1

Linux/drivers/staging/comedi/drivers/gsc_hpdi.c

  1 /*
  2  * gsc_hpdi.c
  3  * Comedi driver the General Standards Corporation
  4  * High Speed Parallel Digital Interface rs485 boards.
  5  *
  6  * Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
  7  * Copyright (C) 2003 Coherent Imaging Systems
  8  *
  9  * COMEDI - Linux Control and Measurement Device Interface
 10  * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
 11  *
 12  * This program is free software; you can redistribute it and/or modify
 13  * it under the terms of the GNU General Public License as published by
 14  * the Free Software Foundation; either version 2 of the License, or
 15  * (at your option) any later version.
 16  *
 17  * This program is distributed in the hope that it will be useful,
 18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 20  * GNU General Public License for more details.
 21  */
 22 
 23 /*
 24  * Driver: gsc_hpdi
 25  * Description: General Standards Corporation High
 26  *    Speed Parallel Digital Interface rs485 boards
 27  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
 28  * Status: only receive mode works, transmit not supported
 29  * Updated: Thu, 01 Nov 2012 16:17:38 +0000
 30  * Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
 31  *   PMC-HPDI32
 32  *
 33  * Configuration options:
 34  *    None.
 35  *
 36  * Manual configuration of supported devices is not supported; they are
 37  * configured automatically.
 38  *
 39  * There are some additional hpdi models available from GSC for which
 40  * support could be added to this driver.
 41  */
 42 
 43 #include <linux/module.h>
 44 #include <linux/delay.h>
 45 #include <linux/interrupt.h>
 46 
 47 #include "../comedi_pci.h"
 48 
 49 #include "plx9080.h"
 50 
 51 /*
 52  * PCI BAR2 Register map (dev->mmio)
 53  */
 54 #define FIRMWARE_REV_REG                        0x00
 55 #define FEATURES_REG_PRESENT_BIT                (1 << 15)
 56 #define BOARD_CONTROL_REG                       0x04
 57 #define BOARD_RESET_BIT                         (1 << 0)
 58 #define TX_FIFO_RESET_BIT                       (1 << 1)
 59 #define RX_FIFO_RESET_BIT                       (1 << 2)
 60 #define TX_ENABLE_BIT                           (1 << 4)
 61 #define RX_ENABLE_BIT                           (1 << 5)
 62 #define DEMAND_DMA_DIRECTION_TX_BIT             (1 << 6)  /* ch 0 only */
 63 #define LINE_VALID_ON_STATUS_VALID_BIT          (1 << 7)
 64 #define START_TX_BIT                            (1 << 8)
 65 #define CABLE_THROTTLE_ENABLE_BIT               (1 << 9)
 66 #define TEST_MODE_ENABLE_BIT                    (1 << 31)
 67 #define BOARD_STATUS_REG                        0x08
 68 #define COMMAND_LINE_STATUS_MASK                (0x7f << 0)
 69 #define TX_IN_PROGRESS_BIT                      (1 << 7)
 70 #define TX_NOT_EMPTY_BIT                        (1 << 8)
 71 #define TX_NOT_ALMOST_EMPTY_BIT                 (1 << 9)
 72 #define TX_NOT_ALMOST_FULL_BIT                  (1 << 10)
 73 #define TX_NOT_FULL_BIT                         (1 << 11)
 74 #define RX_NOT_EMPTY_BIT                        (1 << 12)
 75 #define RX_NOT_ALMOST_EMPTY_BIT                 (1 << 13)
 76 #define RX_NOT_ALMOST_FULL_BIT                  (1 << 14)
 77 #define RX_NOT_FULL_BIT                         (1 << 15)
 78 #define BOARD_JUMPER0_INSTALLED_BIT             (1 << 16)
 79 #define BOARD_JUMPER1_INSTALLED_BIT             (1 << 17)
 80 #define TX_OVERRUN_BIT                          (1 << 21)
 81 #define RX_UNDERRUN_BIT                         (1 << 22)
 82 #define RX_OVERRUN_BIT                          (1 << 23)
 83 #define TX_PROG_ALMOST_REG                      0x0c
 84 #define RX_PROG_ALMOST_REG                      0x10
 85 #define ALMOST_EMPTY_BITS(x)                    (((x) & 0xffff) << 0)
 86 #define ALMOST_FULL_BITS(x)                     (((x) & 0xff) << 16)
 87 #define FEATURES_REG                            0x14
 88 #define FIFO_SIZE_PRESENT_BIT                   (1 << 0)
 89 #define FIFO_WORDS_PRESENT_BIT                  (1 << 1)
 90 #define LEVEL_EDGE_INTERRUPTS_PRESENT_BIT       (1 << 2)
 91 #define GPIO_SUPPORTED_BIT                      (1 << 3)
 92 #define PLX_DMA_CH1_SUPPORTED_BIT               (1 << 4)
 93 #define OVERRUN_UNDERRUN_SUPPORTED_BIT          (1 << 5)
 94 #define FIFO_REG                                0x18
 95 #define TX_STATUS_COUNT_REG                     0x1c
 96 #define TX_LINE_VALID_COUNT_REG                 0x20,
 97 #define TX_LINE_INVALID_COUNT_REG               0x24
 98 #define RX_STATUS_COUNT_REG                     0x28
 99 #define RX_LINE_COUNT_REG                       0x2c
100 #define INTERRUPT_CONTROL_REG                   0x30
101 #define FRAME_VALID_START_INTR                  (1 << 0)
102 #define FRAME_VALID_END_INTR                    (1 << 1)
103 #define TX_FIFO_EMPTY_INTR                      (1 << 8)
104 #define TX_FIFO_ALMOST_EMPTY_INTR               (1 << 9)
105 #define TX_FIFO_ALMOST_FULL_INTR                (1 << 10)
106 #define TX_FIFO_FULL_INTR                       (1 << 11)
107 #define RX_EMPTY_INTR                           (1 << 12)
108 #define RX_ALMOST_EMPTY_INTR                    (1 << 13)
109 #define RX_ALMOST_FULL_INTR                     (1 << 14)
110 #define RX_FULL_INTR                            (1 << 15)
111 #define INTERRUPT_STATUS_REG                    0x34
112 #define TX_CLOCK_DIVIDER_REG                    0x38
113 #define TX_FIFO_SIZE_REG                        0x40
114 #define RX_FIFO_SIZE_REG                        0x44
115 #define FIFO_SIZE_MASK                          (0xfffff << 0)
116 #define TX_FIFO_WORDS_REG                       0x48
117 #define RX_FIFO_WORDS_REG                       0x4c
118 #define INTERRUPT_EDGE_LEVEL_REG                0x50
119 #define INTERRUPT_POLARITY_REG                  0x54
120 
121 #define TIMER_BASE                              50      /* 20MHz master clock */
122 #define DMA_BUFFER_SIZE                         0x10000
123 #define NUM_DMA_BUFFERS                         4
124 #define NUM_DMA_DESCRIPTORS                     256
125 
126 struct hpdi_board {
127         const char *name;
128         int device_id;
129         int subdevice_id;
130 };
131 
132 static const struct hpdi_board hpdi_boards[] = {
133         {
134                 .name           = "pci-hpdi32",
135                 .device_id      = PCI_DEVICE_ID_PLX_9080,
136                 .subdevice_id   = 0x2400,
137          },
138 #if 0
139         {
140                 .name           = "pxi-hpdi32",
141                 .device_id      = 0x9656,
142                 .subdevice_id   = 0x2705,
143          },
144 #endif
145 };
146 
147 struct hpdi_private {
148         void __iomem *plx9080_mmio;
149         uint32_t *dio_buffer[NUM_DMA_BUFFERS];  /*  dma buffers */
150         /* physical addresses of dma buffers */
151         dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
152         /* array of dma descriptors read by plx9080, allocated to get proper
153          * alignment */
154         struct plx_dma_desc *dma_desc;
155         /* physical address of dma descriptor array */
156         dma_addr_t dma_desc_phys_addr;
157         unsigned int num_dma_descriptors;
158         /* pointer to start of buffers indexed by descriptor */
159         uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
160         /* index of the dma descriptor that is currently being used */
161         unsigned int dma_desc_index;
162         unsigned int tx_fifo_size;
163         unsigned int rx_fifo_size;
164         unsigned long dio_count;
165         /* number of bytes at which to generate COMEDI_CB_BLOCK events */
166         unsigned int block_size;
167 };
168 
169 static void gsc_hpdi_drain_dma(struct comedi_device *dev, unsigned int channel)
170 {
171         struct hpdi_private *devpriv = dev->private;
172         struct comedi_subdevice *s = dev->read_subdev;
173         struct comedi_cmd *cmd = &s->async->cmd;
174         unsigned int idx;
175         unsigned int start;
176         unsigned int desc;
177         unsigned int size;
178         unsigned int next;
179 
180         if (channel)
181                 next = readl(devpriv->plx9080_mmio + PLX_DMA1_PCI_ADDRESS_REG);
182         else
183                 next = readl(devpriv->plx9080_mmio + PLX_DMA0_PCI_ADDRESS_REG);
184 
185         idx = devpriv->dma_desc_index;
186         start = le32_to_cpu(devpriv->dma_desc[idx].pci_start_addr);
187         /* loop until we have read all the full buffers */
188         for (desc = 0; (next < start || next >= start + devpriv->block_size) &&
189              desc < devpriv->num_dma_descriptors; desc++) {
190                 /* transfer data from dma buffer to comedi buffer */
191                 size = devpriv->block_size / sizeof(uint32_t);
192                 if (cmd->stop_src == TRIG_COUNT) {
193                         if (size > devpriv->dio_count)
194                                 size = devpriv->dio_count;
195                         devpriv->dio_count -= size;
196                 }
197                 comedi_buf_write_samples(s, devpriv->desc_dio_buffer[idx],
198                                          size);
199                 idx++;
200                 idx %= devpriv->num_dma_descriptors;
201                 start = le32_to_cpu(devpriv->dma_desc[idx].pci_start_addr);
202 
203                 devpriv->dma_desc_index = idx;
204         }
205         /*  XXX check for buffer overrun somehow */
206 }
207 
208 static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
209 {
210         struct comedi_device *dev = d;
211         struct hpdi_private *devpriv = dev->private;
212         struct comedi_subdevice *s = dev->read_subdev;
213         struct comedi_async *async = s->async;
214         uint32_t hpdi_intr_status, hpdi_board_status;
215         uint32_t plx_status;
216         uint32_t plx_bits;
217         uint8_t dma0_status, dma1_status;
218         unsigned long flags;
219 
220         if (!dev->attached)
221                 return IRQ_NONE;
222 
223         plx_status = readl(devpriv->plx9080_mmio + PLX_INTRCS_REG);
224         if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
225                 return IRQ_NONE;
226 
227         hpdi_intr_status = readl(dev->mmio + INTERRUPT_STATUS_REG);
228         hpdi_board_status = readl(dev->mmio + BOARD_STATUS_REG);
229 
230         if (hpdi_intr_status)
231                 writel(hpdi_intr_status, dev->mmio + INTERRUPT_STATUS_REG);
232 
233         /*  spin lock makes sure no one else changes plx dma control reg */
234         spin_lock_irqsave(&dev->spinlock, flags);
235         dma0_status = readb(devpriv->plx9080_mmio + PLX_DMA0_CS_REG);
236         if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
237                 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
238                        devpriv->plx9080_mmio + PLX_DMA0_CS_REG);
239 
240                 if (dma0_status & PLX_DMA_EN_BIT)
241                         gsc_hpdi_drain_dma(dev, 0);
242         }
243         spin_unlock_irqrestore(&dev->spinlock, flags);
244 
245         /*  spin lock makes sure no one else changes plx dma control reg */
246         spin_lock_irqsave(&dev->spinlock, flags);
247         dma1_status = readb(devpriv->plx9080_mmio + PLX_DMA1_CS_REG);
248         if (plx_status & ICS_DMA1_A) {  /*  XXX *//*  dma chan 1 interrupt */
249                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
250                        devpriv->plx9080_mmio + PLX_DMA1_CS_REG);
251         }
252         spin_unlock_irqrestore(&dev->spinlock, flags);
253 
254         /*  clear possible plx9080 interrupt sources */
255         if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
256                 plx_bits = readl(devpriv->plx9080_mmio + PLX_DBR_OUT_REG);
257                 writel(plx_bits, devpriv->plx9080_mmio + PLX_DBR_OUT_REG);
258         }
259 
260         if (hpdi_board_status & RX_OVERRUN_BIT) {
261                 dev_err(dev->class_dev, "rx fifo overrun\n");
262                 async->events |= COMEDI_CB_ERROR;
263         }
264 
265         if (hpdi_board_status & RX_UNDERRUN_BIT) {
266                 dev_err(dev->class_dev, "rx fifo underrun\n");
267                 async->events |= COMEDI_CB_ERROR;
268         }
269 
270         if (devpriv->dio_count == 0)
271                 async->events |= COMEDI_CB_EOA;
272 
273         comedi_handle_events(dev, s);
274 
275         return IRQ_HANDLED;
276 }
277 
278 static void gsc_hpdi_abort_dma(struct comedi_device *dev, unsigned int channel)
279 {
280         struct hpdi_private *devpriv = dev->private;
281         unsigned long flags;
282 
283         /*  spinlock for plx dma control/status reg */
284         spin_lock_irqsave(&dev->spinlock, flags);
285 
286         plx9080_abort_dma(devpriv->plx9080_mmio, channel);
287 
288         spin_unlock_irqrestore(&dev->spinlock, flags);
289 }
290 
291 static int gsc_hpdi_cancel(struct comedi_device *dev,
292                            struct comedi_subdevice *s)
293 {
294         writel(0, dev->mmio + BOARD_CONTROL_REG);
295         writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
296 
297         gsc_hpdi_abort_dma(dev, 0);
298 
299         return 0;
300 }
301 
302 static int gsc_hpdi_cmd(struct comedi_device *dev,
303                         struct comedi_subdevice *s)
304 {
305         struct hpdi_private *devpriv = dev->private;
306         struct comedi_async *async = s->async;
307         struct comedi_cmd *cmd = &async->cmd;
308         unsigned long flags;
309         uint32_t bits;
310 
311         if (s->io_bits)
312                 return -EINVAL;
313 
314         writel(RX_FIFO_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
315 
316         gsc_hpdi_abort_dma(dev, 0);
317 
318         devpriv->dma_desc_index = 0;
319 
320         /*
321          * These register are supposedly unused during chained dma,
322          * but I have found that left over values from last operation
323          * occasionally cause problems with transfer of first dma
324          * block.  Initializing them to zero seems to fix the problem.
325          */
326         writel(0, devpriv->plx9080_mmio + PLX_DMA0_TRANSFER_SIZE_REG);
327         writel(0, devpriv->plx9080_mmio + PLX_DMA0_PCI_ADDRESS_REG);
328         writel(0, devpriv->plx9080_mmio + PLX_DMA0_LOCAL_ADDRESS_REG);
329 
330         /* give location of first dma descriptor */
331         bits = devpriv->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
332                PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
333         writel(bits, devpriv->plx9080_mmio + PLX_DMA0_DESCRIPTOR_REG);
334 
335         /* enable dma transfer */
336         spin_lock_irqsave(&dev->spinlock, flags);
337         writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
338                devpriv->plx9080_mmio + PLX_DMA0_CS_REG);
339         spin_unlock_irqrestore(&dev->spinlock, flags);
340 
341         if (cmd->stop_src == TRIG_COUNT)
342                 devpriv->dio_count = cmd->stop_arg;
343         else
344                 devpriv->dio_count = 1;
345 
346         /* clear over/under run status flags */
347         writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT, dev->mmio + BOARD_STATUS_REG);
348 
349         /* enable interrupts */
350         writel(RX_FULL_INTR, dev->mmio + INTERRUPT_CONTROL_REG);
351 
352         writel(RX_ENABLE_BIT, dev->mmio + BOARD_CONTROL_REG);
353 
354         return 0;
355 }
356 
357 static int gsc_hpdi_check_chanlist(struct comedi_device *dev,
358                                    struct comedi_subdevice *s,
359                                    struct comedi_cmd *cmd)
360 {
361         int i;
362 
363         for (i = 0; i < cmd->chanlist_len; i++) {
364                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
365 
366                 if (chan != i) {
367                         dev_dbg(dev->class_dev,
368                                 "chanlist must be ch 0 to 31 in order\n");
369                         return -EINVAL;
370                 }
371         }
372 
373         return 0;
374 }
375 
376 static int gsc_hpdi_cmd_test(struct comedi_device *dev,
377                              struct comedi_subdevice *s,
378                              struct comedi_cmd *cmd)
379 {
380         int err = 0;
381 
382         if (s->io_bits)
383                 return -EINVAL;
384 
385         /* Step 1 : check if triggers are trivially valid */
386 
387         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
388         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
389         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
390         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
391         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
392 
393         if (err)
394                 return 1;
395 
396         /* Step 2a : make sure trigger sources are unique */
397 
398         err |= comedi_check_trigger_is_unique(cmd->stop_src);
399 
400         /* Step 2b : and mutually compatible */
401 
402         if (err)
403                 return 2;
404 
405         /* Step 3: check if arguments are trivially valid */
406 
407         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
408 
409         if (!cmd->chanlist_len || !cmd->chanlist) {
410                 cmd->chanlist_len = 32;
411                 err |= -EINVAL;
412         }
413         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
414                                            cmd->chanlist_len);
415 
416         if (cmd->stop_src == TRIG_COUNT)
417                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
418         else    /* TRIG_NONE */
419                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
420 
421         if (err)
422                 return 3;
423 
424         /* Step 4: fix up any arguments */
425 
426         /* Step 5: check channel list if it exists */
427 
428         if (cmd->chanlist && cmd->chanlist_len > 0)
429                 err |= gsc_hpdi_check_chanlist(dev, s, cmd);
430 
431         if (err)
432                 return 5;
433 
434         return 0;
435 }
436 
437 /* setup dma descriptors so a link completes every 'len' bytes */
438 static int gsc_hpdi_setup_dma_descriptors(struct comedi_device *dev,
439                                           unsigned int len)
440 {
441         struct hpdi_private *devpriv = dev->private;
442         dma_addr_t phys_addr = devpriv->dma_desc_phys_addr;
443         uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
444                              PLX_XFER_LOCAL_TO_PCI;
445         unsigned int offset = 0;
446         unsigned int idx = 0;
447         unsigned int i;
448 
449         if (len > DMA_BUFFER_SIZE)
450                 len = DMA_BUFFER_SIZE;
451         len -= len % sizeof(uint32_t);
452         if (len == 0)
453                 return -EINVAL;
454 
455         for (i = 0; i < NUM_DMA_DESCRIPTORS && idx < NUM_DMA_BUFFERS; i++) {
456                 devpriv->dma_desc[i].pci_start_addr =
457                     cpu_to_le32(devpriv->dio_buffer_phys_addr[idx] + offset);
458                 devpriv->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
459                 devpriv->dma_desc[i].transfer_size = cpu_to_le32(len);
460                 devpriv->dma_desc[i].next = cpu_to_le32((phys_addr +
461                         (i + 1) * sizeof(devpriv->dma_desc[0])) | next_bits);
462 
463                 devpriv->desc_dio_buffer[i] = devpriv->dio_buffer[idx] +
464                                               (offset / sizeof(uint32_t));
465 
466                 offset += len;
467                 if (len + offset > DMA_BUFFER_SIZE) {
468                         offset = 0;
469                         idx++;
470                 }
471         }
472         devpriv->num_dma_descriptors = i;
473         /* fix last descriptor to point back to first */
474         devpriv->dma_desc[i - 1].next = cpu_to_le32(phys_addr | next_bits);
475 
476         devpriv->block_size = len;
477 
478         return len;
479 }
480 
481 static int gsc_hpdi_dio_insn_config(struct comedi_device *dev,
482                                     struct comedi_subdevice *s,
483                                     struct comedi_insn *insn,
484                                     unsigned int *data)
485 {
486         int ret;
487 
488         switch (data[0]) {
489         case INSN_CONFIG_BLOCK_SIZE:
490                 ret = gsc_hpdi_setup_dma_descriptors(dev, data[1]);
491                 if (ret)
492                         return ret;
493 
494                 data[1] = ret;
495                 break;
496         default:
497                 ret = comedi_dio_insn_config(dev, s, insn, data, 0xffffffff);
498                 if (ret)
499                         return ret;
500                 break;
501         }
502 
503         return insn->n;
504 }
505 
506 static void gsc_hpdi_free_dma(struct comedi_device *dev)
507 {
508         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
509         struct hpdi_private *devpriv = dev->private;
510         int i;
511 
512         if (!devpriv)
513                 return;
514 
515         /* free pci dma buffers */
516         for (i = 0; i < NUM_DMA_BUFFERS; i++) {
517                 if (devpriv->dio_buffer[i])
518                         pci_free_consistent(pcidev,
519                                             DMA_BUFFER_SIZE,
520                                             devpriv->dio_buffer[i],
521                                             devpriv->dio_buffer_phys_addr[i]);
522         }
523         /* free dma descriptors */
524         if (devpriv->dma_desc)
525                 pci_free_consistent(pcidev,
526                                     sizeof(struct plx_dma_desc) *
527                                     NUM_DMA_DESCRIPTORS,
528                                     devpriv->dma_desc,
529                                     devpriv->dma_desc_phys_addr);
530 }
531 
532 static int gsc_hpdi_init(struct comedi_device *dev)
533 {
534         struct hpdi_private *devpriv = dev->private;
535         uint32_t plx_intcsr_bits;
536 
537         /* wait 10usec after reset before accessing fifos */
538         writel(BOARD_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
539         udelay(10);
540 
541         writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
542                dev->mmio + RX_PROG_ALMOST_REG);
543         writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
544                dev->mmio + TX_PROG_ALMOST_REG);
545 
546         devpriv->tx_fifo_size = readl(dev->mmio + TX_FIFO_SIZE_REG) &
547                                 FIFO_SIZE_MASK;
548         devpriv->rx_fifo_size = readl(dev->mmio + RX_FIFO_SIZE_REG) &
549                                 FIFO_SIZE_MASK;
550 
551         writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
552 
553         /*  enable interrupts */
554         plx_intcsr_bits =
555             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
556             ICS_DMA0_E;
557         writel(plx_intcsr_bits, devpriv->plx9080_mmio + PLX_INTRCS_REG);
558 
559         return 0;
560 }
561 
562 static void gsc_hpdi_init_plx9080(struct comedi_device *dev)
563 {
564         struct hpdi_private *devpriv = dev->private;
565         uint32_t bits;
566         void __iomem *plx_iobase = devpriv->plx9080_mmio;
567 
568 #ifdef __BIG_ENDIAN
569         bits = BIGEND_DMA0 | BIGEND_DMA1;
570 #else
571         bits = 0;
572 #endif
573         writel(bits, devpriv->plx9080_mmio + PLX_BIGEND_REG);
574 
575         writel(0, devpriv->plx9080_mmio + PLX_INTRCS_REG);
576 
577         gsc_hpdi_abort_dma(dev, 0);
578         gsc_hpdi_abort_dma(dev, 1);
579 
580         /*  configure dma0 mode */
581         bits = 0;
582         /*  enable ready input */
583         bits |= PLX_DMA_EN_READYIN_BIT;
584         /*  enable dma chaining */
585         bits |= PLX_EN_CHAIN_BIT;
586         /*  enable interrupt on dma done
587          *  (probably don't need this, since chain never finishes) */
588         bits |= PLX_EN_DMA_DONE_INTR_BIT;
589         /*  don't increment local address during transfers
590          *  (we are transferring from a fixed fifo register) */
591         bits |= PLX_LOCAL_ADDR_CONST_BIT;
592         /*  route dma interrupt to pci bus */
593         bits |= PLX_DMA_INTR_PCI_BIT;
594         /*  enable demand mode */
595         bits |= PLX_DEMAND_MODE_BIT;
596         /*  enable local burst mode */
597         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
598         bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
599         writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
600 }
601 
602 static const struct hpdi_board *gsc_hpdi_find_board(struct pci_dev *pcidev)
603 {
604         unsigned int i;
605 
606         for (i = 0; i < ARRAY_SIZE(hpdi_boards); i++)
607                 if (pcidev->device == hpdi_boards[i].device_id &&
608                     pcidev->subsystem_device == hpdi_boards[i].subdevice_id)
609                         return &hpdi_boards[i];
610         return NULL;
611 }
612 
613 static int gsc_hpdi_auto_attach(struct comedi_device *dev,
614                                 unsigned long context_unused)
615 {
616         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
617         const struct hpdi_board *thisboard;
618         struct hpdi_private *devpriv;
619         struct comedi_subdevice *s;
620         int i;
621         int retval;
622 
623         thisboard = gsc_hpdi_find_board(pcidev);
624         if (!thisboard) {
625                 dev_err(dev->class_dev, "gsc_hpdi: pci %s not supported\n",
626                         pci_name(pcidev));
627                 return -EINVAL;
628         }
629         dev->board_ptr = thisboard;
630         dev->board_name = thisboard->name;
631 
632         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
633         if (!devpriv)
634                 return -ENOMEM;
635 
636         retval = comedi_pci_enable(dev);
637         if (retval)
638                 return retval;
639         pci_set_master(pcidev);
640 
641         devpriv->plx9080_mmio = pci_ioremap_bar(pcidev, 0);
642         dev->mmio = pci_ioremap_bar(pcidev, 2);
643         if (!devpriv->plx9080_mmio || !dev->mmio) {
644                 dev_warn(dev->class_dev, "failed to remap io memory\n");
645                 return -ENOMEM;
646         }
647 
648         gsc_hpdi_init_plx9080(dev);
649 
650         /*  get irq */
651         if (request_irq(pcidev->irq, gsc_hpdi_interrupt, IRQF_SHARED,
652                         dev->board_name, dev)) {
653                 dev_warn(dev->class_dev,
654                          "unable to allocate irq %u\n", pcidev->irq);
655                 return -EINVAL;
656         }
657         dev->irq = pcidev->irq;
658 
659         dev_dbg(dev->class_dev, " irq %u\n", dev->irq);
660 
661         /*  allocate pci dma buffers */
662         for (i = 0; i < NUM_DMA_BUFFERS; i++) {
663                 devpriv->dio_buffer[i] =
664                     pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
665                                          &devpriv->dio_buffer_phys_addr[i]);
666         }
667         /*  allocate dma descriptors */
668         devpriv->dma_desc = pci_alloc_consistent(pcidev,
669                                                  sizeof(struct plx_dma_desc) *
670                                                  NUM_DMA_DESCRIPTORS,
671                                                  &devpriv->dma_desc_phys_addr);
672         if (devpriv->dma_desc_phys_addr & 0xf) {
673                 dev_warn(dev->class_dev,
674                          " dma descriptors not quad-word aligned (bug)\n");
675                 return -EIO;
676         }
677 
678         retval = gsc_hpdi_setup_dma_descriptors(dev, 0x1000);
679         if (retval < 0)
680                 return retval;
681 
682         retval = comedi_alloc_subdevices(dev, 1);
683         if (retval)
684                 return retval;
685 
686         /* Digital I/O subdevice */
687         s = &dev->subdevices[0];
688         dev->read_subdev = s;
689         s->type         = COMEDI_SUBD_DIO;
690         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL |
691                           SDF_CMD_READ;
692         s->n_chan       = 32;
693         s->len_chanlist = 32;
694         s->maxdata      = 1;
695         s->range_table  = &range_digital;
696         s->insn_config  = gsc_hpdi_dio_insn_config;
697         s->do_cmd       = gsc_hpdi_cmd;
698         s->do_cmdtest   = gsc_hpdi_cmd_test;
699         s->cancel       = gsc_hpdi_cancel;
700 
701         return gsc_hpdi_init(dev);
702 }
703 
704 static void gsc_hpdi_detach(struct comedi_device *dev)
705 {
706         struct hpdi_private *devpriv = dev->private;
707 
708         if (dev->irq)
709                 free_irq(dev->irq, dev);
710         if (devpriv) {
711                 if (devpriv->plx9080_mmio) {
712                         writel(0, devpriv->plx9080_mmio + PLX_INTRCS_REG);
713                         iounmap(devpriv->plx9080_mmio);
714                 }
715                 if (dev->mmio)
716                         iounmap(dev->mmio);
717         }
718         comedi_pci_disable(dev);
719         gsc_hpdi_free_dma(dev);
720 }
721 
722 static struct comedi_driver gsc_hpdi_driver = {
723         .driver_name    = "gsc_hpdi",
724         .module         = THIS_MODULE,
725         .auto_attach    = gsc_hpdi_auto_attach,
726         .detach         = gsc_hpdi_detach,
727 };
728 
729 static int gsc_hpdi_pci_probe(struct pci_dev *dev,
730                               const struct pci_device_id *id)
731 {
732         return comedi_pci_auto_config(dev, &gsc_hpdi_driver, id->driver_data);
733 }
734 
735 static const struct pci_device_id gsc_hpdi_pci_table[] = {
736         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX,
737                     0x2400, 0, 0, 0},
738         { 0 }
739 };
740 MODULE_DEVICE_TABLE(pci, gsc_hpdi_pci_table);
741 
742 static struct pci_driver gsc_hpdi_pci_driver = {
743         .name           = "gsc_hpdi",
744         .id_table       = gsc_hpdi_pci_table,
745         .probe          = gsc_hpdi_pci_probe,
746         .remove         = comedi_pci_auto_unconfig,
747 };
748 module_comedi_pci_driver(gsc_hpdi_driver, gsc_hpdi_pci_driver);
749 
750 MODULE_AUTHOR("Comedi http://www.comedi.org");
751 MODULE_DESCRIPTION("Comedi low-level driver");
752 MODULE_LICENSE("GPL");
753 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us