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Linux/drivers/staging/comedi/drivers/gsc_hpdi.c

  1 /*
  2  * gsc_hpdi.c
  3  * Comedi driver the General Standards Corporation
  4  * High Speed Parallel Digital Interface rs485 boards.
  5  *
  6  * Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
  7  * Copyright (C) 2003 Coherent Imaging Systems
  8  *
  9  * COMEDI - Linux Control and Measurement Device Interface
 10  * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
 11  *
 12  * This program is free software; you can redistribute it and/or modify
 13  * it under the terms of the GNU General Public License as published by
 14  * the Free Software Foundation; either version 2 of the License, or
 15  * (at your option) any later version.
 16  *
 17  * This program is distributed in the hope that it will be useful,
 18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 20  * GNU General Public License for more details.
 21  */
 22 
 23 /*
 24  * Driver: gsc_hpdi
 25  * Description: General Standards Corporation High
 26  *    Speed Parallel Digital Interface rs485 boards
 27  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
 28  * Status: only receive mode works, transmit not supported
 29  * Updated: Thu, 01 Nov 2012 16:17:38 +0000
 30  * Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
 31  *   PMC-HPDI32
 32  *
 33  * Configuration options:
 34  *    None.
 35  *
 36  * Manual configuration of supported devices is not supported; they are
 37  * configured automatically.
 38  *
 39  * There are some additional hpdi models available from GSC for which
 40  * support could be added to this driver.
 41  */
 42 
 43 #include <linux/module.h>
 44 #include <linux/pci.h>
 45 #include <linux/delay.h>
 46 #include <linux/interrupt.h>
 47 
 48 #include "../comedidev.h"
 49 
 50 #include "plx9080.h"
 51 #include "comedi_fc.h"
 52 
 53 /*
 54  * PCI BAR2 Register map (devpriv->mmio)
 55  */
 56 #define FIRMWARE_REV_REG                        0x00
 57 #define FEATURES_REG_PRESENT_BIT                (1 << 15)
 58 #define BOARD_CONTROL_REG                       0x04
 59 #define BOARD_RESET_BIT                         (1 << 0)
 60 #define TX_FIFO_RESET_BIT                       (1 << 1)
 61 #define RX_FIFO_RESET_BIT                       (1 << 2)
 62 #define TX_ENABLE_BIT                           (1 << 4)
 63 #define RX_ENABLE_BIT                           (1 << 5)
 64 #define DEMAND_DMA_DIRECTION_TX_BIT             (1 << 6)  /* ch 0 only */
 65 #define LINE_VALID_ON_STATUS_VALID_BIT          (1 << 7)
 66 #define START_TX_BIT                            (1 << 8)
 67 #define CABLE_THROTTLE_ENABLE_BIT               (1 << 9)
 68 #define TEST_MODE_ENABLE_BIT                    (1 << 31)
 69 #define BOARD_STATUS_REG                        0x08
 70 #define COMMAND_LINE_STATUS_MASK                (0x7f << 0)
 71 #define TX_IN_PROGRESS_BIT                      (1 << 7)
 72 #define TX_NOT_EMPTY_BIT                        (1 << 8)
 73 #define TX_NOT_ALMOST_EMPTY_BIT                 (1 << 9)
 74 #define TX_NOT_ALMOST_FULL_BIT                  (1 << 10)
 75 #define TX_NOT_FULL_BIT                         (1 << 11)
 76 #define RX_NOT_EMPTY_BIT                        (1 << 12)
 77 #define RX_NOT_ALMOST_EMPTY_BIT                 (1 << 13)
 78 #define RX_NOT_ALMOST_FULL_BIT                  (1 << 14)
 79 #define RX_NOT_FULL_BIT                         (1 << 15)
 80 #define BOARD_JUMPER0_INSTALLED_BIT             (1 << 16)
 81 #define BOARD_JUMPER1_INSTALLED_BIT             (1 << 17)
 82 #define TX_OVERRUN_BIT                          (1 << 21)
 83 #define RX_UNDERRUN_BIT                         (1 << 22)
 84 #define RX_OVERRUN_BIT                          (1 << 23)
 85 #define TX_PROG_ALMOST_REG                      0x0c
 86 #define RX_PROG_ALMOST_REG                      0x10
 87 #define ALMOST_EMPTY_BITS(x)                    (((x) & 0xffff) << 0)
 88 #define ALMOST_FULL_BITS(x)                     (((x) & 0xff) << 16)
 89 #define FEATURES_REG                            0x14
 90 #define FIFO_SIZE_PRESENT_BIT                   (1 << 0)
 91 #define FIFO_WORDS_PRESENT_BIT                  (1 << 1)
 92 #define LEVEL_EDGE_INTERRUPTS_PRESENT_BIT       (1 << 2)
 93 #define GPIO_SUPPORTED_BIT                      (1 << 3)
 94 #define PLX_DMA_CH1_SUPPORTED_BIT               (1 << 4)
 95 #define OVERRUN_UNDERRUN_SUPPORTED_BIT          (1 << 5)
 96 #define FIFO_REG                                0x18
 97 #define TX_STATUS_COUNT_REG                     0x1c
 98 #define TX_LINE_VALID_COUNT_REG                 0x20,
 99 #define TX_LINE_INVALID_COUNT_REG               0x24
100 #define RX_STATUS_COUNT_REG                     0x28
101 #define RX_LINE_COUNT_REG                       0x2c
102 #define INTERRUPT_CONTROL_REG                   0x30
103 #define FRAME_VALID_START_INTR                  (1 << 0)
104 #define FRAME_VALID_END_INTR                    (1 << 1)
105 #define TX_FIFO_EMPTY_INTR                      (1 << 8)
106 #define TX_FIFO_ALMOST_EMPTY_INTR               (1 << 9)
107 #define TX_FIFO_ALMOST_FULL_INTR                (1 << 10)
108 #define TX_FIFO_FULL_INTR                       (1 << 11)
109 #define RX_EMPTY_INTR                           (1 << 12)
110 #define RX_ALMOST_EMPTY_INTR                    (1 << 13)
111 #define RX_ALMOST_FULL_INTR                     (1 << 14)
112 #define RX_FULL_INTR                            (1 << 15)
113 #define INTERRUPT_STATUS_REG                    0x34
114 #define TX_CLOCK_DIVIDER_REG                    0x38
115 #define TX_FIFO_SIZE_REG                        0x40
116 #define RX_FIFO_SIZE_REG                        0x44
117 #define FIFO_SIZE_MASK                          (0xfffff << 0)
118 #define TX_FIFO_WORDS_REG                       0x48
119 #define RX_FIFO_WORDS_REG                       0x4c
120 #define INTERRUPT_EDGE_LEVEL_REG                0x50
121 #define INTERRUPT_POLARITY_REG                  0x54
122 
123 #define TIMER_BASE                              50      /* 20MHz master clock */
124 #define DMA_BUFFER_SIZE                         0x10000
125 #define NUM_DMA_BUFFERS                         4
126 #define NUM_DMA_DESCRIPTORS                     256
127 
128 struct hpdi_board {
129         const char *name;
130         int device_id;
131         int subdevice_id;
132 };
133 
134 static const struct hpdi_board hpdi_boards[] = {
135         {
136                 .name           = "pci-hpdi32",
137                 .device_id      = PCI_DEVICE_ID_PLX_9080,
138                 .subdevice_id   = 0x2400,
139          },
140 #if 0
141         {
142                 .name           = "pxi-hpdi32",
143                 .device_id      = 0x9656,
144                 .subdevice_id   = 0x2705,
145          },
146 #endif
147 };
148 
149 struct hpdi_private {
150         void __iomem *plx9080_mmio;
151         void __iomem *mmio;
152         uint32_t *dio_buffer[NUM_DMA_BUFFERS];  /*  dma buffers */
153         /* physical addresses of dma buffers */
154         dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
155         /* array of dma descriptors read by plx9080, allocated to get proper
156          * alignment */
157         struct plx_dma_desc *dma_desc;
158         /* physical address of dma descriptor array */
159         dma_addr_t dma_desc_phys_addr;
160         unsigned int num_dma_descriptors;
161         /* pointer to start of buffers indexed by descriptor */
162         uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
163         /* index of the dma descriptor that is currently being used */
164         unsigned int dma_desc_index;
165         unsigned int tx_fifo_size;
166         unsigned int rx_fifo_size;
167         unsigned long dio_count;
168         /* number of bytes at which to generate COMEDI_CB_BLOCK events */
169         unsigned int block_size;
170 };
171 
172 static void gsc_hpdi_drain_dma(struct comedi_device *dev, unsigned int channel)
173 {
174         struct hpdi_private *devpriv = dev->private;
175         struct comedi_subdevice *s = dev->read_subdev;
176         struct comedi_cmd *cmd = &s->async->cmd;
177         unsigned int idx;
178         unsigned int start;
179         unsigned int desc;
180         unsigned int size;
181         unsigned int next;
182 
183         if (channel)
184                 next = readl(devpriv->plx9080_mmio + PLX_DMA1_PCI_ADDRESS_REG);
185         else
186                 next = readl(devpriv->plx9080_mmio + PLX_DMA0_PCI_ADDRESS_REG);
187 
188         idx = devpriv->dma_desc_index;
189         start = le32_to_cpu(devpriv->dma_desc[idx].pci_start_addr);
190         /* loop until we have read all the full buffers */
191         for (desc = 0; (next < start || next >= start + devpriv->block_size) &&
192              desc < devpriv->num_dma_descriptors; desc++) {
193                 /* transfer data from dma buffer to comedi buffer */
194                 size = devpriv->block_size / sizeof(uint32_t);
195                 if (cmd->stop_src == TRIG_COUNT) {
196                         if (size > devpriv->dio_count)
197                                 size = devpriv->dio_count;
198                         devpriv->dio_count -= size;
199                 }
200                 cfc_write_array_to_buffer(s, devpriv->desc_dio_buffer[idx],
201                                           size * sizeof(uint32_t));
202                 idx++;
203                 idx %= devpriv->num_dma_descriptors;
204                 start = le32_to_cpu(devpriv->dma_desc[idx].pci_start_addr);
205 
206                 devpriv->dma_desc_index = idx;
207         }
208         /*  XXX check for buffer overrun somehow */
209 }
210 
211 static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
212 {
213         struct comedi_device *dev = d;
214         struct hpdi_private *devpriv = dev->private;
215         struct comedi_subdevice *s = dev->read_subdev;
216         struct comedi_async *async = s->async;
217         uint32_t hpdi_intr_status, hpdi_board_status;
218         uint32_t plx_status;
219         uint32_t plx_bits;
220         uint8_t dma0_status, dma1_status;
221         unsigned long flags;
222 
223         if (!dev->attached)
224                 return IRQ_NONE;
225 
226         plx_status = readl(devpriv->plx9080_mmio + PLX_INTRCS_REG);
227         if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
228                 return IRQ_NONE;
229 
230         hpdi_intr_status = readl(devpriv->mmio + INTERRUPT_STATUS_REG);
231         hpdi_board_status = readl(devpriv->mmio + BOARD_STATUS_REG);
232 
233         if (hpdi_intr_status)
234                 writel(hpdi_intr_status, devpriv->mmio + INTERRUPT_STATUS_REG);
235 
236         /*  spin lock makes sure no one else changes plx dma control reg */
237         spin_lock_irqsave(&dev->spinlock, flags);
238         dma0_status = readb(devpriv->plx9080_mmio + PLX_DMA0_CS_REG);
239         if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
240                 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
241                        devpriv->plx9080_mmio + PLX_DMA0_CS_REG);
242 
243                 if (dma0_status & PLX_DMA_EN_BIT)
244                         gsc_hpdi_drain_dma(dev, 0);
245         }
246         spin_unlock_irqrestore(&dev->spinlock, flags);
247 
248         /*  spin lock makes sure no one else changes plx dma control reg */
249         spin_lock_irqsave(&dev->spinlock, flags);
250         dma1_status = readb(devpriv->plx9080_mmio + PLX_DMA1_CS_REG);
251         if (plx_status & ICS_DMA1_A) {  /*  XXX *//*  dma chan 1 interrupt */
252                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
253                        devpriv->plx9080_mmio + PLX_DMA1_CS_REG);
254         }
255         spin_unlock_irqrestore(&dev->spinlock, flags);
256 
257         /*  clear possible plx9080 interrupt sources */
258         if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
259                 plx_bits = readl(devpriv->plx9080_mmio + PLX_DBR_OUT_REG);
260                 writel(plx_bits, devpriv->plx9080_mmio + PLX_DBR_OUT_REG);
261         }
262 
263         if (hpdi_board_status & RX_OVERRUN_BIT) {
264                 dev_err(dev->class_dev, "rx fifo overrun\n");
265                 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
266         }
267 
268         if (hpdi_board_status & RX_UNDERRUN_BIT) {
269                 dev_err(dev->class_dev, "rx fifo underrun\n");
270                 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
271         }
272 
273         if (devpriv->dio_count == 0)
274                 async->events |= COMEDI_CB_EOA;
275 
276         cfc_handle_events(dev, s);
277 
278         return IRQ_HANDLED;
279 }
280 
281 static void gsc_hpdi_abort_dma(struct comedi_device *dev, unsigned int channel)
282 {
283         struct hpdi_private *devpriv = dev->private;
284         unsigned long flags;
285 
286         /*  spinlock for plx dma control/status reg */
287         spin_lock_irqsave(&dev->spinlock, flags);
288 
289         plx9080_abort_dma(devpriv->plx9080_mmio, channel);
290 
291         spin_unlock_irqrestore(&dev->spinlock, flags);
292 }
293 
294 static int gsc_hpdi_cancel(struct comedi_device *dev,
295                            struct comedi_subdevice *s)
296 {
297         struct hpdi_private *devpriv = dev->private;
298 
299         writel(0, devpriv->mmio + BOARD_CONTROL_REG);
300         writel(0, devpriv->mmio + INTERRUPT_CONTROL_REG);
301 
302         gsc_hpdi_abort_dma(dev, 0);
303 
304         return 0;
305 }
306 
307 static int gsc_hpdi_cmd(struct comedi_device *dev,
308                         struct comedi_subdevice *s)
309 {
310         struct hpdi_private *devpriv = dev->private;
311         struct comedi_async *async = s->async;
312         struct comedi_cmd *cmd = &async->cmd;
313         unsigned long flags;
314         uint32_t bits;
315 
316         if (s->io_bits)
317                 return -EINVAL;
318 
319         writel(RX_FIFO_RESET_BIT, devpriv->mmio + BOARD_CONTROL_REG);
320 
321         gsc_hpdi_abort_dma(dev, 0);
322 
323         devpriv->dma_desc_index = 0;
324 
325         /*
326          * These register are supposedly unused during chained dma,
327          * but I have found that left over values from last operation
328          * occasionally cause problems with transfer of first dma
329          * block.  Initializing them to zero seems to fix the problem.
330          */
331         writel(0, devpriv->plx9080_mmio + PLX_DMA0_TRANSFER_SIZE_REG);
332         writel(0, devpriv->plx9080_mmio + PLX_DMA0_PCI_ADDRESS_REG);
333         writel(0, devpriv->plx9080_mmio + PLX_DMA0_LOCAL_ADDRESS_REG);
334 
335         /* give location of first dma descriptor */
336         bits = devpriv->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
337                PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
338         writel(bits, devpriv->plx9080_mmio + PLX_DMA0_DESCRIPTOR_REG);
339 
340         /* enable dma transfer */
341         spin_lock_irqsave(&dev->spinlock, flags);
342         writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
343                devpriv->plx9080_mmio + PLX_DMA0_CS_REG);
344         spin_unlock_irqrestore(&dev->spinlock, flags);
345 
346         if (cmd->stop_src == TRIG_COUNT)
347                 devpriv->dio_count = cmd->stop_arg;
348         else
349                 devpriv->dio_count = 1;
350 
351         /* clear over/under run status flags */
352         writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT,
353                devpriv->mmio + BOARD_STATUS_REG);
354 
355         /* enable interrupts */
356         writel(RX_FULL_INTR, devpriv->mmio + INTERRUPT_CONTROL_REG);
357 
358         writel(RX_ENABLE_BIT, devpriv->mmio + BOARD_CONTROL_REG);
359 
360         return 0;
361 }
362 
363 static int gsc_hpdi_cmd_test(struct comedi_device *dev,
364                              struct comedi_subdevice *s,
365                              struct comedi_cmd *cmd)
366 {
367         int err = 0;
368         int i;
369 
370         if (s->io_bits)
371                 return -EINVAL;
372 
373         /* Step 1 : check if triggers are trivially valid */
374 
375         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
376         err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
377         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
378         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
379         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
380 
381         if (err)
382                 return 1;
383 
384         /* Step 2a : make sure trigger sources are unique */
385 
386         err |= cfc_check_trigger_is_unique(cmd->stop_src);
387 
388         /* Step 2b : and mutually compatible */
389 
390         if (err)
391                 return 2;
392 
393         /* Step 3: check if arguments are trivially valid */
394 
395         if (!cmd->chanlist_len || !cmd->chanlist) {
396                 cmd->chanlist_len = 32;
397                 err |= -EINVAL;
398         }
399         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
400 
401         if (cmd->stop_src == TRIG_COUNT)
402                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
403         else    /* TRIG_NONE */
404                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
405 
406         if (err)
407                 return 3;
408 
409         /* step 4: fix up any arguments */
410 
411         if (err)
412                 return 4;
413 
414         /* step 5: complain about special chanlist considerations */
415 
416         for (i = 0; i < cmd->chanlist_len; i++) {
417                 if (CR_CHAN(cmd->chanlist[i]) != i) {
418                         /*  XXX could support 8 or 16 channels */
419                         dev_err(dev->class_dev,
420                                 "chanlist must be ch 0 to 31 in order");
421                         err |= -EINVAL;
422                         break;
423                 }
424         }
425 
426         if (err)
427                 return 5;
428 
429         return 0;
430 
431 }
432 
433 /* setup dma descriptors so a link completes every 'len' bytes */
434 static int gsc_hpdi_setup_dma_descriptors(struct comedi_device *dev,
435                                           unsigned int len)
436 {
437         struct hpdi_private *devpriv = dev->private;
438         dma_addr_t phys_addr = devpriv->dma_desc_phys_addr;
439         uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
440                              PLX_XFER_LOCAL_TO_PCI;
441         unsigned int offset = 0;
442         unsigned int idx = 0;
443         unsigned int i;
444 
445         if (len > DMA_BUFFER_SIZE)
446                 len = DMA_BUFFER_SIZE;
447         len -= len % sizeof(uint32_t);
448         if (len == 0)
449                 return -EINVAL;
450 
451         for (i = 0; i < NUM_DMA_DESCRIPTORS && idx < NUM_DMA_BUFFERS; i++) {
452                 devpriv->dma_desc[i].pci_start_addr =
453                     cpu_to_le32(devpriv->dio_buffer_phys_addr[idx] + offset);
454                 devpriv->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
455                 devpriv->dma_desc[i].transfer_size = cpu_to_le32(len);
456                 devpriv->dma_desc[i].next = cpu_to_le32((phys_addr +
457                         (i + 1) * sizeof(devpriv->dma_desc[0])) | next_bits);
458 
459                 devpriv->desc_dio_buffer[i] = devpriv->dio_buffer[idx] +
460                                               (offset / sizeof(uint32_t));
461 
462                 offset += len;
463                 if (len + offset > DMA_BUFFER_SIZE) {
464                         offset = 0;
465                         idx++;
466                 }
467         }
468         devpriv->num_dma_descriptors = i;
469         /* fix last descriptor to point back to first */
470         devpriv->dma_desc[i - 1].next = cpu_to_le32(phys_addr | next_bits);
471 
472         devpriv->block_size = len;
473 
474         return len;
475 }
476 
477 static int gsc_hpdi_dio_insn_config(struct comedi_device *dev,
478                                     struct comedi_subdevice *s,
479                                     struct comedi_insn *insn,
480                                     unsigned int *data)
481 {
482         int ret;
483 
484         switch (data[0]) {
485         case INSN_CONFIG_BLOCK_SIZE:
486                 ret = gsc_hpdi_setup_dma_descriptors(dev, data[1]);
487                 if (ret)
488                         return ret;
489 
490                 data[1] = ret;
491                 break;
492         default:
493                 ret = comedi_dio_insn_config(dev, s, insn, data, 0xffffffff);
494                 if (ret)
495                         return ret;
496                 break;
497         }
498 
499         return insn->n;
500 }
501 
502 static int gsc_hpdi_init(struct comedi_device *dev)
503 {
504         struct hpdi_private *devpriv = dev->private;
505         uint32_t plx_intcsr_bits;
506 
507         /* wait 10usec after reset before accessing fifos */
508         writel(BOARD_RESET_BIT, devpriv->mmio + BOARD_CONTROL_REG);
509         udelay(10);
510 
511         writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
512                devpriv->mmio + RX_PROG_ALMOST_REG);
513         writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
514                devpriv->mmio + TX_PROG_ALMOST_REG);
515 
516         devpriv->tx_fifo_size = readl(devpriv->mmio + TX_FIFO_SIZE_REG) &
517                                 FIFO_SIZE_MASK;
518         devpriv->rx_fifo_size = readl(devpriv->mmio + RX_FIFO_SIZE_REG) &
519                                 FIFO_SIZE_MASK;
520 
521         writel(0, devpriv->mmio + INTERRUPT_CONTROL_REG);
522 
523         /*  enable interrupts */
524         plx_intcsr_bits =
525             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
526             ICS_DMA0_E;
527         writel(plx_intcsr_bits, devpriv->plx9080_mmio + PLX_INTRCS_REG);
528 
529         return 0;
530 }
531 
532 static void gsc_hpdi_init_plx9080(struct comedi_device *dev)
533 {
534         struct hpdi_private *devpriv = dev->private;
535         uint32_t bits;
536         void __iomem *plx_iobase = devpriv->plx9080_mmio;
537 
538 #ifdef __BIG_ENDIAN
539         bits = BIGEND_DMA0 | BIGEND_DMA1;
540 #else
541         bits = 0;
542 #endif
543         writel(bits, devpriv->plx9080_mmio + PLX_BIGEND_REG);
544 
545         writel(0, devpriv->plx9080_mmio + PLX_INTRCS_REG);
546 
547         gsc_hpdi_abort_dma(dev, 0);
548         gsc_hpdi_abort_dma(dev, 1);
549 
550         /*  configure dma0 mode */
551         bits = 0;
552         /*  enable ready input */
553         bits |= PLX_DMA_EN_READYIN_BIT;
554         /*  enable dma chaining */
555         bits |= PLX_EN_CHAIN_BIT;
556         /*  enable interrupt on dma done
557          *  (probably don't need this, since chain never finishes) */
558         bits |= PLX_EN_DMA_DONE_INTR_BIT;
559         /*  don't increment local address during transfers
560          *  (we are transferring from a fixed fifo register) */
561         bits |= PLX_LOCAL_ADDR_CONST_BIT;
562         /*  route dma interrupt to pci bus */
563         bits |= PLX_DMA_INTR_PCI_BIT;
564         /*  enable demand mode */
565         bits |= PLX_DEMAND_MODE_BIT;
566         /*  enable local burst mode */
567         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
568         bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
569         writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
570 }
571 
572 static const struct hpdi_board *gsc_hpdi_find_board(struct pci_dev *pcidev)
573 {
574         unsigned int i;
575 
576         for (i = 0; i < ARRAY_SIZE(hpdi_boards); i++)
577                 if (pcidev->device == hpdi_boards[i].device_id &&
578                     pcidev->subsystem_device == hpdi_boards[i].subdevice_id)
579                         return &hpdi_boards[i];
580         return NULL;
581 }
582 
583 static int gsc_hpdi_auto_attach(struct comedi_device *dev,
584                                 unsigned long context_unused)
585 {
586         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
587         const struct hpdi_board *thisboard;
588         struct hpdi_private *devpriv;
589         struct comedi_subdevice *s;
590         int i;
591         int retval;
592 
593         thisboard = gsc_hpdi_find_board(pcidev);
594         if (!thisboard) {
595                 dev_err(dev->class_dev, "gsc_hpdi: pci %s not supported\n",
596                         pci_name(pcidev));
597                 return -EINVAL;
598         }
599         dev->board_ptr = thisboard;
600         dev->board_name = thisboard->name;
601 
602         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
603         if (!devpriv)
604                 return -ENOMEM;
605 
606         retval = comedi_pci_enable(dev);
607         if (retval)
608                 return retval;
609         pci_set_master(pcidev);
610 
611         devpriv->plx9080_mmio = pci_ioremap_bar(pcidev, 0);
612         devpriv->mmio = pci_ioremap_bar(pcidev, 2);
613         if (!devpriv->plx9080_mmio || !devpriv->mmio) {
614                 dev_warn(dev->class_dev, "failed to remap io memory\n");
615                 return -ENOMEM;
616         }
617 
618         gsc_hpdi_init_plx9080(dev);
619 
620         /*  get irq */
621         if (request_irq(pcidev->irq, gsc_hpdi_interrupt, IRQF_SHARED,
622                         dev->board_name, dev)) {
623                 dev_warn(dev->class_dev,
624                          "unable to allocate irq %u\n", pcidev->irq);
625                 return -EINVAL;
626         }
627         dev->irq = pcidev->irq;
628 
629         dev_dbg(dev->class_dev, " irq %u\n", dev->irq);
630 
631         /*  allocate pci dma buffers */
632         for (i = 0; i < NUM_DMA_BUFFERS; i++) {
633                 devpriv->dio_buffer[i] =
634                     pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
635                                          &devpriv->dio_buffer_phys_addr[i]);
636         }
637         /*  allocate dma descriptors */
638         devpriv->dma_desc = pci_alloc_consistent(pcidev,
639                                                  sizeof(struct plx_dma_desc) *
640                                                  NUM_DMA_DESCRIPTORS,
641                                                  &devpriv->dma_desc_phys_addr);
642         if (devpriv->dma_desc_phys_addr & 0xf) {
643                 dev_warn(dev->class_dev,
644                          " dma descriptors not quad-word aligned (bug)\n");
645                 return -EIO;
646         }
647 
648         retval = gsc_hpdi_setup_dma_descriptors(dev, 0x1000);
649         if (retval < 0)
650                 return retval;
651 
652         retval = comedi_alloc_subdevices(dev, 1);
653         if (retval)
654                 return retval;
655 
656         /* Digital I/O subdevice */
657         s = &dev->subdevices[0];
658         dev->read_subdev = s;
659         s->type         = COMEDI_SUBD_DIO;
660         s->subdev_flags = SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL |
661                           SDF_CMD_READ;
662         s->n_chan       = 32;
663         s->len_chanlist = 32;
664         s->maxdata      = 1;
665         s->range_table  = &range_digital;
666         s->insn_config  = gsc_hpdi_dio_insn_config;
667         s->do_cmd       = gsc_hpdi_cmd;
668         s->do_cmdtest   = gsc_hpdi_cmd_test;
669         s->cancel       = gsc_hpdi_cancel;
670 
671         return gsc_hpdi_init(dev);
672 }
673 
674 static void gsc_hpdi_detach(struct comedi_device *dev)
675 {
676         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
677         struct hpdi_private *devpriv = dev->private;
678         unsigned int i;
679 
680         if (dev->irq)
681                 free_irq(dev->irq, dev);
682         if (devpriv) {
683                 if (devpriv->plx9080_mmio) {
684                         writel(0, devpriv->plx9080_mmio + PLX_INTRCS_REG);
685                         iounmap(devpriv->plx9080_mmio);
686                 }
687                 if (devpriv->mmio)
688                         iounmap(devpriv->mmio);
689                 /*  free pci dma buffers */
690                 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
691                         if (devpriv->dio_buffer[i])
692                                 pci_free_consistent(pcidev,
693                                                     DMA_BUFFER_SIZE,
694                                                     devpriv->dio_buffer[i],
695                                                     devpriv->
696                                                     dio_buffer_phys_addr[i]);
697                 }
698                 /*  free dma descriptors */
699                 if (devpriv->dma_desc)
700                         pci_free_consistent(pcidev,
701                                             sizeof(struct plx_dma_desc) *
702                                             NUM_DMA_DESCRIPTORS,
703                                             devpriv->dma_desc,
704                                             devpriv->dma_desc_phys_addr);
705         }
706         comedi_pci_disable(dev);
707 }
708 
709 static struct comedi_driver gsc_hpdi_driver = {
710         .driver_name    = "gsc_hpdi",
711         .module         = THIS_MODULE,
712         .auto_attach    = gsc_hpdi_auto_attach,
713         .detach         = gsc_hpdi_detach,
714 };
715 
716 static int gsc_hpdi_pci_probe(struct pci_dev *dev,
717                               const struct pci_device_id *id)
718 {
719         return comedi_pci_auto_config(dev, &gsc_hpdi_driver, id->driver_data);
720 }
721 
722 static const struct pci_device_id gsc_hpdi_pci_table[] = {
723         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX,
724                     0x2400, 0, 0, 0},
725         { 0 }
726 };
727 MODULE_DEVICE_TABLE(pci, gsc_hpdi_pci_table);
728 
729 static struct pci_driver gsc_hpdi_pci_driver = {
730         .name           = "gsc_hpdi",
731         .id_table       = gsc_hpdi_pci_table,
732         .probe          = gsc_hpdi_pci_probe,
733         .remove         = comedi_pci_auto_unconfig,
734 };
735 module_comedi_pci_driver(gsc_hpdi_driver, gsc_hpdi_pci_driver);
736 
737 MODULE_AUTHOR("Comedi http://www.comedi.org");
738 MODULE_DESCRIPTION("Comedi low-level driver");
739 MODULE_LICENSE("GPL");
740 

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