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Linux/drivers/staging/comedi/drivers/gsc_hpdi.c

  1 /*
  2  * gsc_hpdi.c
  3  * Comedi driver the General Standards Corporation
  4  * High Speed Parallel Digital Interface rs485 boards.
  5  *
  6  * Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
  7  * Copyright (C) 2003 Coherent Imaging Systems
  8  *
  9  * COMEDI - Linux Control and Measurement Device Interface
 10  * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
 11  *
 12  * This program is free software; you can redistribute it and/or modify
 13  * it under the terms of the GNU General Public License as published by
 14  * the Free Software Foundation; either version 2 of the License, or
 15  * (at your option) any later version.
 16  *
 17  * This program is distributed in the hope that it will be useful,
 18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 20  * GNU General Public License for more details.
 21  */
 22 
 23 /*
 24  * Driver: gsc_hpdi
 25  * Description: General Standards Corporation High
 26  *    Speed Parallel Digital Interface rs485 boards
 27  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
 28  * Status: only receive mode works, transmit not supported
 29  * Updated: Thu, 01 Nov 2012 16:17:38 +0000
 30  * Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
 31  *   PMC-HPDI32
 32  *
 33  * Configuration options:
 34  *    None.
 35  *
 36  * Manual configuration of supported devices is not supported; they are
 37  * configured automatically.
 38  *
 39  * There are some additional hpdi models available from GSC for which
 40  * support could be added to this driver.
 41  */
 42 
 43 #include <linux/module.h>
 44 #include <linux/delay.h>
 45 #include <linux/interrupt.h>
 46 
 47 #include "../comedi_pci.h"
 48 
 49 #include "plx9080.h"
 50 
 51 /*
 52  * PCI BAR2 Register map (dev->mmio)
 53  */
 54 #define FIRMWARE_REV_REG                        0x00
 55 #define FEATURES_REG_PRESENT_BIT                BIT(15)
 56 #define BOARD_CONTROL_REG                       0x04
 57 #define BOARD_RESET_BIT                         BIT(0)
 58 #define TX_FIFO_RESET_BIT                       BIT(1)
 59 #define RX_FIFO_RESET_BIT                       BIT(2)
 60 #define TX_ENABLE_BIT                           BIT(4)
 61 #define RX_ENABLE_BIT                           BIT(5)
 62 #define DEMAND_DMA_DIRECTION_TX_BIT             BIT(6)  /* ch 0 only */
 63 #define LINE_VALID_ON_STATUS_VALID_BIT          BIT(7)
 64 #define START_TX_BIT                            BIT(8)
 65 #define CABLE_THROTTLE_ENABLE_BIT               BIT(9)
 66 #define TEST_MODE_ENABLE_BIT                    BIT(31)
 67 #define BOARD_STATUS_REG                        0x08
 68 #define COMMAND_LINE_STATUS_MASK                (0x7f << 0)
 69 #define TX_IN_PROGRESS_BIT                      BIT(7)
 70 #define TX_NOT_EMPTY_BIT                        BIT(8)
 71 #define TX_NOT_ALMOST_EMPTY_BIT                 BIT(9)
 72 #define TX_NOT_ALMOST_FULL_BIT                  BIT(10)
 73 #define TX_NOT_FULL_BIT                         BIT(11)
 74 #define RX_NOT_EMPTY_BIT                        BIT(12)
 75 #define RX_NOT_ALMOST_EMPTY_BIT                 BIT(13)
 76 #define RX_NOT_ALMOST_FULL_BIT                  BIT(14)
 77 #define RX_NOT_FULL_BIT                         BIT(15)
 78 #define BOARD_JUMPER0_INSTALLED_BIT             BIT(16)
 79 #define BOARD_JUMPER1_INSTALLED_BIT             BIT(17)
 80 #define TX_OVERRUN_BIT                          BIT(21)
 81 #define RX_UNDERRUN_BIT                         BIT(22)
 82 #define RX_OVERRUN_BIT                          BIT(23)
 83 #define TX_PROG_ALMOST_REG                      0x0c
 84 #define RX_PROG_ALMOST_REG                      0x10
 85 #define ALMOST_EMPTY_BITS(x)                    (((x) & 0xffff) << 0)
 86 #define ALMOST_FULL_BITS(x)                     (((x) & 0xff) << 16)
 87 #define FEATURES_REG                            0x14
 88 #define FIFO_SIZE_PRESENT_BIT                   BIT(0)
 89 #define FIFO_WORDS_PRESENT_BIT                  BIT(1)
 90 #define LEVEL_EDGE_INTERRUPTS_PRESENT_BIT       BIT(2)
 91 #define GPIO_SUPPORTED_BIT                      BIT(3)
 92 #define PLX_DMA_CH1_SUPPORTED_BIT               BIT(4)
 93 #define OVERRUN_UNDERRUN_SUPPORTED_BIT          BIT(5)
 94 #define FIFO_REG                                0x18
 95 #define TX_STATUS_COUNT_REG                     0x1c
 96 #define TX_LINE_VALID_COUNT_REG                 0x20,
 97 #define TX_LINE_INVALID_COUNT_REG               0x24
 98 #define RX_STATUS_COUNT_REG                     0x28
 99 #define RX_LINE_COUNT_REG                       0x2c
100 #define INTERRUPT_CONTROL_REG                   0x30
101 #define FRAME_VALID_START_INTR                  BIT(0)
102 #define FRAME_VALID_END_INTR                    BIT(1)
103 #define TX_FIFO_EMPTY_INTR                      BIT(8)
104 #define TX_FIFO_ALMOST_EMPTY_INTR               BIT(9)
105 #define TX_FIFO_ALMOST_FULL_INTR                BIT(10)
106 #define TX_FIFO_FULL_INTR                       BIT(11)
107 #define RX_EMPTY_INTR                           BIT(12)
108 #define RX_ALMOST_EMPTY_INTR                    BIT(13)
109 #define RX_ALMOST_FULL_INTR                     BIT(14)
110 #define RX_FULL_INTR                            BIT(15)
111 #define INTERRUPT_STATUS_REG                    0x34
112 #define TX_CLOCK_DIVIDER_REG                    0x38
113 #define TX_FIFO_SIZE_REG                        0x40
114 #define RX_FIFO_SIZE_REG                        0x44
115 #define FIFO_SIZE_MASK                          (0xfffff << 0)
116 #define TX_FIFO_WORDS_REG                       0x48
117 #define RX_FIFO_WORDS_REG                       0x4c
118 #define INTERRUPT_EDGE_LEVEL_REG                0x50
119 #define INTERRUPT_POLARITY_REG                  0x54
120 
121 #define TIMER_BASE                              50      /* 20MHz master clock */
122 #define DMA_BUFFER_SIZE                         0x10000
123 #define NUM_DMA_BUFFERS                         4
124 #define NUM_DMA_DESCRIPTORS                     256
125 
126 struct hpdi_private {
127         void __iomem *plx9080_mmio;
128         u32 *dio_buffer[NUM_DMA_BUFFERS];       /* dma buffers */
129         /* physical addresses of dma buffers */
130         dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
131         /*
132          * array of dma descriptors read by plx9080, allocated to get proper
133          * alignment
134          */
135         struct plx_dma_desc *dma_desc;
136         /* physical address of dma descriptor array */
137         dma_addr_t dma_desc_phys_addr;
138         unsigned int num_dma_descriptors;
139         /* pointer to start of buffers indexed by descriptor */
140         u32 *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
141         /* index of the dma descriptor that is currently being used */
142         unsigned int dma_desc_index;
143         unsigned int tx_fifo_size;
144         unsigned int rx_fifo_size;
145         unsigned long dio_count;
146         /* number of bytes at which to generate COMEDI_CB_BLOCK events */
147         unsigned int block_size;
148 };
149 
150 static void gsc_hpdi_drain_dma(struct comedi_device *dev, unsigned int channel)
151 {
152         struct hpdi_private *devpriv = dev->private;
153         struct comedi_subdevice *s = dev->read_subdev;
154         struct comedi_cmd *cmd = &s->async->cmd;
155         unsigned int idx;
156         unsigned int start;
157         unsigned int desc;
158         unsigned int size;
159         unsigned int next;
160 
161         next = readl(devpriv->plx9080_mmio + PLX_REG_DMAPADR(channel));
162 
163         idx = devpriv->dma_desc_index;
164         start = le32_to_cpu(devpriv->dma_desc[idx].pci_start_addr);
165         /* loop until we have read all the full buffers */
166         for (desc = 0; (next < start || next >= start + devpriv->block_size) &&
167              desc < devpriv->num_dma_descriptors; desc++) {
168                 /* transfer data from dma buffer to comedi buffer */
169                 size = devpriv->block_size / sizeof(u32);
170                 if (cmd->stop_src == TRIG_COUNT) {
171                         if (size > devpriv->dio_count)
172                                 size = devpriv->dio_count;
173                         devpriv->dio_count -= size;
174                 }
175                 comedi_buf_write_samples(s, devpriv->desc_dio_buffer[idx],
176                                          size);
177                 idx++;
178                 idx %= devpriv->num_dma_descriptors;
179                 start = le32_to_cpu(devpriv->dma_desc[idx].pci_start_addr);
180 
181                 devpriv->dma_desc_index = idx;
182         }
183         /* XXX check for buffer overrun somehow */
184 }
185 
186 static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
187 {
188         struct comedi_device *dev = d;
189         struct hpdi_private *devpriv = dev->private;
190         struct comedi_subdevice *s = dev->read_subdev;
191         struct comedi_async *async = s->async;
192         u32 hpdi_intr_status, hpdi_board_status;
193         u32 plx_status;
194         u32 plx_bits;
195         u8 dma0_status, dma1_status;
196         unsigned long flags;
197 
198         if (!dev->attached)
199                 return IRQ_NONE;
200 
201         plx_status = readl(devpriv->plx9080_mmio + PLX_REG_INTCSR);
202         if ((plx_status &
203              (PLX_INTCSR_DMA0IA | PLX_INTCSR_DMA1IA | PLX_INTCSR_PLIA)) == 0)
204                 return IRQ_NONE;
205 
206         hpdi_intr_status = readl(dev->mmio + INTERRUPT_STATUS_REG);
207         hpdi_board_status = readl(dev->mmio + BOARD_STATUS_REG);
208 
209         if (hpdi_intr_status)
210                 writel(hpdi_intr_status, dev->mmio + INTERRUPT_STATUS_REG);
211 
212         /* spin lock makes sure no one else changes plx dma control reg */
213         spin_lock_irqsave(&dev->spinlock, flags);
214         dma0_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR0);
215         if (plx_status & PLX_INTCSR_DMA0IA) {
216                 /* dma chan 0 interrupt */
217                 writeb((dma0_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR,
218                        devpriv->plx9080_mmio + PLX_REG_DMACSR0);
219 
220                 if (dma0_status & PLX_DMACSR_ENABLE)
221                         gsc_hpdi_drain_dma(dev, 0);
222         }
223         spin_unlock_irqrestore(&dev->spinlock, flags);
224 
225         /* spin lock makes sure no one else changes plx dma control reg */
226         spin_lock_irqsave(&dev->spinlock, flags);
227         dma1_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR1);
228         if (plx_status & PLX_INTCSR_DMA1IA) {
229                 /* XXX */ /* dma chan 1 interrupt */
230                 writeb((dma1_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR,
231                        devpriv->plx9080_mmio + PLX_REG_DMACSR1);
232         }
233         spin_unlock_irqrestore(&dev->spinlock, flags);
234 
235         /* clear possible plx9080 interrupt sources */
236         if (plx_status & PLX_INTCSR_LDBIA) {
237                 /* clear local doorbell interrupt */
238                 plx_bits = readl(devpriv->plx9080_mmio + PLX_REG_L2PDBELL);
239                 writel(plx_bits, devpriv->plx9080_mmio + PLX_REG_L2PDBELL);
240         }
241 
242         if (hpdi_board_status & RX_OVERRUN_BIT) {
243                 dev_err(dev->class_dev, "rx fifo overrun\n");
244                 async->events |= COMEDI_CB_ERROR;
245         }
246 
247         if (hpdi_board_status & RX_UNDERRUN_BIT) {
248                 dev_err(dev->class_dev, "rx fifo underrun\n");
249                 async->events |= COMEDI_CB_ERROR;
250         }
251 
252         if (devpriv->dio_count == 0)
253                 async->events |= COMEDI_CB_EOA;
254 
255         comedi_handle_events(dev, s);
256 
257         return IRQ_HANDLED;
258 }
259 
260 static void gsc_hpdi_abort_dma(struct comedi_device *dev, unsigned int channel)
261 {
262         struct hpdi_private *devpriv = dev->private;
263         unsigned long flags;
264 
265         /* spinlock for plx dma control/status reg */
266         spin_lock_irqsave(&dev->spinlock, flags);
267 
268         plx9080_abort_dma(devpriv->plx9080_mmio, channel);
269 
270         spin_unlock_irqrestore(&dev->spinlock, flags);
271 }
272 
273 static int gsc_hpdi_cancel(struct comedi_device *dev,
274                            struct comedi_subdevice *s)
275 {
276         writel(0, dev->mmio + BOARD_CONTROL_REG);
277         writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
278 
279         gsc_hpdi_abort_dma(dev, 0);
280 
281         return 0;
282 }
283 
284 static int gsc_hpdi_cmd(struct comedi_device *dev,
285                         struct comedi_subdevice *s)
286 {
287         struct hpdi_private *devpriv = dev->private;
288         struct comedi_async *async = s->async;
289         struct comedi_cmd *cmd = &async->cmd;
290         unsigned long flags;
291         u32 bits;
292 
293         if (s->io_bits)
294                 return -EINVAL;
295 
296         writel(RX_FIFO_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
297 
298         gsc_hpdi_abort_dma(dev, 0);
299 
300         devpriv->dma_desc_index = 0;
301 
302         /*
303          * These register are supposedly unused during chained dma,
304          * but I have found that left over values from last operation
305          * occasionally cause problems with transfer of first dma
306          * block.  Initializing them to zero seems to fix the problem.
307          */
308         writel(0, devpriv->plx9080_mmio + PLX_REG_DMASIZ0);
309         writel(0, devpriv->plx9080_mmio + PLX_REG_DMAPADR0);
310         writel(0, devpriv->plx9080_mmio + PLX_REG_DMALADR0);
311 
312         /* give location of first dma descriptor */
313         bits = devpriv->dma_desc_phys_addr | PLX_DMADPR_DESCPCI |
314                PLX_DMADPR_TCINTR | PLX_DMADPR_XFERL2P;
315         writel(bits, devpriv->plx9080_mmio + PLX_REG_DMADPR0);
316 
317         /* enable dma transfer */
318         spin_lock_irqsave(&dev->spinlock, flags);
319         writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_START | PLX_DMACSR_CLEARINTR,
320                devpriv->plx9080_mmio + PLX_REG_DMACSR0);
321         spin_unlock_irqrestore(&dev->spinlock, flags);
322 
323         if (cmd->stop_src == TRIG_COUNT)
324                 devpriv->dio_count = cmd->stop_arg;
325         else
326                 devpriv->dio_count = 1;
327 
328         /* clear over/under run status flags */
329         writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT, dev->mmio + BOARD_STATUS_REG);
330 
331         /* enable interrupts */
332         writel(RX_FULL_INTR, dev->mmio + INTERRUPT_CONTROL_REG);
333 
334         writel(RX_ENABLE_BIT, dev->mmio + BOARD_CONTROL_REG);
335 
336         return 0;
337 }
338 
339 static int gsc_hpdi_check_chanlist(struct comedi_device *dev,
340                                    struct comedi_subdevice *s,
341                                    struct comedi_cmd *cmd)
342 {
343         int i;
344 
345         for (i = 0; i < cmd->chanlist_len; i++) {
346                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
347 
348                 if (chan != i) {
349                         dev_dbg(dev->class_dev,
350                                 "chanlist must be ch 0 to 31 in order\n");
351                         return -EINVAL;
352                 }
353         }
354 
355         return 0;
356 }
357 
358 static int gsc_hpdi_cmd_test(struct comedi_device *dev,
359                              struct comedi_subdevice *s,
360                              struct comedi_cmd *cmd)
361 {
362         int err = 0;
363 
364         if (s->io_bits)
365                 return -EINVAL;
366 
367         /* Step 1 : check if triggers are trivially valid */
368 
369         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
370         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
371         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
372         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
373         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
374 
375         if (err)
376                 return 1;
377 
378         /* Step 2a : make sure trigger sources are unique */
379 
380         err |= comedi_check_trigger_is_unique(cmd->stop_src);
381 
382         /* Step 2b : and mutually compatible */
383 
384         if (err)
385                 return 2;
386 
387         /* Step 3: check if arguments are trivially valid */
388 
389         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
390 
391         if (!cmd->chanlist_len || !cmd->chanlist) {
392                 cmd->chanlist_len = 32;
393                 err |= -EINVAL;
394         }
395         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
396                                            cmd->chanlist_len);
397 
398         if (cmd->stop_src == TRIG_COUNT)
399                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
400         else    /* TRIG_NONE */
401                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
402 
403         if (err)
404                 return 3;
405 
406         /* Step 4: fix up any arguments */
407 
408         /* Step 5: check channel list if it exists */
409 
410         if (cmd->chanlist && cmd->chanlist_len > 0)
411                 err |= gsc_hpdi_check_chanlist(dev, s, cmd);
412 
413         if (err)
414                 return 5;
415 
416         return 0;
417 }
418 
419 /* setup dma descriptors so a link completes every 'len' bytes */
420 static int gsc_hpdi_setup_dma_descriptors(struct comedi_device *dev,
421                                           unsigned int len)
422 {
423         struct hpdi_private *devpriv = dev->private;
424         dma_addr_t phys_addr = devpriv->dma_desc_phys_addr;
425         u32 next_bits = PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR |
426                         PLX_DMADPR_XFERL2P;
427         unsigned int offset = 0;
428         unsigned int idx = 0;
429         unsigned int i;
430 
431         if (len > DMA_BUFFER_SIZE)
432                 len = DMA_BUFFER_SIZE;
433         len -= len % sizeof(u32);
434         if (len == 0)
435                 return -EINVAL;
436 
437         for (i = 0; i < NUM_DMA_DESCRIPTORS && idx < NUM_DMA_BUFFERS; i++) {
438                 devpriv->dma_desc[i].pci_start_addr =
439                     cpu_to_le32(devpriv->dio_buffer_phys_addr[idx] + offset);
440                 devpriv->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
441                 devpriv->dma_desc[i].transfer_size = cpu_to_le32(len);
442                 devpriv->dma_desc[i].next = cpu_to_le32((phys_addr +
443                         (i + 1) * sizeof(devpriv->dma_desc[0])) | next_bits);
444 
445                 devpriv->desc_dio_buffer[i] = devpriv->dio_buffer[idx] +
446                                               (offset / sizeof(u32));
447 
448                 offset += len;
449                 if (len + offset > DMA_BUFFER_SIZE) {
450                         offset = 0;
451                         idx++;
452                 }
453         }
454         devpriv->num_dma_descriptors = i;
455         /* fix last descriptor to point back to first */
456         devpriv->dma_desc[i - 1].next = cpu_to_le32(phys_addr | next_bits);
457 
458         devpriv->block_size = len;
459 
460         return len;
461 }
462 
463 static int gsc_hpdi_dio_insn_config(struct comedi_device *dev,
464                                     struct comedi_subdevice *s,
465                                     struct comedi_insn *insn,
466                                     unsigned int *data)
467 {
468         int ret;
469 
470         switch (data[0]) {
471         case INSN_CONFIG_BLOCK_SIZE:
472                 ret = gsc_hpdi_setup_dma_descriptors(dev, data[1]);
473                 if (ret)
474                         return ret;
475 
476                 data[1] = ret;
477                 break;
478         default:
479                 ret = comedi_dio_insn_config(dev, s, insn, data, 0xffffffff);
480                 if (ret)
481                         return ret;
482                 break;
483         }
484 
485         return insn->n;
486 }
487 
488 static void gsc_hpdi_free_dma(struct comedi_device *dev)
489 {
490         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
491         struct hpdi_private *devpriv = dev->private;
492         int i;
493 
494         if (!devpriv)
495                 return;
496 
497         /* free pci dma buffers */
498         for (i = 0; i < NUM_DMA_BUFFERS; i++) {
499                 if (devpriv->dio_buffer[i])
500                         dma_free_coherent(&pcidev->dev,
501                                           DMA_BUFFER_SIZE,
502                                           devpriv->dio_buffer[i],
503                                           devpriv->dio_buffer_phys_addr[i]);
504         }
505         /* free dma descriptors */
506         if (devpriv->dma_desc)
507                 dma_free_coherent(&pcidev->dev,
508                                   sizeof(struct plx_dma_desc) *
509                                   NUM_DMA_DESCRIPTORS,
510                                   devpriv->dma_desc,
511                                   devpriv->dma_desc_phys_addr);
512 }
513 
514 static int gsc_hpdi_init(struct comedi_device *dev)
515 {
516         struct hpdi_private *devpriv = dev->private;
517         u32 plx_intcsr_bits;
518 
519         /* wait 10usec after reset before accessing fifos */
520         writel(BOARD_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
521         usleep_range(10, 1000);
522 
523         writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
524                dev->mmio + RX_PROG_ALMOST_REG);
525         writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
526                dev->mmio + TX_PROG_ALMOST_REG);
527 
528         devpriv->tx_fifo_size = readl(dev->mmio + TX_FIFO_SIZE_REG) &
529                                 FIFO_SIZE_MASK;
530         devpriv->rx_fifo_size = readl(dev->mmio + RX_FIFO_SIZE_REG) &
531                                 FIFO_SIZE_MASK;
532 
533         writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
534 
535         /* enable interrupts */
536         plx_intcsr_bits =
537             PLX_INTCSR_LSEABORTEN | PLX_INTCSR_LSEPARITYEN | PLX_INTCSR_PIEN |
538             PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN |
539             PLX_INTCSR_DMA0IEN;
540         writel(plx_intcsr_bits, devpriv->plx9080_mmio + PLX_REG_INTCSR);
541 
542         return 0;
543 }
544 
545 static void gsc_hpdi_init_plx9080(struct comedi_device *dev)
546 {
547         struct hpdi_private *devpriv = dev->private;
548         u32 bits;
549         void __iomem *plx_iobase = devpriv->plx9080_mmio;
550 
551 #ifdef __BIG_ENDIAN
552         bits = PLX_BIGEND_DMA0 | PLX_BIGEND_DMA1;
553 #else
554         bits = 0;
555 #endif
556         writel(bits, devpriv->plx9080_mmio + PLX_REG_BIGEND);
557 
558         writel(0, devpriv->plx9080_mmio + PLX_REG_INTCSR);
559 
560         gsc_hpdi_abort_dma(dev, 0);
561         gsc_hpdi_abort_dma(dev, 1);
562 
563         /* configure dma0 mode */
564         bits = 0;
565         /* enable ready input */
566         bits |= PLX_DMAMODE_READYIEN;
567         /* enable dma chaining */
568         bits |= PLX_DMAMODE_CHAINEN;
569         /*
570          * enable interrupt on dma done
571          * (probably don't need this, since chain never finishes)
572          */
573         bits |= PLX_DMAMODE_DONEIEN;
574         /*
575          * don't increment local address during transfers
576          * (we are transferring from a fixed fifo register)
577          */
578         bits |= PLX_DMAMODE_LACONST;
579         /* route dma interrupt to pci bus */
580         bits |= PLX_DMAMODE_INTRPCI;
581         /* enable demand mode */
582         bits |= PLX_DMAMODE_DEMAND;
583         /* enable local burst mode */
584         bits |= PLX_DMAMODE_BURSTEN;
585         bits |= PLX_DMAMODE_WIDTH32;
586         writel(bits, plx_iobase + PLX_REG_DMAMODE0);
587 }
588 
589 static int gsc_hpdi_auto_attach(struct comedi_device *dev,
590                                 unsigned long context_unused)
591 {
592         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
593         struct hpdi_private *devpriv;
594         struct comedi_subdevice *s;
595         int i;
596         int retval;
597 
598         dev->board_name = "pci-hpdi32";
599 
600         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
601         if (!devpriv)
602                 return -ENOMEM;
603 
604         retval = comedi_pci_enable(dev);
605         if (retval)
606                 return retval;
607         pci_set_master(pcidev);
608 
609         devpriv->plx9080_mmio = pci_ioremap_bar(pcidev, 0);
610         dev->mmio = pci_ioremap_bar(pcidev, 2);
611         if (!devpriv->plx9080_mmio || !dev->mmio) {
612                 dev_warn(dev->class_dev, "failed to remap io memory\n");
613                 return -ENOMEM;
614         }
615 
616         gsc_hpdi_init_plx9080(dev);
617 
618         /* get irq */
619         if (request_irq(pcidev->irq, gsc_hpdi_interrupt, IRQF_SHARED,
620                         dev->board_name, dev)) {
621                 dev_warn(dev->class_dev,
622                          "unable to allocate irq %u\n", pcidev->irq);
623                 return -EINVAL;
624         }
625         dev->irq = pcidev->irq;
626 
627         dev_dbg(dev->class_dev, " irq %u\n", dev->irq);
628 
629         /* allocate pci dma buffers */
630         for (i = 0; i < NUM_DMA_BUFFERS; i++) {
631                 devpriv->dio_buffer[i] =
632                     dma_alloc_coherent(&pcidev->dev, DMA_BUFFER_SIZE,
633                                        &devpriv->dio_buffer_phys_addr[i],
634                                        GFP_KERNEL);
635         }
636         /* allocate dma descriptors */
637         devpriv->dma_desc = dma_alloc_coherent(&pcidev->dev,
638                                                sizeof(struct plx_dma_desc) *
639                                                NUM_DMA_DESCRIPTORS,
640                                                &devpriv->dma_desc_phys_addr,
641                                                GFP_KERNEL);
642         if (devpriv->dma_desc_phys_addr & 0xf) {
643                 dev_warn(dev->class_dev,
644                          " dma descriptors not quad-word aligned (bug)\n");
645                 return -EIO;
646         }
647 
648         retval = gsc_hpdi_setup_dma_descriptors(dev, 0x1000);
649         if (retval < 0)
650                 return retval;
651 
652         retval = comedi_alloc_subdevices(dev, 1);
653         if (retval)
654                 return retval;
655 
656         /* Digital I/O subdevice */
657         s = &dev->subdevices[0];
658         dev->read_subdev = s;
659         s->type         = COMEDI_SUBD_DIO;
660         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL |
661                           SDF_CMD_READ;
662         s->n_chan       = 32;
663         s->len_chanlist = 32;
664         s->maxdata      = 1;
665         s->range_table  = &range_digital;
666         s->insn_config  = gsc_hpdi_dio_insn_config;
667         s->do_cmd       = gsc_hpdi_cmd;
668         s->do_cmdtest   = gsc_hpdi_cmd_test;
669         s->cancel       = gsc_hpdi_cancel;
670 
671         return gsc_hpdi_init(dev);
672 }
673 
674 static void gsc_hpdi_detach(struct comedi_device *dev)
675 {
676         struct hpdi_private *devpriv = dev->private;
677 
678         if (dev->irq)
679                 free_irq(dev->irq, dev);
680         if (devpriv) {
681                 if (devpriv->plx9080_mmio) {
682                         writel(0, devpriv->plx9080_mmio + PLX_REG_INTCSR);
683                         iounmap(devpriv->plx9080_mmio);
684                 }
685                 if (dev->mmio)
686                         iounmap(dev->mmio);
687         }
688         comedi_pci_disable(dev);
689         gsc_hpdi_free_dma(dev);
690 }
691 
692 static struct comedi_driver gsc_hpdi_driver = {
693         .driver_name    = "gsc_hpdi",
694         .module         = THIS_MODULE,
695         .auto_attach    = gsc_hpdi_auto_attach,
696         .detach         = gsc_hpdi_detach,
697 };
698 
699 static int gsc_hpdi_pci_probe(struct pci_dev *dev,
700                               const struct pci_device_id *id)
701 {
702         return comedi_pci_auto_config(dev, &gsc_hpdi_driver, id->driver_data);
703 }
704 
705 static const struct pci_device_id gsc_hpdi_pci_table[] = {
706         { PCI_DEVICE_SUB(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080,
707                          PCI_VENDOR_ID_PLX, 0x2400) },
708         { 0 }
709 };
710 MODULE_DEVICE_TABLE(pci, gsc_hpdi_pci_table);
711 
712 static struct pci_driver gsc_hpdi_pci_driver = {
713         .name           = "gsc_hpdi",
714         .id_table       = gsc_hpdi_pci_table,
715         .probe          = gsc_hpdi_pci_probe,
716         .remove         = comedi_pci_auto_unconfig,
717 };
718 module_comedi_pci_driver(gsc_hpdi_driver, gsc_hpdi_pci_driver);
719 
720 MODULE_AUTHOR("Comedi http://www.comedi.org");
721 MODULE_DESCRIPTION("Comedi driver for General Standards PCI-HPDI32/PMC-HPDI32");
722 MODULE_LICENSE("GPL");
723 

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