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Linux/drivers/staging/comedi/drivers/cb_pcidas64.c

  1 /*
  2     comedi/drivers/cb_pcidas64.c
  3     This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
  4     64xx, 60xx, and 4020 cards.
  5 
  6     Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
  7     Copyright (C) 2001, 2002 Frank Mori Hess
  8 
  9     Thanks also go to the following people:
 10 
 11     Steve Rosenbluth, for providing the source code for
 12     his pci-das6402 driver, and source code for working QNX pci-6402
 13     drivers by Greg Laird and Mariusz Bogacz.  None of the code was
 14     used directly here, but it was useful as an additional source of
 15     documentation on how to program the boards.
 16 
 17     John Sims, for much testing and feedback on pcidas-4020 support.
 18 
 19     COMEDI - Linux Control and Measurement Device Interface
 20     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
 21 
 22     This program is free software; you can redistribute it and/or modify
 23     it under the terms of the GNU General Public License as published by
 24     the Free Software Foundation; either version 2 of the License, or
 25     (at your option) any later version.
 26 
 27     This program is distributed in the hope that it will be useful,
 28     but WITHOUT ANY WARRANTY; without even the implied warranty of
 29     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 30     GNU General Public License for more details.
 31 */
 32 
 33 /*
 34  * Driver: cb_pcidas64
 35  * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
 36  *   with the PLX 9080 PCI controller
 37  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
 38  * Status: works
 39  * Updated: Fri, 02 Nov 2012 18:58:55 +0000
 40  * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
 41  *   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
 42  *   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
 43  *   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
 44  *   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
 45  *   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
 46  *   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
 47  *   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
 48  *   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
 49  *
 50  * Configuration options:
 51  *   None.
 52  *
 53  * Manual attachment of PCI cards with the comedi_config utility is not
 54  * supported by this driver; they are attached automatically.
 55  *
 56  * These boards may be autocalibrated with the comedi_calibrate utility.
 57  *
 58  * To select the bnc trigger input on the 4020 (instead of the dio input),
 59  * specify a nonzero channel in the chanspec.  If you wish to use an external
 60  * master clock on the 4020, you may do so by setting the scan_begin_src
 61  * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
 62  * to configure the divisor to use for the external clock.
 63  *
 64  * Some devices are not identified because the PCI device IDs are not yet
 65  * known. If you have such a board, please let the maintainers know.
 66  */
 67 
 68 /*
 69 
 70 TODO:
 71         make it return error if user attempts an ai command that uses the
 72         external queue, and an ao command simultaneously user counter subdevice
 73         there are a number of boards this driver will support when they are
 74         fully released, but does not yet since the pci device id numbers
 75         are not yet available.
 76 
 77         support prescaled 100khz clock for slow pacing (not available on 6000
 78         series?)
 79 
 80         make ao fifo size adjustable like ai fifo
 81 */
 82 
 83 #include <linux/module.h>
 84 #include <linux/delay.h>
 85 #include <linux/interrupt.h>
 86 
 87 #include "../comedi_pci.h"
 88 
 89 #include "8255.h"
 90 #include "plx9080.h"
 91 
 92 #define TIMER_BASE 25           /*  40MHz master clock */
 93 /* 100kHz 'prescaled' clock for slow acquisition,
 94  * maybe I'll support this someday */
 95 #define PRESCALED_TIMER_BASE    10000
 96 #define DMA_BUFFER_SIZE 0x1000
 97 
 98 /* maximum value that can be loaded into board's 24-bit counters*/
 99 static const int max_counter_value = 0xffffff;
100 
101 /* PCI-DAS64xxx base addresses */
102 
103 /* devpriv->main_iobase registers */
104 enum write_only_registers {
105         INTR_ENABLE_REG = 0x0,  /*  interrupt enable register */
106         HW_CONFIG_REG = 0x2,    /*  hardware config register */
107         DAQ_SYNC_REG = 0xc,
108         DAQ_ATRIG_LOW_4020_REG = 0xc,
109         ADC_CONTROL0_REG = 0x10,        /*  adc control register 0 */
110         ADC_CONTROL1_REG = 0x12,        /*  adc control register 1 */
111         CALIBRATION_REG = 0x14,
112         /*  lower 16 bits of adc sample interval counter */
113         ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
114         /*  upper 8 bits of adc sample interval counter */
115         ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
116         /*  lower 16 bits of delay interval counter */
117         ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
118         /*  upper 8 bits of delay interval counter */
119         ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
120         /*  lower 16 bits of hardware conversion/scan counter */
121         ADC_COUNT_LOWER_REG = 0x1e,
122         /*  upper 8 bits of hardware conversion/scan counter */
123         ADC_COUNT_UPPER_REG = 0x20,
124         ADC_START_REG = 0x22,   /*  software trigger to start acquisition */
125         ADC_CONVERT_REG = 0x24, /*  initiates single conversion */
126         ADC_QUEUE_CLEAR_REG = 0x26,     /*  clears adc queue */
127         ADC_QUEUE_LOAD_REG = 0x28,      /*  loads adc queue */
128         ADC_BUFFER_CLEAR_REG = 0x2a,
129         /*  high channel for internal queue, use adc_chan_bits() inline above */
130         ADC_QUEUE_HIGH_REG = 0x2c,
131         DAC_CONTROL0_REG = 0x50,        /*  dac control register 0 */
132         DAC_CONTROL1_REG = 0x52,        /*  dac control register 0 */
133         /*  lower 16 bits of dac sample interval counter */
134         DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
135         /*  upper 8 bits of dac sample interval counter */
136         DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
137         DAC_SELECT_REG = 0x60,
138         DAC_START_REG = 0x64,
139         DAC_BUFFER_CLEAR_REG = 0x66,    /*  clear dac buffer */
140 };
141 
142 static inline unsigned int dac_convert_reg(unsigned int channel)
143 {
144         return 0x70 + (2 * (channel & 0x1));
145 }
146 
147 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
148 {
149         return 0x70 + (4 * (channel & 0x1));
150 }
151 
152 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
153 {
154         return 0x72 + (4 * (channel & 0x1));
155 }
156 
157 enum read_only_registers {
158         /*
159          * hardware status register,
160          * reading this apparently clears pending interrupts as well
161          */
162         HW_STATUS_REG = 0x0,
163         PIPE1_READ_REG = 0x4,
164         ADC_READ_PNTR_REG = 0x8,
165         LOWER_XFER_REG = 0x10,
166         ADC_WRITE_PNTR_REG = 0xc,
167         PREPOST_REG = 0x14,
168 };
169 
170 enum read_write_registers {
171         I8255_4020_REG = 0x48,  /*  8255 offset, for 4020 only */
172         /*  external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
173         ADC_QUEUE_FIFO_REG = 0x100,
174         ADC_FIFO_REG = 0x200,   /* adc data fifo */
175         /* dac data fifo, has weird interactions with external channel queue */
176         DAC_FIFO_REG = 0x300,
177 };
178 
179 /* dev->mmio registers */
180 enum dio_counter_registers {
181         DIO_8255_OFFSET = 0x0,
182         DO_REG = 0x20,
183         DI_REG = 0x28,
184         DIO_DIRECTION_60XX_REG = 0x40,
185         DIO_DATA_60XX_REG = 0x48,
186 };
187 
188 /* bit definitions for write-only registers */
189 
190 enum intr_enable_contents {
191         ADC_INTR_SRC_MASK = 0x3,        /*  adc interrupt source mask */
192         ADC_INTR_QFULL_BITS = 0x0,      /*  interrupt fifo quarter full */
193         ADC_INTR_EOC_BITS = 0x1,        /*  interrupt end of conversion */
194         ADC_INTR_EOSCAN_BITS = 0x2,     /*  interrupt end of scan */
195         ADC_INTR_EOSEQ_BITS = 0x3,      /*  interrupt end of sequence mask */
196         EN_ADC_INTR_SRC_BIT = 0x4,      /*  enable adc interrupt source */
197         EN_ADC_DONE_INTR_BIT = 0x8,     /*  enable adc acquisition done intr */
198         DAC_INTR_SRC_MASK = 0x30,
199         DAC_INTR_QEMPTY_BITS = 0x0,
200         DAC_INTR_HIGH_CHAN_BITS = 0x10,
201         EN_DAC_INTR_SRC_BIT = 0x40,     /*  enable dac interrupt source */
202         EN_DAC_DONE_INTR_BIT = 0x80,
203         EN_ADC_ACTIVE_INTR_BIT = 0x200, /*  enable adc active interrupt */
204         EN_ADC_STOP_INTR_BIT = 0x400,   /*  enable adc stop trigger interrupt */
205         EN_DAC_ACTIVE_INTR_BIT = 0x800, /*  enable dac active interrupt */
206         EN_DAC_UNDERRUN_BIT = 0x4000,   /*  enable dac underrun status bit */
207         EN_ADC_OVERRUN_BIT = 0x8000,    /*  enable adc overrun status bit */
208 };
209 
210 enum hw_config_contents {
211         MASTER_CLOCK_4020_MASK = 0x3,   /*  master clock source mask for 4020 */
212         INTERNAL_CLOCK_4020_BITS = 0x1, /*  use 40 MHz internal master clock */
213         BNC_CLOCK_4020_BITS = 0x2,      /*  use BNC input for master clock */
214         EXT_CLOCK_4020_BITS = 0x3,      /*  use dio input for master clock */
215         EXT_QUEUE_BIT = 0x200,          /*  use external channel/gain queue */
216         /*  use 225 nanosec strobe when loading dac instead of 50 nanosec */
217         SLOW_DAC_BIT = 0x400,
218         /*  bit with unknown function yet given as default value in pci-das64
219          *  manual */
220         HW_CONFIG_DUMMY_BITS = 0x2000,
221         /*  bit selects channels 1/0 for analog input/output, otherwise 0/1 */
222         DMA_CH_SELECT_BIT = 0x8000,
223         FIFO_SIZE_REG = 0x4,            /*  allows adjustment of fifo sizes */
224         DAC_FIFO_SIZE_MASK = 0xff00,    /*  bits that set dac fifo size */
225         DAC_FIFO_BITS = 0xf800,         /*  8k sample ao fifo */
226 };
227 #define DAC_FIFO_SIZE 0x2000
228 
229 enum daq_atrig_low_4020_contents {
230         /*  use trig/ext clk bnc input for analog gate signal */
231         EXT_AGATE_BNC_BIT = 0x8000,
232         /*  use trig/ext clk bnc input for external stop trigger signal */
233         EXT_STOP_TRIG_BNC_BIT = 0x4000,
234         /*  use trig/ext clk bnc input for external start trigger signal */
235         EXT_START_TRIG_BNC_BIT = 0x2000,
236 };
237 
238 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
239 {
240         return threshold & 0xfff;
241 }
242 
243 enum adc_control0_contents {
244         ADC_GATE_SRC_MASK = 0x3,        /*  bits that select gate */
245         ADC_SOFT_GATE_BITS = 0x1,       /*  software gate */
246         ADC_EXT_GATE_BITS = 0x2,        /*  external digital gate */
247         ADC_ANALOG_GATE_BITS = 0x3,     /*  analog level gate */
248         /*  level-sensitive gate (for digital) */
249         ADC_GATE_LEVEL_BIT = 0x4,
250         ADC_GATE_POLARITY_BIT = 0x8,    /*  gate active low */
251         ADC_START_TRIG_SOFT_BITS = 0x10,
252         ADC_START_TRIG_EXT_BITS = 0x20,
253         ADC_START_TRIG_ANALOG_BITS = 0x30,
254         ADC_START_TRIG_MASK = 0x30,
255         ADC_START_TRIG_FALLING_BIT = 0x40,      /*  trig 1 uses falling edge */
256         /*  external pacing uses falling edge */
257         ADC_EXT_CONV_FALLING_BIT = 0x800,
258         /*  enable hardware scan counter */
259         ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
260         ADC_DMA_DISABLE_BIT = 0x4000,   /*  disables dma */
261         ADC_ENABLE_BIT = 0x8000,        /*  master adc enable */
262 };
263 
264 enum adc_control1_contents {
265         /*  should be set for boards with > 16 channels */
266         ADC_QUEUE_CONFIG_BIT = 0x1,
267         CONVERT_POLARITY_BIT = 0x10,
268         EOC_POLARITY_BIT = 0x20,
269         ADC_SW_GATE_BIT = 0x40, /*  software gate of adc */
270         ADC_DITHER_BIT = 0x200, /*  turn on extra noise for dithering */
271         RETRIGGER_BIT = 0x800,
272         ADC_LO_CHANNEL_4020_MASK = 0x300,
273         ADC_HI_CHANNEL_4020_MASK = 0xc00,
274         TWO_CHANNEL_4020_BITS = 0x1000, /*  two channel mode for 4020 */
275         FOUR_CHANNEL_4020_BITS = 0x2000, /*  four channel mode for 4020 */
276         CHANNEL_MODE_4020_MASK = 0x3000,
277         ADC_MODE_MASK = 0xf000,
278 };
279 
280 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
281 {
282         return (channel & 0x3) << 8;
283 };
284 
285 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
286 {
287         return (channel & 0x3) << 10;
288 };
289 
290 static inline uint16_t adc_mode_bits(unsigned int mode)
291 {
292         return (mode & 0xf) << 12;
293 };
294 
295 enum calibration_contents {
296         SELECT_8800_BIT = 0x1,
297         SELECT_8402_64XX_BIT = 0x2,
298         SELECT_1590_60XX_BIT = 0x2,
299         CAL_EN_64XX_BIT = 0x40, /*  calibration enable for 64xx series */
300         SERIAL_DATA_IN_BIT = 0x80,
301         SERIAL_CLOCK_BIT = 0x100,
302         CAL_EN_60XX_BIT = 0x200, /*  calibration enable for 60xx series */
303         CAL_GAIN_BIT = 0x800,
304 };
305 
306 /*
307  * calibration sources for 6025 are:
308  *  0 : ground
309  *  1 : 10V
310  *  2 : 5V
311  *  3 : 0.5V
312  *  4 : 0.05V
313  *  5 : ground
314  *  6 : dac channel 0
315  *  7 : dac channel 1
316  */
317 
318 static inline uint16_t adc_src_bits(unsigned int source)
319 {
320         return (source & 0xf) << 3;
321 };
322 
323 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
324 {
325         return (channel & 0x3) << 8;
326 };
327 
328 enum adc_queue_load_contents {
329         UNIP_BIT = 0x800,       /*  unipolar/bipolar bit */
330         ADC_SE_DIFF_BIT = 0x1000,       /*  single-ended/ differential bit */
331         /*  non-referenced single-ended (common-mode input) */
332         ADC_COMMON_BIT = 0x2000,
333         QUEUE_EOSEQ_BIT = 0x4000,       /*  queue end of sequence */
334         QUEUE_EOSCAN_BIT = 0x8000,      /*  queue end of scan */
335 };
336 
337 static inline uint16_t adc_chan_bits(unsigned int channel)
338 {
339         return channel & 0x3f;
340 };
341 
342 enum dac_control0_contents {
343         DAC_ENABLE_BIT = 0x8000,        /*  dac controller enable bit */
344         DAC_CYCLIC_STOP_BIT = 0x4000,
345         DAC_WAVEFORM_MODE_BIT = 0x100,
346         DAC_EXT_UPDATE_FALLING_BIT = 0x80,
347         DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
348         WAVEFORM_TRIG_MASK = 0x30,
349         WAVEFORM_TRIG_DISABLED_BITS = 0x0,
350         WAVEFORM_TRIG_SOFT_BITS = 0x10,
351         WAVEFORM_TRIG_EXT_BITS = 0x20,
352         WAVEFORM_TRIG_ADC1_BITS = 0x30,
353         WAVEFORM_TRIG_FALLING_BIT = 0x8,
354         WAVEFORM_GATE_LEVEL_BIT = 0x4,
355         WAVEFORM_GATE_ENABLE_BIT = 0x2,
356         WAVEFORM_GATE_SELECT_BIT = 0x1,
357 };
358 
359 enum dac_control1_contents {
360         DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
361         DAC1_EXT_REF_BIT = 0x200,
362         DAC0_EXT_REF_BIT = 0x100,
363         DAC_OUTPUT_ENABLE_BIT = 0x80,   /*  dac output enable bit */
364         DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
365         DAC_SW_GATE_BIT = 0x20,
366         DAC1_UNIPOLAR_BIT = 0x8,
367         DAC0_UNIPOLAR_BIT = 0x2,
368 };
369 
370 /* bit definitions for read-only registers */
371 enum hw_status_contents {
372         DAC_UNDERRUN_BIT = 0x1,
373         ADC_OVERRUN_BIT = 0x2,
374         DAC_ACTIVE_BIT = 0x4,
375         ADC_ACTIVE_BIT = 0x8,
376         DAC_INTR_PENDING_BIT = 0x10,
377         ADC_INTR_PENDING_BIT = 0x20,
378         DAC_DONE_BIT = 0x40,
379         ADC_DONE_BIT = 0x80,
380         EXT_INTR_PENDING_BIT = 0x100,
381         ADC_STOP_BIT = 0x200,
382 };
383 
384 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
385 {
386         return (hw_status_bits >> 10) & 0x3;
387 };
388 
389 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
390 {
391         return (prepost_bits >> 6) & 0x3;
392 }
393 
394 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
395 {
396         return (prepost_bits >> 12) & 0x3;
397 }
398 
399 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
400 {
401         return (prepost_bits >> 14) & 0x3;
402 }
403 
404 /* I2C addresses for 4020 */
405 enum i2c_addresses {
406         RANGE_CAL_I2C_ADDR = 0x20,
407         CALDAC0_I2C_ADDR = 0xc,
408         CALDAC1_I2C_ADDR = 0xd,
409 };
410 
411 enum range_cal_i2c_contents {
412         /*  bits that set what source the adc converter measures */
413         ADC_SRC_4020_MASK = 0x70,
414         /*  make bnc trig/ext clock threshold 0V instead of 2.5V */
415         BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
416 };
417 
418 static inline uint8_t adc_src_4020_bits(unsigned int source)
419 {
420         return (source << 4) & ADC_SRC_4020_MASK;
421 };
422 
423 static inline uint8_t attenuate_bit(unsigned int channel)
424 {
425         /*  attenuate channel (+-5V input range) */
426         return 1 << (channel & 0x3);
427 };
428 
429 /* analog input ranges for 64xx boards */
430 static const struct comedi_lrange ai_ranges_64xx = {
431         8, {
432                 BIP_RANGE(10),
433                 BIP_RANGE(5),
434                 BIP_RANGE(2.5),
435                 BIP_RANGE(1.25),
436                 UNI_RANGE(10),
437                 UNI_RANGE(5),
438                 UNI_RANGE(2.5),
439                 UNI_RANGE(1.25)
440         }
441 };
442 
443 static const uint8_t ai_range_code_64xx[8] = {
444         0x0, 0x1, 0x2, 0x3,     /* bipolar 10, 5, 2,5, 1.25 */
445         0x8, 0x9, 0xa, 0xb      /* unipolar 10, 5, 2.5, 1.25 */
446 };
447 
448 /* analog input ranges for 64-Mx boards */
449 static const struct comedi_lrange ai_ranges_64_mx = {
450         7, {
451                 BIP_RANGE(5),
452                 BIP_RANGE(2.5),
453                 BIP_RANGE(1.25),
454                 BIP_RANGE(0.625),
455                 UNI_RANGE(5),
456                 UNI_RANGE(2.5),
457                 UNI_RANGE(1.25)
458         }
459 };
460 
461 static const uint8_t ai_range_code_64_mx[7] = {
462         0x0, 0x1, 0x2, 0x3,     /* bipolar 5, 2.5, 1.25, 0.625 */
463         0x9, 0xa, 0xb           /* unipolar 5, 2.5, 1.25 */
464 };
465 
466 /* analog input ranges for 60xx boards */
467 static const struct comedi_lrange ai_ranges_60xx = {
468         4, {
469                 BIP_RANGE(10),
470                 BIP_RANGE(5),
471                 BIP_RANGE(0.5),
472                 BIP_RANGE(0.05)
473         }
474 };
475 
476 static const uint8_t ai_range_code_60xx[4] = {
477         0x0, 0x1, 0x4, 0x7      /* bipolar 10, 5, 0.5, 0.05 */
478 };
479 
480 /* analog input ranges for 6030, etc boards */
481 static const struct comedi_lrange ai_ranges_6030 = {
482         14, {
483                 BIP_RANGE(10),
484                 BIP_RANGE(5),
485                 BIP_RANGE(2),
486                 BIP_RANGE(1),
487                 BIP_RANGE(0.5),
488                 BIP_RANGE(0.2),
489                 BIP_RANGE(0.1),
490                 UNI_RANGE(10),
491                 UNI_RANGE(5),
492                 UNI_RANGE(2),
493                 UNI_RANGE(1),
494                 UNI_RANGE(0.5),
495                 UNI_RANGE(0.2),
496                 UNI_RANGE(0.1)
497         }
498 };
499 
500 static const uint8_t ai_range_code_6030[14] = {
501         0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, /* bip 10, 5, 2, 1, 0.5, 0.2, 0.1 */
502         0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf  /* uni 10, 5, 2, 1, 0.5, 0.2, 0.1 */
503 };
504 
505 /* analog input ranges for 6052, etc boards */
506 static const struct comedi_lrange ai_ranges_6052 = {
507         15, {
508                 BIP_RANGE(10),
509                 BIP_RANGE(5),
510                 BIP_RANGE(2.5),
511                 BIP_RANGE(1),
512                 BIP_RANGE(0.5),
513                 BIP_RANGE(0.25),
514                 BIP_RANGE(0.1),
515                 BIP_RANGE(0.05),
516                 UNI_RANGE(10),
517                 UNI_RANGE(5),
518                 UNI_RANGE(2),
519                 UNI_RANGE(1),
520                 UNI_RANGE(0.5),
521                 UNI_RANGE(0.2),
522                 UNI_RANGE(0.1)
523         }
524 };
525 
526 static const uint8_t ai_range_code_6052[15] = {
527         0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, /* bipolar 10 ... 0.05 */
528         0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf       /* unipolar 10 ... 0.1 */
529 };
530 
531 /* analog input ranges for 4020 board */
532 static const struct comedi_lrange ai_ranges_4020 = {
533         2, {
534                 BIP_RANGE(5),
535                 BIP_RANGE(1)
536         }
537 };
538 
539 /* analog output ranges */
540 static const struct comedi_lrange ao_ranges_64xx = {
541         4, {
542                 BIP_RANGE(5),
543                 BIP_RANGE(10),
544                 UNI_RANGE(5),
545                 UNI_RANGE(10)
546         }
547 };
548 
549 static const int ao_range_code_64xx[] = {
550         0x0,
551         0x1,
552         0x2,
553         0x3,
554 };
555 
556 static const int ao_range_code_60xx[] = {
557         0x0,
558 };
559 
560 static const struct comedi_lrange ao_ranges_6030 = {
561         2, {
562                 BIP_RANGE(10),
563                 UNI_RANGE(10)
564         }
565 };
566 
567 static const int ao_range_code_6030[] = {
568         0x0,
569         0x2,
570 };
571 
572 static const struct comedi_lrange ao_ranges_4020 = {
573         2, {
574                 BIP_RANGE(5),
575                 BIP_RANGE(10)
576         }
577 };
578 
579 static const int ao_range_code_4020[] = {
580         0x1,
581         0x0,
582 };
583 
584 enum register_layout {
585         LAYOUT_60XX,
586         LAYOUT_64XX,
587         LAYOUT_4020,
588 };
589 
590 struct hw_fifo_info {
591         unsigned int num_segments;
592         unsigned int max_segment_length;
593         unsigned int sample_packing_ratio;
594         uint16_t fifo_size_reg_mask;
595 };
596 
597 enum pcidas64_boardid {
598         BOARD_PCIDAS6402_16,
599         BOARD_PCIDAS6402_12,
600         BOARD_PCIDAS64_M1_16,
601         BOARD_PCIDAS64_M2_16,
602         BOARD_PCIDAS64_M3_16,
603         BOARD_PCIDAS6013,
604         BOARD_PCIDAS6014,
605         BOARD_PCIDAS6023,
606         BOARD_PCIDAS6025,
607         BOARD_PCIDAS6030,
608         BOARD_PCIDAS6031,
609         BOARD_PCIDAS6032,
610         BOARD_PCIDAS6033,
611         BOARD_PCIDAS6034,
612         BOARD_PCIDAS6035,
613         BOARD_PCIDAS6036,
614         BOARD_PCIDAS6040,
615         BOARD_PCIDAS6052,
616         BOARD_PCIDAS6070,
617         BOARD_PCIDAS6071,
618         BOARD_PCIDAS4020_12,
619         BOARD_PCIDAS6402_16_JR,
620         BOARD_PCIDAS64_M1_16_JR,
621         BOARD_PCIDAS64_M2_16_JR,
622         BOARD_PCIDAS64_M3_16_JR,
623         BOARD_PCIDAS64_M1_14,
624         BOARD_PCIDAS64_M2_14,
625         BOARD_PCIDAS64_M3_14,
626 };
627 
628 struct pcidas64_board {
629         const char *name;
630         int ai_se_chans;        /*  number of ai inputs in single-ended mode */
631         int ai_bits;            /*  analog input resolution */
632         int ai_speed;           /*  fastest conversion period in ns */
633         const struct comedi_lrange *ai_range_table;
634         const uint8_t *ai_range_code;
635         int ao_nchan;           /*  number of analog out channels */
636         int ao_bits;            /*  analog output resolution */
637         int ao_scan_speed;      /*  analog output scan speed */
638         const struct comedi_lrange *ao_range_table;
639         const int *ao_range_code;
640         const struct hw_fifo_info *const ai_fifo;
641         /*  different board families have slightly different registers */
642         enum register_layout layout;
643         unsigned has_8255:1;
644 };
645 
646 static const struct hw_fifo_info ai_fifo_4020 = {
647         .num_segments = 2,
648         .max_segment_length = 0x8000,
649         .sample_packing_ratio = 2,
650         .fifo_size_reg_mask = 0x7f,
651 };
652 
653 static const struct hw_fifo_info ai_fifo_64xx = {
654         .num_segments = 4,
655         .max_segment_length = 0x800,
656         .sample_packing_ratio = 1,
657         .fifo_size_reg_mask = 0x3f,
658 };
659 
660 static const struct hw_fifo_info ai_fifo_60xx = {
661         .num_segments = 4,
662         .max_segment_length = 0x800,
663         .sample_packing_ratio = 1,
664         .fifo_size_reg_mask = 0x7f,
665 };
666 
667 /*
668  * maximum number of dma transfers we will chain together into a ring
669  * (and the maximum number of dma buffers we maintain)
670  */
671 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
672 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
673 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
674 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
675 {
676         if (board->layout == LAYOUT_4020)
677                 return MAX_AI_DMA_RING_COUNT;
678 
679         return MIN_AI_DMA_RING_COUNT;
680 }
681 
682 static const int bytes_in_sample = 2;
683 
684 static const struct pcidas64_board pcidas64_boards[] = {
685         [BOARD_PCIDAS6402_16] = {
686                 .name           = "pci-das6402/16",
687                 .ai_se_chans    = 64,
688                 .ai_bits        = 16,
689                 .ai_speed       = 5000,
690                 .ao_nchan       = 2,
691                 .ao_bits        = 16,
692                 .ao_scan_speed  = 10000,
693                 .layout         = LAYOUT_64XX,
694                 .ai_range_table = &ai_ranges_64xx,
695                 .ai_range_code  = ai_range_code_64xx,
696                 .ao_range_table = &ao_ranges_64xx,
697                 .ao_range_code  = ao_range_code_64xx,
698                 .ai_fifo        = &ai_fifo_64xx,
699                 .has_8255       = 1,
700         },
701         [BOARD_PCIDAS6402_12] = {
702                 .name           = "pci-das6402/12",     /*  XXX check */
703                 .ai_se_chans    = 64,
704                 .ai_bits        = 12,
705                 .ai_speed       = 5000,
706                 .ao_nchan       = 2,
707                 .ao_bits        = 12,
708                 .ao_scan_speed  = 10000,
709                 .layout         = LAYOUT_64XX,
710                 .ai_range_table = &ai_ranges_64xx,
711                 .ai_range_code  = ai_range_code_64xx,
712                 .ao_range_table = &ao_ranges_64xx,
713                 .ao_range_code  = ao_range_code_64xx,
714                 .ai_fifo        = &ai_fifo_64xx,
715                 .has_8255       = 1,
716         },
717         [BOARD_PCIDAS64_M1_16] = {
718                 .name           = "pci-das64/m1/16",
719                 .ai_se_chans    = 64,
720                 .ai_bits        = 16,
721                 .ai_speed       = 1000,
722                 .ao_nchan       = 2,
723                 .ao_bits        = 16,
724                 .ao_scan_speed  = 10000,
725                 .layout         = LAYOUT_64XX,
726                 .ai_range_table = &ai_ranges_64_mx,
727                 .ai_range_code  = ai_range_code_64_mx,
728                 .ao_range_table = &ao_ranges_64xx,
729                 .ao_range_code  = ao_range_code_64xx,
730                 .ai_fifo        = &ai_fifo_64xx,
731                 .has_8255       = 1,
732         },
733         [BOARD_PCIDAS64_M2_16] = {
734                 .name = "pci-das64/m2/16",
735                 .ai_se_chans    = 64,
736                 .ai_bits        = 16,
737                 .ai_speed       = 500,
738                 .ao_nchan       = 2,
739                 .ao_bits        = 16,
740                 .ao_scan_speed  = 10000,
741                 .layout         = LAYOUT_64XX,
742                 .ai_range_table = &ai_ranges_64_mx,
743                 .ai_range_code  = ai_range_code_64_mx,
744                 .ao_range_table = &ao_ranges_64xx,
745                 .ao_range_code  = ao_range_code_64xx,
746                 .ai_fifo        = &ai_fifo_64xx,
747                 .has_8255       = 1,
748         },
749         [BOARD_PCIDAS64_M3_16] = {
750                 .name           = "pci-das64/m3/16",
751                 .ai_se_chans    = 64,
752                 .ai_bits        = 16,
753                 .ai_speed       = 333,
754                 .ao_nchan       = 2,
755                 .ao_bits        = 16,
756                 .ao_scan_speed  = 10000,
757                 .layout         = LAYOUT_64XX,
758                 .ai_range_table = &ai_ranges_64_mx,
759                 .ai_range_code  = ai_range_code_64_mx,
760                 .ao_range_table = &ao_ranges_64xx,
761                 .ao_range_code  = ao_range_code_64xx,
762                 .ai_fifo        = &ai_fifo_64xx,
763                 .has_8255       = 1,
764         },
765         [BOARD_PCIDAS6013] = {
766                 .name           = "pci-das6013",
767                 .ai_se_chans    = 16,
768                 .ai_bits        = 16,
769                 .ai_speed       = 5000,
770                 .ao_nchan       = 0,
771                 .ao_bits        = 16,
772                 .layout         = LAYOUT_60XX,
773                 .ai_range_table = &ai_ranges_60xx,
774                 .ai_range_code  = ai_range_code_60xx,
775                 .ao_range_table = &range_bipolar10,
776                 .ao_range_code  = ao_range_code_60xx,
777                 .ai_fifo        = &ai_fifo_60xx,
778                 .has_8255       = 0,
779         },
780         [BOARD_PCIDAS6014] = {
781                 .name           = "pci-das6014",
782                 .ai_se_chans    = 16,
783                 .ai_bits        = 16,
784                 .ai_speed       = 5000,
785                 .ao_nchan       = 2,
786                 .ao_bits        = 16,
787                 .ao_scan_speed  = 100000,
788                 .layout         = LAYOUT_60XX,
789                 .ai_range_table = &ai_ranges_60xx,
790                 .ai_range_code  = ai_range_code_60xx,
791                 .ao_range_table = &range_bipolar10,
792                 .ao_range_code  = ao_range_code_60xx,
793                 .ai_fifo        = &ai_fifo_60xx,
794                 .has_8255       = 0,
795         },
796         [BOARD_PCIDAS6023] = {
797                 .name           = "pci-das6023",
798                 .ai_se_chans    = 16,
799                 .ai_bits        = 12,
800                 .ai_speed       = 5000,
801                 .ao_nchan       = 0,
802                 .ao_scan_speed  = 100000,
803                 .layout         = LAYOUT_60XX,
804                 .ai_range_table = &ai_ranges_60xx,
805                 .ai_range_code  = ai_range_code_60xx,
806                 .ao_range_table = &range_bipolar10,
807                 .ao_range_code  = ao_range_code_60xx,
808                 .ai_fifo        = &ai_fifo_60xx,
809                 .has_8255       = 1,
810         },
811         [BOARD_PCIDAS6025] = {
812                 .name           = "pci-das6025",
813                 .ai_se_chans    = 16,
814                 .ai_bits        = 12,
815                 .ai_speed       = 5000,
816                 .ao_nchan       = 2,
817                 .ao_bits        = 12,
818                 .ao_scan_speed  = 100000,
819                 .layout         = LAYOUT_60XX,
820                 .ai_range_table = &ai_ranges_60xx,
821                 .ai_range_code  = ai_range_code_60xx,
822                 .ao_range_table = &range_bipolar10,
823                 .ao_range_code  = ao_range_code_60xx,
824                 .ai_fifo        = &ai_fifo_60xx,
825                 .has_8255       = 1,
826         },
827         [BOARD_PCIDAS6030] = {
828                 .name           = "pci-das6030",
829                 .ai_se_chans    = 16,
830                 .ai_bits        = 16,
831                 .ai_speed       = 10000,
832                 .ao_nchan       = 2,
833                 .ao_bits        = 16,
834                 .ao_scan_speed  = 10000,
835                 .layout         = LAYOUT_60XX,
836                 .ai_range_table = &ai_ranges_6030,
837                 .ai_range_code  = ai_range_code_6030,
838                 .ao_range_table = &ao_ranges_6030,
839                 .ao_range_code  = ao_range_code_6030,
840                 .ai_fifo        = &ai_fifo_60xx,
841                 .has_8255       = 0,
842         },
843         [BOARD_PCIDAS6031] = {
844                 .name           = "pci-das6031",
845                 .ai_se_chans    = 64,
846                 .ai_bits        = 16,
847                 .ai_speed       = 10000,
848                 .ao_nchan       = 2,
849                 .ao_bits        = 16,
850                 .ao_scan_speed  = 10000,
851                 .layout         = LAYOUT_60XX,
852                 .ai_range_table = &ai_ranges_6030,
853                 .ai_range_code  = ai_range_code_6030,
854                 .ao_range_table = &ao_ranges_6030,
855                 .ao_range_code  = ao_range_code_6030,
856                 .ai_fifo        = &ai_fifo_60xx,
857                 .has_8255       = 0,
858         },
859         [BOARD_PCIDAS6032] = {
860                 .name           = "pci-das6032",
861                 .ai_se_chans    = 16,
862                 .ai_bits        = 16,
863                 .ai_speed       = 10000,
864                 .ao_nchan       = 0,
865                 .layout         = LAYOUT_60XX,
866                 .ai_range_table = &ai_ranges_6030,
867                 .ai_range_code  = ai_range_code_6030,
868                 .ai_fifo        = &ai_fifo_60xx,
869                 .has_8255       = 0,
870         },
871         [BOARD_PCIDAS6033] = {
872                 .name           = "pci-das6033",
873                 .ai_se_chans    = 64,
874                 .ai_bits        = 16,
875                 .ai_speed       = 10000,
876                 .ao_nchan       = 0,
877                 .layout         = LAYOUT_60XX,
878                 .ai_range_table = &ai_ranges_6030,
879                 .ai_range_code  = ai_range_code_6030,
880                 .ai_fifo        = &ai_fifo_60xx,
881                 .has_8255       = 0,
882         },
883         [BOARD_PCIDAS6034] = {
884                 .name           = "pci-das6034",
885                 .ai_se_chans    = 16,
886                 .ai_bits        = 16,
887                 .ai_speed       = 5000,
888                 .ao_nchan       = 0,
889                 .ao_scan_speed  = 0,
890                 .layout         = LAYOUT_60XX,
891                 .ai_range_table = &ai_ranges_60xx,
892                 .ai_range_code  = ai_range_code_60xx,
893                 .ai_fifo        = &ai_fifo_60xx,
894                 .has_8255       = 0,
895         },
896         [BOARD_PCIDAS6035] = {
897                 .name           = "pci-das6035",
898                 .ai_se_chans    = 16,
899                 .ai_bits        = 16,
900                 .ai_speed       = 5000,
901                 .ao_nchan       = 2,
902                 .ao_bits        = 12,
903                 .ao_scan_speed  = 100000,
904                 .layout         = LAYOUT_60XX,
905                 .ai_range_table = &ai_ranges_60xx,
906                 .ai_range_code  = ai_range_code_60xx,
907                 .ao_range_table = &range_bipolar10,
908                 .ao_range_code  = ao_range_code_60xx,
909                 .ai_fifo        = &ai_fifo_60xx,
910                 .has_8255       = 0,
911         },
912         [BOARD_PCIDAS6036] = {
913                 .name           = "pci-das6036",
914                 .ai_se_chans    = 16,
915                 .ai_bits        = 16,
916                 .ai_speed       = 5000,
917                 .ao_nchan       = 2,
918                 .ao_bits        = 16,
919                 .ao_scan_speed  = 100000,
920                 .layout         = LAYOUT_60XX,
921                 .ai_range_table = &ai_ranges_60xx,
922                 .ai_range_code  = ai_range_code_60xx,
923                 .ao_range_table = &range_bipolar10,
924                 .ao_range_code  = ao_range_code_60xx,
925                 .ai_fifo        = &ai_fifo_60xx,
926                 .has_8255       = 0,
927         },
928         [BOARD_PCIDAS6040] = {
929                 .name           = "pci-das6040",
930                 .ai_se_chans    = 16,
931                 .ai_bits        = 12,
932                 .ai_speed       = 2000,
933                 .ao_nchan       = 2,
934                 .ao_bits        = 12,
935                 .ao_scan_speed  = 1000,
936                 .layout         = LAYOUT_60XX,
937                 .ai_range_table = &ai_ranges_6052,
938                 .ai_range_code  = ai_range_code_6052,
939                 .ao_range_table = &ao_ranges_6030,
940                 .ao_range_code  = ao_range_code_6030,
941                 .ai_fifo        = &ai_fifo_60xx,
942                 .has_8255       = 0,
943         },
944         [BOARD_PCIDAS6052] = {
945                 .name           = "pci-das6052",
946                 .ai_se_chans    = 16,
947                 .ai_bits        = 16,
948                 .ai_speed       = 3333,
949                 .ao_nchan       = 2,
950                 .ao_bits        = 16,
951                 .ao_scan_speed  = 3333,
952                 .layout         = LAYOUT_60XX,
953                 .ai_range_table = &ai_ranges_6052,
954                 .ai_range_code  = ai_range_code_6052,
955                 .ao_range_table = &ao_ranges_6030,
956                 .ao_range_code  = ao_range_code_6030,
957                 .ai_fifo        = &ai_fifo_60xx,
958                 .has_8255       = 0,
959         },
960         [BOARD_PCIDAS6070] = {
961                 .name           = "pci-das6070",
962                 .ai_se_chans    = 16,
963                 .ai_bits        = 12,
964                 .ai_speed       = 800,
965                 .ao_nchan       = 2,
966                 .ao_bits        = 12,
967                 .ao_scan_speed  = 1000,
968                 .layout         = LAYOUT_60XX,
969                 .ai_range_table = &ai_ranges_6052,
970                 .ai_range_code  = ai_range_code_6052,
971                 .ao_range_table = &ao_ranges_6030,
972                 .ao_range_code  = ao_range_code_6030,
973                 .ai_fifo        = &ai_fifo_60xx,
974                 .has_8255       = 0,
975         },
976         [BOARD_PCIDAS6071] = {
977                 .name           = "pci-das6071",
978                 .ai_se_chans    = 64,
979                 .ai_bits        = 12,
980                 .ai_speed       = 800,
981                 .ao_nchan       = 2,
982                 .ao_bits        = 12,
983                 .ao_scan_speed  = 1000,
984                 .layout         = LAYOUT_60XX,
985                 .ai_range_table = &ai_ranges_6052,
986                 .ai_range_code  = ai_range_code_6052,
987                 .ao_range_table = &ao_ranges_6030,
988                 .ao_range_code  = ao_range_code_6030,
989                 .ai_fifo        = &ai_fifo_60xx,
990                 .has_8255       = 0,
991         },
992         [BOARD_PCIDAS4020_12] = {
993                 .name           = "pci-das4020/12",
994                 .ai_se_chans    = 4,
995                 .ai_bits        = 12,
996                 .ai_speed       = 50,
997                 .ao_bits        = 12,
998                 .ao_nchan       = 2,
999                 .ao_scan_speed  = 0,    /*  no hardware pacing on ao */
1000                 .layout         = LAYOUT_4020,
1001                 .ai_range_table = &ai_ranges_4020,
1002                 .ao_range_table = &ao_ranges_4020,
1003                 .ao_range_code  = ao_range_code_4020,
1004                 .ai_fifo        = &ai_fifo_4020,
1005                 .has_8255       = 1,
1006         },
1007 #if 0
1008         /*
1009          * The device id for these boards is unknown
1010          */
1011 
1012         [BOARD_PCIDAS6402_16_JR] = {
1013                 .name           = "pci-das6402/16/jr",
1014                 .ai_se_chans    = 64,
1015                 .ai_bits        = 16,
1016                 .ai_speed       = 5000,
1017                 .ao_nchan       = 0,
1018                 .ao_scan_speed  = 10000,
1019                 .layout         = LAYOUT_64XX,
1020                 .ai_range_table = &ai_ranges_64xx,
1021                 .ai_range_code  = ai_range_code_64xx,
1022                 .ai_fifo        = ai_fifo_64xx,
1023                 .has_8255       = 1,
1024         },
1025         [BOARD_PCIDAS64_M1_16_JR] = {
1026                 .name           = "pci-das64/m1/16/jr",
1027                 .ai_se_chans    = 64,
1028                 .ai_bits        = 16,
1029                 .ai_speed       = 1000,
1030                 .ao_nchan       = 0,
1031                 .ao_scan_speed  = 10000,
1032                 .layout         = LAYOUT_64XX,
1033                 .ai_range_table = &ai_ranges_64_mx,
1034                 .ai_range_code  = ai_range_code_64_mx,
1035                 .ai_fifo        = ai_fifo_64xx,
1036                 .has_8255       = 1,
1037         },
1038         [BOARD_PCIDAS64_M2_16_JR] = {
1039                 .name = "pci-das64/m2/16/jr",
1040                 .ai_se_chans    = 64,
1041                 .ai_bits        = 16,
1042                 .ai_speed       = 500,
1043                 .ao_nchan       = 0,
1044                 .ao_scan_speed  = 10000,
1045                 .layout         = LAYOUT_64XX,
1046                 .ai_range_table = &ai_ranges_64_mx,
1047                 .ai_range_code  = ai_range_code_64_mx,
1048                 .ai_fifo        = ai_fifo_64xx,
1049                 .has_8255       = 1,
1050         },
1051         [BOARD_PCIDAS64_M3_16_JR] = {
1052                 .name           = "pci-das64/m3/16/jr",
1053                 .ai_se_chans    = 64,
1054                 .ai_bits        = 16,
1055                 .ai_speed       = 333,
1056                 .ao_nchan       = 0,
1057                 .ao_scan_speed  = 10000,
1058                 .layout         = LAYOUT_64XX,
1059                 .ai_range_table = &ai_ranges_64_mx,
1060                 .ai_range_code  = ai_range_code_64_mx,
1061                 .ai_fifo        = ai_fifo_64xx,
1062                 .has_8255       = 1,
1063         },
1064         [BOARD_PCIDAS64_M1_14] = {
1065                 .name           = "pci-das64/m1/14",
1066                 .ai_se_chans    = 64,
1067                 .ai_bits        = 14,
1068                 .ai_speed       = 1000,
1069                 .ao_nchan       = 2,
1070                 .ao_scan_speed  = 10000,
1071                 .layout         = LAYOUT_64XX,
1072                 .ai_range_table = &ai_ranges_64_mx,
1073                 .ai_range_code  = ai_range_code_64_mx,
1074                 .ai_fifo        = ai_fifo_64xx,
1075                 .has_8255       = 1,
1076         },
1077         [BOARD_PCIDAS64_M2_14] = {
1078                 .name           = "pci-das64/m2/14",
1079                 .ai_se_chans    = 64,
1080                 .ai_bits        = 14,
1081                 .ai_speed       = 500,
1082                 .ao_nchan       = 2,
1083                 .ao_scan_speed  = 10000,
1084                 .layout         = LAYOUT_64XX,
1085                 .ai_range_table = &ai_ranges_64_mx,
1086                 .ai_range_code  = ai_range_code_64_mx,
1087                 .ai_fifo        = ai_fifo_64xx,
1088                 .has_8255       = 1,
1089         },
1090         [BOARD_PCIDAS64_M3_14] = {
1091                 .name           = "pci-das64/m3/14",
1092                 .ai_se_chans    = 64,
1093                 .ai_bits        = 14,
1094                 .ai_speed       = 333,
1095                 .ao_nchan       = 2,
1096                 .ao_scan_speed  = 10000,
1097                 .layout         = LAYOUT_64XX,
1098                 .ai_range_table = &ai_ranges_64_mx,
1099                 .ai_range_code  = ai_range_code_64_mx,
1100                 .ai_fifo        = ai_fifo_64xx,
1101                 .has_8255       = 1,
1102         },
1103 #endif
1104 };
1105 
1106 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1107                                               int use_differential)
1108 {
1109         const struct pcidas64_board *board = dev->board_ptr;
1110 
1111         if ((board->layout == LAYOUT_64XX && !use_differential) ||
1112             (board->layout == LAYOUT_60XX && use_differential))
1113                 return ADC_SE_DIFF_BIT;
1114 
1115         return 0;
1116 }
1117 
1118 struct ext_clock_info {
1119         /*  master clock divisor to use for scans with external master clock */
1120         unsigned int divisor;
1121         /*  chanspec for master clock input when used as scan begin src */
1122         unsigned int chanspec;
1123 };
1124 
1125 /* this structure is for data unique to this hardware driver. */
1126 struct pcidas64_private {
1127         /*  base addresses (physical) */
1128         resource_size_t main_phys_iobase;
1129         resource_size_t dio_counter_phys_iobase;
1130         /*  base addresses (ioremapped) */
1131         void __iomem *plx9080_iobase;
1132         void __iomem *main_iobase;
1133         /*  local address (used by dma controller) */
1134         uint32_t local0_iobase;
1135         uint32_t local1_iobase;
1136         /*  dma buffers for analog input */
1137         uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];
1138         /*  physical addresses of ai dma buffers */
1139         dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1140         /*  array of ai dma descriptors read by plx9080,
1141          *  allocated to get proper alignment */
1142         struct plx_dma_desc *ai_dma_desc;
1143         /*  physical address of ai dma descriptor array */
1144         dma_addr_t ai_dma_desc_bus_addr;
1145         /*  index of the ai dma descriptor/buffer
1146          *  that is currently being used */
1147         unsigned int ai_dma_index;
1148         /*  dma buffers for analog output */
1149         uint16_t *ao_buffer[AO_DMA_RING_COUNT];
1150         /*  physical addresses of ao dma buffers */
1151         dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1152         struct plx_dma_desc *ao_dma_desc;
1153         dma_addr_t ao_dma_desc_bus_addr;
1154         /*  keeps track of buffer where the next ao sample should go */
1155         unsigned int ao_dma_index;
1156         unsigned int hw_revision;       /*  stc chip hardware revision number */
1157         /*  last bits sent to INTR_ENABLE_REG register */
1158         unsigned int intr_enable_bits;
1159         /*  last bits sent to ADC_CONTROL1_REG register */
1160         uint16_t adc_control1_bits;
1161         /*  last bits sent to FIFO_SIZE_REG register */
1162         uint16_t fifo_size_bits;
1163         /*  last bits sent to HW_CONFIG_REG register */
1164         uint16_t hw_config_bits;
1165         uint16_t dac_control1_bits;
1166         /*  last bits written to plx9080 control register */
1167         uint32_t plx_control_bits;
1168         /*  last bits written to plx interrupt control and status register */
1169         uint32_t plx_intcsr_bits;
1170         /*  index of calibration source readable through ai ch0 */
1171         int calibration_source;
1172         /*  bits written to i2c calibration/range register */
1173         uint8_t i2c_cal_range_bits;
1174         /*  configure digital triggers to trigger on falling edge */
1175         unsigned int ext_trig_falling;
1176         short ai_cmd_running;
1177         unsigned int ai_fifo_segment_length;
1178         struct ext_clock_info ext_clock;
1179         unsigned short ao_bounce_buffer[DAC_FIFO_SIZE];
1180 };
1181 
1182 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1183                                        unsigned int range_index)
1184 {
1185         const struct pcidas64_board *board = dev->board_ptr;
1186 
1187         return board->ai_range_code[range_index] << 8;
1188 }
1189 
1190 static unsigned int hw_revision(const struct comedi_device *dev,
1191                                 uint16_t hw_status_bits)
1192 {
1193         const struct pcidas64_board *board = dev->board_ptr;
1194 
1195         if (board->layout == LAYOUT_4020)
1196                 return (hw_status_bits >> 13) & 0x7;
1197 
1198         return (hw_status_bits >> 12) & 0xf;
1199 }
1200 
1201 static void set_dac_range_bits(struct comedi_device *dev,
1202                                uint16_t *bits, unsigned int channel,
1203                                unsigned int range)
1204 {
1205         const struct pcidas64_board *board = dev->board_ptr;
1206         unsigned int code = board->ao_range_code[range];
1207 
1208         if (channel > 1)
1209                 dev_err(dev->class_dev, "bug! bad channel?\n");
1210         if (code & ~0x3)
1211                 dev_err(dev->class_dev, "bug! bad range code?\n");
1212 
1213         *bits &= ~(0x3 << (2 * channel));
1214         *bits |= code << (2 * channel);
1215 };
1216 
1217 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1218 {
1219         return board->ao_nchan && board->layout != LAYOUT_4020;
1220 }
1221 
1222 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1223 {
1224         struct pcidas64_private *devpriv = dev->private;
1225         unsigned long flags;
1226 
1227         /*  spinlock for plx dma control/status reg */
1228         spin_lock_irqsave(&dev->spinlock, flags);
1229 
1230         plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1231 
1232         spin_unlock_irqrestore(&dev->spinlock, flags);
1233 }
1234 
1235 static void disable_plx_interrupts(struct comedi_device *dev)
1236 {
1237         struct pcidas64_private *devpriv = dev->private;
1238 
1239         devpriv->plx_intcsr_bits = 0;
1240         writel(devpriv->plx_intcsr_bits,
1241                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1242 }
1243 
1244 static void disable_ai_interrupts(struct comedi_device *dev)
1245 {
1246         struct pcidas64_private *devpriv = dev->private;
1247         unsigned long flags;
1248 
1249         spin_lock_irqsave(&dev->spinlock, flags);
1250         devpriv->intr_enable_bits &=
1251                 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1252                 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1253                 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1254         writew(devpriv->intr_enable_bits,
1255                devpriv->main_iobase + INTR_ENABLE_REG);
1256         spin_unlock_irqrestore(&dev->spinlock, flags);
1257 }
1258 
1259 static void enable_ai_interrupts(struct comedi_device *dev,
1260                                  const struct comedi_cmd *cmd)
1261 {
1262         const struct pcidas64_board *board = dev->board_ptr;
1263         struct pcidas64_private *devpriv = dev->private;
1264         uint32_t bits;
1265         unsigned long flags;
1266 
1267         bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1268                EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1269         /*
1270          * Use pio transfer and interrupt on end of conversion
1271          * if CMDF_WAKE_EOS flag is set.
1272          */
1273         if (cmd->flags & CMDF_WAKE_EOS) {
1274                 /*  4020 doesn't support pio transfers except for fifo dregs */
1275                 if (board->layout != LAYOUT_4020)
1276                         bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1277         }
1278         spin_lock_irqsave(&dev->spinlock, flags);
1279         devpriv->intr_enable_bits |= bits;
1280         writew(devpriv->intr_enable_bits,
1281                devpriv->main_iobase + INTR_ENABLE_REG);
1282         spin_unlock_irqrestore(&dev->spinlock, flags);
1283 }
1284 
1285 /* initialize plx9080 chip */
1286 static void init_plx9080(struct comedi_device *dev)
1287 {
1288         const struct pcidas64_board *board = dev->board_ptr;
1289         struct pcidas64_private *devpriv = dev->private;
1290         uint32_t bits;
1291         void __iomem *plx_iobase = devpriv->plx9080_iobase;
1292 
1293         devpriv->plx_control_bits =
1294                 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
1295 
1296 #ifdef __BIG_ENDIAN
1297         bits = BIGEND_DMA0 | BIGEND_DMA1;
1298 #else
1299         bits = 0;
1300 #endif
1301         writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
1302 
1303         disable_plx_interrupts(dev);
1304 
1305         abort_dma(dev, 0);
1306         abort_dma(dev, 1);
1307 
1308         /*  configure dma0 mode */
1309         bits = 0;
1310         /*  enable ready input, not sure if this is necessary */
1311         bits |= PLX_DMA_EN_READYIN_BIT;
1312         /*  enable bterm, not sure if this is necessary */
1313         bits |= PLX_EN_BTERM_BIT;
1314         /*  enable dma chaining */
1315         bits |= PLX_EN_CHAIN_BIT;
1316         /*  enable interrupt on dma done
1317          *  (probably don't need this, since chain never finishes) */
1318         bits |= PLX_EN_DMA_DONE_INTR_BIT;
1319         /*  don't increment local address during transfers
1320          *  (we are transferring from a fixed fifo register) */
1321         bits |= PLX_LOCAL_ADDR_CONST_BIT;
1322         /*  route dma interrupt to pci bus */
1323         bits |= PLX_DMA_INTR_PCI_BIT;
1324         /*  enable demand mode */
1325         bits |= PLX_DEMAND_MODE_BIT;
1326         /*  enable local burst mode */
1327         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1328         /*  4020 uses 32 bit dma */
1329         if (board->layout == LAYOUT_4020)
1330                 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1331         else            /*  localspace0 bus is 16 bits wide */
1332                 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1333         writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1334         if (ao_cmd_is_supported(board))
1335                 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1336 
1337         /*  enable interrupts on plx 9080 */
1338         devpriv->plx_intcsr_bits |=
1339             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1340             ICS_DMA0_E | ICS_DMA1_E;
1341         writel(devpriv->plx_intcsr_bits,
1342                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1343 }
1344 
1345 static void disable_ai_pacing(struct comedi_device *dev)
1346 {
1347         struct pcidas64_private *devpriv = dev->private;
1348         unsigned long flags;
1349 
1350         disable_ai_interrupts(dev);
1351 
1352         spin_lock_irqsave(&dev->spinlock, flags);
1353         devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1354         writew(devpriv->adc_control1_bits,
1355                devpriv->main_iobase + ADC_CONTROL1_REG);
1356         spin_unlock_irqrestore(&dev->spinlock, flags);
1357 
1358         /* disable pacing, triggering, etc */
1359         writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1360                devpriv->main_iobase + ADC_CONTROL0_REG);
1361 }
1362 
1363 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1364                                       unsigned int num_entries)
1365 {
1366         const struct pcidas64_board *board = dev->board_ptr;
1367         struct pcidas64_private *devpriv = dev->private;
1368         static const int increment_size = 0x100;
1369         const struct hw_fifo_info *const fifo = board->ai_fifo;
1370         unsigned int num_increments;
1371         uint16_t bits;
1372 
1373         if (num_entries < increment_size)
1374                 num_entries = increment_size;
1375         if (num_entries > fifo->max_segment_length)
1376                 num_entries = fifo->max_segment_length;
1377 
1378         /*  1 == 256 entries, 2 == 512 entries, etc */
1379         num_increments = (num_entries + increment_size / 2) / increment_size;
1380 
1381         bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1382         devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1383         devpriv->fifo_size_bits |= bits;
1384         writew(devpriv->fifo_size_bits,
1385                devpriv->main_iobase + FIFO_SIZE_REG);
1386 
1387         devpriv->ai_fifo_segment_length = num_increments * increment_size;
1388 
1389         return devpriv->ai_fifo_segment_length;
1390 }
1391 
1392 /*
1393  * adjusts the size of hardware fifo (which determines block size for dma xfers)
1394  */
1395 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1396 {
1397         const struct pcidas64_board *board = dev->board_ptr;
1398         unsigned int num_fifo_entries;
1399         int retval;
1400         const struct hw_fifo_info *const fifo = board->ai_fifo;
1401 
1402         num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1403 
1404         retval = set_ai_fifo_segment_length(dev,
1405                                             num_fifo_entries /
1406                                             fifo->num_segments);
1407         if (retval < 0)
1408                 return retval;
1409 
1410         num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
1411 
1412         return num_samples;
1413 }
1414 
1415 /* query length of fifo */
1416 static unsigned int ai_fifo_size(struct comedi_device *dev)
1417 {
1418         const struct pcidas64_board *board = dev->board_ptr;
1419         struct pcidas64_private *devpriv = dev->private;
1420 
1421         return devpriv->ai_fifo_segment_length *
1422                board->ai_fifo->num_segments *
1423                board->ai_fifo->sample_packing_ratio;
1424 }
1425 
1426 static void init_stc_registers(struct comedi_device *dev)
1427 {
1428         const struct pcidas64_board *board = dev->board_ptr;
1429         struct pcidas64_private *devpriv = dev->private;
1430         uint16_t bits;
1431         unsigned long flags;
1432 
1433         spin_lock_irqsave(&dev->spinlock, flags);
1434 
1435         /*
1436          * bit should be set for 6025,
1437          * although docs say boards with <= 16 chans should be cleared XXX
1438          */
1439         if (1)
1440                 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1441         writew(devpriv->adc_control1_bits,
1442                devpriv->main_iobase + ADC_CONTROL1_REG);
1443 
1444         /*  6402/16 manual says this register must be initialized to 0xff? */
1445         writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1446 
1447         bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1448         if (board->layout == LAYOUT_4020)
1449                 bits |= INTERNAL_CLOCK_4020_BITS;
1450         devpriv->hw_config_bits |= bits;
1451         writew(devpriv->hw_config_bits,
1452                devpriv->main_iobase + HW_CONFIG_REG);
1453 
1454         writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1455         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1456 
1457         spin_unlock_irqrestore(&dev->spinlock, flags);
1458 
1459         /*  set fifos to maximum size */
1460         devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1461         set_ai_fifo_segment_length(dev, board->ai_fifo->max_segment_length);
1462 
1463         devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1464         devpriv->intr_enable_bits =
1465                 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1466                 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1467         writew(devpriv->intr_enable_bits,
1468                devpriv->main_iobase + INTR_ENABLE_REG);
1469 
1470         disable_ai_pacing(dev);
1471 };
1472 
1473 static int alloc_and_init_dma_members(struct comedi_device *dev)
1474 {
1475         const struct pcidas64_board *board = dev->board_ptr;
1476         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1477         struct pcidas64_private *devpriv = dev->private;
1478         int i;
1479 
1480         /*  allocate pci dma buffers */
1481         for (i = 0; i < ai_dma_ring_count(board); i++) {
1482                 devpriv->ai_buffer[i] =
1483                         pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1484                                              &devpriv->ai_buffer_bus_addr[i]);
1485                 if (!devpriv->ai_buffer[i])
1486                         return -ENOMEM;
1487         }
1488         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1489                 if (ao_cmd_is_supported(board)) {
1490                         devpriv->ao_buffer[i] =
1491                                 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1492                                                      &devpriv->
1493                                                       ao_buffer_bus_addr[i]);
1494                         if (!devpriv->ao_buffer[i])
1495                                 return -ENOMEM;
1496                 }
1497         }
1498         /*  allocate dma descriptors */
1499         devpriv->ai_dma_desc =
1500                 pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) *
1501                                      ai_dma_ring_count(board),
1502                                      &devpriv->ai_dma_desc_bus_addr);
1503         if (!devpriv->ai_dma_desc)
1504                 return -ENOMEM;
1505 
1506         if (ao_cmd_is_supported(board)) {
1507                 devpriv->ao_dma_desc =
1508                         pci_alloc_consistent(pcidev,
1509                                              sizeof(struct plx_dma_desc) *
1510                                              AO_DMA_RING_COUNT,
1511                                              &devpriv->ao_dma_desc_bus_addr);
1512                 if (!devpriv->ao_dma_desc)
1513                         return -ENOMEM;
1514         }
1515         /*  initialize dma descriptors */
1516         for (i = 0; i < ai_dma_ring_count(board); i++) {
1517                 devpriv->ai_dma_desc[i].pci_start_addr =
1518                         cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1519                 if (board->layout == LAYOUT_4020)
1520                         devpriv->ai_dma_desc[i].local_start_addr =
1521                                 cpu_to_le32(devpriv->local1_iobase +
1522                                             ADC_FIFO_REG);
1523                 else
1524                         devpriv->ai_dma_desc[i].local_start_addr =
1525                                 cpu_to_le32(devpriv->local0_iobase +
1526                                             ADC_FIFO_REG);
1527                 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1528                 devpriv->ai_dma_desc[i].next =
1529                         cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1530                                      ((i + 1) % ai_dma_ring_count(board)) *
1531                                      sizeof(devpriv->ai_dma_desc[0])) |
1532                                     PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1533                                     PLX_XFER_LOCAL_TO_PCI);
1534         }
1535         if (ao_cmd_is_supported(board)) {
1536                 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1537                         devpriv->ao_dma_desc[i].pci_start_addr =
1538                                 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1539                         devpriv->ao_dma_desc[i].local_start_addr =
1540                                 cpu_to_le32(devpriv->local0_iobase +
1541                                             DAC_FIFO_REG);
1542                         devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1543                         devpriv->ao_dma_desc[i].next =
1544                                 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1545                                              ((i + 1) % (AO_DMA_RING_COUNT)) *
1546                                              sizeof(devpriv->ao_dma_desc[0])) |
1547                                             PLX_DESC_IN_PCI_BIT |
1548                                             PLX_INTR_TERM_COUNT);
1549                 }
1550         }
1551         return 0;
1552 }
1553 
1554 static void cb_pcidas64_free_dma(struct comedi_device *dev)
1555 {
1556         const struct pcidas64_board *board = dev->board_ptr;
1557         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1558         struct pcidas64_private *devpriv = dev->private;
1559         int i;
1560 
1561         if (!devpriv)
1562                 return;
1563 
1564         /* free pci dma buffers */
1565         for (i = 0; i < ai_dma_ring_count(board); i++) {
1566                 if (devpriv->ai_buffer[i])
1567                         pci_free_consistent(pcidev,
1568                                             DMA_BUFFER_SIZE,
1569                                             devpriv->ai_buffer[i],
1570                                             devpriv->ai_buffer_bus_addr[i]);
1571         }
1572         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1573                 if (devpriv->ao_buffer[i])
1574                         pci_free_consistent(pcidev,
1575                                             DMA_BUFFER_SIZE,
1576                                             devpriv->ao_buffer[i],
1577                                             devpriv->ao_buffer_bus_addr[i]);
1578         }
1579         /* free dma descriptors */
1580         if (devpriv->ai_dma_desc)
1581                 pci_free_consistent(pcidev,
1582                                     sizeof(struct plx_dma_desc) *
1583                                     ai_dma_ring_count(board),
1584                                     devpriv->ai_dma_desc,
1585                                     devpriv->ai_dma_desc_bus_addr);
1586         if (devpriv->ao_dma_desc)
1587                 pci_free_consistent(pcidev,
1588                                     sizeof(struct plx_dma_desc) *
1589                                     AO_DMA_RING_COUNT,
1590                                     devpriv->ao_dma_desc,
1591                                     devpriv->ao_dma_desc_bus_addr);
1592 }
1593 
1594 static inline void warn_external_queue(struct comedi_device *dev)
1595 {
1596         dev_err(dev->class_dev,
1597                 "AO command and AI external channel queue cannot be used simultaneously\n");
1598         dev_err(dev->class_dev,
1599                 "Use internal AI channel queue (channels must be consecutive and use same range/aref)\n");
1600 }
1601 
1602 /*
1603  * their i2c requires a huge delay on setting clock or data high for some reason
1604  */
1605 static const int i2c_high_udelay = 1000;
1606 static const int i2c_low_udelay = 10;
1607 
1608 /* set i2c data line high or low */
1609 static void i2c_set_sda(struct comedi_device *dev, int state)
1610 {
1611         struct pcidas64_private *devpriv = dev->private;
1612         static const int data_bit = CTL_EE_W;
1613         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1614                                          PLX_CONTROL_REG;
1615 
1616         if (state) {
1617                 /*  set data line high */
1618                 devpriv->plx_control_bits &= ~data_bit;
1619                 writel(devpriv->plx_control_bits, plx_control_addr);
1620                 udelay(i2c_high_udelay);
1621         } else {                /*  set data line low */
1622 
1623                 devpriv->plx_control_bits |= data_bit;
1624                 writel(devpriv->plx_control_bits, plx_control_addr);
1625                 udelay(i2c_low_udelay);
1626         }
1627 }
1628 
1629 /* set i2c clock line high or low */
1630 static void i2c_set_scl(struct comedi_device *dev, int state)
1631 {
1632         struct pcidas64_private *devpriv = dev->private;
1633         static const int clock_bit = CTL_USERO;
1634         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1635                                          PLX_CONTROL_REG;
1636 
1637         if (state) {
1638                 /*  set clock line high */
1639                 devpriv->plx_control_bits &= ~clock_bit;
1640                 writel(devpriv->plx_control_bits, plx_control_addr);
1641                 udelay(i2c_high_udelay);
1642         } else {                /*  set clock line low */
1643 
1644                 devpriv->plx_control_bits |= clock_bit;
1645                 writel(devpriv->plx_control_bits, plx_control_addr);
1646                 udelay(i2c_low_udelay);
1647         }
1648 }
1649 
1650 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
1651 {
1652         uint8_t bit;
1653         unsigned int num_bits = 8;
1654 
1655         for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1656                 i2c_set_scl(dev, 0);
1657                 if ((byte & bit))
1658                         i2c_set_sda(dev, 1);
1659                 else
1660                         i2c_set_sda(dev, 0);
1661                 i2c_set_scl(dev, 1);
1662         }
1663 }
1664 
1665 /* we can't really read the lines, so fake it */
1666 static int i2c_read_ack(struct comedi_device *dev)
1667 {
1668         i2c_set_scl(dev, 0);
1669         i2c_set_sda(dev, 1);
1670         i2c_set_scl(dev, 1);
1671 
1672         return 0;               /*  return fake acknowledge bit */
1673 }
1674 
1675 /* send start bit */
1676 static void i2c_start(struct comedi_device *dev)
1677 {
1678         i2c_set_scl(dev, 1);
1679         i2c_set_sda(dev, 1);
1680         i2c_set_sda(dev, 0);
1681 }
1682 
1683 /* send stop bit */
1684 static void i2c_stop(struct comedi_device *dev)
1685 {
1686         i2c_set_scl(dev, 0);
1687         i2c_set_sda(dev, 0);
1688         i2c_set_scl(dev, 1);
1689         i2c_set_sda(dev, 1);
1690 }
1691 
1692 static void i2c_write(struct comedi_device *dev, unsigned int address,
1693                       const uint8_t *data, unsigned int length)
1694 {
1695         struct pcidas64_private *devpriv = dev->private;
1696         unsigned int i;
1697         uint8_t bitstream;
1698         static const int read_bit = 0x1;
1699 
1700         /*
1701          * XXX need mutex to prevent simultaneous attempts to access
1702          * eeprom and i2c bus
1703          */
1704 
1705         /*  make sure we dont send anything to eeprom */
1706         devpriv->plx_control_bits &= ~CTL_EE_CS;
1707 
1708         i2c_stop(dev);
1709         i2c_start(dev);
1710 
1711         /*  send address and write bit */
1712         bitstream = (address << 1) & ~read_bit;
1713         i2c_write_byte(dev, bitstream);
1714 
1715         /*  get acknowledge */
1716         if (i2c_read_ack(dev) != 0) {
1717                 dev_err(dev->class_dev, "failed: no acknowledge\n");
1718                 i2c_stop(dev);
1719                 return;
1720         }
1721         /*  write data bytes */
1722         for (i = 0; i < length; i++) {
1723                 i2c_write_byte(dev, data[i]);
1724                 if (i2c_read_ack(dev) != 0) {
1725                         dev_err(dev->class_dev, "failed: no acknowledge\n");
1726                         i2c_stop(dev);
1727                         return;
1728                 }
1729         }
1730         i2c_stop(dev);
1731 }
1732 
1733 static int cb_pcidas64_ai_eoc(struct comedi_device *dev,
1734                               struct comedi_subdevice *s,
1735                               struct comedi_insn *insn,
1736                               unsigned long context)
1737 {
1738         const struct pcidas64_board *board = dev->board_ptr;
1739         struct pcidas64_private *devpriv = dev->private;
1740         unsigned int status;
1741 
1742         status = readw(devpriv->main_iobase + HW_STATUS_REG);
1743         if (board->layout == LAYOUT_4020) {
1744                 status = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG);
1745                 if (status)
1746                         return 0;
1747         } else {
1748                 if (pipe_full_bits(status))
1749                         return 0;
1750         }
1751         return -EBUSY;
1752 }
1753 
1754 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1755                     struct comedi_insn *insn, unsigned int *data)
1756 {
1757         const struct pcidas64_board *board = dev->board_ptr;
1758         struct pcidas64_private *devpriv = dev->private;
1759         unsigned int bits = 0, n;
1760         unsigned int channel, range, aref;
1761         unsigned long flags;
1762         int ret;
1763 
1764         channel = CR_CHAN(insn->chanspec);
1765         range = CR_RANGE(insn->chanspec);
1766         aref = CR_AREF(insn->chanspec);
1767 
1768         /*  disable card's analog input interrupt sources and pacing */
1769         /*  4020 generates dac done interrupts even though they are disabled */
1770         disable_ai_pacing(dev);
1771 
1772         spin_lock_irqsave(&dev->spinlock, flags);
1773         if (insn->chanspec & CR_ALT_FILTER)
1774                 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1775         else
1776                 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1777         writew(devpriv->adc_control1_bits,
1778                devpriv->main_iobase + ADC_CONTROL1_REG);
1779         spin_unlock_irqrestore(&dev->spinlock, flags);
1780 
1781         if (board->layout != LAYOUT_4020) {
1782                 /*  use internal queue */
1783                 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1784                 writew(devpriv->hw_config_bits,
1785                        devpriv->main_iobase + HW_CONFIG_REG);
1786 
1787                 /*  ALT_SOURCE is internal calibration reference */
1788                 if (insn->chanspec & CR_ALT_SOURCE) {
1789                         unsigned int cal_en_bit;
1790 
1791                         if (board->layout == LAYOUT_60XX)
1792                                 cal_en_bit = CAL_EN_60XX_BIT;
1793                         else
1794                                 cal_en_bit = CAL_EN_64XX_BIT;
1795                         /*
1796                          * select internal reference source to connect
1797                          * to channel 0
1798                          */
1799                         writew(cal_en_bit |
1800                                adc_src_bits(devpriv->calibration_source),
1801                                devpriv->main_iobase + CALIBRATION_REG);
1802                 } else {
1803                         /*
1804                          * make sure internal calibration source
1805                          * is turned off
1806                          */
1807                         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1808                 }
1809                 /*  load internal queue */
1810                 bits = 0;
1811                 /*  set gain */
1812                 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1813                 /*  set single-ended / differential */
1814                 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1815                 if (aref == AREF_COMMON)
1816                         bits |= ADC_COMMON_BIT;
1817                 bits |= adc_chan_bits(channel);
1818                 /*  set stop channel */
1819                 writew(adc_chan_bits(channel),
1820                        devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1821                 /*  set start channel, and rest of settings */
1822                 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1823         } else {
1824                 uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1825 
1826                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1827                 if (insn->chanspec & CR_ALT_SOURCE) {
1828                         devpriv->i2c_cal_range_bits |=
1829                                 adc_src_4020_bits(devpriv->calibration_source);
1830                 } else {        /* select BNC inputs */
1831                         devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1832                 }
1833                 /*  select range */
1834                 if (range == 0)
1835                         devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1836                 else
1837                         devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1838                 /*
1839                  * update calibration/range i2c register only if necessary,
1840                  * as it is very slow
1841                  */
1842                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1843                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1844 
1845                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1846                                   sizeof(i2c_data));
1847                 }
1848 
1849                 /*
1850                  * 4020 manual asks that sample interval register to be set
1851                  * before writing to convert register.
1852                  * Using somewhat arbitrary setting of 4 master clock ticks
1853                  * = 0.1 usec
1854                  */
1855                 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1856                 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1857         }
1858 
1859         for (n = 0; n < insn->n; n++) {
1860                 /*  clear adc buffer (inside loop for 4020 sake) */
1861                 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1862 
1863                 /* trigger conversion, bits sent only matter for 4020 */
1864                 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1865                        devpriv->main_iobase + ADC_CONVERT_REG);
1866 
1867                 /*  wait for data */
1868                 ret = comedi_timeout(dev, s, insn, cb_pcidas64_ai_eoc, 0);
1869                 if (ret)
1870                         return ret;
1871 
1872                 if (board->layout == LAYOUT_4020)
1873                         data[n] = readl(dev->mmio + ADC_FIFO_REG) & 0xffff;
1874                 else
1875                         data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1876         }
1877 
1878         return n;
1879 }
1880 
1881 static int ai_config_calibration_source(struct comedi_device *dev,
1882                                         unsigned int *data)
1883 {
1884         const struct pcidas64_board *board = dev->board_ptr;
1885         struct pcidas64_private *devpriv = dev->private;
1886         unsigned int source = data[1];
1887         int num_calibration_sources;
1888 
1889         if (board->layout == LAYOUT_60XX)
1890                 num_calibration_sources = 16;
1891         else
1892                 num_calibration_sources = 8;
1893         if (source >= num_calibration_sources) {
1894                 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1895                         source);
1896                 return -EINVAL;
1897         }
1898 
1899         devpriv->calibration_source = source;
1900 
1901         return 2;
1902 }
1903 
1904 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1905 {
1906         const struct pcidas64_board *board = dev->board_ptr;
1907         int fifo_size;
1908         const struct hw_fifo_info *const fifo = board->ai_fifo;
1909         unsigned int block_size, requested_block_size;
1910         int retval;
1911 
1912         requested_block_size = data[1];
1913 
1914         if (requested_block_size) {
1915                 fifo_size = requested_block_size * fifo->num_segments /
1916                             bytes_in_sample;
1917 
1918                 retval = set_ai_fifo_size(dev, fifo_size);
1919                 if (retval < 0)
1920                         return retval;
1921         }
1922 
1923         block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1924 
1925         data[1] = block_size;
1926 
1927         return 2;
1928 }
1929 
1930 static int ai_config_master_clock_4020(struct comedi_device *dev,
1931                                        unsigned int *data)
1932 {
1933         struct pcidas64_private *devpriv = dev->private;
1934         unsigned int divisor = data[4];
1935         int retval = 0;
1936 
1937         if (divisor < 2) {
1938                 divisor = 2;
1939                 retval = -EAGAIN;
1940         }
1941 
1942         switch (data[1]) {
1943         case COMEDI_EV_SCAN_BEGIN:
1944                 devpriv->ext_clock.divisor = divisor;
1945                 devpriv->ext_clock.chanspec = data[2];
1946                 break;
1947         default:
1948                 return -EINVAL;
1949         }
1950 
1951         data[4] = divisor;
1952 
1953         return retval ? retval : 5;
1954 }
1955 
1956 /* XXX could add support for 60xx series */
1957 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1958 {
1959         const struct pcidas64_board *board = dev->board_ptr;
1960 
1961         switch (board->layout) {
1962         case LAYOUT_4020:
1963                 return ai_config_master_clock_4020(dev, data);
1964         default:
1965                 return -EINVAL;
1966         }
1967 
1968         return -EINVAL;
1969 }
1970 
1971 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1972                           struct comedi_insn *insn, unsigned int *data)
1973 {
1974         int id = data[0];
1975 
1976         switch (id) {
1977         case INSN_CONFIG_ALT_SOURCE:
1978                 return ai_config_calibration_source(dev, data);
1979         case INSN_CONFIG_BLOCK_SIZE:
1980                 return ai_config_block_size(dev, data);
1981         case INSN_CONFIG_TIMER_1:
1982                 return ai_config_master_clock(dev, data);
1983         default:
1984                 return -EINVAL;
1985         }
1986         return -EINVAL;
1987 }
1988 
1989 /*
1990  * Gets nearest achievable timing given master clock speed, does not
1991  * take into account possible minimum/maximum divisor values.  Used
1992  * by other timing checking functions.
1993  */
1994 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
1995 {
1996         unsigned int divisor;
1997 
1998         switch (flags & CMDF_ROUND_MASK) {
1999         case CMDF_ROUND_UP:
2000                 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
2001                 break;
2002         case CMDF_ROUND_DOWN:
2003                 divisor = ns / TIMER_BASE;
2004                 break;
2005         case CMDF_ROUND_NEAREST:
2006         default:
2007                 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
2008                 break;
2009         }
2010         return divisor;
2011 }
2012 
2013 /*
2014  * utility function that rounds desired timing to an achievable time, and
2015  * sets cmd members appropriately.
2016  * adc paces conversions from master clock by dividing by (x + 3) where x is
2017  * 24 bit number
2018  */
2019 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
2020 {
2021         const struct pcidas64_board *board = dev->board_ptr;
2022         unsigned long long convert_divisor = 0;
2023         unsigned int scan_divisor;
2024         static const int min_convert_divisor = 3;
2025         static const int max_convert_divisor =
2026                 max_counter_value + min_convert_divisor;
2027         static const int min_scan_divisor_4020 = 2;
2028         unsigned long long max_scan_divisor, min_scan_divisor;
2029 
2030         if (cmd->convert_src == TRIG_TIMER) {
2031                 if (board->layout == LAYOUT_4020) {
2032                         cmd->convert_arg = 0;
2033                 } else {
2034                         convert_divisor = get_divisor(cmd->convert_arg,
2035                                                       cmd->flags);
2036                         if (convert_divisor > max_convert_divisor)
2037                                 convert_divisor = max_convert_divisor;
2038                         if (convert_divisor < min_convert_divisor)
2039                                 convert_divisor = min_convert_divisor;
2040                         cmd->convert_arg = convert_divisor * TIMER_BASE;
2041                 }
2042         } else if (cmd->convert_src == TRIG_NOW) {
2043                 cmd->convert_arg = 0;
2044         }
2045 
2046         if (cmd->scan_begin_src == TRIG_TIMER) {
2047                 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
2048                 if (cmd->convert_src == TRIG_TIMER) {
2049                         min_scan_divisor = convert_divisor * cmd->chanlist_len;
2050                         max_scan_divisor =
2051                                 (convert_divisor * cmd->chanlist_len - 1) +
2052                                 max_counter_value;
2053                 } else {
2054                         min_scan_divisor = min_scan_divisor_4020;
2055                         max_scan_divisor = max_counter_value + min_scan_divisor;
2056                 }
2057                 if (scan_divisor > max_scan_divisor)
2058                         scan_divisor = max_scan_divisor;
2059                 if (scan_divisor < min_scan_divisor)
2060                         scan_divisor = min_scan_divisor;
2061                 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
2062         }
2063 }
2064 
2065 static int cb_pcidas64_ai_check_chanlist(struct comedi_device *dev,
2066                                          struct comedi_subdevice *s,
2067                                          struct comedi_cmd *cmd)
2068 {
2069         const struct pcidas64_board *board = dev->board_ptr;
2070         unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
2071         int i;
2072 
2073         for (i = 1; i < cmd->chanlist_len; i++) {
2074                 unsigned int aref = CR_AREF(cmd->chanlist[i]);
2075 
2076                 if (aref != aref0) {
2077                         dev_dbg(dev->class_dev,
2078                                 "all elements in chanlist must use the same analog reference\n");
2079                         return -EINVAL;
2080                 }
2081         }
2082 
2083         if (board->layout == LAYOUT_4020) {
2084                 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
2085 
2086                 for (i = 1; i < cmd->chanlist_len; i++) {
2087                         unsigned int chan = CR_CHAN(cmd->chanlist[i]);
2088 
2089                         if (chan != (chan0 + i)) {
2090                                 dev_dbg(dev->class_dev,
2091                                         "chanlist must use consecutive channels\n");
2092                                 return -EINVAL;
2093                         }
2094                 }
2095                 if (cmd->chanlist_len == 3) {
2096                         dev_dbg(dev->class_dev,
2097                                 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels\n");
2098                         return -EINVAL;
2099                 }
2100         }
2101 
2102         return 0;
2103 }
2104 
2105 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2106                       struct comedi_cmd *cmd)
2107 {
2108         const struct pcidas64_board *board = dev->board_ptr;
2109         int err = 0;
2110         unsigned int tmp_arg, tmp_arg2;
2111         unsigned int triggers;
2112 
2113         /* Step 1 : check if triggers are trivially valid */
2114 
2115         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2116 
2117         triggers = TRIG_TIMER;
2118         if (board->layout == LAYOUT_4020)
2119                 triggers |= TRIG_OTHER;
2120         else
2121                 triggers |= TRIG_FOLLOW;
2122         err |= comedi_check_trigger_src(&cmd->scan_begin_src, triggers);
2123 
2124         triggers = TRIG_TIMER;
2125         if (board->layout == LAYOUT_4020)
2126                 triggers |= TRIG_NOW;
2127         else
2128                 triggers |= TRIG_EXT;
2129         err |= comedi_check_trigger_src(&cmd->convert_src, triggers);
2130         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2131         err |= comedi_check_trigger_src(&cmd->stop_src,
2132                                         TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2133 
2134         if (err)
2135                 return 1;
2136 
2137         /* Step 2a : make sure trigger sources are unique */
2138 
2139         err |= comedi_check_trigger_is_unique(cmd->start_src);
2140         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2141         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2142         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2143 
2144         /* Step 2b : and mutually compatible */
2145 
2146         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2147                 err |= -EINVAL;
2148 
2149         if (err)
2150                 return 2;
2151 
2152         /* Step 3: check if arguments are trivially valid */
2153 
2154         switch (cmd->start_src) {
2155         case TRIG_NOW:
2156                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2157                 break;
2158         case TRIG_EXT:
2159                 /*
2160                  * start_arg is the CR_CHAN | CR_INVERT of the
2161                  * external trigger.
2162                  */
2163                 break;
2164         }
2165 
2166         if (cmd->convert_src == TRIG_TIMER) {
2167                 if (board->layout == LAYOUT_4020) {
2168                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2169                                                            0);
2170                 } else {
2171                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2172                                                             board->ai_speed);
2173                         /*
2174                          * if scans are timed faster than conversion rate
2175                          * allows
2176                          */
2177                         if (cmd->scan_begin_src == TRIG_TIMER) {
2178                                 err |= comedi_check_trigger_arg_min(
2179                                                 &cmd->scan_begin_arg,
2180                                                 cmd->convert_arg *
2181                                                 cmd->chanlist_len);
2182                         }
2183                 }
2184         }
2185 
2186         err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1);
2187         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2188                                            cmd->chanlist_len);
2189 
2190         switch (cmd->stop_src) {
2191         case TRIG_EXT:
2192                 break;
2193         case TRIG_COUNT:
2194                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2195                 break;
2196         case TRIG_NONE:
2197                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2198                 break;
2199         default:
2200                 break;
2201         }
2202 
2203         if (err)
2204                 return 3;
2205 
2206         /* step 4: fix up any arguments */
2207 
2208         if (cmd->convert_src == TRIG_TIMER) {
2209                 tmp_arg = cmd->convert_arg;
2210                 tmp_arg2 = cmd->scan_begin_arg;
2211                 check_adc_timing(dev, cmd);
2212                 if (tmp_arg != cmd->convert_arg)
2213                         err++;
2214                 if (tmp_arg2 != cmd->scan_begin_arg)
2215                         err++;
2216         }
2217 
2218         if (err)
2219                 return 4;
2220 
2221         /* Step 5: check channel list if it exists */
2222         if (cmd->chanlist && cmd->chanlist_len > 0)
2223                 err |= cb_pcidas64_ai_check_chanlist(dev, s, cmd);
2224 
2225         if (err)
2226                 return 5;
2227 
2228         return 0;
2229 }
2230 
2231 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2232 {
2233 /* disable for now until I work out a race */
2234         return 0;
2235 
2236         if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2237                 return 1;
2238 
2239         return 0;
2240 }
2241 
2242 static void setup_sample_counters(struct comedi_device *dev,
2243                                   struct comedi_cmd *cmd)
2244 {
2245         struct pcidas64_private *devpriv = dev->private;
2246 
2247         /*  load hardware conversion counter */
2248         if (use_hw_sample_counter(cmd)) {
2249                 writew(cmd->stop_arg & 0xffff,
2250                        devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2251                 writew((cmd->stop_arg >> 16) & 0xff,
2252                        devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2253         } else {
2254                 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2255         }
2256 }
2257 
2258 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2259 {
2260         const struct pcidas64_board *board = dev->board_ptr;
2261         struct pcidas64_private *devpriv = dev->private;
2262         unsigned int num_samples;
2263 
2264         num_samples = devpriv->ai_fifo_segment_length *
2265                       board->ai_fifo->sample_packing_ratio;
2266         if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2267                 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2268 
2269         return num_samples;
2270 }
2271 
2272 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2273                                         const struct comedi_cmd *cmd)
2274 {
2275         /*  supposed to load counter with desired divisor minus 3 */
2276         return cmd->convert_arg / TIMER_BASE - 3;
2277 }
2278 
2279 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2280                                      struct comedi_cmd *cmd)
2281 {
2282         uint32_t count;
2283 
2284         /*  figure out how long we need to delay at end of scan */
2285         switch (cmd->scan_begin_src) {
2286         case TRIG_TIMER:
2287                 count = (cmd->scan_begin_arg -
2288                          (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2289                         TIMER_BASE;
2290                 break;
2291         case TRIG_FOLLOW:
2292                 count = cmd->convert_arg / TIMER_BASE;
2293                 break;
2294         default:
2295                 return 0;
2296         }
2297         return count - 3;
2298 }
2299 
2300 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2301                                         struct comedi_cmd *cmd)
2302 {
2303         struct pcidas64_private *devpriv = dev->private;
2304         unsigned int divisor;
2305 
2306         switch (cmd->scan_begin_src) {
2307         case TRIG_TIMER:
2308                 divisor = cmd->scan_begin_arg / TIMER_BASE;
2309                 break;
2310         case TRIG_OTHER:
2311                 divisor = devpriv->ext_clock.divisor;
2312                 break;
2313         default:                /*  should never happen */
2314                 dev_err(dev->class_dev, "bug! failed to set ai pacing!\n");
2315                 divisor = 1000;
2316                 break;
2317         }
2318 
2319         /*  supposed to load counter with desired divisor minus 2 for 4020 */
2320         return divisor - 2;
2321 }
2322 
2323 static void select_master_clock_4020(struct comedi_device *dev,
2324                                      const struct comedi_cmd *cmd)
2325 {
2326         struct pcidas64_private *devpriv = dev->private;
2327 
2328         /*  select internal/external master clock */
2329         devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2330         if (cmd->scan_begin_src == TRIG_OTHER) {
2331                 int chanspec = devpriv->ext_clock.chanspec;
2332 
2333                 if (CR_CHAN(chanspec))
2334                         devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2335                 else
2336                         devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2337         } else {
2338                 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2339         }
2340         writew(devpriv->hw_config_bits,
2341                devpriv->main_iobase + HW_CONFIG_REG);
2342 }
2343 
2344 static void select_master_clock(struct comedi_device *dev,
2345                                 const struct comedi_cmd *cmd)
2346 {
2347         const struct pcidas64_board *board = dev->board_ptr;
2348 
2349         switch (board->layout) {
2350         case LAYOUT_4020:
2351                 select_master_clock_4020(dev, cmd);
2352                 break;
2353         default:
2354                 break;
2355         }
2356 }
2357 
2358 static inline void dma_start_sync(struct comedi_device *dev,
2359                                   unsigned int channel)
2360 {
2361         struct pcidas64_private *devpriv = dev->private;
2362         unsigned long flags;
2363 
2364         /*  spinlock for plx dma control/status reg */
2365         spin_lock_irqsave(&dev->spinlock, flags);
2366         if (channel)
2367                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2368                        PLX_CLEAR_DMA_INTR_BIT,
2369                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2370         else
2371                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2372                        PLX_CLEAR_DMA_INTR_BIT,
2373                        devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2374         spin_unlock_irqrestore(&dev->spinlock, flags);
2375 }
2376 
2377 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2378 {
2379         const struct pcidas64_board *board = dev->board_ptr;
2380         struct pcidas64_private *devpriv = dev->private;
2381         uint32_t convert_counter = 0, scan_counter = 0;
2382 
2383         check_adc_timing(dev, cmd);
2384 
2385         select_master_clock(dev, cmd);
2386 
2387         if (board->layout == LAYOUT_4020) {
2388                 convert_counter = ai_convert_counter_4020(dev, cmd);
2389         } else {
2390                 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2391                 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2392         }
2393 
2394         /*  load lower 16 bits of convert interval */
2395         writew(convert_counter & 0xffff,
2396                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2397         /*  load upper 8 bits of convert interval */
2398         writew((convert_counter >> 16) & 0xff,
2399                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2400         /*  load lower 16 bits of scan delay */
2401         writew(scan_counter & 0xffff,
2402                devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2403         /*  load upper 8 bits of scan delay */
2404         writew((scan_counter >> 16) & 0xff,
2405                devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2406 }
2407 
2408 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2409 {
2410         int i;
2411 
2412         for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2413                 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2414                     CR_CHAN(cmd->chanlist[i]) + 1)
2415                         return 0;
2416                 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2417                     CR_RANGE(cmd->chanlist[i]))
2418                         return 0;
2419                 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2420                         return 0;
2421         }
2422         return 1;
2423 }
2424 
2425 static int setup_channel_queue(struct comedi_device *dev,
2426                                const struct comedi_cmd *cmd)
2427 {
2428         const struct pcidas64_board *board = dev->board_ptr;
2429         struct pcidas64_private *devpriv = dev->private;
2430         unsigned short bits;
2431         int i;
2432 
2433         if (board->layout != LAYOUT_4020) {
2434                 if (use_internal_queue_6xxx(cmd)) {
2435                         devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2436                         writew(devpriv->hw_config_bits,
2437                                devpriv->main_iobase + HW_CONFIG_REG);
2438                         bits = 0;
2439                         /*  set channel */
2440                         bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2441                         /*  set gain */
2442                         bits |= ai_range_bits_6xxx(dev,
2443                                                    CR_RANGE(cmd->chanlist[0]));
2444                         /*  set single-ended / differential */
2445                         bits |= se_diff_bit_6xxx(dev,
2446                                                  CR_AREF(cmd->chanlist[0]) ==
2447                                                  AREF_DIFF);
2448                         if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2449                                 bits |= ADC_COMMON_BIT;
2450                         /*  set stop channel */
2451                         writew(adc_chan_bits
2452                                (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2453                                devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2454                         /*  set start channel, and rest of settings */
2455                         writew(bits,
2456                                devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2457                 } else {
2458                         /*  use external queue */
2459                         if (dev->write_subdev && dev->write_subdev->busy) {
2460                                 warn_external_queue(dev);
2461                                 return -EBUSY;
2462                         }
2463                         devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2464                         writew(devpriv->hw_config_bits,
2465                                devpriv->main_iobase + HW_CONFIG_REG);
2466                         /*  clear DAC buffer to prevent weird interactions */
2467                         writew(0,
2468                                devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2469                         /*  clear queue pointer */
2470                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2471                         /*  load external queue */
2472                         for (i = 0; i < cmd->chanlist_len; i++) {
2473                                 bits = 0;
2474                                 /*  set channel */
2475                                 bits |= adc_chan_bits(CR_CHAN(cmd->
2476                                                               chanlist[i]));
2477                                 /*  set gain */
2478                                 bits |= ai_range_bits_6xxx(dev,
2479                                                            CR_RANGE(cmd->
2480                                                                     chanlist
2481                                                                     [i]));
2482                                 /*  set single-ended / differential */
2483                                 bits |= se_diff_bit_6xxx(dev,
2484                                                          CR_AREF(cmd->
2485                                                                  chanlist[i]) ==
2486                                                          AREF_DIFF);
2487                                 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2488                                         bits |= ADC_COMMON_BIT;
2489                                 /*  mark end of queue */
2490                                 if (i == cmd->chanlist_len - 1)
2491                                         bits |= QUEUE_EOSCAN_BIT |
2492                                                 QUEUE_EOSEQ_BIT;
2493                                 writew(bits,
2494                                        devpriv->main_iobase +
2495                                        ADC_QUEUE_FIFO_REG);
2496                         }
2497                         /*
2498                          * doing a queue clear is not specified in board docs,
2499                          * but required for reliable operation
2500                          */
2501                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2502                         /*  prime queue holding register */
2503                         writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2504                 }
2505         } else {
2506                 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2507 
2508                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2509                 /* select BNC inputs */
2510                 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2511                 /*  select ranges */
2512                 for (i = 0; i < cmd->chanlist_len; i++) {
2513                         unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2514                         unsigned int range = CR_RANGE(cmd->chanlist[i]);
2515 
2516                         if (range == 0)
2517                                 devpriv->i2c_cal_range_bits |=
2518                                         attenuate_bit(channel);
2519                         else
2520                                 devpriv->i2c_cal_range_bits &=
2521                                         ~attenuate_bit(channel);
2522                 }
2523                 /*
2524                  * update calibration/range i2c register only if necessary,
2525                  * as it is very slow
2526                  */
2527                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2528                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2529 
2530                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2531                                   sizeof(i2c_data));
2532                 }
2533         }
2534         return 0;
2535 }
2536 
2537 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2538                                              unsigned int dma_channel,
2539                                              unsigned int descriptor_bits)
2540 {
2541         struct pcidas64_private *devpriv = dev->private;
2542 
2543         /*
2544          * The transfer size, pci address, and local address registers
2545          * are supposedly unused during chained dma,
2546          * but I have found that left over values from last operation
2547          * occasionally cause problems with transfer of first dma
2548          * block.  Initializing them to zero seems to fix the problem.
2549          */
2550         if (dma_channel) {
2551                 writel(0,
2552                        devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2553                 writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2554                 writel(0,
2555                        devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2556                 writel(descriptor_bits,
2557                        devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2558         } else {
2559                 writel(0,
2560                        devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2561                 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2562                 writel(0,
2563                        devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2564                 writel(descriptor_bits,
2565                        devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2566         }
2567 }
2568 
2569 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2570 {
2571         const struct pcidas64_board *board = dev->board_ptr;
2572         struct pcidas64_private *devpriv = dev->private;
2573         struct comedi_async *async = s->async;
2574         struct comedi_cmd *cmd = &async->cmd;
2575         uint32_t bits;
2576         unsigned int i;
2577         unsigned long flags;
2578         int retval;
2579 
2580         disable_ai_pacing(dev);
2581         abort_dma(dev, 1);
2582 
2583         retval = setup_channel_queue(dev, cmd);
2584         if (retval < 0)
2585                 return retval;
2586 
2587         /*  make sure internal calibration source is turned off */
2588         writew(0, devpriv->main_iobase + CALIBRATION_REG);
2589 
2590         set_ai_pacing(dev, cmd);
2591 
2592         setup_sample_counters(dev, cmd);
2593 
2594         enable_ai_interrupts(dev, cmd);
2595 
2596         spin_lock_irqsave(&dev->spinlock, flags);
2597         /* set mode, allow conversions through software gate */
2598         devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2599         devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2600         if (board->layout != LAYOUT_4020) {
2601                 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2602                 if (cmd->convert_src == TRIG_EXT)
2603                         /*  good old mode 13 */
2604                         devpriv->adc_control1_bits |= adc_mode_bits(13);
2605                 else
2606                         /*  mode 8.  What else could you need? */
2607                         devpriv->adc_control1_bits |= adc_mode_bits(8);
2608         } else {
2609                 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2610                 if (cmd->chanlist_len == 4)
2611                         devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2612                 else if (cmd->chanlist_len == 2)
2613                         devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2614                 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2615                 devpriv->adc_control1_bits |=
2616                         adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2617                 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2618                 devpriv->adc_control1_bits |=
2619                         adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2620                                                       [cmd->chanlist_len - 1]));
2621         }
2622         writew(devpriv->adc_control1_bits,
2623                devpriv->main_iobase + ADC_CONTROL1_REG);
2624         spin_unlock_irqrestore(&dev->spinlock, flags);
2625 
2626         /*  clear adc buffer */
2627         writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2628 
2629         if ((cmd->flags & CMDF_WAKE_EOS) == 0 ||
2630             board->layout == LAYOUT_4020) {
2631                 devpriv->ai_dma_index = 0;
2632 
2633                 /*  set dma transfer size */
2634                 for (i = 0; i < ai_dma_ring_count(board); i++)
2635                         devpriv->ai_dma_desc[i].transfer_size =
2636                                 cpu_to_le32(dma_transfer_size(dev) *
2637                                             sizeof(uint16_t));
2638 
2639                 /*  give location of first dma descriptor */
2640                 load_first_dma_descriptor(dev, 1,
2641                                           devpriv->ai_dma_desc_bus_addr |
2642                                           PLX_DESC_IN_PCI_BIT |
2643                                           PLX_INTR_TERM_COUNT |
2644                                           PLX_XFER_LOCAL_TO_PCI);
2645 
2646                 dma_start_sync(dev, 1);
2647         }
2648 
2649         if (board->layout == LAYOUT_4020) {
2650                 /* set source for external triggers */
2651                 bits = 0;
2652                 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2653                         bits |= EXT_START_TRIG_BNC_BIT;
2654                 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2655                         bits |= EXT_STOP_TRIG_BNC_BIT;
2656                 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2657         }
2658 
2659         spin_lock_irqsave(&dev->spinlock, flags);
2660 
2661         /* enable pacing, triggering, etc */
2662         bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2663         if (cmd->flags & CMDF_WAKE_EOS)
2664                 bits |= ADC_DMA_DISABLE_BIT;
2665         /*  set start trigger */
2666         if (cmd->start_src == TRIG_EXT) {
2667                 bits |= ADC_START_TRIG_EXT_BITS;
2668                 if (cmd->start_arg & CR_INVERT)
2669                         bits |= ADC_START_TRIG_FALLING_BIT;
2670         } else if (cmd->start_src == TRIG_NOW) {
2671                 bits |= ADC_START_TRIG_SOFT_BITS;
2672         }
2673         if (use_hw_sample_counter(cmd))
2674                 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2675         writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2676 
2677         devpriv->ai_cmd_running = 1;
2678 
2679         spin_unlock_irqrestore(&dev->spinlock, flags);
2680 
2681         /*  start acquisition */
2682         if (cmd->start_src == TRIG_NOW)
2683                 writew(0, devpriv->main_iobase + ADC_START_REG);
2684 
2685         return 0;
2686 }
2687 
2688 /* read num_samples from 16 bit wide ai fifo */
2689 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2690 {
2691         struct pcidas64_private *devpriv = dev->private;
2692         struct comedi_subdevice *s = dev->read_subdev;
2693         unsigned int i;
2694         uint16_t prepost_bits;
2695         int read_segment, read_index, write_segment, write_index;
2696         int num_samples;
2697 
2698         do {
2699                 /*  get least significant 15 bits */
2700                 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2701                              0x7fff;
2702                 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2703                               0x7fff;
2704                 /*
2705                  * Get most significant bits (grey code).
2706                  * Different boards use different code so use a scheme
2707                  * that doesn't depend on encoding.  This read must
2708                  * occur after reading least significant 15 bits to avoid race
2709                  * with fifo switching to next segment.
2710                  */
2711                 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2712 
2713                 /*
2714                  * if read and write pointers are not on the same fifo segment,
2715                  * read to the end of the read segment
2716                  */
2717                 read_segment = adc_upper_read_ptr_code(prepost_bits);
2718                 write_segment = adc_upper_write_ptr_code(prepost_bits);
2719 
2720                 if (read_segment != write_segment)
2721                         num_samples =
2722                                 devpriv->ai_fifo_segment_length - read_index;
2723                 else
2724                         num_samples = write_index - read_index;
2725                 if (num_samples < 0) {
2726                         dev_err(dev->class_dev,
2727                                 "cb_pcidas64: bug! num_samples < 0\n");
2728                         break;
2729                 }
2730 
2731                 num_samples = comedi_nsamples_left(s, num_samples);
2732                 if (num_samples == 0)
2733                         break;
2734 
2735                 for (i = 0; i < num_samples; i++) {
2736                         unsigned short val;
2737 
2738                         val = readw(devpriv->main_iobase + ADC_FIFO_REG);
2739                         comedi_buf_write_samples(s, &val, 1);
2740                 }
2741 
2742         } while (read_segment != write_segment);
2743 }
2744 
2745 /*
2746  * Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2747  * pointers.  The pci-4020 hardware only supports dma transfers (it only
2748  * supports the use of pio for draining the last remaining points from the
2749  * fifo when a data acquisition operation has completed).
2750  */
2751 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2752 {
2753         struct pcidas64_private *devpriv = dev->private;
2754         struct comedi_subdevice *s = dev->read_subdev;
2755         unsigned int nsamples;
2756         unsigned int i;
2757         uint32_t fifo_data;
2758         int write_code =
2759                 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2760         int read_code =
2761                 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2762 
2763         nsamples = comedi_nsamples_left(s, 100000);
2764         for (i = 0; read_code != write_code && i < nsamples;) {
2765                 unsigned short val;
2766 
2767                 fifo_data = readl(dev->mmio + ADC_FIFO_REG);
2768                 val = fifo_data & 0xffff;
2769                 comedi_buf_write_samples(s, &val, 1);
2770                 i++;
2771                 if (i < nsamples) {
2772                         val = (fifo_data >> 16) & 0xffff;
2773                         comedi_buf_write_samples(s, &val, 1);
2774                         i++;
2775                 }
2776                 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2777                             0x7fff;
2778         }
2779 }
2780 
2781 /* empty fifo */
2782 static void pio_drain_ai_fifo(struct comedi_device *dev)
2783 {
2784         const struct pcidas64_board *board = dev->board_ptr;
2785 
2786         if (board->layout == LAYOUT_4020)
2787                 pio_drain_ai_fifo_32(dev);
2788         else
2789                 pio_drain_ai_fifo_16(dev);
2790 }
2791 
2792 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2793 {
2794         const struct pcidas64_board *board = dev->board_ptr;
2795         struct pcidas64_private *devpriv = dev->private;
2796         struct comedi_subdevice *s = dev->read_subdev;
2797         uint32_t next_transfer_addr;
2798         int j;
2799         int num_samples = 0;
2800         void __iomem *pci_addr_reg;
2801 
2802         if (channel)
2803                 pci_addr_reg =
2804                     devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2805         else
2806                 pci_addr_reg =
2807                     devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2808 
2809         /*  loop until we have read all the full buffers */
2810         for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2811              (next_transfer_addr <
2812               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2813               next_transfer_addr >=
2814               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2815               DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board); j++) {
2816                 /*  transfer data from dma buffer to comedi buffer */
2817                 num_samples = comedi_nsamples_left(s, dma_transfer_size(dev));
2818                 comedi_buf_write_samples(s,
2819                                 devpriv->ai_buffer[devpriv->ai_dma_index],
2820                                 num_samples);
2821                 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2822                                         ai_dma_ring_count(board);
2823         }
2824         /*
2825          * XXX check for dma ring buffer overrun
2826          * (use end-of-chain bit to mark last unused buffer)
2827          */
2828 }
2829 
2830 static void handle_ai_interrupt(struct comedi_device *dev,
2831                                 unsigned short status,
2832                                 unsigned int plx_status)
2833 {
2834         const struct pcidas64_board *board = dev->board_ptr;
2835         struct pcidas64_private *devpriv = dev->private;
2836         struct comedi_subdevice *s = dev->read_subdev;
2837         struct comedi_async *async = s->async;
2838         struct comedi_cmd *cmd = &async->cmd;
2839         uint8_t dma1_status;
2840         unsigned long flags;
2841 
2842         /*  check for fifo overrun */
2843         if (status & ADC_OVERRUN_BIT) {
2844                 dev_err(dev->class_dev, "fifo overrun\n");
2845                 async->events |= COMEDI_CB_ERROR;
2846         }
2847         /*  spin lock makes sure no one else changes plx dma control reg */
2848         spin_lock_irqsave(&dev->spinlock, flags);
2849         dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2850         if (plx_status & ICS_DMA1_A) {  /*  dma chan 1 interrupt */
2851                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2852                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2853 
2854                 if (dma1_status & PLX_DMA_EN_BIT)
2855                         drain_dma_buffers(dev, 1);
2856         }
2857         spin_unlock_irqrestore(&dev->spinlock, flags);
2858 
2859         /*  drain fifo with pio */
2860         if ((status & ADC_DONE_BIT) ||
2861             ((cmd->flags & CMDF_WAKE_EOS) &&
2862              (status & ADC_INTR_PENDING_BIT) &&
2863              (board->layout != LAYOUT_4020))) {
2864                 spin_lock_irqsave(&dev->spinlock, flags);
2865                 if (devpriv->ai_cmd_running) {
2866                         spin_unlock_irqrestore(&dev->spinlock, flags);
2867                         pio_drain_ai_fifo(dev);
2868                 } else {
2869                         spin_unlock_irqrestore(&dev->spinlock, flags);
2870                 }
2871         }
2872         /*  if we are have all the data, then quit */
2873         if ((cmd->stop_src == TRIG_COUNT &&
2874              async->scans_done >= cmd->stop_arg) ||
2875             (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT)))
2876                 async->events |= COMEDI_CB_EOA;
2877 
2878         comedi_handle_events(dev, s);
2879 }
2880 
2881 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2882 {
2883         struct pcidas64_private *devpriv = dev->private;
2884         unsigned int buffer_index;
2885 
2886         if (devpriv->ao_dma_index == 0)
2887                 buffer_index = AO_DMA_RING_COUNT - 1;
2888         else
2889                 buffer_index = devpriv->ao_dma_index - 1;
2890         return buffer_index;
2891 }
2892 
2893 static int last_ao_dma_load_completed(struct comedi_device *dev)
2894 {
2895         struct pcidas64_private *devpriv = dev->private;
2896         unsigned int buffer_index;
2897         unsigned int transfer_address;
2898         unsigned short dma_status;
2899 
2900         buffer_index = prev_ao_dma_index(dev);
2901         dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2902         if ((dma_status & PLX_DMA_DONE_BIT) == 0)
2903                 return 0;
2904 
2905         transfer_address =
2906                 readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2907         if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2908                 return 0;
2909 
2910         return 1;
2911 }
2912 
2913 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2914                                        unsigned short dma_status)
2915 {
2916         if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
2917             (dma_status & PLX_DMA_EN_BIT) == 0)
2918                 return 0;
2919         if (last_ao_dma_load_completed(dev))
2920                 return 0;
2921 
2922         return 1;
2923 }
2924 
2925 static void restart_ao_dma(struct comedi_device *dev)
2926 {
2927         struct pcidas64_private *devpriv = dev->private;
2928         unsigned int dma_desc_bits;
2929 
2930         dma_desc_bits =
2931                 readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2932         dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
2933         load_first_dma_descriptor(dev, 0, dma_desc_bits);
2934 
2935         dma_start_sync(dev, 0);
2936 }
2937 
2938 static unsigned int cb_pcidas64_ao_fill_buffer(struct comedi_device *dev,
2939                                                struct comedi_subdevice *s,
2940                                                unsigned short *dest,
2941                                                unsigned int max_bytes)
2942 {
2943         unsigned int nsamples = comedi_bytes_to_samples(s, max_bytes);
2944         unsigned int actual_bytes;
2945 
2946         nsamples = comedi_nsamples_left(s, nsamples);
2947         actual_bytes = comedi_buf_read_samples(s, dest, nsamples);
2948 
2949         return comedi_bytes_to_samples(s, actual_bytes);
2950 }
2951 
2952 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2953                                        const struct comedi_cmd *cmd)
2954 {
2955         struct pcidas64_private *devpriv = dev->private;
2956         struct comedi_subdevice *s = dev->write_subdev;
2957         unsigned int buffer_index = devpriv->ao_dma_index;
2958         unsigned int prev_buffer_index = prev_ao_dma_index(dev);
2959         unsigned int nsamples;
2960         unsigned int nbytes;
2961         unsigned int next_bits;
2962 
2963         nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
2964                                               devpriv->ao_buffer[buffer_index],
2965                                               DMA_BUFFER_SIZE);
2966         if (nsamples == 0)
2967                 return 0;
2968 
2969         nbytes = comedi_samples_to_bytes(s, nsamples);
2970         devpriv->ao_dma_desc[buffer_index].transfer_size = cpu_to_le32(nbytes);
2971         /* set end of chain bit so we catch underruns */
2972         next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
2973         next_bits |= PLX_END_OF_CHAIN_BIT;
2974         devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
2975         /*
2976          * clear end of chain bit on previous buffer now that we have set it
2977          * for the last buffer
2978          */
2979         next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
2980         next_bits &= ~PLX_END_OF_CHAIN_BIT;
2981         devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
2982 
2983         devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
2984 
2985         return nbytes;
2986 }
2987 
2988 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
2989 {
2990         struct pcidas64_private *devpriv = dev->private;
2991         unsigned int num_bytes;
2992         unsigned int next_transfer_addr;
2993         void __iomem *pci_addr_reg =
2994                 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2995         unsigned int buffer_index;
2996 
2997         do {
2998                 buffer_index = devpriv->ao_dma_index;
2999                 /* don't overwrite data that hasn't been transferred yet */
3000                 next_transfer_addr = readl(pci_addr_reg);
3001                 if (next_transfer_addr >=
3002                     devpriv->ao_buffer_bus_addr[buffer_index] &&
3003                     next_transfer_addr <
3004                     devpriv->ao_buffer_bus_addr[buffer_index] +
3005                     DMA_BUFFER_SIZE)
3006                         return;
3007                 num_bytes = load_ao_dma_buffer(dev, cmd);
3008         } while (num_bytes >= DMA_BUFFER_SIZE);
3009 }
3010 
3011 static void handle_ao_interrupt(struct comedi_device *dev,
3012                                 unsigned short status, unsigned int plx_status)
3013 {
3014         struct pcidas64_private *devpriv = dev->private;
3015         struct comedi_subdevice *s = dev->write_subdev;
3016         struct comedi_async *async;
3017         struct comedi_cmd *cmd;
3018         uint8_t dma0_status;
3019         unsigned long flags;
3020 
3021         /* board might not support ao, in which case write_subdev is NULL */
3022         if (!s)
3023                 return;
3024         async = s->async;
3025         cmd = &async->cmd;
3026 
3027         /*  spin lock makes sure no one else changes plx dma control reg */
3028         spin_lock_irqsave(&dev->spinlock, flags);
3029         dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3030         if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
3031                 if ((dma0_status & PLX_DMA_EN_BIT) &&
3032                     !(dma0_status & PLX_DMA_DONE_BIT))
3033                         writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3034                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3035                 else
3036                         writeb(PLX_CLEAR_DMA_INTR_BIT,
3037                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3038                 spin_unlock_irqrestore(&dev->spinlock, flags);
3039                 if (dma0_status & PLX_DMA_EN_BIT) {
3040                         load_ao_dma(dev, cmd);
3041                         /* try to recover from dma end-of-chain event */
3042                         if (ao_dma_needs_restart(dev, dma0_status))
3043                                 restart_ao_dma(dev);
3044                 }
3045         } else {
3046                 spin_unlock_irqrestore(&dev->spinlock, flags);
3047         }
3048 
3049         if ((status & DAC_DONE_BIT)) {
3050                 if ((cmd->stop_src == TRIG_COUNT &&
3051                      async->scans_done >= cmd->stop_arg) ||
3052                     last_ao_dma_load_completed(dev))
3053                         async->events |= COMEDI_CB_EOA;
3054                 else
3055                         async->events |= COMEDI_CB_ERROR;
3056         }
3057         comedi_handle_events(dev, s);
3058 }
3059 
3060 static irqreturn_t handle_interrupt(int irq, void *d)
3061 {
3062         struct comedi_device *dev = d;
3063         struct pcidas64_private *devpriv = dev->private;
3064         unsigned short status;
3065         uint32_t plx_status;
3066         uint32_t plx_bits;
3067 
3068         plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
3069         status = readw(devpriv->main_iobase + HW_STATUS_REG);
3070 
3071         /*
3072          * an interrupt before all the postconfig stuff gets done could
3073          * cause a NULL dereference if we continue through the
3074          * interrupt handler
3075          */
3076         if (!dev->attached)
3077                 return IRQ_HANDLED;
3078 
3079         handle_ai_interrupt(dev, status, plx_status);
3080         handle_ao_interrupt(dev, status, plx_status);
3081 
3082         /*  clear possible plx9080 interrupt sources */
3083         if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
3084                 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3085                 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3086         }
3087 
3088         return IRQ_HANDLED;
3089 }
3090 
3091 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3092 {
3093         struct pcidas64_private *devpriv = dev->private;
3094         unsigned long flags;
3095 
3096         spin_lock_irqsave(&dev->spinlock, flags);
3097         if (devpriv->ai_cmd_running == 0) {
3098                 spin_unlock_irqrestore(&dev->spinlock, flags);
3099                 return 0;
3100         }
3101         devpriv->ai_cmd_running = 0;
3102         spin_unlock_irqrestore(&dev->spinlock, flags);
3103 
3104         disable_ai_pacing(dev);
3105 
3106         abort_dma(dev, 1);
3107 
3108         return 0;
3109 }
3110 
3111 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3112                     struct comedi_insn *insn, unsigned int *data)
3113 {
3114         const struct pcidas64_board *board = dev->board_ptr;
3115         struct pcidas64_private *devpriv = dev->private;
3116         int chan = CR_CHAN(insn->chanspec);
3117         int range = CR_RANGE(insn->chanspec);
3118 
3119         /*  do some initializing */
3120         writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3121 
3122         /*  set range */
3123         set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3124         writew(devpriv->dac_control1_bits,
3125                devpriv->main_iobase + DAC_CONTROL1_REG);
3126 
3127         /*  write to channel */
3128         if (board->layout == LAYOUT_4020) {
3129                 writew(data[0] & 0xff,
3130                        devpriv->main_iobase + dac_lsb_4020_reg(chan));
3131                 writew((data[0] >> 8) & 0xf,
3132                        devpriv->main_iobase + dac_msb_4020_reg(chan));
3133         } else {
3134                 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3135         }
3136 
3137         /*  remember output value */
3138         s->readback[chan] = data[0];
3139 
3140         return 1;
3141 }
3142 
3143 static void set_dac_control0_reg(struct comedi_device *dev,
3144                                  const struct comedi_cmd *cmd)
3145 {
3146         struct pcidas64_private *devpriv = dev->private;
3147         unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3148                             WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3149 
3150         if (cmd->start_src == TRIG_EXT) {
3151                 bits |= WAVEFORM_TRIG_EXT_BITS;
3152                 if (cmd->start_arg & CR_INVERT)
3153                         bits |= WAVEFORM_TRIG_FALLING_BIT;
3154         } else {
3155                 bits |= WAVEFORM_TRIG_SOFT_BITS;
3156         }
3157         if (cmd->scan_begin_src == TRIG_EXT) {
3158                 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3159                 if (cmd->scan_begin_arg & CR_INVERT)
3160                         bits |= DAC_EXT_UPDATE_FALLING_BIT;
3161         }
3162         writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3163 }
3164 
3165 static void set_dac_control1_reg(struct comedi_device *dev,
3166                                  const struct comedi_cmd *cmd)
3167 {
3168         struct pcidas64_private *devpriv = dev->private;
3169         int i;
3170 
3171         for (i = 0; i < cmd->chanlist_len; i++) {
3172                 int channel, range;
3173 
3174                 channel = CR_CHAN(cmd->chanlist[i]);
3175                 range = CR_RANGE(cmd->chanlist[i]);
3176                 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3177                                    range);
3178         }
3179         devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3180         writew(devpriv->dac_control1_bits,
3181                devpriv->main_iobase + DAC_CONTROL1_REG);
3182 }
3183 
3184 static void set_dac_select_reg(struct comedi_device *dev,
3185                                const struct comedi_cmd *cmd)
3186 {
3187         struct pcidas64_private *devpriv = dev->private;
3188         uint16_t bits;
3189         unsigned int first_channel, last_channel;
3190 
3191         first_channel = CR_CHAN(cmd->chanlist[0]);
3192         last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3193         if (last_channel < first_channel)
3194                 dev_err(dev->class_dev,
3195                         "bug! last ao channel < first ao channel\n");
3196 
3197         bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3198 
3199         writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3200 }
3201 
3202 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3203 {
3204         return get_divisor(ns, flags) - 2;
3205 }
3206 
3207 static void set_dac_interval_regs(struct comedi_device *dev,
3208                                   const struct comedi_cmd *cmd)
3209 {
3210         struct pcidas64_private *devpriv = dev->private;
3211         unsigned int divisor;
3212 
3213         if (cmd->scan_begin_src != TRIG_TIMER)
3214                 return;
3215 
3216         divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3217         if (divisor > max_counter_value) {
3218                 dev_err(dev->class_dev, "bug! ao divisor too big\n");
3219                 divisor = max_counter_value;
3220         }
3221         writew(divisor & 0xffff,
3222                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3223         writew((divisor >> 16) & 0xff,
3224                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3225 }
3226 
3227 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3228 {
3229         struct pcidas64_private *devpriv = dev->private;
3230         struct comedi_subdevice *s = dev->write_subdev;
3231         unsigned int nsamples;
3232         unsigned int nbytes;
3233         int i;
3234 
3235         /*
3236          * clear queue pointer too, since external queue has
3237          * weird interactions with ao fifo
3238          */
3239         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3240         writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3241 
3242         nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
3243                                               devpriv->ao_bounce_buffer,
3244                                               DAC_FIFO_SIZE);
3245         if (nsamples == 0)
3246                 return -1;
3247 
3248         for (i = 0; i < nsamples; i++) {
3249                 writew(devpriv->ao_bounce_buffer[i],
3250                        devpriv->main_iobase + DAC_FIFO_REG);
3251         }
3252 
3253         if (cmd->stop_src == TRIG_COUNT &&
3254             s->async->scans_done >= cmd->stop_arg)
3255                 return 0;
3256 
3257         nbytes = load_ao_dma_buffer(dev, cmd);
3258         if (nbytes == 0)
3259                 return -1;
3260         load_ao_dma(dev, cmd);
3261 
3262         dma_start_sync(dev, 0);
3263 
3264         return 0;
3265 }
3266 
3267 static inline int external_ai_queue_in_use(struct comedi_device *dev,
3268                                            struct comedi_subdevice *s,
3269                                            struct comedi_cmd *cmd)
3270 {
3271         const struct pcidas64_board *board = dev->board_ptr;
3272 
3273         if (s->busy)
3274                 return 0;
3275         if (board->layout == LAYOUT_4020)
3276                 return 0;
3277         else if (use_internal_queue_6xxx(cmd))
3278                 return 0;
3279         return 1;
3280 }
3281 
3282 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3283                       unsigned int trig_num)
3284 {
3285         struct pcidas64_private *devpriv = dev->private;
3286         struct comedi_cmd *cmd = &s->async->cmd;
3287         int retval;
3288 
3289         if (trig_num != cmd->start_arg)
3290                 return -EINVAL;
3291 
3292         retval = prep_ao_dma(dev, cmd);
3293         if (retval < 0)
3294                 return -EPIPE;
3295 
3296         set_dac_control0_reg(dev, cmd);
3297 
3298         if (cmd->start_src == TRIG_INT)
3299                 writew(0, devpriv->main_iobase + DAC_START_REG);
3300 
3301         s->async->inttrig = NULL;
3302 
3303         return 0;
3304 }
3305 
3306 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3307 {
3308         struct pcidas64_private *devpriv = dev->private;
3309         struct comedi_cmd *cmd = &s->async->cmd;
3310 
3311         if (external_ai_queue_in_use(dev, s, cmd)) {
3312                 warn_external_queue(dev);
3313                 return -EBUSY;
3314         }
3315         /* disable analog output system during setup */
3316         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3317 
3318         devpriv->ao_dma_index = 0;
3319 
3320         set_dac_select_reg(dev, cmd);
3321         set_dac_interval_regs(dev, cmd);
3322         load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3323                                   PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3324 
3325         set_dac_control1_reg(dev, cmd);
3326         s->async->inttrig = ao_inttrig;
3327 
3328         return 0;
3329 }
3330 
3331 static int cb_pcidas64_ao_check_chanlist(struct comedi_device *dev,
3332                                          struct comedi_subdevice *s,
3333                                          struct comedi_cmd *cmd)
3334 {
3335         unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
3336         int i;
3337 
3338         for (i = 1; i < cmd->chanlist_len; i++) {
3339                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3340 
3341                 if (chan != (chan0 + i)) {
3342                         dev_dbg(dev->class_dev,
3343                                 "chanlist must use consecutive channels\n");
3344                         return -EINVAL;
3345                 }
3346         }
3347 
3348         return 0;
3349 }
3350 
3351 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3352                       struct comedi_cmd *cmd)
3353 {
3354         const struct pcidas64_board *board = dev->board_ptr;
3355         int err = 0;
3356         unsigned int tmp_arg;
3357 
3358         /* Step 1 : check if triggers are trivially valid */
3359 
3360         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3361         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3362                                         TRIG_TIMER | TRIG_EXT);
3363         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3364         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3365         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3366 
3367         if (err)
3368                 return 1;
3369 
3370         /* Step 2a : make sure trigger sources are unique */
3371 
3372         err |= comedi_check_trigger_is_unique(cmd->start_src);
3373         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3374 
3375         /* Step 2b : and mutually compatible */
3376 
3377         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3378                 err |= -EINVAL;
3379         if (cmd->stop_src != TRIG_COUNT &&
3380             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3381                 err |= -EINVAL;
3382 
3383         if (err)
3384                 return 2;
3385 
3386         /* Step 3: check if arguments are trivially valid */
3387 
3388         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3389 
3390         if (cmd->scan_begin_src == TRIG_TIMER) {
3391                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3392                                                     board->ao_scan_speed);
3393                 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3394                     max_counter_value) {
3395                         cmd->scan_begin_arg = (max_counter_value + 2) *
3396                                               TIMER_BASE;
3397                         err |= -EINVAL;
3398                 }
3399         }
3400 
3401         err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1);
3402         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3403                                            cmd->chanlist_len);
3404 
3405         if (err)
3406                 return 3;
3407 
3408         /* step 4: fix up any arguments */
3409 
3410         if (cmd->scan_begin_src == TRIG_TIMER) {
3411                 tmp_arg = cmd->scan_begin_arg;
3412                 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3413                                                   cmd->flags) * TIMER_BASE;
3414                 if (tmp_arg != cmd->scan_begin_arg)
3415                         err++;
3416         }
3417 
3418         if (err)
3419                 return 4;
3420 
3421         /* Step 5: check channel list if it exists */
3422         if (cmd->chanlist && cmd->chanlist_len > 0)
3423                 err |= cb_pcidas64_ao_check_chanlist(dev, s, cmd);
3424 
3425         if (err)
3426                 return 5;
3427 
3428         return 0;
3429 }
3430 
3431 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3432 {
3433         struct pcidas64_private *devpriv = dev->private;
3434 
3435         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3436         abort_dma(dev, 0);
3437         return 0;
3438 }
3439 
3440 static int dio_callback_4020(struct comedi_device *dev,
3441                              int dir, int port, int data, unsigned long iobase)
3442 {
3443         struct pcidas64_private *devpriv = dev->private;
3444 
3445         if (dir) {
3446                 writew(data, devpriv->main_iobase + iobase + 2 * port);
3447                 return 0;
3448         }
3449         return readw(devpriv->main_iobase + iobase + 2 * port);
3450 }
3451 
3452 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3453                     struct comedi_insn *insn, unsigned int *data)
3454 {
3455         unsigned int bits;
3456 
3457         bits = readb(dev->mmio + DI_REG);
3458         bits &= 0xf;
3459         data[1] = bits;
3460         data[0] = 0;
3461 
3462         return insn->n;
3463 }
3464 
3465 static int do_wbits(struct comedi_device *dev,
3466                     struct comedi_subdevice *s,
3467                     struct comedi_insn *insn,
3468                     unsigned int *data)
3469 {
3470         if (comedi_dio_update_state(s, data))
3471                 writeb(s->state, dev->mmio + DO_REG);
3472 
3473         data[1] = s->state;
3474 
3475         return insn->n;
3476 }
3477 
3478 static int dio_60xx_config_insn(struct comedi_device *dev,
3479                                 struct comedi_subdevice *s,
3480                                 struct comedi_insn *insn,
3481                                 unsigned int *data)
3482 {
3483         int ret;
3484 
3485         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3486         if (ret)
3487                 return ret;
3488 
3489         writeb(s->io_bits, dev->mmio + DIO_DIRECTION_60XX_REG);
3490 
3491         return insn->n;
3492 }
3493 
3494 static int dio_60xx_wbits(struct comedi_device *dev,
3495                           struct comedi_subdevice *s,
3496                           struct comedi_insn *insn,
3497                           unsigned int *data)
3498 {
3499         if (comedi_dio_update_state(s, data))
3500                 writeb(s->state, dev->mmio + DIO_DATA_60XX_REG);
3501 
3502         data[1] = readb(dev->mmio + DIO_DATA_60XX_REG);
3503 
3504         return insn->n;
3505 }
3506 
3507 /*
3508  * pci-6025 8800 caldac:
3509  * address 0 == dac channel 0 offset
3510  * address 1 == dac channel 0 gain
3511  * address 2 == dac channel 1 offset
3512  * address 3 == dac channel 1 gain
3513  * address 4 == fine adc offset
3514  * address 5 == coarse adc offset
3515  * address 6 == coarse adc gain
3516  * address 7 == fine adc gain
3517  */
3518 /*
3519  * pci-6402/16 uses all 8 channels for dac:
3520  * address 0 == dac channel 0 fine gain
3521  * address 1 == dac channel 0 coarse gain
3522  * address 2 == dac channel 0 coarse offset
3523  * address 3 == dac channel 1 coarse offset
3524  * address 4 == dac channel 1 fine gain
3525  * address 5 == dac channel 1 coarse gain
3526  * address 6 == dac channel 0 fine offset
3527  * address 7 == dac channel 1 fine offset
3528  */
3529 
3530 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3531                              uint8_t value)
3532 {
3533         struct pcidas64_private *devpriv = dev->private;
3534         static const int num_caldac_channels = 8;
3535         static const int bitstream_length = 11;
3536         unsigned int bitstream = ((address & 0x7) << 8) | value;
3537         unsigned int bit, register_bits;
3538         static const int caldac_8800_udelay = 1;
3539 
3540         if (address >= num_caldac_channels) {
3541                 dev_err(dev->class_dev, "illegal caldac channel\n");
3542                 return -1;
3543         }
3544         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3545                 register_bits = 0;
3546                 if (bitstream & bit)
3547                         register_bits |= SERIAL_DATA_IN_BIT;
3548                 udelay(caldac_8800_udelay);
3549                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3550                 register_bits |= SERIAL_CLOCK_BIT;
3551                 udelay(caldac_8800_udelay);
3552                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3553         }
3554         udelay(caldac_8800_udelay);
3555         writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3556         udelay(caldac_8800_udelay);
3557         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3558         udelay(caldac_8800_udelay);
3559         return 0;
3560 }
3561 
3562 /* 4020 caldacs */
3563 static int caldac_i2c_write(struct comedi_device *dev,
3564                             unsigned int caldac_channel, unsigned int value)
3565 {
3566         uint8_t serial_bytes[3];
3567         uint8_t i2c_addr;
3568         enum pointer_bits {
3569                 /*  manual has gain and offset bits switched */
3570                 OFFSET_0_2 = 0x1,
3571                 GAIN_0_2 = 0x2,
3572                 OFFSET_1_3 = 0x4,
3573                 GAIN_1_3 = 0x8,
3574         };
3575         enum data_bits {
3576                 NOT_CLEAR_REGISTERS = 0x20,
3577         };
3578 
3579         switch (caldac_channel) {
3580         case 0:         /*  chan 0 offset */
3581                 i2c_addr = CALDAC0_I2C_ADDR;
3582                 serial_bytes[0] = OFFSET_0_2;
3583                 break;
3584         case 1:         /*  chan 1 offset */
3585                 i2c_addr = CALDAC0_I2C_ADDR;
3586                 serial_bytes[0] = OFFSET_1_3;
3587                 break;
3588         case 2:         /*  chan 2 offset */
3589                 i2c_addr = CALDAC1_I2C_ADDR;
3590                 serial_bytes[0] = OFFSET_0_2;
3591                 break;
3592         case 3:         /*  chan 3 offset */
3593                 i2c_addr = CALDAC1_I2C_ADDR;
3594                 serial_bytes[0] = OFFSET_1_3;
3595                 break;
3596         case 4:         /*  chan 0 gain */
3597                 i2c_addr = CALDAC0_I2C_ADDR;
3598                 serial_bytes[0] = GAIN_0_2;
3599                 break;
3600         case 5:         /*  chan 1 gain */
3601                 i2c_addr = CALDAC0_I2C_ADDR;
3602                 serial_bytes[0] = GAIN_1_3;
3603                 break;
3604         case 6:         /*  chan 2 gain */
3605                 i2c_addr = CALDAC1_I2C_ADDR;
3606                 serial_bytes[0] = GAIN_0_2;
3607                 break;
3608         case 7:         /*  chan 3 gain */
3609                 i2c_addr = CALDAC1_I2C_ADDR;
3610                 serial_bytes[0] = GAIN_1_3;
3611                 break;
3612         default:
3613                 dev_err(dev->class_dev, "invalid caldac channel\n");
3614                 return -1;
3615         }
3616         serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3617         serial_bytes[2] = value & 0xff;
3618         i2c_write(dev, i2c_addr, serial_bytes, 3);
3619         return 0;
3620 }
3621 
3622 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3623                          unsigned int value)
3624 {
3625         const struct pcidas64_board *board = dev->board_ptr;
3626 
3627         switch (board->layout) {
3628         case LAYOUT_60XX:
3629         case LAYOUT_64XX:
3630                 caldac_8800_write(dev, channel, value);
3631                 break;
3632         case LAYOUT_4020:
3633                 caldac_i2c_write(dev, channel, value);
3634                 break;
3635         default:
3636                 break;
3637         }
3638 }
3639 
3640 static int cb_pcidas64_calib_insn_write(struct comedi_device *dev,
3641                                         struct comedi_subdevice *s,
3642                                         struct comedi_insn *insn,
3643                                         unsigned int *data)
3644 {
3645         unsigned int chan = CR_CHAN(insn->chanspec);
3646 
3647         /*
3648          * Programming the calib device is slow. Only write the
3649          * last data value if the value has changed.
3650          */
3651         if (insn->n) {
3652                 unsigned int val = data[insn->n - 1];
3653 
3654                 if (s->readback[chan] != val) {
3655                         caldac_write(dev, chan, val);
3656                         s->readback[chan] = val;
3657                 }
3658         }
3659 
3660         return insn->n;
3661 }
3662 
3663 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3664                          unsigned int value)
3665 {
3666         struct pcidas64_private *devpriv = dev->private;
3667         static const int bitstream_length = 10;
3668         unsigned int bit, register_bits;
3669         unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3670         static const int ad8402_udelay = 1;
3671 
3672         register_bits = SELECT_8402_64XX_BIT;
3673         udelay(ad8402_udelay);
3674         writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3675 
3676         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3677                 if (bitstream & bit)
3678                         register_bits |= SERIAL_DATA_IN_BIT;
3679                 else
3680                         register_bits &= ~SERIAL_DATA_IN_BIT;
3681                 udelay(ad8402_udelay);
3682                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3683                 udelay(ad8402_udelay);
3684                 writew(register_bits | SERIAL_CLOCK_BIT,
3685                        devpriv->main_iobase + CALIBRATION_REG);
3686         }
3687 
3688         udelay(ad8402_udelay);
3689         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3690 }
3691 
3692 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3693 static int cb_pcidas64_ad8402_insn_write(struct comedi_device *dev,
3694                                          struct comedi_subdevice *s,
3695                                          struct comedi_insn *insn,
3696                                          unsigned int *data)
3697 {
3698         unsigned int chan = CR_CHAN(insn->chanspec);
3699 
3700         /*
3701          * Programming the calib device is slow. Only write the
3702          * last data value if the value has changed.
3703          */
3704         if (insn->n) {
3705                 unsigned int val = data[insn->n - 1];
3706 
3707                 if (s->readback[chan] != val) {
3708                         ad8402_write(dev, chan, val);
3709                         s->readback[chan] = val;
3710                 }
3711         }
3712 
3713         return insn->n;
3714 }
3715 
3716 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3717 {
3718         struct pcidas64_private *devpriv = dev->private;
3719         static const int bitstream_length = 11;
3720         static const int read_command = 0x6;
3721         unsigned int bitstream = (read_command << 8) | address;
3722         unsigned int bit;
3723         void __iomem * const plx_control_addr =
3724                 devpriv->plx9080_iobase + PLX_CONTROL_REG;
3725         uint16_t value;
3726         static const int value_length = 16;
3727         static const int eeprom_udelay = 1;
3728 
3729         udelay(eeprom_udelay);
3730         devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3731         /*  make sure we don't send anything to the i2c bus on 4020 */
3732         devpriv->plx_control_bits |= CTL_USERO;
3733         writel(devpriv->plx_control_bits, plx_control_addr);
3734         /*  activate serial eeprom */
3735         udelay(eeprom_udelay);
3736         devpriv->plx_control_bits |= CTL_EE_CS;
3737         writel(devpriv->plx_control_bits, plx_control_addr);
3738 
3739         /*  write read command and desired memory address */
3740         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3741                 /*  set bit to be written */
3742                 udelay(eeprom_udelay);
3743                 if (bitstream & bit)
3744                         devpriv->plx_control_bits |= CTL_EE_W;
3745                 else
3746                         devpriv->plx_control_bits &= ~CTL_EE_W;
3747                 writel(devpriv->plx_control_bits, plx_control_addr);
3748                 /*  clock in bit */
3749                 udelay(eeprom_udelay);
3750                 devpriv->plx_control_bits |= CTL_EE_CLK;
3751                 writel(devpriv->plx_control_bits, plx_control_addr);
3752                 udelay(eeprom_udelay);
3753                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3754                 writel(devpriv->plx_control_bits, plx_control_addr);
3755         }
3756         /*  read back value from eeprom memory location */
3757         value = 0;
3758         for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3759                 /*  clock out bit */
3760                 udelay(eeprom_udelay);
3761                 devpriv->plx_control_bits |= CTL_EE_CLK;
3762                 writel(devpriv->plx_control_bits, plx_control_addr);
3763                 udelay(eeprom_udelay);
3764                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3765                 writel(devpriv->plx_control_bits, plx_control_addr);
3766                 udelay(eeprom_udelay);
3767                 if (readl(plx_control_addr) & CTL_EE_R)
3768                         value |= bit;
3769         }
3770 
3771         /*  deactivate eeprom serial input */
3772         udelay(eeprom_udelay);
3773         devpriv->plx_control_bits &= ~CTL_EE_CS;
3774         writel(devpriv->plx_control_bits, plx_control_addr);
3775 
3776         return value;
3777 }
3778 
3779 static int eeprom_read_insn(struct comedi_device *dev,
3780                             struct comedi_subdevice *s,
3781                             struct comedi_insn *insn, unsigned int *data)
3782 {
3783         data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3784 
3785         return 1;
3786 }
3787 
3788 /*
3789  * Allocate and initialize the subdevice structures.
3790  */
3791 static int setup_subdevices(struct comedi_device *dev)
3792 {
3793         const struct pcidas64_board *board = dev->board_ptr;
3794         struct pcidas64_private *devpriv = dev->private;
3795         struct comedi_subdevice *s;
3796         int i;
3797         int ret;
3798 
3799         ret = comedi_alloc_subdevices(dev, 10);
3800         if (ret)
3801                 return ret;
3802 
3803         s = &dev->subdevices[0];
3804         /* analog input subdevice */
3805         dev->read_subdev = s;
3806         s->type = COMEDI_SUBD_AI;
3807         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3808         if (board->layout == LAYOUT_60XX)
3809                 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3810         else if (board->layout == LAYOUT_64XX)
3811                 s->subdev_flags |= SDF_DIFF;
3812         /* XXX Number of inputs in differential mode is ignored */
3813         s->n_chan = board->ai_se_chans;
3814         s->len_chanlist = 0x2000;
3815         s->maxdata = (1 << board->ai_bits) - 1;
3816         s->range_table = board->ai_range_table;
3817         s->insn_read = ai_rinsn;
3818         s->insn_config = ai_config_insn;
3819         s->do_cmd = ai_cmd;
3820         s->do_cmdtest = ai_cmdtest;
3821         s->cancel = ai_cancel;
3822         if (board->layout == LAYOUT_4020) {
3823                 uint8_t data;
3824                 /*
3825                  * set adc to read from inputs
3826                  * (not internal calibration sources)
3827                  */
3828                 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3829                 /*  set channels to +-5 volt input ranges */
3830                 for (i = 0; i < s->n_chan; i++)
3831                         devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3832                 data = devpriv->i2c_cal_range_bits;
3833                 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3834         }
3835 
3836         /* analog output subdevice */
3837         s = &dev->subdevices[1];
3838         if (board->ao_nchan) {
3839                 s->type = COMEDI_SUBD_AO;
3840                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3841                                   SDF_GROUND | SDF_CMD_WRITE;
3842                 s->n_chan = board->ao_nchan;
3843                 s->maxdata = (1 << board->ao_bits) - 1;
3844                 s->range_table = board->ao_range_table;
3845                 s->insn_write = ao_winsn;
3846 
3847                 ret = comedi_alloc_subdev_readback(s);
3848                 if (ret)
3849                         return ret;
3850 
3851                 if (ao_cmd_is_supported(board)) {
3852                         dev->write_subdev = s;
3853                         s->do_cmdtest = ao_cmdtest;
3854                         s->do_cmd = ao_cmd;
3855                         s->len_chanlist = board->ao_nchan;
3856                         s->cancel = ao_cancel;
3857                 }
3858         } else {
3859                 s->type = COMEDI_SUBD_UNUSED;
3860         }
3861 
3862         /*  digital input */
3863         s = &dev->subdevices[2];
3864         if (board->layout == LAYOUT_64XX) {
3865                 s->type = COMEDI_SUBD_DI;
3866                 s->subdev_flags = SDF_READABLE;
3867                 s->n_chan = 4;
3868                 s->maxdata = 1;
3869                 s->range_table = &range_digital;
3870                 s->insn_bits = di_rbits;
3871         } else {
3872                 s->type = COMEDI_SUBD_UNUSED;
3873         }
3874 
3875         /*  digital output */
3876         if (board->layout == LAYOUT_64XX) {
3877                 s = &dev->subdevices[3];
3878                 s->type = COMEDI_SUBD_DO;
3879                 s->subdev_flags = SDF_WRITABLE;
3880                 s->n_chan = 4;
3881                 s->maxdata = 1;
3882                 s->range_table = &range_digital;
3883                 s->insn_bits = do_wbits;
3884         } else {
3885                 s->type = COMEDI_SUBD_UNUSED;
3886         }
3887 
3888         /* 8255 */
3889         s = &dev->subdevices[4];
3890         if (board->has_8255) {
3891                 if (board->layout == LAYOUT_4020) {
3892                         ret = subdev_8255_init(dev, s, dio_callback_4020,
3893                                                I8255_4020_REG);
3894                 } else {
3895                         ret = subdev_8255_mm_init(dev, s, NULL,
3896                                                   DIO_8255_OFFSET);
3897                 }
3898                 if (ret)
3899                         return ret;
3900         } else {
3901                 s->type = COMEDI_SUBD_UNUSED;
3902         }
3903 
3904         /*  8 channel dio for 60xx */
3905         s = &dev->subdevices[5];
3906         if (board->layout == LAYOUT_60XX) {
3907                 s->type = COMEDI_SUBD_DIO;
3908                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3909                 s->n_chan = 8;
3910                 s->maxdata = 1;
3911                 s->range_table = &range_digital;
3912                 s->insn_config = dio_60xx_config_insn;
3913                 s->insn_bits = dio_60xx_wbits;
3914         } else {
3915                 s->type = COMEDI_SUBD_UNUSED;
3916         }
3917 
3918         /*  caldac */
3919         s = &dev->subdevices[6];
3920         s->type = COMEDI_SUBD_CALIB;
3921         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3922         s->n_chan = 8;
3923         if (board->layout == LAYOUT_4020)
3924                 s->maxdata = 0xfff;
3925         else
3926                 s->maxdata = 0xff;
3927         s->insn_write = cb_pcidas64_calib_insn_write;
3928 
3929         ret = comedi_alloc_subdev_readback(s);
3930         if (ret)
3931                 return ret;
3932 
3933         for (i = 0; i < s->n_chan; i++) {
3934                 caldac_write(dev, i, s->maxdata / 2);
3935                 s->readback[i] = s->maxdata / 2;
3936         }
3937 
3938         /*  2 channel ad8402 potentiometer */
3939         s = &dev->subdevices[7];
3940         if (board->layout == LAYOUT_64XX) {
3941                 s->type = COMEDI_SUBD_CALIB;
3942                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3943                 s->n_chan = 2;
3944                 s->maxdata = 0xff;
3945                 s->insn_write = cb_pcidas64_ad8402_insn_write;
3946 
3947                 ret = comedi_alloc_subdev_readback(s);
3948                 if (ret)
3949                         return ret;
3950 
3951                 for (i = 0; i < s->n_chan; i++) {
3952                         ad8402_write(dev, i, s->maxdata / 2);
3953                         s->readback[i] = s->maxdata / 2;
3954                 }
3955         } else {
3956                 s->type = COMEDI_SUBD_UNUSED;
3957         }
3958 
3959         /* serial EEPROM, if present */
3960         s = &dev->subdevices[8];
3961         if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
3962                 s->type = COMEDI_SUBD_MEMORY;
3963                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
3964                 s->n_chan = 128;
3965                 s->maxdata = 0xffff;
3966                 s->insn_read = eeprom_read_insn;
3967         } else {
3968                 s->type = COMEDI_SUBD_UNUSED;
3969         }
3970 
3971         /*  user counter subd XXX */
3972         s = &dev->subdevices[9];
3973         s->type = COMEDI_SUBD_UNUSED;
3974 
3975         return 0;
3976 }
3977 
3978 static int auto_attach(struct comedi_device *dev,
3979                        unsigned long context)
3980 {
3981         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
3982         const struct pcidas64_board *board = NULL;
3983         struct pcidas64_private *devpriv;
3984         uint32_t local_range, local_decode;
3985         int retval;
3986 
3987         if (context < ARRAY_SIZE(pcidas64_boards))
3988                 board = &pcidas64_boards[context];
3989         if (!board)
3990                 return -ENODEV;
3991         dev->board_ptr = board;
3992 
3993         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
3994         if (!devpriv)
3995                 return -ENOMEM;
3996 
3997         retval = comedi_pci_enable(dev);
3998         if (retval)
3999                 return retval;
4000         pci_set_master(pcidev);
4001 
4002         /* Initialize dev->board_name */
4003         dev->board_name = board->name;
4004 
4005         devpriv->main_phys_iobase = pci_resource_start(pcidev, 2);
4006         devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3);
4007 
4008         devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
4009         devpriv->main_iobase = pci_ioremap_bar(pcidev, 2);
4010         dev->mmio = pci_ioremap_bar(pcidev, 3);
4011 
4012         if (!devpriv->plx9080_iobase || !devpriv->main_iobase || !dev->mmio) {
4013                 dev_warn(dev->class_dev, "failed to remap io memory\n");
4014                 return -ENOMEM;
4015         }
4016 
4017         /*  figure out what local addresses are */
4018         local_range = readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) &
4019                       LRNG_MEM_MASK;
4020         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS0MAP_REG) &
4021                        local_range & LMAP_MEM_MASK;
4022         devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
4023                                   ~local_range) | local_decode;
4024         local_range = readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) &
4025                       LRNG_MEM_MASK;
4026         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS1MAP_REG) &
4027                        local_range & LMAP_MEM_MASK;
4028         devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
4029                                   ~local_range) | local_decode;
4030 
4031         retval = alloc_and_init_dma_members(dev);
4032         if (retval < 0)
4033                 return retval;
4034 
4035         devpriv->hw_revision =
4036                 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
4037         dev_dbg(dev->class_dev, "stc hardware revision %i\n",
4038                 devpriv->hw_revision);
4039         init_plx9080(dev);
4040         init_stc_registers(dev);
4041 
4042         retval = request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
4043                              dev->board_name, dev);
4044         if (retval) {
4045                 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
4046                         pcidev->irq);
4047                 return retval;
4048         }
4049         dev->irq = pcidev->irq;
4050         dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
4051 
4052         retval = setup_subdevices(dev);
4053         if (retval < 0)
4054                 return retval;
4055 
4056         return 0;
4057 }
4058 
4059 static void detach(struct comedi_device *dev)
4060 {
4061         struct pcidas64_private *devpriv = dev->private;
4062 
4063         if (dev->irq)
4064                 free_irq(dev->irq, dev);
4065         if (devpriv) {
4066                 if (devpriv->plx9080_iobase) {
4067                         disable_plx_interrupts(dev);
4068                         iounmap(devpriv->plx9080_iobase);
4069                 }
4070                 if (devpriv->main_iobase)
4071                         iounmap(devpriv->main_iobase);
4072                 if (dev->mmio)
4073                         iounmap(dev->mmio);
4074         }
4075         comedi_pci_disable(dev);
4076         cb_pcidas64_free_dma(dev);
4077 }
4078 
4079 static struct comedi_driver cb_pcidas64_driver = {
4080         .driver_name    = "cb_pcidas64",
4081         .module         = THIS_MODULE,
4082         .auto_attach    = auto_attach,
4083         .detach         = detach,
4084 };
4085 
4086 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4087                                  const struct pci_device_id *id)
4088 {
4089         return comedi_pci_auto_config(dev, &cb_pcidas64_driver,
4090                                       id->driver_data);
4091 }
4092 
4093 static const struct pci_device_id cb_pcidas64_pci_table[] = {
4094         { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 },
4095         { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 },
4096         { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 },
4097         { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 },
4098         { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 },
4099         { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 },
4100         { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 },
4101         { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 },
4102         { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 },
4103         { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 },
4104         { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 },
4105         { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 },
4106         { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 },
4107         { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 },
4108         { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 },
4109         { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 },
4110         { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 },
4111         { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 },
4112         { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 },
4113         { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 },
4114         { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 },
4115         { 0 }
4116 };
4117 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4118 
4119 static struct pci_driver cb_pcidas64_pci_driver = {
4120         .name           = "cb_pcidas64",
4121         .id_table       = cb_pcidas64_pci_table,
4122         .probe          = cb_pcidas64_pci_probe,
4123         .remove         = comedi_pci_auto_unconfig,
4124 };
4125 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4126 
4127 MODULE_AUTHOR("Comedi http://www.comedi.org");
4128 MODULE_DESCRIPTION("Comedi low-level driver");
4129 MODULE_LICENSE("GPL");
4130 

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