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Linux/drivers/staging/comedi/drivers/cb_pcidas64.c

  1 /*
  2  * comedi/drivers/cb_pcidas64.c
  3  * This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
  4  * 64xx, 60xx, and 4020 cards.
  5  *
  6  * Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
  7  * Copyright (C) 2001, 2002 Frank Mori Hess
  8  *
  9  * Thanks also go to the following people:
 10  *
 11  * Steve Rosenbluth, for providing the source code for
 12  * his pci-das6402 driver, and source code for working QNX pci-6402
 13  * drivers by Greg Laird and Mariusz Bogacz.  None of the code was
 14  * used directly here, but it was useful as an additional source of
 15  * documentation on how to program the boards.
 16  *
 17  * John Sims, for much testing and feedback on pcidas-4020 support.
 18  *
 19  * COMEDI - Linux Control and Measurement Device Interface
 20  * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
 21  *
 22  * This program is free software; you can redistribute it and/or modify
 23  * it under the terms of the GNU General Public License as published by
 24  * the Free Software Foundation; either version 2 of the License, or
 25  * (at your option) any later version.
 26  *
 27  * This program is distributed in the hope that it will be useful,
 28  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 29  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 30  * GNU General Public License for more details.
 31  */
 32 
 33 /*
 34  * Driver: cb_pcidas64
 35  * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
 36  *   with the PLX 9080 PCI controller
 37  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
 38  * Status: works
 39  * Updated: Fri, 02 Nov 2012 18:58:55 +0000
 40  * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
 41  *   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
 42  *   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
 43  *   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
 44  *   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
 45  *   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
 46  *   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
 47  *   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
 48  *   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
 49  *
 50  * Configuration options:
 51  *   None.
 52  *
 53  * Manual attachment of PCI cards with the comedi_config utility is not
 54  * supported by this driver; they are attached automatically.
 55  *
 56  * These boards may be autocalibrated with the comedi_calibrate utility.
 57  *
 58  * To select the bnc trigger input on the 4020 (instead of the dio input),
 59  * specify a nonzero channel in the chanspec.  If you wish to use an external
 60  * master clock on the 4020, you may do so by setting the scan_begin_src
 61  * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
 62  * to configure the divisor to use for the external clock.
 63  *
 64  * Some devices are not identified because the PCI device IDs are not yet
 65  * known. If you have such a board, please let the maintainers know.
 66  */
 67 
 68 /*
 69  * TODO:
 70  * make it return error if user attempts an ai command that uses the
 71  * external queue, and an ao command simultaneously user counter subdevice
 72  * there are a number of boards this driver will support when they are
 73  * fully released, but does not yet since the pci device id numbers
 74  * are not yet available.
 75  *
 76  * support prescaled 100khz clock for slow pacing (not available on 6000
 77  * series?)
 78  *
 79  * make ao fifo size adjustable like ai fifo
 80  */
 81 
 82 #include <linux/module.h>
 83 #include <linux/delay.h>
 84 #include <linux/interrupt.h>
 85 
 86 #include "../comedi_pci.h"
 87 
 88 #include "8255.h"
 89 #include "plx9080.h"
 90 
 91 #define TIMER_BASE 25           /*  40MHz master clock */
 92 /*
 93  * 100kHz 'prescaled' clock for slow acquisition,
 94  * maybe I'll support this someday
 95  */
 96 #define PRESCALED_TIMER_BASE    10000
 97 #define DMA_BUFFER_SIZE         0x1000
 98 #define DAC_FIFO_SIZE           0x2000
 99 
100 /* maximum value that can be loaded into board's 24-bit counters */
101 static const int max_counter_value = 0xffffff;
102 
103 /* PCI-DAS64xxx base addresses */
104 
105 /* devpriv->main_iobase registers */
106 enum write_only_registers {
107         INTR_ENABLE_REG = 0x0,          /* interrupt enable register */
108         HW_CONFIG_REG = 0x2,            /* hardware config register */
109         DAQ_SYNC_REG = 0xc,
110         DAQ_ATRIG_LOW_4020_REG = 0xc,
111         ADC_CONTROL0_REG = 0x10,        /* adc control register 0 */
112         ADC_CONTROL1_REG = 0x12,        /* adc control register 1 */
113         CALIBRATION_REG = 0x14,
114         /* lower 16 bits of adc sample interval counter */
115         ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
116         /* upper 8 bits of adc sample interval counter */
117         ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
118         /* lower 16 bits of delay interval counter */
119         ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
120         /* upper 8 bits of delay interval counter */
121         ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
122         /* lower 16 bits of hardware conversion/scan counter */
123         ADC_COUNT_LOWER_REG = 0x1e,
124         /* upper 8 bits of hardware conversion/scan counter */
125         ADC_COUNT_UPPER_REG = 0x20,
126         ADC_START_REG = 0x22,   /* software trigger to start acquisition */
127         ADC_CONVERT_REG = 0x24, /* initiates single conversion */
128         ADC_QUEUE_CLEAR_REG = 0x26,     /* clears adc queue */
129         ADC_QUEUE_LOAD_REG = 0x28,      /* loads adc queue */
130         ADC_BUFFER_CLEAR_REG = 0x2a,
131         /* high channel for internal queue, use adc_chan_bits() inline above */
132         ADC_QUEUE_HIGH_REG = 0x2c,
133         DAC_CONTROL0_REG = 0x50,        /* dac control register 0 */
134         DAC_CONTROL1_REG = 0x52,        /* dac control register 0 */
135         /* lower 16 bits of dac sample interval counter */
136         DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
137         /* upper 8 bits of dac sample interval counter */
138         DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
139         DAC_SELECT_REG = 0x60,
140         DAC_START_REG = 0x64,
141         DAC_BUFFER_CLEAR_REG = 0x66,    /* clear dac buffer */
142 };
143 
144 static inline unsigned int dac_convert_reg(unsigned int channel)
145 {
146         return 0x70 + (2 * (channel & 0x1));
147 }
148 
149 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
150 {
151         return 0x70 + (4 * (channel & 0x1));
152 }
153 
154 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
155 {
156         return 0x72 + (4 * (channel & 0x1));
157 }
158 
159 enum read_only_registers {
160         /*
161          * hardware status register,
162          * reading this apparently clears pending interrupts as well
163          */
164         HW_STATUS_REG = 0x0,
165         PIPE1_READ_REG = 0x4,
166         ADC_READ_PNTR_REG = 0x8,
167         LOWER_XFER_REG = 0x10,
168         ADC_WRITE_PNTR_REG = 0xc,
169         PREPOST_REG = 0x14,
170 };
171 
172 enum read_write_registers {
173         I8255_4020_REG = 0x48,  /* 8255 offset, for 4020 only */
174         /* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
175         ADC_QUEUE_FIFO_REG = 0x100,
176         ADC_FIFO_REG = 0x200,   /* adc data fifo */
177         /* dac data fifo, has weird interactions with external channel queue */
178         DAC_FIFO_REG = 0x300,
179 };
180 
181 /* dev->mmio registers */
182 enum dio_counter_registers {
183         DIO_8255_OFFSET = 0x0,
184         DO_REG = 0x20,
185         DI_REG = 0x28,
186         DIO_DIRECTION_60XX_REG = 0x40,
187         DIO_DATA_60XX_REG = 0x48,
188 };
189 
190 /* bit definitions for write-only registers */
191 
192 enum intr_enable_contents {
193         ADC_INTR_SRC_MASK = 0x3,        /* adc interrupt source mask */
194         ADC_INTR_QFULL_BITS = 0x0,      /* interrupt fifo quarter full */
195         ADC_INTR_EOC_BITS = 0x1,        /* interrupt end of conversion */
196         ADC_INTR_EOSCAN_BITS = 0x2,     /* interrupt end of scan */
197         ADC_INTR_EOSEQ_BITS = 0x3,      /* interrupt end of sequence mask */
198         EN_ADC_INTR_SRC_BIT = 0x4,      /* enable adc interrupt source */
199         EN_ADC_DONE_INTR_BIT = 0x8,     /* enable adc acquisition done intr */
200         DAC_INTR_SRC_MASK = 0x30,
201         DAC_INTR_QEMPTY_BITS = 0x0,
202         DAC_INTR_HIGH_CHAN_BITS = 0x10,
203         EN_DAC_INTR_SRC_BIT = 0x40,     /* enable dac interrupt source */
204         EN_DAC_DONE_INTR_BIT = 0x80,
205         EN_ADC_ACTIVE_INTR_BIT = 0x200, /* enable adc active interrupt */
206         EN_ADC_STOP_INTR_BIT = 0x400,   /* enable adc stop trigger interrupt */
207         EN_DAC_ACTIVE_INTR_BIT = 0x800, /* enable dac active interrupt */
208         EN_DAC_UNDERRUN_BIT = 0x4000,   /* enable dac underrun status bit */
209         EN_ADC_OVERRUN_BIT = 0x8000,    /* enable adc overrun status bit */
210 };
211 
212 enum hw_config_contents {
213         MASTER_CLOCK_4020_MASK = 0x3,   /* master clock source mask for 4020 */
214         INTERNAL_CLOCK_4020_BITS = 0x1, /* use 40 MHz internal master clock */
215         BNC_CLOCK_4020_BITS = 0x2,      /* use BNC input for master clock */
216         EXT_CLOCK_4020_BITS = 0x3,      /* use dio input for master clock */
217         EXT_QUEUE_BIT = 0x200,          /* use external channel/gain queue */
218         /* use 225 nanosec strobe when loading dac instead of 50 nanosec */
219         SLOW_DAC_BIT = 0x400,
220         /*
221          * bit with unknown function yet given as default value in pci-das64
222          * manual
223          */
224         HW_CONFIG_DUMMY_BITS = 0x2000,
225         /* bit selects channels 1/0 for analog input/output, otherwise 0/1 */
226         DMA_CH_SELECT_BIT = 0x8000,
227         FIFO_SIZE_REG = 0x4,            /* allows adjustment of fifo sizes */
228         DAC_FIFO_SIZE_MASK = 0xff00,    /* bits that set dac fifo size */
229         DAC_FIFO_BITS = 0xf800,         /* 8k sample ao fifo */
230 };
231 
232 enum daq_atrig_low_4020_contents {
233         /* use trig/ext clk bnc input for analog gate signal */
234         EXT_AGATE_BNC_BIT = 0x8000,
235         /* use trig/ext clk bnc input for external stop trigger signal */
236         EXT_STOP_TRIG_BNC_BIT = 0x4000,
237         /* use trig/ext clk bnc input for external start trigger signal */
238         EXT_START_TRIG_BNC_BIT = 0x2000,
239 };
240 
241 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
242 {
243         return threshold & 0xfff;
244 }
245 
246 enum adc_control0_contents {
247         ADC_GATE_SRC_MASK = 0x3,        /* bits that select gate */
248         ADC_SOFT_GATE_BITS = 0x1,       /* software gate */
249         ADC_EXT_GATE_BITS = 0x2,        /* external digital gate */
250         ADC_ANALOG_GATE_BITS = 0x3,     /* analog level gate */
251         /* level-sensitive gate (for digital) */
252         ADC_GATE_LEVEL_BIT = 0x4,
253         ADC_GATE_POLARITY_BIT = 0x8,    /* gate active low */
254         ADC_START_TRIG_SOFT_BITS = 0x10,
255         ADC_START_TRIG_EXT_BITS = 0x20,
256         ADC_START_TRIG_ANALOG_BITS = 0x30,
257         ADC_START_TRIG_MASK = 0x30,
258         ADC_START_TRIG_FALLING_BIT = 0x40,      /* trig 1 uses falling edge */
259         /* external pacing uses falling edge */
260         ADC_EXT_CONV_FALLING_BIT = 0x800,
261         /* enable hardware scan counter */
262         ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
263         ADC_DMA_DISABLE_BIT = 0x4000,   /* disables dma */
264         ADC_ENABLE_BIT = 0x8000,        /* master adc enable */
265 };
266 
267 enum adc_control1_contents {
268         /* should be set for boards with > 16 channels */
269         ADC_QUEUE_CONFIG_BIT = 0x1,
270         CONVERT_POLARITY_BIT = 0x10,
271         EOC_POLARITY_BIT = 0x20,
272         ADC_SW_GATE_BIT = 0x40,         /* software gate of adc */
273         ADC_DITHER_BIT = 0x200,         /* turn on extra noise for dithering */
274         RETRIGGER_BIT = 0x800,
275         ADC_LO_CHANNEL_4020_MASK = 0x300,
276         ADC_HI_CHANNEL_4020_MASK = 0xc00,
277         TWO_CHANNEL_4020_BITS = 0x1000,         /* two channel mode for 4020 */
278         FOUR_CHANNEL_4020_BITS = 0x2000,        /* four channel mode for 4020 */
279         CHANNEL_MODE_4020_MASK = 0x3000,
280         ADC_MODE_MASK = 0xf000,
281 };
282 
283 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
284 {
285         return (channel & 0x3) << 8;
286 };
287 
288 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
289 {
290         return (channel & 0x3) << 10;
291 };
292 
293 static inline uint16_t adc_mode_bits(unsigned int mode)
294 {
295         return (mode & 0xf) << 12;
296 };
297 
298 enum calibration_contents {
299         SELECT_8800_BIT = 0x1,
300         SELECT_8402_64XX_BIT = 0x2,
301         SELECT_1590_60XX_BIT = 0x2,
302         CAL_EN_64XX_BIT = 0x40,         /* calibration enable for 64xx series */
303         SERIAL_DATA_IN_BIT = 0x80,
304         SERIAL_CLOCK_BIT = 0x100,
305         CAL_EN_60XX_BIT = 0x200,        /* calibration enable for 60xx series */
306         CAL_GAIN_BIT = 0x800,
307 };
308 
309 /*
310  * calibration sources for 6025 are:
311  *  0 : ground
312  *  1 : 10V
313  *  2 : 5V
314  *  3 : 0.5V
315  *  4 : 0.05V
316  *  5 : ground
317  *  6 : dac channel 0
318  *  7 : dac channel 1
319  */
320 
321 static inline uint16_t adc_src_bits(unsigned int source)
322 {
323         return (source & 0xf) << 3;
324 };
325 
326 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
327 {
328         return (channel & 0x3) << 8;
329 };
330 
331 enum adc_queue_load_contents {
332         UNIP_BIT = 0x800,               /* unipolar/bipolar bit */
333         ADC_SE_DIFF_BIT = 0x1000,       /* single-ended/ differential bit */
334         /* non-referenced single-ended (common-mode input) */
335         ADC_COMMON_BIT = 0x2000,
336         QUEUE_EOSEQ_BIT = 0x4000,       /* queue end of sequence */
337         QUEUE_EOSCAN_BIT = 0x8000,      /* queue end of scan */
338 };
339 
340 static inline uint16_t adc_chan_bits(unsigned int channel)
341 {
342         return channel & 0x3f;
343 };
344 
345 enum dac_control0_contents {
346         DAC_ENABLE_BIT = 0x8000,        /* dac controller enable bit */
347         DAC_CYCLIC_STOP_BIT = 0x4000,
348         DAC_WAVEFORM_MODE_BIT = 0x100,
349         DAC_EXT_UPDATE_FALLING_BIT = 0x80,
350         DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
351         WAVEFORM_TRIG_MASK = 0x30,
352         WAVEFORM_TRIG_DISABLED_BITS = 0x0,
353         WAVEFORM_TRIG_SOFT_BITS = 0x10,
354         WAVEFORM_TRIG_EXT_BITS = 0x20,
355         WAVEFORM_TRIG_ADC1_BITS = 0x30,
356         WAVEFORM_TRIG_FALLING_BIT = 0x8,
357         WAVEFORM_GATE_LEVEL_BIT = 0x4,
358         WAVEFORM_GATE_ENABLE_BIT = 0x2,
359         WAVEFORM_GATE_SELECT_BIT = 0x1,
360 };
361 
362 enum dac_control1_contents {
363         DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
364         DAC1_EXT_REF_BIT = 0x200,
365         DAC0_EXT_REF_BIT = 0x100,
366         DAC_OUTPUT_ENABLE_BIT = 0x80,   /* dac output enable bit */
367         DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
368         DAC_SW_GATE_BIT = 0x20,
369         DAC1_UNIPOLAR_BIT = 0x8,
370         DAC0_UNIPOLAR_BIT = 0x2,
371 };
372 
373 /* bit definitions for read-only registers */
374 enum hw_status_contents {
375         DAC_UNDERRUN_BIT = 0x1,
376         ADC_OVERRUN_BIT = 0x2,
377         DAC_ACTIVE_BIT = 0x4,
378         ADC_ACTIVE_BIT = 0x8,
379         DAC_INTR_PENDING_BIT = 0x10,
380         ADC_INTR_PENDING_BIT = 0x20,
381         DAC_DONE_BIT = 0x40,
382         ADC_DONE_BIT = 0x80,
383         EXT_INTR_PENDING_BIT = 0x100,
384         ADC_STOP_BIT = 0x200,
385 };
386 
387 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
388 {
389         return (hw_status_bits >> 10) & 0x3;
390 };
391 
392 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
393 {
394         return (prepost_bits >> 6) & 0x3;
395 }
396 
397 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
398 {
399         return (prepost_bits >> 12) & 0x3;
400 }
401 
402 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
403 {
404         return (prepost_bits >> 14) & 0x3;
405 }
406 
407 /* I2C addresses for 4020 */
408 enum i2c_addresses {
409         RANGE_CAL_I2C_ADDR = 0x20,
410         CALDAC0_I2C_ADDR = 0xc,
411         CALDAC1_I2C_ADDR = 0xd,
412 };
413 
414 enum range_cal_i2c_contents {
415         /* bits that set what source the adc converter measures */
416         ADC_SRC_4020_MASK = 0x70,
417         /* make bnc trig/ext clock threshold 0V instead of 2.5V */
418         BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
419 };
420 
421 static inline uint8_t adc_src_4020_bits(unsigned int source)
422 {
423         return (source << 4) & ADC_SRC_4020_MASK;
424 };
425 
426 static inline uint8_t attenuate_bit(unsigned int channel)
427 {
428         /* attenuate channel (+-5V input range) */
429         return 1 << (channel & 0x3);
430 };
431 
432 /* analog input ranges for 64xx boards */
433 static const struct comedi_lrange ai_ranges_64xx = {
434         8, {
435                 BIP_RANGE(10),
436                 BIP_RANGE(5),
437                 BIP_RANGE(2.5),
438                 BIP_RANGE(1.25),
439                 UNI_RANGE(10),
440                 UNI_RANGE(5),
441                 UNI_RANGE(2.5),
442                 UNI_RANGE(1.25)
443         }
444 };
445 
446 static const uint8_t ai_range_code_64xx[8] = {
447         0x0, 0x1, 0x2, 0x3,     /* bipolar 10, 5, 2,5, 1.25 */
448         0x8, 0x9, 0xa, 0xb      /* unipolar 10, 5, 2.5, 1.25 */
449 };
450 
451 /* analog input ranges for 64-Mx boards */
452 static const struct comedi_lrange ai_ranges_64_mx = {
453         7, {
454                 BIP_RANGE(5),
455                 BIP_RANGE(2.5),
456                 BIP_RANGE(1.25),
457                 BIP_RANGE(0.625),
458                 UNI_RANGE(5),
459                 UNI_RANGE(2.5),
460                 UNI_RANGE(1.25)
461         }
462 };
463 
464 static const uint8_t ai_range_code_64_mx[7] = {
465         0x0, 0x1, 0x2, 0x3,     /* bipolar 5, 2.5, 1.25, 0.625 */
466         0x9, 0xa, 0xb           /* unipolar 5, 2.5, 1.25 */
467 };
468 
469 /* analog input ranges for 60xx boards */
470 static const struct comedi_lrange ai_ranges_60xx = {
471         4, {
472                 BIP_RANGE(10),
473                 BIP_RANGE(5),
474                 BIP_RANGE(0.5),
475                 BIP_RANGE(0.05)
476         }
477 };
478 
479 static const uint8_t ai_range_code_60xx[4] = {
480         0x0, 0x1, 0x4, 0x7      /* bipolar 10, 5, 0.5, 0.05 */
481 };
482 
483 /* analog input ranges for 6030, etc boards */
484 static const struct comedi_lrange ai_ranges_6030 = {
485         14, {
486                 BIP_RANGE(10),
487                 BIP_RANGE(5),
488                 BIP_RANGE(2),
489                 BIP_RANGE(1),
490                 BIP_RANGE(0.5),
491                 BIP_RANGE(0.2),
492                 BIP_RANGE(0.1),
493                 UNI_RANGE(10),
494                 UNI_RANGE(5),
495                 UNI_RANGE(2),
496                 UNI_RANGE(1),
497                 UNI_RANGE(0.5),
498                 UNI_RANGE(0.2),
499                 UNI_RANGE(0.1)
500         }
501 };
502 
503 static const uint8_t ai_range_code_6030[14] = {
504         0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, /* bip 10, 5, 2, 1, 0.5, 0.2, 0.1 */
505         0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf  /* uni 10, 5, 2, 1, 0.5, 0.2, 0.1 */
506 };
507 
508 /* analog input ranges for 6052, etc boards */
509 static const struct comedi_lrange ai_ranges_6052 = {
510         15, {
511                 BIP_RANGE(10),
512                 BIP_RANGE(5),
513                 BIP_RANGE(2.5),
514                 BIP_RANGE(1),
515                 BIP_RANGE(0.5),
516                 BIP_RANGE(0.25),
517                 BIP_RANGE(0.1),
518                 BIP_RANGE(0.05),
519                 UNI_RANGE(10),
520                 UNI_RANGE(5),
521                 UNI_RANGE(2),
522                 UNI_RANGE(1),
523                 UNI_RANGE(0.5),
524                 UNI_RANGE(0.2),
525                 UNI_RANGE(0.1)
526         }
527 };
528 
529 static const uint8_t ai_range_code_6052[15] = {
530         0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, /* bipolar 10 ... 0.05 */
531         0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf       /* unipolar 10 ... 0.1 */
532 };
533 
534 /* analog input ranges for 4020 board */
535 static const struct comedi_lrange ai_ranges_4020 = {
536         2, {
537                 BIP_RANGE(5),
538                 BIP_RANGE(1)
539         }
540 };
541 
542 /* analog output ranges */
543 static const struct comedi_lrange ao_ranges_64xx = {
544         4, {
545                 BIP_RANGE(5),
546                 BIP_RANGE(10),
547                 UNI_RANGE(5),
548                 UNI_RANGE(10)
549         }
550 };
551 
552 static const int ao_range_code_64xx[] = {
553         0x0,
554         0x1,
555         0x2,
556         0x3,
557 };
558 
559 static const int ao_range_code_60xx[] = {
560         0x0,
561 };
562 
563 static const struct comedi_lrange ao_ranges_6030 = {
564         2, {
565                 BIP_RANGE(10),
566                 UNI_RANGE(10)
567         }
568 };
569 
570 static const int ao_range_code_6030[] = {
571         0x0,
572         0x2,
573 };
574 
575 static const struct comedi_lrange ao_ranges_4020 = {
576         2, {
577                 BIP_RANGE(5),
578                 BIP_RANGE(10)
579         }
580 };
581 
582 static const int ao_range_code_4020[] = {
583         0x1,
584         0x0,
585 };
586 
587 enum register_layout {
588         LAYOUT_60XX,
589         LAYOUT_64XX,
590         LAYOUT_4020,
591 };
592 
593 struct hw_fifo_info {
594         unsigned int num_segments;
595         unsigned int max_segment_length;
596         unsigned int sample_packing_ratio;
597         uint16_t fifo_size_reg_mask;
598 };
599 
600 enum pcidas64_boardid {
601         BOARD_PCIDAS6402_16,
602         BOARD_PCIDAS6402_12,
603         BOARD_PCIDAS64_M1_16,
604         BOARD_PCIDAS64_M2_16,
605         BOARD_PCIDAS64_M3_16,
606         BOARD_PCIDAS6013,
607         BOARD_PCIDAS6014,
608         BOARD_PCIDAS6023,
609         BOARD_PCIDAS6025,
610         BOARD_PCIDAS6030,
611         BOARD_PCIDAS6031,
612         BOARD_PCIDAS6032,
613         BOARD_PCIDAS6033,
614         BOARD_PCIDAS6034,
615         BOARD_PCIDAS6035,
616         BOARD_PCIDAS6036,
617         BOARD_PCIDAS6040,
618         BOARD_PCIDAS6052,
619         BOARD_PCIDAS6070,
620         BOARD_PCIDAS6071,
621         BOARD_PCIDAS4020_12,
622         BOARD_PCIDAS6402_16_JR,
623         BOARD_PCIDAS64_M1_16_JR,
624         BOARD_PCIDAS64_M2_16_JR,
625         BOARD_PCIDAS64_M3_16_JR,
626         BOARD_PCIDAS64_M1_14,
627         BOARD_PCIDAS64_M2_14,
628         BOARD_PCIDAS64_M3_14,
629 };
630 
631 struct pcidas64_board {
632         const char *name;
633         int ai_se_chans;        /* number of ai inputs in single-ended mode */
634         int ai_bits;            /* analog input resolution */
635         int ai_speed;           /* fastest conversion period in ns */
636         const struct comedi_lrange *ai_range_table;
637         const uint8_t *ai_range_code;
638         int ao_nchan;           /* number of analog out channels */
639         int ao_bits;            /* analog output resolution */
640         int ao_scan_speed;      /* analog output scan speed */
641         const struct comedi_lrange *ao_range_table;
642         const int *ao_range_code;
643         const struct hw_fifo_info *const ai_fifo;
644         /* different board families have slightly different registers */
645         enum register_layout layout;
646         unsigned has_8255:1;
647 };
648 
649 static const struct hw_fifo_info ai_fifo_4020 = {
650         .num_segments = 2,
651         .max_segment_length = 0x8000,
652         .sample_packing_ratio = 2,
653         .fifo_size_reg_mask = 0x7f,
654 };
655 
656 static const struct hw_fifo_info ai_fifo_64xx = {
657         .num_segments = 4,
658         .max_segment_length = 0x800,
659         .sample_packing_ratio = 1,
660         .fifo_size_reg_mask = 0x3f,
661 };
662 
663 static const struct hw_fifo_info ai_fifo_60xx = {
664         .num_segments = 4,
665         .max_segment_length = 0x800,
666         .sample_packing_ratio = 1,
667         .fifo_size_reg_mask = 0x7f,
668 };
669 
670 /*
671  * maximum number of dma transfers we will chain together into a ring
672  * (and the maximum number of dma buffers we maintain)
673  */
674 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
675 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
676 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
677 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
678 {
679         if (board->layout == LAYOUT_4020)
680                 return MAX_AI_DMA_RING_COUNT;
681 
682         return MIN_AI_DMA_RING_COUNT;
683 }
684 
685 static const int bytes_in_sample = 2;
686 
687 static const struct pcidas64_board pcidas64_boards[] = {
688         [BOARD_PCIDAS6402_16] = {
689                 .name           = "pci-das6402/16",
690                 .ai_se_chans    = 64,
691                 .ai_bits        = 16,
692                 .ai_speed       = 5000,
693                 .ao_nchan       = 2,
694                 .ao_bits        = 16,
695                 .ao_scan_speed  = 10000,
696                 .layout         = LAYOUT_64XX,
697                 .ai_range_table = &ai_ranges_64xx,
698                 .ai_range_code  = ai_range_code_64xx,
699                 .ao_range_table = &ao_ranges_64xx,
700                 .ao_range_code  = ao_range_code_64xx,
701                 .ai_fifo        = &ai_fifo_64xx,
702                 .has_8255       = 1,
703         },
704         [BOARD_PCIDAS6402_12] = {
705                 .name           = "pci-das6402/12",     /* XXX check */
706                 .ai_se_chans    = 64,
707                 .ai_bits        = 12,
708                 .ai_speed       = 5000,
709                 .ao_nchan       = 2,
710                 .ao_bits        = 12,
711                 .ao_scan_speed  = 10000,
712                 .layout         = LAYOUT_64XX,
713                 .ai_range_table = &ai_ranges_64xx,
714                 .ai_range_code  = ai_range_code_64xx,
715                 .ao_range_table = &ao_ranges_64xx,
716                 .ao_range_code  = ao_range_code_64xx,
717                 .ai_fifo        = &ai_fifo_64xx,
718                 .has_8255       = 1,
719         },
720         [BOARD_PCIDAS64_M1_16] = {
721                 .name           = "pci-das64/m1/16",
722                 .ai_se_chans    = 64,
723                 .ai_bits        = 16,
724                 .ai_speed       = 1000,
725                 .ao_nchan       = 2,
726                 .ao_bits        = 16,
727                 .ao_scan_speed  = 10000,
728                 .layout         = LAYOUT_64XX,
729                 .ai_range_table = &ai_ranges_64_mx,
730                 .ai_range_code  = ai_range_code_64_mx,
731                 .ao_range_table = &ao_ranges_64xx,
732                 .ao_range_code  = ao_range_code_64xx,
733                 .ai_fifo        = &ai_fifo_64xx,
734                 .has_8255       = 1,
735         },
736         [BOARD_PCIDAS64_M2_16] = {
737                 .name = "pci-das64/m2/16",
738                 .ai_se_chans    = 64,
739                 .ai_bits        = 16,
740                 .ai_speed       = 500,
741                 .ao_nchan       = 2,
742                 .ao_bits        = 16,
743                 .ao_scan_speed  = 10000,
744                 .layout         = LAYOUT_64XX,
745                 .ai_range_table = &ai_ranges_64_mx,
746                 .ai_range_code  = ai_range_code_64_mx,
747                 .ao_range_table = &ao_ranges_64xx,
748                 .ao_range_code  = ao_range_code_64xx,
749                 .ai_fifo        = &ai_fifo_64xx,
750                 .has_8255       = 1,
751         },
752         [BOARD_PCIDAS64_M3_16] = {
753                 .name           = "pci-das64/m3/16",
754                 .ai_se_chans    = 64,
755                 .ai_bits        = 16,
756                 .ai_speed       = 333,
757                 .ao_nchan       = 2,
758                 .ao_bits        = 16,
759                 .ao_scan_speed  = 10000,
760                 .layout         = LAYOUT_64XX,
761                 .ai_range_table = &ai_ranges_64_mx,
762                 .ai_range_code  = ai_range_code_64_mx,
763                 .ao_range_table = &ao_ranges_64xx,
764                 .ao_range_code  = ao_range_code_64xx,
765                 .ai_fifo        = &ai_fifo_64xx,
766                 .has_8255       = 1,
767         },
768         [BOARD_PCIDAS6013] = {
769                 .name           = "pci-das6013",
770                 .ai_se_chans    = 16,
771                 .ai_bits        = 16,
772                 .ai_speed       = 5000,
773                 .ao_nchan       = 0,
774                 .ao_bits        = 16,
775                 .layout         = LAYOUT_60XX,
776                 .ai_range_table = &ai_ranges_60xx,
777                 .ai_range_code  = ai_range_code_60xx,
778                 .ao_range_table = &range_bipolar10,
779                 .ao_range_code  = ao_range_code_60xx,
780                 .ai_fifo        = &ai_fifo_60xx,
781                 .has_8255       = 0,
782         },
783         [BOARD_PCIDAS6014] = {
784                 .name           = "pci-das6014",
785                 .ai_se_chans    = 16,
786                 .ai_bits        = 16,
787                 .ai_speed       = 5000,
788                 .ao_nchan       = 2,
789                 .ao_bits        = 16,
790                 .ao_scan_speed  = 100000,
791                 .layout         = LAYOUT_60XX,
792                 .ai_range_table = &ai_ranges_60xx,
793                 .ai_range_code  = ai_range_code_60xx,
794                 .ao_range_table = &range_bipolar10,
795                 .ao_range_code  = ao_range_code_60xx,
796                 .ai_fifo        = &ai_fifo_60xx,
797                 .has_8255       = 0,
798         },
799         [BOARD_PCIDAS6023] = {
800                 .name           = "pci-das6023",
801                 .ai_se_chans    = 16,
802                 .ai_bits        = 12,
803                 .ai_speed       = 5000,
804                 .ao_nchan       = 0,
805                 .ao_scan_speed  = 100000,
806                 .layout         = LAYOUT_60XX,
807                 .ai_range_table = &ai_ranges_60xx,
808                 .ai_range_code  = ai_range_code_60xx,
809                 .ao_range_table = &range_bipolar10,
810                 .ao_range_code  = ao_range_code_60xx,
811                 .ai_fifo        = &ai_fifo_60xx,
812                 .has_8255       = 1,
813         },
814         [BOARD_PCIDAS6025] = {
815                 .name           = "pci-das6025",
816                 .ai_se_chans    = 16,
817                 .ai_bits        = 12,
818                 .ai_speed       = 5000,
819                 .ao_nchan       = 2,
820                 .ao_bits        = 12,
821                 .ao_scan_speed  = 100000,
822                 .layout         = LAYOUT_60XX,
823                 .ai_range_table = &ai_ranges_60xx,
824                 .ai_range_code  = ai_range_code_60xx,
825                 .ao_range_table = &range_bipolar10,
826                 .ao_range_code  = ao_range_code_60xx,
827                 .ai_fifo        = &ai_fifo_60xx,
828                 .has_8255       = 1,
829         },
830         [BOARD_PCIDAS6030] = {
831                 .name           = "pci-das6030",
832                 .ai_se_chans    = 16,
833                 .ai_bits        = 16,
834                 .ai_speed       = 10000,
835                 .ao_nchan       = 2,
836                 .ao_bits        = 16,
837                 .ao_scan_speed  = 10000,
838                 .layout         = LAYOUT_60XX,
839                 .ai_range_table = &ai_ranges_6030,
840                 .ai_range_code  = ai_range_code_6030,
841                 .ao_range_table = &ao_ranges_6030,
842                 .ao_range_code  = ao_range_code_6030,
843                 .ai_fifo        = &ai_fifo_60xx,
844                 .has_8255       = 0,
845         },
846         [BOARD_PCIDAS6031] = {
847                 .name           = "pci-das6031",
848                 .ai_se_chans    = 64,
849                 .ai_bits        = 16,
850                 .ai_speed       = 10000,
851                 .ao_nchan       = 2,
852                 .ao_bits        = 16,
853                 .ao_scan_speed  = 10000,
854                 .layout         = LAYOUT_60XX,
855                 .ai_range_table = &ai_ranges_6030,
856                 .ai_range_code  = ai_range_code_6030,
857                 .ao_range_table = &ao_ranges_6030,
858                 .ao_range_code  = ao_range_code_6030,
859                 .ai_fifo        = &ai_fifo_60xx,
860                 .has_8255       = 0,
861         },
862         [BOARD_PCIDAS6032] = {
863                 .name           = "pci-das6032",
864                 .ai_se_chans    = 16,
865                 .ai_bits        = 16,
866                 .ai_speed       = 10000,
867                 .ao_nchan       = 0,
868                 .layout         = LAYOUT_60XX,
869                 .ai_range_table = &ai_ranges_6030,
870                 .ai_range_code  = ai_range_code_6030,
871                 .ai_fifo        = &ai_fifo_60xx,
872                 .has_8255       = 0,
873         },
874         [BOARD_PCIDAS6033] = {
875                 .name           = "pci-das6033",
876                 .ai_se_chans    = 64,
877                 .ai_bits        = 16,
878                 .ai_speed       = 10000,
879                 .ao_nchan       = 0,
880                 .layout         = LAYOUT_60XX,
881                 .ai_range_table = &ai_ranges_6030,
882                 .ai_range_code  = ai_range_code_6030,
883                 .ai_fifo        = &ai_fifo_60xx,
884                 .has_8255       = 0,
885         },
886         [BOARD_PCIDAS6034] = {
887                 .name           = "pci-das6034",
888                 .ai_se_chans    = 16,
889                 .ai_bits        = 16,
890                 .ai_speed       = 5000,
891                 .ao_nchan       = 0,
892                 .ao_scan_speed  = 0,
893                 .layout         = LAYOUT_60XX,
894                 .ai_range_table = &ai_ranges_60xx,
895                 .ai_range_code  = ai_range_code_60xx,
896                 .ai_fifo        = &ai_fifo_60xx,
897                 .has_8255       = 0,
898         },
899         [BOARD_PCIDAS6035] = {
900                 .name           = "pci-das6035",
901                 .ai_se_chans    = 16,
902                 .ai_bits        = 16,
903                 .ai_speed       = 5000,
904                 .ao_nchan       = 2,
905                 .ao_bits        = 12,
906                 .ao_scan_speed  = 100000,
907                 .layout         = LAYOUT_60XX,
908                 .ai_range_table = &ai_ranges_60xx,
909                 .ai_range_code  = ai_range_code_60xx,
910                 .ao_range_table = &range_bipolar10,
911                 .ao_range_code  = ao_range_code_60xx,
912                 .ai_fifo        = &ai_fifo_60xx,
913                 .has_8255       = 0,
914         },
915         [BOARD_PCIDAS6036] = {
916                 .name           = "pci-das6036",
917                 .ai_se_chans    = 16,
918                 .ai_bits        = 16,
919                 .ai_speed       = 5000,
920                 .ao_nchan       = 2,
921                 .ao_bits        = 16,
922                 .ao_scan_speed  = 100000,
923                 .layout         = LAYOUT_60XX,
924                 .ai_range_table = &ai_ranges_60xx,
925                 .ai_range_code  = ai_range_code_60xx,
926                 .ao_range_table = &range_bipolar10,
927                 .ao_range_code  = ao_range_code_60xx,
928                 .ai_fifo        = &ai_fifo_60xx,
929                 .has_8255       = 0,
930         },
931         [BOARD_PCIDAS6040] = {
932                 .name           = "pci-das6040",
933                 .ai_se_chans    = 16,
934                 .ai_bits        = 12,
935                 .ai_speed       = 2000,
936                 .ao_nchan       = 2,
937                 .ao_bits        = 12,
938                 .ao_scan_speed  = 1000,
939                 .layout         = LAYOUT_60XX,
940                 .ai_range_table = &ai_ranges_6052,
941                 .ai_range_code  = ai_range_code_6052,
942                 .ao_range_table = &ao_ranges_6030,
943                 .ao_range_code  = ao_range_code_6030,
944                 .ai_fifo        = &ai_fifo_60xx,
945                 .has_8255       = 0,
946         },
947         [BOARD_PCIDAS6052] = {
948                 .name           = "pci-das6052",
949                 .ai_se_chans    = 16,
950                 .ai_bits        = 16,
951                 .ai_speed       = 3333,
952                 .ao_nchan       = 2,
953                 .ao_bits        = 16,
954                 .ao_scan_speed  = 3333,
955                 .layout         = LAYOUT_60XX,
956                 .ai_range_table = &ai_ranges_6052,
957                 .ai_range_code  = ai_range_code_6052,
958                 .ao_range_table = &ao_ranges_6030,
959                 .ao_range_code  = ao_range_code_6030,
960                 .ai_fifo        = &ai_fifo_60xx,
961                 .has_8255       = 0,
962         },
963         [BOARD_PCIDAS6070] = {
964                 .name           = "pci-das6070",
965                 .ai_se_chans    = 16,
966                 .ai_bits        = 12,
967                 .ai_speed       = 800,
968                 .ao_nchan       = 2,
969                 .ao_bits        = 12,
970                 .ao_scan_speed  = 1000,
971                 .layout         = LAYOUT_60XX,
972                 .ai_range_table = &ai_ranges_6052,
973                 .ai_range_code  = ai_range_code_6052,
974                 .ao_range_table = &ao_ranges_6030,
975                 .ao_range_code  = ao_range_code_6030,
976                 .ai_fifo        = &ai_fifo_60xx,
977                 .has_8255       = 0,
978         },
979         [BOARD_PCIDAS6071] = {
980                 .name           = "pci-das6071",
981                 .ai_se_chans    = 64,
982                 .ai_bits        = 12,
983                 .ai_speed       = 800,
984                 .ao_nchan       = 2,
985                 .ao_bits        = 12,
986                 .ao_scan_speed  = 1000,
987                 .layout         = LAYOUT_60XX,
988                 .ai_range_table = &ai_ranges_6052,
989                 .ai_range_code  = ai_range_code_6052,
990                 .ao_range_table = &ao_ranges_6030,
991                 .ao_range_code  = ao_range_code_6030,
992                 .ai_fifo        = &ai_fifo_60xx,
993                 .has_8255       = 0,
994         },
995         [BOARD_PCIDAS4020_12] = {
996                 .name           = "pci-das4020/12",
997                 .ai_se_chans    = 4,
998                 .ai_bits        = 12,
999                 .ai_speed       = 50,
1000                 .ao_bits        = 12,
1001                 .ao_nchan       = 2,
1002                 .ao_scan_speed  = 0,    /* no hardware pacing on ao */
1003                 .layout         = LAYOUT_4020,
1004                 .ai_range_table = &ai_ranges_4020,
1005                 .ao_range_table = &ao_ranges_4020,
1006                 .ao_range_code  = ao_range_code_4020,
1007                 .ai_fifo        = &ai_fifo_4020,
1008                 .has_8255       = 1,
1009         },
1010 #if 0
1011         /* The device id for these boards is unknown */
1012 
1013         [BOARD_PCIDAS6402_16_JR] = {
1014                 .name           = "pci-das6402/16/jr",
1015                 .ai_se_chans    = 64,
1016                 .ai_bits        = 16,
1017                 .ai_speed       = 5000,
1018                 .ao_nchan       = 0,
1019                 .ao_scan_speed  = 10000,
1020                 .layout         = LAYOUT_64XX,
1021                 .ai_range_table = &ai_ranges_64xx,
1022                 .ai_range_code  = ai_range_code_64xx,
1023                 .ai_fifo        = ai_fifo_64xx,
1024                 .has_8255       = 1,
1025         },
1026         [BOARD_PCIDAS64_M1_16_JR] = {
1027                 .name           = "pci-das64/m1/16/jr",
1028                 .ai_se_chans    = 64,
1029                 .ai_bits        = 16,
1030                 .ai_speed       = 1000,
1031                 .ao_nchan       = 0,
1032                 .ao_scan_speed  = 10000,
1033                 .layout         = LAYOUT_64XX,
1034                 .ai_range_table = &ai_ranges_64_mx,
1035                 .ai_range_code  = ai_range_code_64_mx,
1036                 .ai_fifo        = ai_fifo_64xx,
1037                 .has_8255       = 1,
1038         },
1039         [BOARD_PCIDAS64_M2_16_JR] = {
1040                 .name = "pci-das64/m2/16/jr",
1041                 .ai_se_chans    = 64,
1042                 .ai_bits        = 16,
1043                 .ai_speed       = 500,
1044                 .ao_nchan       = 0,
1045                 .ao_scan_speed  = 10000,
1046                 .layout         = LAYOUT_64XX,
1047                 .ai_range_table = &ai_ranges_64_mx,
1048                 .ai_range_code  = ai_range_code_64_mx,
1049                 .ai_fifo        = ai_fifo_64xx,
1050                 .has_8255       = 1,
1051         },
1052         [BOARD_PCIDAS64_M3_16_JR] = {
1053                 .name           = "pci-das64/m3/16/jr",
1054                 .ai_se_chans    = 64,
1055                 .ai_bits        = 16,
1056                 .ai_speed       = 333,
1057                 .ao_nchan       = 0,
1058                 .ao_scan_speed  = 10000,
1059                 .layout         = LAYOUT_64XX,
1060                 .ai_range_table = &ai_ranges_64_mx,
1061                 .ai_range_code  = ai_range_code_64_mx,
1062                 .ai_fifo        = ai_fifo_64xx,
1063                 .has_8255       = 1,
1064         },
1065         [BOARD_PCIDAS64_M1_14] = {
1066                 .name           = "pci-das64/m1/14",
1067                 .ai_se_chans    = 64,
1068                 .ai_bits        = 14,
1069                 .ai_speed       = 1000,
1070                 .ao_nchan       = 2,
1071                 .ao_scan_speed  = 10000,
1072                 .layout         = LAYOUT_64XX,
1073                 .ai_range_table = &ai_ranges_64_mx,
1074                 .ai_range_code  = ai_range_code_64_mx,
1075                 .ai_fifo        = ai_fifo_64xx,
1076                 .has_8255       = 1,
1077         },
1078         [BOARD_PCIDAS64_M2_14] = {
1079                 .name           = "pci-das64/m2/14",
1080                 .ai_se_chans    = 64,
1081                 .ai_bits        = 14,
1082                 .ai_speed       = 500,
1083                 .ao_nchan       = 2,
1084                 .ao_scan_speed  = 10000,
1085                 .layout         = LAYOUT_64XX,
1086                 .ai_range_table = &ai_ranges_64_mx,
1087                 .ai_range_code  = ai_range_code_64_mx,
1088                 .ai_fifo        = ai_fifo_64xx,
1089                 .has_8255       = 1,
1090         },
1091         [BOARD_PCIDAS64_M3_14] = {
1092                 .name           = "pci-das64/m3/14",
1093                 .ai_se_chans    = 64,
1094                 .ai_bits        = 14,
1095                 .ai_speed       = 333,
1096                 .ao_nchan       = 2,
1097                 .ao_scan_speed  = 10000,
1098                 .layout         = LAYOUT_64XX,
1099                 .ai_range_table = &ai_ranges_64_mx,
1100                 .ai_range_code  = ai_range_code_64_mx,
1101                 .ai_fifo        = ai_fifo_64xx,
1102                 .has_8255       = 1,
1103         },
1104 #endif
1105 };
1106 
1107 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1108                                               int use_differential)
1109 {
1110         const struct pcidas64_board *board = dev->board_ptr;
1111 
1112         if ((board->layout == LAYOUT_64XX && !use_differential) ||
1113             (board->layout == LAYOUT_60XX && use_differential))
1114                 return ADC_SE_DIFF_BIT;
1115 
1116         return 0;
1117 }
1118 
1119 struct ext_clock_info {
1120         /* master clock divisor to use for scans with external master clock */
1121         unsigned int divisor;
1122         /* chanspec for master clock input when used as scan begin src */
1123         unsigned int chanspec;
1124 };
1125 
1126 /* this structure is for data unique to this hardware driver. */
1127 struct pcidas64_private {
1128         /* base addresses (physical) */
1129         resource_size_t main_phys_iobase;
1130         resource_size_t dio_counter_phys_iobase;
1131         /* base addresses (ioremapped) */
1132         void __iomem *plx9080_iobase;
1133         void __iomem *main_iobase;
1134         /* local address (used by dma controller) */
1135         uint32_t local0_iobase;
1136         uint32_t local1_iobase;
1137         /* dma buffers for analog input */
1138         uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];
1139         /* physical addresses of ai dma buffers */
1140         dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1141         /*
1142          * array of ai dma descriptors read by plx9080,
1143          * allocated to get proper alignment
1144          */
1145         struct plx_dma_desc *ai_dma_desc;
1146         /* physical address of ai dma descriptor array */
1147         dma_addr_t ai_dma_desc_bus_addr;
1148         /*
1149          * index of the ai dma descriptor/buffer
1150          * that is currently being used
1151          */
1152         unsigned int ai_dma_index;
1153         /* dma buffers for analog output */
1154         uint16_t *ao_buffer[AO_DMA_RING_COUNT];
1155         /* physical addresses of ao dma buffers */
1156         dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1157         struct plx_dma_desc *ao_dma_desc;
1158         dma_addr_t ao_dma_desc_bus_addr;
1159         /* keeps track of buffer where the next ao sample should go */
1160         unsigned int ao_dma_index;
1161         unsigned int hw_revision;       /* stc chip hardware revision number */
1162         /* last bits sent to INTR_ENABLE_REG register */
1163         unsigned int intr_enable_bits;
1164         /* last bits sent to ADC_CONTROL1_REG register */
1165         uint16_t adc_control1_bits;
1166         /* last bits sent to FIFO_SIZE_REG register */
1167         uint16_t fifo_size_bits;
1168         /* last bits sent to HW_CONFIG_REG register */
1169         uint16_t hw_config_bits;
1170         uint16_t dac_control1_bits;
1171         /* last bits written to plx9080 control register */
1172         uint32_t plx_control_bits;
1173         /* last bits written to plx interrupt control and status register */
1174         uint32_t plx_intcsr_bits;
1175         /* index of calibration source readable through ai ch0 */
1176         int calibration_source;
1177         /* bits written to i2c calibration/range register */
1178         uint8_t i2c_cal_range_bits;
1179         /* configure digital triggers to trigger on falling edge */
1180         unsigned int ext_trig_falling;
1181         short ai_cmd_running;
1182         unsigned int ai_fifo_segment_length;
1183         struct ext_clock_info ext_clock;
1184         unsigned short ao_bounce_buffer[DAC_FIFO_SIZE];
1185 };
1186 
1187 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1188                                        unsigned int range_index)
1189 {
1190         const struct pcidas64_board *board = dev->board_ptr;
1191 
1192         return board->ai_range_code[range_index] << 8;
1193 }
1194 
1195 static unsigned int hw_revision(const struct comedi_device *dev,
1196                                 uint16_t hw_status_bits)
1197 {
1198         const struct pcidas64_board *board = dev->board_ptr;
1199 
1200         if (board->layout == LAYOUT_4020)
1201                 return (hw_status_bits >> 13) & 0x7;
1202 
1203         return (hw_status_bits >> 12) & 0xf;
1204 }
1205 
1206 static void set_dac_range_bits(struct comedi_device *dev,
1207                                uint16_t *bits, unsigned int channel,
1208                                unsigned int range)
1209 {
1210         const struct pcidas64_board *board = dev->board_ptr;
1211         unsigned int code = board->ao_range_code[range];
1212 
1213         if (channel > 1)
1214                 dev_err(dev->class_dev, "bug! bad channel?\n");
1215         if (code & ~0x3)
1216                 dev_err(dev->class_dev, "bug! bad range code?\n");
1217 
1218         *bits &= ~(0x3 << (2 * channel));
1219         *bits |= code << (2 * channel);
1220 };
1221 
1222 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1223 {
1224         return board->ao_nchan && board->layout != LAYOUT_4020;
1225 }
1226 
1227 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1228 {
1229         struct pcidas64_private *devpriv = dev->private;
1230         unsigned long flags;
1231 
1232         /* spinlock for plx dma control/status reg */
1233         spin_lock_irqsave(&dev->spinlock, flags);
1234 
1235         plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1236 
1237         spin_unlock_irqrestore(&dev->spinlock, flags);
1238 }
1239 
1240 static void disable_plx_interrupts(struct comedi_device *dev)
1241 {
1242         struct pcidas64_private *devpriv = dev->private;
1243 
1244         devpriv->plx_intcsr_bits = 0;
1245         writel(devpriv->plx_intcsr_bits,
1246                devpriv->plx9080_iobase + PLX_REG_INTCSR);
1247 }
1248 
1249 static void disable_ai_interrupts(struct comedi_device *dev)
1250 {
1251         struct pcidas64_private *devpriv = dev->private;
1252         unsigned long flags;
1253 
1254         spin_lock_irqsave(&dev->spinlock, flags);
1255         devpriv->intr_enable_bits &=
1256                 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1257                 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1258                 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1259         writew(devpriv->intr_enable_bits,
1260                devpriv->main_iobase + INTR_ENABLE_REG);
1261         spin_unlock_irqrestore(&dev->spinlock, flags);
1262 }
1263 
1264 static void enable_ai_interrupts(struct comedi_device *dev,
1265                                  const struct comedi_cmd *cmd)
1266 {
1267         const struct pcidas64_board *board = dev->board_ptr;
1268         struct pcidas64_private *devpriv = dev->private;
1269         uint32_t bits;
1270         unsigned long flags;
1271 
1272         bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1273                EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1274         /*
1275          * Use pio transfer and interrupt on end of conversion
1276          * if CMDF_WAKE_EOS flag is set.
1277          */
1278         if (cmd->flags & CMDF_WAKE_EOS) {
1279                 /* 4020 doesn't support pio transfers except for fifo dregs */
1280                 if (board->layout != LAYOUT_4020)
1281                         bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1282         }
1283         spin_lock_irqsave(&dev->spinlock, flags);
1284         devpriv->intr_enable_bits |= bits;
1285         writew(devpriv->intr_enable_bits,
1286                devpriv->main_iobase + INTR_ENABLE_REG);
1287         spin_unlock_irqrestore(&dev->spinlock, flags);
1288 }
1289 
1290 /* initialize plx9080 chip */
1291 static void init_plx9080(struct comedi_device *dev)
1292 {
1293         const struct pcidas64_board *board = dev->board_ptr;
1294         struct pcidas64_private *devpriv = dev->private;
1295         uint32_t bits;
1296         void __iomem *plx_iobase = devpriv->plx9080_iobase;
1297 
1298         devpriv->plx_control_bits =
1299                 readl(devpriv->plx9080_iobase + PLX_REG_CNTRL);
1300 
1301 #ifdef __BIG_ENDIAN
1302         bits = PLX_BIGEND_DMA0 | PLX_BIGEND_DMA1;
1303 #else
1304         bits = 0;
1305 #endif
1306         writel(bits, devpriv->plx9080_iobase + PLX_REG_BIGEND);
1307 
1308         disable_plx_interrupts(dev);
1309 
1310         abort_dma(dev, 0);
1311         abort_dma(dev, 1);
1312 
1313         /* configure dma0 mode */
1314         bits = 0;
1315         /* enable ready input, not sure if this is necessary */
1316         bits |= PLX_DMAMODE_READYIEN;
1317         /* enable bterm, not sure if this is necessary */
1318         bits |= PLX_DMAMODE_BTERMIEN;
1319         /* enable dma chaining */
1320         bits |= PLX_DMAMODE_CHAINEN;
1321         /*
1322          * enable interrupt on dma done
1323          * (probably don't need this, since chain never finishes)
1324          */
1325         bits |= PLX_DMAMODE_DONEIEN;
1326         /*
1327          * don't increment local address during transfers
1328          * (we are transferring from a fixed fifo register)
1329          */
1330         bits |= PLX_DMAMODE_LACONST;
1331         /* route dma interrupt to pci bus */
1332         bits |= PLX_DMAMODE_INTRPCI;
1333         /* enable demand mode */
1334         bits |= PLX_DMAMODE_DEMAND;
1335         /* enable local burst mode */
1336         bits |= PLX_DMAMODE_BURSTEN;
1337         /* 4020 uses 32 bit dma */
1338         if (board->layout == LAYOUT_4020)
1339                 bits |= PLX_DMAMODE_WIDTH_32;
1340         else                            /* localspace0 bus is 16 bits wide */
1341                 bits |= PLX_DMAMODE_WIDTH_16;
1342         writel(bits, plx_iobase + PLX_REG_DMAMODE1);
1343         if (ao_cmd_is_supported(board))
1344                 writel(bits, plx_iobase + PLX_REG_DMAMODE0);
1345 
1346         /* enable interrupts on plx 9080 */
1347         devpriv->plx_intcsr_bits |=
1348             PLX_INTCSR_LSEABORTEN | PLX_INTCSR_LSEPARITYEN | PLX_INTCSR_PIEN |
1349             PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN |
1350             PLX_INTCSR_DMA0IEN | PLX_INTCSR_DMA1IEN;
1351         writel(devpriv->plx_intcsr_bits,
1352                devpriv->plx9080_iobase + PLX_REG_INTCSR);
1353 }
1354 
1355 static void disable_ai_pacing(struct comedi_device *dev)
1356 {
1357         struct pcidas64_private *devpriv = dev->private;
1358         unsigned long flags;
1359 
1360         disable_ai_interrupts(dev);
1361 
1362         spin_lock_irqsave(&dev->spinlock, flags);
1363         devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1364         writew(devpriv->adc_control1_bits,
1365                devpriv->main_iobase + ADC_CONTROL1_REG);
1366         spin_unlock_irqrestore(&dev->spinlock, flags);
1367 
1368         /* disable pacing, triggering, etc */
1369         writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1370                devpriv->main_iobase + ADC_CONTROL0_REG);
1371 }
1372 
1373 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1374                                       unsigned int num_entries)
1375 {
1376         const struct pcidas64_board *board = dev->board_ptr;
1377         struct pcidas64_private *devpriv = dev->private;
1378         static const int increment_size = 0x100;
1379         const struct hw_fifo_info *const fifo = board->ai_fifo;
1380         unsigned int num_increments;
1381         uint16_t bits;
1382 
1383         if (num_entries < increment_size)
1384                 num_entries = increment_size;
1385         if (num_entries > fifo->max_segment_length)
1386                 num_entries = fifo->max_segment_length;
1387 
1388         /* 1 == 256 entries, 2 == 512 entries, etc */
1389         num_increments = DIV_ROUND_CLOSEST(num_entries, increment_size);
1390 
1391         bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1392         devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1393         devpriv->fifo_size_bits |= bits;
1394         writew(devpriv->fifo_size_bits,
1395                devpriv->main_iobase + FIFO_SIZE_REG);
1396 
1397         devpriv->ai_fifo_segment_length = num_increments * increment_size;
1398 
1399         return devpriv->ai_fifo_segment_length;
1400 }
1401 
1402 /*
1403  * adjusts the size of hardware fifo (which determines block size for dma xfers)
1404  */
1405 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1406 {
1407         const struct pcidas64_board *board = dev->board_ptr;
1408         unsigned int num_fifo_entries;
1409         int retval;
1410         const struct hw_fifo_info *const fifo = board->ai_fifo;
1411 
1412         num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1413 
1414         retval = set_ai_fifo_segment_length(dev,
1415                                             num_fifo_entries /
1416                                             fifo->num_segments);
1417         if (retval < 0)
1418                 return retval;
1419 
1420         num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
1421 
1422         return num_samples;
1423 }
1424 
1425 /* query length of fifo */
1426 static unsigned int ai_fifo_size(struct comedi_device *dev)
1427 {
1428         const struct pcidas64_board *board = dev->board_ptr;
1429         struct pcidas64_private *devpriv = dev->private;
1430 
1431         return devpriv->ai_fifo_segment_length *
1432                board->ai_fifo->num_segments *
1433                board->ai_fifo->sample_packing_ratio;
1434 }
1435 
1436 static void init_stc_registers(struct comedi_device *dev)
1437 {
1438         const struct pcidas64_board *board = dev->board_ptr;
1439         struct pcidas64_private *devpriv = dev->private;
1440         uint16_t bits;
1441         unsigned long flags;
1442 
1443         spin_lock_irqsave(&dev->spinlock, flags);
1444 
1445         /*
1446          * bit should be set for 6025,
1447          * although docs say boards with <= 16 chans should be cleared XXX
1448          */
1449         if (1)
1450                 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1451         writew(devpriv->adc_control1_bits,
1452                devpriv->main_iobase + ADC_CONTROL1_REG);
1453 
1454         /* 6402/16 manual says this register must be initialized to 0xff? */
1455         writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1456 
1457         bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1458         if (board->layout == LAYOUT_4020)
1459                 bits |= INTERNAL_CLOCK_4020_BITS;
1460         devpriv->hw_config_bits |= bits;
1461         writew(devpriv->hw_config_bits,
1462                devpriv->main_iobase + HW_CONFIG_REG);
1463 
1464         writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1465         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1466 
1467         spin_unlock_irqrestore(&dev->spinlock, flags);
1468 
1469         /* set fifos to maximum size */
1470         devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1471         set_ai_fifo_segment_length(dev, board->ai_fifo->max_segment_length);
1472 
1473         devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1474         devpriv->intr_enable_bits =
1475                 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1476                 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1477         writew(devpriv->intr_enable_bits,
1478                devpriv->main_iobase + INTR_ENABLE_REG);
1479 
1480         disable_ai_pacing(dev);
1481 };
1482 
1483 static int alloc_and_init_dma_members(struct comedi_device *dev)
1484 {
1485         const struct pcidas64_board *board = dev->board_ptr;
1486         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1487         struct pcidas64_private *devpriv = dev->private;
1488         int i;
1489 
1490         /* allocate pci dma buffers */
1491         for (i = 0; i < ai_dma_ring_count(board); i++) {
1492                 devpriv->ai_buffer[i] =
1493                         dma_alloc_coherent(&pcidev->dev, DMA_BUFFER_SIZE,
1494                                            &devpriv->ai_buffer_bus_addr[i],
1495                                            GFP_KERNEL);
1496                 if (!devpriv->ai_buffer[i])
1497                         return -ENOMEM;
1498         }
1499         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1500                 if (ao_cmd_is_supported(board)) {
1501                         devpriv->ao_buffer[i] =
1502                                 dma_alloc_coherent(&pcidev->dev,
1503                                                    DMA_BUFFER_SIZE,
1504                                                    &devpriv->
1505                                                    ao_buffer_bus_addr[i],
1506                                                    GFP_KERNEL);
1507                         if (!devpriv->ao_buffer[i])
1508                                 return -ENOMEM;
1509                 }
1510         }
1511         /* allocate dma descriptors */
1512         devpriv->ai_dma_desc =
1513                 dma_alloc_coherent(&pcidev->dev, sizeof(struct plx_dma_desc) *
1514                                    ai_dma_ring_count(board),
1515                                    &devpriv->ai_dma_desc_bus_addr, GFP_KERNEL);
1516         if (!devpriv->ai_dma_desc)
1517                 return -ENOMEM;
1518 
1519         if (ao_cmd_is_supported(board)) {
1520                 devpriv->ao_dma_desc =
1521                         dma_alloc_coherent(&pcidev->dev,
1522                                            sizeof(struct plx_dma_desc) *
1523                                            AO_DMA_RING_COUNT,
1524                                            &devpriv->ao_dma_desc_bus_addr,
1525                                            GFP_KERNEL);
1526                 if (!devpriv->ao_dma_desc)
1527                         return -ENOMEM;
1528         }
1529         /* initialize dma descriptors */
1530         for (i = 0; i < ai_dma_ring_count(board); i++) {
1531                 devpriv->ai_dma_desc[i].pci_start_addr =
1532                         cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1533                 if (board->layout == LAYOUT_4020)
1534                         devpriv->ai_dma_desc[i].local_start_addr =
1535                                 cpu_to_le32(devpriv->local1_iobase +
1536                                             ADC_FIFO_REG);
1537                 else
1538                         devpriv->ai_dma_desc[i].local_start_addr =
1539                                 cpu_to_le32(devpriv->local0_iobase +
1540                                             ADC_FIFO_REG);
1541                 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1542                 devpriv->ai_dma_desc[i].next =
1543                         cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1544                                      ((i + 1) % ai_dma_ring_count(board)) *
1545                                      sizeof(devpriv->ai_dma_desc[0])) |
1546                                     PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR |
1547                                     PLX_DMADPR_XFERL2P);
1548         }
1549         if (ao_cmd_is_supported(board)) {
1550                 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1551                         devpriv->ao_dma_desc[i].pci_start_addr =
1552                                 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1553                         devpriv->ao_dma_desc[i].local_start_addr =
1554                                 cpu_to_le32(devpriv->local0_iobase +
1555                                             DAC_FIFO_REG);
1556                         devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1557                         devpriv->ao_dma_desc[i].next =
1558                                 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1559                                              ((i + 1) % (AO_DMA_RING_COUNT)) *
1560                                              sizeof(devpriv->ao_dma_desc[0])) |
1561                                             PLX_DMADPR_DESCPCI |
1562                                             PLX_DMADPR_TCINTR);
1563                 }
1564         }
1565         return 0;
1566 }
1567 
1568 static void cb_pcidas64_free_dma(struct comedi_device *dev)
1569 {
1570         const struct pcidas64_board *board = dev->board_ptr;
1571         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1572         struct pcidas64_private *devpriv = dev->private;
1573         int i;
1574 
1575         if (!devpriv)
1576                 return;
1577 
1578         /* free pci dma buffers */
1579         for (i = 0; i < ai_dma_ring_count(board); i++) {
1580                 if (devpriv->ai_buffer[i])
1581                         dma_free_coherent(&pcidev->dev,
1582                                           DMA_BUFFER_SIZE,
1583                                           devpriv->ai_buffer[i],
1584                                           devpriv->ai_buffer_bus_addr[i]);
1585         }
1586         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1587                 if (devpriv->ao_buffer[i])
1588                         dma_free_coherent(&pcidev->dev,
1589                                           DMA_BUFFER_SIZE,
1590                                           devpriv->ao_buffer[i],
1591                                           devpriv->ao_buffer_bus_addr[i]);
1592         }
1593         /* free dma descriptors */
1594         if (devpriv->ai_dma_desc)
1595                 dma_free_coherent(&pcidev->dev,
1596                                   sizeof(struct plx_dma_desc) *
1597                                   ai_dma_ring_count(board),
1598                                   devpriv->ai_dma_desc,
1599                                   devpriv->ai_dma_desc_bus_addr);
1600         if (devpriv->ao_dma_desc)
1601                 dma_free_coherent(&pcidev->dev,
1602                                   sizeof(struct plx_dma_desc) *
1603                                   AO_DMA_RING_COUNT,
1604                                   devpriv->ao_dma_desc,
1605                                   devpriv->ao_dma_desc_bus_addr);
1606 }
1607 
1608 static inline void warn_external_queue(struct comedi_device *dev)
1609 {
1610         dev_err(dev->class_dev,
1611                 "AO command and AI external channel queue cannot be used simultaneously\n");
1612         dev_err(dev->class_dev,
1613                 "Use internal AI channel queue (channels must be consecutive and use same range/aref)\n");
1614 }
1615 
1616 /*
1617  * their i2c requires a huge delay on setting clock or data high for some reason
1618  */
1619 static const int i2c_high_udelay = 1000;
1620 static const int i2c_low_udelay = 10;
1621 
1622 /* set i2c data line high or low */
1623 static void i2c_set_sda(struct comedi_device *dev, int state)
1624 {
1625         struct pcidas64_private *devpriv = dev->private;
1626         static const int data_bit = PLX_CNTRL_EEWB;
1627         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1628                                          PLX_REG_CNTRL;
1629 
1630         if (state) {                            /* set data line high */
1631                 devpriv->plx_control_bits &= ~data_bit;
1632                 writel(devpriv->plx_control_bits, plx_control_addr);
1633                 udelay(i2c_high_udelay);
1634         } else {                                /* set data line low */
1635                 devpriv->plx_control_bits |= data_bit;
1636                 writel(devpriv->plx_control_bits, plx_control_addr);
1637                 udelay(i2c_low_udelay);
1638         }
1639 }
1640 
1641 /* set i2c clock line high or low */
1642 static void i2c_set_scl(struct comedi_device *dev, int state)
1643 {
1644         struct pcidas64_private *devpriv = dev->private;
1645         static const int clock_bit = PLX_CNTRL_USERO;
1646         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1647                                          PLX_REG_CNTRL;
1648 
1649         if (state) {                            /* set clock line high */
1650                 devpriv->plx_control_bits &= ~clock_bit;
1651                 writel(devpriv->plx_control_bits, plx_control_addr);
1652                 udelay(i2c_high_udelay);
1653         } else {                                /* set clock line low */
1654                 devpriv->plx_control_bits |= clock_bit;
1655                 writel(devpriv->plx_control_bits, plx_control_addr);
1656                 udelay(i2c_low_udelay);
1657         }
1658 }
1659 
1660 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
1661 {
1662         uint8_t bit;
1663         unsigned int num_bits = 8;
1664 
1665         for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1666                 i2c_set_scl(dev, 0);
1667                 if ((byte & bit))
1668                         i2c_set_sda(dev, 1);
1669                 else
1670                         i2c_set_sda(dev, 0);
1671                 i2c_set_scl(dev, 1);
1672         }
1673 }
1674 
1675 /* we can't really read the lines, so fake it */
1676 static int i2c_read_ack(struct comedi_device *dev)
1677 {
1678         i2c_set_scl(dev, 0);
1679         i2c_set_sda(dev, 1);
1680         i2c_set_scl(dev, 1);
1681 
1682         return 0;               /* return fake acknowledge bit */
1683 }
1684 
1685 /* send start bit */
1686 static void i2c_start(struct comedi_device *dev)
1687 {
1688         i2c_set_scl(dev, 1);
1689         i2c_set_sda(dev, 1);
1690         i2c_set_sda(dev, 0);
1691 }
1692 
1693 /* send stop bit */
1694 static void i2c_stop(struct comedi_device *dev)
1695 {
1696         i2c_set_scl(dev, 0);
1697         i2c_set_sda(dev, 0);
1698         i2c_set_scl(dev, 1);
1699         i2c_set_sda(dev, 1);
1700 }
1701 
1702 static void i2c_write(struct comedi_device *dev, unsigned int address,
1703                       const uint8_t *data, unsigned int length)
1704 {
1705         struct pcidas64_private *devpriv = dev->private;
1706         unsigned int i;
1707         uint8_t bitstream;
1708         static const int read_bit = 0x1;
1709 
1710         /*
1711          * XXX need mutex to prevent simultaneous attempts to access
1712          * eeprom and i2c bus
1713          */
1714 
1715         /* make sure we dont send anything to eeprom */
1716         devpriv->plx_control_bits &= ~PLX_CNTRL_EECS;
1717 
1718         i2c_stop(dev);
1719         i2c_start(dev);
1720 
1721         /* send address and write bit */
1722         bitstream = (address << 1) & ~read_bit;
1723         i2c_write_byte(dev, bitstream);
1724 
1725         /* get acknowledge */
1726         if (i2c_read_ack(dev) != 0) {
1727                 dev_err(dev->class_dev, "failed: no acknowledge\n");
1728                 i2c_stop(dev);
1729                 return;
1730         }
1731         /* write data bytes */
1732         for (i = 0; i < length; i++) {
1733                 i2c_write_byte(dev, data[i]);
1734                 if (i2c_read_ack(dev) != 0) {
1735                         dev_err(dev->class_dev, "failed: no acknowledge\n");
1736                         i2c_stop(dev);
1737                         return;
1738                 }
1739         }
1740         i2c_stop(dev);
1741 }
1742 
1743 static int cb_pcidas64_ai_eoc(struct comedi_device *dev,
1744                               struct comedi_subdevice *s,
1745                               struct comedi_insn *insn,
1746                               unsigned long context)
1747 {
1748         const struct pcidas64_board *board = dev->board_ptr;
1749         struct pcidas64_private *devpriv = dev->private;
1750         unsigned int status;
1751 
1752         status = readw(devpriv->main_iobase + HW_STATUS_REG);
1753         if (board->layout == LAYOUT_4020) {
1754                 status = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG);
1755                 if (status)
1756                         return 0;
1757         } else {
1758                 if (pipe_full_bits(status))
1759                         return 0;
1760         }
1761         return -EBUSY;
1762 }
1763 
1764 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1765                     struct comedi_insn *insn, unsigned int *data)
1766 {
1767         const struct pcidas64_board *board = dev->board_ptr;
1768         struct pcidas64_private *devpriv = dev->private;
1769         unsigned int bits = 0, n;
1770         unsigned int channel, range, aref;
1771         unsigned long flags;
1772         int ret;
1773 
1774         channel = CR_CHAN(insn->chanspec);
1775         range = CR_RANGE(insn->chanspec);
1776         aref = CR_AREF(insn->chanspec);
1777 
1778         /* disable card's analog input interrupt sources and pacing */
1779         /* 4020 generates dac done interrupts even though they are disabled */
1780         disable_ai_pacing(dev);
1781 
1782         spin_lock_irqsave(&dev->spinlock, flags);
1783         if (insn->chanspec & CR_ALT_FILTER)
1784                 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1785         else
1786                 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1787         writew(devpriv->adc_control1_bits,
1788                devpriv->main_iobase + ADC_CONTROL1_REG);
1789         spin_unlock_irqrestore(&dev->spinlock, flags);
1790 
1791         if (board->layout != LAYOUT_4020) {
1792                 /* use internal queue */
1793                 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1794                 writew(devpriv->hw_config_bits,
1795                        devpriv->main_iobase + HW_CONFIG_REG);
1796 
1797                 /* ALT_SOURCE is internal calibration reference */
1798                 if (insn->chanspec & CR_ALT_SOURCE) {
1799                         unsigned int cal_en_bit;
1800 
1801                         if (board->layout == LAYOUT_60XX)
1802                                 cal_en_bit = CAL_EN_60XX_BIT;
1803                         else
1804                                 cal_en_bit = CAL_EN_64XX_BIT;
1805                         /*
1806                          * select internal reference source to connect
1807                          * to channel 0
1808                          */
1809                         writew(cal_en_bit |
1810                                adc_src_bits(devpriv->calibration_source),
1811                                devpriv->main_iobase + CALIBRATION_REG);
1812                 } else {
1813                         /*
1814                          * make sure internal calibration source
1815                          * is turned off
1816                          */
1817                         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1818                 }
1819                 /* load internal queue */
1820                 bits = 0;
1821                 /* set gain */
1822                 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1823                 /* set single-ended / differential */
1824                 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1825                 if (aref == AREF_COMMON)
1826                         bits |= ADC_COMMON_BIT;
1827                 bits |= adc_chan_bits(channel);
1828                 /* set stop channel */
1829                 writew(adc_chan_bits(channel),
1830                        devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1831                 /* set start channel, and rest of settings */
1832                 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1833         } else {
1834                 uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1835 
1836                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1837                 if (insn->chanspec & CR_ALT_SOURCE) {
1838                         devpriv->i2c_cal_range_bits |=
1839                                 adc_src_4020_bits(devpriv->calibration_source);
1840                 } else {        /* select BNC inputs */
1841                         devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1842                 }
1843                 /* select range */
1844                 if (range == 0)
1845                         devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1846                 else
1847                         devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1848                 /*
1849                  * update calibration/range i2c register only if necessary,
1850                  * as it is very slow
1851                  */
1852                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1853                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1854 
1855                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1856                                   sizeof(i2c_data));
1857                 }
1858 
1859                 /*
1860                  * 4020 manual asks that sample interval register to be set
1861                  * before writing to convert register.
1862                  * Using somewhat arbitrary setting of 4 master clock ticks
1863                  * = 0.1 usec
1864                  */
1865                 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1866                 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1867         }
1868 
1869         for (n = 0; n < insn->n; n++) {
1870                 /* clear adc buffer (inside loop for 4020 sake) */
1871                 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1872 
1873                 /* trigger conversion, bits sent only matter for 4020 */
1874                 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1875                        devpriv->main_iobase + ADC_CONVERT_REG);
1876 
1877                 /* wait for data */
1878                 ret = comedi_timeout(dev, s, insn, cb_pcidas64_ai_eoc, 0);
1879                 if (ret)
1880                         return ret;
1881 
1882                 if (board->layout == LAYOUT_4020)
1883                         data[n] = readl(dev->mmio + ADC_FIFO_REG) & 0xffff;
1884                 else
1885                         data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1886         }
1887 
1888         return n;
1889 }
1890 
1891 static int ai_config_calibration_source(struct comedi_device *dev,
1892                                         unsigned int *data)
1893 {
1894         const struct pcidas64_board *board = dev->board_ptr;
1895         struct pcidas64_private *devpriv = dev->private;
1896         unsigned int source = data[1];
1897         int num_calibration_sources;
1898 
1899         if (board->layout == LAYOUT_60XX)
1900                 num_calibration_sources = 16;
1901         else
1902                 num_calibration_sources = 8;
1903         if (source >= num_calibration_sources) {
1904                 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1905                         source);
1906                 return -EINVAL;
1907         }
1908 
1909         devpriv->calibration_source = source;
1910 
1911         return 2;
1912 }
1913 
1914 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1915 {
1916         const struct pcidas64_board *board = dev->board_ptr;
1917         int fifo_size;
1918         const struct hw_fifo_info *const fifo = board->ai_fifo;
1919         unsigned int block_size, requested_block_size;
1920         int retval;
1921 
1922         requested_block_size = data[1];
1923 
1924         if (requested_block_size) {
1925                 fifo_size = requested_block_size * fifo->num_segments /
1926                             bytes_in_sample;
1927 
1928                 retval = set_ai_fifo_size(dev, fifo_size);
1929                 if (retval < 0)
1930                         return retval;
1931         }
1932 
1933         block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1934 
1935         data[1] = block_size;
1936 
1937         return 2;
1938 }
1939 
1940 static int ai_config_master_clock_4020(struct comedi_device *dev,
1941                                        unsigned int *data)
1942 {
1943         struct pcidas64_private *devpriv = dev->private;
1944         unsigned int divisor = data[4];
1945         int retval = 0;
1946 
1947         if (divisor < 2) {
1948                 divisor = 2;
1949                 retval = -EAGAIN;
1950         }
1951 
1952         switch (data[1]) {
1953         case COMEDI_EV_SCAN_BEGIN:
1954                 devpriv->ext_clock.divisor = divisor;
1955                 devpriv->ext_clock.chanspec = data[2];
1956                 break;
1957         default:
1958                 return -EINVAL;
1959         }
1960 
1961         data[4] = divisor;
1962 
1963         return retval ? retval : 5;
1964 }
1965 
1966 /* XXX could add support for 60xx series */
1967 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1968 {
1969         const struct pcidas64_board *board = dev->board_ptr;
1970 
1971         switch (board->layout) {
1972         case LAYOUT_4020:
1973                 return ai_config_master_clock_4020(dev, data);
1974         default:
1975                 return -EINVAL;
1976         }
1977 
1978         return -EINVAL;
1979 }
1980 
1981 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1982                           struct comedi_insn *insn, unsigned int *data)
1983 {
1984         int id = data[0];
1985 
1986         switch (id) {
1987         case INSN_CONFIG_ALT_SOURCE:
1988                 return ai_config_calibration_source(dev, data);
1989         case INSN_CONFIG_BLOCK_SIZE:
1990                 return ai_config_block_size(dev, data);
1991         case INSN_CONFIG_TIMER_1:
1992                 return ai_config_master_clock(dev, data);
1993         default:
1994                 return -EINVAL;
1995         }
1996         return -EINVAL;
1997 }
1998 
1999 /*
2000  * Gets nearest achievable timing given master clock speed, does not
2001  * take into account possible minimum/maximum divisor values.  Used
2002  * by other timing checking functions.
2003  */
2004 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
2005 {
2006         unsigned int divisor;
2007 
2008         switch (flags & CMDF_ROUND_MASK) {
2009         case CMDF_ROUND_UP:
2010                 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
2011                 break;
2012         case CMDF_ROUND_DOWN:
2013                 divisor = ns / TIMER_BASE;
2014                 break;
2015         case CMDF_ROUND_NEAREST:
2016         default:
2017                 divisor = DIV_ROUND_CLOSEST(ns, TIMER_BASE);
2018                 break;
2019         }
2020         return divisor;
2021 }
2022 
2023 /*
2024  * utility function that rounds desired timing to an achievable time, and
2025  * sets cmd members appropriately.
2026  * adc paces conversions from master clock by dividing by (x + 3) where x is
2027  * 24 bit number
2028  */
2029 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
2030 {
2031         const struct pcidas64_board *board = dev->board_ptr;
2032         unsigned long long convert_divisor = 0;
2033         unsigned int scan_divisor;
2034         static const int min_convert_divisor = 3;
2035         static const int max_convert_divisor =
2036                 max_counter_value + min_convert_divisor;
2037         static const int min_scan_divisor_4020 = 2;
2038         unsigned long long max_scan_divisor, min_scan_divisor;
2039 
2040         if (cmd->convert_src == TRIG_TIMER) {
2041                 if (board->layout == LAYOUT_4020) {
2042                         cmd->convert_arg = 0;
2043                 } else {
2044                         convert_divisor = get_divisor(cmd->convert_arg,
2045                                                       cmd->flags);
2046                         if (convert_divisor > max_convert_divisor)
2047                                 convert_divisor = max_convert_divisor;
2048                         if (convert_divisor < min_convert_divisor)
2049                                 convert_divisor = min_convert_divisor;
2050                         cmd->convert_arg = convert_divisor * TIMER_BASE;
2051                 }
2052         } else if (cmd->convert_src == TRIG_NOW) {
2053                 cmd->convert_arg = 0;
2054         }
2055 
2056         if (cmd->scan_begin_src == TRIG_TIMER) {
2057                 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
2058                 if (cmd->convert_src == TRIG_TIMER) {
2059                         min_scan_divisor = convert_divisor * cmd->chanlist_len;
2060                         max_scan_divisor =
2061                                 (convert_divisor * cmd->chanlist_len - 1) +
2062                                 max_counter_value;
2063                 } else {
2064                         min_scan_divisor = min_scan_divisor_4020;
2065                         max_scan_divisor = max_counter_value + min_scan_divisor;
2066                 }
2067                 if (scan_divisor > max_scan_divisor)
2068                         scan_divisor = max_scan_divisor;
2069                 if (scan_divisor < min_scan_divisor)
2070                         scan_divisor = min_scan_divisor;
2071                 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
2072         }
2073 }
2074 
2075 static int cb_pcidas64_ai_check_chanlist(struct comedi_device *dev,
2076                                          struct comedi_subdevice *s,
2077                                          struct comedi_cmd *cmd)
2078 {
2079         const struct pcidas64_board *board = dev->board_ptr;
2080         unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
2081         int i;
2082 
2083         for (i = 1; i < cmd->chanlist_len; i++) {
2084                 unsigned int aref = CR_AREF(cmd->chanlist[i]);
2085 
2086                 if (aref != aref0) {
2087                         dev_dbg(dev->class_dev,
2088                                 "all elements in chanlist must use the same analog reference\n");
2089                         return -EINVAL;
2090                 }
2091         }
2092 
2093         if (board->layout == LAYOUT_4020) {
2094                 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
2095 
2096                 for (i = 1; i < cmd->chanlist_len; i++) {
2097                         unsigned int chan = CR_CHAN(cmd->chanlist[i]);
2098 
2099                         if (chan != (chan0 + i)) {
2100                                 dev_dbg(dev->class_dev,
2101                                         "chanlist must use consecutive channels\n");
2102                                 return -EINVAL;
2103                         }
2104                 }
2105                 if (cmd->chanlist_len == 3) {
2106                         dev_dbg(dev->class_dev,
2107                                 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels\n");
2108                         return -EINVAL;
2109                 }
2110         }
2111 
2112         return 0;
2113 }
2114 
2115 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2116                       struct comedi_cmd *cmd)
2117 {
2118         const struct pcidas64_board *board = dev->board_ptr;
2119         int err = 0;
2120         unsigned int tmp_arg, tmp_arg2;
2121         unsigned int triggers;
2122 
2123         /* Step 1 : check if triggers are trivially valid */
2124 
2125         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2126 
2127         triggers = TRIG_TIMER;
2128         if (board->layout == LAYOUT_4020)
2129                 triggers |= TRIG_OTHER;
2130         else
2131                 triggers |= TRIG_FOLLOW;
2132         err |= comedi_check_trigger_src(&cmd->scan_begin_src, triggers);
2133 
2134         triggers = TRIG_TIMER;
2135         if (board->layout == LAYOUT_4020)
2136                 triggers |= TRIG_NOW;
2137         else
2138                 triggers |= TRIG_EXT;
2139         err |= comedi_check_trigger_src(&cmd->convert_src, triggers);
2140         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2141         err |= comedi_check_trigger_src(&cmd->stop_src,
2142                                         TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2143 
2144         if (err)
2145                 return 1;
2146 
2147         /* Step 2a : make sure trigger sources are unique */
2148 
2149         err |= comedi_check_trigger_is_unique(cmd->start_src);
2150         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2151         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2152         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2153 
2154         /* Step 2b : and mutually compatible */
2155 
2156         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2157                 err |= -EINVAL;
2158 
2159         if (err)
2160                 return 2;
2161 
2162         /* Step 3: check if arguments are trivially valid */
2163 
2164         switch (cmd->start_src) {
2165         case TRIG_NOW:
2166                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2167                 break;
2168         case TRIG_EXT:
2169                 /*
2170                  * start_arg is the CR_CHAN | CR_INVERT of the
2171                  * external trigger.
2172                  */
2173                 break;
2174         }
2175 
2176         if (cmd->convert_src == TRIG_TIMER) {
2177                 if (board->layout == LAYOUT_4020) {
2178                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2179                                                            0);
2180                 } else {
2181                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2182                                                             board->ai_speed);
2183                         /*
2184                          * if scans are timed faster than conversion rate
2185                          * allows
2186                          */
2187                         if (cmd->scan_begin_src == TRIG_TIMER) {
2188                                 err |= comedi_check_trigger_arg_min(
2189                                                 &cmd->scan_begin_arg,
2190                                                 cmd->convert_arg *
2191                                                 cmd->chanlist_len);
2192                         }
2193                 }
2194         }
2195 
2196         err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1);
2197         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2198                                            cmd->chanlist_len);
2199 
2200         switch (cmd->stop_src) {
2201         case TRIG_EXT:
2202                 break;
2203         case TRIG_COUNT:
2204                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2205                 break;
2206         case TRIG_NONE:
2207                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2208                 break;
2209         default:
2210                 break;
2211         }
2212 
2213         if (err)
2214                 return 3;
2215 
2216         /* step 4: fix up any arguments */
2217 
2218         if (cmd->convert_src == TRIG_TIMER) {
2219                 tmp_arg = cmd->convert_arg;
2220                 tmp_arg2 = cmd->scan_begin_arg;
2221                 check_adc_timing(dev, cmd);
2222                 if (tmp_arg != cmd->convert_arg)
2223                         err++;
2224                 if (tmp_arg2 != cmd->scan_begin_arg)
2225                         err++;
2226         }
2227 
2228         if (err)
2229                 return 4;
2230 
2231         /* Step 5: check channel list if it exists */
2232         if (cmd->chanlist && cmd->chanlist_len > 0)
2233                 err |= cb_pcidas64_ai_check_chanlist(dev, s, cmd);
2234 
2235         if (err)
2236                 return 5;
2237 
2238         return 0;
2239 }
2240 
2241 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2242 {
2243 /* disable for now until I work out a race */
2244         return 0;
2245 
2246         if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2247                 return 1;
2248 
2249         return 0;
2250 }
2251 
2252 static void setup_sample_counters(struct comedi_device *dev,
2253                                   struct comedi_cmd *cmd)
2254 {
2255         struct pcidas64_private *devpriv = dev->private;
2256 
2257         /* load hardware conversion counter */
2258         if (use_hw_sample_counter(cmd)) {
2259                 writew(cmd->stop_arg & 0xffff,
2260                        devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2261                 writew((cmd->stop_arg >> 16) & 0xff,
2262                        devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2263         } else {
2264                 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2265         }
2266 }
2267 
2268 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2269 {
2270         const struct pcidas64_board *board = dev->board_ptr;
2271         struct pcidas64_private *devpriv = dev->private;
2272         unsigned int num_samples;
2273 
2274         num_samples = devpriv->ai_fifo_segment_length *
2275                       board->ai_fifo->sample_packing_ratio;
2276         if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2277                 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2278 
2279         return num_samples;
2280 }
2281 
2282 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2283                                         const struct comedi_cmd *cmd)
2284 {
2285         /* supposed to load counter with desired divisor minus 3 */
2286         return cmd->convert_arg / TIMER_BASE - 3;
2287 }
2288 
2289 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2290                                      struct comedi_cmd *cmd)
2291 {
2292         uint32_t count;
2293 
2294         /* figure out how long we need to delay at end of scan */
2295         switch (cmd->scan_begin_src) {
2296         case TRIG_TIMER:
2297                 count = (cmd->scan_begin_arg -
2298                          (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2299                         TIMER_BASE;
2300                 break;
2301         case TRIG_FOLLOW:
2302                 count = cmd->convert_arg / TIMER_BASE;
2303                 break;
2304         default:
2305                 return 0;
2306         }
2307         return count - 3;
2308 }
2309 
2310 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2311                                         struct comedi_cmd *cmd)
2312 {
2313         struct pcidas64_private *devpriv = dev->private;
2314         unsigned int divisor;
2315 
2316         switch (cmd->scan_begin_src) {
2317         case TRIG_TIMER:
2318                 divisor = cmd->scan_begin_arg / TIMER_BASE;
2319                 break;
2320         case TRIG_OTHER:
2321                 divisor = devpriv->ext_clock.divisor;
2322                 break;
2323         default:                /* should never happen */
2324                 dev_err(dev->class_dev, "bug! failed to set ai pacing!\n");
2325                 divisor = 1000;
2326                 break;
2327         }
2328 
2329         /* supposed to load counter with desired divisor minus 2 for 4020 */
2330         return divisor - 2;
2331 }
2332 
2333 static void select_master_clock_4020(struct comedi_device *dev,
2334                                      const struct comedi_cmd *cmd)
2335 {
2336         struct pcidas64_private *devpriv = dev->private;
2337 
2338         /* select internal/external master clock */
2339         devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2340         if (cmd->scan_begin_src == TRIG_OTHER) {
2341                 int chanspec = devpriv->ext_clock.chanspec;
2342 
2343                 if (CR_CHAN(chanspec))
2344                         devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2345                 else
2346                         devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2347         } else {
2348                 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2349         }
2350         writew(devpriv->hw_config_bits,
2351                devpriv->main_iobase + HW_CONFIG_REG);
2352 }
2353 
2354 static void select_master_clock(struct comedi_device *dev,
2355                                 const struct comedi_cmd *cmd)
2356 {
2357         const struct pcidas64_board *board = dev->board_ptr;
2358 
2359         switch (board->layout) {
2360         case LAYOUT_4020:
2361                 select_master_clock_4020(dev, cmd);
2362                 break;
2363         default:
2364                 break;
2365         }
2366 }
2367 
2368 static inline void dma_start_sync(struct comedi_device *dev,
2369                                   unsigned int channel)
2370 {
2371         struct pcidas64_private *devpriv = dev->private;
2372         unsigned long flags;
2373 
2374         /* spinlock for plx dma control/status reg */
2375         spin_lock_irqsave(&dev->spinlock, flags);
2376         writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_START | PLX_DMACSR_CLEARINTR,
2377                devpriv->plx9080_iobase + PLX_REG_DMACSR(channel));
2378         spin_unlock_irqrestore(&dev->spinlock, flags);
2379 }
2380 
2381 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2382 {
2383         const struct pcidas64_board *board = dev->board_ptr;
2384         struct pcidas64_private *devpriv = dev->private;
2385         uint32_t convert_counter = 0, scan_counter = 0;
2386 
2387         check_adc_timing(dev, cmd);
2388 
2389         select_master_clock(dev, cmd);
2390 
2391         if (board->layout == LAYOUT_4020) {
2392                 convert_counter = ai_convert_counter_4020(dev, cmd);
2393         } else {
2394                 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2395                 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2396         }
2397 
2398         /* load lower 16 bits of convert interval */
2399         writew(convert_counter & 0xffff,
2400                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2401         /* load upper 8 bits of convert interval */
2402         writew((convert_counter >> 16) & 0xff,
2403                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2404         /* load lower 16 bits of scan delay */
2405         writew(scan_counter & 0xffff,
2406                devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2407         /* load upper 8 bits of scan delay */
2408         writew((scan_counter >> 16) & 0xff,
2409                devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2410 }
2411 
2412 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2413 {
2414         int i;
2415 
2416         for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2417                 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2418                     CR_CHAN(cmd->chanlist[i]) + 1)
2419                         return 0;
2420                 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2421                     CR_RANGE(cmd->chanlist[i]))
2422                         return 0;
2423                 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2424                         return 0;
2425         }
2426         return 1;
2427 }
2428 
2429 static int setup_channel_queue(struct comedi_device *dev,
2430                                const struct comedi_cmd *cmd)
2431 {
2432         const struct pcidas64_board *board = dev->board_ptr;
2433         struct pcidas64_private *devpriv = dev->private;
2434         unsigned short bits;
2435         int i;
2436 
2437         if (board->layout != LAYOUT_4020) {
2438                 if (use_internal_queue_6xxx(cmd)) {
2439                         devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2440                         writew(devpriv->hw_config_bits,
2441                                devpriv->main_iobase + HW_CONFIG_REG);
2442                         bits = 0;
2443                         /* set channel */
2444                         bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2445                         /* set gain */
2446                         bits |= ai_range_bits_6xxx(dev,
2447                                                    CR_RANGE(cmd->chanlist[0]));
2448                         /* set single-ended / differential */
2449                         bits |= se_diff_bit_6xxx(dev,
2450                                                  CR_AREF(cmd->chanlist[0]) ==
2451                                                  AREF_DIFF);
2452                         if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2453                                 bits |= ADC_COMMON_BIT;
2454                         /* set stop channel */
2455                         writew(adc_chan_bits
2456                                (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2457                                devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2458                         /* set start channel, and rest of settings */
2459                         writew(bits,
2460                                devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2461                 } else {
2462                         /* use external queue */
2463                         if (dev->write_subdev && dev->write_subdev->busy) {
2464                                 warn_external_queue(dev);
2465                                 return -EBUSY;
2466                         }
2467                         devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2468                         writew(devpriv->hw_config_bits,
2469                                devpriv->main_iobase + HW_CONFIG_REG);
2470                         /* clear DAC buffer to prevent weird interactions */
2471                         writew(0,
2472                                devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2473                         /* clear queue pointer */
2474                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2475                         /* load external queue */
2476                         for (i = 0; i < cmd->chanlist_len; i++) {
2477                                 bits = 0;
2478                                 /* set channel */
2479                                 bits |= adc_chan_bits(CR_CHAN(cmd->
2480                                                               chanlist[i]));
2481                                 /* set gain */
2482                                 bits |= ai_range_bits_6xxx(dev,
2483                                                            CR_RANGE(cmd->
2484                                                                     chanlist
2485                                                                     [i]));
2486                                 /* set single-ended / differential */
2487                                 bits |= se_diff_bit_6xxx(dev,
2488                                                          CR_AREF(cmd->
2489                                                                  chanlist[i]) ==
2490                                                          AREF_DIFF);
2491                                 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2492                                         bits |= ADC_COMMON_BIT;
2493                                 /* mark end of queue */
2494                                 if (i == cmd->chanlist_len - 1)
2495                                         bits |= QUEUE_EOSCAN_BIT |
2496                                                 QUEUE_EOSEQ_BIT;
2497                                 writew(bits,
2498                                        devpriv->main_iobase +
2499                                        ADC_QUEUE_FIFO_REG);
2500                         }
2501                         /*
2502                          * doing a queue clear is not specified in board docs,
2503                          * but required for reliable operation
2504                          */
2505                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2506                         /* prime queue holding register */
2507                         writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2508                 }
2509         } else {
2510                 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2511 
2512                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2513                 /* select BNC inputs */
2514                 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2515                 /* select ranges */
2516                 for (i = 0; i < cmd->chanlist_len; i++) {
2517                         unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2518                         unsigned int range = CR_RANGE(cmd->chanlist[i]);
2519 
2520                         if (range == 0)
2521                                 devpriv->i2c_cal_range_bits |=
2522                                         attenuate_bit(channel);
2523                         else
2524                                 devpriv->i2c_cal_range_bits &=
2525                                         ~attenuate_bit(channel);
2526                 }
2527                 /*
2528                  * update calibration/range i2c register only if necessary,
2529                  * as it is very slow
2530                  */
2531                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2532                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2533 
2534                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2535                                   sizeof(i2c_data));
2536                 }
2537         }
2538         return 0;
2539 }
2540 
2541 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2542                                              unsigned int dma_channel,
2543                                              unsigned int descriptor_bits)
2544 {
2545         struct pcidas64_private *devpriv = dev->private;
2546 
2547         /*
2548          * The transfer size, pci address, and local address registers
2549          * are supposedly unused during chained dma,
2550          * but I have found that left over values from last operation
2551          * occasionally cause problems with transfer of first dma
2552          * block.  Initializing them to zero seems to fix the problem.
2553          */
2554         if (dma_channel) {
2555                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMASIZ1);
2556                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMAPADR1);
2557                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMALADR1);
2558                 writel(descriptor_bits,
2559                        devpriv->plx9080_iobase + PLX_REG_DMADPR1);
2560         } else {
2561                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMASIZ0);
2562                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMAPADR0);
2563                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMALADR0);
2564                 writel(descriptor_bits,
2565                        devpriv->plx9080_iobase + PLX_REG_DMADPR0);
2566         }
2567 }
2568 
2569 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2570 {
2571         const struct pcidas64_board *board = dev->board_ptr;
2572         struct pcidas64_private *devpriv = dev->private;
2573         struct comedi_async *async = s->async;
2574         struct comedi_cmd *cmd = &async->cmd;
2575         uint32_t bits;
2576         unsigned int i;
2577         unsigned long flags;
2578         int retval;
2579 
2580         disable_ai_pacing(dev);
2581         abort_dma(dev, 1);
2582 
2583         retval = setup_channel_queue(dev, cmd);
2584         if (retval < 0)
2585                 return retval;
2586 
2587         /* make sure internal calibration source is turned off */
2588         writew(0, devpriv->main_iobase + CALIBRATION_REG);
2589 
2590         set_ai_pacing(dev, cmd);
2591 
2592         setup_sample_counters(dev, cmd);
2593 
2594         enable_ai_interrupts(dev, cmd);
2595 
2596         spin_lock_irqsave(&dev->spinlock, flags);
2597         /* set mode, allow conversions through software gate */
2598         devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2599         devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2600         if (board->layout != LAYOUT_4020) {
2601                 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2602                 if (cmd->convert_src == TRIG_EXT)
2603                         /* good old mode 13 */
2604                         devpriv->adc_control1_bits |= adc_mode_bits(13);
2605                 else
2606                         /* mode 8.  What else could you need? */
2607                         devpriv->adc_control1_bits |= adc_mode_bits(8);
2608         } else {
2609                 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2610                 if (cmd->chanlist_len == 4)
2611                         devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2612                 else if (cmd->chanlist_len == 2)
2613                         devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2614                 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2615                 devpriv->adc_control1_bits |=
2616                         adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2617                 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2618                 devpriv->adc_control1_bits |=
2619                         adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2620                                                       [cmd->chanlist_len - 1]));
2621         }
2622         writew(devpriv->adc_control1_bits,
2623                devpriv->main_iobase + ADC_CONTROL1_REG);
2624         spin_unlock_irqrestore(&dev->spinlock, flags);
2625 
2626         /* clear adc buffer */
2627         writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2628 
2629         if ((cmd->flags & CMDF_WAKE_EOS) == 0 ||
2630             board->layout == LAYOUT_4020) {
2631                 devpriv->ai_dma_index = 0;
2632 
2633                 /* set dma transfer size */
2634                 for (i = 0; i < ai_dma_ring_count(board); i++)
2635                         devpriv->ai_dma_desc[i].transfer_size =
2636                                 cpu_to_le32(dma_transfer_size(dev) *
2637                                             sizeof(uint16_t));
2638 
2639                 /* give location of first dma descriptor */
2640                 load_first_dma_descriptor(dev, 1,
2641                                           devpriv->ai_dma_desc_bus_addr |
2642                                           PLX_DMADPR_DESCPCI |
2643                                           PLX_DMADPR_TCINTR |
2644                                           PLX_DMADPR_XFERL2P);
2645 
2646                 dma_start_sync(dev, 1);
2647         }
2648 
2649         if (board->layout == LAYOUT_4020) {
2650                 /* set source for external triggers */
2651                 bits = 0;
2652                 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2653                         bits |= EXT_START_TRIG_BNC_BIT;
2654                 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2655                         bits |= EXT_STOP_TRIG_BNC_BIT;
2656                 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2657         }
2658 
2659         spin_lock_irqsave(&dev->spinlock, flags);
2660 
2661         /* enable pacing, triggering, etc */
2662         bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2663         if (cmd->flags & CMDF_WAKE_EOS)
2664                 bits |= ADC_DMA_DISABLE_BIT;
2665         /* set start trigger */
2666         if (cmd->start_src == TRIG_EXT) {
2667                 bits |= ADC_START_TRIG_EXT_BITS;
2668                 if (cmd->start_arg & CR_INVERT)
2669                         bits |= ADC_START_TRIG_FALLING_BIT;
2670         } else if (cmd->start_src == TRIG_NOW) {
2671                 bits |= ADC_START_TRIG_SOFT_BITS;
2672         }
2673         if (use_hw_sample_counter(cmd))
2674                 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2675         writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2676 
2677         devpriv->ai_cmd_running = 1;
2678 
2679         spin_unlock_irqrestore(&dev->spinlock, flags);
2680 
2681         /* start acquisition */
2682         if (cmd->start_src == TRIG_NOW)
2683                 writew(0, devpriv->main_iobase + ADC_START_REG);
2684 
2685         return 0;
2686 }
2687 
2688 /* read num_samples from 16 bit wide ai fifo */
2689 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2690 {
2691         struct pcidas64_private *devpriv = dev->private;
2692         struct comedi_subdevice *s = dev->read_subdev;
2693         unsigned int i;
2694         uint16_t prepost_bits;
2695         int read_segment, read_index, write_segment, write_index;
2696         int num_samples;
2697 
2698         do {
2699                 /* get least significant 15 bits */
2700                 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2701                              0x7fff;
2702                 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2703                               0x7fff;
2704                 /*
2705                  * Get most significant bits (grey code).
2706                  * Different boards use different code so use a scheme
2707                  * that doesn't depend on encoding.  This read must
2708                  * occur after reading least significant 15 bits to avoid race
2709                  * with fifo switching to next segment.
2710                  */
2711                 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2712 
2713                 /*
2714                  * if read and write pointers are not on the same fifo segment,
2715                  * read to the end of the read segment
2716                  */
2717                 read_segment = adc_upper_read_ptr_code(prepost_bits);
2718                 write_segment = adc_upper_write_ptr_code(prepost_bits);
2719 
2720                 if (read_segment != write_segment)
2721                         num_samples =
2722                                 devpriv->ai_fifo_segment_length - read_index;
2723                 else
2724                         num_samples = write_index - read_index;
2725                 if (num_samples < 0) {
2726                         dev_err(dev->class_dev,
2727                                 "cb_pcidas64: bug! num_samples < 0\n");
2728                         break;
2729                 }
2730 
2731                 num_samples = comedi_nsamples_left(s, num_samples);
2732                 if (num_samples == 0)
2733                         break;
2734 
2735                 for (i = 0; i < num_samples; i++) {
2736                         unsigned short val;
2737 
2738                         val = readw(devpriv->main_iobase + ADC_FIFO_REG);
2739                         comedi_buf_write_samples(s, &val, 1);
2740                 }
2741 
2742         } while (read_segment != write_segment);
2743 }
2744 
2745 /*
2746  * Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2747  * pointers.  The pci-4020 hardware only supports dma transfers (it only
2748  * supports the use of pio for draining the last remaining points from the
2749  * fifo when a data acquisition operation has completed).
2750  */
2751 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2752 {
2753         struct pcidas64_private *devpriv = dev->private;
2754         struct comedi_subdevice *s = dev->read_subdev;
2755         unsigned int nsamples;
2756         unsigned int i;
2757         uint32_t fifo_data;
2758         int write_code =
2759                 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2760         int read_code =
2761                 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2762 
2763         nsamples = comedi_nsamples_left(s, 100000);
2764         for (i = 0; read_code != write_code && i < nsamples;) {
2765                 unsigned short val;
2766 
2767                 fifo_data = readl(dev->mmio + ADC_FIFO_REG);
2768                 val = fifo_data & 0xffff;
2769                 comedi_buf_write_samples(s, &val, 1);
2770                 i++;
2771                 if (i < nsamples) {
2772                         val = (fifo_data >> 16) & 0xffff;
2773                         comedi_buf_write_samples(s, &val, 1);
2774                         i++;
2775                 }
2776                 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2777                             0x7fff;
2778         }
2779 }
2780 
2781 /* empty fifo */
2782 static void pio_drain_ai_fifo(struct comedi_device *dev)
2783 {
2784         const struct pcidas64_board *board = dev->board_ptr;
2785 
2786         if (board->layout == LAYOUT_4020)
2787                 pio_drain_ai_fifo_32(dev);
2788         else
2789                 pio_drain_ai_fifo_16(dev);
2790 }
2791 
2792 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2793 {
2794         const struct pcidas64_board *board = dev->board_ptr;
2795         struct pcidas64_private *devpriv = dev->private;
2796         struct comedi_subdevice *s = dev->read_subdev;
2797         uint32_t next_transfer_addr;
2798         int j;
2799         int num_samples = 0;
2800         void __iomem *pci_addr_reg;
2801 
2802         pci_addr_reg = devpriv->plx9080_iobase + PLX_REG_DMAPADR(channel);
2803 
2804         /* loop until we have read all the full buffers */
2805         for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2806              (next_transfer_addr <
2807               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2808               next_transfer_addr >=
2809               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2810               DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board); j++) {
2811                 /* transfer data from dma buffer to comedi buffer */
2812                 num_samples = comedi_nsamples_left(s, dma_transfer_size(dev));
2813                 comedi_buf_write_samples(s,
2814                                 devpriv->ai_buffer[devpriv->ai_dma_index],
2815                                 num_samples);
2816                 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2817                                         ai_dma_ring_count(board);
2818         }
2819         /*
2820          * XXX check for dma ring buffer overrun
2821          * (use end-of-chain bit to mark last unused buffer)
2822          */
2823 }
2824 
2825 static void handle_ai_interrupt(struct comedi_device *dev,
2826                                 unsigned short status,
2827                                 unsigned int plx_status)
2828 {
2829         const struct pcidas64_board *board = dev->board_ptr;
2830         struct pcidas64_private *devpriv = dev->private;
2831         struct comedi_subdevice *s = dev->read_subdev;
2832         struct comedi_async *async = s->async;
2833         struct comedi_cmd *cmd = &async->cmd;
2834         uint8_t dma1_status;
2835         unsigned long flags;
2836 
2837         /* check for fifo overrun */
2838         if (status & ADC_OVERRUN_BIT) {
2839                 dev_err(dev->class_dev, "fifo overrun\n");
2840                 async->events |= COMEDI_CB_ERROR;
2841         }
2842         /* spin lock makes sure no one else changes plx dma control reg */
2843         spin_lock_irqsave(&dev->spinlock, flags);
2844         dma1_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR1);
2845         if (plx_status & PLX_INTCSR_DMA1IA) {   /* dma chan 1 interrupt */
2846                 writeb((dma1_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR,
2847                        devpriv->plx9080_iobase + PLX_REG_DMACSR1);
2848 
2849                 if (dma1_status & PLX_DMACSR_ENABLE)
2850                         drain_dma_buffers(dev, 1);
2851         }
2852         spin_unlock_irqrestore(&dev->spinlock, flags);
2853 
2854         /* drain fifo with pio */
2855         if ((status & ADC_DONE_BIT) ||
2856             ((cmd->flags & CMDF_WAKE_EOS) &&
2857              (status & ADC_INTR_PENDING_BIT) &&
2858              (board->layout != LAYOUT_4020))) {
2859                 spin_lock_irqsave(&dev->spinlock, flags);
2860                 if (devpriv->ai_cmd_running) {
2861                         spin_unlock_irqrestore(&dev->spinlock, flags);
2862                         pio_drain_ai_fifo(dev);
2863                 } else {
2864                         spin_unlock_irqrestore(&dev->spinlock, flags);
2865                 }
2866         }
2867         /* if we are have all the data, then quit */
2868         if ((cmd->stop_src == TRIG_COUNT &&
2869              async->scans_done >= cmd->stop_arg) ||
2870             (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT)))
2871                 async->events |= COMEDI_CB_EOA;
2872 
2873         comedi_handle_events(dev, s);
2874 }
2875 
2876 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2877 {
2878         struct pcidas64_private *devpriv = dev->private;
2879         unsigned int buffer_index;
2880 
2881         if (devpriv->ao_dma_index == 0)
2882                 buffer_index = AO_DMA_RING_COUNT - 1;
2883         else
2884                 buffer_index = devpriv->ao_dma_index - 1;
2885         return buffer_index;
2886 }
2887 
2888 static int last_ao_dma_load_completed(struct comedi_device *dev)
2889 {
2890         struct pcidas64_private *devpriv = dev->private;
2891         unsigned int buffer_index;
2892         unsigned int transfer_address;
2893         unsigned short dma_status;
2894 
2895         buffer_index = prev_ao_dma_index(dev);
2896         dma_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
2897         if ((dma_status & PLX_DMACSR_DONE) == 0)
2898                 return 0;
2899 
2900         transfer_address =
2901                 readl(devpriv->plx9080_iobase + PLX_REG_DMAPADR0);
2902         if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2903                 return 0;
2904 
2905         return 1;
2906 }
2907 
2908 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2909                                        unsigned short dma_status)
2910 {
2911         if ((dma_status & PLX_DMACSR_DONE) == 0 ||
2912             (dma_status & PLX_DMACSR_ENABLE) == 0)
2913                 return 0;
2914         if (last_ao_dma_load_completed(dev))
2915                 return 0;
2916 
2917         return 1;
2918 }
2919 
2920 static void restart_ao_dma(struct comedi_device *dev)
2921 {
2922         struct pcidas64_private *devpriv = dev->private;
2923         unsigned int dma_desc_bits;
2924 
2925         dma_desc_bits = readl(devpriv->plx9080_iobase + PLX_REG_DMADPR0);
2926         dma_desc_bits &= ~PLX_DMADPR_CHAINEND;
2927         load_first_dma_descriptor(dev, 0, dma_desc_bits);
2928 
2929         dma_start_sync(dev, 0);
2930 }
2931 
2932 static unsigned int cb_pcidas64_ao_fill_buffer(struct comedi_device *dev,
2933                                                struct comedi_subdevice *s,
2934                                                unsigned short *dest,
2935                                                unsigned int max_bytes)
2936 {
2937         unsigned int nsamples = comedi_bytes_to_samples(s, max_bytes);
2938         unsigned int actual_bytes;
2939 
2940         nsamples = comedi_nsamples_left(s, nsamples);
2941         actual_bytes = comedi_buf_read_samples(s, dest, nsamples);
2942 
2943         return comedi_bytes_to_samples(s, actual_bytes);
2944 }
2945 
2946 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2947                                        const struct comedi_cmd *cmd)
2948 {
2949         struct pcidas64_private *devpriv = dev->private;
2950         struct comedi_subdevice *s = dev->write_subdev;
2951         unsigned int buffer_index = devpriv->ao_dma_index;
2952         unsigned int prev_buffer_index = prev_ao_dma_index(dev);
2953         unsigned int nsamples;
2954         unsigned int nbytes;
2955         unsigned int next_bits;
2956 
2957         nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
2958                                               devpriv->ao_buffer[buffer_index],
2959                                               DMA_BUFFER_SIZE);
2960         if (nsamples == 0)
2961                 return 0;
2962 
2963         nbytes = comedi_samples_to_bytes(s, nsamples);
2964         devpriv->ao_dma_desc[buffer_index].transfer_size = cpu_to_le32(nbytes);
2965         /* set end of chain bit so we catch underruns */
2966         next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
2967         next_bits |= PLX_DMADPR_CHAINEND;
2968         devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
2969         /*
2970          * clear end of chain bit on previous buffer now that we have set it
2971          * for the last buffer
2972          */
2973         next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
2974         next_bits &= ~PLX_DMADPR_CHAINEND;
2975         devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
2976 
2977         devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
2978 
2979         return nbytes;
2980 }
2981 
2982 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
2983 {
2984         struct pcidas64_private *devpriv = dev->private;
2985         unsigned int num_bytes;
2986         unsigned int next_transfer_addr;
2987         void __iomem *pci_addr_reg = devpriv->plx9080_iobase + PLX_REG_DMAPADR0;
2988         unsigned int buffer_index;
2989 
2990         do {
2991                 buffer_index = devpriv->ao_dma_index;
2992                 /* don't overwrite data that hasn't been transferred yet */
2993                 next_transfer_addr = readl(pci_addr_reg);
2994                 if (next_transfer_addr >=
2995                     devpriv->ao_buffer_bus_addr[buffer_index] &&
2996                     next_transfer_addr <
2997                     devpriv->ao_buffer_bus_addr[buffer_index] +
2998                     DMA_BUFFER_SIZE)
2999                         return;
3000                 num_bytes = load_ao_dma_buffer(dev, cmd);
3001         } while (num_bytes >= DMA_BUFFER_SIZE);
3002 }
3003 
3004 static void handle_ao_interrupt(struct comedi_device *dev,
3005                                 unsigned short status, unsigned int plx_status)
3006 {
3007         struct pcidas64_private *devpriv = dev->private;
3008         struct comedi_subdevice *s = dev->write_subdev;
3009         struct comedi_async *async;
3010         struct comedi_cmd *cmd;
3011         uint8_t dma0_status;
3012         unsigned long flags;
3013 
3014         /* board might not support ao, in which case write_subdev is NULL */
3015         if (!s)
3016                 return;
3017         async = s->async;
3018         cmd = &async->cmd;
3019 
3020         /* spin lock makes sure no one else changes plx dma control reg */
3021         spin_lock_irqsave(&dev->spinlock, flags);
3022         dma0_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
3023         if (plx_status & PLX_INTCSR_DMA0IA) {   /*  dma chan 0 interrupt */
3024                 if ((dma0_status & PLX_DMACSR_ENABLE) &&
3025                     !(dma0_status & PLX_DMACSR_DONE)) {
3026                         writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_CLEARINTR,
3027                                devpriv->plx9080_iobase + PLX_REG_DMACSR0);
3028                 } else {
3029                         writeb(PLX_DMACSR_CLEARINTR,
3030                                devpriv->plx9080_iobase + PLX_REG_DMACSR0);
3031                 }
3032                 spin_unlock_irqrestore(&dev->spinlock, flags);
3033                 if (dma0_status & PLX_DMACSR_ENABLE) {
3034                         load_ao_dma(dev, cmd);
3035                         /* try to recover from dma end-of-chain event */
3036                         if (ao_dma_needs_restart(dev, dma0_status))
3037                                 restart_ao_dma(dev);
3038                 }
3039         } else {
3040                 spin_unlock_irqrestore(&dev->spinlock, flags);
3041         }
3042 
3043         if ((status & DAC_DONE_BIT)) {
3044                 if ((cmd->stop_src == TRIG_COUNT &&
3045                      async->scans_done >= cmd->stop_arg) ||
3046                     last_ao_dma_load_completed(dev))
3047                         async->events |= COMEDI_CB_EOA;
3048                 else
3049                         async->events |= COMEDI_CB_ERROR;
3050         }
3051         comedi_handle_events(dev, s);
3052 }
3053 
3054 static irqreturn_t handle_interrupt(int irq, void *d)
3055 {
3056         struct comedi_device *dev = d;
3057         struct pcidas64_private *devpriv = dev->private;
3058         unsigned short status;
3059         uint32_t plx_status;
3060         uint32_t plx_bits;
3061 
3062         plx_status = readl(devpriv->plx9080_iobase + PLX_REG_INTCSR);
3063         status = readw(devpriv->main_iobase + HW_STATUS_REG);
3064 
3065         /*
3066          * an interrupt before all the postconfig stuff gets done could
3067          * cause a NULL dereference if we continue through the
3068          * interrupt handler
3069          */
3070         if (!dev->attached)
3071                 return IRQ_HANDLED;
3072 
3073         handle_ai_interrupt(dev, status, plx_status);
3074         handle_ao_interrupt(dev, status, plx_status);
3075 
3076         /* clear possible plx9080 interrupt sources */
3077         if (plx_status & PLX_INTCSR_LDBIA) {
3078                 /* clear local doorbell interrupt */
3079                 plx_bits = readl(devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
3080                 writel(plx_bits, devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
3081         }
3082 
3083         return IRQ_HANDLED;
3084 }
3085 
3086 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3087 {
3088         struct pcidas64_private *devpriv = dev->private;
3089         unsigned long flags;
3090 
3091         spin_lock_irqsave(&dev->spinlock, flags);
3092         if (devpriv->ai_cmd_running == 0) {
3093                 spin_unlock_irqrestore(&dev->spinlock, flags);
3094                 return 0;
3095         }
3096         devpriv->ai_cmd_running = 0;
3097         spin_unlock_irqrestore(&dev->spinlock, flags);
3098 
3099         disable_ai_pacing(dev);
3100 
3101         abort_dma(dev, 1);
3102 
3103         return 0;
3104 }
3105 
3106 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3107                     struct comedi_insn *insn, unsigned int *data)
3108 {
3109         const struct pcidas64_board *board = dev->board_ptr;
3110         struct pcidas64_private *devpriv = dev->private;
3111         int chan = CR_CHAN(insn->chanspec);
3112         int range = CR_RANGE(insn->chanspec);
3113 
3114         /* do some initializing */
3115         writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3116 
3117         /* set range */
3118         set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3119         writew(devpriv->dac_control1_bits,
3120                devpriv->main_iobase + DAC_CONTROL1_REG);
3121 
3122         /* write to channel */
3123         if (board->layout == LAYOUT_4020) {
3124                 writew(data[0] & 0xff,
3125                        devpriv->main_iobase + dac_lsb_4020_reg(chan));
3126                 writew((data[0] >> 8) & 0xf,
3127                        devpriv->main_iobase + dac_msb_4020_reg(chan));
3128         } else {
3129                 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3130         }
3131 
3132         /* remember output value */
3133         s->readback[chan] = data[0];
3134 
3135         return 1;
3136 }
3137 
3138 static void set_dac_control0_reg(struct comedi_device *dev,
3139                                  const struct comedi_cmd *cmd)
3140 {
3141         struct pcidas64_private *devpriv = dev->private;
3142         unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3143                             WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3144 
3145         if (cmd->start_src == TRIG_EXT) {
3146                 bits |= WAVEFORM_TRIG_EXT_BITS;
3147                 if (cmd->start_arg & CR_INVERT)
3148                         bits |= WAVEFORM_TRIG_FALLING_BIT;
3149         } else {
3150                 bits |= WAVEFORM_TRIG_SOFT_BITS;
3151         }
3152         if (cmd->scan_begin_src == TRIG_EXT) {
3153                 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3154                 if (cmd->scan_begin_arg & CR_INVERT)
3155                         bits |= DAC_EXT_UPDATE_FALLING_BIT;
3156         }
3157         writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3158 }
3159 
3160 static void set_dac_control1_reg(struct comedi_device *dev,
3161                                  const struct comedi_cmd *cmd)
3162 {
3163         struct pcidas64_private *devpriv = dev->private;
3164         int i;
3165 
3166         for (i = 0; i < cmd->chanlist_len; i++) {
3167                 int channel, range;
3168 
3169                 channel = CR_CHAN(cmd->chanlist[i]);
3170                 range = CR_RANGE(cmd->chanlist[i]);
3171                 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3172                                    range);
3173         }
3174         devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3175         writew(devpriv->dac_control1_bits,
3176                devpriv->main_iobase + DAC_CONTROL1_REG);
3177 }
3178 
3179 static void set_dac_select_reg(struct comedi_device *dev,
3180                                const struct comedi_cmd *cmd)
3181 {
3182         struct pcidas64_private *devpriv = dev->private;
3183         uint16_t bits;
3184         unsigned int first_channel, last_channel;
3185 
3186         first_channel = CR_CHAN(cmd->chanlist[0]);
3187         last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3188         if (last_channel < first_channel)
3189                 dev_err(dev->class_dev,
3190                         "bug! last ao channel < first ao channel\n");
3191 
3192         bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3193 
3194         writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3195 }
3196 
3197 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3198 {
3199         return get_divisor(ns, flags) - 2;
3200 }
3201 
3202 static void set_dac_interval_regs(struct comedi_device *dev,
3203                                   const struct comedi_cmd *cmd)
3204 {
3205         struct pcidas64_private *devpriv = dev->private;
3206         unsigned int divisor;
3207 
3208         if (cmd->scan_begin_src != TRIG_TIMER)
3209                 return;
3210 
3211         divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3212         if (divisor > max_counter_value) {
3213                 dev_err(dev->class_dev, "bug! ao divisor too big\n");
3214                 divisor = max_counter_value;
3215         }
3216         writew(divisor & 0xffff,
3217                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3218         writew((divisor >> 16) & 0xff,
3219                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3220 }
3221 
3222 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3223 {
3224         struct pcidas64_private *devpriv = dev->private;
3225         struct comedi_subdevice *s = dev->write_subdev;
3226         unsigned int nsamples;
3227         unsigned int nbytes;
3228         int i;
3229 
3230         /*
3231          * clear queue pointer too, since external queue has
3232          * weird interactions with ao fifo
3233          */
3234         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3235         writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3236 
3237         nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
3238                                               devpriv->ao_bounce_buffer,
3239                                               DAC_FIFO_SIZE);
3240         if (nsamples == 0)
3241                 return -1;
3242 
3243         for (i = 0; i < nsamples; i++) {
3244                 writew(devpriv->ao_bounce_buffer[i],
3245                        devpriv->main_iobase + DAC_FIFO_REG);
3246         }
3247 
3248         if (cmd->stop_src == TRIG_COUNT &&
3249             s->async->scans_done >= cmd->stop_arg)
3250                 return 0;
3251 
3252         nbytes = load_ao_dma_buffer(dev, cmd);
3253         if (nbytes == 0)
3254                 return -1;
3255         load_ao_dma(dev, cmd);
3256 
3257         dma_start_sync(dev, 0);
3258 
3259         return 0;
3260 }
3261 
3262 static inline int external_ai_queue_in_use(struct comedi_device *dev,
3263                                            struct comedi_subdevice *s,
3264                                            struct comedi_cmd *cmd)
3265 {
3266         const struct pcidas64_board *board = dev->board_ptr;
3267 
3268         if (s->busy)
3269                 return 0;
3270         if (board->layout == LAYOUT_4020)
3271                 return 0;
3272         else if (use_internal_queue_6xxx(cmd))
3273                 return 0;
3274         return 1;
3275 }
3276 
3277 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3278                       unsigned int trig_num)
3279 {
3280         struct pcidas64_private *devpriv = dev->private;
3281         struct comedi_cmd *cmd = &s->async->cmd;
3282         int retval;
3283 
3284         if (trig_num != cmd->start_arg)
3285                 return -EINVAL;
3286 
3287         retval = prep_ao_dma(dev, cmd);
3288         if (retval < 0)
3289                 return -EPIPE;
3290 
3291         set_dac_control0_reg(dev, cmd);
3292 
3293         if (cmd->start_src == TRIG_INT)
3294                 writew(0, devpriv->main_iobase + DAC_START_REG);
3295 
3296         s->async->inttrig = NULL;
3297 
3298         return 0;
3299 }
3300 
3301 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3302 {
3303         struct pcidas64_private *devpriv = dev->private;
3304         struct comedi_cmd *cmd = &s->async->cmd;
3305 
3306         if (external_ai_queue_in_use(dev, s, cmd)) {
3307                 warn_external_queue(dev);
3308                 return -EBUSY;
3309         }
3310         /* disable analog output system during setup */
3311         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3312 
3313         devpriv->ao_dma_index = 0;
3314 
3315         set_dac_select_reg(dev, cmd);
3316         set_dac_interval_regs(dev, cmd);
3317         load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3318                                   PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR);
3319 
3320         set_dac_control1_reg(dev, cmd);
3321         s->async->inttrig = ao_inttrig;
3322 
3323         return 0;
3324 }
3325 
3326 static int cb_pcidas64_ao_check_chanlist(struct comedi_device *dev,
3327                                          struct comedi_subdevice *s,
3328                                          struct comedi_cmd *cmd)
3329 {
3330         unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
3331         int i;
3332 
3333         for (i = 1; i < cmd->chanlist_len; i++) {
3334                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3335 
3336                 if (chan != (chan0 + i)) {
3337                         dev_dbg(dev->class_dev,
3338                                 "chanlist must use consecutive channels\n");
3339                         return -EINVAL;
3340                 }
3341         }
3342 
3343         return 0;
3344 }
3345 
3346 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3347                       struct comedi_cmd *cmd)
3348 {
3349         const struct pcidas64_board *board = dev->board_ptr;
3350         int err = 0;
3351         unsigned int tmp_arg;
3352 
3353         /* Step 1 : check if triggers are trivially valid */
3354 
3355         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3356         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3357                                         TRIG_TIMER | TRIG_EXT);
3358         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3359         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3360         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3361 
3362         if (err)
3363                 return 1;
3364 
3365         /* Step 2a : make sure trigger sources are unique */
3366 
3367         err |= comedi_check_trigger_is_unique(cmd->start_src);
3368         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3369 
3370         /* Step 2b : and mutually compatible */
3371 
3372         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3373                 err |= -EINVAL;
3374         if (cmd->stop_src != TRIG_COUNT &&
3375             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3376                 err |= -EINVAL;
3377 
3378         if (err)
3379                 return 2;
3380 
3381         /* Step 3: check if arguments are trivially valid */
3382 
3383         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3384 
3385         if (cmd->scan_begin_src == TRIG_TIMER) {
3386                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3387                                                     board->ao_scan_speed);
3388                 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3389                     max_counter_value) {
3390                         cmd->scan_begin_arg = (max_counter_value + 2) *
3391                                               TIMER_BASE;
3392                         err |= -EINVAL;
3393                 }
3394         }
3395 
3396         err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1);
3397         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3398                                            cmd->chanlist_len);
3399 
3400         if (err)
3401                 return 3;
3402 
3403         /* step 4: fix up any arguments */
3404 
3405         if (cmd->scan_begin_src == TRIG_TIMER) {
3406                 tmp_arg = cmd->scan_begin_arg;
3407                 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3408                                                   cmd->flags) * TIMER_BASE;
3409                 if (tmp_arg != cmd->scan_begin_arg)
3410                         err++;
3411         }
3412 
3413         if (err)
3414                 return 4;
3415 
3416         /* Step 5: check channel list if it exists */
3417         if (cmd->chanlist && cmd->chanlist_len > 0)
3418                 err |= cb_pcidas64_ao_check_chanlist(dev, s, cmd);
3419 
3420         if (err)
3421                 return 5;
3422 
3423         return 0;
3424 }
3425 
3426 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3427 {
3428         struct pcidas64_private *devpriv = dev->private;
3429 
3430         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3431         abort_dma(dev, 0);
3432         return 0;
3433 }
3434 
3435 static int dio_callback_4020(struct comedi_device *dev,
3436                              int dir, int port, int data, unsigned long iobase)
3437 {
3438         struct pcidas64_private *devpriv = dev->private;
3439 
3440         if (dir) {
3441                 writew(data, devpriv->main_iobase + iobase + 2 * port);
3442                 return 0;
3443         }
3444         return readw(devpriv->main_iobase + iobase + 2 * port);
3445 }
3446 
3447 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3448                     struct comedi_insn *insn, unsigned int *data)
3449 {
3450         unsigned int bits;
3451 
3452         bits = readb(dev->mmio + DI_REG);
3453         bits &= 0xf;
3454         data[1] = bits;
3455         data[0] = 0;
3456 
3457         return insn->n;
3458 }
3459 
3460 static int do_wbits(struct comedi_device *dev,
3461                     struct comedi_subdevice *s,
3462                     struct comedi_insn *insn,
3463                     unsigned int *data)
3464 {
3465         if (comedi_dio_update_state(s, data))
3466                 writeb(s->state, dev->mmio + DO_REG);
3467 
3468         data[1] = s->state;
3469 
3470         return insn->n;
3471 }
3472 
3473 static int dio_60xx_config_insn(struct comedi_device *dev,
3474                                 struct comedi_subdevice *s,
3475                                 struct comedi_insn *insn,
3476                                 unsigned int *data)
3477 {
3478         int ret;
3479 
3480         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3481         if (ret)
3482                 return ret;
3483 
3484         writeb(s->io_bits, dev->mmio + DIO_DIRECTION_60XX_REG);
3485 
3486         return insn->n;
3487 }
3488 
3489 static int dio_60xx_wbits(struct comedi_device *dev,
3490                           struct comedi_subdevice *s,
3491                           struct comedi_insn *insn,
3492                           unsigned int *data)
3493 {
3494         if (comedi_dio_update_state(s, data))
3495                 writeb(s->state, dev->mmio + DIO_DATA_60XX_REG);
3496 
3497         data[1] = readb(dev->mmio + DIO_DATA_60XX_REG);
3498 
3499         return insn->n;
3500 }
3501 
3502 /*
3503  * pci-6025 8800 caldac:
3504  * address 0 == dac channel 0 offset
3505  * address 1 == dac channel 0 gain
3506  * address 2 == dac channel 1 offset
3507  * address 3 == dac channel 1 gain
3508  * address 4 == fine adc offset
3509  * address 5 == coarse adc offset
3510  * address 6 == coarse adc gain
3511  * address 7 == fine adc gain
3512  */
3513 /*
3514  * pci-6402/16 uses all 8 channels for dac:
3515  * address 0 == dac channel 0 fine gain
3516  * address 1 == dac channel 0 coarse gain
3517  * address 2 == dac channel 0 coarse offset
3518  * address 3 == dac channel 1 coarse offset
3519  * address 4 == dac channel 1 fine gain
3520  * address 5 == dac channel 1 coarse gain
3521  * address 6 == dac channel 0 fine offset
3522  * address 7 == dac channel 1 fine offset
3523  */
3524 
3525 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3526                              uint8_t value)
3527 {
3528         struct pcidas64_private *devpriv = dev->private;
3529         static const int num_caldac_channels = 8;
3530         static const int bitstream_length = 11;
3531         unsigned int bitstream = ((address & 0x7) << 8) | value;
3532         unsigned int bit, register_bits;
3533         static const int caldac_8800_udelay = 1;
3534 
3535         if (address >= num_caldac_channels) {
3536                 dev_err(dev->class_dev, "illegal caldac channel\n");
3537                 return -1;
3538         }
3539         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3540                 register_bits = 0;
3541                 if (bitstream & bit)
3542                         register_bits |= SERIAL_DATA_IN_BIT;
3543                 udelay(caldac_8800_udelay);
3544                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3545                 register_bits |= SERIAL_CLOCK_BIT;
3546                 udelay(caldac_8800_udelay);
3547                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3548         }
3549         udelay(caldac_8800_udelay);
3550         writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3551         udelay(caldac_8800_udelay);
3552         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3553         udelay(caldac_8800_udelay);
3554         return 0;
3555 }
3556 
3557 /* 4020 caldacs */
3558 static int caldac_i2c_write(struct comedi_device *dev,
3559                             unsigned int caldac_channel, unsigned int value)
3560 {
3561         uint8_t serial_bytes[3];
3562         uint8_t i2c_addr;
3563         enum pointer_bits {
3564                 /* manual has gain and offset bits switched */
3565                 OFFSET_0_2 = 0x1,
3566                 GAIN_0_2 = 0x2,
3567                 OFFSET_1_3 = 0x4,
3568                 GAIN_1_3 = 0x8,
3569         };
3570         enum data_bits {
3571                 NOT_CLEAR_REGISTERS = 0x20,
3572         };
3573 
3574         switch (caldac_channel) {
3575         case 0:                                 /* chan 0 offset */
3576                 i2c_addr = CALDAC0_I2C_ADDR;
3577                 serial_bytes[0] = OFFSET_0_2;
3578                 break;
3579         case 1:                                 /* chan 1 offset */
3580                 i2c_addr = CALDAC0_I2C_ADDR;
3581                 serial_bytes[0] = OFFSET_1_3;
3582                 break;
3583         case 2:                                 /* chan 2 offset */
3584                 i2c_addr = CALDAC1_I2C_ADDR;
3585                 serial_bytes[0] = OFFSET_0_2;
3586                 break;
3587         case 3:                                 /* chan 3 offset */
3588                 i2c_addr = CALDAC1_I2C_ADDR;
3589                 serial_bytes[0] = OFFSET_1_3;
3590                 break;
3591         case 4:                                 /* chan 0 gain */
3592                 i2c_addr = CALDAC0_I2C_ADDR;
3593                 serial_bytes[0] = GAIN_0_2;
3594                 break;
3595         case 5:                                 /* chan 1 gain */
3596                 i2c_addr = CALDAC0_I2C_ADDR;
3597                 serial_bytes[0] = GAIN_1_3;
3598                 break;
3599         case 6:                                 /* chan 2 gain */
3600                 i2c_addr = CALDAC1_I2C_ADDR;
3601                 serial_bytes[0] = GAIN_0_2;
3602                 break;
3603         case 7:                                 /* chan 3 gain */
3604                 i2c_addr = CALDAC1_I2C_ADDR;
3605                 serial_bytes[0] = GAIN_1_3;
3606                 break;
3607         default:
3608                 dev_err(dev->class_dev, "invalid caldac channel\n");
3609                 return -1;
3610         }
3611         serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3612         serial_bytes[2] = value & 0xff;
3613         i2c_write(dev, i2c_addr, serial_bytes, 3);
3614         return 0;
3615 }
3616 
3617 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3618                          unsigned int value)
3619 {
3620         const struct pcidas64_board *board = dev->board_ptr;
3621 
3622         switch (board->layout) {
3623         case LAYOUT_60XX:
3624         case LAYOUT_64XX:
3625                 caldac_8800_write(dev, channel, value);
3626                 break;
3627         case LAYOUT_4020:
3628                 caldac_i2c_write(dev, channel, value);
3629                 break;
3630         default:
3631                 break;
3632         }
3633 }
3634 
3635 static int cb_pcidas64_calib_insn_write(struct comedi_device *dev,
3636                                         struct comedi_subdevice *s,
3637                                         struct comedi_insn *insn,
3638                                         unsigned int *data)
3639 {
3640         unsigned int chan = CR_CHAN(insn->chanspec);
3641 
3642         /*
3643          * Programming the calib device is slow. Only write the
3644          * last data value if the value has changed.
3645          */
3646         if (insn->n) {
3647                 unsigned int val = data[insn->n - 1];
3648 
3649                 if (s->readback[chan] != val) {
3650                         caldac_write(dev, chan, val);
3651                         s->readback[chan] = val;
3652                 }
3653         }
3654 
3655         return insn->n;
3656 }
3657 
3658 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3659                          unsigned int value)
3660 {
3661         struct pcidas64_private *devpriv = dev->private;
3662         static const int bitstream_length = 10;
3663         unsigned int bit, register_bits;
3664         unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3665         static const int ad8402_udelay = 1;
3666 
3667         register_bits = SELECT_8402_64XX_BIT;
3668         udelay(ad8402_udelay);
3669         writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3670 
3671         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3672                 if (bitstream & bit)
3673                         register_bits |= SERIAL_DATA_IN_BIT;
3674                 else
3675                         register_bits &= ~SERIAL_DATA_IN_BIT;
3676                 udelay(ad8402_udelay);
3677                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3678                 udelay(ad8402_udelay);
3679                 writew(register_bits | SERIAL_CLOCK_BIT,
3680                        devpriv->main_iobase + CALIBRATION_REG);
3681         }
3682 
3683         udelay(ad8402_udelay);
3684         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3685 }
3686 
3687 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3688 static int cb_pcidas64_ad8402_insn_write(struct comedi_device *dev,
3689                                          struct comedi_subdevice *s,
3690                                          struct comedi_insn *insn,
3691                                          unsigned int *data)
3692 {
3693         unsigned int chan = CR_CHAN(insn->chanspec);
3694 
3695         /*
3696          * Programming the calib device is slow. Only write the
3697          * last data value if the value has changed.
3698          */
3699         if (insn->n) {
3700                 unsigned int val = data[insn->n - 1];
3701 
3702                 if (s->readback[chan] != val) {
3703                         ad8402_write(dev, chan, val);
3704                         s->readback[chan] = val;
3705                 }
3706         }
3707 
3708         return insn->n;
3709 }
3710 
3711 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3712 {
3713         struct pcidas64_private *devpriv = dev->private;
3714         static const int bitstream_length = 11;
3715         static const int read_command = 0x6;
3716         unsigned int bitstream = (read_command << 8) | address;
3717         unsigned int bit;
3718         void __iomem * const plx_control_addr =
3719                 devpriv->plx9080_iobase + PLX_REG_CNTRL;
3720         uint16_t value;
3721         static const int value_length = 16;
3722         static const int eeprom_udelay = 1;
3723 
3724         udelay(eeprom_udelay);
3725         devpriv->plx_control_bits &= ~PLX_CNTRL_EESK & ~PLX_CNTRL_EECS;
3726         /* make sure we don't send anything to the i2c bus on 4020 */
3727         devpriv->plx_control_bits |= PLX_CNTRL_USERO;
3728         writel(devpriv->plx_control_bits, plx_control_addr);
3729         /* activate serial eeprom */
3730         udelay(eeprom_udelay);
3731         devpriv->plx_control_bits |= PLX_CNTRL_EECS;
3732         writel(devpriv->plx_control_bits, plx_control_addr);
3733 
3734         /* write read command and desired memory address */
3735         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3736                 /* set bit to be written */
3737                 udelay(eeprom_udelay);
3738                 if (bitstream & bit)
3739                         devpriv->plx_control_bits |= PLX_CNTRL_EEWB;
3740                 else
3741                         devpriv->plx_control_bits &= ~PLX_CNTRL_EEWB;
3742                 writel(devpriv->plx_control_bits, plx_control_addr);
3743                 /* clock in bit */
3744                 udelay(eeprom_udelay);
3745                 devpriv->plx_control_bits |= PLX_CNTRL_EESK;
3746                 writel(devpriv->plx_control_bits, plx_control_addr);
3747                 udelay(eeprom_udelay);
3748                 devpriv->plx_control_bits &= ~PLX_CNTRL_EESK;
3749                 writel(devpriv->plx_control_bits, plx_control_addr);
3750         }
3751         /* read back value from eeprom memory location */
3752         value = 0;
3753         for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3754                 /* clock out bit */
3755                 udelay(eeprom_udelay);
3756                 devpriv->plx_control_bits |= PLX_CNTRL_EESK;
3757                 writel(devpriv->plx_control_bits, plx_control_addr);
3758                 udelay(eeprom_udelay);
3759                 devpriv->plx_control_bits &= ~PLX_CNTRL_EESK;
3760                 writel(devpriv->plx_control_bits, plx_control_addr);
3761                 udelay(eeprom_udelay);
3762                 if (readl(plx_control_addr) & PLX_CNTRL_EERB)
3763                         value |= bit;
3764         }
3765 
3766         /* deactivate eeprom serial input */
3767         udelay(eeprom_udelay);
3768         devpriv->plx_control_bits &= ~PLX_CNTRL_EECS;
3769         writel(devpriv->plx_control_bits, plx_control_addr);
3770 
3771         return value;
3772 }
3773 
3774 static int eeprom_read_insn(struct comedi_device *dev,
3775                             struct comedi_subdevice *s,
3776                             struct comedi_insn *insn, unsigned int *data)
3777 {
3778         data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3779 
3780         return 1;
3781 }
3782 
3783 /* Allocate and initialize the subdevice structures. */
3784 static int setup_subdevices(struct comedi_device *dev)
3785 {
3786         const struct pcidas64_board *board = dev->board_ptr;
3787         struct pcidas64_private *devpriv = dev->private;
3788         struct comedi_subdevice *s;
3789         int i;
3790         int ret;
3791 
3792         ret = comedi_alloc_subdevices(dev, 10);
3793         if (ret)
3794                 return ret;
3795 
3796         s = &dev->subdevices[0];
3797         /* analog input subdevice */
3798         dev->read_subdev = s;
3799         s->type = COMEDI_SUBD_AI;
3800         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3801         if (board->layout == LAYOUT_60XX)
3802                 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3803         else if (board->layout == LAYOUT_64XX)
3804                 s->subdev_flags |= SDF_DIFF;
3805         /* XXX Number of inputs in differential mode is ignored */
3806         s->n_chan = board->ai_se_chans;
3807         s->len_chanlist = 0x2000;
3808         s->maxdata = (1 << board->ai_bits) - 1;
3809         s->range_table = board->ai_range_table;
3810         s->insn_read = ai_rinsn;
3811         s->insn_config = ai_config_insn;
3812         s->do_cmd = ai_cmd;
3813         s->do_cmdtest = ai_cmdtest;
3814         s->cancel = ai_cancel;
3815         if (board->layout == LAYOUT_4020) {
3816                 uint8_t data;
3817                 /*
3818                  * set adc to read from inputs
3819                  * (not internal calibration sources)
3820                  */
3821                 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3822                 /* set channels to +-5 volt input ranges */
3823                 for (i = 0; i < s->n_chan; i++)
3824                         devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3825                 data = devpriv->i2c_cal_range_bits;
3826                 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3827         }
3828 
3829         /* analog output subdevice */
3830         s = &dev->subdevices[1];
3831         if (board->ao_nchan) {
3832                 s->type = COMEDI_SUBD_AO;
3833                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3834                                   SDF_GROUND | SDF_CMD_WRITE;
3835                 s->n_chan = board->ao_nchan;
3836                 s->maxdata = (1 << board->ao_bits) - 1;
3837                 s->range_table = board->ao_range_table;
3838                 s->insn_write = ao_winsn;
3839 
3840                 ret = comedi_alloc_subdev_readback(s);
3841                 if (ret)
3842                         return ret;
3843 
3844                 if (ao_cmd_is_supported(board)) {
3845                         dev->write_subdev = s;
3846                         s->do_cmdtest = ao_cmdtest;
3847                         s->do_cmd = ao_cmd;
3848                         s->len_chanlist = board->ao_nchan;
3849                         s->cancel = ao_cancel;
3850                 }
3851         } else {
3852                 s->type = COMEDI_SUBD_UNUSED;
3853         }
3854 
3855         /* digital input */
3856         s = &dev->subdevices[2];
3857         if (board->layout == LAYOUT_64XX) {
3858                 s->type = COMEDI_SUBD_DI;
3859                 s->subdev_flags = SDF_READABLE;
3860                 s->n_chan = 4;
3861                 s->maxdata = 1;
3862                 s->range_table = &range_digital;
3863                 s->insn_bits = di_rbits;
3864         } else {
3865                 s->type = COMEDI_SUBD_UNUSED;
3866         }
3867 
3868         /* digital output */
3869         if (board->layout == LAYOUT_64XX) {
3870                 s = &dev->subdevices[3];
3871                 s->type = COMEDI_SUBD_DO;
3872                 s->subdev_flags = SDF_WRITABLE;
3873                 s->n_chan = 4;
3874                 s->maxdata = 1;
3875                 s->range_table = &range_digital;
3876                 s->insn_bits = do_wbits;
3877         } else {
3878                 s->type = COMEDI_SUBD_UNUSED;
3879         }
3880 
3881         /* 8255 */
3882         s = &dev->subdevices[4];
3883         if (board->has_8255) {
3884                 if (board->layout == LAYOUT_4020) {
3885                         ret = subdev_8255_init(dev, s, dio_callback_4020,
3886                                                I8255_4020_REG);
3887                 } else {
3888                         ret = subdev_8255_mm_init(dev, s, NULL,
3889                                                   DIO_8255_OFFSET);
3890                 }
3891                 if (ret)
3892                         return ret;
3893         } else {
3894                 s->type = COMEDI_SUBD_UNUSED;
3895         }
3896 
3897         /* 8 channel dio for 60xx */
3898         s = &dev->subdevices[5];
3899         if (board->layout == LAYOUT_60XX) {
3900                 s->type = COMEDI_SUBD_DIO;
3901                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3902                 s->n_chan = 8;
3903                 s->maxdata = 1;
3904                 s->range_table = &range_digital;
3905                 s->insn_config = dio_60xx_config_insn;
3906                 s->insn_bits = dio_60xx_wbits;
3907         } else {
3908                 s->type = COMEDI_SUBD_UNUSED;
3909         }
3910 
3911         /* caldac */
3912         s = &dev->subdevices[6];
3913         s->type = COMEDI_SUBD_CALIB;
3914         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3915         s->n_chan = 8;
3916         if (board->layout == LAYOUT_4020)
3917                 s->maxdata = 0xfff;
3918         else
3919                 s->maxdata = 0xff;
3920         s->insn_write = cb_pcidas64_calib_insn_write;
3921 
3922         ret = comedi_alloc_subdev_readback(s);
3923         if (ret)
3924                 return ret;
3925 
3926         for (i = 0; i < s->n_chan; i++) {
3927                 caldac_write(dev, i, s->maxdata / 2);
3928                 s->readback[i] = s->maxdata / 2;
3929         }
3930 
3931         /* 2 channel ad8402 potentiometer */
3932         s = &dev->subdevices[7];
3933         if (board->layout == LAYOUT_64XX) {
3934                 s->type = COMEDI_SUBD_CALIB;
3935                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3936                 s->n_chan = 2;
3937                 s->maxdata = 0xff;
3938                 s->insn_write = cb_pcidas64_ad8402_insn_write;
3939 
3940                 ret = comedi_alloc_subdev_readback(s);
3941                 if (ret)
3942                         return ret;
3943 
3944                 for (i = 0; i < s->n_chan; i++) {
3945                         ad8402_write(dev, i, s->maxdata / 2);
3946                         s->readback[i] = s->maxdata / 2;
3947                 }
3948         } else {
3949                 s->type = COMEDI_SUBD_UNUSED;
3950         }
3951 
3952         /* serial EEPROM, if present */
3953         s = &dev->subdevices[8];
3954         if (readl(devpriv->plx9080_iobase + PLX_REG_CNTRL) &
3955             PLX_CNTRL_EEPRESENT) {
3956                 s->type = COMEDI_SUBD_MEMORY;
3957                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
3958                 s->n_chan = 128;
3959                 s->maxdata = 0xffff;
3960                 s->insn_read = eeprom_read_insn;
3961         } else {
3962                 s->type = COMEDI_SUBD_UNUSED;
3963         }
3964 
3965         /* user counter subd XXX */
3966         s = &dev->subdevices[9];
3967         s->type = COMEDI_SUBD_UNUSED;
3968 
3969         return 0;
3970 }
3971 
3972 static int auto_attach(struct comedi_device *dev,
3973                        unsigned long context)
3974 {
3975         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
3976         const struct pcidas64_board *board = NULL;
3977         struct pcidas64_private *devpriv;
3978         uint32_t local_range, local_decode;
3979         int retval;
3980 
3981         if (context < ARRAY_SIZE(pcidas64_boards))
3982                 board = &pcidas64_boards[context];
3983         if (!board)
3984                 return -ENODEV;
3985         dev->board_ptr = board;
3986 
3987         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
3988         if (!devpriv)
3989                 return -ENOMEM;
3990 
3991         retval = comedi_pci_enable(dev);
3992         if (retval)
3993                 return retval;
3994         pci_set_master(pcidev);
3995 
3996         /* Initialize dev->board_name */
3997         dev->board_name = board->name;
3998 
3999         devpriv->main_phys_iobase = pci_resource_start(pcidev, 2);
4000         devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3);
4001 
4002         devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
4003         devpriv->main_iobase = pci_ioremap_bar(pcidev, 2);
4004         dev->mmio = pci_ioremap_bar(pcidev, 3);
4005 
4006         if (!devpriv->plx9080_iobase || !devpriv->main_iobase || !dev->mmio) {
4007                 dev_warn(dev->class_dev, "failed to remap io memory\n");
4008                 return -ENOMEM;
4009         }
4010 
4011         /* figure out what local addresses are */
4012         local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS0RR) &
4013                       PLX_LASRR_MEM_MASK;
4014         local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS0BA) &
4015                        local_range & PLX_LASBA_MEM_MASK;
4016         devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
4017                                   ~local_range) | local_decode;
4018         local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS1RR) &
4019                       PLX_LASRR_MEM_MASK;
4020         local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS1BA) &
4021                        local_range & PLX_LASBA_MEM_MASK;
4022         devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
4023                                   ~local_range) | local_decode;
4024 
4025         retval = alloc_and_init_dma_members(dev);
4026         if (retval < 0)
4027                 return retval;
4028 
4029         devpriv->hw_revision =
4030                 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
4031         dev_dbg(dev->class_dev, "stc hardware revision %i\n",
4032                 devpriv->hw_revision);
4033         init_plx9080(dev);
4034         init_stc_registers(dev);
4035 
4036         retval = request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
4037                              dev->board_name, dev);
4038         if (retval) {
4039                 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
4040                         pcidev->irq);
4041                 return retval;
4042         }
4043         dev->irq = pcidev->irq;
4044         dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
4045 
4046         retval = setup_subdevices(dev);
4047         if (retval < 0)
4048                 return retval;
4049 
4050         return 0;
4051 }
4052 
4053 static void detach(struct comedi_device *dev)
4054 {
4055         struct pcidas64_private *devpriv = dev->private;
4056 
4057         if (dev->irq)
4058                 free_irq(dev->irq, dev);
4059         if (devpriv) {
4060                 if (devpriv->plx9080_iobase) {
4061                         disable_plx_interrupts(dev);
4062                         iounmap(devpriv->plx9080_iobase);
4063                 }
4064                 if (devpriv->main_iobase)
4065                         iounmap(devpriv->main_iobase);
4066                 if (dev->mmio)
4067                         iounmap(dev->mmio);
4068         }
4069         comedi_pci_disable(dev);
4070         cb_pcidas64_free_dma(dev);
4071 }
4072 
4073 static struct comedi_driver cb_pcidas64_driver = {
4074         .driver_name    = "cb_pcidas64",
4075         .module         = THIS_MODULE,
4076         .auto_attach    = auto_attach,
4077         .detach         = detach,
4078 };
4079 
4080 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4081                                  const struct pci_device_id *id)
4082 {
4083         return comedi_pci_auto_config(dev, &cb_pcidas64_driver,
4084                                       id->driver_data);
4085 }
4086 
4087 static const struct pci_device_id cb_pcidas64_pci_table[] = {
4088         { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 },
4089         { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 },
4090         { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 },
4091         { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 },
4092         { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 },
4093         { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 },
4094         { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 },
4095         { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 },
4096         { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 },
4097         { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 },
4098         { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 },
4099         { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 },
4100         { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 },
4101         { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 },
4102         { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 },
4103         { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 },
4104         { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 },
4105         { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 },
4106         { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 },
4107         { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 },
4108         { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 },
4109         { 0 }
4110 };
4111 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4112 
4113 static struct pci_driver cb_pcidas64_pci_driver = {
4114         .name           = "cb_pcidas64",
4115         .id_table       = cb_pcidas64_pci_table,
4116         .probe          = cb_pcidas64_pci_probe,
4117         .remove         = comedi_pci_auto_unconfig,
4118 };
4119 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4120 
4121 MODULE_AUTHOR("Comedi http://www.comedi.org");
4122 MODULE_DESCRIPTION("Comedi low-level driver");
4123 MODULE_LICENSE("GPL");
4124 

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