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Linux/drivers/staging/comedi/drivers/cb_pcidas64.c

  1 /*
  2     comedi/drivers/cb_pcidas64.c
  3     This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
  4     64xx, 60xx, and 4020 cards.
  5 
  6     Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
  7     Copyright (C) 2001, 2002 Frank Mori Hess
  8 
  9     Thanks also go to the following people:
 10 
 11     Steve Rosenbluth, for providing the source code for
 12     his pci-das6402 driver, and source code for working QNX pci-6402
 13     drivers by Greg Laird and Mariusz Bogacz.  None of the code was
 14     used directly here, but it was useful as an additional source of
 15     documentation on how to program the boards.
 16 
 17     John Sims, for much testing and feedback on pcidas-4020 support.
 18 
 19     COMEDI - Linux Control and Measurement Device Interface
 20     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
 21 
 22     This program is free software; you can redistribute it and/or modify
 23     it under the terms of the GNU General Public License as published by
 24     the Free Software Foundation; either version 2 of the License, or
 25     (at your option) any later version.
 26 
 27     This program is distributed in the hope that it will be useful,
 28     but WITHOUT ANY WARRANTY; without even the implied warranty of
 29     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 30     GNU General Public License for more details.
 31 */
 32 
 33 /*
 34  * Driver: cb_pcidas64
 35  * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
 36  *   with the PLX 9080 PCI controller
 37  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
 38  * Status: works
 39  * Updated: Fri, 02 Nov 2012 18:58:55 +0000
 40  * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
 41  *   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
 42  *   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
 43  *   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
 44  *   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
 45  *   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
 46  *   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
 47  *   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
 48  *   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
 49  *
 50  * Configuration options:
 51  *   None.
 52  *
 53  * Manual attachment of PCI cards with the comedi_config utility is not
 54  * supported by this driver; they are attached automatically.
 55  *
 56  * These boards may be autocalibrated with the comedi_calibrate utility.
 57  *
 58  * To select the bnc trigger input on the 4020 (instead of the dio input),
 59  * specify a nonzero channel in the chanspec.  If you wish to use an external
 60  * master clock on the 4020, you may do so by setting the scan_begin_src
 61  * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
 62  * to configure the divisor to use for the external clock.
 63  *
 64  * Some devices are not identified because the PCI device IDs are not yet
 65  * known. If you have such a board, please let the maintainers know.
 66  */
 67 
 68 /*
 69 
 70 TODO:
 71         make it return error if user attempts an ai command that uses the
 72         external queue, and an ao command simultaneously user counter subdevice
 73         there are a number of boards this driver will support when they are
 74         fully released, but does not yet since the pci device id numbers
 75         are not yet available.
 76 
 77         support prescaled 100khz clock for slow pacing (not available on 6000
 78         series?)
 79 
 80         make ao fifo size adjustable like ai fifo
 81 */
 82 
 83 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 84 
 85 #include <linux/module.h>
 86 #include <linux/pci.h>
 87 #include <linux/delay.h>
 88 #include <linux/interrupt.h>
 89 
 90 #include "../comedidev.h"
 91 
 92 #include "8253.h"
 93 #include "8255.h"
 94 #include "plx9080.h"
 95 #include "comedi_fc.h"
 96 
 97 #define TIMER_BASE 25           /*  40MHz master clock */
 98 /* 100kHz 'prescaled' clock for slow acquisition,
 99  * maybe I'll support this someday */
100 #define PRESCALED_TIMER_BASE    10000
101 #define DMA_BUFFER_SIZE 0x1000
102 
103 /* maximum value that can be loaded into board's 24-bit counters*/
104 static const int max_counter_value = 0xffffff;
105 
106 /* PCI-DAS64xxx base addresses */
107 
108 /* devpriv->main_iobase registers */
109 enum write_only_registers {
110         INTR_ENABLE_REG = 0x0,  /*  interrupt enable register */
111         HW_CONFIG_REG = 0x2,    /*  hardware config register */
112         DAQ_SYNC_REG = 0xc,
113         DAQ_ATRIG_LOW_4020_REG = 0xc,
114         ADC_CONTROL0_REG = 0x10,        /*  adc control register 0 */
115         ADC_CONTROL1_REG = 0x12,        /*  adc control register 1 */
116         CALIBRATION_REG = 0x14,
117         /*  lower 16 bits of adc sample interval counter */
118         ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
119         /*  upper 8 bits of adc sample interval counter */
120         ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
121         /*  lower 16 bits of delay interval counter */
122         ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
123         /*  upper 8 bits of delay interval counter */
124         ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
125         /*  lower 16 bits of hardware conversion/scan counter */
126         ADC_COUNT_LOWER_REG = 0x1e,
127         /*  upper 8 bits of hardware conversion/scan counter */
128         ADC_COUNT_UPPER_REG = 0x20,
129         ADC_START_REG = 0x22,   /*  software trigger to start acquisition */
130         ADC_CONVERT_REG = 0x24, /*  initiates single conversion */
131         ADC_QUEUE_CLEAR_REG = 0x26,     /*  clears adc queue */
132         ADC_QUEUE_LOAD_REG = 0x28,      /*  loads adc queue */
133         ADC_BUFFER_CLEAR_REG = 0x2a,
134         /*  high channel for internal queue, use adc_chan_bits() inline above */
135         ADC_QUEUE_HIGH_REG = 0x2c,
136         DAC_CONTROL0_REG = 0x50,        /*  dac control register 0 */
137         DAC_CONTROL1_REG = 0x52,        /*  dac control register 0 */
138         /*  lower 16 bits of dac sample interval counter */
139         DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
140         /*  upper 8 bits of dac sample interval counter */
141         DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
142         DAC_SELECT_REG = 0x60,
143         DAC_START_REG = 0x64,
144         DAC_BUFFER_CLEAR_REG = 0x66,    /*  clear dac buffer */
145 };
146 
147 static inline unsigned int dac_convert_reg(unsigned int channel)
148 {
149         return 0x70 + (2 * (channel & 0x1));
150 }
151 
152 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
153 {
154         return 0x70 + (4 * (channel & 0x1));
155 }
156 
157 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
158 {
159         return 0x72 + (4 * (channel & 0x1));
160 }
161 
162 enum read_only_registers {
163         /*  hardware status register,
164          *  reading this apparently clears pending interrupts as well */
165         HW_STATUS_REG = 0x0,
166         PIPE1_READ_REG = 0x4,
167         ADC_READ_PNTR_REG = 0x8,
168         LOWER_XFER_REG = 0x10,
169         ADC_WRITE_PNTR_REG = 0xc,
170         PREPOST_REG = 0x14,
171 };
172 
173 enum read_write_registers {
174         I8255_4020_REG = 0x48,  /*  8255 offset, for 4020 only */
175         /*  external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
176         ADC_QUEUE_FIFO_REG = 0x100,
177         ADC_FIFO_REG = 0x200,   /* adc data fifo */
178         /* dac data fifo, has weird interactions with external channel queue */
179         DAC_FIFO_REG = 0x300,
180 };
181 
182 /* devpriv->dio_counter_iobase registers */
183 enum dio_counter_registers {
184         DIO_8255_OFFSET = 0x0,
185         DO_REG = 0x20,
186         DI_REG = 0x28,
187         DIO_DIRECTION_60XX_REG = 0x40,
188         DIO_DATA_60XX_REG = 0x48,
189 };
190 
191 /* bit definitions for write-only registers */
192 
193 enum intr_enable_contents {
194         ADC_INTR_SRC_MASK = 0x3,        /*  adc interrupt source mask */
195         ADC_INTR_QFULL_BITS = 0x0,      /*  interrupt fifo quarter full */
196         ADC_INTR_EOC_BITS = 0x1,        /*  interrupt end of conversion */
197         ADC_INTR_EOSCAN_BITS = 0x2,     /*  interrupt end of scan */
198         ADC_INTR_EOSEQ_BITS = 0x3,      /*  interrupt end of sequence mask */
199         EN_ADC_INTR_SRC_BIT = 0x4,      /*  enable adc interrupt source */
200         EN_ADC_DONE_INTR_BIT = 0x8,     /*  enable adc acquisition done intr */
201         DAC_INTR_SRC_MASK = 0x30,
202         DAC_INTR_QEMPTY_BITS = 0x0,
203         DAC_INTR_HIGH_CHAN_BITS = 0x10,
204         EN_DAC_INTR_SRC_BIT = 0x40,     /*  enable dac interrupt source */
205         EN_DAC_DONE_INTR_BIT = 0x80,
206         EN_ADC_ACTIVE_INTR_BIT = 0x200, /*  enable adc active interrupt */
207         EN_ADC_STOP_INTR_BIT = 0x400,   /*  enable adc stop trigger interrupt */
208         EN_DAC_ACTIVE_INTR_BIT = 0x800, /*  enable dac active interrupt */
209         EN_DAC_UNDERRUN_BIT = 0x4000,   /*  enable dac underrun status bit */
210         EN_ADC_OVERRUN_BIT = 0x8000,    /*  enable adc overrun status bit */
211 };
212 
213 enum hw_config_contents {
214         MASTER_CLOCK_4020_MASK = 0x3,   /*  master clock source mask for 4020 */
215         INTERNAL_CLOCK_4020_BITS = 0x1, /*  use 40 MHz internal master clock */
216         BNC_CLOCK_4020_BITS = 0x2,      /*  use BNC input for master clock */
217         EXT_CLOCK_4020_BITS = 0x3,      /*  use dio input for master clock */
218         EXT_QUEUE_BIT = 0x200,          /*  use external channel/gain queue */
219         /*  use 225 nanosec strobe when loading dac instead of 50 nanosec */
220         SLOW_DAC_BIT = 0x400,
221         /*  bit with unknown function yet given as default value in pci-das64
222          *  manual */
223         HW_CONFIG_DUMMY_BITS = 0x2000,
224         /*  bit selects channels 1/0 for analog input/output, otherwise 0/1 */
225         DMA_CH_SELECT_BIT = 0x8000,
226         FIFO_SIZE_REG = 0x4,            /*  allows adjustment of fifo sizes */
227         DAC_FIFO_SIZE_MASK = 0xff00,    /*  bits that set dac fifo size */
228         DAC_FIFO_BITS = 0xf800,         /*  8k sample ao fifo */
229 };
230 #define DAC_FIFO_SIZE 0x2000
231 
232 enum daq_atrig_low_4020_contents {
233         /*  use trig/ext clk bnc input for analog gate signal */
234         EXT_AGATE_BNC_BIT = 0x8000,
235         /*  use trig/ext clk bnc input for external stop trigger signal */
236         EXT_STOP_TRIG_BNC_BIT = 0x4000,
237         /*  use trig/ext clk bnc input for external start trigger signal */
238         EXT_START_TRIG_BNC_BIT = 0x2000,
239 };
240 
241 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
242 {
243         return threshold & 0xfff;
244 }
245 
246 enum adc_control0_contents {
247         ADC_GATE_SRC_MASK = 0x3,        /*  bits that select gate */
248         ADC_SOFT_GATE_BITS = 0x1,       /*  software gate */
249         ADC_EXT_GATE_BITS = 0x2,        /*  external digital gate */
250         ADC_ANALOG_GATE_BITS = 0x3,     /*  analog level gate */
251         ADC_GATE_LEVEL_BIT = 0x4,       /*  level-sensitive gate (for digital) */
252         ADC_GATE_POLARITY_BIT = 0x8,    /*  gate active low */
253         ADC_START_TRIG_SOFT_BITS = 0x10,
254         ADC_START_TRIG_EXT_BITS = 0x20,
255         ADC_START_TRIG_ANALOG_BITS = 0x30,
256         ADC_START_TRIG_MASK = 0x30,
257         ADC_START_TRIG_FALLING_BIT = 0x40,      /*  trig 1 uses falling edge */
258         /*  external pacing uses falling edge */
259         ADC_EXT_CONV_FALLING_BIT = 0x800,
260         /*  enable hardware scan counter */
261         ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
262         ADC_DMA_DISABLE_BIT = 0x4000,   /*  disables dma */
263         ADC_ENABLE_BIT = 0x8000,        /*  master adc enable */
264 };
265 
266 enum adc_control1_contents {
267         /*  should be set for boards with > 16 channels */
268         ADC_QUEUE_CONFIG_BIT = 0x1,
269         CONVERT_POLARITY_BIT = 0x10,
270         EOC_POLARITY_BIT = 0x20,
271         ADC_SW_GATE_BIT = 0x40, /*  software gate of adc */
272         ADC_DITHER_BIT = 0x200, /*  turn on extra noise for dithering */
273         RETRIGGER_BIT = 0x800,
274         ADC_LO_CHANNEL_4020_MASK = 0x300,
275         ADC_HI_CHANNEL_4020_MASK = 0xc00,
276         TWO_CHANNEL_4020_BITS = 0x1000, /*  two channel mode for 4020 */
277         FOUR_CHANNEL_4020_BITS = 0x2000, /*  four channel mode for 4020 */
278         CHANNEL_MODE_4020_MASK = 0x3000,
279         ADC_MODE_MASK = 0xf000,
280 };
281 
282 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
283 {
284         return (channel & 0x3) << 8;
285 };
286 
287 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
288 {
289         return (channel & 0x3) << 10;
290 };
291 
292 static inline uint16_t adc_mode_bits(unsigned int mode)
293 {
294         return (mode & 0xf) << 12;
295 };
296 
297 enum calibration_contents {
298         SELECT_8800_BIT = 0x1,
299         SELECT_8402_64XX_BIT = 0x2,
300         SELECT_1590_60XX_BIT = 0x2,
301         CAL_EN_64XX_BIT = 0x40, /*  calibration enable for 64xx series */
302         SERIAL_DATA_IN_BIT = 0x80,
303         SERIAL_CLOCK_BIT = 0x100,
304         CAL_EN_60XX_BIT = 0x200, /*  calibration enable for 60xx series */
305         CAL_GAIN_BIT = 0x800,
306 };
307 
308 /* calibration sources for 6025 are:
309  *  0 : ground
310  *  1 : 10V
311  *  2 : 5V
312  *  3 : 0.5V
313  *  4 : 0.05V
314  *  5 : ground
315  *  6 : dac channel 0
316  *  7 : dac channel 1
317  */
318 
319 static inline uint16_t adc_src_bits(unsigned int source)
320 {
321         return (source & 0xf) << 3;
322 };
323 
324 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
325 {
326         return (channel & 0x3) << 8;
327 };
328 
329 enum adc_queue_load_contents {
330         UNIP_BIT = 0x800,       /*  unipolar/bipolar bit */
331         ADC_SE_DIFF_BIT = 0x1000,       /*  single-ended/ differential bit */
332         /*  non-referenced single-ended (common-mode input) */
333         ADC_COMMON_BIT = 0x2000,
334         QUEUE_EOSEQ_BIT = 0x4000,       /*  queue end of sequence */
335         QUEUE_EOSCAN_BIT = 0x8000,      /*  queue end of scan */
336 };
337 
338 static inline uint16_t adc_chan_bits(unsigned int channel)
339 {
340         return channel & 0x3f;
341 };
342 
343 enum dac_control0_contents {
344         DAC_ENABLE_BIT = 0x8000,        /*  dac controller enable bit */
345         DAC_CYCLIC_STOP_BIT = 0x4000,
346         DAC_WAVEFORM_MODE_BIT = 0x100,
347         DAC_EXT_UPDATE_FALLING_BIT = 0x80,
348         DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
349         WAVEFORM_TRIG_MASK = 0x30,
350         WAVEFORM_TRIG_DISABLED_BITS = 0x0,
351         WAVEFORM_TRIG_SOFT_BITS = 0x10,
352         WAVEFORM_TRIG_EXT_BITS = 0x20,
353         WAVEFORM_TRIG_ADC1_BITS = 0x30,
354         WAVEFORM_TRIG_FALLING_BIT = 0x8,
355         WAVEFORM_GATE_LEVEL_BIT = 0x4,
356         WAVEFORM_GATE_ENABLE_BIT = 0x2,
357         WAVEFORM_GATE_SELECT_BIT = 0x1,
358 };
359 
360 enum dac_control1_contents {
361         DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
362         DAC1_EXT_REF_BIT = 0x200,
363         DAC0_EXT_REF_BIT = 0x100,
364         DAC_OUTPUT_ENABLE_BIT = 0x80,   /*  dac output enable bit */
365         DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
366         DAC_SW_GATE_BIT = 0x20,
367         DAC1_UNIPOLAR_BIT = 0x8,
368         DAC0_UNIPOLAR_BIT = 0x2,
369 };
370 
371 /* bit definitions for read-only registers */
372 enum hw_status_contents {
373         DAC_UNDERRUN_BIT = 0x1,
374         ADC_OVERRUN_BIT = 0x2,
375         DAC_ACTIVE_BIT = 0x4,
376         ADC_ACTIVE_BIT = 0x8,
377         DAC_INTR_PENDING_BIT = 0x10,
378         ADC_INTR_PENDING_BIT = 0x20,
379         DAC_DONE_BIT = 0x40,
380         ADC_DONE_BIT = 0x80,
381         EXT_INTR_PENDING_BIT = 0x100,
382         ADC_STOP_BIT = 0x200,
383 };
384 
385 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
386 {
387         return (hw_status_bits >> 10) & 0x3;
388 };
389 
390 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
391 {
392         return (prepost_bits >> 6) & 0x3;
393 }
394 
395 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
396 {
397         return (prepost_bits >> 12) & 0x3;
398 }
399 
400 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
401 {
402         return (prepost_bits >> 14) & 0x3;
403 }
404 
405 /* I2C addresses for 4020 */
406 enum i2c_addresses {
407         RANGE_CAL_I2C_ADDR = 0x20,
408         CALDAC0_I2C_ADDR = 0xc,
409         CALDAC1_I2C_ADDR = 0xd,
410 };
411 
412 enum range_cal_i2c_contents {
413         /*  bits that set what source the adc converter measures */
414         ADC_SRC_4020_MASK = 0x70,
415         /*  make bnc trig/ext clock threshold 0V instead of 2.5V */
416         BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
417 };
418 
419 static inline uint8_t adc_src_4020_bits(unsigned int source)
420 {
421         return (source << 4) & ADC_SRC_4020_MASK;
422 };
423 
424 static inline uint8_t attenuate_bit(unsigned int channel)
425 {
426         /*  attenuate channel (+-5V input range) */
427         return 1 << (channel & 0x3);
428 };
429 
430 /* analog input ranges for 64xx boards */
431 static const struct comedi_lrange ai_ranges_64xx = {
432         8, {
433                 BIP_RANGE(10),
434                 BIP_RANGE(5),
435                 BIP_RANGE(2.5),
436                 BIP_RANGE(1.25),
437                 UNI_RANGE(10),
438                 UNI_RANGE(5),
439                 UNI_RANGE(2.5),
440                 UNI_RANGE(1.25)
441         }
442 };
443 
444 /* analog input ranges for 60xx boards */
445 static const struct comedi_lrange ai_ranges_60xx = {
446         4, {
447                 BIP_RANGE(10),
448                 BIP_RANGE(5),
449                 BIP_RANGE(0.5),
450                 BIP_RANGE(0.05)
451         }
452 };
453 
454 /* analog input ranges for 6030, etc boards */
455 static const struct comedi_lrange ai_ranges_6030 = {
456         14, {
457                 BIP_RANGE(10),
458                 BIP_RANGE(5),
459                 BIP_RANGE(2),
460                 BIP_RANGE(1),
461                 BIP_RANGE(0.5),
462                 BIP_RANGE(0.2),
463                 BIP_RANGE(0.1),
464                 UNI_RANGE(10),
465                 UNI_RANGE(5),
466                 UNI_RANGE(2),
467                 UNI_RANGE(1),
468                 UNI_RANGE(0.5),
469                 UNI_RANGE(0.2),
470                 UNI_RANGE(0.1)
471         }
472 };
473 
474 /* analog input ranges for 6052, etc boards */
475 static const struct comedi_lrange ai_ranges_6052 = {
476         15, {
477                 BIP_RANGE(10),
478                 BIP_RANGE(5),
479                 BIP_RANGE(2.5),
480                 BIP_RANGE(1),
481                 BIP_RANGE(0.5),
482                 BIP_RANGE(0.25),
483                 BIP_RANGE(0.1),
484                 BIP_RANGE(0.05),
485                 UNI_RANGE(10),
486                 UNI_RANGE(5),
487                 UNI_RANGE(2),
488                 UNI_RANGE(1),
489                 UNI_RANGE(0.5),
490                 UNI_RANGE(0.2),
491                 UNI_RANGE(0.1)
492         }
493 };
494 
495 /* analog input ranges for 4020 board */
496 static const struct comedi_lrange ai_ranges_4020 = {
497         2, {
498                 BIP_RANGE(5),
499                 BIP_RANGE(1)
500         }
501 };
502 
503 /* analog output ranges */
504 static const struct comedi_lrange ao_ranges_64xx = {
505         4, {
506                 BIP_RANGE(5),
507                 BIP_RANGE(10),
508                 UNI_RANGE(5),
509                 UNI_RANGE(10)
510         }
511 };
512 
513 static const int ao_range_code_64xx[] = {
514         0x0,
515         0x1,
516         0x2,
517         0x3,
518 };
519 
520 static const int ao_range_code_60xx[] = {
521         0x0,
522 };
523 
524 static const struct comedi_lrange ao_ranges_6030 = {
525         2, {
526                 BIP_RANGE(10),
527                 UNI_RANGE(10)
528         }
529 };
530 
531 static const int ao_range_code_6030[] = {
532         0x0,
533         0x2,
534 };
535 
536 static const struct comedi_lrange ao_ranges_4020 = {
537         2, {
538                 BIP_RANGE(5),
539                 BIP_RANGE(10)
540         }
541 };
542 
543 static const int ao_range_code_4020[] = {
544         0x1,
545         0x0,
546 };
547 
548 enum register_layout {
549         LAYOUT_60XX,
550         LAYOUT_64XX,
551         LAYOUT_4020,
552 };
553 
554 struct hw_fifo_info {
555         unsigned int num_segments;
556         unsigned int max_segment_length;
557         unsigned int sample_packing_ratio;
558         uint16_t fifo_size_reg_mask;
559 };
560 
561 enum pcidas64_boardid {
562         BOARD_PCIDAS6402_16,
563         BOARD_PCIDAS6402_12,
564         BOARD_PCIDAS64_M1_16,
565         BOARD_PCIDAS64_M2_16,
566         BOARD_PCIDAS64_M3_16,
567         BOARD_PCIDAS6013,
568         BOARD_PCIDAS6014,
569         BOARD_PCIDAS6023,
570         BOARD_PCIDAS6025,
571         BOARD_PCIDAS6030,
572         BOARD_PCIDAS6031,
573         BOARD_PCIDAS6032,
574         BOARD_PCIDAS6033,
575         BOARD_PCIDAS6034,
576         BOARD_PCIDAS6035,
577         BOARD_PCIDAS6036,
578         BOARD_PCIDAS6040,
579         BOARD_PCIDAS6052,
580         BOARD_PCIDAS6070,
581         BOARD_PCIDAS6071,
582         BOARD_PCIDAS4020_12,
583         BOARD_PCIDAS6402_16_JR,
584         BOARD_PCIDAS64_M1_16_JR,
585         BOARD_PCIDAS64_M2_16_JR,
586         BOARD_PCIDAS64_M3_16_JR,
587         BOARD_PCIDAS64_M1_14,
588         BOARD_PCIDAS64_M2_14,
589         BOARD_PCIDAS64_M3_14,
590 };
591 
592 struct pcidas64_board {
593         const char *name;
594         int ai_se_chans;        /*  number of ai inputs in single-ended mode */
595         int ai_bits;            /*  analog input resolution */
596         int ai_speed;           /*  fastest conversion period in ns */
597         const struct comedi_lrange *ai_range_table;
598         int ao_nchan;           /*  number of analog out channels */
599         int ao_bits;            /*  analog output resolution */
600         int ao_scan_speed;      /*  analog output scan speed */
601         const struct comedi_lrange *ao_range_table;
602         const int *ao_range_code;
603         const struct hw_fifo_info *const ai_fifo;
604         /*  different board families have slightly different registers */
605         enum register_layout layout;
606         unsigned has_8255:1;
607 };
608 
609 static const struct hw_fifo_info ai_fifo_4020 = {
610         .num_segments = 2,
611         .max_segment_length = 0x8000,
612         .sample_packing_ratio = 2,
613         .fifo_size_reg_mask = 0x7f,
614 };
615 
616 static const struct hw_fifo_info ai_fifo_64xx = {
617         .num_segments = 4,
618         .max_segment_length = 0x800,
619         .sample_packing_ratio = 1,
620         .fifo_size_reg_mask = 0x3f,
621 };
622 
623 static const struct hw_fifo_info ai_fifo_60xx = {
624         .num_segments = 4,
625         .max_segment_length = 0x800,
626         .sample_packing_ratio = 1,
627         .fifo_size_reg_mask = 0x7f,
628 };
629 
630 /* maximum number of dma transfers we will chain together into a ring
631  * (and the maximum number of dma buffers we maintain) */
632 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
633 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
634 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
635 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
636 {
637         if (board->layout == LAYOUT_4020)
638                 return MAX_AI_DMA_RING_COUNT;
639         else
640                 return MIN_AI_DMA_RING_COUNT;
641 }
642 
643 static const int bytes_in_sample = 2;
644 
645 static const struct pcidas64_board pcidas64_boards[] = {
646         [BOARD_PCIDAS6402_16] = {
647                 .name           = "pci-das6402/16",
648                 .ai_se_chans    = 64,
649                 .ai_bits        = 16,
650                 .ai_speed       = 5000,
651                 .ao_nchan       = 2,
652                 .ao_bits        = 16,
653                 .ao_scan_speed  = 10000,
654                 .layout         = LAYOUT_64XX,
655                 .ai_range_table = &ai_ranges_64xx,
656                 .ao_range_table = &ao_ranges_64xx,
657                 .ao_range_code  = ao_range_code_64xx,
658                 .ai_fifo        = &ai_fifo_64xx,
659                 .has_8255       = 1,
660         },
661         [BOARD_PCIDAS6402_12] = {
662                 .name           = "pci-das6402/12",     /*  XXX check */
663                 .ai_se_chans    = 64,
664                 .ai_bits        = 12,
665                 .ai_speed       = 5000,
666                 .ao_nchan       = 2,
667                 .ao_bits        = 12,
668                 .ao_scan_speed  = 10000,
669                 .layout         = LAYOUT_64XX,
670                 .ai_range_table = &ai_ranges_64xx,
671                 .ao_range_table = &ao_ranges_64xx,
672                 .ao_range_code  = ao_range_code_64xx,
673                 .ai_fifo        = &ai_fifo_64xx,
674                 .has_8255       = 1,
675         },
676         [BOARD_PCIDAS64_M1_16] = {
677                 .name           = "pci-das64/m1/16",
678                 .ai_se_chans    = 64,
679                 .ai_bits        = 16,
680                 .ai_speed       = 1000,
681                 .ao_nchan       = 2,
682                 .ao_bits        = 16,
683                 .ao_scan_speed  = 10000,
684                 .layout         = LAYOUT_64XX,
685                 .ai_range_table = &ai_ranges_64xx,
686                 .ao_range_table = &ao_ranges_64xx,
687                 .ao_range_code  = ao_range_code_64xx,
688                 .ai_fifo        = &ai_fifo_64xx,
689                 .has_8255       = 1,
690         },
691         [BOARD_PCIDAS64_M2_16] = {
692                 .name = "pci-das64/m2/16",
693                 .ai_se_chans    = 64,
694                 .ai_bits        = 16,
695                 .ai_speed       = 500,
696                 .ao_nchan       = 2,
697                 .ao_bits        = 16,
698                 .ao_scan_speed  = 10000,
699                 .layout         = LAYOUT_64XX,
700                 .ai_range_table = &ai_ranges_64xx,
701                 .ao_range_table = &ao_ranges_64xx,
702                 .ao_range_code  = ao_range_code_64xx,
703                 .ai_fifo        = &ai_fifo_64xx,
704                 .has_8255       = 1,
705         },
706         [BOARD_PCIDAS64_M3_16] = {
707                 .name           = "pci-das64/m3/16",
708                 .ai_se_chans    = 64,
709                 .ai_bits        = 16,
710                 .ai_speed       = 333,
711                 .ao_nchan       = 2,
712                 .ao_bits        = 16,
713                 .ao_scan_speed  = 10000,
714                 .layout         = LAYOUT_64XX,
715                 .ai_range_table = &ai_ranges_64xx,
716                 .ao_range_table = &ao_ranges_64xx,
717                 .ao_range_code  = ao_range_code_64xx,
718                 .ai_fifo        = &ai_fifo_64xx,
719                 .has_8255       = 1,
720         },
721         [BOARD_PCIDAS6013] = {
722                 .name           = "pci-das6013",
723                 .ai_se_chans    = 16,
724                 .ai_bits        = 16,
725                 .ai_speed       = 5000,
726                 .ao_nchan       = 0,
727                 .ao_bits        = 16,
728                 .layout         = LAYOUT_60XX,
729                 .ai_range_table = &ai_ranges_60xx,
730                 .ao_range_table = &range_bipolar10,
731                 .ao_range_code  = ao_range_code_60xx,
732                 .ai_fifo        = &ai_fifo_60xx,
733                 .has_8255       = 0,
734         },
735         [BOARD_PCIDAS6014] = {
736                 .name           = "pci-das6014",
737                 .ai_se_chans    = 16,
738                 .ai_bits        = 16,
739                 .ai_speed       = 5000,
740                 .ao_nchan       = 2,
741                 .ao_bits        = 16,
742                 .ao_scan_speed  = 100000,
743                 .layout         = LAYOUT_60XX,
744                 .ai_range_table = &ai_ranges_60xx,
745                 .ao_range_table = &range_bipolar10,
746                 .ao_range_code  = ao_range_code_60xx,
747                 .ai_fifo        = &ai_fifo_60xx,
748                 .has_8255       = 0,
749         },
750         [BOARD_PCIDAS6023] = {
751                 .name           = "pci-das6023",
752                 .ai_se_chans    = 16,
753                 .ai_bits        = 12,
754                 .ai_speed       = 5000,
755                 .ao_nchan       = 0,
756                 .ao_scan_speed  = 100000,
757                 .layout         = LAYOUT_60XX,
758                 .ai_range_table = &ai_ranges_60xx,
759                 .ao_range_table = &range_bipolar10,
760                 .ao_range_code  = ao_range_code_60xx,
761                 .ai_fifo        = &ai_fifo_60xx,
762                 .has_8255       = 1,
763         },
764         [BOARD_PCIDAS6025] = {
765                 .name           = "pci-das6025",
766                 .ai_se_chans    = 16,
767                 .ai_bits        = 12,
768                 .ai_speed       = 5000,
769                 .ao_nchan       = 2,
770                 .ao_bits        = 12,
771                 .ao_scan_speed  = 100000,
772                 .layout         = LAYOUT_60XX,
773                 .ai_range_table = &ai_ranges_60xx,
774                 .ao_range_table = &range_bipolar10,
775                 .ao_range_code  = ao_range_code_60xx,
776                 .ai_fifo        = &ai_fifo_60xx,
777                 .has_8255       = 1,
778         },
779         [BOARD_PCIDAS6030] = {
780                 .name           = "pci-das6030",
781                 .ai_se_chans    = 16,
782                 .ai_bits        = 16,
783                 .ai_speed       = 10000,
784                 .ao_nchan       = 2,
785                 .ao_bits        = 16,
786                 .ao_scan_speed  = 10000,
787                 .layout         = LAYOUT_60XX,
788                 .ai_range_table = &ai_ranges_6030,
789                 .ao_range_table = &ao_ranges_6030,
790                 .ao_range_code  = ao_range_code_6030,
791                 .ai_fifo        = &ai_fifo_60xx,
792                 .has_8255       = 0,
793         },
794         [BOARD_PCIDAS6031] = {
795                 .name           = "pci-das6031",
796                 .ai_se_chans    = 64,
797                 .ai_bits        = 16,
798                 .ai_speed       = 10000,
799                 .ao_nchan       = 2,
800                 .ao_bits        = 16,
801                 .ao_scan_speed  = 10000,
802                 .layout         = LAYOUT_60XX,
803                 .ai_range_table = &ai_ranges_6030,
804                 .ao_range_table = &ao_ranges_6030,
805                 .ao_range_code  = ao_range_code_6030,
806                 .ai_fifo        = &ai_fifo_60xx,
807                 .has_8255       = 0,
808         },
809         [BOARD_PCIDAS6032] = {
810                 .name           = "pci-das6032",
811                 .ai_se_chans    = 16,
812                 .ai_bits        = 16,
813                 .ai_speed       = 10000,
814                 .ao_nchan       = 0,
815                 .layout         = LAYOUT_60XX,
816                 .ai_range_table = &ai_ranges_6030,
817                 .ai_fifo        = &ai_fifo_60xx,
818                 .has_8255       = 0,
819         },
820         [BOARD_PCIDAS6033] = {
821                 .name           = "pci-das6033",
822                 .ai_se_chans    = 64,
823                 .ai_bits        = 16,
824                 .ai_speed       = 10000,
825                 .ao_nchan       = 0,
826                 .layout         = LAYOUT_60XX,
827                 .ai_range_table = &ai_ranges_6030,
828                 .ai_fifo        = &ai_fifo_60xx,
829                 .has_8255       = 0,
830         },
831         [BOARD_PCIDAS6034] = {
832                 .name           = "pci-das6034",
833                 .ai_se_chans    = 16,
834                 .ai_bits        = 16,
835                 .ai_speed       = 5000,
836                 .ao_nchan       = 0,
837                 .ao_scan_speed  = 0,
838                 .layout         = LAYOUT_60XX,
839                 .ai_range_table = &ai_ranges_60xx,
840                 .ai_fifo        = &ai_fifo_60xx,
841                 .has_8255       = 0,
842         },
843         [BOARD_PCIDAS6035] = {
844                 .name           = "pci-das6035",
845                 .ai_se_chans    = 16,
846                 .ai_bits        = 16,
847                 .ai_speed       = 5000,
848                 .ao_nchan       = 2,
849                 .ao_bits        = 12,
850                 .ao_scan_speed  = 100000,
851                 .layout         = LAYOUT_60XX,
852                 .ai_range_table = &ai_ranges_60xx,
853                 .ao_range_table = &range_bipolar10,
854                 .ao_range_code  = ao_range_code_60xx,
855                 .ai_fifo        = &ai_fifo_60xx,
856                 .has_8255       = 0,
857         },
858         [BOARD_PCIDAS6036] = {
859                 .name           = "pci-das6036",
860                 .ai_se_chans    = 16,
861                 .ai_bits        = 16,
862                 .ai_speed       = 5000,
863                 .ao_nchan       = 2,
864                 .ao_bits        = 16,
865                 .ao_scan_speed  = 100000,
866                 .layout         = LAYOUT_60XX,
867                 .ai_range_table = &ai_ranges_60xx,
868                 .ao_range_table = &range_bipolar10,
869                 .ao_range_code  = ao_range_code_60xx,
870                 .ai_fifo        = &ai_fifo_60xx,
871                 .has_8255       = 0,
872         },
873         [BOARD_PCIDAS6040] = {
874                 .name           = "pci-das6040",
875                 .ai_se_chans    = 16,
876                 .ai_bits        = 12,
877                 .ai_speed       = 2000,
878                 .ao_nchan       = 2,
879                 .ao_bits        = 12,
880                 .ao_scan_speed  = 1000,
881                 .layout         = LAYOUT_60XX,
882                 .ai_range_table = &ai_ranges_6052,
883                 .ao_range_table = &ao_ranges_6030,
884                 .ao_range_code  = ao_range_code_6030,
885                 .ai_fifo        = &ai_fifo_60xx,
886                 .has_8255       = 0,
887         },
888         [BOARD_PCIDAS6052] = {
889                 .name           = "pci-das6052",
890                 .ai_se_chans    = 16,
891                 .ai_bits        = 16,
892                 .ai_speed       = 3333,
893                 .ao_nchan       = 2,
894                 .ao_bits        = 16,
895                 .ao_scan_speed  = 3333,
896                 .layout         = LAYOUT_60XX,
897                 .ai_range_table = &ai_ranges_6052,
898                 .ao_range_table = &ao_ranges_6030,
899                 .ao_range_code  = ao_range_code_6030,
900                 .ai_fifo        = &ai_fifo_60xx,
901                 .has_8255       = 0,
902         },
903         [BOARD_PCIDAS6070] = {
904                 .name           = "pci-das6070",
905                 .ai_se_chans    = 16,
906                 .ai_bits        = 12,
907                 .ai_speed       = 800,
908                 .ao_nchan       = 2,
909                 .ao_bits        = 12,
910                 .ao_scan_speed  = 1000,
911                 .layout         = LAYOUT_60XX,
912                 .ai_range_table = &ai_ranges_6052,
913                 .ao_range_table = &ao_ranges_6030,
914                 .ao_range_code  = ao_range_code_6030,
915                 .ai_fifo        = &ai_fifo_60xx,
916                 .has_8255       = 0,
917         },
918         [BOARD_PCIDAS6071] = {
919                 .name           = "pci-das6071",
920                 .ai_se_chans    = 64,
921                 .ai_bits        = 12,
922                 .ai_speed       = 800,
923                 .ao_nchan       = 2,
924                 .ao_bits        = 12,
925                 .ao_scan_speed  = 1000,
926                 .layout         = LAYOUT_60XX,
927                 .ai_range_table = &ai_ranges_6052,
928                 .ao_range_table = &ao_ranges_6030,
929                 .ao_range_code  = ao_range_code_6030,
930                 .ai_fifo        = &ai_fifo_60xx,
931                 .has_8255       = 0,
932         },
933         [BOARD_PCIDAS4020_12] = {
934                 .name           = "pci-das4020/12",
935                 .ai_se_chans    = 4,
936                 .ai_bits        = 12,
937                 .ai_speed       = 50,
938                 .ao_bits        = 12,
939                 .ao_nchan       = 2,
940                 .ao_scan_speed  = 0,    /*  no hardware pacing on ao */
941                 .layout         = LAYOUT_4020,
942                 .ai_range_table = &ai_ranges_4020,
943                 .ao_range_table = &ao_ranges_4020,
944                 .ao_range_code  = ao_range_code_4020,
945                 .ai_fifo        = &ai_fifo_4020,
946                 .has_8255       = 1,
947         },
948 #if 0
949         /*
950          * The device id for these boards is unknown
951          */
952 
953         [BOARD_PCIDAS6402_16_JR] = {
954                 .name           = "pci-das6402/16/jr",
955                 .ai_se_chans    = 64,
956                 .ai_bits        = 16,
957                 .ai_speed       = 5000,
958                 .ao_nchan       = 0,
959                 .ao_scan_speed  = 10000,
960                 .layout         = LAYOUT_64XX,
961                 .ai_range_table = &ai_ranges_64xx,
962                 .ai_fifo        = ai_fifo_64xx,
963                 .has_8255       = 1,
964         },
965         [BOARD_PCIDAS64_M1_16_JR] = {
966                 .name           = "pci-das64/m1/16/jr",
967                 .ai_se_chans    = 64,
968                 .ai_bits        = 16,
969                 .ai_speed       = 1000,
970                 .ao_nchan       = 0,
971                 .ao_scan_speed  = 10000,
972                 .layout         = LAYOUT_64XX,
973                 .ai_range_table = &ai_ranges_64xx,
974                 .ai_fifo        = ai_fifo_64xx,
975                 .has_8255       = 1,
976         },
977         [BOARD_PCIDAS64_M2_16_JR] = {
978                 .name = "pci-das64/m2/16/jr",
979                 .ai_se_chans    = 64,
980                 .ai_bits        = 16,
981                 .ai_speed       = 500,
982                 .ao_nchan       = 0,
983                 .ao_scan_speed  = 10000,
984                 .layout         = LAYOUT_64XX,
985                 .ai_range_table = &ai_ranges_64xx,
986                 .ai_fifo        = ai_fifo_64xx,
987                 .has_8255       = 1,
988         },
989         [BOARD_PCIDAS64_M3_16_JR] = {
990                 .name           = "pci-das64/m3/16/jr",
991                 .ai_se_chans    = 64,
992                 .ai_bits        = 16,
993                 .ai_speed       = 333,
994                 .ao_nchan       = 0,
995                 .ao_scan_speed  = 10000,
996                 .layout         = LAYOUT_64XX,
997                 .ai_range_table = &ai_ranges_64xx,
998                 .ai_fifo        = ai_fifo_64xx,
999                 .has_8255       = 1,
1000         },
1001         [BOARD_PCIDAS64_M1_14] = {
1002                 .name           = "pci-das64/m1/14",
1003                 .ai_se_chans    = 64,
1004                 .ai_bits        = 14,
1005                 .ai_speed       = 1000,
1006                 .ao_nchan       = 2,
1007                 .ao_scan_speed  = 10000,
1008                 .layout         = LAYOUT_64XX,
1009                 .ai_range_table = &ai_ranges_64xx,
1010                 .ai_fifo        = ai_fifo_64xx,
1011                 .has_8255       = 1,
1012         },
1013         [BOARD_PCIDAS64_M2_14] = {
1014                 .name           = "pci-das64/m2/14",
1015                 .ai_se_chans    = 64,
1016                 .ai_bits        = 14,
1017                 .ai_speed       = 500,
1018                 .ao_nchan       = 2,
1019                 .ao_scan_speed  = 10000,
1020                 .layout         = LAYOUT_64XX,
1021                 .ai_range_table = &ai_ranges_64xx,
1022                 .ai_fifo        = ai_fifo_64xx,
1023                 .has_8255       = 1,
1024         },
1025         [BOARD_PCIDAS64_M3_14] = {
1026                 .name           = "pci-das64/m3/14",
1027                 .ai_se_chans    = 64,
1028                 .ai_bits        = 14,
1029                 .ai_speed       = 333,
1030                 .ao_nchan       = 2,
1031                 .ao_scan_speed  = 10000,
1032                 .layout         = LAYOUT_64XX,
1033                 .ai_range_table = &ai_ranges_64xx,
1034                 .ai_fifo        = ai_fifo_64xx,
1035                 .has_8255       = 1,
1036         },
1037 #endif
1038 };
1039 
1040 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1041                                               int use_differential)
1042 {
1043         const struct pcidas64_board *thisboard = comedi_board(dev);
1044 
1045         if ((thisboard->layout == LAYOUT_64XX && !use_differential) ||
1046             (thisboard->layout == LAYOUT_60XX && use_differential))
1047                 return ADC_SE_DIFF_BIT;
1048         else
1049                 return 0;
1050 };
1051 
1052 struct ext_clock_info {
1053         /*  master clock divisor to use for scans with external master clock */
1054         unsigned int divisor;
1055         /*  chanspec for master clock input when used as scan begin src */
1056         unsigned int chanspec;
1057 };
1058 
1059 /* this structure is for data unique to this hardware driver. */
1060 struct pcidas64_private {
1061         /*  base addresses (physical) */
1062         resource_size_t main_phys_iobase;
1063         resource_size_t dio_counter_phys_iobase;
1064         /*  base addresses (ioremapped) */
1065         void __iomem *plx9080_iobase;
1066         void __iomem *main_iobase;
1067         void __iomem *dio_counter_iobase;
1068         /*  local address (used by dma controller) */
1069         uint32_t local0_iobase;
1070         uint32_t local1_iobase;
1071         /*  number of analog input samples remaining */
1072         volatile unsigned int ai_count;
1073         /*  dma buffers for analog input */
1074         uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];
1075         /*  physical addresses of ai dma buffers */
1076         dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1077         /*  array of ai dma descriptors read by plx9080,
1078          *  allocated to get proper alignment */
1079         struct plx_dma_desc *ai_dma_desc;
1080         /*  physical address of ai dma descriptor array */
1081         dma_addr_t ai_dma_desc_bus_addr;
1082         /*  index of the ai dma descriptor/buffer
1083          *  that is currently being used */
1084         volatile unsigned int ai_dma_index;
1085         /*  dma buffers for analog output */
1086         uint16_t *ao_buffer[AO_DMA_RING_COUNT];
1087         /*  physical addresses of ao dma buffers */
1088         dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1089         struct plx_dma_desc *ao_dma_desc;
1090         dma_addr_t ao_dma_desc_bus_addr;
1091         /*  keeps track of buffer where the next ao sample should go */
1092         volatile unsigned int ao_dma_index;
1093         /*  number of analog output samples remaining */
1094         volatile unsigned long ao_count;
1095         /*  remember what the analog outputs are set to, to allow readback */
1096         volatile unsigned int ao_value[2];
1097         unsigned int hw_revision;       /*  stc chip hardware revision number */
1098         /*  last bits sent to INTR_ENABLE_REG register */
1099         volatile unsigned int intr_enable_bits;
1100         /*  last bits sent to ADC_CONTROL1_REG register */
1101         volatile uint16_t adc_control1_bits;
1102         /*  last bits sent to FIFO_SIZE_REG register */
1103         volatile uint16_t fifo_size_bits;
1104         /*  last bits sent to HW_CONFIG_REG register */
1105         volatile uint16_t hw_config_bits;
1106         volatile uint16_t dac_control1_bits;
1107         /*  last bits written to plx9080 control register */
1108         volatile uint32_t plx_control_bits;
1109         /*  last bits written to plx interrupt control and status register */
1110         volatile uint32_t plx_intcsr_bits;
1111         /*  index of calibration source readable through ai ch0 */
1112         volatile int calibration_source;
1113         /*  bits written to i2c calibration/range register */
1114         volatile uint8_t i2c_cal_range_bits;
1115         /*  configure digital triggers to trigger on falling edge */
1116         volatile unsigned int ext_trig_falling;
1117         /*  states of various devices stored to enable read-back */
1118         unsigned int ad8402_state[2];
1119         unsigned int caldac_state[8];
1120         volatile short ai_cmd_running;
1121         unsigned int ai_fifo_segment_length;
1122         struct ext_clock_info ext_clock;
1123         unsigned short ao_bounce_buffer[DAC_FIFO_SIZE];
1124 };
1125 
1126 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1127                                        unsigned int range_index)
1128 {
1129         const struct pcidas64_board *thisboard = comedi_board(dev);
1130         const struct comedi_krange *range =
1131                 &thisboard->ai_range_table->range[range_index];
1132         unsigned int bits = 0;
1133 
1134         switch (range->max) {
1135         case 10000000:
1136                 bits = 0x000;
1137                 break;
1138         case 5000000:
1139                 bits = 0x100;
1140                 break;
1141         case 2000000:
1142         case 2500000:
1143                 bits = 0x200;
1144                 break;
1145         case 1000000:
1146         case 1250000:
1147                 bits = 0x300;
1148                 break;
1149         case 500000:
1150                 bits = 0x400;
1151                 break;
1152         case 200000:
1153         case 250000:
1154                 bits = 0x500;
1155                 break;
1156         case 100000:
1157                 bits = 0x600;
1158                 break;
1159         case 50000:
1160                 bits = 0x700;
1161                 break;
1162         default:
1163                 comedi_error(dev, "bug! in ai_range_bits_6xxx");
1164                 break;
1165         }
1166         if (range->min == 0)
1167                 bits += 0x900;
1168         return bits;
1169 }
1170 
1171 static unsigned int hw_revision(const struct comedi_device *dev,
1172                                 uint16_t hw_status_bits)
1173 {
1174         const struct pcidas64_board *thisboard = comedi_board(dev);
1175 
1176         if (thisboard->layout == LAYOUT_4020)
1177                 return (hw_status_bits >> 13) & 0x7;
1178 
1179         return (hw_status_bits >> 12) & 0xf;
1180 }
1181 
1182 static void set_dac_range_bits(struct comedi_device *dev,
1183                                volatile uint16_t *bits, unsigned int channel,
1184                                unsigned int range)
1185 {
1186         const struct pcidas64_board *thisboard = comedi_board(dev);
1187         unsigned int code = thisboard->ao_range_code[range];
1188 
1189         if (channel > 1)
1190                 comedi_error(dev, "bug! bad channel?");
1191         if (code & ~0x3)
1192                 comedi_error(dev, "bug! bad range code?");
1193 
1194         *bits &= ~(0x3 << (2 * channel));
1195         *bits |= code << (2 * channel);
1196 };
1197 
1198 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1199 {
1200         return board->ao_nchan && board->layout != LAYOUT_4020;
1201 }
1202 
1203 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1204 {
1205         struct pcidas64_private *devpriv = dev->private;
1206         unsigned long flags;
1207 
1208         /*  spinlock for plx dma control/status reg */
1209         spin_lock_irqsave(&dev->spinlock, flags);
1210 
1211         plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1212 
1213         spin_unlock_irqrestore(&dev->spinlock, flags);
1214 }
1215 
1216 static void disable_plx_interrupts(struct comedi_device *dev)
1217 {
1218         struct pcidas64_private *devpriv = dev->private;
1219 
1220         devpriv->plx_intcsr_bits = 0;
1221         writel(devpriv->plx_intcsr_bits,
1222                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1223 }
1224 
1225 static void disable_ai_interrupts(struct comedi_device *dev)
1226 {
1227         struct pcidas64_private *devpriv = dev->private;
1228         unsigned long flags;
1229 
1230         spin_lock_irqsave(&dev->spinlock, flags);
1231         devpriv->intr_enable_bits &=
1232                 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1233                 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1234                 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1235         writew(devpriv->intr_enable_bits,
1236                devpriv->main_iobase + INTR_ENABLE_REG);
1237         spin_unlock_irqrestore(&dev->spinlock, flags);
1238 }
1239 
1240 static void enable_ai_interrupts(struct comedi_device *dev,
1241                                  const struct comedi_cmd *cmd)
1242 {
1243         const struct pcidas64_board *thisboard = comedi_board(dev);
1244         struct pcidas64_private *devpriv = dev->private;
1245         uint32_t bits;
1246         unsigned long flags;
1247 
1248         bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1249                EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1250         /*  Use pio transfer and interrupt on end of conversion
1251          *  if TRIG_WAKE_EOS flag is set. */
1252         if (cmd->flags & TRIG_WAKE_EOS) {
1253                 /*  4020 doesn't support pio transfers except for fifo dregs */
1254                 if (thisboard->layout != LAYOUT_4020)
1255                         bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1256         }
1257         spin_lock_irqsave(&dev->spinlock, flags);
1258         devpriv->intr_enable_bits |= bits;
1259         writew(devpriv->intr_enable_bits,
1260                devpriv->main_iobase + INTR_ENABLE_REG);
1261         spin_unlock_irqrestore(&dev->spinlock, flags);
1262 }
1263 
1264 /* initialize plx9080 chip */
1265 static void init_plx9080(struct comedi_device *dev)
1266 {
1267         const struct pcidas64_board *thisboard = comedi_board(dev);
1268         struct pcidas64_private *devpriv = dev->private;
1269         uint32_t bits;
1270         void __iomem *plx_iobase = devpriv->plx9080_iobase;
1271 
1272         devpriv->plx_control_bits =
1273                 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
1274 
1275 #ifdef __BIG_ENDIAN
1276         bits = BIGEND_DMA0 | BIGEND_DMA1;
1277 #else
1278         bits = 0;
1279 #endif
1280         writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
1281 
1282         disable_plx_interrupts(dev);
1283 
1284         abort_dma(dev, 0);
1285         abort_dma(dev, 1);
1286 
1287         /*  configure dma0 mode */
1288         bits = 0;
1289         /*  enable ready input, not sure if this is necessary */
1290         bits |= PLX_DMA_EN_READYIN_BIT;
1291         /*  enable bterm, not sure if this is necessary */
1292         bits |= PLX_EN_BTERM_BIT;
1293         /*  enable dma chaining */
1294         bits |= PLX_EN_CHAIN_BIT;
1295         /*  enable interrupt on dma done
1296          *  (probably don't need this, since chain never finishes) */
1297         bits |= PLX_EN_DMA_DONE_INTR_BIT;
1298         /*  don't increment local address during transfers
1299          *  (we are transferring from a fixed fifo register) */
1300         bits |= PLX_LOCAL_ADDR_CONST_BIT;
1301         /*  route dma interrupt to pci bus */
1302         bits |= PLX_DMA_INTR_PCI_BIT;
1303         /*  enable demand mode */
1304         bits |= PLX_DEMAND_MODE_BIT;
1305         /*  enable local burst mode */
1306         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1307         /*  4020 uses 32 bit dma */
1308         if (thisboard->layout == LAYOUT_4020)
1309                 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1310         else            /*  localspace0 bus is 16 bits wide */
1311                 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1312         writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1313         if (ao_cmd_is_supported(thisboard))
1314                 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1315 
1316         /*  enable interrupts on plx 9080 */
1317         devpriv->plx_intcsr_bits |=
1318             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1319             ICS_DMA0_E | ICS_DMA1_E;
1320         writel(devpriv->plx_intcsr_bits,
1321                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1322 }
1323 
1324 static void disable_ai_pacing(struct comedi_device *dev)
1325 {
1326         struct pcidas64_private *devpriv = dev->private;
1327         unsigned long flags;
1328 
1329         disable_ai_interrupts(dev);
1330 
1331         spin_lock_irqsave(&dev->spinlock, flags);
1332         devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1333         writew(devpriv->adc_control1_bits,
1334                devpriv->main_iobase + ADC_CONTROL1_REG);
1335         spin_unlock_irqrestore(&dev->spinlock, flags);
1336 
1337         /* disable pacing, triggering, etc */
1338         writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1339                devpriv->main_iobase + ADC_CONTROL0_REG);
1340 }
1341 
1342 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1343                                       unsigned int num_entries)
1344 {
1345         const struct pcidas64_board *thisboard = comedi_board(dev);
1346         struct pcidas64_private *devpriv = dev->private;
1347         static const int increment_size = 0x100;
1348         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1349         unsigned int num_increments;
1350         uint16_t bits;
1351 
1352         if (num_entries < increment_size)
1353                 num_entries = increment_size;
1354         if (num_entries > fifo->max_segment_length)
1355                 num_entries = fifo->max_segment_length;
1356 
1357         /*  1 == 256 entries, 2 == 512 entries, etc */
1358         num_increments = (num_entries + increment_size / 2) / increment_size;
1359 
1360         bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1361         devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1362         devpriv->fifo_size_bits |= bits;
1363         writew(devpriv->fifo_size_bits,
1364                devpriv->main_iobase + FIFO_SIZE_REG);
1365 
1366         devpriv->ai_fifo_segment_length = num_increments * increment_size;
1367 
1368         return devpriv->ai_fifo_segment_length;
1369 }
1370 
1371 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
1372 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1373 {
1374         const struct pcidas64_board *thisboard = comedi_board(dev);
1375         unsigned int num_fifo_entries;
1376         int retval;
1377         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1378 
1379         num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1380 
1381         retval = set_ai_fifo_segment_length(dev,
1382                                             num_fifo_entries /
1383                                             fifo->num_segments);
1384         if (retval < 0)
1385                 return retval;
1386 
1387         num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
1388 
1389         return num_samples;
1390 }
1391 
1392 /* query length of fifo */
1393 static unsigned int ai_fifo_size(struct comedi_device *dev)
1394 {
1395         const struct pcidas64_board *thisboard = comedi_board(dev);
1396         struct pcidas64_private *devpriv = dev->private;
1397 
1398         return devpriv->ai_fifo_segment_length *
1399                thisboard->ai_fifo->num_segments *
1400                thisboard->ai_fifo->sample_packing_ratio;
1401 }
1402 
1403 static void init_stc_registers(struct comedi_device *dev)
1404 {
1405         const struct pcidas64_board *thisboard = comedi_board(dev);
1406         struct pcidas64_private *devpriv = dev->private;
1407         uint16_t bits;
1408         unsigned long flags;
1409 
1410         spin_lock_irqsave(&dev->spinlock, flags);
1411 
1412         /*  bit should be set for 6025,
1413          *  although docs say boards with <= 16 chans should be cleared XXX */
1414         if (1)
1415                 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1416         writew(devpriv->adc_control1_bits,
1417                devpriv->main_iobase + ADC_CONTROL1_REG);
1418 
1419         /*  6402/16 manual says this register must be initialized to 0xff? */
1420         writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1421 
1422         bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1423         if (thisboard->layout == LAYOUT_4020)
1424                 bits |= INTERNAL_CLOCK_4020_BITS;
1425         devpriv->hw_config_bits |= bits;
1426         writew(devpriv->hw_config_bits,
1427                devpriv->main_iobase + HW_CONFIG_REG);
1428 
1429         writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1430         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1431 
1432         spin_unlock_irqrestore(&dev->spinlock, flags);
1433 
1434         /*  set fifos to maximum size */
1435         devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1436         set_ai_fifo_segment_length(dev,
1437                                    thisboard->ai_fifo->max_segment_length);
1438 
1439         devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1440         devpriv->intr_enable_bits =
1441                 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1442                 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1443         writew(devpriv->intr_enable_bits,
1444                devpriv->main_iobase + INTR_ENABLE_REG);
1445 
1446         disable_ai_pacing(dev);
1447 };
1448 
1449 static int alloc_and_init_dma_members(struct comedi_device *dev)
1450 {
1451         const struct pcidas64_board *thisboard = comedi_board(dev);
1452         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1453         struct pcidas64_private *devpriv = dev->private;
1454         int i;
1455 
1456         /*  allocate pci dma buffers */
1457         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1458                 devpriv->ai_buffer[i] =
1459                         pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1460                                              &devpriv->ai_buffer_bus_addr[i]);
1461                 if (devpriv->ai_buffer[i] == NULL)
1462                         return -ENOMEM;
1463 
1464         }
1465         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1466                 if (ao_cmd_is_supported(thisboard)) {
1467                         devpriv->ao_buffer[i] =
1468                                 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1469                                                      &devpriv->
1470                                                       ao_buffer_bus_addr[i]);
1471                         if (devpriv->ao_buffer[i] == NULL)
1472                                 return -ENOMEM;
1473 
1474                 }
1475         }
1476         /*  allocate dma descriptors */
1477         devpriv->ai_dma_desc =
1478                 pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) *
1479                                      ai_dma_ring_count(thisboard),
1480                                      &devpriv->ai_dma_desc_bus_addr);
1481         if (devpriv->ai_dma_desc == NULL)
1482                 return -ENOMEM;
1483 
1484         if (ao_cmd_is_supported(thisboard)) {
1485                 devpriv->ao_dma_desc =
1486                         pci_alloc_consistent(pcidev,
1487                                              sizeof(struct plx_dma_desc) *
1488                                              AO_DMA_RING_COUNT,
1489                                              &devpriv->ao_dma_desc_bus_addr);
1490                 if (devpriv->ao_dma_desc == NULL)
1491                         return -ENOMEM;
1492         }
1493         /*  initialize dma descriptors */
1494         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1495                 devpriv->ai_dma_desc[i].pci_start_addr =
1496                         cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1497                 if (thisboard->layout == LAYOUT_4020)
1498                         devpriv->ai_dma_desc[i].local_start_addr =
1499                                 cpu_to_le32(devpriv->local1_iobase +
1500                                             ADC_FIFO_REG);
1501                 else
1502                         devpriv->ai_dma_desc[i].local_start_addr =
1503                                 cpu_to_le32(devpriv->local0_iobase +
1504                                             ADC_FIFO_REG);
1505                 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1506                 devpriv->ai_dma_desc[i].next =
1507                         cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1508                                      ((i + 1) % ai_dma_ring_count(thisboard)) *
1509                                      sizeof(devpriv->ai_dma_desc[0])) |
1510                                     PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1511                                     PLX_XFER_LOCAL_TO_PCI);
1512         }
1513         if (ao_cmd_is_supported(thisboard)) {
1514                 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1515                         devpriv->ao_dma_desc[i].pci_start_addr =
1516                                 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1517                         devpriv->ao_dma_desc[i].local_start_addr =
1518                                 cpu_to_le32(devpriv->local0_iobase +
1519                                             DAC_FIFO_REG);
1520                         devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1521                         devpriv->ao_dma_desc[i].next =
1522                                 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1523                                              ((i + 1) % (AO_DMA_RING_COUNT)) *
1524                                              sizeof(devpriv->ao_dma_desc[0])) |
1525                                             PLX_DESC_IN_PCI_BIT |
1526                                             PLX_INTR_TERM_COUNT);
1527                 }
1528         }
1529         return 0;
1530 }
1531 
1532 static inline void warn_external_queue(struct comedi_device *dev)
1533 {
1534         comedi_error(dev,
1535                      "AO command and AI external channel queue cannot be used simultaneously.");
1536         comedi_error(dev,
1537                      "Use internal AI channel queue (channels must be consecutive and use same range/aref)");
1538 }
1539 
1540 /* Their i2c requires a huge delay on setting clock or data high for some reason */
1541 static const int i2c_high_udelay = 1000;
1542 static const int i2c_low_udelay = 10;
1543 
1544 /* set i2c data line high or low */
1545 static void i2c_set_sda(struct comedi_device *dev, int state)
1546 {
1547         struct pcidas64_private *devpriv = dev->private;
1548         static const int data_bit = CTL_EE_W;
1549         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1550                                          PLX_CONTROL_REG;
1551 
1552         if (state) {
1553                 /*  set data line high */
1554                 devpriv->plx_control_bits &= ~data_bit;
1555                 writel(devpriv->plx_control_bits, plx_control_addr);
1556                 udelay(i2c_high_udelay);
1557         } else {                /*  set data line low */
1558 
1559                 devpriv->plx_control_bits |= data_bit;
1560                 writel(devpriv->plx_control_bits, plx_control_addr);
1561                 udelay(i2c_low_udelay);
1562         }
1563 }
1564 
1565 /* set i2c clock line high or low */
1566 static void i2c_set_scl(struct comedi_device *dev, int state)
1567 {
1568         struct pcidas64_private *devpriv = dev->private;
1569         static const int clock_bit = CTL_USERO;
1570         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1571                                          PLX_CONTROL_REG;
1572 
1573         if (state) {
1574                 /*  set clock line high */
1575                 devpriv->plx_control_bits &= ~clock_bit;
1576                 writel(devpriv->plx_control_bits, plx_control_addr);
1577                 udelay(i2c_high_udelay);
1578         } else {                /*  set clock line low */
1579 
1580                 devpriv->plx_control_bits |= clock_bit;
1581                 writel(devpriv->plx_control_bits, plx_control_addr);
1582                 udelay(i2c_low_udelay);
1583         }
1584 }
1585 
1586 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
1587 {
1588         uint8_t bit;
1589         unsigned int num_bits = 8;
1590 
1591         for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1592                 i2c_set_scl(dev, 0);
1593                 if ((byte & bit))
1594                         i2c_set_sda(dev, 1);
1595                 else
1596                         i2c_set_sda(dev, 0);
1597                 i2c_set_scl(dev, 1);
1598         }
1599 }
1600 
1601 /* we can't really read the lines, so fake it */
1602 static int i2c_read_ack(struct comedi_device *dev)
1603 {
1604         i2c_set_scl(dev, 0);
1605         i2c_set_sda(dev, 1);
1606         i2c_set_scl(dev, 1);
1607 
1608         return 0;               /*  return fake acknowledge bit */
1609 }
1610 
1611 /* send start bit */
1612 static void i2c_start(struct comedi_device *dev)
1613 {
1614         i2c_set_scl(dev, 1);
1615         i2c_set_sda(dev, 1);
1616         i2c_set_sda(dev, 0);
1617 }
1618 
1619 /* send stop bit */
1620 static void i2c_stop(struct comedi_device *dev)
1621 {
1622         i2c_set_scl(dev, 0);
1623         i2c_set_sda(dev, 0);
1624         i2c_set_scl(dev, 1);
1625         i2c_set_sda(dev, 1);
1626 }
1627 
1628 static void i2c_write(struct comedi_device *dev, unsigned int address,
1629                       const uint8_t *data, unsigned int length)
1630 {
1631         struct pcidas64_private *devpriv = dev->private;
1632         unsigned int i;
1633         uint8_t bitstream;
1634         static const int read_bit = 0x1;
1635 
1636         /* XXX need mutex to prevent simultaneous attempts to access
1637          * eeprom and i2c bus */
1638 
1639         /*  make sure we dont send anything to eeprom */
1640         devpriv->plx_control_bits &= ~CTL_EE_CS;
1641 
1642         i2c_stop(dev);
1643         i2c_start(dev);
1644 
1645         /*  send address and write bit */
1646         bitstream = (address << 1) & ~read_bit;
1647         i2c_write_byte(dev, bitstream);
1648 
1649         /*  get acknowledge */
1650         if (i2c_read_ack(dev) != 0) {
1651                 comedi_error(dev, "i2c write failed: no acknowledge");
1652                 i2c_stop(dev);
1653                 return;
1654         }
1655         /*  write data bytes */
1656         for (i = 0; i < length; i++) {
1657                 i2c_write_byte(dev, data[i]);
1658                 if (i2c_read_ack(dev) != 0) {
1659                         comedi_error(dev, "i2c write failed: no acknowledge");
1660                         i2c_stop(dev);
1661                         return;
1662                 }
1663         }
1664         i2c_stop(dev);
1665 }
1666 
1667 static int cb_pcidas64_ai_eoc(struct comedi_device *dev,
1668                               struct comedi_subdevice *s,
1669                               struct comedi_insn *insn,
1670                               unsigned long context)
1671 {
1672         const struct pcidas64_board *thisboard = comedi_board(dev);
1673         struct pcidas64_private *devpriv = dev->private;
1674         unsigned int status;
1675 
1676         status = readw(devpriv->main_iobase + HW_STATUS_REG);
1677         if (thisboard->layout == LAYOUT_4020) {
1678                 status = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG);
1679                 if (status)
1680                         return 0;
1681         } else {
1682                 if (pipe_full_bits(status))
1683                         return 0;
1684         }
1685         return -EBUSY;
1686 }
1687 
1688 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1689                     struct comedi_insn *insn, unsigned int *data)
1690 {
1691         const struct pcidas64_board *thisboard = comedi_board(dev);
1692         struct pcidas64_private *devpriv = dev->private;
1693         unsigned int bits = 0, n;
1694         unsigned int channel, range, aref;
1695         unsigned long flags;
1696         int ret;
1697 
1698         channel = CR_CHAN(insn->chanspec);
1699         range = CR_RANGE(insn->chanspec);
1700         aref = CR_AREF(insn->chanspec);
1701 
1702         /*  disable card's analog input interrupt sources and pacing */
1703         /*  4020 generates dac done interrupts even though they are disabled */
1704         disable_ai_pacing(dev);
1705 
1706         spin_lock_irqsave(&dev->spinlock, flags);
1707         if (insn->chanspec & CR_ALT_FILTER)
1708                 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1709         else
1710                 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1711         writew(devpriv->adc_control1_bits,
1712                devpriv->main_iobase + ADC_CONTROL1_REG);
1713         spin_unlock_irqrestore(&dev->spinlock, flags);
1714 
1715         if (thisboard->layout != LAYOUT_4020) {
1716                 /*  use internal queue */
1717                 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1718                 writew(devpriv->hw_config_bits,
1719                        devpriv->main_iobase + HW_CONFIG_REG);
1720 
1721                 /*  ALT_SOURCE is internal calibration reference */
1722                 if (insn->chanspec & CR_ALT_SOURCE) {
1723                         unsigned int cal_en_bit;
1724 
1725                         if (thisboard->layout == LAYOUT_60XX)
1726                                 cal_en_bit = CAL_EN_60XX_BIT;
1727                         else
1728                                 cal_en_bit = CAL_EN_64XX_BIT;
1729                         /*  select internal reference source to connect
1730                          *  to channel 0 */
1731                         writew(cal_en_bit |
1732                                adc_src_bits(devpriv->calibration_source),
1733                                devpriv->main_iobase + CALIBRATION_REG);
1734                 } else {
1735                         /*  make sure internal calibration source
1736                          *  is turned off */
1737                         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1738                 }
1739                 /*  load internal queue */
1740                 bits = 0;
1741                 /*  set gain */
1742                 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1743                 /*  set single-ended / differential */
1744                 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1745                 if (aref == AREF_COMMON)
1746                         bits |= ADC_COMMON_BIT;
1747                 bits |= adc_chan_bits(channel);
1748                 /*  set stop channel */
1749                 writew(adc_chan_bits(channel),
1750                        devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1751                 /*  set start channel, and rest of settings */
1752                 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1753         } else {
1754                 uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1755 
1756                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1757                 if (insn->chanspec & CR_ALT_SOURCE) {
1758                         devpriv->i2c_cal_range_bits |=
1759                                 adc_src_4020_bits(devpriv->calibration_source);
1760                 } else {        /* select BNC inputs */
1761                         devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1762                 }
1763                 /*  select range */
1764                 if (range == 0)
1765                         devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1766                 else
1767                         devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1768                 /*  update calibration/range i2c register only if necessary,
1769                  *  as it is very slow */
1770                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1771                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1772                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1773                                   sizeof(i2c_data));
1774                 }
1775 
1776                 /* 4020 manual asks that sample interval register to be set
1777                  * before writing to convert register.
1778                  * Using somewhat arbitrary setting of 4 master clock ticks
1779                  * = 0.1 usec */
1780                 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1781                 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1782         }
1783 
1784         for (n = 0; n < insn->n; n++) {
1785 
1786                 /*  clear adc buffer (inside loop for 4020 sake) */
1787                 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1788 
1789                 /* trigger conversion, bits sent only matter for 4020 */
1790                 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1791                        devpriv->main_iobase + ADC_CONVERT_REG);
1792 
1793                 /*  wait for data */
1794                 ret = comedi_timeout(dev, s, insn, cb_pcidas64_ai_eoc, 0);
1795                 if (ret)
1796                         return ret;
1797 
1798                 if (thisboard->layout == LAYOUT_4020)
1799                         data[n] = readl(devpriv->dio_counter_iobase +
1800                                         ADC_FIFO_REG) & 0xffff;
1801                 else
1802                         data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1803         }
1804 
1805         return n;
1806 }
1807 
1808 static int ai_config_calibration_source(struct comedi_device *dev,
1809                                         unsigned int *data)
1810 {
1811         const struct pcidas64_board *thisboard = comedi_board(dev);
1812         struct pcidas64_private *devpriv = dev->private;
1813         unsigned int source = data[1];
1814         int num_calibration_sources;
1815 
1816         if (thisboard->layout == LAYOUT_60XX)
1817                 num_calibration_sources = 16;
1818         else
1819                 num_calibration_sources = 8;
1820         if (source >= num_calibration_sources) {
1821                 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1822                         source);
1823                 return -EINVAL;
1824         }
1825 
1826         devpriv->calibration_source = source;
1827 
1828         return 2;
1829 }
1830 
1831 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1832 {
1833         const struct pcidas64_board *thisboard = comedi_board(dev);
1834         int fifo_size;
1835         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1836         unsigned int block_size, requested_block_size;
1837         int retval;
1838 
1839         requested_block_size = data[1];
1840 
1841         if (requested_block_size) {
1842                 fifo_size = requested_block_size * fifo->num_segments /
1843                             bytes_in_sample;
1844 
1845                 retval = set_ai_fifo_size(dev, fifo_size);
1846                 if (retval < 0)
1847                         return retval;
1848 
1849         }
1850 
1851         block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1852 
1853         data[1] = block_size;
1854 
1855         return 2;
1856 }
1857 
1858 static int ai_config_master_clock_4020(struct comedi_device *dev,
1859                                        unsigned int *data)
1860 {
1861         struct pcidas64_private *devpriv = dev->private;
1862         unsigned int divisor = data[4];
1863         int retval = 0;
1864 
1865         if (divisor < 2) {
1866                 divisor = 2;
1867                 retval = -EAGAIN;
1868         }
1869 
1870         switch (data[1]) {
1871         case COMEDI_EV_SCAN_BEGIN:
1872                 devpriv->ext_clock.divisor = divisor;
1873                 devpriv->ext_clock.chanspec = data[2];
1874                 break;
1875         default:
1876                 return -EINVAL;
1877                 break;
1878         }
1879 
1880         data[4] = divisor;
1881 
1882         return retval ? retval : 5;
1883 }
1884 
1885 /* XXX could add support for 60xx series */
1886 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1887 {
1888         const struct pcidas64_board *thisboard = comedi_board(dev);
1889 
1890         switch (thisboard->layout) {
1891         case LAYOUT_4020:
1892                 return ai_config_master_clock_4020(dev, data);
1893                 break;
1894         default:
1895                 return -EINVAL;
1896                 break;
1897         }
1898 
1899         return -EINVAL;
1900 }
1901 
1902 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1903                           struct comedi_insn *insn, unsigned int *data)
1904 {
1905         int id = data[0];
1906 
1907         switch (id) {
1908         case INSN_CONFIG_ALT_SOURCE:
1909                 return ai_config_calibration_source(dev, data);
1910                 break;
1911         case INSN_CONFIG_BLOCK_SIZE:
1912                 return ai_config_block_size(dev, data);
1913                 break;
1914         case INSN_CONFIG_TIMER_1:
1915                 return ai_config_master_clock(dev, data);
1916                 break;
1917         default:
1918                 return -EINVAL;
1919                 break;
1920         }
1921         return -EINVAL;
1922 }
1923 
1924 /* Gets nearest achievable timing given master clock speed, does not
1925  * take into account possible minimum/maximum divisor values.  Used
1926  * by other timing checking functions. */
1927 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
1928 {
1929         unsigned int divisor;
1930 
1931         switch (flags & TRIG_ROUND_MASK) {
1932         case TRIG_ROUND_UP:
1933                 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
1934                 break;
1935         case TRIG_ROUND_DOWN:
1936                 divisor = ns / TIMER_BASE;
1937                 break;
1938         case TRIG_ROUND_NEAREST:
1939         default:
1940                 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
1941                 break;
1942         }
1943         return divisor;
1944 }
1945 
1946 /* utility function that rounds desired timing to an achievable time, and
1947  * sets cmd members appropriately.
1948  * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
1949  */
1950 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
1951 {
1952         const struct pcidas64_board *thisboard = comedi_board(dev);
1953         unsigned int convert_divisor = 0, scan_divisor;
1954         static const int min_convert_divisor = 3;
1955         static const int max_convert_divisor =
1956                 max_counter_value + min_convert_divisor;
1957         static const int min_scan_divisor_4020 = 2;
1958         unsigned long long max_scan_divisor, min_scan_divisor;
1959 
1960         if (cmd->convert_src == TRIG_TIMER) {
1961                 if (thisboard->layout == LAYOUT_4020) {
1962                         cmd->convert_arg = 0;
1963                 } else {
1964                         convert_divisor = get_divisor(cmd->convert_arg,
1965                                                       cmd->flags);
1966                         if (convert_divisor > max_convert_divisor)
1967                                 convert_divisor = max_convert_divisor;
1968                         if (convert_divisor < min_convert_divisor)
1969                                 convert_divisor = min_convert_divisor;
1970                         cmd->convert_arg = convert_divisor * TIMER_BASE;
1971                 }
1972         } else if (cmd->convert_src == TRIG_NOW) {
1973                 cmd->convert_arg = 0;
1974         }
1975 
1976         if (cmd->scan_begin_src == TRIG_TIMER) {
1977                 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
1978                 if (cmd->convert_src == TRIG_TIMER) {
1979                         /*  XXX check for integer overflows */
1980                         min_scan_divisor = convert_divisor * cmd->chanlist_len;
1981                         max_scan_divisor =
1982                                 (convert_divisor * cmd->chanlist_len - 1) +
1983                                 max_counter_value;
1984                 } else {
1985                         min_scan_divisor = min_scan_divisor_4020;
1986                         max_scan_divisor = max_counter_value + min_scan_divisor;
1987                 }
1988                 if (scan_divisor > max_scan_divisor)
1989                         scan_divisor = max_scan_divisor;
1990                 if (scan_divisor < min_scan_divisor)
1991                         scan_divisor = min_scan_divisor;
1992                 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
1993         }
1994 
1995         return;
1996 }
1997 
1998 static int cb_pcidas64_ai_check_chanlist(struct comedi_device *dev,
1999                                          struct comedi_subdevice *s,
2000                                          struct comedi_cmd *cmd)
2001 {
2002         const struct pcidas64_board *board = comedi_board(dev);
2003         unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
2004         int i;
2005 
2006         for (i = 1; i < cmd->chanlist_len; i++) {
2007                 unsigned int aref = CR_AREF(cmd->chanlist[i]);
2008 
2009                 if (aref != aref0) {
2010                         dev_dbg(dev->class_dev,
2011                                 "all elements in chanlist must use the same analog reference\n");
2012                         return -EINVAL;
2013                 }
2014         }
2015 
2016         if (board->layout == LAYOUT_4020) {
2017                 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
2018 
2019                 for (i = 1; i < cmd->chanlist_len; i++) {
2020                         unsigned int chan = CR_CHAN(cmd->chanlist[i]);
2021 
2022                         if (chan != (chan0 + i)) {
2023                                 dev_dbg(dev->class_dev,
2024                                         "chanlist must use consecutive channels\n");
2025                                 return -EINVAL;
2026                         }
2027                 }
2028                 if (cmd->chanlist_len == 3) {
2029                         dev_dbg(dev->class_dev,
2030                                 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels\n");
2031                         return -EINVAL;
2032                 }
2033         }
2034 
2035         return 0;
2036 }
2037 
2038 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2039                       struct comedi_cmd *cmd)
2040 {
2041         const struct pcidas64_board *thisboard = comedi_board(dev);
2042         int err = 0;
2043         unsigned int tmp_arg, tmp_arg2;
2044         unsigned int triggers;
2045 
2046         /* Step 1 : check if triggers are trivially valid */
2047 
2048         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2049 
2050         triggers = TRIG_TIMER;
2051         if (thisboard->layout == LAYOUT_4020)
2052                 triggers |= TRIG_OTHER;
2053         else
2054                 triggers |= TRIG_FOLLOW;
2055         err |= cfc_check_trigger_src(&cmd->scan_begin_src, triggers);
2056 
2057         triggers = TRIG_TIMER;
2058         if (thisboard->layout == LAYOUT_4020)
2059                 triggers |= TRIG_NOW;
2060         else
2061                 triggers |= TRIG_EXT;
2062         err |= cfc_check_trigger_src(&cmd->convert_src, triggers);
2063         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2064         err |= cfc_check_trigger_src(&cmd->stop_src,
2065                                      TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2066 
2067         if (err)
2068                 return 1;
2069 
2070         /* Step 2a : make sure trigger sources are unique */
2071 
2072         err |= cfc_check_trigger_is_unique(cmd->start_src);
2073         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2074         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2075         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2076 
2077         /* Step 2b : and mutually compatible */
2078 
2079         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2080                 err |= -EINVAL;
2081 
2082         if (err)
2083                 return 2;
2084 
2085         /* Step 3: check if arguments are trivially valid */
2086 
2087         switch (cmd->start_src) {
2088         case TRIG_NOW:
2089                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2090                 break;
2091         case TRIG_EXT:
2092                 /*
2093                  * start_arg is the CR_CHAN | CR_INVERT of the
2094                  * external trigger.
2095                  */
2096                 break;
2097         }
2098 
2099         if (cmd->convert_src == TRIG_TIMER) {
2100                 if (thisboard->layout == LAYOUT_4020) {
2101                         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2102                 } else {
2103                         err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2104                                                          thisboard->ai_speed);
2105                         /* if scans are timed faster than conversion rate allows */
2106                         if (cmd->scan_begin_src == TRIG_TIMER)
2107                                 err |= cfc_check_trigger_arg_min(
2108                                                 &cmd->scan_begin_arg,
2109                                                 cmd->convert_arg *
2110                                                 cmd->chanlist_len);
2111                 }
2112         }
2113 
2114         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
2115         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2116 
2117         switch (cmd->stop_src) {
2118         case TRIG_EXT:
2119                 break;
2120         case TRIG_COUNT:
2121                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2122                 break;
2123         case TRIG_NONE:
2124                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2125                 break;
2126         default:
2127                 break;
2128         }
2129 
2130         if (err)
2131                 return 3;
2132 
2133         /* step 4: fix up any arguments */
2134 
2135         if (cmd->convert_src == TRIG_TIMER) {
2136                 tmp_arg = cmd->convert_arg;
2137                 tmp_arg2 = cmd->scan_begin_arg;
2138                 check_adc_timing(dev, cmd);
2139                 if (tmp_arg != cmd->convert_arg)
2140                         err++;
2141                 if (tmp_arg2 != cmd->scan_begin_arg)
2142                         err++;
2143         }
2144 
2145         if (err)
2146                 return 4;
2147 
2148         /* Step 5: check channel list if it exists */
2149         if (cmd->chanlist && cmd->chanlist_len > 0)
2150                 err |= cb_pcidas64_ai_check_chanlist(dev, s, cmd);
2151 
2152         if (err)
2153                 return 5;
2154 
2155         return 0;
2156 }
2157 
2158 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2159 {
2160 /* disable for now until I work out a race */
2161         return 0;
2162 
2163         if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2164                 return 1;
2165         else
2166                 return 0;
2167 }
2168 
2169 static void setup_sample_counters(struct comedi_device *dev,
2170                                   struct comedi_cmd *cmd)
2171 {
2172         struct pcidas64_private *devpriv = dev->private;
2173 
2174         if (cmd->stop_src == TRIG_COUNT) {
2175                 /*  set software count */
2176                 devpriv->ai_count = cmd->stop_arg * cmd->chanlist_len;
2177         }
2178         /*  load hardware conversion counter */
2179         if (use_hw_sample_counter(cmd)) {
2180                 writew(cmd->stop_arg & 0xffff,
2181                        devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2182                 writew((cmd->stop_arg >> 16) & 0xff,
2183                        devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2184         } else {
2185                 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2186         }
2187 }
2188 
2189 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2190 {
2191         const struct pcidas64_board *thisboard = comedi_board(dev);
2192         struct pcidas64_private *devpriv = dev->private;
2193         unsigned int num_samples;
2194 
2195         num_samples = devpriv->ai_fifo_segment_length *
2196                       thisboard->ai_fifo->sample_packing_ratio;
2197         if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2198                 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2199 
2200         return num_samples;
2201 }
2202 
2203 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2204                                         const struct comedi_cmd *cmd)
2205 {
2206         /*  supposed to load counter with desired divisor minus 3 */
2207         return cmd->convert_arg / TIMER_BASE - 3;
2208 }
2209 
2210 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2211                                      struct comedi_cmd *cmd)
2212 {
2213         uint32_t count;
2214 
2215         /*  figure out how long we need to delay at end of scan */
2216         switch (cmd->scan_begin_src) {
2217         case TRIG_TIMER:
2218                 count = (cmd->scan_begin_arg -
2219                          (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2220                         TIMER_BASE;
2221                 break;
2222         case TRIG_FOLLOW:
2223                 count = cmd->convert_arg / TIMER_BASE;
2224                 break;
2225         default:
2226                 return 0;
2227                 break;
2228         }
2229         return count - 3;
2230 }
2231 
2232 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2233                                         struct comedi_cmd *cmd)
2234 {
2235         struct pcidas64_private *devpriv = dev->private;
2236         unsigned int divisor;
2237 
2238         switch (cmd->scan_begin_src) {
2239         case TRIG_TIMER:
2240                 divisor = cmd->scan_begin_arg / TIMER_BASE;
2241                 break;
2242         case TRIG_OTHER:
2243                 divisor = devpriv->ext_clock.divisor;
2244                 break;
2245         default:                /*  should never happen */
2246                 comedi_error(dev, "bug! failed to set ai pacing!");
2247                 divisor = 1000;
2248                 break;
2249         }
2250 
2251         /*  supposed to load counter with desired divisor minus 2 for 4020 */
2252         return divisor - 2;
2253 }
2254 
2255 static void select_master_clock_4020(struct comedi_device *dev,
2256                                      const struct comedi_cmd *cmd)
2257 {
2258         struct pcidas64_private *devpriv = dev->private;
2259 
2260         /*  select internal/external master clock */
2261         devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2262         if (cmd->scan_begin_src == TRIG_OTHER) {
2263                 int chanspec = devpriv->ext_clock.chanspec;
2264 
2265                 if (CR_CHAN(chanspec))
2266                         devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2267                 else
2268                         devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2269         } else {
2270                 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2271         }
2272         writew(devpriv->hw_config_bits,
2273                devpriv->main_iobase + HW_CONFIG_REG);
2274 }
2275 
2276 static void select_master_clock(struct comedi_device *dev,
2277                                 const struct comedi_cmd *cmd)
2278 {
2279         const struct pcidas64_board *thisboard = comedi_board(dev);
2280 
2281         switch (thisboard->layout) {
2282         case LAYOUT_4020:
2283                 select_master_clock_4020(dev, cmd);
2284                 break;
2285         default:
2286                 break;
2287         }
2288 }
2289 
2290 static inline void dma_start_sync(struct comedi_device *dev,
2291                                   unsigned int channel)
2292 {
2293         struct pcidas64_private *devpriv = dev->private;
2294         unsigned long flags;
2295 
2296         /*  spinlock for plx dma control/status reg */
2297         spin_lock_irqsave(&dev->spinlock, flags);
2298         if (channel)
2299                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2300                        PLX_CLEAR_DMA_INTR_BIT,
2301                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2302         else
2303                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2304                        PLX_CLEAR_DMA_INTR_BIT,
2305                        devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2306         spin_unlock_irqrestore(&dev->spinlock, flags);
2307 }
2308 
2309 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2310 {
2311         const struct pcidas64_board *thisboard = comedi_board(dev);
2312         struct pcidas64_private *devpriv = dev->private;
2313         uint32_t convert_counter = 0, scan_counter = 0;
2314 
2315         check_adc_timing(dev, cmd);
2316 
2317         select_master_clock(dev, cmd);
2318 
2319         if (thisboard->layout == LAYOUT_4020) {
2320                 convert_counter = ai_convert_counter_4020(dev, cmd);
2321         } else {
2322                 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2323                 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2324         }
2325 
2326         /*  load lower 16 bits of convert interval */
2327         writew(convert_counter & 0xffff,
2328                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2329         /*  load upper 8 bits of convert interval */
2330         writew((convert_counter >> 16) & 0xff,
2331                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2332         /*  load lower 16 bits of scan delay */
2333         writew(scan_counter & 0xffff,
2334                devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2335         /*  load upper 8 bits of scan delay */
2336         writew((scan_counter >> 16) & 0xff,
2337                devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2338 }
2339 
2340 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2341 {
2342         int i;
2343 
2344         for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2345                 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2346                     CR_CHAN(cmd->chanlist[i]) + 1)
2347                         return 0;
2348                 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2349                     CR_RANGE(cmd->chanlist[i]))
2350                         return 0;
2351                 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2352                         return 0;
2353         }
2354         return 1;
2355 }
2356 
2357 static int setup_channel_queue(struct comedi_device *dev,
2358                                const struct comedi_cmd *cmd)
2359 {
2360         const struct pcidas64_board *thisboard = comedi_board(dev);
2361         struct pcidas64_private *devpriv = dev->private;
2362         unsigned short bits;
2363         int i;
2364 
2365         if (thisboard->layout != LAYOUT_4020) {
2366                 if (use_internal_queue_6xxx(cmd)) {
2367                         devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2368                         writew(devpriv->hw_config_bits,
2369                                devpriv->main_iobase + HW_CONFIG_REG);
2370                         bits = 0;
2371                         /*  set channel */
2372                         bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2373                         /*  set gain */
2374                         bits |= ai_range_bits_6xxx(dev,
2375                                                    CR_RANGE(cmd->chanlist[0]));
2376                         /*  set single-ended / differential */
2377                         bits |= se_diff_bit_6xxx(dev,
2378                                                  CR_AREF(cmd->chanlist[0]) ==
2379                                                  AREF_DIFF);
2380                         if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2381                                 bits |= ADC_COMMON_BIT;
2382                         /*  set stop channel */
2383                         writew(adc_chan_bits
2384                                (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2385                                devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2386                         /*  set start channel, and rest of settings */
2387                         writew(bits,
2388                                devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2389                 } else {
2390                         /*  use external queue */
2391                         if (dev->write_subdev && dev->write_subdev->busy) {
2392                                 warn_external_queue(dev);
2393                                 return -EBUSY;
2394                         }
2395                         devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2396                         writew(devpriv->hw_config_bits,
2397                                devpriv->main_iobase + HW_CONFIG_REG);
2398                         /*  clear DAC buffer to prevent weird interactions */
2399                         writew(0,
2400                                devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2401                         /*  clear queue pointer */
2402                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2403                         /*  load external queue */
2404                         for (i = 0; i < cmd->chanlist_len; i++) {
2405                                 bits = 0;
2406                                 /*  set channel */
2407                                 bits |= adc_chan_bits(CR_CHAN(cmd->
2408                                                               chanlist[i]));
2409                                 /*  set gain */
2410                                 bits |= ai_range_bits_6xxx(dev,
2411                                                            CR_RANGE(cmd->
2412                                                                     chanlist
2413                                                                     [i]));
2414                                 /*  set single-ended / differential */
2415                                 bits |= se_diff_bit_6xxx(dev,
2416                                                          CR_AREF(cmd->
2417                                                                  chanlist[i]) ==
2418                                                          AREF_DIFF);
2419                                 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2420                                         bits |= ADC_COMMON_BIT;
2421                                 /*  mark end of queue */
2422                                 if (i == cmd->chanlist_len - 1)
2423                                         bits |= QUEUE_EOSCAN_BIT |
2424                                                 QUEUE_EOSEQ_BIT;
2425                                 writew(bits,
2426                                        devpriv->main_iobase +
2427                                        ADC_QUEUE_FIFO_REG);
2428                         }
2429                         /* doing a queue clear is not specified in board docs,
2430                          * but required for reliable operation */
2431                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2432                         /*  prime queue holding register */
2433                         writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2434                 }
2435         } else {
2436                 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2437 
2438                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2439                 /* select BNC inputs */
2440                 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2441                 /*  select ranges */
2442                 for (i = 0; i < cmd->chanlist_len; i++) {
2443                         unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2444                         unsigned int range = CR_RANGE(cmd->chanlist[i]);
2445 
2446                         if (range == 0)
2447                                 devpriv->i2c_cal_range_bits |=
2448                                         attenuate_bit(channel);
2449                         else
2450                                 devpriv->i2c_cal_range_bits &=
2451                                         ~attenuate_bit(channel);
2452                 }
2453                 /*  update calibration/range i2c register only if necessary,
2454                  *  as it is very slow */
2455                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2456                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2457                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2458                                   sizeof(i2c_data));
2459                 }
2460         }
2461         return 0;
2462 }
2463 
2464 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2465                                              unsigned int dma_channel,
2466                                              unsigned int descriptor_bits)
2467 {
2468         struct pcidas64_private *devpriv = dev->private;
2469 
2470         /* The transfer size, pci address, and local address registers
2471          * are supposedly unused during chained dma,
2472          * but I have found that left over values from last operation
2473          * occasionally cause problems with transfer of first dma
2474          * block.  Initializing them to zero seems to fix the problem. */
2475         if (dma_channel) {
2476                 writel(0,
2477                        devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2478                 writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2479                 writel(0,
2480                        devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2481                 writel(descriptor_bits,
2482                        devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2483         } else {
2484                 writel(0,
2485                        devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2486                 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2487                 writel(0,
2488                        devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2489                 writel(descriptor_bits,
2490                        devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2491         }
2492 }
2493 
2494 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2495 {
2496         const struct pcidas64_board *thisboard = comedi_board(dev);
2497         struct pcidas64_private *devpriv = dev->private;
2498         struct comedi_async *async = s->async;
2499         struct comedi_cmd *cmd = &async->cmd;
2500         uint32_t bits;
2501         unsigned int i;
2502         unsigned long flags;
2503         int retval;
2504 
2505         disable_ai_pacing(dev);
2506         abort_dma(dev, 1);
2507 
2508         retval = setup_channel_queue(dev, cmd);
2509         if (retval < 0)
2510                 return retval;
2511 
2512         /*  make sure internal calibration source is turned off */
2513         writew(0, devpriv->main_iobase + CALIBRATION_REG);
2514 
2515         set_ai_pacing(dev, cmd);
2516 
2517         setup_sample_counters(dev, cmd);
2518 
2519         enable_ai_interrupts(dev, cmd);
2520 
2521         spin_lock_irqsave(&dev->spinlock, flags);
2522         /* set mode, allow conversions through software gate */
2523         devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2524         devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2525         if (thisboard->layout != LAYOUT_4020) {
2526                 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2527                 if (cmd->convert_src == TRIG_EXT)
2528                         /*  good old mode 13 */
2529                         devpriv->adc_control1_bits |= adc_mode_bits(13);
2530                 else
2531                         /*  mode 8.  What else could you need? */
2532                         devpriv->adc_control1_bits |= adc_mode_bits(8);
2533         } else {
2534                 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2535                 if (cmd->chanlist_len == 4)
2536                         devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2537                 else if (cmd->chanlist_len == 2)
2538                         devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2539                 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2540                 devpriv->adc_control1_bits |=
2541                         adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2542                 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2543                 devpriv->adc_control1_bits |=
2544                         adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2545                                                       [cmd->chanlist_len - 1]));
2546         }
2547         writew(devpriv->adc_control1_bits,
2548                devpriv->main_iobase + ADC_CONTROL1_REG);
2549         spin_unlock_irqrestore(&dev->spinlock, flags);
2550 
2551         /*  clear adc buffer */
2552         writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2553 
2554         if ((cmd->flags & TRIG_WAKE_EOS) == 0 ||
2555             thisboard->layout == LAYOUT_4020) {
2556                 devpriv->ai_dma_index = 0;
2557 
2558                 /*  set dma transfer size */
2559                 for (i = 0; i < ai_dma_ring_count(thisboard); i++)
2560                         devpriv->ai_dma_desc[i].transfer_size =
2561                                 cpu_to_le32(dma_transfer_size(dev) *
2562                                             sizeof(uint16_t));
2563 
2564                 /*  give location of first dma descriptor */
2565                 load_first_dma_descriptor(dev, 1,
2566                                           devpriv->ai_dma_desc_bus_addr |
2567                                           PLX_DESC_IN_PCI_BIT |
2568                                           PLX_INTR_TERM_COUNT |
2569                                           PLX_XFER_LOCAL_TO_PCI);
2570 
2571                 dma_start_sync(dev, 1);
2572         }
2573 
2574         if (thisboard->layout == LAYOUT_4020) {
2575                 /* set source for external triggers */
2576                 bits = 0;
2577                 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2578                         bits |= EXT_START_TRIG_BNC_BIT;
2579                 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2580                         bits |= EXT_STOP_TRIG_BNC_BIT;
2581                 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2582         }
2583 
2584         spin_lock_irqsave(&dev->spinlock, flags);
2585 
2586         /* enable pacing, triggering, etc */
2587         bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2588         if (cmd->flags & TRIG_WAKE_EOS)
2589                 bits |= ADC_DMA_DISABLE_BIT;
2590         /*  set start trigger */
2591         if (cmd->start_src == TRIG_EXT) {
2592                 bits |= ADC_START_TRIG_EXT_BITS;
2593                 if (cmd->start_arg & CR_INVERT)
2594                         bits |= ADC_START_TRIG_FALLING_BIT;
2595         } else if (cmd->start_src == TRIG_NOW)
2596                 bits |= ADC_START_TRIG_SOFT_BITS;
2597         if (use_hw_sample_counter(cmd))
2598                 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2599         writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2600 
2601         devpriv->ai_cmd_running = 1;
2602 
2603         spin_unlock_irqrestore(&dev->spinlock, flags);
2604 
2605         /*  start acquisition */
2606         if (cmd->start_src == TRIG_NOW)
2607                 writew(0, devpriv->main_iobase + ADC_START_REG);
2608 
2609         return 0;
2610 }
2611 
2612 /* read num_samples from 16 bit wide ai fifo */
2613 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2614 {
2615         struct pcidas64_private *devpriv = dev->private;
2616         struct comedi_subdevice *s = dev->read_subdev;
2617         struct comedi_async *async = s->async;
2618         struct comedi_cmd *cmd = &async->cmd;
2619         unsigned int i;
2620         uint16_t prepost_bits;
2621         int read_segment, read_index, write_segment, write_index;
2622         int num_samples;
2623 
2624         do {
2625                 /*  get least significant 15 bits */
2626                 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2627                              0x7fff;
2628                 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2629                               0x7fff;
2630                 /* Get most significant bits (grey code).
2631                  * Different boards use different code so use a scheme
2632                  * that doesn't depend on encoding.  This read must
2633                  * occur after reading least significant 15 bits to avoid race
2634                  * with fifo switching to next segment. */
2635                 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2636 
2637                 /* if read and write pointers are not on the same fifo segment,
2638                  * read to the end of the read segment */
2639                 read_segment = adc_upper_read_ptr_code(prepost_bits);
2640                 write_segment = adc_upper_write_ptr_code(prepost_bits);
2641 
2642                 if (read_segment != write_segment)
2643                         num_samples =
2644                                 devpriv->ai_fifo_segment_length - read_index;
2645                 else
2646                         num_samples = write_index - read_index;
2647 
2648                 if (cmd->stop_src == TRIG_COUNT) {
2649                         if (devpriv->ai_count == 0)
2650                                 break;
2651                         if (num_samples > devpriv->ai_count)
2652                                 num_samples = devpriv->ai_count;
2653 
2654                         devpriv->ai_count -= num_samples;
2655                 }
2656 
2657                 if (num_samples < 0) {
2658                         dev_err(dev->class_dev,
2659                                 "cb_pcidas64: bug! num_samples < 0\n");
2660                         break;
2661                 }
2662 
2663                 for (i = 0; i < num_samples; i++) {
2664                         cfc_write_to_buffer(s,
2665                                             readw(devpriv->main_iobase +
2666                                                   ADC_FIFO_REG));
2667                 }
2668 
2669         } while (read_segment != write_segment);
2670 }
2671 
2672 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2673  * pointers.  The pci-4020 hardware only supports dma transfers (it only
2674  * supports the use of pio for draining the last remaining points from the
2675  * fifo when a data acquisition operation has completed).
2676  */
2677 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2678 {
2679         struct pcidas64_private *devpriv = dev->private;
2680         struct comedi_subdevice *s = dev->read_subdev;
2681         struct comedi_async *async = s->async;
2682         struct comedi_cmd *cmd = &async->cmd;
2683         unsigned int i;
2684         unsigned int max_transfer = 100000;
2685         uint32_t fifo_data;
2686         int write_code =
2687                 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2688         int read_code =
2689                 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2690 
2691         if (cmd->stop_src == TRIG_COUNT) {
2692                 if (max_transfer > devpriv->ai_count)
2693                         max_transfer = devpriv->ai_count;
2694 
2695         }
2696         for (i = 0; read_code != write_code && i < max_transfer;) {
2697                 fifo_data = readl(devpriv->dio_counter_iobase + ADC_FIFO_REG);
2698                 cfc_write_to_buffer(s, fifo_data & 0xffff);
2699                 i++;
2700                 if (i < max_transfer) {
2701                         cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2702                         i++;
2703                 }
2704                 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2705                             0x7fff;
2706         }
2707         devpriv->ai_count -= i;
2708 }
2709 
2710 /* empty fifo */
2711 static void pio_drain_ai_fifo(struct comedi_device *dev)
2712 {
2713         const struct pcidas64_board *thisboard = comedi_board(dev);
2714 
2715         if (thisboard->layout == LAYOUT_4020)
2716                 pio_drain_ai_fifo_32(dev);
2717         else
2718                 pio_drain_ai_fifo_16(dev);
2719 }
2720 
2721 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2722 {
2723         const struct pcidas64_board *thisboard = comedi_board(dev);
2724         struct pcidas64_private *devpriv = dev->private;
2725         struct comedi_async *async = dev->read_subdev->async;
2726         struct comedi_cmd *cmd = &async->cmd;
2727         uint32_t next_transfer_addr;
2728         int j;
2729         int num_samples = 0;
2730         void __iomem *pci_addr_reg;
2731 
2732         if (channel)
2733                 pci_addr_reg =
2734                     devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2735         else
2736                 pci_addr_reg =
2737                     devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2738 
2739         /*  loop until we have read all the full buffers */
2740         for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2741              (next_transfer_addr <
2742               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2743               next_transfer_addr >=
2744               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2745               DMA_BUFFER_SIZE) && j < ai_dma_ring_count(thisboard); j++) {
2746                 /*  transfer data from dma buffer to comedi buffer */
2747                 num_samples = dma_transfer_size(dev);
2748                 if (cmd->stop_src == TRIG_COUNT) {
2749                         if (num_samples > devpriv->ai_count)
2750                                 num_samples = devpriv->ai_count;
2751                         devpriv->ai_count -= num_samples;
2752                 }
2753                 cfc_write_array_to_buffer(dev->read_subdev,
2754                                           devpriv->ai_buffer[devpriv->
2755                                                              ai_dma_index],
2756                                           num_samples * sizeof(uint16_t));
2757                 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2758                                         ai_dma_ring_count(thisboard);
2759         }
2760         /* XXX check for dma ring buffer overrun
2761          * (use end-of-chain bit to mark last unused buffer) */
2762 }
2763 
2764 static void handle_ai_interrupt(struct comedi_device *dev,
2765                                 unsigned short status,
2766                                 unsigned int plx_status)
2767 {
2768         const struct pcidas64_board *thisboard = comedi_board(dev);
2769         struct pcidas64_private *devpriv = dev->private;
2770         struct comedi_subdevice *s = dev->read_subdev;
2771         struct comedi_async *async = s->async;
2772         struct comedi_cmd *cmd = &async->cmd;
2773         uint8_t dma1_status;
2774         unsigned long flags;
2775 
2776         /*  check for fifo overrun */
2777         if (status & ADC_OVERRUN_BIT) {
2778                 comedi_error(dev, "fifo overrun");
2779                 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2780         }
2781         /*  spin lock makes sure no one else changes plx dma control reg */
2782         spin_lock_irqsave(&dev->spinlock, flags);
2783         dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2784         if (plx_status & ICS_DMA1_A) {  /*  dma chan 1 interrupt */
2785                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2786                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2787 
2788                 if (dma1_status & PLX_DMA_EN_BIT)
2789                         drain_dma_buffers(dev, 1);
2790         }
2791         spin_unlock_irqrestore(&dev->spinlock, flags);
2792 
2793         /*  drain fifo with pio */
2794         if ((status & ADC_DONE_BIT) ||
2795             ((cmd->flags & TRIG_WAKE_EOS) &&
2796              (status & ADC_INTR_PENDING_BIT) &&
2797              (thisboard->layout != LAYOUT_4020))) {
2798                 spin_lock_irqsave(&dev->spinlock, flags);
2799                 if (devpriv->ai_cmd_running) {
2800                         spin_unlock_irqrestore(&dev->spinlock, flags);
2801                         pio_drain_ai_fifo(dev);
2802                 } else
2803                         spin_unlock_irqrestore(&dev->spinlock, flags);
2804         }
2805         /*  if we are have all the data, then quit */
2806         if ((cmd->stop_src == TRIG_COUNT && (int)devpriv->ai_count <= 0) ||
2807             (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
2808                 async->events |= COMEDI_CB_EOA;
2809         }
2810 
2811         cfc_handle_events(dev, s);
2812 }
2813 
2814 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2815 {
2816         struct pcidas64_private *devpriv = dev->private;
2817         unsigned int buffer_index;
2818 
2819         if (devpriv->ao_dma_index == 0)
2820                 buffer_index = AO_DMA_RING_COUNT - 1;
2821         else
2822                 buffer_index = devpriv->ao_dma_index - 1;
2823         return buffer_index;
2824 }
2825 
2826 static int last_ao_dma_load_completed(struct comedi_device *dev)
2827 {
2828         struct pcidas64_private *devpriv = dev->private;
2829         unsigned int buffer_index;
2830         unsigned int transfer_address;
2831         unsigned short dma_status;
2832 
2833         buffer_index = prev_ao_dma_index(dev);
2834         dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2835         if ((dma_status & PLX_DMA_DONE_BIT) == 0)
2836                 return 0;
2837 
2838         transfer_address =
2839                 readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2840         if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2841                 return 0;
2842 
2843         return 1;
2844 }
2845 
2846 static int ao_stopped_by_error(struct comedi_device *dev,
2847                                const struct comedi_cmd *cmd)
2848 {
2849         struct pcidas64_private *devpriv = dev->private;
2850 
2851         if (cmd->stop_src == TRIG_NONE)
2852                 return 1;
2853         if (cmd->stop_src == TRIG_COUNT) {
2854                 if (devpriv->ao_count)
2855                         return 1;
2856                 if (last_ao_dma_load_completed(dev) == 0)
2857                         return 1;
2858         }
2859         return 0;
2860 }
2861 
2862 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2863                                        unsigned short dma_status)
2864 {
2865         if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
2866             (dma_status & PLX_DMA_EN_BIT) == 0)
2867                 return 0;
2868         if (last_ao_dma_load_completed(dev))
2869                 return 0;
2870 
2871         return 1;
2872 }
2873 
2874 static void restart_ao_dma(struct comedi_device *dev)
2875 {
2876         struct pcidas64_private *devpriv = dev->private;
2877         unsigned int dma_desc_bits;
2878 
2879         dma_desc_bits =
2880                 readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2881         dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
2882         load_first_dma_descriptor(dev, 0, dma_desc_bits);
2883 
2884         dma_start_sync(dev, 0);
2885 }
2886 
2887 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2888                                        const struct comedi_cmd *cmd)
2889 {
2890         struct pcidas64_private *devpriv = dev->private;
2891         unsigned int num_bytes, buffer_index, prev_buffer_index;
2892         unsigned int next_bits;
2893 
2894         buffer_index = devpriv->ao_dma_index;
2895         prev_buffer_index = prev_ao_dma_index(dev);
2896 
2897         num_bytes = comedi_buf_read_n_available(dev->write_subdev);
2898         if (num_bytes > DMA_BUFFER_SIZE)
2899                 num_bytes = DMA_BUFFER_SIZE;
2900         if (cmd->stop_src == TRIG_COUNT && num_bytes > devpriv->ao_count)
2901                 num_bytes = devpriv->ao_count;
2902         num_bytes -= num_bytes % bytes_in_sample;
2903 
2904         if (num_bytes == 0)
2905                 return 0;
2906 
2907         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
2908                                                devpriv->
2909                                                ao_buffer[buffer_index],
2910                                                num_bytes);
2911         devpriv->ao_dma_desc[buffer_index].transfer_size =
2912                 cpu_to_le32(num_bytes);
2913         /* set end of chain bit so we catch underruns */
2914         next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
2915         next_bits |= PLX_END_OF_CHAIN_BIT;
2916         devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
2917         /* clear end of chain bit on previous buffer now that we have set it
2918          * for the last buffer */
2919         next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
2920         next_bits &= ~PLX_END_OF_CHAIN_BIT;
2921         devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
2922 
2923         devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
2924         devpriv->ao_count -= num_bytes;
2925 
2926         return num_bytes;
2927 }
2928 
2929 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
2930 {
2931         struct pcidas64_private *devpriv = dev->private;
2932         unsigned int num_bytes;
2933         unsigned int next_transfer_addr;
2934         void __iomem *pci_addr_reg =
2935                 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2936         unsigned int buffer_index;
2937 
2938         do {
2939                 buffer_index = devpriv->ao_dma_index;
2940                 /* don't overwrite data that hasn't been transferred yet */
2941                 next_transfer_addr = readl(pci_addr_reg);
2942                 if (next_transfer_addr >=
2943                     devpriv->ao_buffer_bus_addr[buffer_index] &&
2944                     next_transfer_addr <
2945                     devpriv->ao_buffer_bus_addr[buffer_index] +
2946                     DMA_BUFFER_SIZE)
2947                         return;
2948                 num_bytes = load_ao_dma_buffer(dev, cmd);
2949         } while (num_bytes >= DMA_BUFFER_SIZE);
2950 }
2951 
2952 static void handle_ao_interrupt(struct comedi_device *dev,
2953                                 unsigned short status, unsigned int plx_status)
2954 {
2955         struct pcidas64_private *devpriv = dev->private;
2956         struct comedi_subdevice *s = dev->write_subdev;
2957         struct comedi_async *async;
2958         struct comedi_cmd *cmd;
2959         uint8_t dma0_status;
2960         unsigned long flags;
2961 
2962         /* board might not support ao, in which case write_subdev is NULL */
2963         if (s == NULL)
2964                 return;
2965         async = s->async;
2966         cmd = &async->cmd;
2967 
2968         /*  spin lock makes sure no one else changes plx dma control reg */
2969         spin_lock_irqsave(&dev->spinlock, flags);
2970         dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2971         if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
2972                 if ((dma0_status & PLX_DMA_EN_BIT) &&
2973                     !(dma0_status & PLX_DMA_DONE_BIT))
2974                         writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
2975                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2976                 else
2977                         writeb(PLX_CLEAR_DMA_INTR_BIT,
2978                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2979                 spin_unlock_irqrestore(&dev->spinlock, flags);
2980                 if (dma0_status & PLX_DMA_EN_BIT) {
2981                         load_ao_dma(dev, cmd);
2982                         /* try to recover from dma end-of-chain event */
2983                         if (ao_dma_needs_restart(dev, dma0_status))
2984                                 restart_ao_dma(dev);
2985                 }
2986         } else {
2987                 spin_unlock_irqrestore(&dev->spinlock, flags);
2988         }
2989 
2990         if ((status & DAC_DONE_BIT)) {
2991                 async->events |= COMEDI_CB_EOA;
2992                 if (ao_stopped_by_error(dev, cmd))
2993                         async->events |= COMEDI_CB_ERROR;
2994         }
2995         cfc_handle_events(dev, s);
2996 }
2997 
2998 static irqreturn_t handle_interrupt(int irq, void *d)
2999 {
3000         struct comedi_device *dev = d;
3001         struct pcidas64_private *devpriv = dev->private;
3002         unsigned short status;
3003         uint32_t plx_status;
3004         uint32_t plx_bits;
3005 
3006         plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
3007         status = readw(devpriv->main_iobase + HW_STATUS_REG);
3008 
3009         /* an interrupt before all the postconfig stuff gets done could
3010          * cause a NULL dereference if we continue through the
3011          * interrupt handler */
3012         if (!dev->attached)
3013                 return IRQ_HANDLED;
3014 
3015         handle_ai_interrupt(dev, status, plx_status);
3016         handle_ao_interrupt(dev, status, plx_status);
3017 
3018         /*  clear possible plx9080 interrupt sources */
3019         if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
3020                 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3021                 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3022         }
3023 
3024         return IRQ_HANDLED;
3025 }
3026 
3027 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3028 {
3029         struct pcidas64_private *devpriv = dev->private;
3030         unsigned long flags;
3031 
3032         spin_lock_irqsave(&dev->spinlock, flags);
3033         if (devpriv->ai_cmd_running == 0) {
3034                 spin_unlock_irqrestore(&dev->spinlock, flags);
3035                 return 0;
3036         }
3037         devpriv->ai_cmd_running = 0;
3038         spin_unlock_irqrestore(&dev->spinlock, flags);
3039 
3040         disable_ai_pacing(dev);
3041 
3042         abort_dma(dev, 1);
3043 
3044         return 0;
3045 }
3046 
3047 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3048                     struct comedi_insn *insn, unsigned int *data)
3049 {
3050         const struct pcidas64_board *thisboard = comedi_board(dev);
3051         struct pcidas64_private *devpriv = dev->private;
3052         int chan = CR_CHAN(insn->chanspec);
3053         int range = CR_RANGE(insn->chanspec);
3054 
3055         /*  do some initializing */
3056         writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3057 
3058         /*  set range */
3059         set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3060         writew(devpriv->dac_control1_bits,
3061                devpriv->main_iobase + DAC_CONTROL1_REG);
3062 
3063         /*  write to channel */
3064         if (thisboard->layout == LAYOUT_4020) {
3065                 writew(data[0] & 0xff,
3066                        devpriv->main_iobase + dac_lsb_4020_reg(chan));
3067                 writew((data[0] >> 8) & 0xf,
3068                        devpriv->main_iobase + dac_msb_4020_reg(chan));
3069         } else {
3070                 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3071         }
3072 
3073         /*  remember output value */
3074         devpriv->ao_value[chan] = data[0];
3075 
3076         return 1;
3077 }
3078 
3079 static int ao_readback_insn(struct comedi_device *dev,
3080                             struct comedi_subdevice *s,
3081                             struct comedi_insn *insn, unsigned int *data)
3082 {
3083         struct pcidas64_private *devpriv = dev->private;
3084 
3085         data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
3086 
3087         return 1;
3088 }
3089 
3090 static void set_dac_control0_reg(struct comedi_device *dev,
3091                                  const struct comedi_cmd *cmd)
3092 {
3093         struct pcidas64_private *devpriv = dev->private;
3094         unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3095                             WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3096 
3097         if (cmd->start_src == TRIG_EXT) {
3098                 bits |= WAVEFORM_TRIG_EXT_BITS;
3099                 if (cmd->start_arg & CR_INVERT)
3100                         bits |= WAVEFORM_TRIG_FALLING_BIT;
3101         } else {
3102                 bits |= WAVEFORM_TRIG_SOFT_BITS;
3103         }
3104         if (cmd->scan_begin_src == TRIG_EXT) {
3105                 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3106                 if (cmd->scan_begin_arg & CR_INVERT)
3107                         bits |= DAC_EXT_UPDATE_FALLING_BIT;
3108         }
3109         writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3110 }
3111 
3112 static void set_dac_control1_reg(struct comedi_device *dev,
3113                                  const struct comedi_cmd *cmd)
3114 {
3115         struct pcidas64_private *devpriv = dev->private;
3116         int i;
3117 
3118         for (i = 0; i < cmd->chanlist_len; i++) {
3119                 int channel, range;
3120 
3121                 channel = CR_CHAN(cmd->chanlist[i]);
3122                 range = CR_RANGE(cmd->chanlist[i]);
3123                 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3124                                    range);
3125         }
3126         devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3127         writew(devpriv->dac_control1_bits,
3128                devpriv->main_iobase + DAC_CONTROL1_REG);
3129 }
3130 
3131 static void set_dac_select_reg(struct comedi_device *dev,
3132                                const struct comedi_cmd *cmd)
3133 {
3134         struct pcidas64_private *devpriv = dev->private;
3135         uint16_t bits;
3136         unsigned int first_channel, last_channel;
3137 
3138         first_channel = CR_CHAN(cmd->chanlist[0]);
3139         last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3140         if (last_channel < first_channel)
3141                 comedi_error(dev, "bug! last ao channel < first ao channel");
3142 
3143         bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3144 
3145         writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3146 }
3147 
3148 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3149 {
3150         return get_divisor(ns, flags) - 2;
3151 }
3152 
3153 static void set_dac_interval_regs(struct comedi_device *dev,
3154                                   const struct comedi_cmd *cmd)
3155 {
3156         struct pcidas64_private *devpriv = dev->private;
3157         unsigned int divisor;
3158 
3159         if (cmd->scan_begin_src != TRIG_TIMER)
3160                 return;
3161 
3162         divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3163         if (divisor > max_counter_value) {
3164                 comedi_error(dev, "bug! ao divisor too big");
3165                 divisor = max_counter_value;
3166         }
3167         writew(divisor & 0xffff,
3168                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3169         writew((divisor >> 16) & 0xff,
3170                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3171 }
3172 
3173 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3174 {
3175         struct pcidas64_private *devpriv = dev->private;
3176         unsigned int num_bytes;
3177         int i;
3178 
3179         /* clear queue pointer too, since external queue has
3180          * weird interactions with ao fifo */
3181         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3182         writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3183 
3184         num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample;
3185         if (cmd->stop_src == TRIG_COUNT &&
3186             num_bytes / bytes_in_sample > devpriv->ao_count)
3187                 num_bytes = devpriv->ao_count * bytes_in_sample;
3188         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3189                                                devpriv->ao_bounce_buffer,
3190                                                num_bytes);
3191         for (i = 0; i < num_bytes / bytes_in_sample; i++) {
3192                 writew(devpriv->ao_bounce_buffer[i],
3193                        devpriv->main_iobase + DAC_FIFO_REG);
3194         }
3195         devpriv->ao_count -= num_bytes / bytes_in_sample;
3196         if (cmd->stop_src == TRIG_COUNT && devpriv->ao_count == 0)
3197                 return 0;
3198         num_bytes = load_ao_dma_buffer(dev, cmd);
3199         if (num_bytes == 0)
3200                 return -1;
3201         load_ao_dma(dev, cmd);
3202 
3203         dma_start_sync(dev, 0);
3204 
3205         return 0;
3206 }
3207 
3208 static inline int external_ai_queue_in_use(struct comedi_device *dev,
3209                                            struct comedi_subdevice *s,
3210                                            struct comedi_cmd *cmd)
3211 {
3212         const struct pcidas64_board *thisboard = comedi_board(dev);
3213 
3214         if (s->busy)
3215                 return 0;
3216         if (thisboard->layout == LAYOUT_4020)
3217                 return 0;
3218         else if (use_internal_queue_6xxx(cmd))
3219                 return 0;
3220         return 1;
3221 }
3222 
3223 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3224                       unsigned int trig_num)
3225 {
3226         struct pcidas64_private *devpriv = dev->private;
3227         struct comedi_cmd *cmd = &s->async->cmd;
3228         int retval;
3229 
3230         if (trig_num != cmd->start_arg)
3231                 return -EINVAL;
3232 
3233         retval = prep_ao_dma(dev, cmd);
3234         if (retval < 0)
3235                 return -EPIPE;
3236 
3237         set_dac_control0_reg(dev, cmd);
3238 
3239         if (cmd->start_src == TRIG_INT)
3240                 writew(0, devpriv->main_iobase + DAC_START_REG);
3241 
3242         s->async->inttrig = NULL;
3243 
3244         return 0;
3245 }
3246 
3247 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3248 {
3249         struct pcidas64_private *devpriv = dev->private;
3250         struct comedi_cmd *cmd = &s->async->cmd;
3251 
3252         if (external_ai_queue_in_use(dev, s, cmd)) {
3253                 warn_external_queue(dev);
3254                 return -EBUSY;
3255         }
3256         /* disable analog output system during setup */
3257         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3258 
3259         devpriv->ao_dma_index = 0;
3260         devpriv->ao_count = cmd->stop_arg * cmd->chanlist_len;
3261 
3262         set_dac_select_reg(dev, cmd);
3263         set_dac_interval_regs(dev, cmd);
3264         load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3265                                   PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3266 
3267         set_dac_control1_reg(dev, cmd);
3268         s->async->inttrig = ao_inttrig;
3269 
3270         return 0;
3271 }
3272 
3273 static int cb_pcidas64_ao_check_chanlist(struct comedi_device *dev,
3274                                          struct comedi_subdevice *s,
3275                                          struct comedi_cmd *cmd)
3276 {
3277         unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
3278         int i;
3279 
3280         for (i = 1; i < cmd->chanlist_len; i++) {
3281                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3282 
3283                 if (chan != (chan0 + i)) {
3284                         dev_dbg(dev->class_dev,
3285                                 "chanlist must use consecutive channels\n");
3286                         return -EINVAL;
3287                 }
3288         }
3289 
3290         return 0;
3291 }
3292 
3293 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3294                       struct comedi_cmd *cmd)
3295 {
3296         const struct pcidas64_board *thisboard = comedi_board(dev);
3297         int err = 0;
3298         unsigned int tmp_arg;
3299 
3300         /* Step 1 : check if triggers are trivially valid */
3301 
3302         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3303         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3304                                      TRIG_TIMER | TRIG_EXT);
3305         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3306         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3307         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3308 
3309         if (err)
3310                 return 1;
3311 
3312         /* Step 2a : make sure trigger sources are unique */
3313 
3314         err |= cfc_check_trigger_is_unique(cmd->start_src);
3315         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3316 
3317         /* Step 2b : and mutually compatible */
3318 
3319         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3320                 err |= -EINVAL;
3321         if (cmd->stop_src != TRIG_COUNT &&
3322             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3323                 err |= -EINVAL;
3324 
3325         if (err)
3326                 return 2;
3327 
3328         /* Step 3: check if arguments are trivially valid */
3329 
3330         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3331 
3332         if (cmd->scan_begin_src == TRIG_TIMER) {
3333                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3334                                                  thisboard->ao_scan_speed);
3335                 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3336                     max_counter_value) {
3337                         cmd->scan_begin_arg = (max_counter_value + 2) *
3338                                               TIMER_BASE;
3339                         err |= -EINVAL;
3340                 }
3341         }
3342 
3343         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
3344         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3345 
3346         if (err)
3347                 return 3;
3348 
3349         /* step 4: fix up any arguments */
3350 
3351         if (cmd->scan_begin_src == TRIG_TIMER) {
3352                 tmp_arg = cmd->scan_begin_arg;
3353                 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3354                                                   cmd->flags) * TIMER_BASE;
3355                 if (tmp_arg != cmd->scan_begin_arg)
3356                         err++;
3357         }
3358 
3359         if (err)
3360                 return 4;
3361 
3362         /* Step 5: check channel list if it exists */
3363         if (cmd->chanlist && cmd->chanlist_len > 0)
3364                 err |= cb_pcidas64_ao_check_chanlist(dev, s, cmd);
3365 
3366         if (err)
3367                 return 5;
3368 
3369         return 0;
3370 }
3371 
3372 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3373 {
3374         struct pcidas64_private *devpriv = dev->private;
3375 
3376         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3377         abort_dma(dev, 0);
3378         return 0;
3379 }
3380 
3381 static int dio_callback(int dir, int port, int data, unsigned long arg)
3382 {
3383         void __iomem *iobase = (void __iomem *)arg;
3384         if (dir) {
3385                 writeb(data, iobase + port);
3386                 return 0;
3387         } else {
3388                 return readb(iobase + port);
3389         }
3390 }
3391 
3392 static int dio_callback_4020(int dir, int port, int data, unsigned long arg)
3393 {
3394         void __iomem *iobase = (void __iomem *)arg;
3395         if (dir) {
3396                 writew(data, iobase + 2 * port);
3397                 return 0;
3398         } else {
3399                 return readw(iobase + 2 * port);
3400         }
3401 }
3402 
3403 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3404                     struct comedi_insn *insn, unsigned int *data)
3405 {
3406         struct pcidas64_private *devpriv = dev->private;
3407         unsigned int bits;
3408 
3409         bits = readb(devpriv->dio_counter_iobase + DI_REG);
3410         bits &= 0xf;
3411         data[1] = bits;
3412         data[0] = 0;
3413 
3414         return insn->n;
3415 }
3416 
3417 static int do_wbits(struct comedi_device *dev,
3418                     struct comedi_subdevice *s,
3419                     struct comedi_insn *insn,
3420                     unsigned int *data)
3421 {
3422         struct pcidas64_private *devpriv = dev->private;
3423 
3424         if (comedi_dio_update_state(s, data))
3425                 writeb(s->state, devpriv->dio_counter_iobase + DO_REG);
3426 
3427         data[1] = s->state;
3428 
3429         return insn->n;
3430 }
3431 
3432 static int dio_60xx_config_insn(struct comedi_device *dev,
3433                                 struct comedi_subdevice *s,
3434                                 struct comedi_insn *insn,
3435                                 unsigned int *data)
3436 {
3437         struct pcidas64_private *devpriv = dev->private;
3438         int ret;
3439 
3440         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3441         if (ret)
3442                 return ret;
3443 
3444         writeb(s->io_bits,
3445                devpriv->dio_counter_iobase + DIO_DIRECTION_60XX_REG);
3446 
3447         return insn->n;
3448 }
3449 
3450 static int dio_60xx_wbits(struct comedi_device *dev,
3451                           struct comedi_subdevice *s,
3452                           struct comedi_insn *insn,
3453                           unsigned int *data)
3454 {
3455         struct pcidas64_private *devpriv = dev->private;
3456 
3457         if (comedi_dio_update_state(s, data)) {
3458                 writeb(s->state,
3459                        devpriv->dio_counter_iobase + DIO_DATA_60XX_REG);
3460         }
3461 
3462         data[1] = readb(devpriv->dio_counter_iobase + DIO_DATA_60XX_REG);
3463 
3464         return insn->n;
3465 }
3466 
3467 /* pci-6025 8800 caldac:
3468  * address 0 == dac channel 0 offset
3469  * address 1 == dac channel 0 gain
3470  * address 2 == dac channel 1 offset
3471  * address 3 == dac channel 1 gain
3472  * address 4 == fine adc offset
3473  * address 5 == coarse adc offset
3474  * address 6 == coarse adc gain
3475  * address 7 == fine adc gain
3476  */
3477 /* pci-6402/16 uses all 8 channels for dac:
3478  * address 0 == dac channel 0 fine gain
3479  * address 1 == dac channel 0 coarse gain
3480  * address 2 == dac channel 0 coarse offset
3481  * address 3 == dac channel 1 coarse offset
3482  * address 4 == dac channel 1 fine gain
3483  * address 5 == dac channel 1 coarse gain
3484  * address 6 == dac channel 0 fine offset
3485  * address 7 == dac channel 1 fine offset
3486 */
3487 
3488 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3489                              uint8_t value)
3490 {
3491         struct pcidas64_private *devpriv = dev->private;
3492         static const int num_caldac_channels = 8;
3493         static const int bitstream_length = 11;
3494         unsigned int bitstream = ((address & 0x7) << 8) | value;
3495         unsigned int bit, register_bits;
3496         static const int caldac_8800_udelay = 1;
3497 
3498         if (address >= num_caldac_channels) {
3499                 comedi_error(dev, "illegal caldac channel");
3500                 return -1;
3501         }
3502         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3503                 register_bits = 0;
3504                 if (bitstream & bit)
3505                         register_bits |= SERIAL_DATA_IN_BIT;
3506                 udelay(caldac_8800_udelay);
3507                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3508                 register_bits |= SERIAL_CLOCK_BIT;
3509                 udelay(caldac_8800_udelay);
3510                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3511         }
3512         udelay(caldac_8800_udelay);
3513         writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3514         udelay(caldac_8800_udelay);
3515         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3516         udelay(caldac_8800_udelay);
3517         return 0;
3518 }
3519 
3520 /* 4020 caldacs */
3521 static int caldac_i2c_write(struct comedi_device *dev,
3522                             unsigned int caldac_channel, unsigned int value)
3523 {
3524         uint8_t serial_bytes[3];
3525         uint8_t i2c_addr;
3526         enum pointer_bits {
3527                 /*  manual has gain and offset bits switched */
3528                 OFFSET_0_2 = 0x1,
3529                 GAIN_0_2 = 0x2,
3530                 OFFSET_1_3 = 0x4,
3531                 GAIN_1_3 = 0x8,
3532         };
3533         enum data_bits {
3534                 NOT_CLEAR_REGISTERS = 0x20,
3535         };
3536 
3537         switch (caldac_channel) {
3538         case 0:         /*  chan 0 offset */
3539                 i2c_addr = CALDAC0_I2C_ADDR;
3540                 serial_bytes[0] = OFFSET_0_2;
3541                 break;
3542         case 1:         /*  chan 1 offset */
3543                 i2c_addr = CALDAC0_I2C_ADDR;
3544                 serial_bytes[0] = OFFSET_1_3;
3545                 break;
3546         case 2:         /*  chan 2 offset */
3547                 i2c_addr = CALDAC1_I2C_ADDR;
3548                 serial_bytes[0] = OFFSET_0_2;
3549                 break;
3550         case 3:         /*  chan 3 offset */
3551                 i2c_addr = CALDAC1_I2C_ADDR;
3552                 serial_bytes[0] = OFFSET_1_3;
3553                 break;
3554         case 4:         /*  chan 0 gain */
3555                 i2c_addr = CALDAC0_I2C_ADDR;
3556                 serial_bytes[0] = GAIN_0_2;
3557                 break;
3558         case 5:         /*  chan 1 gain */
3559                 i2c_addr = CALDAC0_I2C_ADDR;
3560                 serial_bytes[0] = GAIN_1_3;
3561                 break;
3562         case 6:         /*  chan 2 gain */
3563                 i2c_addr = CALDAC1_I2C_ADDR;
3564                 serial_bytes[0] = GAIN_0_2;
3565                 break;
3566         case 7:         /*  chan 3 gain */
3567                 i2c_addr = CALDAC1_I2C_ADDR;
3568                 serial_bytes[0] = GAIN_1_3;
3569                 break;
3570         default:
3571                 comedi_error(dev, "invalid caldac channel\n");
3572                 return -1;
3573                 break;
3574         }
3575         serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3576         serial_bytes[2] = value & 0xff;
3577         i2c_write(dev, i2c_addr, serial_bytes, 3);
3578         return 0;
3579 }
3580 
3581 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3582                          unsigned int value)
3583 {
3584         const struct pcidas64_board *thisboard = comedi_board(dev);
3585         struct pcidas64_private *devpriv = dev->private;
3586 
3587         devpriv->caldac_state[channel] = value;
3588 
3589         switch (thisboard->layout) {
3590         case LAYOUT_60XX:
3591         case LAYOUT_64XX:
3592                 caldac_8800_write(dev, channel, value);
3593                 break;
3594         case LAYOUT_4020:
3595                 caldac_i2c_write(dev, channel, value);
3596                 break;
3597         default:
3598                 break;
3599         }
3600 }
3601 
3602 static int calib_write_insn(struct comedi_device *dev,
3603                             struct comedi_subdevice *s,
3604                             struct comedi_insn *insn, unsigned int *data)
3605 {
3606         struct pcidas64_private *devpriv = dev->private;
3607         int channel = CR_CHAN(insn->chanspec);
3608 
3609         /* return immediately if setting hasn't changed, since
3610          * programming these things is slow */
3611         if (devpriv->caldac_state[channel] == data[0])
3612                 return 1;
3613 
3614         caldac_write(dev, channel, data[0]);
3615 
3616         return 1;
3617 }
3618 
3619 static int calib_read_insn(struct comedi_device *dev,
3620                            struct comedi_subdevice *s, struct comedi_insn *insn,
3621                            unsigned int *data)
3622 {
3623         struct pcidas64_private *devpriv = dev->private;
3624         unsigned int channel = CR_CHAN(insn->chanspec);
3625 
3626         data[0] = devpriv->caldac_state[channel];
3627 
3628         return 1;
3629 }
3630 
3631 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3632                          unsigned int value)
3633 {
3634         struct pcidas64_private *devpriv = dev->private;
3635         static const int bitstream_length = 10;
3636         unsigned int bit, register_bits;
3637         unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3638         static const int ad8402_udelay = 1;
3639 
3640         devpriv->ad8402_state[channel] = value;
3641 
3642         register_bits = SELECT_8402_64XX_BIT;
3643         udelay(ad8402_udelay);
3644         writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3645 
3646         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3647                 if (bitstream & bit)
3648                         register_bits |= SERIAL_DATA_IN_BIT;
3649                 else
3650                         register_bits &= ~SERIAL_DATA_IN_BIT;
3651                 udelay(ad8402_udelay);
3652                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3653                 udelay(ad8402_udelay);
3654                 writew(register_bits | SERIAL_CLOCK_BIT,
3655                        devpriv->main_iobase + CALIBRATION_REG);
3656         }
3657 
3658         udelay(ad8402_udelay);
3659         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3660 }
3661 
3662 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3663 static int ad8402_write_insn(struct comedi_device *dev,
3664                              struct comedi_subdevice *s,
3665                              struct comedi_insn *insn, unsigned int *data)
3666 {
3667         struct pcidas64_private *devpriv = dev->private;
3668         int channel = CR_CHAN(insn->chanspec);
3669 
3670         /* return immediately if setting hasn't changed, since
3671          * programming these things is slow */
3672         if (devpriv->ad8402_state[channel] == data[0])
3673                 return 1;
3674 
3675         devpriv->ad8402_state[channel] = data[0];
3676 
3677         ad8402_write(dev, channel, data[0]);
3678 
3679         return 1;
3680 }
3681 
3682 static int ad8402_read_insn(struct comedi_device *dev,
3683                             struct comedi_subdevice *s,
3684                             struct comedi_insn *insn, unsigned int *data)
3685 {
3686         struct pcidas64_private *devpriv = dev->private;
3687         unsigned int channel = CR_CHAN(insn->chanspec);
3688 
3689         data[0] = devpriv->ad8402_state[channel];
3690 
3691         return 1;
3692 }
3693 
3694 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3695 {
3696         struct pcidas64_private *devpriv = dev->private;
3697         static const int bitstream_length = 11;
3698         static const int read_command = 0x6;
3699         unsigned int bitstream = (read_command << 8) | address;
3700         unsigned int bit;
3701         void __iomem * const plx_control_addr =
3702                 devpriv->plx9080_iobase + PLX_CONTROL_REG;
3703         uint16_t value;
3704         static const int value_length = 16;
3705         static const int eeprom_udelay = 1;
3706 
3707         udelay(eeprom_udelay);
3708         devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3709         /*  make sure we don't send anything to the i2c bus on 4020 */
3710         devpriv->plx_control_bits |= CTL_USERO;
3711         writel(devpriv->plx_control_bits, plx_control_addr);
3712         /*  activate serial eeprom */
3713         udelay(eeprom_udelay);
3714         devpriv->plx_control_bits |= CTL_EE_CS;
3715         writel(devpriv->plx_control_bits, plx_control_addr);
3716 
3717         /*  write read command and desired memory address */
3718         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3719                 /*  set bit to be written */
3720                 udelay(eeprom_udelay);
3721                 if (bitstream & bit)
3722                         devpriv->plx_control_bits |= CTL_EE_W;
3723                 else
3724                         devpriv->plx_control_bits &= ~CTL_EE_W;
3725                 writel(devpriv->plx_control_bits, plx_control_addr);
3726                 /*  clock in bit */
3727                 udelay(eeprom_udelay);
3728                 devpriv->plx_control_bits |= CTL_EE_CLK;
3729                 writel(devpriv->plx_control_bits, plx_control_addr);
3730                 udelay(eeprom_udelay);
3731                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3732                 writel(devpriv->plx_control_bits, plx_control_addr);
3733         }
3734         /*  read back value from eeprom memory location */
3735         value = 0;
3736         for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3737                 /*  clock out bit */
3738                 udelay(eeprom_udelay);
3739                 devpriv->plx_control_bits |= CTL_EE_CLK;
3740                 writel(devpriv->plx_control_bits, plx_control_addr);
3741                 udelay(eeprom_udelay);
3742                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3743                 writel(devpriv->plx_control_bits, plx_control_addr);
3744                 udelay(eeprom_udelay);
3745                 if (readl(plx_control_addr) & CTL_EE_R)
3746                         value |= bit;
3747         }
3748 
3749         /*  deactivate eeprom serial input */
3750         udelay(eeprom_udelay);
3751         devpriv->plx_control_bits &= ~CTL_EE_CS;
3752         writel(devpriv->plx_control_bits, plx_control_addr);
3753 
3754         return value;
3755 }
3756 
3757 static int eeprom_read_insn(struct comedi_device *dev,
3758                             struct comedi_subdevice *s,
3759                             struct comedi_insn *insn, unsigned int *data)
3760 {
3761         data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3762 
3763         return 1;
3764 }
3765 
3766 /* Allocate and initialize the subdevice structures.
3767  */
3768 static int setup_subdevices(struct comedi_device *dev)
3769 {
3770         const struct pcidas64_board *thisboard = comedi_board(dev);
3771         struct pcidas64_private *devpriv = dev->private;
3772         struct comedi_subdevice *s;
3773         void __iomem *dio_8255_iobase;
3774         int i;
3775         int ret;
3776 
3777         ret = comedi_alloc_subdevices(dev, 10);
3778         if (ret)
3779                 return ret;
3780 
3781         s = &dev->subdevices[0];
3782         /* analog input subdevice */
3783         dev->read_subdev = s;
3784         s->type = COMEDI_SUBD_AI;
3785         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3786         if (thisboard->layout == LAYOUT_60XX)
3787                 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3788         else if (thisboard->layout == LAYOUT_64XX)
3789                 s->subdev_flags |= SDF_DIFF;
3790         /* XXX Number of inputs in differential mode is ignored */
3791         s->n_chan = thisboard->ai_se_chans;
3792         s->len_chanlist = 0x2000;
3793         s->maxdata = (1 << thisboard->ai_bits) - 1;
3794         s->range_table = thisboard->ai_range_table;
3795         s->insn_read = ai_rinsn;
3796         s->insn_config = ai_config_insn;
3797         s->do_cmd = ai_cmd;
3798         s->do_cmdtest = ai_cmdtest;
3799         s->cancel = ai_cancel;
3800         if (thisboard->layout == LAYOUT_4020) {
3801                 uint8_t data;
3802                 /*  set adc to read from inputs
3803                  *  (not internal calibration sources) */
3804                 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3805                 /*  set channels to +-5 volt input ranges */
3806                 for (i = 0; i < s->n_chan; i++)
3807                         devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3808                 data = devpriv->i2c_cal_range_bits;
3809                 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3810         }
3811 
3812         /* analog output subdevice */
3813         s = &dev->subdevices[1];
3814         if (thisboard->ao_nchan) {
3815                 s->type = COMEDI_SUBD_AO;
3816                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3817                                   SDF_GROUND | SDF_CMD_WRITE;
3818                 s->n_chan = thisboard->ao_nchan;
3819                 s->maxdata = (1 << thisboard->ao_bits) - 1;
3820                 s->range_table = thisboard->ao_range_table;
3821                 s->insn_read = ao_readback_insn;
3822                 s->insn_write = ao_winsn;
3823                 if (ao_cmd_is_supported(thisboard)) {
3824                         dev->write_subdev = s;
3825                         s->do_cmdtest = ao_cmdtest;
3826                         s->do_cmd = ao_cmd;
3827                         s->len_chanlist = thisboard->ao_nchan;
3828                         s->cancel = ao_cancel;
3829                 }
3830         } else {
3831                 s->type = COMEDI_SUBD_UNUSED;
3832         }
3833 
3834         /*  digital input */
3835         s = &dev->subdevices[2];
3836         if (thisboard->layout == LAYOUT_64XX) {
3837                 s->type = COMEDI_SUBD_DI;
3838                 s->subdev_flags = SDF_READABLE;
3839                 s->n_chan = 4;
3840                 s->maxdata = 1;
3841                 s->range_table = &range_digital;
3842                 s->insn_bits = di_rbits;
3843         } else
3844                 s->type = COMEDI_SUBD_UNUSED;
3845 
3846         /*  digital output */
3847         if (thisboard->layout == LAYOUT_64XX) {
3848                 s = &dev->subdevices[3];
3849                 s->type = COMEDI_SUBD_DO;
3850                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3851                 s->n_chan = 4;
3852                 s->maxdata = 1;
3853                 s->range_table = &range_digital;
3854                 s->insn_bits = do_wbits;
3855         } else
3856                 s->type = COMEDI_SUBD_UNUSED;
3857 
3858         /* 8255 */
3859         s = &dev->subdevices[4];
3860         if (thisboard->has_8255) {
3861                 if (thisboard->layout == LAYOUT_4020) {
3862                         dio_8255_iobase = devpriv->main_iobase + I8255_4020_REG;
3863                         ret = subdev_8255_init(dev, s, dio_callback_4020,
3864                                                (unsigned long)dio_8255_iobase);
3865                 } else {
3866                         dio_8255_iobase =
3867                                 devpriv->dio_counter_iobase + DIO_8255_OFFSET;
3868                         ret = subdev_8255_init(dev, s, dio_callback,
3869                                                (unsigned long)dio_8255_iobase);
3870                 }
3871                 if (ret)
3872                         return ret;
3873         } else {
3874                 s->type = COMEDI_SUBD_UNUSED;
3875         }
3876 
3877         /*  8 channel dio for 60xx */
3878         s = &dev->subdevices[5];
3879         if (thisboard->layout == LAYOUT_60XX) {
3880                 s->type = COMEDI_SUBD_DIO;
3881                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3882                 s->n_chan = 8;
3883                 s->maxdata = 1;
3884                 s->range_table = &range_digital;
3885                 s->insn_config = dio_60xx_config_insn;
3886                 s->insn_bits = dio_60xx_wbits;
3887         } else
3888                 s->type = COMEDI_SUBD_UNUSED;
3889 
3890         /*  caldac */
3891         s = &dev->subdevices[6];
3892         s->type = COMEDI_SUBD_CALIB;
3893         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3894         s->n_chan = 8;
3895         if (thisboard->layout == LAYOUT_4020)
3896                 s->maxdata = 0xfff;
3897         else
3898                 s->maxdata = 0xff;
3899         s->insn_read = calib_read_insn;
3900         s->insn_write = calib_write_insn;
3901         for (i = 0; i < s->n_chan; i++)
3902                 caldac_write(dev, i, s->maxdata / 2);
3903 
3904         /*  2 channel ad8402 potentiometer */
3905         s = &dev->subdevices[7];
3906         if (thisboard->layout == LAYOUT_64XX) {
3907                 s->type = COMEDI_SUBD_CALIB;
3908                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3909                 s->n_chan = 2;
3910                 s->insn_read = ad8402_read_insn;
3911                 s->insn_write = ad8402_write_insn;
3912                 s->maxdata = 0xff;
3913                 for (i = 0; i < s->n_chan; i++)
3914                         ad8402_write(dev, i, s->maxdata / 2);
3915         } else
3916                 s->type = COMEDI_SUBD_UNUSED;
3917 
3918         /* serial EEPROM, if present */
3919         s = &dev->subdevices[8];
3920         if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
3921                 s->type = COMEDI_SUBD_MEMORY;
3922                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
3923                 s->n_chan = 128;
3924                 s->maxdata = 0xffff;
3925                 s->insn_read = eeprom_read_insn;
3926         } else
3927                 s->type = COMEDI_SUBD_UNUSED;
3928 
3929         /*  user counter subd XXX */
3930         s = &dev->subdevices[9];
3931         s->type = COMEDI_SUBD_UNUSED;
3932 
3933         return 0;
3934 }
3935 
3936 static int auto_attach(struct comedi_device *dev,
3937                        unsigned long context)
3938 {
3939         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
3940         const struct pcidas64_board *thisboard = NULL;
3941         struct pcidas64_private *devpriv;
3942         uint32_t local_range, local_decode;
3943         int retval;
3944 
3945         if (context < ARRAY_SIZE(pcidas64_boards))
3946                 thisboard = &pcidas64_boards[context];
3947         if (!thisboard)
3948                 return -ENODEV;
3949         dev->board_ptr = thisboard;
3950 
3951         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
3952         if (!devpriv)
3953                 return -ENOMEM;
3954 
3955         retval = comedi_pci_enable(dev);
3956         if (retval)
3957                 return retval;
3958         pci_set_master(pcidev);
3959 
3960         /* Initialize dev->board_name */
3961         dev->board_name = thisboard->name;
3962 
3963         devpriv->main_phys_iobase = pci_resource_start(pcidev, 2);
3964         devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3);
3965 
3966         devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
3967         devpriv->main_iobase = pci_ioremap_bar(pcidev, 2);
3968         devpriv->dio_counter_iobase = pci_ioremap_bar(pcidev, 3);
3969 
3970         if (!devpriv->plx9080_iobase || !devpriv->main_iobase
3971             || !devpriv->dio_counter_iobase) {
3972                 dev_warn(dev->class_dev, "failed to remap io memory\n");
3973                 return -ENOMEM;
3974         }
3975 
3976         /*  figure out what local addresses are */
3977         local_range = readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) &
3978                       LRNG_MEM_MASK;
3979         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS0MAP_REG) &
3980                        local_range & LMAP_MEM_MASK;
3981         devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
3982                                   ~local_range) | local_decode;
3983         local_range = readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) &
3984                       LRNG_MEM_MASK;
3985         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS1MAP_REG) &
3986                        local_range & LMAP_MEM_MASK;
3987         devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
3988                                   ~local_range) | local_decode;
3989 
3990         retval = alloc_and_init_dma_members(dev);
3991         if (retval < 0)
3992                 return retval;
3993 
3994         devpriv->hw_revision =
3995                 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
3996         dev_dbg(dev->class_dev, "stc hardware revision %i\n",
3997                 devpriv->hw_revision);
3998         init_plx9080(dev);
3999         init_stc_registers(dev);
4000         /*  get irq */
4001         if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
4002                         "cb_pcidas64", dev)) {
4003                 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
4004                         pcidev->irq);
4005                 return -EINVAL;
4006         }
4007         dev->irq = pcidev->irq;
4008         dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
4009 
4010         retval = setup_subdevices(dev);
4011         if (retval < 0)
4012                 return retval;
4013 
4014         return 0;
4015 }
4016 
4017 static void detach(struct comedi_device *dev)
4018 {
4019         const struct pcidas64_board *thisboard = comedi_board(dev);
4020         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4021         struct pcidas64_private *devpriv = dev->private;
4022         unsigned int i;
4023 
4024         if (dev->irq)
4025                 free_irq(dev->irq, dev);
4026         if (devpriv) {
4027                 if (pcidev) {
4028                         if (devpriv->plx9080_iobase) {
4029                                 disable_plx_interrupts(dev);
4030                                 iounmap(devpriv->plx9080_iobase);
4031                         }
4032                         if (devpriv->main_iobase)
4033                                 iounmap(devpriv->main_iobase);
4034                         if (devpriv->dio_counter_iobase)
4035                                 iounmap(devpriv->dio_counter_iobase);
4036                         /*  free pci dma buffers */
4037                         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
4038                                 if (devpriv->ai_buffer[i])
4039                                         pci_free_consistent(pcidev,
4040                                                 DMA_BUFFER_SIZE,
4041                                                 devpriv->ai_buffer[i],
4042                                                 devpriv->ai_buffer_bus_addr[i]);
4043                         }
4044                         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
4045                                 if (devpriv->ao_buffer[i])
4046                                         pci_free_consistent(pcidev,
4047                                                 DMA_BUFFER_SIZE,
4048                                                 devpriv->ao_buffer[i],
4049                                                 devpriv->ao_buffer_bus_addr[i]);
4050                         }
4051                         /*  free dma descriptors */
4052                         if (devpriv->ai_dma_desc)
4053                                 pci_free_consistent(pcidev,
4054                                         sizeof(struct plx_dma_desc) *
4055                                         ai_dma_ring_count(thisboard),
4056                                         devpriv->ai_dma_desc,
4057                                         devpriv->ai_dma_desc_bus_addr);
4058                         if (devpriv->ao_dma_desc)
4059                                 pci_free_consistent(pcidev,
4060                                         sizeof(struct plx_dma_desc) *
4061                                         AO_DMA_RING_COUNT,
4062                                         devpriv->ao_dma_desc,
4063                                         devpriv->ao_dma_desc_bus_addr);
4064                 }
4065         }
4066         comedi_pci_disable(dev);
4067 }
4068 
4069 static struct comedi_driver cb_pcidas64_driver = {
4070         .driver_name    = "cb_pcidas64",
4071         .module         = THIS_MODULE,
4072         .auto_attach    = auto_attach,
4073         .detach         = detach,
4074 };
4075 
4076 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4077                                  const struct pci_device_id *id)
4078 {
4079         return comedi_pci_auto_config(dev, &cb_pcidas64_driver,
4080                                       id->driver_data);
4081 }
4082 
4083 static const struct pci_device_id cb_pcidas64_pci_table[] = {
4084         { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 },
4085         { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 },
4086         { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 },
4087         { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 },
4088         { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 },
4089         { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 },
4090         { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 },
4091         { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 },
4092         { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 },
4093         { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 },
4094         { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 },
4095         { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 },
4096         { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 },
4097         { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 },
4098         { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 },
4099         { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 },
4100         { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 },
4101         { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 },
4102         { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 },
4103         { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 },
4104         { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 },
4105         { 0 }
4106 };
4107 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4108 
4109 static struct pci_driver cb_pcidas64_pci_driver = {
4110         .name           = "cb_pcidas64",
4111         .id_table       = cb_pcidas64_pci_table,
4112         .probe          = cb_pcidas64_pci_probe,
4113         .remove         = comedi_pci_auto_unconfig,
4114 };
4115 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4116 
4117 MODULE_AUTHOR("Comedi http://www.comedi.org");
4118 MODULE_DESCRIPTION("Comedi low-level driver");
4119 MODULE_LICENSE("GPL");
4120 

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