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Linux/drivers/staging/comedi/drivers/cb_pcidas64.c

  1 /*
  2     comedi/drivers/cb_pcidas64.c
  3     This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
  4     64xx, 60xx, and 4020 cards.
  5 
  6     Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
  7     Copyright (C) 2001, 2002 Frank Mori Hess
  8 
  9     Thanks also go to the following people:
 10 
 11     Steve Rosenbluth, for providing the source code for
 12     his pci-das6402 driver, and source code for working QNX pci-6402
 13     drivers by Greg Laird and Mariusz Bogacz.  None of the code was
 14     used directly here, but it was useful as an additional source of
 15     documentation on how to program the boards.
 16 
 17     John Sims, for much testing and feedback on pcidas-4020 support.
 18 
 19     COMEDI - Linux Control and Measurement Device Interface
 20     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
 21 
 22     This program is free software; you can redistribute it and/or modify
 23     it under the terms of the GNU General Public License as published by
 24     the Free Software Foundation; either version 2 of the License, or
 25     (at your option) any later version.
 26 
 27     This program is distributed in the hope that it will be useful,
 28     but WITHOUT ANY WARRANTY; without even the implied warranty of
 29     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 30     GNU General Public License for more details.
 31 */
 32 
 33 /*
 34  * Driver: cb_pcidas64
 35  * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
 36  *   with the PLX 9080 PCI controller
 37  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
 38  * Status: works
 39  * Updated: Fri, 02 Nov 2012 18:58:55 +0000
 40  * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
 41  *   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
 42  *   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
 43  *   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
 44  *   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
 45  *   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
 46  *   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
 47  *   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
 48  *   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
 49  *
 50  * Configuration options:
 51  *   None.
 52  *
 53  * Manual attachment of PCI cards with the comedi_config utility is not
 54  * supported by this driver; they are attached automatically.
 55  *
 56  * These boards may be autocalibrated with the comedi_calibrate utility.
 57  *
 58  * To select the bnc trigger input on the 4020 (instead of the dio input),
 59  * specify a nonzero channel in the chanspec.  If you wish to use an external
 60  * master clock on the 4020, you may do so by setting the scan_begin_src
 61  * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
 62  * to configure the divisor to use for the external clock.
 63  *
 64  * Some devices are not identified because the PCI device IDs are not yet
 65  * known. If you have such a board, please let the maintainers know.
 66  */
 67 
 68 /*
 69 
 70 TODO:
 71         make it return error if user attempts an ai command that uses the
 72         external queue, and an ao command simultaneously user counter subdevice
 73         there are a number of boards this driver will support when they are
 74         fully released, but does not yet since the pci device id numbers
 75         are not yet available.
 76 
 77         support prescaled 100khz clock for slow pacing (not available on 6000
 78         series?)
 79 
 80         make ao fifo size adjustable like ai fifo
 81 */
 82 
 83 #include <linux/module.h>
 84 #include <linux/pci.h>
 85 #include <linux/delay.h>
 86 #include <linux/interrupt.h>
 87 
 88 #include "../comedidev.h"
 89 
 90 #include "8253.h"
 91 #include "8255.h"
 92 #include "plx9080.h"
 93 #include "comedi_fc.h"
 94 
 95 #define TIMER_BASE 25           /*  40MHz master clock */
 96 /* 100kHz 'prescaled' clock for slow acquisition,
 97  * maybe I'll support this someday */
 98 #define PRESCALED_TIMER_BASE    10000
 99 #define DMA_BUFFER_SIZE 0x1000
100 
101 /* maximum value that can be loaded into board's 24-bit counters*/
102 static const int max_counter_value = 0xffffff;
103 
104 /* PCI-DAS64xxx base addresses */
105 
106 /* devpriv->main_iobase registers */
107 enum write_only_registers {
108         INTR_ENABLE_REG = 0x0,  /*  interrupt enable register */
109         HW_CONFIG_REG = 0x2,    /*  hardware config register */
110         DAQ_SYNC_REG = 0xc,
111         DAQ_ATRIG_LOW_4020_REG = 0xc,
112         ADC_CONTROL0_REG = 0x10,        /*  adc control register 0 */
113         ADC_CONTROL1_REG = 0x12,        /*  adc control register 1 */
114         CALIBRATION_REG = 0x14,
115         /*  lower 16 bits of adc sample interval counter */
116         ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
117         /*  upper 8 bits of adc sample interval counter */
118         ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
119         /*  lower 16 bits of delay interval counter */
120         ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
121         /*  upper 8 bits of delay interval counter */
122         ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
123         /*  lower 16 bits of hardware conversion/scan counter */
124         ADC_COUNT_LOWER_REG = 0x1e,
125         /*  upper 8 bits of hardware conversion/scan counter */
126         ADC_COUNT_UPPER_REG = 0x20,
127         ADC_START_REG = 0x22,   /*  software trigger to start acquisition */
128         ADC_CONVERT_REG = 0x24, /*  initiates single conversion */
129         ADC_QUEUE_CLEAR_REG = 0x26,     /*  clears adc queue */
130         ADC_QUEUE_LOAD_REG = 0x28,      /*  loads adc queue */
131         ADC_BUFFER_CLEAR_REG = 0x2a,
132         /*  high channel for internal queue, use adc_chan_bits() inline above */
133         ADC_QUEUE_HIGH_REG = 0x2c,
134         DAC_CONTROL0_REG = 0x50,        /*  dac control register 0 */
135         DAC_CONTROL1_REG = 0x52,        /*  dac control register 0 */
136         /*  lower 16 bits of dac sample interval counter */
137         DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
138         /*  upper 8 bits of dac sample interval counter */
139         DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
140         DAC_SELECT_REG = 0x60,
141         DAC_START_REG = 0x64,
142         DAC_BUFFER_CLEAR_REG = 0x66,    /*  clear dac buffer */
143 };
144 
145 static inline unsigned int dac_convert_reg(unsigned int channel)
146 {
147         return 0x70 + (2 * (channel & 0x1));
148 }
149 
150 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
151 {
152         return 0x70 + (4 * (channel & 0x1));
153 }
154 
155 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
156 {
157         return 0x72 + (4 * (channel & 0x1));
158 }
159 
160 enum read_only_registers {
161         /*  hardware status register,
162          *  reading this apparently clears pending interrupts as well */
163         HW_STATUS_REG = 0x0,
164         PIPE1_READ_REG = 0x4,
165         ADC_READ_PNTR_REG = 0x8,
166         LOWER_XFER_REG = 0x10,
167         ADC_WRITE_PNTR_REG = 0xc,
168         PREPOST_REG = 0x14,
169 };
170 
171 enum read_write_registers {
172         I8255_4020_REG = 0x48,  /*  8255 offset, for 4020 only */
173         /*  external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
174         ADC_QUEUE_FIFO_REG = 0x100,
175         ADC_FIFO_REG = 0x200,   /* adc data fifo */
176         /* dac data fifo, has weird interactions with external channel queue */
177         DAC_FIFO_REG = 0x300,
178 };
179 
180 /* dev->mmio registers */
181 enum dio_counter_registers {
182         DIO_8255_OFFSET = 0x0,
183         DO_REG = 0x20,
184         DI_REG = 0x28,
185         DIO_DIRECTION_60XX_REG = 0x40,
186         DIO_DATA_60XX_REG = 0x48,
187 };
188 
189 /* bit definitions for write-only registers */
190 
191 enum intr_enable_contents {
192         ADC_INTR_SRC_MASK = 0x3,        /*  adc interrupt source mask */
193         ADC_INTR_QFULL_BITS = 0x0,      /*  interrupt fifo quarter full */
194         ADC_INTR_EOC_BITS = 0x1,        /*  interrupt end of conversion */
195         ADC_INTR_EOSCAN_BITS = 0x2,     /*  interrupt end of scan */
196         ADC_INTR_EOSEQ_BITS = 0x3,      /*  interrupt end of sequence mask */
197         EN_ADC_INTR_SRC_BIT = 0x4,      /*  enable adc interrupt source */
198         EN_ADC_DONE_INTR_BIT = 0x8,     /*  enable adc acquisition done intr */
199         DAC_INTR_SRC_MASK = 0x30,
200         DAC_INTR_QEMPTY_BITS = 0x0,
201         DAC_INTR_HIGH_CHAN_BITS = 0x10,
202         EN_DAC_INTR_SRC_BIT = 0x40,     /*  enable dac interrupt source */
203         EN_DAC_DONE_INTR_BIT = 0x80,
204         EN_ADC_ACTIVE_INTR_BIT = 0x200, /*  enable adc active interrupt */
205         EN_ADC_STOP_INTR_BIT = 0x400,   /*  enable adc stop trigger interrupt */
206         EN_DAC_ACTIVE_INTR_BIT = 0x800, /*  enable dac active interrupt */
207         EN_DAC_UNDERRUN_BIT = 0x4000,   /*  enable dac underrun status bit */
208         EN_ADC_OVERRUN_BIT = 0x8000,    /*  enable adc overrun status bit */
209 };
210 
211 enum hw_config_contents {
212         MASTER_CLOCK_4020_MASK = 0x3,   /*  master clock source mask for 4020 */
213         INTERNAL_CLOCK_4020_BITS = 0x1, /*  use 40 MHz internal master clock */
214         BNC_CLOCK_4020_BITS = 0x2,      /*  use BNC input for master clock */
215         EXT_CLOCK_4020_BITS = 0x3,      /*  use dio input for master clock */
216         EXT_QUEUE_BIT = 0x200,          /*  use external channel/gain queue */
217         /*  use 225 nanosec strobe when loading dac instead of 50 nanosec */
218         SLOW_DAC_BIT = 0x400,
219         /*  bit with unknown function yet given as default value in pci-das64
220          *  manual */
221         HW_CONFIG_DUMMY_BITS = 0x2000,
222         /*  bit selects channels 1/0 for analog input/output, otherwise 0/1 */
223         DMA_CH_SELECT_BIT = 0x8000,
224         FIFO_SIZE_REG = 0x4,            /*  allows adjustment of fifo sizes */
225         DAC_FIFO_SIZE_MASK = 0xff00,    /*  bits that set dac fifo size */
226         DAC_FIFO_BITS = 0xf800,         /*  8k sample ao fifo */
227 };
228 #define DAC_FIFO_SIZE 0x2000
229 
230 enum daq_atrig_low_4020_contents {
231         /*  use trig/ext clk bnc input for analog gate signal */
232         EXT_AGATE_BNC_BIT = 0x8000,
233         /*  use trig/ext clk bnc input for external stop trigger signal */
234         EXT_STOP_TRIG_BNC_BIT = 0x4000,
235         /*  use trig/ext clk bnc input for external start trigger signal */
236         EXT_START_TRIG_BNC_BIT = 0x2000,
237 };
238 
239 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
240 {
241         return threshold & 0xfff;
242 }
243 
244 enum adc_control0_contents {
245         ADC_GATE_SRC_MASK = 0x3,        /*  bits that select gate */
246         ADC_SOFT_GATE_BITS = 0x1,       /*  software gate */
247         ADC_EXT_GATE_BITS = 0x2,        /*  external digital gate */
248         ADC_ANALOG_GATE_BITS = 0x3,     /*  analog level gate */
249         ADC_GATE_LEVEL_BIT = 0x4,       /*  level-sensitive gate (for digital) */
250         ADC_GATE_POLARITY_BIT = 0x8,    /*  gate active low */
251         ADC_START_TRIG_SOFT_BITS = 0x10,
252         ADC_START_TRIG_EXT_BITS = 0x20,
253         ADC_START_TRIG_ANALOG_BITS = 0x30,
254         ADC_START_TRIG_MASK = 0x30,
255         ADC_START_TRIG_FALLING_BIT = 0x40,      /*  trig 1 uses falling edge */
256         /*  external pacing uses falling edge */
257         ADC_EXT_CONV_FALLING_BIT = 0x800,
258         /*  enable hardware scan counter */
259         ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
260         ADC_DMA_DISABLE_BIT = 0x4000,   /*  disables dma */
261         ADC_ENABLE_BIT = 0x8000,        /*  master adc enable */
262 };
263 
264 enum adc_control1_contents {
265         /*  should be set for boards with > 16 channels */
266         ADC_QUEUE_CONFIG_BIT = 0x1,
267         CONVERT_POLARITY_BIT = 0x10,
268         EOC_POLARITY_BIT = 0x20,
269         ADC_SW_GATE_BIT = 0x40, /*  software gate of adc */
270         ADC_DITHER_BIT = 0x200, /*  turn on extra noise for dithering */
271         RETRIGGER_BIT = 0x800,
272         ADC_LO_CHANNEL_4020_MASK = 0x300,
273         ADC_HI_CHANNEL_4020_MASK = 0xc00,
274         TWO_CHANNEL_4020_BITS = 0x1000, /*  two channel mode for 4020 */
275         FOUR_CHANNEL_4020_BITS = 0x2000, /*  four channel mode for 4020 */
276         CHANNEL_MODE_4020_MASK = 0x3000,
277         ADC_MODE_MASK = 0xf000,
278 };
279 
280 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
281 {
282         return (channel & 0x3) << 8;
283 };
284 
285 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
286 {
287         return (channel & 0x3) << 10;
288 };
289 
290 static inline uint16_t adc_mode_bits(unsigned int mode)
291 {
292         return (mode & 0xf) << 12;
293 };
294 
295 enum calibration_contents {
296         SELECT_8800_BIT = 0x1,
297         SELECT_8402_64XX_BIT = 0x2,
298         SELECT_1590_60XX_BIT = 0x2,
299         CAL_EN_64XX_BIT = 0x40, /*  calibration enable for 64xx series */
300         SERIAL_DATA_IN_BIT = 0x80,
301         SERIAL_CLOCK_BIT = 0x100,
302         CAL_EN_60XX_BIT = 0x200, /*  calibration enable for 60xx series */
303         CAL_GAIN_BIT = 0x800,
304 };
305 
306 /* calibration sources for 6025 are:
307  *  0 : ground
308  *  1 : 10V
309  *  2 : 5V
310  *  3 : 0.5V
311  *  4 : 0.05V
312  *  5 : ground
313  *  6 : dac channel 0
314  *  7 : dac channel 1
315  */
316 
317 static inline uint16_t adc_src_bits(unsigned int source)
318 {
319         return (source & 0xf) << 3;
320 };
321 
322 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
323 {
324         return (channel & 0x3) << 8;
325 };
326 
327 enum adc_queue_load_contents {
328         UNIP_BIT = 0x800,       /*  unipolar/bipolar bit */
329         ADC_SE_DIFF_BIT = 0x1000,       /*  single-ended/ differential bit */
330         /*  non-referenced single-ended (common-mode input) */
331         ADC_COMMON_BIT = 0x2000,
332         QUEUE_EOSEQ_BIT = 0x4000,       /*  queue end of sequence */
333         QUEUE_EOSCAN_BIT = 0x8000,      /*  queue end of scan */
334 };
335 
336 static inline uint16_t adc_chan_bits(unsigned int channel)
337 {
338         return channel & 0x3f;
339 };
340 
341 enum dac_control0_contents {
342         DAC_ENABLE_BIT = 0x8000,        /*  dac controller enable bit */
343         DAC_CYCLIC_STOP_BIT = 0x4000,
344         DAC_WAVEFORM_MODE_BIT = 0x100,
345         DAC_EXT_UPDATE_FALLING_BIT = 0x80,
346         DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
347         WAVEFORM_TRIG_MASK = 0x30,
348         WAVEFORM_TRIG_DISABLED_BITS = 0x0,
349         WAVEFORM_TRIG_SOFT_BITS = 0x10,
350         WAVEFORM_TRIG_EXT_BITS = 0x20,
351         WAVEFORM_TRIG_ADC1_BITS = 0x30,
352         WAVEFORM_TRIG_FALLING_BIT = 0x8,
353         WAVEFORM_GATE_LEVEL_BIT = 0x4,
354         WAVEFORM_GATE_ENABLE_BIT = 0x2,
355         WAVEFORM_GATE_SELECT_BIT = 0x1,
356 };
357 
358 enum dac_control1_contents {
359         DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
360         DAC1_EXT_REF_BIT = 0x200,
361         DAC0_EXT_REF_BIT = 0x100,
362         DAC_OUTPUT_ENABLE_BIT = 0x80,   /*  dac output enable bit */
363         DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
364         DAC_SW_GATE_BIT = 0x20,
365         DAC1_UNIPOLAR_BIT = 0x8,
366         DAC0_UNIPOLAR_BIT = 0x2,
367 };
368 
369 /* bit definitions for read-only registers */
370 enum hw_status_contents {
371         DAC_UNDERRUN_BIT = 0x1,
372         ADC_OVERRUN_BIT = 0x2,
373         DAC_ACTIVE_BIT = 0x4,
374         ADC_ACTIVE_BIT = 0x8,
375         DAC_INTR_PENDING_BIT = 0x10,
376         ADC_INTR_PENDING_BIT = 0x20,
377         DAC_DONE_BIT = 0x40,
378         ADC_DONE_BIT = 0x80,
379         EXT_INTR_PENDING_BIT = 0x100,
380         ADC_STOP_BIT = 0x200,
381 };
382 
383 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
384 {
385         return (hw_status_bits >> 10) & 0x3;
386 };
387 
388 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
389 {
390         return (prepost_bits >> 6) & 0x3;
391 }
392 
393 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
394 {
395         return (prepost_bits >> 12) & 0x3;
396 }
397 
398 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
399 {
400         return (prepost_bits >> 14) & 0x3;
401 }
402 
403 /* I2C addresses for 4020 */
404 enum i2c_addresses {
405         RANGE_CAL_I2C_ADDR = 0x20,
406         CALDAC0_I2C_ADDR = 0xc,
407         CALDAC1_I2C_ADDR = 0xd,
408 };
409 
410 enum range_cal_i2c_contents {
411         /*  bits that set what source the adc converter measures */
412         ADC_SRC_4020_MASK = 0x70,
413         /*  make bnc trig/ext clock threshold 0V instead of 2.5V */
414         BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
415 };
416 
417 static inline uint8_t adc_src_4020_bits(unsigned int source)
418 {
419         return (source << 4) & ADC_SRC_4020_MASK;
420 };
421 
422 static inline uint8_t attenuate_bit(unsigned int channel)
423 {
424         /*  attenuate channel (+-5V input range) */
425         return 1 << (channel & 0x3);
426 };
427 
428 /* analog input ranges for 64xx boards */
429 static const struct comedi_lrange ai_ranges_64xx = {
430         8, {
431                 BIP_RANGE(10),
432                 BIP_RANGE(5),
433                 BIP_RANGE(2.5),
434                 BIP_RANGE(1.25),
435                 UNI_RANGE(10),
436                 UNI_RANGE(5),
437                 UNI_RANGE(2.5),
438                 UNI_RANGE(1.25)
439         }
440 };
441 
442 /* analog input ranges for 60xx boards */
443 static const struct comedi_lrange ai_ranges_60xx = {
444         4, {
445                 BIP_RANGE(10),
446                 BIP_RANGE(5),
447                 BIP_RANGE(0.5),
448                 BIP_RANGE(0.05)
449         }
450 };
451 
452 /* analog input ranges for 6030, etc boards */
453 static const struct comedi_lrange ai_ranges_6030 = {
454         14, {
455                 BIP_RANGE(10),
456                 BIP_RANGE(5),
457                 BIP_RANGE(2),
458                 BIP_RANGE(1),
459                 BIP_RANGE(0.5),
460                 BIP_RANGE(0.2),
461                 BIP_RANGE(0.1),
462                 UNI_RANGE(10),
463                 UNI_RANGE(5),
464                 UNI_RANGE(2),
465                 UNI_RANGE(1),
466                 UNI_RANGE(0.5),
467                 UNI_RANGE(0.2),
468                 UNI_RANGE(0.1)
469         }
470 };
471 
472 /* analog input ranges for 6052, etc boards */
473 static const struct comedi_lrange ai_ranges_6052 = {
474         15, {
475                 BIP_RANGE(10),
476                 BIP_RANGE(5),
477                 BIP_RANGE(2.5),
478                 BIP_RANGE(1),
479                 BIP_RANGE(0.5),
480                 BIP_RANGE(0.25),
481                 BIP_RANGE(0.1),
482                 BIP_RANGE(0.05),
483                 UNI_RANGE(10),
484                 UNI_RANGE(5),
485                 UNI_RANGE(2),
486                 UNI_RANGE(1),
487                 UNI_RANGE(0.5),
488                 UNI_RANGE(0.2),
489                 UNI_RANGE(0.1)
490         }
491 };
492 
493 /* analog input ranges for 4020 board */
494 static const struct comedi_lrange ai_ranges_4020 = {
495         2, {
496                 BIP_RANGE(5),
497                 BIP_RANGE(1)
498         }
499 };
500 
501 /* analog output ranges */
502 static const struct comedi_lrange ao_ranges_64xx = {
503         4, {
504                 BIP_RANGE(5),
505                 BIP_RANGE(10),
506                 UNI_RANGE(5),
507                 UNI_RANGE(10)
508         }
509 };
510 
511 static const int ao_range_code_64xx[] = {
512         0x0,
513         0x1,
514         0x2,
515         0x3,
516 };
517 
518 static const int ao_range_code_60xx[] = {
519         0x0,
520 };
521 
522 static const struct comedi_lrange ao_ranges_6030 = {
523         2, {
524                 BIP_RANGE(10),
525                 UNI_RANGE(10)
526         }
527 };
528 
529 static const int ao_range_code_6030[] = {
530         0x0,
531         0x2,
532 };
533 
534 static const struct comedi_lrange ao_ranges_4020 = {
535         2, {
536                 BIP_RANGE(5),
537                 BIP_RANGE(10)
538         }
539 };
540 
541 static const int ao_range_code_4020[] = {
542         0x1,
543         0x0,
544 };
545 
546 enum register_layout {
547         LAYOUT_60XX,
548         LAYOUT_64XX,
549         LAYOUT_4020,
550 };
551 
552 struct hw_fifo_info {
553         unsigned int num_segments;
554         unsigned int max_segment_length;
555         unsigned int sample_packing_ratio;
556         uint16_t fifo_size_reg_mask;
557 };
558 
559 enum pcidas64_boardid {
560         BOARD_PCIDAS6402_16,
561         BOARD_PCIDAS6402_12,
562         BOARD_PCIDAS64_M1_16,
563         BOARD_PCIDAS64_M2_16,
564         BOARD_PCIDAS64_M3_16,
565         BOARD_PCIDAS6013,
566         BOARD_PCIDAS6014,
567         BOARD_PCIDAS6023,
568         BOARD_PCIDAS6025,
569         BOARD_PCIDAS6030,
570         BOARD_PCIDAS6031,
571         BOARD_PCIDAS6032,
572         BOARD_PCIDAS6033,
573         BOARD_PCIDAS6034,
574         BOARD_PCIDAS6035,
575         BOARD_PCIDAS6036,
576         BOARD_PCIDAS6040,
577         BOARD_PCIDAS6052,
578         BOARD_PCIDAS6070,
579         BOARD_PCIDAS6071,
580         BOARD_PCIDAS4020_12,
581         BOARD_PCIDAS6402_16_JR,
582         BOARD_PCIDAS64_M1_16_JR,
583         BOARD_PCIDAS64_M2_16_JR,
584         BOARD_PCIDAS64_M3_16_JR,
585         BOARD_PCIDAS64_M1_14,
586         BOARD_PCIDAS64_M2_14,
587         BOARD_PCIDAS64_M3_14,
588 };
589 
590 struct pcidas64_board {
591         const char *name;
592         int ai_se_chans;        /*  number of ai inputs in single-ended mode */
593         int ai_bits;            /*  analog input resolution */
594         int ai_speed;           /*  fastest conversion period in ns */
595         const struct comedi_lrange *ai_range_table;
596         int ao_nchan;           /*  number of analog out channels */
597         int ao_bits;            /*  analog output resolution */
598         int ao_scan_speed;      /*  analog output scan speed */
599         const struct comedi_lrange *ao_range_table;
600         const int *ao_range_code;
601         const struct hw_fifo_info *const ai_fifo;
602         /*  different board families have slightly different registers */
603         enum register_layout layout;
604         unsigned has_8255:1;
605 };
606 
607 static const struct hw_fifo_info ai_fifo_4020 = {
608         .num_segments = 2,
609         .max_segment_length = 0x8000,
610         .sample_packing_ratio = 2,
611         .fifo_size_reg_mask = 0x7f,
612 };
613 
614 static const struct hw_fifo_info ai_fifo_64xx = {
615         .num_segments = 4,
616         .max_segment_length = 0x800,
617         .sample_packing_ratio = 1,
618         .fifo_size_reg_mask = 0x3f,
619 };
620 
621 static const struct hw_fifo_info ai_fifo_60xx = {
622         .num_segments = 4,
623         .max_segment_length = 0x800,
624         .sample_packing_ratio = 1,
625         .fifo_size_reg_mask = 0x7f,
626 };
627 
628 /* maximum number of dma transfers we will chain together into a ring
629  * (and the maximum number of dma buffers we maintain) */
630 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
631 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
632 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
633 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
634 {
635         if (board->layout == LAYOUT_4020)
636                 return MAX_AI_DMA_RING_COUNT;
637 
638         return MIN_AI_DMA_RING_COUNT;
639 }
640 
641 static const int bytes_in_sample = 2;
642 
643 static const struct pcidas64_board pcidas64_boards[] = {
644         [BOARD_PCIDAS6402_16] = {
645                 .name           = "pci-das6402/16",
646                 .ai_se_chans    = 64,
647                 .ai_bits        = 16,
648                 .ai_speed       = 5000,
649                 .ao_nchan       = 2,
650                 .ao_bits        = 16,
651                 .ao_scan_speed  = 10000,
652                 .layout         = LAYOUT_64XX,
653                 .ai_range_table = &ai_ranges_64xx,
654                 .ao_range_table = &ao_ranges_64xx,
655                 .ao_range_code  = ao_range_code_64xx,
656                 .ai_fifo        = &ai_fifo_64xx,
657                 .has_8255       = 1,
658         },
659         [BOARD_PCIDAS6402_12] = {
660                 .name           = "pci-das6402/12",     /*  XXX check */
661                 .ai_se_chans    = 64,
662                 .ai_bits        = 12,
663                 .ai_speed       = 5000,
664                 .ao_nchan       = 2,
665                 .ao_bits        = 12,
666                 .ao_scan_speed  = 10000,
667                 .layout         = LAYOUT_64XX,
668                 .ai_range_table = &ai_ranges_64xx,
669                 .ao_range_table = &ao_ranges_64xx,
670                 .ao_range_code  = ao_range_code_64xx,
671                 .ai_fifo        = &ai_fifo_64xx,
672                 .has_8255       = 1,
673         },
674         [BOARD_PCIDAS64_M1_16] = {
675                 .name           = "pci-das64/m1/16",
676                 .ai_se_chans    = 64,
677                 .ai_bits        = 16,
678                 .ai_speed       = 1000,
679                 .ao_nchan       = 2,
680                 .ao_bits        = 16,
681                 .ao_scan_speed  = 10000,
682                 .layout         = LAYOUT_64XX,
683                 .ai_range_table = &ai_ranges_64xx,
684                 .ao_range_table = &ao_ranges_64xx,
685                 .ao_range_code  = ao_range_code_64xx,
686                 .ai_fifo        = &ai_fifo_64xx,
687                 .has_8255       = 1,
688         },
689         [BOARD_PCIDAS64_M2_16] = {
690                 .name = "pci-das64/m2/16",
691                 .ai_se_chans    = 64,
692                 .ai_bits        = 16,
693                 .ai_speed       = 500,
694                 .ao_nchan       = 2,
695                 .ao_bits        = 16,
696                 .ao_scan_speed  = 10000,
697                 .layout         = LAYOUT_64XX,
698                 .ai_range_table = &ai_ranges_64xx,
699                 .ao_range_table = &ao_ranges_64xx,
700                 .ao_range_code  = ao_range_code_64xx,
701                 .ai_fifo        = &ai_fifo_64xx,
702                 .has_8255       = 1,
703         },
704         [BOARD_PCIDAS64_M3_16] = {
705                 .name           = "pci-das64/m3/16",
706                 .ai_se_chans    = 64,
707                 .ai_bits        = 16,
708                 .ai_speed       = 333,
709                 .ao_nchan       = 2,
710                 .ao_bits        = 16,
711                 .ao_scan_speed  = 10000,
712                 .layout         = LAYOUT_64XX,
713                 .ai_range_table = &ai_ranges_64xx,
714                 .ao_range_table = &ao_ranges_64xx,
715                 .ao_range_code  = ao_range_code_64xx,
716                 .ai_fifo        = &ai_fifo_64xx,
717                 .has_8255       = 1,
718         },
719         [BOARD_PCIDAS6013] = {
720                 .name           = "pci-das6013",
721                 .ai_se_chans    = 16,
722                 .ai_bits        = 16,
723                 .ai_speed       = 5000,
724                 .ao_nchan       = 0,
725                 .ao_bits        = 16,
726                 .layout         = LAYOUT_60XX,
727                 .ai_range_table = &ai_ranges_60xx,
728                 .ao_range_table = &range_bipolar10,
729                 .ao_range_code  = ao_range_code_60xx,
730                 .ai_fifo        = &ai_fifo_60xx,
731                 .has_8255       = 0,
732         },
733         [BOARD_PCIDAS6014] = {
734                 .name           = "pci-das6014",
735                 .ai_se_chans    = 16,
736                 .ai_bits        = 16,
737                 .ai_speed       = 5000,
738                 .ao_nchan       = 2,
739                 .ao_bits        = 16,
740                 .ao_scan_speed  = 100000,
741                 .layout         = LAYOUT_60XX,
742                 .ai_range_table = &ai_ranges_60xx,
743                 .ao_range_table = &range_bipolar10,
744                 .ao_range_code  = ao_range_code_60xx,
745                 .ai_fifo        = &ai_fifo_60xx,
746                 .has_8255       = 0,
747         },
748         [BOARD_PCIDAS6023] = {
749                 .name           = "pci-das6023",
750                 .ai_se_chans    = 16,
751                 .ai_bits        = 12,
752                 .ai_speed       = 5000,
753                 .ao_nchan       = 0,
754                 .ao_scan_speed  = 100000,
755                 .layout         = LAYOUT_60XX,
756                 .ai_range_table = &ai_ranges_60xx,
757                 .ao_range_table = &range_bipolar10,
758                 .ao_range_code  = ao_range_code_60xx,
759                 .ai_fifo        = &ai_fifo_60xx,
760                 .has_8255       = 1,
761         },
762         [BOARD_PCIDAS6025] = {
763                 .name           = "pci-das6025",
764                 .ai_se_chans    = 16,
765                 .ai_bits        = 12,
766                 .ai_speed       = 5000,
767                 .ao_nchan       = 2,
768                 .ao_bits        = 12,
769                 .ao_scan_speed  = 100000,
770                 .layout         = LAYOUT_60XX,
771                 .ai_range_table = &ai_ranges_60xx,
772                 .ao_range_table = &range_bipolar10,
773                 .ao_range_code  = ao_range_code_60xx,
774                 .ai_fifo        = &ai_fifo_60xx,
775                 .has_8255       = 1,
776         },
777         [BOARD_PCIDAS6030] = {
778                 .name           = "pci-das6030",
779                 .ai_se_chans    = 16,
780                 .ai_bits        = 16,
781                 .ai_speed       = 10000,
782                 .ao_nchan       = 2,
783                 .ao_bits        = 16,
784                 .ao_scan_speed  = 10000,
785                 .layout         = LAYOUT_60XX,
786                 .ai_range_table = &ai_ranges_6030,
787                 .ao_range_table = &ao_ranges_6030,
788                 .ao_range_code  = ao_range_code_6030,
789                 .ai_fifo        = &ai_fifo_60xx,
790                 .has_8255       = 0,
791         },
792         [BOARD_PCIDAS6031] = {
793                 .name           = "pci-das6031",
794                 .ai_se_chans    = 64,
795                 .ai_bits        = 16,
796                 .ai_speed       = 10000,
797                 .ao_nchan       = 2,
798                 .ao_bits        = 16,
799                 .ao_scan_speed  = 10000,
800                 .layout         = LAYOUT_60XX,
801                 .ai_range_table = &ai_ranges_6030,
802                 .ao_range_table = &ao_ranges_6030,
803                 .ao_range_code  = ao_range_code_6030,
804                 .ai_fifo        = &ai_fifo_60xx,
805                 .has_8255       = 0,
806         },
807         [BOARD_PCIDAS6032] = {
808                 .name           = "pci-das6032",
809                 .ai_se_chans    = 16,
810                 .ai_bits        = 16,
811                 .ai_speed       = 10000,
812                 .ao_nchan       = 0,
813                 .layout         = LAYOUT_60XX,
814                 .ai_range_table = &ai_ranges_6030,
815                 .ai_fifo        = &ai_fifo_60xx,
816                 .has_8255       = 0,
817         },
818         [BOARD_PCIDAS6033] = {
819                 .name           = "pci-das6033",
820                 .ai_se_chans    = 64,
821                 .ai_bits        = 16,
822                 .ai_speed       = 10000,
823                 .ao_nchan       = 0,
824                 .layout         = LAYOUT_60XX,
825                 .ai_range_table = &ai_ranges_6030,
826                 .ai_fifo        = &ai_fifo_60xx,
827                 .has_8255       = 0,
828         },
829         [BOARD_PCIDAS6034] = {
830                 .name           = "pci-das6034",
831                 .ai_se_chans    = 16,
832                 .ai_bits        = 16,
833                 .ai_speed       = 5000,
834                 .ao_nchan       = 0,
835                 .ao_scan_speed  = 0,
836                 .layout         = LAYOUT_60XX,
837                 .ai_range_table = &ai_ranges_60xx,
838                 .ai_fifo        = &ai_fifo_60xx,
839                 .has_8255       = 0,
840         },
841         [BOARD_PCIDAS6035] = {
842                 .name           = "pci-das6035",
843                 .ai_se_chans    = 16,
844                 .ai_bits        = 16,
845                 .ai_speed       = 5000,
846                 .ao_nchan       = 2,
847                 .ao_bits        = 12,
848                 .ao_scan_speed  = 100000,
849                 .layout         = LAYOUT_60XX,
850                 .ai_range_table = &ai_ranges_60xx,
851                 .ao_range_table = &range_bipolar10,
852                 .ao_range_code  = ao_range_code_60xx,
853                 .ai_fifo        = &ai_fifo_60xx,
854                 .has_8255       = 0,
855         },
856         [BOARD_PCIDAS6036] = {
857                 .name           = "pci-das6036",
858                 .ai_se_chans    = 16,
859                 .ai_bits        = 16,
860                 .ai_speed       = 5000,
861                 .ao_nchan       = 2,
862                 .ao_bits        = 16,
863                 .ao_scan_speed  = 100000,
864                 .layout         = LAYOUT_60XX,
865                 .ai_range_table = &ai_ranges_60xx,
866                 .ao_range_table = &range_bipolar10,
867                 .ao_range_code  = ao_range_code_60xx,
868                 .ai_fifo        = &ai_fifo_60xx,
869                 .has_8255       = 0,
870         },
871         [BOARD_PCIDAS6040] = {
872                 .name           = "pci-das6040",
873                 .ai_se_chans    = 16,
874                 .ai_bits        = 12,
875                 .ai_speed       = 2000,
876                 .ao_nchan       = 2,
877                 .ao_bits        = 12,
878                 .ao_scan_speed  = 1000,
879                 .layout         = LAYOUT_60XX,
880                 .ai_range_table = &ai_ranges_6052,
881                 .ao_range_table = &ao_ranges_6030,
882                 .ao_range_code  = ao_range_code_6030,
883                 .ai_fifo        = &ai_fifo_60xx,
884                 .has_8255       = 0,
885         },
886         [BOARD_PCIDAS6052] = {
887                 .name           = "pci-das6052",
888                 .ai_se_chans    = 16,
889                 .ai_bits        = 16,
890                 .ai_speed       = 3333,
891                 .ao_nchan       = 2,
892                 .ao_bits        = 16,
893                 .ao_scan_speed  = 3333,
894                 .layout         = LAYOUT_60XX,
895                 .ai_range_table = &ai_ranges_6052,
896                 .ao_range_table = &ao_ranges_6030,
897                 .ao_range_code  = ao_range_code_6030,
898                 .ai_fifo        = &ai_fifo_60xx,
899                 .has_8255       = 0,
900         },
901         [BOARD_PCIDAS6070] = {
902                 .name           = "pci-das6070",
903                 .ai_se_chans    = 16,
904                 .ai_bits        = 12,
905                 .ai_speed       = 800,
906                 .ao_nchan       = 2,
907                 .ao_bits        = 12,
908                 .ao_scan_speed  = 1000,
909                 .layout         = LAYOUT_60XX,
910                 .ai_range_table = &ai_ranges_6052,
911                 .ao_range_table = &ao_ranges_6030,
912                 .ao_range_code  = ao_range_code_6030,
913                 .ai_fifo        = &ai_fifo_60xx,
914                 .has_8255       = 0,
915         },
916         [BOARD_PCIDAS6071] = {
917                 .name           = "pci-das6071",
918                 .ai_se_chans    = 64,
919                 .ai_bits        = 12,
920                 .ai_speed       = 800,
921                 .ao_nchan       = 2,
922                 .ao_bits        = 12,
923                 .ao_scan_speed  = 1000,
924                 .layout         = LAYOUT_60XX,
925                 .ai_range_table = &ai_ranges_6052,
926                 .ao_range_table = &ao_ranges_6030,
927                 .ao_range_code  = ao_range_code_6030,
928                 .ai_fifo        = &ai_fifo_60xx,
929                 .has_8255       = 0,
930         },
931         [BOARD_PCIDAS4020_12] = {
932                 .name           = "pci-das4020/12",
933                 .ai_se_chans    = 4,
934                 .ai_bits        = 12,
935                 .ai_speed       = 50,
936                 .ao_bits        = 12,
937                 .ao_nchan       = 2,
938                 .ao_scan_speed  = 0,    /*  no hardware pacing on ao */
939                 .layout         = LAYOUT_4020,
940                 .ai_range_table = &ai_ranges_4020,
941                 .ao_range_table = &ao_ranges_4020,
942                 .ao_range_code  = ao_range_code_4020,
943                 .ai_fifo        = &ai_fifo_4020,
944                 .has_8255       = 1,
945         },
946 #if 0
947         /*
948          * The device id for these boards is unknown
949          */
950 
951         [BOARD_PCIDAS6402_16_JR] = {
952                 .name           = "pci-das6402/16/jr",
953                 .ai_se_chans    = 64,
954                 .ai_bits        = 16,
955                 .ai_speed       = 5000,
956                 .ao_nchan       = 0,
957                 .ao_scan_speed  = 10000,
958                 .layout         = LAYOUT_64XX,
959                 .ai_range_table = &ai_ranges_64xx,
960                 .ai_fifo        = ai_fifo_64xx,
961                 .has_8255       = 1,
962         },
963         [BOARD_PCIDAS64_M1_16_JR] = {
964                 .name           = "pci-das64/m1/16/jr",
965                 .ai_se_chans    = 64,
966                 .ai_bits        = 16,
967                 .ai_speed       = 1000,
968                 .ao_nchan       = 0,
969                 .ao_scan_speed  = 10000,
970                 .layout         = LAYOUT_64XX,
971                 .ai_range_table = &ai_ranges_64xx,
972                 .ai_fifo        = ai_fifo_64xx,
973                 .has_8255       = 1,
974         },
975         [BOARD_PCIDAS64_M2_16_JR] = {
976                 .name = "pci-das64/m2/16/jr",
977                 .ai_se_chans    = 64,
978                 .ai_bits        = 16,
979                 .ai_speed       = 500,
980                 .ao_nchan       = 0,
981                 .ao_scan_speed  = 10000,
982                 .layout         = LAYOUT_64XX,
983                 .ai_range_table = &ai_ranges_64xx,
984                 .ai_fifo        = ai_fifo_64xx,
985                 .has_8255       = 1,
986         },
987         [BOARD_PCIDAS64_M3_16_JR] = {
988                 .name           = "pci-das64/m3/16/jr",
989                 .ai_se_chans    = 64,
990                 .ai_bits        = 16,
991                 .ai_speed       = 333,
992                 .ao_nchan       = 0,
993                 .ao_scan_speed  = 10000,
994                 .layout         = LAYOUT_64XX,
995                 .ai_range_table = &ai_ranges_64xx,
996                 .ai_fifo        = ai_fifo_64xx,
997                 .has_8255       = 1,
998         },
999         [BOARD_PCIDAS64_M1_14] = {
1000                 .name           = "pci-das64/m1/14",
1001                 .ai_se_chans    = 64,
1002                 .ai_bits        = 14,
1003                 .ai_speed       = 1000,
1004                 .ao_nchan       = 2,
1005                 .ao_scan_speed  = 10000,
1006                 .layout         = LAYOUT_64XX,
1007                 .ai_range_table = &ai_ranges_64xx,
1008                 .ai_fifo        = ai_fifo_64xx,
1009                 .has_8255       = 1,
1010         },
1011         [BOARD_PCIDAS64_M2_14] = {
1012                 .name           = "pci-das64/m2/14",
1013                 .ai_se_chans    = 64,
1014                 .ai_bits        = 14,
1015                 .ai_speed       = 500,
1016                 .ao_nchan       = 2,
1017                 .ao_scan_speed  = 10000,
1018                 .layout         = LAYOUT_64XX,
1019                 .ai_range_table = &ai_ranges_64xx,
1020                 .ai_fifo        = ai_fifo_64xx,
1021                 .has_8255       = 1,
1022         },
1023         [BOARD_PCIDAS64_M3_14] = {
1024                 .name           = "pci-das64/m3/14",
1025                 .ai_se_chans    = 64,
1026                 .ai_bits        = 14,
1027                 .ai_speed       = 333,
1028                 .ao_nchan       = 2,
1029                 .ao_scan_speed  = 10000,
1030                 .layout         = LAYOUT_64XX,
1031                 .ai_range_table = &ai_ranges_64xx,
1032                 .ai_fifo        = ai_fifo_64xx,
1033                 .has_8255       = 1,
1034         },
1035 #endif
1036 };
1037 
1038 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1039                                               int use_differential)
1040 {
1041         const struct pcidas64_board *thisboard = comedi_board(dev);
1042 
1043         if ((thisboard->layout == LAYOUT_64XX && !use_differential) ||
1044             (thisboard->layout == LAYOUT_60XX && use_differential))
1045                 return ADC_SE_DIFF_BIT;
1046 
1047         return 0;
1048 }
1049 
1050 struct ext_clock_info {
1051         /*  master clock divisor to use for scans with external master clock */
1052         unsigned int divisor;
1053         /*  chanspec for master clock input when used as scan begin src */
1054         unsigned int chanspec;
1055 };
1056 
1057 /* this structure is for data unique to this hardware driver. */
1058 struct pcidas64_private {
1059         /*  base addresses (physical) */
1060         resource_size_t main_phys_iobase;
1061         resource_size_t dio_counter_phys_iobase;
1062         /*  base addresses (ioremapped) */
1063         void __iomem *plx9080_iobase;
1064         void __iomem *main_iobase;
1065         /*  local address (used by dma controller) */
1066         uint32_t local0_iobase;
1067         uint32_t local1_iobase;
1068         /*  number of analog input samples remaining */
1069         unsigned int ai_count;
1070         /*  dma buffers for analog input */
1071         uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];
1072         /*  physical addresses of ai dma buffers */
1073         dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1074         /*  array of ai dma descriptors read by plx9080,
1075          *  allocated to get proper alignment */
1076         struct plx_dma_desc *ai_dma_desc;
1077         /*  physical address of ai dma descriptor array */
1078         dma_addr_t ai_dma_desc_bus_addr;
1079         /*  index of the ai dma descriptor/buffer
1080          *  that is currently being used */
1081         unsigned int ai_dma_index;
1082         /*  dma buffers for analog output */
1083         uint16_t *ao_buffer[AO_DMA_RING_COUNT];
1084         /*  physical addresses of ao dma buffers */
1085         dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1086         struct plx_dma_desc *ao_dma_desc;
1087         dma_addr_t ao_dma_desc_bus_addr;
1088         /*  keeps track of buffer where the next ao sample should go */
1089         unsigned int ao_dma_index;
1090         /*  number of analog output samples remaining */
1091         unsigned long ao_count;
1092         /*  remember what the analog outputs are set to, to allow readback */
1093         unsigned int ao_value[2];
1094         unsigned int hw_revision;       /*  stc chip hardware revision number */
1095         /*  last bits sent to INTR_ENABLE_REG register */
1096         unsigned int intr_enable_bits;
1097         /*  last bits sent to ADC_CONTROL1_REG register */
1098         uint16_t adc_control1_bits;
1099         /*  last bits sent to FIFO_SIZE_REG register */
1100         uint16_t fifo_size_bits;
1101         /*  last bits sent to HW_CONFIG_REG register */
1102         uint16_t hw_config_bits;
1103         uint16_t dac_control1_bits;
1104         /*  last bits written to plx9080 control register */
1105         uint32_t plx_control_bits;
1106         /*  last bits written to plx interrupt control and status register */
1107         uint32_t plx_intcsr_bits;
1108         /*  index of calibration source readable through ai ch0 */
1109         int calibration_source;
1110         /*  bits written to i2c calibration/range register */
1111         uint8_t i2c_cal_range_bits;
1112         /*  configure digital triggers to trigger on falling edge */
1113         unsigned int ext_trig_falling;
1114         /*  states of various devices stored to enable read-back */
1115         unsigned int ad8402_state[2];
1116         unsigned int caldac_state[8];
1117         short ai_cmd_running;
1118         unsigned int ai_fifo_segment_length;
1119         struct ext_clock_info ext_clock;
1120         unsigned short ao_bounce_buffer[DAC_FIFO_SIZE];
1121 };
1122 
1123 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1124                                        unsigned int range_index)
1125 {
1126         const struct pcidas64_board *thisboard = comedi_board(dev);
1127         const struct comedi_krange *range =
1128                 &thisboard->ai_range_table->range[range_index];
1129         unsigned int bits = 0;
1130 
1131         switch (range->max) {
1132         case 10000000:
1133                 bits = 0x000;
1134                 break;
1135         case 5000000:
1136                 bits = 0x100;
1137                 break;
1138         case 2000000:
1139         case 2500000:
1140                 bits = 0x200;
1141                 break;
1142         case 1000000:
1143         case 1250000:
1144                 bits = 0x300;
1145                 break;
1146         case 500000:
1147                 bits = 0x400;
1148                 break;
1149         case 200000:
1150         case 250000:
1151                 bits = 0x500;
1152                 break;
1153         case 100000:
1154                 bits = 0x600;
1155                 break;
1156         case 50000:
1157                 bits = 0x700;
1158                 break;
1159         default:
1160                 dev_err(dev->class_dev, "bug! in %s\n", __func__);
1161                 break;
1162         }
1163         if (range->min == 0)
1164                 bits += 0x900;
1165         return bits;
1166 }
1167 
1168 static unsigned int hw_revision(const struct comedi_device *dev,
1169                                 uint16_t hw_status_bits)
1170 {
1171         const struct pcidas64_board *thisboard = comedi_board(dev);
1172 
1173         if (thisboard->layout == LAYOUT_4020)
1174                 return (hw_status_bits >> 13) & 0x7;
1175 
1176         return (hw_status_bits >> 12) & 0xf;
1177 }
1178 
1179 static void set_dac_range_bits(struct comedi_device *dev,
1180                                uint16_t *bits, unsigned int channel,
1181                                unsigned int range)
1182 {
1183         const struct pcidas64_board *thisboard = comedi_board(dev);
1184         unsigned int code = thisboard->ao_range_code[range];
1185 
1186         if (channel > 1)
1187                 dev_err(dev->class_dev, "bug! bad channel?\n");
1188         if (code & ~0x3)
1189                 dev_err(dev->class_dev, "bug! bad range code?\n");
1190 
1191         *bits &= ~(0x3 << (2 * channel));
1192         *bits |= code << (2 * channel);
1193 };
1194 
1195 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1196 {
1197         return board->ao_nchan && board->layout != LAYOUT_4020;
1198 }
1199 
1200 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1201 {
1202         struct pcidas64_private *devpriv = dev->private;
1203         unsigned long flags;
1204 
1205         /*  spinlock for plx dma control/status reg */
1206         spin_lock_irqsave(&dev->spinlock, flags);
1207 
1208         plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1209 
1210         spin_unlock_irqrestore(&dev->spinlock, flags);
1211 }
1212 
1213 static void disable_plx_interrupts(struct comedi_device *dev)
1214 {
1215         struct pcidas64_private *devpriv = dev->private;
1216 
1217         devpriv->plx_intcsr_bits = 0;
1218         writel(devpriv->plx_intcsr_bits,
1219                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1220 }
1221 
1222 static void disable_ai_interrupts(struct comedi_device *dev)
1223 {
1224         struct pcidas64_private *devpriv = dev->private;
1225         unsigned long flags;
1226 
1227         spin_lock_irqsave(&dev->spinlock, flags);
1228         devpriv->intr_enable_bits &=
1229                 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1230                 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1231                 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1232         writew(devpriv->intr_enable_bits,
1233                devpriv->main_iobase + INTR_ENABLE_REG);
1234         spin_unlock_irqrestore(&dev->spinlock, flags);
1235 }
1236 
1237 static void enable_ai_interrupts(struct comedi_device *dev,
1238                                  const struct comedi_cmd *cmd)
1239 {
1240         const struct pcidas64_board *thisboard = comedi_board(dev);
1241         struct pcidas64_private *devpriv = dev->private;
1242         uint32_t bits;
1243         unsigned long flags;
1244 
1245         bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1246                EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1247         /*  Use pio transfer and interrupt on end of conversion
1248          *  if TRIG_WAKE_EOS flag is set. */
1249         if (cmd->flags & TRIG_WAKE_EOS) {
1250                 /*  4020 doesn't support pio transfers except for fifo dregs */
1251                 if (thisboard->layout != LAYOUT_4020)
1252                         bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1253         }
1254         spin_lock_irqsave(&dev->spinlock, flags);
1255         devpriv->intr_enable_bits |= bits;
1256         writew(devpriv->intr_enable_bits,
1257                devpriv->main_iobase + INTR_ENABLE_REG);
1258         spin_unlock_irqrestore(&dev->spinlock, flags);
1259 }
1260 
1261 /* initialize plx9080 chip */
1262 static void init_plx9080(struct comedi_device *dev)
1263 {
1264         const struct pcidas64_board *thisboard = comedi_board(dev);
1265         struct pcidas64_private *devpriv = dev->private;
1266         uint32_t bits;
1267         void __iomem *plx_iobase = devpriv->plx9080_iobase;
1268 
1269         devpriv->plx_control_bits =
1270                 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
1271 
1272 #ifdef __BIG_ENDIAN
1273         bits = BIGEND_DMA0 | BIGEND_DMA1;
1274 #else
1275         bits = 0;
1276 #endif
1277         writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
1278 
1279         disable_plx_interrupts(dev);
1280 
1281         abort_dma(dev, 0);
1282         abort_dma(dev, 1);
1283 
1284         /*  configure dma0 mode */
1285         bits = 0;
1286         /*  enable ready input, not sure if this is necessary */
1287         bits |= PLX_DMA_EN_READYIN_BIT;
1288         /*  enable bterm, not sure if this is necessary */
1289         bits |= PLX_EN_BTERM_BIT;
1290         /*  enable dma chaining */
1291         bits |= PLX_EN_CHAIN_BIT;
1292         /*  enable interrupt on dma done
1293          *  (probably don't need this, since chain never finishes) */
1294         bits |= PLX_EN_DMA_DONE_INTR_BIT;
1295         /*  don't increment local address during transfers
1296          *  (we are transferring from a fixed fifo register) */
1297         bits |= PLX_LOCAL_ADDR_CONST_BIT;
1298         /*  route dma interrupt to pci bus */
1299         bits |= PLX_DMA_INTR_PCI_BIT;
1300         /*  enable demand mode */
1301         bits |= PLX_DEMAND_MODE_BIT;
1302         /*  enable local burst mode */
1303         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1304         /*  4020 uses 32 bit dma */
1305         if (thisboard->layout == LAYOUT_4020)
1306                 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1307         else            /*  localspace0 bus is 16 bits wide */
1308                 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1309         writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1310         if (ao_cmd_is_supported(thisboard))
1311                 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1312 
1313         /*  enable interrupts on plx 9080 */
1314         devpriv->plx_intcsr_bits |=
1315             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1316             ICS_DMA0_E | ICS_DMA1_E;
1317         writel(devpriv->plx_intcsr_bits,
1318                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1319 }
1320 
1321 static void disable_ai_pacing(struct comedi_device *dev)
1322 {
1323         struct pcidas64_private *devpriv = dev->private;
1324         unsigned long flags;
1325 
1326         disable_ai_interrupts(dev);
1327 
1328         spin_lock_irqsave(&dev->spinlock, flags);
1329         devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1330         writew(devpriv->adc_control1_bits,
1331                devpriv->main_iobase + ADC_CONTROL1_REG);
1332         spin_unlock_irqrestore(&dev->spinlock, flags);
1333 
1334         /* disable pacing, triggering, etc */
1335         writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1336                devpriv->main_iobase + ADC_CONTROL0_REG);
1337 }
1338 
1339 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1340                                       unsigned int num_entries)
1341 {
1342         const struct pcidas64_board *thisboard = comedi_board(dev);
1343         struct pcidas64_private *devpriv = dev->private;
1344         static const int increment_size = 0x100;
1345         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1346         unsigned int num_increments;
1347         uint16_t bits;
1348 
1349         if (num_entries < increment_size)
1350                 num_entries = increment_size;
1351         if (num_entries > fifo->max_segment_length)
1352                 num_entries = fifo->max_segment_length;
1353 
1354         /*  1 == 256 entries, 2 == 512 entries, etc */
1355         num_increments = (num_entries + increment_size / 2) / increment_size;
1356 
1357         bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1358         devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1359         devpriv->fifo_size_bits |= bits;
1360         writew(devpriv->fifo_size_bits,
1361                devpriv->main_iobase + FIFO_SIZE_REG);
1362 
1363         devpriv->ai_fifo_segment_length = num_increments * increment_size;
1364 
1365         return devpriv->ai_fifo_segment_length;
1366 }
1367 
1368 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
1369 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1370 {
1371         const struct pcidas64_board *thisboard = comedi_board(dev);
1372         unsigned int num_fifo_entries;
1373         int retval;
1374         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1375 
1376         num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1377 
1378         retval = set_ai_fifo_segment_length(dev,
1379                                             num_fifo_entries /
1380                                             fifo->num_segments);
1381         if (retval < 0)
1382                 return retval;
1383 
1384         num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
1385 
1386         return num_samples;
1387 }
1388 
1389 /* query length of fifo */
1390 static unsigned int ai_fifo_size(struct comedi_device *dev)
1391 {
1392         const struct pcidas64_board *thisboard = comedi_board(dev);
1393         struct pcidas64_private *devpriv = dev->private;
1394 
1395         return devpriv->ai_fifo_segment_length *
1396                thisboard->ai_fifo->num_segments *
1397                thisboard->ai_fifo->sample_packing_ratio;
1398 }
1399 
1400 static void init_stc_registers(struct comedi_device *dev)
1401 {
1402         const struct pcidas64_board *thisboard = comedi_board(dev);
1403         struct pcidas64_private *devpriv = dev->private;
1404         uint16_t bits;
1405         unsigned long flags;
1406 
1407         spin_lock_irqsave(&dev->spinlock, flags);
1408 
1409         /*  bit should be set for 6025,
1410          *  although docs say boards with <= 16 chans should be cleared XXX */
1411         if (1)
1412                 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1413         writew(devpriv->adc_control1_bits,
1414                devpriv->main_iobase + ADC_CONTROL1_REG);
1415 
1416         /*  6402/16 manual says this register must be initialized to 0xff? */
1417         writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1418 
1419         bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1420         if (thisboard->layout == LAYOUT_4020)
1421                 bits |= INTERNAL_CLOCK_4020_BITS;
1422         devpriv->hw_config_bits |= bits;
1423         writew(devpriv->hw_config_bits,
1424                devpriv->main_iobase + HW_CONFIG_REG);
1425 
1426         writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1427         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1428 
1429         spin_unlock_irqrestore(&dev->spinlock, flags);
1430 
1431         /*  set fifos to maximum size */
1432         devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1433         set_ai_fifo_segment_length(dev,
1434                                    thisboard->ai_fifo->max_segment_length);
1435 
1436         devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1437         devpriv->intr_enable_bits =
1438                 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1439                 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1440         writew(devpriv->intr_enable_bits,
1441                devpriv->main_iobase + INTR_ENABLE_REG);
1442 
1443         disable_ai_pacing(dev);
1444 };
1445 
1446 static int alloc_and_init_dma_members(struct comedi_device *dev)
1447 {
1448         const struct pcidas64_board *thisboard = comedi_board(dev);
1449         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1450         struct pcidas64_private *devpriv = dev->private;
1451         int i;
1452 
1453         /*  allocate pci dma buffers */
1454         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1455                 devpriv->ai_buffer[i] =
1456                         pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1457                                              &devpriv->ai_buffer_bus_addr[i]);
1458                 if (devpriv->ai_buffer[i] == NULL)
1459                         return -ENOMEM;
1460 
1461         }
1462         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1463                 if (ao_cmd_is_supported(thisboard)) {
1464                         devpriv->ao_buffer[i] =
1465                                 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1466                                                      &devpriv->
1467                                                       ao_buffer_bus_addr[i]);
1468                         if (devpriv->ao_buffer[i] == NULL)
1469                                 return -ENOMEM;
1470 
1471                 }
1472         }
1473         /*  allocate dma descriptors */
1474         devpriv->ai_dma_desc =
1475                 pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) *
1476                                      ai_dma_ring_count(thisboard),
1477                                      &devpriv->ai_dma_desc_bus_addr);
1478         if (devpriv->ai_dma_desc == NULL)
1479                 return -ENOMEM;
1480 
1481         if (ao_cmd_is_supported(thisboard)) {
1482                 devpriv->ao_dma_desc =
1483                         pci_alloc_consistent(pcidev,
1484                                              sizeof(struct plx_dma_desc) *
1485                                              AO_DMA_RING_COUNT,
1486                                              &devpriv->ao_dma_desc_bus_addr);
1487                 if (devpriv->ao_dma_desc == NULL)
1488                         return -ENOMEM;
1489         }
1490         /*  initialize dma descriptors */
1491         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1492                 devpriv->ai_dma_desc[i].pci_start_addr =
1493                         cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1494                 if (thisboard->layout == LAYOUT_4020)
1495                         devpriv->ai_dma_desc[i].local_start_addr =
1496                                 cpu_to_le32(devpriv->local1_iobase +
1497                                             ADC_FIFO_REG);
1498                 else
1499                         devpriv->ai_dma_desc[i].local_start_addr =
1500                                 cpu_to_le32(devpriv->local0_iobase +
1501                                             ADC_FIFO_REG);
1502                 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1503                 devpriv->ai_dma_desc[i].next =
1504                         cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1505                                      ((i + 1) % ai_dma_ring_count(thisboard)) *
1506                                      sizeof(devpriv->ai_dma_desc[0])) |
1507                                     PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1508                                     PLX_XFER_LOCAL_TO_PCI);
1509         }
1510         if (ao_cmd_is_supported(thisboard)) {
1511                 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1512                         devpriv->ao_dma_desc[i].pci_start_addr =
1513                                 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1514                         devpriv->ao_dma_desc[i].local_start_addr =
1515                                 cpu_to_le32(devpriv->local0_iobase +
1516                                             DAC_FIFO_REG);
1517                         devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1518                         devpriv->ao_dma_desc[i].next =
1519                                 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1520                                              ((i + 1) % (AO_DMA_RING_COUNT)) *
1521                                              sizeof(devpriv->ao_dma_desc[0])) |
1522                                             PLX_DESC_IN_PCI_BIT |
1523                                             PLX_INTR_TERM_COUNT);
1524                 }
1525         }
1526         return 0;
1527 }
1528 
1529 static inline void warn_external_queue(struct comedi_device *dev)
1530 {
1531         dev_err(dev->class_dev,
1532                 "AO command and AI external channel queue cannot be used simultaneously\n");
1533         dev_err(dev->class_dev,
1534                 "Use internal AI channel queue (channels must be consecutive and use same range/aref)\n");
1535 }
1536 
1537 /* Their i2c requires a huge delay on setting clock or data high for some reason */
1538 static const int i2c_high_udelay = 1000;
1539 static const int i2c_low_udelay = 10;
1540 
1541 /* set i2c data line high or low */
1542 static void i2c_set_sda(struct comedi_device *dev, int state)
1543 {
1544         struct pcidas64_private *devpriv = dev->private;
1545         static const int data_bit = CTL_EE_W;
1546         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1547                                          PLX_CONTROL_REG;
1548 
1549         if (state) {
1550                 /*  set data line high */
1551                 devpriv->plx_control_bits &= ~data_bit;
1552                 writel(devpriv->plx_control_bits, plx_control_addr);
1553                 udelay(i2c_high_udelay);
1554         } else {                /*  set data line low */
1555 
1556                 devpriv->plx_control_bits |= data_bit;
1557                 writel(devpriv->plx_control_bits, plx_control_addr);
1558                 udelay(i2c_low_udelay);
1559         }
1560 }
1561 
1562 /* set i2c clock line high or low */
1563 static void i2c_set_scl(struct comedi_device *dev, int state)
1564 {
1565         struct pcidas64_private *devpriv = dev->private;
1566         static const int clock_bit = CTL_USERO;
1567         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1568                                          PLX_CONTROL_REG;
1569 
1570         if (state) {
1571                 /*  set clock line high */
1572                 devpriv->plx_control_bits &= ~clock_bit;
1573                 writel(devpriv->plx_control_bits, plx_control_addr);
1574                 udelay(i2c_high_udelay);
1575         } else {                /*  set clock line low */
1576 
1577                 devpriv->plx_control_bits |= clock_bit;
1578                 writel(devpriv->plx_control_bits, plx_control_addr);
1579                 udelay(i2c_low_udelay);
1580         }
1581 }
1582 
1583 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
1584 {
1585         uint8_t bit;
1586         unsigned int num_bits = 8;
1587 
1588         for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1589                 i2c_set_scl(dev, 0);
1590                 if ((byte & bit))
1591                         i2c_set_sda(dev, 1);
1592                 else
1593                         i2c_set_sda(dev, 0);
1594                 i2c_set_scl(dev, 1);
1595         }
1596 }
1597 
1598 /* we can't really read the lines, so fake it */
1599 static int i2c_read_ack(struct comedi_device *dev)
1600 {
1601         i2c_set_scl(dev, 0);
1602         i2c_set_sda(dev, 1);
1603         i2c_set_scl(dev, 1);
1604 
1605         return 0;               /*  return fake acknowledge bit */
1606 }
1607 
1608 /* send start bit */
1609 static void i2c_start(struct comedi_device *dev)
1610 {
1611         i2c_set_scl(dev, 1);
1612         i2c_set_sda(dev, 1);
1613         i2c_set_sda(dev, 0);
1614 }
1615 
1616 /* send stop bit */
1617 static void i2c_stop(struct comedi_device *dev)
1618 {
1619         i2c_set_scl(dev, 0);
1620         i2c_set_sda(dev, 0);
1621         i2c_set_scl(dev, 1);
1622         i2c_set_sda(dev, 1);
1623 }
1624 
1625 static void i2c_write(struct comedi_device *dev, unsigned int address,
1626                       const uint8_t *data, unsigned int length)
1627 {
1628         struct pcidas64_private *devpriv = dev->private;
1629         unsigned int i;
1630         uint8_t bitstream;
1631         static const int read_bit = 0x1;
1632 
1633         /* XXX need mutex to prevent simultaneous attempts to access
1634          * eeprom and i2c bus */
1635 
1636         /*  make sure we dont send anything to eeprom */
1637         devpriv->plx_control_bits &= ~CTL_EE_CS;
1638 
1639         i2c_stop(dev);
1640         i2c_start(dev);
1641 
1642         /*  send address and write bit */
1643         bitstream = (address << 1) & ~read_bit;
1644         i2c_write_byte(dev, bitstream);
1645 
1646         /*  get acknowledge */
1647         if (i2c_read_ack(dev) != 0) {
1648                 dev_err(dev->class_dev, "%s failed: no acknowledge\n",
1649                         __func__);
1650                 i2c_stop(dev);
1651                 return;
1652         }
1653         /*  write data bytes */
1654         for (i = 0; i < length; i++) {
1655                 i2c_write_byte(dev, data[i]);
1656                 if (i2c_read_ack(dev) != 0) {
1657                         dev_err(dev->class_dev, "%s failed: no acknowledge\n",
1658                                 __func__);
1659                         i2c_stop(dev);
1660                         return;
1661                 }
1662         }
1663         i2c_stop(dev);
1664 }
1665 
1666 static int cb_pcidas64_ai_eoc(struct comedi_device *dev,
1667                               struct comedi_subdevice *s,
1668                               struct comedi_insn *insn,
1669                               unsigned long context)
1670 {
1671         const struct pcidas64_board *thisboard = comedi_board(dev);
1672         struct pcidas64_private *devpriv = dev->private;
1673         unsigned int status;
1674 
1675         status = readw(devpriv->main_iobase + HW_STATUS_REG);
1676         if (thisboard->layout == LAYOUT_4020) {
1677                 status = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG);
1678                 if (status)
1679                         return 0;
1680         } else {
1681                 if (pipe_full_bits(status))
1682                         return 0;
1683         }
1684         return -EBUSY;
1685 }
1686 
1687 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1688                     struct comedi_insn *insn, unsigned int *data)
1689 {
1690         const struct pcidas64_board *thisboard = comedi_board(dev);
1691         struct pcidas64_private *devpriv = dev->private;
1692         unsigned int bits = 0, n;
1693         unsigned int channel, range, aref;
1694         unsigned long flags;
1695         int ret;
1696 
1697         channel = CR_CHAN(insn->chanspec);
1698         range = CR_RANGE(insn->chanspec);
1699         aref = CR_AREF(insn->chanspec);
1700 
1701         /*  disable card's analog input interrupt sources and pacing */
1702         /*  4020 generates dac done interrupts even though they are disabled */
1703         disable_ai_pacing(dev);
1704 
1705         spin_lock_irqsave(&dev->spinlock, flags);
1706         if (insn->chanspec & CR_ALT_FILTER)
1707                 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1708         else
1709                 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1710         writew(devpriv->adc_control1_bits,
1711                devpriv->main_iobase + ADC_CONTROL1_REG);
1712         spin_unlock_irqrestore(&dev->spinlock, flags);
1713 
1714         if (thisboard->layout != LAYOUT_4020) {
1715                 /*  use internal queue */
1716                 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1717                 writew(devpriv->hw_config_bits,
1718                        devpriv->main_iobase + HW_CONFIG_REG);
1719 
1720                 /*  ALT_SOURCE is internal calibration reference */
1721                 if (insn->chanspec & CR_ALT_SOURCE) {
1722                         unsigned int cal_en_bit;
1723 
1724                         if (thisboard->layout == LAYOUT_60XX)
1725                                 cal_en_bit = CAL_EN_60XX_BIT;
1726                         else
1727                                 cal_en_bit = CAL_EN_64XX_BIT;
1728                         /*  select internal reference source to connect
1729                          *  to channel 0 */
1730                         writew(cal_en_bit |
1731                                adc_src_bits(devpriv->calibration_source),
1732                                devpriv->main_iobase + CALIBRATION_REG);
1733                 } else {
1734                         /*  make sure internal calibration source
1735                          *  is turned off */
1736                         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1737                 }
1738                 /*  load internal queue */
1739                 bits = 0;
1740                 /*  set gain */
1741                 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1742                 /*  set single-ended / differential */
1743                 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1744                 if (aref == AREF_COMMON)
1745                         bits |= ADC_COMMON_BIT;
1746                 bits |= adc_chan_bits(channel);
1747                 /*  set stop channel */
1748                 writew(adc_chan_bits(channel),
1749                        devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1750                 /*  set start channel, and rest of settings */
1751                 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1752         } else {
1753                 uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1754 
1755                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1756                 if (insn->chanspec & CR_ALT_SOURCE) {
1757                         devpriv->i2c_cal_range_bits |=
1758                                 adc_src_4020_bits(devpriv->calibration_source);
1759                 } else {        /* select BNC inputs */
1760                         devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1761                 }
1762                 /*  select range */
1763                 if (range == 0)
1764                         devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1765                 else
1766                         devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1767                 /*  update calibration/range i2c register only if necessary,
1768                  *  as it is very slow */
1769                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1770                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1771 
1772                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1773                                   sizeof(i2c_data));
1774                 }
1775 
1776                 /* 4020 manual asks that sample interval register to be set
1777                  * before writing to convert register.
1778                  * Using somewhat arbitrary setting of 4 master clock ticks
1779                  * = 0.1 usec */
1780                 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1781                 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1782         }
1783 
1784         for (n = 0; n < insn->n; n++) {
1785 
1786                 /*  clear adc buffer (inside loop for 4020 sake) */
1787                 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1788 
1789                 /* trigger conversion, bits sent only matter for 4020 */
1790                 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1791                        devpriv->main_iobase + ADC_CONVERT_REG);
1792 
1793                 /*  wait for data */
1794                 ret = comedi_timeout(dev, s, insn, cb_pcidas64_ai_eoc, 0);
1795                 if (ret)
1796                         return ret;
1797 
1798                 if (thisboard->layout == LAYOUT_4020)
1799                         data[n] = readl(dev->mmio + ADC_FIFO_REG) & 0xffff;
1800                 else
1801                         data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1802         }
1803 
1804         return n;
1805 }
1806 
1807 static int ai_config_calibration_source(struct comedi_device *dev,
1808                                         unsigned int *data)
1809 {
1810         const struct pcidas64_board *thisboard = comedi_board(dev);
1811         struct pcidas64_private *devpriv = dev->private;
1812         unsigned int source = data[1];
1813         int num_calibration_sources;
1814 
1815         if (thisboard->layout == LAYOUT_60XX)
1816                 num_calibration_sources = 16;
1817         else
1818                 num_calibration_sources = 8;
1819         if (source >= num_calibration_sources) {
1820                 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1821                         source);
1822                 return -EINVAL;
1823         }
1824 
1825         devpriv->calibration_source = source;
1826 
1827         return 2;
1828 }
1829 
1830 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1831 {
1832         const struct pcidas64_board *thisboard = comedi_board(dev);
1833         int fifo_size;
1834         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1835         unsigned int block_size, requested_block_size;
1836         int retval;
1837 
1838         requested_block_size = data[1];
1839 
1840         if (requested_block_size) {
1841                 fifo_size = requested_block_size * fifo->num_segments /
1842                             bytes_in_sample;
1843 
1844                 retval = set_ai_fifo_size(dev, fifo_size);
1845                 if (retval < 0)
1846                         return retval;
1847 
1848         }
1849 
1850         block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1851 
1852         data[1] = block_size;
1853 
1854         return 2;
1855 }
1856 
1857 static int ai_config_master_clock_4020(struct comedi_device *dev,
1858                                        unsigned int *data)
1859 {
1860         struct pcidas64_private *devpriv = dev->private;
1861         unsigned int divisor = data[4];
1862         int retval = 0;
1863 
1864         if (divisor < 2) {
1865                 divisor = 2;
1866                 retval = -EAGAIN;
1867         }
1868 
1869         switch (data[1]) {
1870         case COMEDI_EV_SCAN_BEGIN:
1871                 devpriv->ext_clock.divisor = divisor;
1872                 devpriv->ext_clock.chanspec = data[2];
1873                 break;
1874         default:
1875                 return -EINVAL;
1876         }
1877 
1878         data[4] = divisor;
1879 
1880         return retval ? retval : 5;
1881 }
1882 
1883 /* XXX could add support for 60xx series */
1884 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1885 {
1886         const struct pcidas64_board *thisboard = comedi_board(dev);
1887 
1888         switch (thisboard->layout) {
1889         case LAYOUT_4020:
1890                 return ai_config_master_clock_4020(dev, data);
1891         default:
1892                 return -EINVAL;
1893         }
1894 
1895         return -EINVAL;
1896 }
1897 
1898 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1899                           struct comedi_insn *insn, unsigned int *data)
1900 {
1901         int id = data[0];
1902 
1903         switch (id) {
1904         case INSN_CONFIG_ALT_SOURCE:
1905                 return ai_config_calibration_source(dev, data);
1906         case INSN_CONFIG_BLOCK_SIZE:
1907                 return ai_config_block_size(dev, data);
1908         case INSN_CONFIG_TIMER_1:
1909                 return ai_config_master_clock(dev, data);
1910         default:
1911                 return -EINVAL;
1912         }
1913         return -EINVAL;
1914 }
1915 
1916 /* Gets nearest achievable timing given master clock speed, does not
1917  * take into account possible minimum/maximum divisor values.  Used
1918  * by other timing checking functions. */
1919 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
1920 {
1921         unsigned int divisor;
1922 
1923         switch (flags & TRIG_ROUND_MASK) {
1924         case TRIG_ROUND_UP:
1925                 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
1926                 break;
1927         case TRIG_ROUND_DOWN:
1928                 divisor = ns / TIMER_BASE;
1929                 break;
1930         case TRIG_ROUND_NEAREST:
1931         default:
1932                 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
1933                 break;
1934         }
1935         return divisor;
1936 }
1937 
1938 /* utility function that rounds desired timing to an achievable time, and
1939  * sets cmd members appropriately.
1940  * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
1941  */
1942 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
1943 {
1944         const struct pcidas64_board *thisboard = comedi_board(dev);
1945         unsigned int convert_divisor = 0, scan_divisor;
1946         static const int min_convert_divisor = 3;
1947         static const int max_convert_divisor =
1948                 max_counter_value + min_convert_divisor;
1949         static const int min_scan_divisor_4020 = 2;
1950         unsigned long long max_scan_divisor, min_scan_divisor;
1951 
1952         if (cmd->convert_src == TRIG_TIMER) {
1953                 if (thisboard->layout == LAYOUT_4020) {
1954                         cmd->convert_arg = 0;
1955                 } else {
1956                         convert_divisor = get_divisor(cmd->convert_arg,
1957                                                       cmd->flags);
1958                         if (convert_divisor > max_convert_divisor)
1959                                 convert_divisor = max_convert_divisor;
1960                         if (convert_divisor < min_convert_divisor)
1961                                 convert_divisor = min_convert_divisor;
1962                         cmd->convert_arg = convert_divisor * TIMER_BASE;
1963                 }
1964         } else if (cmd->convert_src == TRIG_NOW) {
1965                 cmd->convert_arg = 0;
1966         }
1967 
1968         if (cmd->scan_begin_src == TRIG_TIMER) {
1969                 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
1970                 if (cmd->convert_src == TRIG_TIMER) {
1971                         /*  XXX check for integer overflows */
1972                         min_scan_divisor = convert_divisor * cmd->chanlist_len;
1973                         max_scan_divisor =
1974                                 (convert_divisor * cmd->chanlist_len - 1) +
1975                                 max_counter_value;
1976                 } else {
1977                         min_scan_divisor = min_scan_divisor_4020;
1978                         max_scan_divisor = max_counter_value + min_scan_divisor;
1979                 }
1980                 if (scan_divisor > max_scan_divisor)
1981                         scan_divisor = max_scan_divisor;
1982                 if (scan_divisor < min_scan_divisor)
1983                         scan_divisor = min_scan_divisor;
1984                 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
1985         }
1986 }
1987 
1988 static int cb_pcidas64_ai_check_chanlist(struct comedi_device *dev,
1989                                          struct comedi_subdevice *s,
1990                                          struct comedi_cmd *cmd)
1991 {
1992         const struct pcidas64_board *board = comedi_board(dev);
1993         unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
1994         int i;
1995 
1996         for (i = 1; i < cmd->chanlist_len; i++) {
1997                 unsigned int aref = CR_AREF(cmd->chanlist[i]);
1998 
1999                 if (aref != aref0) {
2000                         dev_dbg(dev->class_dev,
2001                                 "all elements in chanlist must use the same analog reference\n");
2002                         return -EINVAL;
2003                 }
2004         }
2005 
2006         if (board->layout == LAYOUT_4020) {
2007                 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
2008 
2009                 for (i = 1; i < cmd->chanlist_len; i++) {
2010                         unsigned int chan = CR_CHAN(cmd->chanlist[i]);
2011 
2012                         if (chan != (chan0 + i)) {
2013                                 dev_dbg(dev->class_dev,
2014                                         "chanlist must use consecutive channels\n");
2015                                 return -EINVAL;
2016                         }
2017                 }
2018                 if (cmd->chanlist_len == 3) {
2019                         dev_dbg(dev->class_dev,
2020                                 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels\n");
2021                         return -EINVAL;
2022                 }
2023         }
2024 
2025         return 0;
2026 }
2027 
2028 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2029                       struct comedi_cmd *cmd)
2030 {
2031         const struct pcidas64_board *thisboard = comedi_board(dev);
2032         int err = 0;
2033         unsigned int tmp_arg, tmp_arg2;
2034         unsigned int triggers;
2035 
2036         /* Step 1 : check if triggers are trivially valid */
2037 
2038         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2039 
2040         triggers = TRIG_TIMER;
2041         if (thisboard->layout == LAYOUT_4020)
2042                 triggers |= TRIG_OTHER;
2043         else
2044                 triggers |= TRIG_FOLLOW;
2045         err |= cfc_check_trigger_src(&cmd->scan_begin_src, triggers);
2046 
2047         triggers = TRIG_TIMER;
2048         if (thisboard->layout == LAYOUT_4020)
2049                 triggers |= TRIG_NOW;
2050         else
2051                 triggers |= TRIG_EXT;
2052         err |= cfc_check_trigger_src(&cmd->convert_src, triggers);
2053         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2054         err |= cfc_check_trigger_src(&cmd->stop_src,
2055                                      TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2056 
2057         if (err)
2058                 return 1;
2059 
2060         /* Step 2a : make sure trigger sources are unique */
2061 
2062         err |= cfc_check_trigger_is_unique(cmd->start_src);
2063         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2064         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2065         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2066 
2067         /* Step 2b : and mutually compatible */
2068 
2069         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2070                 err |= -EINVAL;
2071 
2072         if (err)
2073                 return 2;
2074 
2075         /* Step 3: check if arguments are trivially valid */
2076 
2077         switch (cmd->start_src) {
2078         case TRIG_NOW:
2079                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2080                 break;
2081         case TRIG_EXT:
2082                 /*
2083                  * start_arg is the CR_CHAN | CR_INVERT of the
2084                  * external trigger.
2085                  */
2086                 break;
2087         }
2088 
2089         if (cmd->convert_src == TRIG_TIMER) {
2090                 if (thisboard->layout == LAYOUT_4020) {
2091                         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2092                 } else {
2093                         err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2094                                                          thisboard->ai_speed);
2095                         /* if scans are timed faster than conversion rate allows */
2096                         if (cmd->scan_begin_src == TRIG_TIMER)
2097                                 err |= cfc_check_trigger_arg_min(
2098                                                 &cmd->scan_begin_arg,
2099                                                 cmd->convert_arg *
2100                                                 cmd->chanlist_len);
2101                 }
2102         }
2103 
2104         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
2105         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2106 
2107         switch (cmd->stop_src) {
2108         case TRIG_EXT:
2109                 break;
2110         case TRIG_COUNT:
2111                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2112                 break;
2113         case TRIG_NONE:
2114                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2115                 break;
2116         default:
2117                 break;
2118         }
2119 
2120         if (err)
2121                 return 3;
2122 
2123         /* step 4: fix up any arguments */
2124 
2125         if (cmd->convert_src == TRIG_TIMER) {
2126                 tmp_arg = cmd->convert_arg;
2127                 tmp_arg2 = cmd->scan_begin_arg;
2128                 check_adc_timing(dev, cmd);
2129                 if (tmp_arg != cmd->convert_arg)
2130                         err++;
2131                 if (tmp_arg2 != cmd->scan_begin_arg)
2132                         err++;
2133         }
2134 
2135         if (err)
2136                 return 4;
2137 
2138         /* Step 5: check channel list if it exists */
2139         if (cmd->chanlist && cmd->chanlist_len > 0)
2140                 err |= cb_pcidas64_ai_check_chanlist(dev, s, cmd);
2141 
2142         if (err)
2143                 return 5;
2144 
2145         return 0;
2146 }
2147 
2148 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2149 {
2150 /* disable for now until I work out a race */
2151         return 0;
2152 
2153         if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2154                 return 1;
2155 
2156         return 0;
2157 }
2158 
2159 static void setup_sample_counters(struct comedi_device *dev,
2160                                   struct comedi_cmd *cmd)
2161 {
2162         struct pcidas64_private *devpriv = dev->private;
2163 
2164         if (cmd->stop_src == TRIG_COUNT) {
2165                 /*  set software count */
2166                 devpriv->ai_count = cmd->stop_arg * cmd->chanlist_len;
2167         }
2168         /*  load hardware conversion counter */
2169         if (use_hw_sample_counter(cmd)) {
2170                 writew(cmd->stop_arg & 0xffff,
2171                        devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2172                 writew((cmd->stop_arg >> 16) & 0xff,
2173                        devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2174         } else {
2175                 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2176         }
2177 }
2178 
2179 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2180 {
2181         const struct pcidas64_board *thisboard = comedi_board(dev);
2182         struct pcidas64_private *devpriv = dev->private;
2183         unsigned int num_samples;
2184 
2185         num_samples = devpriv->ai_fifo_segment_length *
2186                       thisboard->ai_fifo->sample_packing_ratio;
2187         if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2188                 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2189 
2190         return num_samples;
2191 }
2192 
2193 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2194                                         const struct comedi_cmd *cmd)
2195 {
2196         /*  supposed to load counter with desired divisor minus 3 */
2197         return cmd->convert_arg / TIMER_BASE - 3;
2198 }
2199 
2200 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2201                                      struct comedi_cmd *cmd)
2202 {
2203         uint32_t count;
2204 
2205         /*  figure out how long we need to delay at end of scan */
2206         switch (cmd->scan_begin_src) {
2207         case TRIG_TIMER:
2208                 count = (cmd->scan_begin_arg -
2209                          (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2210                         TIMER_BASE;
2211                 break;
2212         case TRIG_FOLLOW:
2213                 count = cmd->convert_arg / TIMER_BASE;
2214                 break;
2215         default:
2216                 return 0;
2217         }
2218         return count - 3;
2219 }
2220 
2221 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2222                                         struct comedi_cmd *cmd)
2223 {
2224         struct pcidas64_private *devpriv = dev->private;
2225         unsigned int divisor;
2226 
2227         switch (cmd->scan_begin_src) {
2228         case TRIG_TIMER:
2229                 divisor = cmd->scan_begin_arg / TIMER_BASE;
2230                 break;
2231         case TRIG_OTHER:
2232                 divisor = devpriv->ext_clock.divisor;
2233                 break;
2234         default:                /*  should never happen */
2235                 dev_err(dev->class_dev, "bug! failed to set ai pacing!\n");
2236                 divisor = 1000;
2237                 break;
2238         }
2239 
2240         /*  supposed to load counter with desired divisor minus 2 for 4020 */
2241         return divisor - 2;
2242 }
2243 
2244 static void select_master_clock_4020(struct comedi_device *dev,
2245                                      const struct comedi_cmd *cmd)
2246 {
2247         struct pcidas64_private *devpriv = dev->private;
2248 
2249         /*  select internal/external master clock */
2250         devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2251         if (cmd->scan_begin_src == TRIG_OTHER) {
2252                 int chanspec = devpriv->ext_clock.chanspec;
2253 
2254                 if (CR_CHAN(chanspec))
2255                         devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2256                 else
2257                         devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2258         } else {
2259                 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2260         }
2261         writew(devpriv->hw_config_bits,
2262                devpriv->main_iobase + HW_CONFIG_REG);
2263 }
2264 
2265 static void select_master_clock(struct comedi_device *dev,
2266                                 const struct comedi_cmd *cmd)
2267 {
2268         const struct pcidas64_board *thisboard = comedi_board(dev);
2269 
2270         switch (thisboard->layout) {
2271         case LAYOUT_4020:
2272                 select_master_clock_4020(dev, cmd);
2273                 break;
2274         default:
2275                 break;
2276         }
2277 }
2278 
2279 static inline void dma_start_sync(struct comedi_device *dev,
2280                                   unsigned int channel)
2281 {
2282         struct pcidas64_private *devpriv = dev->private;
2283         unsigned long flags;
2284 
2285         /*  spinlock for plx dma control/status reg */
2286         spin_lock_irqsave(&dev->spinlock, flags);
2287         if (channel)
2288                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2289                        PLX_CLEAR_DMA_INTR_BIT,
2290                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2291         else
2292                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2293                        PLX_CLEAR_DMA_INTR_BIT,
2294                        devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2295         spin_unlock_irqrestore(&dev->spinlock, flags);
2296 }
2297 
2298 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2299 {
2300         const struct pcidas64_board *thisboard = comedi_board(dev);
2301         struct pcidas64_private *devpriv = dev->private;
2302         uint32_t convert_counter = 0, scan_counter = 0;
2303 
2304         check_adc_timing(dev, cmd);
2305 
2306         select_master_clock(dev, cmd);
2307 
2308         if (thisboard->layout == LAYOUT_4020) {
2309                 convert_counter = ai_convert_counter_4020(dev, cmd);
2310         } else {
2311                 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2312                 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2313         }
2314 
2315         /*  load lower 16 bits of convert interval */
2316         writew(convert_counter & 0xffff,
2317                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2318         /*  load upper 8 bits of convert interval */
2319         writew((convert_counter >> 16) & 0xff,
2320                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2321         /*  load lower 16 bits of scan delay */
2322         writew(scan_counter & 0xffff,
2323                devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2324         /*  load upper 8 bits of scan delay */
2325         writew((scan_counter >> 16) & 0xff,
2326                devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2327 }
2328 
2329 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2330 {
2331         int i;
2332 
2333         for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2334                 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2335                     CR_CHAN(cmd->chanlist[i]) + 1)
2336                         return 0;
2337                 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2338                     CR_RANGE(cmd->chanlist[i]))
2339                         return 0;
2340                 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2341                         return 0;
2342         }
2343         return 1;
2344 }
2345 
2346 static int setup_channel_queue(struct comedi_device *dev,
2347                                const struct comedi_cmd *cmd)
2348 {
2349         const struct pcidas64_board *thisboard = comedi_board(dev);
2350         struct pcidas64_private *devpriv = dev->private;
2351         unsigned short bits;
2352         int i;
2353 
2354         if (thisboard->layout != LAYOUT_4020) {
2355                 if (use_internal_queue_6xxx(cmd)) {
2356                         devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2357                         writew(devpriv->hw_config_bits,
2358                                devpriv->main_iobase + HW_CONFIG_REG);
2359                         bits = 0;
2360                         /*  set channel */
2361                         bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2362                         /*  set gain */
2363                         bits |= ai_range_bits_6xxx(dev,
2364                                                    CR_RANGE(cmd->chanlist[0]));
2365                         /*  set single-ended / differential */
2366                         bits |= se_diff_bit_6xxx(dev,
2367                                                  CR_AREF(cmd->chanlist[0]) ==
2368                                                  AREF_DIFF);
2369                         if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2370                                 bits |= ADC_COMMON_BIT;
2371                         /*  set stop channel */
2372                         writew(adc_chan_bits
2373                                (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2374                                devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2375                         /*  set start channel, and rest of settings */
2376                         writew(bits,
2377                                devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2378                 } else {
2379                         /*  use external queue */
2380                         if (dev->write_subdev && dev->write_subdev->busy) {
2381                                 warn_external_queue(dev);
2382                                 return -EBUSY;
2383                         }
2384                         devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2385                         writew(devpriv->hw_config_bits,
2386                                devpriv->main_iobase + HW_CONFIG_REG);
2387                         /*  clear DAC buffer to prevent weird interactions */
2388                         writew(0,
2389                                devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2390                         /*  clear queue pointer */
2391                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2392                         /*  load external queue */
2393                         for (i = 0; i < cmd->chanlist_len; i++) {
2394                                 bits = 0;
2395                                 /*  set channel */
2396                                 bits |= adc_chan_bits(CR_CHAN(cmd->
2397                                                               chanlist[i]));
2398                                 /*  set gain */
2399                                 bits |= ai_range_bits_6xxx(dev,
2400                                                            CR_RANGE(cmd->
2401                                                                     chanlist
2402                                                                     [i]));
2403                                 /*  set single-ended / differential */
2404                                 bits |= se_diff_bit_6xxx(dev,
2405                                                          CR_AREF(cmd->
2406                                                                  chanlist[i]) ==
2407                                                          AREF_DIFF);
2408                                 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2409                                         bits |= ADC_COMMON_BIT;
2410                                 /*  mark end of queue */
2411                                 if (i == cmd->chanlist_len - 1)
2412                                         bits |= QUEUE_EOSCAN_BIT |
2413                                                 QUEUE_EOSEQ_BIT;
2414                                 writew(bits,
2415                                        devpriv->main_iobase +
2416                                        ADC_QUEUE_FIFO_REG);
2417                         }
2418                         /* doing a queue clear is not specified in board docs,
2419                          * but required for reliable operation */
2420                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2421                         /*  prime queue holding register */
2422                         writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2423                 }
2424         } else {
2425                 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2426 
2427                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2428                 /* select BNC inputs */
2429                 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2430                 /*  select ranges */
2431                 for (i = 0; i < cmd->chanlist_len; i++) {
2432                         unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2433                         unsigned int range = CR_RANGE(cmd->chanlist[i]);
2434 
2435                         if (range == 0)
2436                                 devpriv->i2c_cal_range_bits |=
2437                                         attenuate_bit(channel);
2438                         else
2439                                 devpriv->i2c_cal_range_bits &=
2440                                         ~attenuate_bit(channel);
2441                 }
2442                 /*  update calibration/range i2c register only if necessary,
2443                  *  as it is very slow */
2444                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2445                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2446 
2447                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2448                                   sizeof(i2c_data));
2449                 }
2450         }
2451         return 0;
2452 }
2453 
2454 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2455                                              unsigned int dma_channel,
2456                                              unsigned int descriptor_bits)
2457 {
2458         struct pcidas64_private *devpriv = dev->private;
2459 
2460         /* The transfer size, pci address, and local address registers
2461          * are supposedly unused during chained dma,
2462          * but I have found that left over values from last operation
2463          * occasionally cause problems with transfer of first dma
2464          * block.  Initializing them to zero seems to fix the problem. */
2465         if (dma_channel) {
2466                 writel(0,
2467                        devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2468                 writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2469                 writel(0,
2470                        devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2471                 writel(descriptor_bits,
2472                        devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2473         } else {
2474                 writel(0,
2475                        devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2476                 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2477                 writel(0,
2478                        devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2479                 writel(descriptor_bits,
2480                        devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2481         }
2482 }
2483 
2484 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2485 {
2486         const struct pcidas64_board *thisboard = comedi_board(dev);
2487         struct pcidas64_private *devpriv = dev->private;
2488         struct comedi_async *async = s->async;
2489         struct comedi_cmd *cmd = &async->cmd;
2490         uint32_t bits;
2491         unsigned int i;
2492         unsigned long flags;
2493         int retval;
2494 
2495         disable_ai_pacing(dev);
2496         abort_dma(dev, 1);
2497 
2498         retval = setup_channel_queue(dev, cmd);
2499         if (retval < 0)
2500                 return retval;
2501 
2502         /*  make sure internal calibration source is turned off */
2503         writew(0, devpriv->main_iobase + CALIBRATION_REG);
2504 
2505         set_ai_pacing(dev, cmd);
2506 
2507         setup_sample_counters(dev, cmd);
2508 
2509         enable_ai_interrupts(dev, cmd);
2510 
2511         spin_lock_irqsave(&dev->spinlock, flags);
2512         /* set mode, allow conversions through software gate */
2513         devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2514         devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2515         if (thisboard->layout != LAYOUT_4020) {
2516                 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2517                 if (cmd->convert_src == TRIG_EXT)
2518                         /*  good old mode 13 */
2519                         devpriv->adc_control1_bits |= adc_mode_bits(13);
2520                 else
2521                         /*  mode 8.  What else could you need? */
2522                         devpriv->adc_control1_bits |= adc_mode_bits(8);
2523         } else {
2524                 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2525                 if (cmd->chanlist_len == 4)
2526                         devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2527                 else if (cmd->chanlist_len == 2)
2528                         devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2529                 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2530                 devpriv->adc_control1_bits |=
2531                         adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2532                 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2533                 devpriv->adc_control1_bits |=
2534                         adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2535                                                       [cmd->chanlist_len - 1]));
2536         }
2537         writew(devpriv->adc_control1_bits,
2538                devpriv->main_iobase + ADC_CONTROL1_REG);
2539         spin_unlock_irqrestore(&dev->spinlock, flags);
2540 
2541         /*  clear adc buffer */
2542         writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2543 
2544         if ((cmd->flags & TRIG_WAKE_EOS) == 0 ||
2545             thisboard->layout == LAYOUT_4020) {
2546                 devpriv->ai_dma_index = 0;
2547 
2548                 /*  set dma transfer size */
2549                 for (i = 0; i < ai_dma_ring_count(thisboard); i++)
2550                         devpriv->ai_dma_desc[i].transfer_size =
2551                                 cpu_to_le32(dma_transfer_size(dev) *
2552                                             sizeof(uint16_t));
2553 
2554                 /*  give location of first dma descriptor */
2555                 load_first_dma_descriptor(dev, 1,
2556                                           devpriv->ai_dma_desc_bus_addr |
2557                                           PLX_DESC_IN_PCI_BIT |
2558                                           PLX_INTR_TERM_COUNT |
2559                                           PLX_XFER_LOCAL_TO_PCI);
2560 
2561                 dma_start_sync(dev, 1);
2562         }
2563 
2564         if (thisboard->layout == LAYOUT_4020) {
2565                 /* set source for external triggers */
2566                 bits = 0;
2567                 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2568                         bits |= EXT_START_TRIG_BNC_BIT;
2569                 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2570                         bits |= EXT_STOP_TRIG_BNC_BIT;
2571                 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2572         }
2573 
2574         spin_lock_irqsave(&dev->spinlock, flags);
2575 
2576         /* enable pacing, triggering, etc */
2577         bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2578         if (cmd->flags & TRIG_WAKE_EOS)
2579                 bits |= ADC_DMA_DISABLE_BIT;
2580         /*  set start trigger */
2581         if (cmd->start_src == TRIG_EXT) {
2582                 bits |= ADC_START_TRIG_EXT_BITS;
2583                 if (cmd->start_arg & CR_INVERT)
2584                         bits |= ADC_START_TRIG_FALLING_BIT;
2585         } else if (cmd->start_src == TRIG_NOW)
2586                 bits |= ADC_START_TRIG_SOFT_BITS;
2587         if (use_hw_sample_counter(cmd))
2588                 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2589         writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2590 
2591         devpriv->ai_cmd_running = 1;
2592 
2593         spin_unlock_irqrestore(&dev->spinlock, flags);
2594 
2595         /*  start acquisition */
2596         if (cmd->start_src == TRIG_NOW)
2597                 writew(0, devpriv->main_iobase + ADC_START_REG);
2598 
2599         return 0;
2600 }
2601 
2602 /* read num_samples from 16 bit wide ai fifo */
2603 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2604 {
2605         struct pcidas64_private *devpriv = dev->private;
2606         struct comedi_subdevice *s = dev->read_subdev;
2607         struct comedi_async *async = s->async;
2608         struct comedi_cmd *cmd = &async->cmd;
2609         unsigned int i;
2610         uint16_t prepost_bits;
2611         int read_segment, read_index, write_segment, write_index;
2612         int num_samples;
2613 
2614         do {
2615                 /*  get least significant 15 bits */
2616                 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2617                              0x7fff;
2618                 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2619                               0x7fff;
2620                 /* Get most significant bits (grey code).
2621                  * Different boards use different code so use a scheme
2622                  * that doesn't depend on encoding.  This read must
2623                  * occur after reading least significant 15 bits to avoid race
2624                  * with fifo switching to next segment. */
2625                 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2626 
2627                 /* if read and write pointers are not on the same fifo segment,
2628                  * read to the end of the read segment */
2629                 read_segment = adc_upper_read_ptr_code(prepost_bits);
2630                 write_segment = adc_upper_write_ptr_code(prepost_bits);
2631 
2632                 if (read_segment != write_segment)
2633                         num_samples =
2634                                 devpriv->ai_fifo_segment_length - read_index;
2635                 else
2636                         num_samples = write_index - read_index;
2637 
2638                 if (cmd->stop_src == TRIG_COUNT) {
2639                         if (devpriv->ai_count == 0)
2640                                 break;
2641                         if (num_samples > devpriv->ai_count)
2642                                 num_samples = devpriv->ai_count;
2643 
2644                         devpriv->ai_count -= num_samples;
2645                 }
2646 
2647                 if (num_samples < 0) {
2648                         dev_err(dev->class_dev,
2649                                 "cb_pcidas64: bug! num_samples < 0\n");
2650                         break;
2651                 }
2652 
2653                 for (i = 0; i < num_samples; i++) {
2654                         cfc_write_to_buffer(s,
2655                                             readw(devpriv->main_iobase +
2656                                                   ADC_FIFO_REG));
2657                 }
2658 
2659         } while (read_segment != write_segment);
2660 }
2661 
2662 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2663  * pointers.  The pci-4020 hardware only supports dma transfers (it only
2664  * supports the use of pio for draining the last remaining points from the
2665  * fifo when a data acquisition operation has completed).
2666  */
2667 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2668 {
2669         struct pcidas64_private *devpriv = dev->private;
2670         struct comedi_subdevice *s = dev->read_subdev;
2671         struct comedi_async *async = s->async;
2672         struct comedi_cmd *cmd = &async->cmd;
2673         unsigned int i;
2674         unsigned int max_transfer = 100000;
2675         uint32_t fifo_data;
2676         int write_code =
2677                 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2678         int read_code =
2679                 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2680 
2681         if (cmd->stop_src == TRIG_COUNT) {
2682                 if (max_transfer > devpriv->ai_count)
2683                         max_transfer = devpriv->ai_count;
2684 
2685         }
2686         for (i = 0; read_code != write_code && i < max_transfer;) {
2687                 fifo_data = readl(dev->mmio + ADC_FIFO_REG);
2688                 cfc_write_to_buffer(s, fifo_data & 0xffff);
2689                 i++;
2690                 if (i < max_transfer) {
2691                         cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2692                         i++;
2693                 }
2694                 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2695                             0x7fff;
2696         }
2697         devpriv->ai_count -= i;
2698 }
2699 
2700 /* empty fifo */
2701 static void pio_drain_ai_fifo(struct comedi_device *dev)
2702 {
2703         const struct pcidas64_board *thisboard = comedi_board(dev);
2704 
2705         if (thisboard->layout == LAYOUT_4020)
2706                 pio_drain_ai_fifo_32(dev);
2707         else
2708                 pio_drain_ai_fifo_16(dev);
2709 }
2710 
2711 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2712 {
2713         const struct pcidas64_board *thisboard = comedi_board(dev);
2714         struct pcidas64_private *devpriv = dev->private;
2715         struct comedi_async *async = dev->read_subdev->async;
2716         struct comedi_cmd *cmd = &async->cmd;
2717         uint32_t next_transfer_addr;
2718         int j;
2719         int num_samples = 0;
2720         void __iomem *pci_addr_reg;
2721 
2722         if (channel)
2723                 pci_addr_reg =
2724                     devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2725         else
2726                 pci_addr_reg =
2727                     devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2728 
2729         /*  loop until we have read all the full buffers */
2730         for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2731              (next_transfer_addr <
2732               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2733               next_transfer_addr >=
2734               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2735               DMA_BUFFER_SIZE) && j < ai_dma_ring_count(thisboard); j++) {
2736                 /*  transfer data from dma buffer to comedi buffer */
2737                 num_samples = dma_transfer_size(dev);
2738                 if (cmd->stop_src == TRIG_COUNT) {
2739                         if (num_samples > devpriv->ai_count)
2740                                 num_samples = devpriv->ai_count;
2741                         devpriv->ai_count -= num_samples;
2742                 }
2743                 cfc_write_array_to_buffer(dev->read_subdev,
2744                                           devpriv->ai_buffer[devpriv->
2745                                                              ai_dma_index],
2746                                           num_samples * sizeof(uint16_t));
2747                 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2748                                         ai_dma_ring_count(thisboard);
2749         }
2750         /* XXX check for dma ring buffer overrun
2751          * (use end-of-chain bit to mark last unused buffer) */
2752 }
2753 
2754 static void handle_ai_interrupt(struct comedi_device *dev,
2755                                 unsigned short status,
2756                                 unsigned int plx_status)
2757 {
2758         const struct pcidas64_board *thisboard = comedi_board(dev);
2759         struct pcidas64_private *devpriv = dev->private;
2760         struct comedi_subdevice *s = dev->read_subdev;
2761         struct comedi_async *async = s->async;
2762         struct comedi_cmd *cmd = &async->cmd;
2763         uint8_t dma1_status;
2764         unsigned long flags;
2765 
2766         /*  check for fifo overrun */
2767         if (status & ADC_OVERRUN_BIT) {
2768                 dev_err(dev->class_dev, "fifo overrun\n");
2769                 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2770         }
2771         /*  spin lock makes sure no one else changes plx dma control reg */
2772         spin_lock_irqsave(&dev->spinlock, flags);
2773         dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2774         if (plx_status & ICS_DMA1_A) {  /*  dma chan 1 interrupt */
2775                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2776                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2777 
2778                 if (dma1_status & PLX_DMA_EN_BIT)
2779                         drain_dma_buffers(dev, 1);
2780         }
2781         spin_unlock_irqrestore(&dev->spinlock, flags);
2782 
2783         /*  drain fifo with pio */
2784         if ((status & ADC_DONE_BIT) ||
2785             ((cmd->flags & TRIG_WAKE_EOS) &&
2786              (status & ADC_INTR_PENDING_BIT) &&
2787              (thisboard->layout != LAYOUT_4020))) {
2788                 spin_lock_irqsave(&dev->spinlock, flags);
2789                 if (devpriv->ai_cmd_running) {
2790                         spin_unlock_irqrestore(&dev->spinlock, flags);
2791                         pio_drain_ai_fifo(dev);
2792                 } else
2793                         spin_unlock_irqrestore(&dev->spinlock, flags);
2794         }
2795         /*  if we are have all the data, then quit */
2796         if ((cmd->stop_src == TRIG_COUNT && (int)devpriv->ai_count <= 0) ||
2797             (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
2798                 async->events |= COMEDI_CB_EOA;
2799         }
2800 
2801         cfc_handle_events(dev, s);
2802 }
2803 
2804 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2805 {
2806         struct pcidas64_private *devpriv = dev->private;
2807         unsigned int buffer_index;
2808 
2809         if (devpriv->ao_dma_index == 0)
2810                 buffer_index = AO_DMA_RING_COUNT - 1;
2811         else
2812                 buffer_index = devpriv->ao_dma_index - 1;
2813         return buffer_index;
2814 }
2815 
2816 static int last_ao_dma_load_completed(struct comedi_device *dev)
2817 {
2818         struct pcidas64_private *devpriv = dev->private;
2819         unsigned int buffer_index;
2820         unsigned int transfer_address;
2821         unsigned short dma_status;
2822 
2823         buffer_index = prev_ao_dma_index(dev);
2824         dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2825         if ((dma_status & PLX_DMA_DONE_BIT) == 0)
2826                 return 0;
2827 
2828         transfer_address =
2829                 readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2830         if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2831                 return 0;
2832 
2833         return 1;
2834 }
2835 
2836 static int ao_stopped_by_error(struct comedi_device *dev,
2837                                const struct comedi_cmd *cmd)
2838 {
2839         struct pcidas64_private *devpriv = dev->private;
2840 
2841         if (cmd->stop_src == TRIG_NONE)
2842                 return 1;
2843         if (cmd->stop_src == TRIG_COUNT) {
2844                 if (devpriv->ao_count)
2845                         return 1;
2846                 if (last_ao_dma_load_completed(dev) == 0)
2847                         return 1;
2848         }
2849         return 0;
2850 }
2851 
2852 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2853                                        unsigned short dma_status)
2854 {
2855         if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
2856             (dma_status & PLX_DMA_EN_BIT) == 0)
2857                 return 0;
2858         if (last_ao_dma_load_completed(dev))
2859                 return 0;
2860 
2861         return 1;
2862 }
2863 
2864 static void restart_ao_dma(struct comedi_device *dev)
2865 {
2866         struct pcidas64_private *devpriv = dev->private;
2867         unsigned int dma_desc_bits;
2868 
2869         dma_desc_bits =
2870                 readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2871         dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
2872         load_first_dma_descriptor(dev, 0, dma_desc_bits);
2873 
2874         dma_start_sync(dev, 0);
2875 }
2876 
2877 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2878                                        const struct comedi_cmd *cmd)
2879 {
2880         struct pcidas64_private *devpriv = dev->private;
2881         unsigned int num_bytes, buffer_index, prev_buffer_index;
2882         unsigned int next_bits;
2883 
2884         buffer_index = devpriv->ao_dma_index;
2885         prev_buffer_index = prev_ao_dma_index(dev);
2886 
2887         num_bytes = comedi_buf_read_n_available(dev->write_subdev);
2888         if (num_bytes > DMA_BUFFER_SIZE)
2889                 num_bytes = DMA_BUFFER_SIZE;
2890         if (cmd->stop_src == TRIG_COUNT && num_bytes > devpriv->ao_count)
2891                 num_bytes = devpriv->ao_count;
2892         num_bytes -= num_bytes % bytes_in_sample;
2893 
2894         if (num_bytes == 0)
2895                 return 0;
2896 
2897         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
2898                                                devpriv->
2899                                                ao_buffer[buffer_index],
2900                                                num_bytes);
2901         devpriv->ao_dma_desc[buffer_index].transfer_size =
2902                 cpu_to_le32(num_bytes);
2903         /* set end of chain bit so we catch underruns */
2904         next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
2905         next_bits |= PLX_END_OF_CHAIN_BIT;
2906         devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
2907         /* clear end of chain bit on previous buffer now that we have set it
2908          * for the last buffer */
2909         next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
2910         next_bits &= ~PLX_END_OF_CHAIN_BIT;
2911         devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
2912 
2913         devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
2914         devpriv->ao_count -= num_bytes;
2915 
2916         return num_bytes;
2917 }
2918 
2919 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
2920 {
2921         struct pcidas64_private *devpriv = dev->private;
2922         unsigned int num_bytes;
2923         unsigned int next_transfer_addr;
2924         void __iomem *pci_addr_reg =
2925                 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2926         unsigned int buffer_index;
2927 
2928         do {
2929                 buffer_index = devpriv->ao_dma_index;
2930                 /* don't overwrite data that hasn't been transferred yet */
2931                 next_transfer_addr = readl(pci_addr_reg);
2932                 if (next_transfer_addr >=
2933                     devpriv->ao_buffer_bus_addr[buffer_index] &&
2934                     next_transfer_addr <
2935                     devpriv->ao_buffer_bus_addr[buffer_index] +
2936                     DMA_BUFFER_SIZE)
2937                         return;
2938                 num_bytes = load_ao_dma_buffer(dev, cmd);
2939         } while (num_bytes >= DMA_BUFFER_SIZE);
2940 }
2941 
2942 static void handle_ao_interrupt(struct comedi_device *dev,
2943                                 unsigned short status, unsigned int plx_status)
2944 {
2945         struct pcidas64_private *devpriv = dev->private;
2946         struct comedi_subdevice *s = dev->write_subdev;
2947         struct comedi_async *async;
2948         struct comedi_cmd *cmd;
2949         uint8_t dma0_status;
2950         unsigned long flags;
2951 
2952         /* board might not support ao, in which case write_subdev is NULL */
2953         if (s == NULL)
2954                 return;
2955         async = s->async;
2956         cmd = &async->cmd;
2957 
2958         /*  spin lock makes sure no one else changes plx dma control reg */
2959         spin_lock_irqsave(&dev->spinlock, flags);
2960         dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2961         if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
2962                 if ((dma0_status & PLX_DMA_EN_BIT) &&
2963                     !(dma0_status & PLX_DMA_DONE_BIT))
2964                         writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
2965                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2966                 else
2967                         writeb(PLX_CLEAR_DMA_INTR_BIT,
2968                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2969                 spin_unlock_irqrestore(&dev->spinlock, flags);
2970                 if (dma0_status & PLX_DMA_EN_BIT) {
2971                         load_ao_dma(dev, cmd);
2972                         /* try to recover from dma end-of-chain event */
2973                         if (ao_dma_needs_restart(dev, dma0_status))
2974                                 restart_ao_dma(dev);
2975                 }
2976         } else {
2977                 spin_unlock_irqrestore(&dev->spinlock, flags);
2978         }
2979 
2980         if ((status & DAC_DONE_BIT)) {
2981                 async->events |= COMEDI_CB_EOA;
2982                 if (ao_stopped_by_error(dev, cmd))
2983                         async->events |= COMEDI_CB_ERROR;
2984         }
2985         cfc_handle_events(dev, s);
2986 }
2987 
2988 static irqreturn_t handle_interrupt(int irq, void *d)
2989 {
2990         struct comedi_device *dev = d;
2991         struct pcidas64_private *devpriv = dev->private;
2992         unsigned short status;
2993         uint32_t plx_status;
2994         uint32_t plx_bits;
2995 
2996         plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
2997         status = readw(devpriv->main_iobase + HW_STATUS_REG);
2998 
2999         /* an interrupt before all the postconfig stuff gets done could
3000          * cause a NULL dereference if we continue through the
3001          * interrupt handler */
3002         if (!dev->attached)
3003                 return IRQ_HANDLED;
3004 
3005         handle_ai_interrupt(dev, status, plx_status);
3006         handle_ao_interrupt(dev, status, plx_status);
3007 
3008         /*  clear possible plx9080 interrupt sources */
3009         if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
3010                 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3011                 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3012         }
3013 
3014         return IRQ_HANDLED;
3015 }
3016 
3017 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3018 {
3019         struct pcidas64_private *devpriv = dev->private;
3020         unsigned long flags;
3021 
3022         spin_lock_irqsave(&dev->spinlock, flags);
3023         if (devpriv->ai_cmd_running == 0) {
3024                 spin_unlock_irqrestore(&dev->spinlock, flags);
3025                 return 0;
3026         }
3027         devpriv->ai_cmd_running = 0;
3028         spin_unlock_irqrestore(&dev->spinlock, flags);
3029 
3030         disable_ai_pacing(dev);
3031 
3032         abort_dma(dev, 1);
3033 
3034         return 0;
3035 }
3036 
3037 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3038                     struct comedi_insn *insn, unsigned int *data)
3039 {
3040         const struct pcidas64_board *thisboard = comedi_board(dev);
3041         struct pcidas64_private *devpriv = dev->private;
3042         int chan = CR_CHAN(insn->chanspec);
3043         int range = CR_RANGE(insn->chanspec);
3044 
3045         /*  do some initializing */
3046         writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3047 
3048         /*  set range */
3049         set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3050         writew(devpriv->dac_control1_bits,
3051                devpriv->main_iobase + DAC_CONTROL1_REG);
3052 
3053         /*  write to channel */
3054         if (thisboard->layout == LAYOUT_4020) {
3055                 writew(data[0] & 0xff,
3056                        devpriv->main_iobase + dac_lsb_4020_reg(chan));
3057                 writew((data[0] >> 8) & 0xf,
3058                        devpriv->main_iobase + dac_msb_4020_reg(chan));
3059         } else {
3060                 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3061         }
3062 
3063         /*  remember output value */
3064         devpriv->ao_value[chan] = data[0];
3065 
3066         return 1;
3067 }
3068 
3069 static int ao_readback_insn(struct comedi_device *dev,
3070                             struct comedi_subdevice *s,
3071                             struct comedi_insn *insn, unsigned int *data)
3072 {
3073         struct pcidas64_private *devpriv = dev->private;
3074 
3075         data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
3076 
3077         return 1;
3078 }
3079 
3080 static void set_dac_control0_reg(struct comedi_device *dev,
3081                                  const struct comedi_cmd *cmd)
3082 {
3083         struct pcidas64_private *devpriv = dev->private;
3084         unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3085                             WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3086 
3087         if (cmd->start_src == TRIG_EXT) {
3088                 bits |= WAVEFORM_TRIG_EXT_BITS;
3089                 if (cmd->start_arg & CR_INVERT)
3090                         bits |= WAVEFORM_TRIG_FALLING_BIT;
3091         } else {
3092                 bits |= WAVEFORM_TRIG_SOFT_BITS;
3093         }
3094         if (cmd->scan_begin_src == TRIG_EXT) {
3095                 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3096                 if (cmd->scan_begin_arg & CR_INVERT)
3097                         bits |= DAC_EXT_UPDATE_FALLING_BIT;
3098         }
3099         writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3100 }
3101 
3102 static void set_dac_control1_reg(struct comedi_device *dev,
3103                                  const struct comedi_cmd *cmd)
3104 {
3105         struct pcidas64_private *devpriv = dev->private;
3106         int i;
3107 
3108         for (i = 0; i < cmd->chanlist_len; i++) {
3109                 int channel, range;
3110 
3111                 channel = CR_CHAN(cmd->chanlist[i]);
3112                 range = CR_RANGE(cmd->chanlist[i]);
3113                 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3114                                    range);
3115         }
3116         devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3117         writew(devpriv->dac_control1_bits,
3118                devpriv->main_iobase + DAC_CONTROL1_REG);
3119 }
3120 
3121 static void set_dac_select_reg(struct comedi_device *dev,
3122                                const struct comedi_cmd *cmd)
3123 {
3124         struct pcidas64_private *devpriv = dev->private;
3125         uint16_t bits;
3126         unsigned int first_channel, last_channel;
3127 
3128         first_channel = CR_CHAN(cmd->chanlist[0]);
3129         last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3130         if (last_channel < first_channel)
3131                 dev_err(dev->class_dev,
3132                         "bug! last ao channel < first ao channel\n");
3133 
3134         bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3135 
3136         writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3137 }
3138 
3139 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3140 {
3141         return get_divisor(ns, flags) - 2;
3142 }
3143 
3144 static void set_dac_interval_regs(struct comedi_device *dev,
3145                                   const struct comedi_cmd *cmd)
3146 {
3147         struct pcidas64_private *devpriv = dev->private;
3148         unsigned int divisor;
3149 
3150         if (cmd->scan_begin_src != TRIG_TIMER)
3151                 return;
3152 
3153         divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3154         if (divisor > max_counter_value) {
3155                 dev_err(dev->class_dev, "bug! ao divisor too big\n");
3156                 divisor = max_counter_value;
3157         }
3158         writew(divisor & 0xffff,
3159                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3160         writew((divisor >> 16) & 0xff,
3161                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3162 }
3163 
3164 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3165 {
3166         struct pcidas64_private *devpriv = dev->private;
3167         unsigned int num_bytes;
3168         int i;
3169 
3170         /* clear queue pointer too, since external queue has
3171          * weird interactions with ao fifo */
3172         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3173         writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3174 
3175         num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample;
3176         if (cmd->stop_src == TRIG_COUNT &&
3177             num_bytes / bytes_in_sample > devpriv->ao_count)
3178                 num_bytes = devpriv->ao_count * bytes_in_sample;
3179         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3180                                                devpriv->ao_bounce_buffer,
3181                                                num_bytes);
3182         for (i = 0; i < num_bytes / bytes_in_sample; i++) {
3183                 writew(devpriv->ao_bounce_buffer[i],
3184                        devpriv->main_iobase + DAC_FIFO_REG);
3185         }
3186         devpriv->ao_count -= num_bytes / bytes_in_sample;
3187         if (cmd->stop_src == TRIG_COUNT && devpriv->ao_count == 0)
3188                 return 0;
3189         num_bytes = load_ao_dma_buffer(dev, cmd);
3190         if (num_bytes == 0)
3191                 return -1;
3192         load_ao_dma(dev, cmd);
3193 
3194         dma_start_sync(dev, 0);
3195 
3196         return 0;
3197 }
3198 
3199 static inline int external_ai_queue_in_use(struct comedi_device *dev,
3200                                            struct comedi_subdevice *s,
3201                                            struct comedi_cmd *cmd)
3202 {
3203         const struct pcidas64_board *thisboard = comedi_board(dev);
3204 
3205         if (s->busy)
3206                 return 0;
3207         if (thisboard->layout == LAYOUT_4020)
3208                 return 0;
3209         else if (use_internal_queue_6xxx(cmd))
3210                 return 0;
3211         return 1;
3212 }
3213 
3214 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3215                       unsigned int trig_num)
3216 {
3217         struct pcidas64_private *devpriv = dev->private;
3218         struct comedi_cmd *cmd = &s->async->cmd;
3219         int retval;
3220 
3221         if (trig_num != cmd->start_arg)
3222                 return -EINVAL;
3223 
3224         retval = prep_ao_dma(dev, cmd);
3225         if (retval < 0)
3226                 return -EPIPE;
3227 
3228         set_dac_control0_reg(dev, cmd);
3229 
3230         if (cmd->start_src == TRIG_INT)
3231                 writew(0, devpriv->main_iobase + DAC_START_REG);
3232 
3233         s->async->inttrig = NULL;
3234 
3235         return 0;
3236 }
3237 
3238 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3239 {
3240         struct pcidas64_private *devpriv = dev->private;
3241         struct comedi_cmd *cmd = &s->async->cmd;
3242 
3243         if (external_ai_queue_in_use(dev, s, cmd)) {
3244                 warn_external_queue(dev);
3245                 return -EBUSY;
3246         }
3247         /* disable analog output system during setup */
3248         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3249 
3250         devpriv->ao_dma_index = 0;
3251         devpriv->ao_count = cmd->stop_arg * cmd->chanlist_len;
3252 
3253         set_dac_select_reg(dev, cmd);
3254         set_dac_interval_regs(dev, cmd);
3255         load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3256                                   PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3257 
3258         set_dac_control1_reg(dev, cmd);
3259         s->async->inttrig = ao_inttrig;
3260 
3261         return 0;
3262 }
3263 
3264 static int cb_pcidas64_ao_check_chanlist(struct comedi_device *dev,
3265                                          struct comedi_subdevice *s,
3266                                          struct comedi_cmd *cmd)
3267 {
3268         unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
3269         int i;
3270 
3271         for (i = 1; i < cmd->chanlist_len; i++) {
3272                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3273 
3274                 if (chan != (chan0 + i)) {
3275                         dev_dbg(dev->class_dev,
3276                                 "chanlist must use consecutive channels\n");
3277                         return -EINVAL;
3278                 }
3279         }
3280 
3281         return 0;
3282 }
3283 
3284 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3285                       struct comedi_cmd *cmd)
3286 {
3287         const struct pcidas64_board *thisboard = comedi_board(dev);
3288         int err = 0;
3289         unsigned int tmp_arg;
3290 
3291         /* Step 1 : check if triggers are trivially valid */
3292 
3293         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3294         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3295                                      TRIG_TIMER | TRIG_EXT);
3296         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3297         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3298         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3299 
3300         if (err)
3301                 return 1;
3302 
3303         /* Step 2a : make sure trigger sources are unique */
3304 
3305         err |= cfc_check_trigger_is_unique(cmd->start_src);
3306         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3307 
3308         /* Step 2b : and mutually compatible */
3309 
3310         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3311                 err |= -EINVAL;
3312         if (cmd->stop_src != TRIG_COUNT &&
3313             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3314                 err |= -EINVAL;
3315 
3316         if (err)
3317                 return 2;
3318 
3319         /* Step 3: check if arguments are trivially valid */
3320 
3321         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3322 
3323         if (cmd->scan_begin_src == TRIG_TIMER) {
3324                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3325                                                  thisboard->ao_scan_speed);
3326                 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3327                     max_counter_value) {
3328                         cmd->scan_begin_arg = (max_counter_value + 2) *
3329                                               TIMER_BASE;
3330                         err |= -EINVAL;
3331                 }
3332         }
3333 
3334         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
3335         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3336 
3337         if (err)
3338                 return 3;
3339 
3340         /* step 4: fix up any arguments */
3341 
3342         if (cmd->scan_begin_src == TRIG_TIMER) {
3343                 tmp_arg = cmd->scan_begin_arg;
3344                 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3345                                                   cmd->flags) * TIMER_BASE;
3346                 if (tmp_arg != cmd->scan_begin_arg)
3347                         err++;
3348         }
3349 
3350         if (err)
3351                 return 4;
3352 
3353         /* Step 5: check channel list if it exists */
3354         if (cmd->chanlist && cmd->chanlist_len > 0)
3355                 err |= cb_pcidas64_ao_check_chanlist(dev, s, cmd);
3356 
3357         if (err)
3358                 return 5;
3359 
3360         return 0;
3361 }
3362 
3363 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3364 {
3365         struct pcidas64_private *devpriv = dev->private;
3366 
3367         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3368         abort_dma(dev, 0);
3369         return 0;
3370 }
3371 
3372 static int dio_callback(int dir, int port, int data, unsigned long arg)
3373 {
3374         void __iomem *iobase = (void __iomem *)arg;
3375 
3376         if (dir) {
3377                 writeb(data, iobase + port);
3378                 return 0;
3379         }
3380         return readb(iobase + port);
3381 }
3382 
3383 static int dio_callback_4020(int dir, int port, int data, unsigned long arg)
3384 {
3385         void __iomem *iobase = (void __iomem *)arg;
3386 
3387         if (dir) {
3388                 writew(data, iobase + 2 * port);
3389                 return 0;
3390         }
3391         return readw(iobase + 2 * port);
3392 }
3393 
3394 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3395                     struct comedi_insn *insn, unsigned int *data)
3396 {
3397         unsigned int bits;
3398 
3399         bits = readb(dev->mmio + DI_REG);
3400         bits &= 0xf;
3401         data[1] = bits;
3402         data[0] = 0;
3403 
3404         return insn->n;
3405 }
3406 
3407 static int do_wbits(struct comedi_device *dev,
3408                     struct comedi_subdevice *s,
3409                     struct comedi_insn *insn,
3410                     unsigned int *data)
3411 {
3412         if (comedi_dio_update_state(s, data))
3413                 writeb(s->state, dev->mmio + DO_REG);
3414 
3415         data[1] = s->state;
3416 
3417         return insn->n;
3418 }
3419 
3420 static int dio_60xx_config_insn(struct comedi_device *dev,
3421                                 struct comedi_subdevice *s,
3422                                 struct comedi_insn *insn,
3423                                 unsigned int *data)
3424 {
3425         int ret;
3426 
3427         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3428         if (ret)
3429                 return ret;
3430 
3431         writeb(s->io_bits, dev->mmio + DIO_DIRECTION_60XX_REG);
3432 
3433         return insn->n;
3434 }
3435 
3436 static int dio_60xx_wbits(struct comedi_device *dev,
3437                           struct comedi_subdevice *s,
3438                           struct comedi_insn *insn,
3439                           unsigned int *data)
3440 {
3441         if (comedi_dio_update_state(s, data))
3442                 writeb(s->state, dev->mmio + DIO_DATA_60XX_REG);
3443 
3444         data[1] = readb(dev->mmio + DIO_DATA_60XX_REG);
3445 
3446         return insn->n;
3447 }
3448 
3449 /* pci-6025 8800 caldac:
3450  * address 0 == dac channel 0 offset
3451  * address 1 == dac channel 0 gain
3452  * address 2 == dac channel 1 offset
3453  * address 3 == dac channel 1 gain
3454  * address 4 == fine adc offset
3455  * address 5 == coarse adc offset
3456  * address 6 == coarse adc gain
3457  * address 7 == fine adc gain
3458  */
3459 /* pci-6402/16 uses all 8 channels for dac:
3460  * address 0 == dac channel 0 fine gain
3461  * address 1 == dac channel 0 coarse gain
3462  * address 2 == dac channel 0 coarse offset
3463  * address 3 == dac channel 1 coarse offset
3464  * address 4 == dac channel 1 fine gain
3465  * address 5 == dac channel 1 coarse gain
3466  * address 6 == dac channel 0 fine offset
3467  * address 7 == dac channel 1 fine offset
3468 */
3469 
3470 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3471                              uint8_t value)
3472 {
3473         struct pcidas64_private *devpriv = dev->private;
3474         static const int num_caldac_channels = 8;
3475         static const int bitstream_length = 11;
3476         unsigned int bitstream = ((address & 0x7) << 8) | value;
3477         unsigned int bit, register_bits;
3478         static const int caldac_8800_udelay = 1;
3479 
3480         if (address >= num_caldac_channels) {
3481                 dev_err(dev->class_dev, "illegal caldac channel\n");
3482                 return -1;
3483         }
3484         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3485                 register_bits = 0;
3486                 if (bitstream & bit)
3487                         register_bits |= SERIAL_DATA_IN_BIT;
3488                 udelay(caldac_8800_udelay);
3489                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3490                 register_bits |= SERIAL_CLOCK_BIT;
3491                 udelay(caldac_8800_udelay);
3492                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3493         }
3494         udelay(caldac_8800_udelay);
3495         writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3496         udelay(caldac_8800_udelay);
3497         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3498         udelay(caldac_8800_udelay);
3499         return 0;
3500 }
3501 
3502 /* 4020 caldacs */
3503 static int caldac_i2c_write(struct comedi_device *dev,
3504                             unsigned int caldac_channel, unsigned int value)
3505 {
3506         uint8_t serial_bytes[3];
3507         uint8_t i2c_addr;
3508         enum pointer_bits {
3509                 /*  manual has gain and offset bits switched */
3510                 OFFSET_0_2 = 0x1,
3511                 GAIN_0_2 = 0x2,
3512                 OFFSET_1_3 = 0x4,
3513                 GAIN_1_3 = 0x8,
3514         };
3515         enum data_bits {
3516                 NOT_CLEAR_REGISTERS = 0x20,
3517         };
3518 
3519         switch (caldac_channel) {
3520         case 0:         /*  chan 0 offset */
3521                 i2c_addr = CALDAC0_I2C_ADDR;
3522                 serial_bytes[0] = OFFSET_0_2;
3523                 break;
3524         case 1:         /*  chan 1 offset */
3525                 i2c_addr = CALDAC0_I2C_ADDR;
3526                 serial_bytes[0] = OFFSET_1_3;
3527                 break;
3528         case 2:         /*  chan 2 offset */
3529                 i2c_addr = CALDAC1_I2C_ADDR;
3530                 serial_bytes[0] = OFFSET_0_2;
3531                 break;
3532         case 3:         /*  chan 3 offset */
3533                 i2c_addr = CALDAC1_I2C_ADDR;
3534                 serial_bytes[0] = OFFSET_1_3;
3535                 break;
3536         case 4:         /*  chan 0 gain */
3537                 i2c_addr = CALDAC0_I2C_ADDR;
3538                 serial_bytes[0] = GAIN_0_2;
3539                 break;
3540         case 5:         /*  chan 1 gain */
3541                 i2c_addr = CALDAC0_I2C_ADDR;
3542                 serial_bytes[0] = GAIN_1_3;
3543                 break;
3544         case 6:         /*  chan 2 gain */
3545                 i2c_addr = CALDAC1_I2C_ADDR;
3546                 serial_bytes[0] = GAIN_0_2;
3547                 break;
3548         case 7:         /*  chan 3 gain */
3549                 i2c_addr = CALDAC1_I2C_ADDR;
3550                 serial_bytes[0] = GAIN_1_3;
3551                 break;
3552         default:
3553                 dev_err(dev->class_dev, "invalid caldac channel\n");
3554                 return -1;
3555         }
3556         serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3557         serial_bytes[2] = value & 0xff;
3558         i2c_write(dev, i2c_addr, serial_bytes, 3);
3559         return 0;
3560 }
3561 
3562 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3563                          unsigned int value)
3564 {
3565         const struct pcidas64_board *thisboard = comedi_board(dev);
3566         struct pcidas64_private *devpriv = dev->private;
3567 
3568         devpriv->caldac_state[channel] = value;
3569 
3570         switch (thisboard->layout) {
3571         case LAYOUT_60XX:
3572         case LAYOUT_64XX:
3573                 caldac_8800_write(dev, channel, value);
3574                 break;
3575         case LAYOUT_4020:
3576                 caldac_i2c_write(dev, channel, value);
3577                 break;
3578         default:
3579                 break;
3580         }
3581 }
3582 
3583 static int calib_write_insn(struct comedi_device *dev,
3584                             struct comedi_subdevice *s,
3585                             struct comedi_insn *insn, unsigned int *data)
3586 {
3587         struct pcidas64_private *devpriv = dev->private;
3588         int channel = CR_CHAN(insn->chanspec);
3589 
3590         /* return immediately if setting hasn't changed, since
3591          * programming these things is slow */
3592         if (devpriv->caldac_state[channel] == data[0])
3593                 return 1;
3594 
3595         caldac_write(dev, channel, data[0]);
3596 
3597         return 1;
3598 }
3599 
3600 static int calib_read_insn(struct comedi_device *dev,
3601                            struct comedi_subdevice *s, struct comedi_insn *insn,
3602                            unsigned int *data)
3603 {
3604         struct pcidas64_private *devpriv = dev->private;
3605         unsigned int channel = CR_CHAN(insn->chanspec);
3606 
3607         data[0] = devpriv->caldac_state[channel];
3608 
3609         return 1;
3610 }
3611 
3612 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3613                          unsigned int value)
3614 {
3615         struct pcidas64_private *devpriv = dev->private;
3616         static const int bitstream_length = 10;
3617         unsigned int bit, register_bits;
3618         unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3619         static const int ad8402_udelay = 1;
3620 
3621         devpriv->ad8402_state[channel] = value;
3622 
3623         register_bits = SELECT_8402_64XX_BIT;
3624         udelay(ad8402_udelay);
3625         writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3626 
3627         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3628                 if (bitstream & bit)
3629                         register_bits |= SERIAL_DATA_IN_BIT;
3630                 else
3631                         register_bits &= ~SERIAL_DATA_IN_BIT;
3632                 udelay(ad8402_udelay);
3633                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3634                 udelay(ad8402_udelay);
3635                 writew(register_bits | SERIAL_CLOCK_BIT,
3636                        devpriv->main_iobase + CALIBRATION_REG);
3637         }
3638 
3639         udelay(ad8402_udelay);
3640         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3641 }
3642 
3643 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3644 static int ad8402_write_insn(struct comedi_device *dev,
3645                              struct comedi_subdevice *s,
3646                              struct comedi_insn *insn, unsigned int *data)
3647 {
3648         struct pcidas64_private *devpriv = dev->private;
3649         int channel = CR_CHAN(insn->chanspec);
3650 
3651         /* return immediately if setting hasn't changed, since
3652          * programming these things is slow */
3653         if (devpriv->ad8402_state[channel] == data[0])
3654                 return 1;
3655 
3656         devpriv->ad8402_state[channel] = data[0];
3657 
3658         ad8402_write(dev, channel, data[0]);
3659 
3660         return 1;
3661 }
3662 
3663 static int ad8402_read_insn(struct comedi_device *dev,
3664                             struct comedi_subdevice *s,
3665                             struct comedi_insn *insn, unsigned int *data)
3666 {
3667         struct pcidas64_private *devpriv = dev->private;
3668         unsigned int channel = CR_CHAN(insn->chanspec);
3669 
3670         data[0] = devpriv->ad8402_state[channel];
3671 
3672         return 1;
3673 }
3674 
3675 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3676 {
3677         struct pcidas64_private *devpriv = dev->private;
3678         static const int bitstream_length = 11;
3679         static const int read_command = 0x6;
3680         unsigned int bitstream = (read_command << 8) | address;
3681         unsigned int bit;
3682         void __iomem * const plx_control_addr =
3683                 devpriv->plx9080_iobase + PLX_CONTROL_REG;
3684         uint16_t value;
3685         static const int value_length = 16;
3686         static const int eeprom_udelay = 1;
3687 
3688         udelay(eeprom_udelay);
3689         devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3690         /*  make sure we don't send anything to the i2c bus on 4020 */
3691         devpriv->plx_control_bits |= CTL_USERO;
3692         writel(devpriv->plx_control_bits, plx_control_addr);
3693         /*  activate serial eeprom */
3694         udelay(eeprom_udelay);
3695         devpriv->plx_control_bits |= CTL_EE_CS;
3696         writel(devpriv->plx_control_bits, plx_control_addr);
3697 
3698         /*  write read command and desired memory address */
3699         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3700                 /*  set bit to be written */
3701                 udelay(eeprom_udelay);
3702                 if (bitstream & bit)
3703                         devpriv->plx_control_bits |= CTL_EE_W;
3704                 else
3705                         devpriv->plx_control_bits &= ~CTL_EE_W;
3706                 writel(devpriv->plx_control_bits, plx_control_addr);
3707                 /*  clock in bit */
3708                 udelay(eeprom_udelay);
3709                 devpriv->plx_control_bits |= CTL_EE_CLK;
3710                 writel(devpriv->plx_control_bits, plx_control_addr);
3711                 udelay(eeprom_udelay);
3712                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3713                 writel(devpriv->plx_control_bits, plx_control_addr);
3714         }
3715         /*  read back value from eeprom memory location */
3716         value = 0;
3717         for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3718                 /*  clock out bit */
3719                 udelay(eeprom_udelay);
3720                 devpriv->plx_control_bits |= CTL_EE_CLK;
3721                 writel(devpriv->plx_control_bits, plx_control_addr);
3722                 udelay(eeprom_udelay);
3723                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3724                 writel(devpriv->plx_control_bits, plx_control_addr);
3725                 udelay(eeprom_udelay);
3726                 if (readl(plx_control_addr) & CTL_EE_R)
3727                         value |= bit;
3728         }
3729 
3730         /*  deactivate eeprom serial input */
3731         udelay(eeprom_udelay);
3732         devpriv->plx_control_bits &= ~CTL_EE_CS;
3733         writel(devpriv->plx_control_bits, plx_control_addr);
3734 
3735         return value;
3736 }
3737 
3738 static int eeprom_read_insn(struct comedi_device *dev,
3739                             struct comedi_subdevice *s,
3740                             struct comedi_insn *insn, unsigned int *data)
3741 {
3742         data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3743 
3744         return 1;
3745 }
3746 
3747 /* Allocate and initialize the subdevice structures.
3748  */
3749 static int setup_subdevices(struct comedi_device *dev)
3750 {
3751         const struct pcidas64_board *thisboard = comedi_board(dev);
3752         struct pcidas64_private *devpriv = dev->private;
3753         struct comedi_subdevice *s;
3754         void __iomem *dio_8255_iobase;
3755         int i;
3756         int ret;
3757 
3758         ret = comedi_alloc_subdevices(dev, 10);
3759         if (ret)
3760                 return ret;
3761 
3762         s = &dev->subdevices[0];
3763         /* analog input subdevice */
3764         dev->read_subdev = s;
3765         s->type = COMEDI_SUBD_AI;
3766         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3767         if (thisboard->layout == LAYOUT_60XX)
3768                 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3769         else if (thisboard->layout == LAYOUT_64XX)
3770                 s->subdev_flags |= SDF_DIFF;
3771         /* XXX Number of inputs in differential mode is ignored */
3772         s->n_chan = thisboard->ai_se_chans;
3773         s->len_chanlist = 0x2000;
3774         s->maxdata = (1 << thisboard->ai_bits) - 1;
3775         s->range_table = thisboard->ai_range_table;
3776         s->insn_read = ai_rinsn;
3777         s->insn_config = ai_config_insn;
3778         s->do_cmd = ai_cmd;
3779         s->do_cmdtest = ai_cmdtest;
3780         s->cancel = ai_cancel;
3781         if (thisboard->layout == LAYOUT_4020) {
3782                 uint8_t data;
3783                 /*  set adc to read from inputs
3784                  *  (not internal calibration sources) */
3785                 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3786                 /*  set channels to +-5 volt input ranges */
3787                 for (i = 0; i < s->n_chan; i++)
3788                         devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3789                 data = devpriv->i2c_cal_range_bits;
3790                 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3791         }
3792 
3793         /* analog output subdevice */
3794         s = &dev->subdevices[1];
3795         if (thisboard->ao_nchan) {
3796                 s->type = COMEDI_SUBD_AO;
3797                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3798                                   SDF_GROUND | SDF_CMD_WRITE;
3799                 s->n_chan = thisboard->ao_nchan;
3800                 s->maxdata = (1 << thisboard->ao_bits) - 1;
3801                 s->range_table = thisboard->ao_range_table;
3802                 s->insn_read = ao_readback_insn;
3803                 s->insn_write = ao_winsn;
3804                 if (ao_cmd_is_supported(thisboard)) {
3805                         dev->write_subdev = s;
3806                         s->do_cmdtest = ao_cmdtest;
3807                         s->do_cmd = ao_cmd;
3808                         s->len_chanlist = thisboard->ao_nchan;
3809                         s->cancel = ao_cancel;
3810                 }
3811         } else {
3812                 s->type = COMEDI_SUBD_UNUSED;
3813         }
3814 
3815         /*  digital input */
3816         s = &dev->subdevices[2];
3817         if (thisboard->layout == LAYOUT_64XX) {
3818                 s->type = COMEDI_SUBD_DI;
3819                 s->subdev_flags = SDF_READABLE;
3820                 s->n_chan = 4;
3821                 s->maxdata = 1;
3822                 s->range_table = &range_digital;
3823                 s->insn_bits = di_rbits;
3824         } else
3825                 s->type = COMEDI_SUBD_UNUSED;
3826 
3827         /*  digital output */
3828         if (thisboard->layout == LAYOUT_64XX) {
3829                 s = &dev->subdevices[3];
3830                 s->type = COMEDI_SUBD_DO;
3831                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3832                 s->n_chan = 4;
3833                 s->maxdata = 1;
3834                 s->range_table = &range_digital;
3835                 s->insn_bits = do_wbits;
3836         } else
3837                 s->type = COMEDI_SUBD_UNUSED;
3838 
3839         /* 8255 */
3840         s = &dev->subdevices[4];
3841         if (thisboard->has_8255) {
3842                 if (thisboard->layout == LAYOUT_4020) {
3843                         dio_8255_iobase = devpriv->main_iobase + I8255_4020_REG;
3844                         ret = subdev_8255_init(dev, s, dio_callback_4020,
3845                                                (unsigned long)dio_8255_iobase);
3846                 } else {
3847                         dio_8255_iobase = dev->mmio + DIO_8255_OFFSET;
3848                         ret = subdev_8255_init(dev, s, dio_callback,
3849                                                (unsigned long)dio_8255_iobase);
3850                 }
3851                 if (ret)
3852                         return ret;
3853         } else {
3854                 s->type = COMEDI_SUBD_UNUSED;
3855         }
3856 
3857         /*  8 channel dio for 60xx */
3858         s = &dev->subdevices[5];
3859         if (thisboard->layout == LAYOUT_60XX) {
3860                 s->type = COMEDI_SUBD_DIO;
3861                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3862                 s->n_chan = 8;
3863                 s->maxdata = 1;
3864                 s->range_table = &range_digital;
3865                 s->insn_config = dio_60xx_config_insn;
3866                 s->insn_bits = dio_60xx_wbits;
3867         } else
3868                 s->type = COMEDI_SUBD_UNUSED;
3869 
3870         /*  caldac */
3871         s = &dev->subdevices[6];
3872         s->type = COMEDI_SUBD_CALIB;
3873         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3874         s->n_chan = 8;
3875         if (thisboard->layout == LAYOUT_4020)
3876                 s->maxdata = 0xfff;
3877         else
3878                 s->maxdata = 0xff;
3879         s->insn_read = calib_read_insn;
3880         s->insn_write = calib_write_insn;
3881         for (i = 0; i < s->n_chan; i++)
3882                 caldac_write(dev, i, s->maxdata / 2);
3883 
3884         /*  2 channel ad8402 potentiometer */
3885         s = &dev->subdevices[7];
3886         if (thisboard->layout == LAYOUT_64XX) {
3887                 s->type = COMEDI_SUBD_CALIB;
3888                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3889                 s->n_chan = 2;
3890                 s->insn_read = ad8402_read_insn;
3891                 s->insn_write = ad8402_write_insn;
3892                 s->maxdata = 0xff;
3893                 for (i = 0; i < s->n_chan; i++)
3894                         ad8402_write(dev, i, s->maxdata / 2);
3895         } else
3896                 s->type = COMEDI_SUBD_UNUSED;
3897 
3898         /* serial EEPROM, if present */
3899         s = &dev->subdevices[8];
3900         if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
3901                 s->type = COMEDI_SUBD_MEMORY;
3902                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
3903                 s->n_chan = 128;
3904                 s->maxdata = 0xffff;
3905                 s->insn_read = eeprom_read_insn;
3906         } else
3907                 s->type = COMEDI_SUBD_UNUSED;
3908 
3909         /*  user counter subd XXX */
3910         s = &dev->subdevices[9];
3911         s->type = COMEDI_SUBD_UNUSED;
3912 
3913         return 0;
3914 }
3915 
3916 static int auto_attach(struct comedi_device *dev,
3917                        unsigned long context)
3918 {
3919         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
3920         const struct pcidas64_board *thisboard = NULL;
3921         struct pcidas64_private *devpriv;
3922         uint32_t local_range, local_decode;
3923         int retval;
3924 
3925         if (context < ARRAY_SIZE(pcidas64_boards))
3926                 thisboard = &pcidas64_boards[context];
3927         if (!thisboard)
3928                 return -ENODEV;
3929         dev->board_ptr = thisboard;
3930 
3931         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
3932         if (!devpriv)
3933                 return -ENOMEM;
3934 
3935         retval = comedi_pci_enable(dev);
3936         if (retval)
3937                 return retval;
3938         pci_set_master(pcidev);
3939 
3940         /* Initialize dev->board_name */
3941         dev->board_name = thisboard->name;
3942 
3943         devpriv->main_phys_iobase = pci_resource_start(pcidev, 2);
3944         devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3);
3945 
3946         devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
3947         devpriv->main_iobase = pci_ioremap_bar(pcidev, 2);
3948         dev->mmio = pci_ioremap_bar(pcidev, 3);
3949 
3950         if (!devpriv->plx9080_iobase || !devpriv->main_iobase || !dev->mmio) {
3951                 dev_warn(dev->class_dev, "failed to remap io memory\n");
3952                 return -ENOMEM;
3953         }
3954 
3955         /*  figure out what local addresses are */
3956         local_range = readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) &
3957                       LRNG_MEM_MASK;
3958         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS0MAP_REG) &
3959                        local_range & LMAP_MEM_MASK;
3960         devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
3961                                   ~local_range) | local_decode;
3962         local_range = readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) &
3963                       LRNG_MEM_MASK;
3964         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS1MAP_REG) &
3965                        local_range & LMAP_MEM_MASK;
3966         devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
3967                                   ~local_range) | local_decode;
3968 
3969         retval = alloc_and_init_dma_members(dev);
3970         if (retval < 0)
3971                 return retval;
3972 
3973         devpriv->hw_revision =
3974                 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
3975         dev_dbg(dev->class_dev, "stc hardware revision %i\n",
3976                 devpriv->hw_revision);
3977         init_plx9080(dev);
3978         init_stc_registers(dev);
3979 
3980         retval = request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
3981                              dev->board_name, dev);
3982         if (retval) {
3983                 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
3984                         pcidev->irq);
3985                 return retval;
3986         }
3987         dev->irq = pcidev->irq;
3988         dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
3989 
3990         retval = setup_subdevices(dev);
3991         if (retval < 0)
3992                 return retval;
3993 
3994         return 0;
3995 }
3996 
3997 static void detach(struct comedi_device *dev)
3998 {
3999         const struct pcidas64_board *thisboard = comedi_board(dev);
4000         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4001         struct pcidas64_private *devpriv = dev->private;
4002         unsigned int i;
4003 
4004         if (dev->irq)
4005                 free_irq(dev->irq, dev);
4006         if (devpriv) {
4007                 if (pcidev) {
4008                         if (devpriv->plx9080_iobase) {
4009                                 disable_plx_interrupts(dev);
4010                                 iounmap(devpriv->plx9080_iobase);
4011                         }
4012                         if (devpriv->main_iobase)
4013                                 iounmap(devpriv->main_iobase);
4014                         if (dev->mmio)
4015                                 iounmap(dev->mmio);
4016                         /*  free pci dma buffers */
4017                         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
4018                                 if (devpriv->ai_buffer[i])
4019                                         pci_free_consistent(pcidev,
4020                                                 DMA_BUFFER_SIZE,
4021                                                 devpriv->ai_buffer[i],
4022                                                 devpriv->ai_buffer_bus_addr[i]);
4023                         }
4024                         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
4025                                 if (devpriv->ao_buffer[i])
4026                                         pci_free_consistent(pcidev,
4027                                                 DMA_BUFFER_SIZE,
4028                                                 devpriv->ao_buffer[i],
4029                                                 devpriv->ao_buffer_bus_addr[i]);
4030                         }
4031                         /*  free dma descriptors */
4032                         if (devpriv->ai_dma_desc)
4033                                 pci_free_consistent(pcidev,
4034                                         sizeof(struct plx_dma_desc) *
4035                                         ai_dma_ring_count(thisboard),
4036                                         devpriv->ai_dma_desc,
4037                                         devpriv->ai_dma_desc_bus_addr);
4038                         if (devpriv->ao_dma_desc)
4039                                 pci_free_consistent(pcidev,
4040                                         sizeof(struct plx_dma_desc) *
4041                                         AO_DMA_RING_COUNT,
4042                                         devpriv->ao_dma_desc,
4043                                         devpriv->ao_dma_desc_bus_addr);
4044                 }
4045         }
4046         comedi_pci_disable(dev);
4047 }
4048 
4049 static struct comedi_driver cb_pcidas64_driver = {
4050         .driver_name    = "cb_pcidas64",
4051         .module         = THIS_MODULE,
4052         .auto_attach    = auto_attach,
4053         .detach         = detach,
4054 };
4055 
4056 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4057                                  const struct pci_device_id *id)
4058 {
4059         return comedi_pci_auto_config(dev, &cb_pcidas64_driver,
4060                                       id->driver_data);
4061 }
4062 
4063 static const struct pci_device_id cb_pcidas64_pci_table[] = {
4064         { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 },
4065         { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 },
4066         { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 },
4067         { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 },
4068         { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 },
4069         { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 },
4070         { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 },
4071         { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 },
4072         { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 },
4073         { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 },
4074         { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 },
4075         { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 },
4076         { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 },
4077         { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 },
4078         { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 },
4079         { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 },
4080         { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 },
4081         { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 },
4082         { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 },
4083         { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 },
4084         { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 },
4085         { 0 }
4086 };
4087 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4088 
4089 static struct pci_driver cb_pcidas64_pci_driver = {
4090         .name           = "cb_pcidas64",
4091         .id_table       = cb_pcidas64_pci_table,
4092         .probe          = cb_pcidas64_pci_probe,
4093         .remove         = comedi_pci_auto_unconfig,
4094 };
4095 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4096 
4097 MODULE_AUTHOR("Comedi http://www.comedi.org");
4098 MODULE_DESCRIPTION("Comedi low-level driver");
4099 MODULE_LICENSE("GPL");
4100 

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