Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5

Linux/drivers/staging/comedi/drivers/amplc_dio200_pci.c

  1 /* comedi/drivers/amplc_dio200_pci.c
  2  *
  3  * Driver for Amplicon PCI215, PCI272, PCIe215, PCIe236, PCIe296.
  4  *
  5  * Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/>
  6  *
  7  * COMEDI - Linux Control and Measurement Device Interface
  8  * Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License as published by
 12  * the Free Software Foundation; either version 2 of the License, or
 13  * (at your option) any later version.
 14  *
 15  * This program is distributed in the hope that it will be useful,
 16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 18  * GNU General Public License for more details.
 19  */
 20 
 21 /*
 22  * Driver: amplc_dio200_pci
 23  * Description: Amplicon 200 Series PCI Digital I/O
 24  * Author: Ian Abbott <abbotti@mev.co.uk>
 25  * Devices: [Amplicon] PCI215 (amplc_dio200_pci), PCIe215, PCIe236,
 26  *   PCI272, PCIe296
 27  * Updated: Mon, 18 Mar 2013 15:03:50 +0000
 28  * Status: works
 29  *
 30  * Configuration options:
 31  *   none
 32  *
 33  * Manual configuration of PCI(e) cards is not supported; they are configured
 34  * automatically.
 35  *
 36  * SUBDEVICES
 37  *
 38  *                     PCI215         PCIe215        PCIe236
 39  *                  -------------  -------------  -------------
 40  *   Subdevices           5              8              8
 41  *    0                 PPI-X          PPI-X          PPI-X
 42  *    1                 PPI-Y          UNUSED         UNUSED
 43  *    2                 CTR-Z1         PPI-Y          UNUSED
 44  *    3                 CTR-Z2         UNUSED         UNUSED
 45  *    4               INTERRUPT        CTR-Z1         CTR-Z1
 46  *    5                                CTR-Z2         CTR-Z2
 47  *    6                                TIMER          TIMER
 48  *    7                              INTERRUPT      INTERRUPT
 49  *
 50  *
 51  *                     PCI272         PCIe296
 52  *                  -------------  -------------
 53  *   Subdevices           4              8
 54  *    0                 PPI-X          PPI-X1
 55  *    1                 PPI-Y          PPI-X2
 56  *    2                 PPI-Z          PPI-Y1
 57  *    3               INTERRUPT        PPI-Y2
 58  *    4                                CTR-Z1
 59  *    5                                CTR-Z2
 60  *    6                                TIMER
 61  *    7                              INTERRUPT
 62  *
 63  * Each PPI is a 8255 chip providing 24 DIO channels.  The DIO channels
 64  * are configurable as inputs or outputs in four groups:
 65  *
 66  *   Port A  - channels  0 to  7
 67  *   Port B  - channels  8 to 15
 68  *   Port CL - channels 16 to 19
 69  *   Port CH - channels 20 to 23
 70  *
 71  * Only mode 0 of the 8255 chips is supported.
 72  *
 73  * Each CTR is a 8254 chip providing 3 16-bit counter channels.  Each
 74  * channel is configured individually with INSN_CONFIG instructions.  The
 75  * specific type of configuration instruction is specified in data[0].
 76  * Some configuration instructions expect an additional parameter in
 77  * data[1]; others return a value in data[1].  The following configuration
 78  * instructions are supported:
 79  *
 80  *   INSN_CONFIG_SET_COUNTER_MODE.  Sets the counter channel's mode and
 81  *     BCD/binary setting specified in data[1].
 82  *
 83  *   INSN_CONFIG_8254_READ_STATUS.  Reads the status register value for the
 84  *     counter channel into data[1].
 85  *
 86  *   INSN_CONFIG_SET_CLOCK_SRC.  Sets the counter channel's clock source as
 87  *     specified in data[1] (this is a hardware-specific value).  Not
 88  *     supported on PC214E.  For the other boards, valid clock sources are
 89  *     0 to 7 as follows:
 90  *
 91  *       0.  CLK n, the counter channel's dedicated CLK input from the SK1
 92  *         connector.  (N.B. for other values, the counter channel's CLKn
 93  *         pin on the SK1 connector is an output!)
 94  *       1.  Internal 10 MHz clock.
 95  *       2.  Internal 1 MHz clock.
 96  *       3.  Internal 100 kHz clock.
 97  *       4.  Internal 10 kHz clock.
 98  *       5.  Internal 1 kHz clock.
 99  *       6.  OUT n-1, the output of counter channel n-1 (see note 1 below).
100  *       7.  Ext Clock, the counter chip's dedicated Ext Clock input from
101  *         the SK1 connector.  This pin is shared by all three counter
102  *         channels on the chip.
103  *
104  *     For the PCIe boards, clock sources in the range 0 to 31 are allowed
105  *     and the following additional clock sources are defined:
106  *
107  *       8.  HIGH logic level.
108  *       9.  LOW logic level.
109  *      10.  "Pattern present" signal.
110  *      11.  Internal 20 MHz clock.
111  *
112  *   INSN_CONFIG_GET_CLOCK_SRC.  Returns the counter channel's current
113  *     clock source in data[1].  For internal clock sources, data[2] is set
114  *     to the period in ns.
115  *
116  *   INSN_CONFIG_SET_GATE_SRC.  Sets the counter channel's gate source as
117  *     specified in data[2] (this is a hardware-specific value).  Not
118  *     supported on PC214E.  For the other boards, valid gate sources are 0
119  *     to 7 as follows:
120  *
121  *       0.  VCC (internal +5V d.c.), i.e. gate permanently enabled.
122  *       1.  GND (internal 0V d.c.), i.e. gate permanently disabled.
123  *       2.  GAT n, the counter channel's dedicated GAT input from the SK1
124  *         connector.  (N.B. for other values, the counter channel's GATn
125  *         pin on the SK1 connector is an output!)
126  *       3.  /OUT n-2, the inverted output of counter channel n-2 (see note
127  *         2 below).
128  *       4.  Reserved.
129  *       5.  Reserved.
130  *       6.  Reserved.
131  *       7.  Reserved.
132  *
133  *     For the PCIe boards, gate sources in the range 0 to 31 are allowed;
134  *     the following additional clock sources and clock sources 6 and 7 are
135  *     (re)defined:
136  *
137  *       6.  /GAT n, negated version of the counter channel's dedicated
138  *         GAT input (negated version of gate source 2).
139  *       7.  OUT n-2, the non-inverted output of counter channel n-2
140  *         (negated version of gate source 3).
141  *       8.  "Pattern present" signal, HIGH while pattern present.
142  *       9.  "Pattern occurred" latched signal, latches HIGH when pattern
143  *         occurs.
144  *      10.  "Pattern gone away" latched signal, latches LOW when pattern
145  *         goes away after it occurred.
146  *      11.  Negated "pattern present" signal, LOW while pattern present
147  *         (negated version of gate source 8).
148  *      12.  Negated "pattern occurred" latched signal, latches LOW when
149  *         pattern occurs (negated version of gate source 9).
150  *      13.  Negated "pattern gone away" latched signal, latches LOW when
151  *         pattern goes away after it occurred (negated version of gate
152  *         source 10).
153  *
154  *   INSN_CONFIG_GET_GATE_SRC.  Returns the counter channel's current gate
155  *     source in data[2].
156  *
157  * Clock and gate interconnection notes:
158  *
159  *   1.  Clock source OUT n-1 is the output of the preceding channel on the
160  *   same counter subdevice if n > 0, or the output of channel 2 on the
161  *   preceding counter subdevice (see note 3) if n = 0.
162  *
163  *   2.  Gate source /OUT n-2 is the inverted output of channel 0 on the
164  *   same counter subdevice if n = 2, or the inverted output of channel n+1
165  *   on the preceding counter subdevice (see note 3) if n < 2.
166  *
167  *   3.  The counter subdevices are connected in a ring, so the highest
168  *   counter subdevice precedes the lowest.
169  *
170  * The 'TIMER' subdevice is a free-running 32-bit timer subdevice.
171  *
172  * The 'INTERRUPT' subdevice pretends to be a digital input subdevice.  The
173  * digital inputs come from the interrupt status register.  The number of
174  * channels matches the number of interrupt sources.  The PC214E does not
175  * have an interrupt status register; see notes on 'INTERRUPT SOURCES'
176  * below.
177  *
178  * INTERRUPT SOURCES
179  *
180  *                     PCI215         PCIe215        PCIe236
181  *                  -------------  -------------  -------------
182  *   Sources              6              6              6
183  *    0               PPI-X-C0       PPI-X-C0       PPI-X-C0
184  *    1               PPI-X-C3       PPI-X-C3       PPI-X-C3
185  *    2               PPI-Y-C0       PPI-Y-C0        unused
186  *    3               PPI-Y-C3       PPI-Y-C3        unused
187  *    4              CTR-Z1-OUT1    CTR-Z1-OUT1    CTR-Z1-OUT1
188  *    5              CTR-Z2-OUT1    CTR-Z2-OUT1    CTR-Z2-OUT1
189  *
190  *                     PCI272         PCIe296
191  *                  -------------  -------------
192  *   Sources              6              6
193  *    0               PPI-X-C0       PPI-X1-C0
194  *    1               PPI-X-C3       PPI-X1-C3
195  *    2               PPI-Y-C0       PPI-Y1-C0
196  *    3               PPI-Y-C3       PPI-Y1-C3
197  *    4               PPI-Z-C0      CTR-Z1-OUT1
198  *    5               PPI-Z-C3      CTR-Z2-OUT1
199  *
200  * When an interrupt source is enabled in the interrupt source enable
201  * register, a rising edge on the source signal latches the corresponding
202  * bit to 1 in the interrupt status register.
203  *
204  * When the interrupt status register value as a whole (actually, just the
205  * 6 least significant bits) goes from zero to non-zero, the board will
206  * generate an interrupt.  The interrupt will remain asserted until the
207  * interrupt status register is cleared to zero.  To clear a bit to zero in
208  * the interrupt status register, the corresponding interrupt source must
209  * be disabled in the interrupt source enable register (there is no
210  * separate interrupt clear register).
211  *
212  * COMMANDS
213  *
214  * The driver supports a read streaming acquisition command on the
215  * 'INTERRUPT' subdevice.  The channel list selects the interrupt sources
216  * to be enabled.  All channels will be sampled together (convert_src ==
217  * TRIG_NOW).  The scan begins a short time after the hardware interrupt
218  * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
219  * scan_begin_arg == 0).  The value read from the interrupt status register
220  * is packed into a short value, one bit per requested channel, in the
221  * order they appear in the channel list.
222  */
223 
224 #include <linux/module.h>
225 #include <linux/interrupt.h>
226 
227 #include "../comedi_pci.h"
228 
229 #include "amplc_dio200.h"
230 
231 /*
232  * Board descriptions.
233  */
234 
235 enum dio200_pci_model {
236         pci215_model,
237         pci272_model,
238         pcie215_model,
239         pcie236_model,
240         pcie296_model
241 };
242 
243 static const struct dio200_board dio200_pci_boards[] = {
244         [pci215_model] = {
245                 .name           = "pci215",
246                 .mainbar        = 2,
247                 .n_subdevs      = 5,
248                 .sdtype         = {
249                         sd_8255, sd_8255, sd_8254, sd_8254, sd_intr
250                 },
251                 .sdinfo         = { 0x00, 0x08, 0x10, 0x14, 0x3f },
252                 .has_int_sce    = true,
253                 .has_clk_gat_sce = true,
254         },
255         [pci272_model] = {
256                 .name           = "pci272",
257                 .mainbar        = 2,
258                 .n_subdevs      = 4,
259                 .sdtype         = {
260                         sd_8255, sd_8255, sd_8255, sd_intr
261                 },
262                 .sdinfo         = { 0x00, 0x08, 0x10, 0x3f },
263                 .has_int_sce    = true,
264         },
265         [pcie215_model] = {
266                 .name           = "pcie215",
267                 .mainbar        = 1,
268                 .n_subdevs      = 8,
269                 .sdtype         = {
270                         sd_8255, sd_none, sd_8255, sd_none,
271                         sd_8254, sd_8254, sd_timer, sd_intr
272                 },
273                 .sdinfo         = {
274                         0x00, 0x00, 0x08, 0x00, 0x10, 0x14, 0x00, 0x3f
275                 },
276                 .has_int_sce    = true,
277                 .has_clk_gat_sce = true,
278                 .is_pcie        = true,
279         },
280         [pcie236_model] = {
281                 .name           = "pcie236",
282                 .mainbar        = 1,
283                 .n_subdevs      = 8,
284                 .sdtype         = {
285                         sd_8255, sd_none, sd_none, sd_none,
286                         sd_8254, sd_8254, sd_timer, sd_intr
287                 },
288                 .sdinfo         = {
289                         0x00, 0x00, 0x00, 0x00, 0x10, 0x14, 0x00, 0x3f
290                 },
291                 .has_int_sce    = true,
292                 .has_clk_gat_sce = true,
293                 .is_pcie        = true,
294         },
295         [pcie296_model] = {
296                 .name           = "pcie296",
297                 .mainbar        = 1,
298                 .n_subdevs      = 8,
299                 .sdtype         = {
300                         sd_8255, sd_8255, sd_8255, sd_8255,
301                         sd_8254, sd_8254, sd_timer, sd_intr
302                 },
303                 .sdinfo         = {
304                         0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x00, 0x3f
305                 },
306                 .has_int_sce    = true,
307                 .has_clk_gat_sce = true,
308                 .is_pcie        = true,
309         },
310 };
311 
312 /*
313  * This function does some special set-up for the PCIe boards
314  * PCIe215, PCIe236, PCIe296.
315  */
316 static int dio200_pcie_board_setup(struct comedi_device *dev)
317 {
318         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
319         void __iomem *brbase;
320 
321         /*
322          * The board uses Altera Cyclone IV with PCI-Express hard IP.
323          * The FPGA configuration has the PCI-Express Avalon-MM Bridge
324          * Control registers in PCI BAR 0, offset 0, and the length of
325          * these registers is 0x4000.
326          *
327          * We need to write 0x80 to the "Avalon-MM to PCI-Express Interrupt
328          * Enable" register at offset 0x50 to allow generation of PCIe
329          * interrupts when RXmlrq_i is asserted in the SOPC Builder system.
330          */
331         if (pci_resource_len(pcidev, 0) < 0x4000) {
332                 dev_err(dev->class_dev, "error! bad PCI region!\n");
333                 return -EINVAL;
334         }
335         brbase = pci_ioremap_bar(pcidev, 0);
336         if (!brbase) {
337                 dev_err(dev->class_dev, "error! failed to map registers!\n");
338                 return -ENOMEM;
339         }
340         writel(0x80, brbase + 0x50);
341         iounmap(brbase);
342         /* Enable "enhanced" features of board. */
343         amplc_dio200_set_enhance(dev, 1);
344         return 0;
345 }
346 
347 static int dio200_pci_auto_attach(struct comedi_device *dev,
348                                   unsigned long context_model)
349 {
350         struct pci_dev *pci_dev = comedi_to_pci_dev(dev);
351         const struct dio200_board *board = NULL;
352         unsigned int bar;
353         int ret;
354 
355         if (context_model < ARRAY_SIZE(dio200_pci_boards))
356                 board = &dio200_pci_boards[context_model];
357         if (!board)
358                 return -EINVAL;
359         dev->board_ptr = board;
360         dev->board_name = board->name;
361 
362         dev_info(dev->class_dev, "%s: attach pci %s (%s)\n",
363                  dev->driver->driver_name, pci_name(pci_dev), dev->board_name);
364 
365         ret = comedi_pci_enable(dev);
366         if (ret)
367                 return ret;
368 
369         bar = board->mainbar;
370         if (pci_resource_flags(pci_dev, bar) & IORESOURCE_MEM) {
371                 dev->mmio = pci_ioremap_bar(pci_dev, bar);
372                 if (!dev->mmio) {
373                         dev_err(dev->class_dev,
374                                 "error! cannot remap registers\n");
375                         return -ENOMEM;
376                 }
377         } else {
378                 dev->iobase = pci_resource_start(pci_dev, bar);
379         }
380 
381         if (board->is_pcie) {
382                 ret = dio200_pcie_board_setup(dev);
383                 if (ret < 0)
384                         return ret;
385         }
386 
387         return amplc_dio200_common_attach(dev, pci_dev->irq, IRQF_SHARED);
388 }
389 
390 static struct comedi_driver dio200_pci_comedi_driver = {
391         .driver_name    = "amplc_dio200_pci",
392         .module         = THIS_MODULE,
393         .auto_attach    = dio200_pci_auto_attach,
394         .detach         = comedi_pci_detach,
395 };
396 
397 static const struct pci_device_id dio200_pci_table[] = {
398         { PCI_VDEVICE(AMPLICON, 0x000b), pci215_model },
399         { PCI_VDEVICE(AMPLICON, 0x000a), pci272_model },
400         { PCI_VDEVICE(AMPLICON, 0x0011), pcie236_model },
401         { PCI_VDEVICE(AMPLICON, 0x0012), pcie215_model },
402         { PCI_VDEVICE(AMPLICON, 0x0014), pcie296_model },
403         {0}
404 };
405 
406 MODULE_DEVICE_TABLE(pci, dio200_pci_table);
407 
408 static int dio200_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
409 {
410         return comedi_pci_auto_config(dev, &dio200_pci_comedi_driver,
411                                       id->driver_data);
412 }
413 
414 static struct pci_driver dio200_pci_pci_driver = {
415         .name           = "amplc_dio200_pci",
416         .id_table       = dio200_pci_table,
417         .probe          = dio200_pci_probe,
418         .remove         = comedi_pci_auto_unconfig,
419 };
420 module_comedi_pci_driver(dio200_pci_comedi_driver, dio200_pci_pci_driver);
421 
422 MODULE_AUTHOR("Comedi http://www.comedi.org");
423 MODULE_DESCRIPTION("Comedi driver for Amplicon 200 Series PCI(e) DIO boards");
424 MODULE_LICENSE("GPL");
425 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us