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Linux/drivers/staging/comedi/drivers/adl_pci9118.c

  1 /*
  2  *  comedi/drivers/adl_pci9118.c
  3  *
  4  *  hardware driver for ADLink cards:
  5  *   card:   PCI-9118DG, PCI-9118HG, PCI-9118HR
  6  *   driver: pci9118dg,  pci9118hg,  pci9118hr
  7  *
  8  * Author: Michal Dobes <dobes@tesnet.cz>
  9  *
 10  */
 11 
 12 /*
 13  * Driver: adl_pci9118
 14  * Description: Adlink PCI-9118DG, PCI-9118HG, PCI-9118HR
 15  * Author: Michal Dobes <dobes@tesnet.cz>
 16  * Devices: [ADLink] PCI-9118DG (pci9118dg), PCI-9118HG (pci9118hg),
 17  * PCI-9118HR (pci9118hr)
 18  * Status: works
 19  *
 20  * This driver supports AI, AO, DI and DO subdevices.
 21  * AI subdevice supports cmd and insn interface,
 22  * other subdevices support only insn interface.
 23  * For AI:
 24  * - If cmd->scan_begin_src=TRIG_EXT then trigger input is TGIN (pin 46).
 25  * - If cmd->convert_src=TRIG_EXT then trigger input is EXTTRG (pin 44).
 26  * - If cmd->start_src/stop_src=TRIG_EXT then trigger input is TGIN (pin 46).
 27  * - It is not necessary to have cmd.scan_end_arg=cmd.chanlist_len but
 28  * cmd.scan_end_arg modulo cmd.chanlist_len must by 0.
 29  * - If return value of cmdtest is 5 then you've bad channel list
 30  * (it isn't possible mixture S.E. and DIFF inputs or bipolar and unipolar
 31  * ranges).
 32  *
 33  * There are some hardware limitations:
 34  * a) You cann't use mixture of unipolar/bipoar ranges or differencial/single
 35  *  ended inputs.
 36  * b) DMA transfers must have the length aligned to two samples (32 bit),
 37  *  so there is some problems if cmd->chanlist_len is odd. This driver tries
 38  *  bypass this with adding one sample to the end of the every scan and discard
 39  *  it on output but this can't be used if cmd->scan_begin_src=TRIG_FOLLOW
 40  *  and is used flag CMDF_WAKE_EOS, then driver switch to interrupt driven mode
 41  *  with interrupt after every sample.
 42  * c) If isn't used DMA then you can use only mode where
 43  *  cmd->scan_begin_src=TRIG_FOLLOW.
 44  *
 45  * Configuration options:
 46  * [0] - PCI bus of device (optional)
 47  * [1] - PCI slot of device (optional)
 48  *       If bus/slot is not specified, then first available PCI
 49  *       card will be used.
 50  * [2] - 0= standard 8 DIFF/16 SE channels configuration
 51  *       n = external multiplexer connected, 1 <= n <= 256
 52  * [3] - ignored
 53  * [4] - sample&hold signal - card can generate signal for external S&H board
 54  *       0 = use SSHO(pin 45) signal is generated in onboard hardware S&H logic
 55  *       0 != use ADCHN7(pin 23) signal is generated from driver, number say how
 56  *              long delay is requested in ns and sign polarity of the hold
 57  *              (in this case external multiplexor can serve only 128 channels)
 58  * [5] - ignored
 59  */
 60 
 61 /*
 62  * FIXME
 63  *
 64  * All the supported boards have the same PCI vendor and device IDs, so
 65  * auto-attachment of PCI devices will always find the first board type.
 66  *
 67  * Perhaps the boards have different subdevice IDs that we could use to
 68  * distinguish them?
 69  *
 70  * Need some device attributes so the board type can be corrected after
 71  * attachment if necessary, and possibly to set other options supported by
 72  * manual attachment.
 73  */
 74 
 75 #include <linux/module.h>
 76 #include <linux/pci.h>
 77 #include <linux/delay.h>
 78 #include <linux/gfp.h>
 79 #include <linux/interrupt.h>
 80 #include <linux/io.h>
 81 
 82 #include "../comedidev.h"
 83 
 84 #include "amcc_s5933.h"
 85 #include "8253.h"
 86 #include "comedi_fc.h"
 87 
 88 #define IORANGE_9118    64      /* I hope */
 89 #define PCI9118_CHANLEN 255     /*
 90                                  * len of chanlist, some source say 256,
 91                                  * but reality looks like 255 :-(
 92                                  */
 93 
 94 /*
 95  * PCI BAR2 Register map (dev->iobase)
 96  */
 97 #define PCI9118_TIMER_REG(x)            (0x00 + ((x) * 4))
 98 #define PCI9118_TIMER_CTRL_REG          0x0c
 99 #define PCI9118_AI_FIFO_REG             0x10
100 #define PCI9118_AO_REG(x)               (0x10 + ((x) * 4))
101 #define PCI9118_AI_STATUS_REG           0x18
102 #define PCI9118_AI_STATUS_NFULL         (1 << 8)  /* 0=FIFO full (fatal) */
103 #define PCI9118_AI_STATUS_NHFULL        (1 << 7)  /* 0=FIFO half full */
104 #define PCI9118_AI_STATUS_NEPTY         (1 << 6)  /* 0=FIFO empty */
105 #define PCI9118_AI_STATUS_ACMP          (1 << 5)  /* 1=about trigger complete */
106 #define PCI9118_AI_STATUS_DTH           (1 << 4)  /* 1=ext. digital trigger */
107 #define PCI9118_AI_STATUS_BOVER         (1 << 3)  /* 1=burst overrun (fatal) */
108 #define PCI9118_AI_STATUS_ADOS          (1 << 2)  /* 1=A/D over speed (warn) */
109 #define PCI9118_AI_STATUS_ADOR          (1 << 1)  /* 1=A/D overrun (fatal) */
110 #define PCI9118_AI_STATUS_ADRDY         (1 << 0)  /* 1=A/D ready */
111 #define PCI9118_AI_CTRL_REG             0x18
112 #define PCI9118_AI_CTRL_UNIP            (1 << 7)  /* 1=unipolar */
113 #define PCI9118_AI_CTRL_DIFF            (1 << 6)  /* 1=differential inputs */
114 #define PCI9118_AI_CTRL_SOFTG           (1 << 5)  /* 1=8254 software gate */
115 #define PCI9118_AI_CTRL_EXTG            (1 << 4)  /* 1=8254 TGIN(pin 46) gate */
116 #define PCI9118_AI_CTRL_EXTM            (1 << 3)  /* 1=ext. trigger (pin 44) */
117 #define PCI9118_AI_CTRL_TMRTR           (1 << 2)  /* 1=8254 is trigger source */
118 #define PCI9118_AI_CTRL_INT             (1 << 1)  /* 1=enable interrupt */
119 #define PCI9118_AI_CTRL_DMA             (1 << 0)  /* 1=enable DMA */
120 #define PCI9118_DIO_REG                 0x1c
121 #define PCI9118_SOFTTRG_REG             0x20
122 #define PCI9118_AI_CHANLIST_REG         0x24
123 #define PCI9118_AI_CHANLIST_RANGE(x)    (((x) & 0x3) << 8)
124 #define PCI9118_AI_CHANLIST_CHAN(x)     ((x) << 0)
125 #define PCI9118_AI_BURST_NUM_REG        0x28
126 #define PCI9118_AI_AUTOSCAN_MODE_REG    0x2c
127 #define PCI9118_AI_CFG_REG              0x30
128 #define PCI9118_AI_CFG_PDTRG            (1 << 7)  /* 1=positive trigger */
129 #define PCI9118_AI_CFG_PETRG            (1 << 6)  /* 1=positive ext. trigger */
130 #define PCI9118_AI_CFG_BSSH             (1 << 5)  /* 1=with sample & hold */
131 #define PCI9118_AI_CFG_BM               (1 << 4)  /* 1=burst mode */
132 #define PCI9118_AI_CFG_BS               (1 << 3)  /* 1=burst mode start */
133 #define PCI9118_AI_CFG_PM               (1 << 2)  /* 1=post trigger */
134 #define PCI9118_AI_CFG_AM               (1 << 1)  /* 1=about trigger */
135 #define PCI9118_AI_CFG_START            (1 << 0)  /* 1=trigger start */
136 #define PCI9118_FIFO_RESET_REG          0x34
137 #define PCI9118_INT_CTRL_REG            0x38
138 #define PCI9118_INT_CTRL_TIMER          (1 << 3)  /* timer interrupt */
139 #define PCI9118_INT_CTRL_ABOUT          (1 << 2)  /* about trigger complete */
140 #define PCI9118_INT_CTRL_HFULL          (1 << 1)  /* A/D FIFO half full */
141 #define PCI9118_INT_CTRL_DTRG           (1 << 0)  /* ext. digital trigger */
142 
143 #define START_AI_EXT    0x01    /* start measure on external trigger */
144 #define STOP_AI_EXT     0x02    /* stop measure on external trigger */
145 #define STOP_AI_INT     0x08    /* stop measure on internal trigger */
146 
147 #define PCI9118_HALF_FIFO_SZ    (1024 / 2)
148 
149 static const struct comedi_lrange pci9118_ai_range = {
150         8, {
151                 BIP_RANGE(5),
152                 BIP_RANGE(2.5),
153                 BIP_RANGE(1.25),
154                 BIP_RANGE(0.625),
155                 UNI_RANGE(10),
156                 UNI_RANGE(5),
157                 UNI_RANGE(2.5),
158                 UNI_RANGE(1.25)
159         }
160 };
161 
162 static const struct comedi_lrange pci9118hg_ai_range = {
163         8, {
164                 BIP_RANGE(5),
165                 BIP_RANGE(0.5),
166                 BIP_RANGE(0.05),
167                 BIP_RANGE(0.005),
168                 UNI_RANGE(10),
169                 UNI_RANGE(1),
170                 UNI_RANGE(0.1),
171                 UNI_RANGE(0.01)
172         }
173 };
174 
175 #define PCI9118_BIPOLAR_RANGES  4       /*
176                                          * used for test on mixture
177                                          * of BIP/UNI ranges
178                                          */
179 
180 enum pci9118_boardid {
181         BOARD_PCI9118DG,
182         BOARD_PCI9118HG,
183         BOARD_PCI9118HR,
184 };
185 
186 struct pci9118_boardinfo {
187         const char *name;
188         unsigned int ai_is_16bit:1;
189         unsigned int is_hg:1;
190 };
191 
192 static const struct pci9118_boardinfo pci9118_boards[] = {
193         [BOARD_PCI9118DG] = {
194                 .name           = "pci9118dg",
195         },
196         [BOARD_PCI9118HG] = {
197                 .name           = "pci9118hg",
198                 .is_hg          = 1,
199         },
200         [BOARD_PCI9118HR] = {
201                 .name           = "pci9118hr",
202                 .ai_is_16bit    = 1,
203         },
204 };
205 
206 struct pci9118_dmabuf {
207         unsigned short *virt;   /* virtual address of buffer */
208         dma_addr_t hw;          /* hardware (bus) address of buffer */
209         unsigned int size;      /* size of dma buffer in bytes */
210         unsigned int use_size;  /* which size we may now use for transfer */
211 };
212 
213 struct pci9118_private {
214         unsigned long iobase_a; /* base+size for AMCC chip */
215         unsigned int master:1;
216         unsigned int dma_doublebuf:1;
217         unsigned int ai_neverending:1;
218         unsigned int usedma:1;
219         unsigned int usemux:1;
220         unsigned char ai_ctrl;
221         unsigned char int_ctrl;
222         unsigned char ai_cfg;
223         unsigned int ai_do;             /* what do AI? 0=nothing, 1 to 4 mode */
224         unsigned int ai_act_scan;       /* how many scans we finished */
225         unsigned int ai_n_realscanlen;  /*
226                                          * what we must transfer for one
227                                          * outgoing scan include front/back adds
228                                          */
229         unsigned int ai_act_dmapos;     /* position in actual real stream */
230         unsigned int ai_add_front;      /*
231                                          * how many channels we must add
232                                          * before scan to satisfy S&H?
233                                          */
234         unsigned int ai_add_back;       /*
235                                          * how many channels we must add
236                                          * before scan to satisfy DMA?
237                                          */
238         unsigned int ai_flags;
239         char ai12_startstop;            /*
240                                          * measure can start/stop
241                                          * on external trigger
242                                          */
243         unsigned int ai_divisor1, ai_divisor2;  /*
244                                                  * divisors for start of measure
245                                                  * on external start
246                                                  */
247         unsigned int dma_actbuf;                /* which buffer is used now */
248         struct pci9118_dmabuf dmabuf[2];
249         int softsshdelay;               /*
250                                          * >0 use software S&H,
251                                          * numer is requested delay in ns
252                                          */
253         unsigned char softsshsample;    /*
254                                          * polarity of S&H signal
255                                          * in sample state
256                                          */
257         unsigned char softsshhold;      /*
258                                          * polarity of S&H signal
259                                          * in hold state
260                                          */
261         unsigned int ai_ns_min;
262 };
263 
264 static void pci9118_amcc_setup_dma(struct comedi_device *dev, unsigned int buf)
265 {
266         struct pci9118_private *devpriv = dev->private;
267         struct pci9118_dmabuf *dmabuf = &devpriv->dmabuf[buf];
268 
269         /* set the master write address and transfer count */
270         outl(dmabuf->hw, devpriv->iobase_a + AMCC_OP_REG_MWAR);
271         outl(dmabuf->use_size, devpriv->iobase_a + AMCC_OP_REG_MWTC);
272 }
273 
274 static void pci9118_amcc_dma_ena(struct comedi_device *dev, bool enable)
275 {
276         struct pci9118_private *devpriv = dev->private;
277         unsigned int mcsr;
278 
279         mcsr = inl(devpriv->iobase_a + AMCC_OP_REG_MCSR);
280         if (enable)
281                 mcsr |= RESET_A2P_FLAGS | A2P_HI_PRIORITY | EN_A2P_TRANSFERS;
282         else
283                 mcsr &= ~EN_A2P_TRANSFERS;
284         outl(mcsr, devpriv->iobase_a + AMCC_OP_REG_MCSR);
285 }
286 
287 static void pci9118_amcc_int_ena(struct comedi_device *dev, bool enable)
288 {
289         struct pci9118_private *devpriv = dev->private;
290         unsigned int intcsr;
291 
292         /* enable/disable interrupt for AMCC Incoming Mailbox 4 (32-bit) */
293         intcsr = inl(devpriv->iobase_a + AMCC_OP_REG_INTCSR);
294         if (enable)
295                 intcsr |= 0x1f00;
296         else
297                 intcsr &= ~0x1f00;
298         outl(intcsr, devpriv->iobase_a + AMCC_OP_REG_INTCSR);
299 }
300 
301 static void pci9118_timer_write(struct comedi_device *dev,
302                                 unsigned int timer, unsigned int val)
303 {
304         outl(val & 0xff, dev->iobase + PCI9118_TIMER_REG(timer));
305         outl((val >> 8) & 0xff, dev->iobase + PCI9118_TIMER_REG(timer));
306 }
307 
308 static void pci9118_timer_set_mode(struct comedi_device *dev,
309                                    unsigned int timer, unsigned int mode)
310 {
311         unsigned int val;
312 
313         val = timer << 6;       /* select timer */
314         val |= 0x30;            /* load low then high byte */
315         val |= mode;            /* set timer mode and BCD|binary */
316         outl(val, dev->iobase + PCI9118_TIMER_CTRL_REG);
317 }
318 
319 static void pci9118_ai_reset_fifo(struct comedi_device *dev)
320 {
321         /* writing any value resets the A/D FIFO */
322         outl(0, dev->iobase + PCI9118_FIFO_RESET_REG);
323 }
324 
325 static int check_channel_list(struct comedi_device *dev,
326                               struct comedi_subdevice *s, int n_chan,
327                               unsigned int *chanlist, int frontadd, int backadd)
328 {
329         struct pci9118_private *devpriv = dev->private;
330         unsigned int i, differencial = 0, bipolar = 0;
331 
332         /* correct channel and range number check itself comedi/range.c */
333         if (n_chan < 1) {
334                 dev_err(dev->class_dev, "range/channel list is empty!\n");
335                 return 0;
336         }
337         if ((frontadd + n_chan + backadd) > s->len_chanlist) {
338                 dev_err(dev->class_dev,
339                         "range/channel list is too long for actual configuration!\n");
340                 return 0;
341         }
342 
343         if (CR_AREF(chanlist[0]) == AREF_DIFF)
344                 differencial = 1;       /* all input must be diff */
345         if (CR_RANGE(chanlist[0]) < PCI9118_BIPOLAR_RANGES)
346                 bipolar = 1;    /* all input must be bipolar */
347         if (n_chan > 1)
348                 for (i = 1; i < n_chan; i++) {  /* check S.E/diff */
349                         if ((CR_AREF(chanlist[i]) == AREF_DIFF) !=
350                             (differencial)) {
351                                 dev_err(dev->class_dev,
352                                         "Differential and single ended inputs can't be mixed!\n");
353                                 return 0;
354                         }
355                         if ((CR_RANGE(chanlist[i]) < PCI9118_BIPOLAR_RANGES) !=
356                             (bipolar)) {
357                                 dev_err(dev->class_dev,
358                                         "Bipolar and unipolar ranges can't be mixed!\n");
359                                 return 0;
360                         }
361                         if (!devpriv->usemux && differencial &&
362                             (CR_CHAN(chanlist[i]) >= (s->n_chan / 2))) {
363                                 dev_err(dev->class_dev,
364                                         "AREF_DIFF is only available for the first 8 channels!\n");
365                                 return 0;
366                         }
367                 }
368 
369         return 1;
370 }
371 
372 static void pci9118_set_chanlist(struct comedi_device *dev,
373                                  struct comedi_subdevice *s,
374                                  int n_chan, unsigned int *chanlist,
375                                  int frontadd, int backadd)
376 {
377         struct pci9118_private *devpriv = dev->private;
378         unsigned int chan0 = CR_CHAN(chanlist[0]);
379         unsigned int range0 = CR_RANGE(chanlist[0]);
380         unsigned int aref0 = CR_AREF(chanlist[0]);
381         unsigned int ssh = 0x00;
382         unsigned int val;
383         int i;
384 
385         /*
386          * Configure analog input based on the first chanlist entry.
387          * All entries are either unipolar or bipolar and single-ended
388          * or differential.
389          */
390         devpriv->ai_ctrl = 0;
391         if (comedi_range_is_unipolar(s, range0))
392                 devpriv->ai_ctrl |= PCI9118_AI_CTRL_UNIP;
393         if (aref0 == AREF_DIFF)
394                 devpriv->ai_ctrl |= PCI9118_AI_CTRL_DIFF;
395         outl(devpriv->ai_ctrl, dev->iobase + PCI9118_AI_CTRL_REG);
396 
397         /* gods know why this sequence! */
398         outl(2, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
399         outl(0, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
400         outl(1, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
401 
402         /* insert channels for S&H */
403         if (frontadd) {
404                 val = PCI9118_AI_CHANLIST_CHAN(chan0) |
405                       PCI9118_AI_CHANLIST_RANGE(range0);
406                 ssh = devpriv->softsshsample;
407                 for (i = 0; i < frontadd; i++) {
408                         outl(val | ssh, dev->iobase + PCI9118_AI_CHANLIST_REG);
409                         ssh = devpriv->softsshhold;
410                 }
411         }
412 
413         /* store chanlist */
414         for (i = 0; i < n_chan; i++) {
415                 unsigned int chan = CR_CHAN(chanlist[i]);
416                 unsigned int range = CR_RANGE(chanlist[i]);
417 
418                 val = PCI9118_AI_CHANLIST_CHAN(chan) |
419                       PCI9118_AI_CHANLIST_RANGE(range);
420                 outl(val | ssh, dev->iobase + PCI9118_AI_CHANLIST_REG);
421         }
422 
423         /* insert channels to fit onto 32bit DMA */
424         if (backadd) {
425                 val = PCI9118_AI_CHANLIST_CHAN(chan0) |
426                       PCI9118_AI_CHANLIST_RANGE(range0);
427                 for (i = 0; i < backadd; i++)
428                         outl(val | ssh, dev->iobase + PCI9118_AI_CHANLIST_REG);
429         }
430         /* close scan queue */
431         outl(0, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
432         /* udelay(100); important delay, or first sample will be crippled */
433 }
434 
435 static void interrupt_pci9118_ai_mode4_switch(struct comedi_device *dev,
436                                               unsigned int next_buf)
437 {
438         struct pci9118_private *devpriv = dev->private;
439         struct pci9118_dmabuf *dmabuf = &devpriv->dmabuf[next_buf];
440 
441         devpriv->ai_cfg = PCI9118_AI_CFG_PDTRG | PCI9118_AI_CFG_PETRG |
442                           PCI9118_AI_CFG_AM;
443         outl(devpriv->ai_cfg, dev->iobase + PCI9118_AI_CFG_REG);
444         pci9118_timer_set_mode(dev, 0, I8254_MODE0);
445         pci9118_timer_write(dev, 0, dmabuf->hw >> 1);
446         devpriv->ai_cfg |= PCI9118_AI_CFG_START;
447         outl(devpriv->ai_cfg, dev->iobase + PCI9118_AI_CFG_REG);
448 }
449 
450 static unsigned int defragment_dma_buffer(struct comedi_device *dev,
451                                           struct comedi_subdevice *s,
452                                           unsigned short *dma_buffer,
453                                           unsigned int num_samples)
454 {
455         struct pci9118_private *devpriv = dev->private;
456         struct comedi_cmd *cmd = &s->async->cmd;
457         unsigned int i = 0, j = 0;
458         unsigned int start_pos = devpriv->ai_add_front,
459             stop_pos = devpriv->ai_add_front + cmd->chanlist_len;
460         unsigned int raw_scanlen = devpriv->ai_add_front + cmd->chanlist_len +
461             devpriv->ai_add_back;
462 
463         for (i = 0; i < num_samples; i++) {
464                 if (devpriv->ai_act_dmapos >= start_pos &&
465                     devpriv->ai_act_dmapos < stop_pos) {
466                         dma_buffer[j++] = dma_buffer[i];
467                 }
468                 devpriv->ai_act_dmapos++;
469                 devpriv->ai_act_dmapos %= raw_scanlen;
470         }
471 
472         return j;
473 }
474 
475 static int move_block_from_dma(struct comedi_device *dev,
476                                struct comedi_subdevice *s,
477                                unsigned short *dma_buffer,
478                                unsigned int num_samples)
479 {
480         struct pci9118_private *devpriv = dev->private;
481         struct comedi_cmd *cmd = &s->async->cmd;
482         unsigned int num_bytes;
483 
484         num_samples = defragment_dma_buffer(dev, s, dma_buffer, num_samples);
485         devpriv->ai_act_scan +=
486             (s->async->cur_chan + num_samples) / cmd->scan_end_arg;
487         s->async->cur_chan += num_samples;
488         s->async->cur_chan %= cmd->scan_end_arg;
489         num_bytes =
490             cfc_write_array_to_buffer(s, dma_buffer,
491                                       num_samples * sizeof(short));
492         if (num_bytes < num_samples * sizeof(short))
493                 return -1;
494         return 0;
495 }
496 
497 static void pci9118_exttrg_enable(struct comedi_device *dev, bool enable)
498 {
499         struct pci9118_private *devpriv = dev->private;
500 
501         if (enable)
502                 devpriv->int_ctrl |= PCI9118_INT_CTRL_DTRG;
503         else
504                 devpriv->int_ctrl &= ~PCI9118_INT_CTRL_DTRG;
505         outl(devpriv->int_ctrl, dev->iobase + PCI9118_INT_CTRL_REG);
506 
507         if (devpriv->int_ctrl)
508                 pci9118_amcc_int_ena(dev, true);
509         else
510                 pci9118_amcc_int_ena(dev, false);
511 }
512 
513 static void pci9118_calc_divisors(struct comedi_device *dev,
514                                   struct comedi_subdevice *s,
515                                   unsigned int *tim1, unsigned int *tim2,
516                                   unsigned int flags, int chans,
517                                   unsigned int *div1, unsigned int *div2,
518                                   unsigned int chnsshfront)
519 {
520         struct comedi_cmd *cmd = &s->async->cmd;
521 
522         *div1 = *tim2 / I8254_OSC_BASE_4MHZ;    /* convert timer (burst) */
523         *div2 = *tim1 / I8254_OSC_BASE_4MHZ;    /* scan timer */
524         *div2 = *div2 / *div1;                  /* major timer is c1*c2 */
525         if (*div2 < chans)
526                 *div2 = chans;
527 
528         *tim2 = *div1 * I8254_OSC_BASE_4MHZ;    /* real convert timer */
529 
530         if (cmd->convert_src == TRIG_NOW && !chnsshfront) {
531                 /* use BSSH signal */
532                 if (*div2 < (chans + 2))
533                         *div2 = chans + 2;
534         }
535 
536         *tim1 = *div1 * *div2 * I8254_OSC_BASE_4MHZ;
537 }
538 
539 static void pci9118_start_pacer(struct comedi_device *dev, int mode)
540 {
541         struct pci9118_private *devpriv = dev->private;
542 
543         pci9118_timer_set_mode(dev, 1, I8254_MODE2);
544         pci9118_timer_set_mode(dev, 2, I8254_MODE2);
545         udelay(1);
546 
547         if ((mode == 1) || (mode == 2) || (mode == 4)) {
548                 pci9118_timer_write(dev, 2, devpriv->ai_divisor2);
549                 pci9118_timer_write(dev, 1, devpriv->ai_divisor1);
550         }
551 }
552 
553 static int pci9118_ai_cancel(struct comedi_device *dev,
554                              struct comedi_subdevice *s)
555 {
556         struct pci9118_private *devpriv = dev->private;
557 
558         if (devpriv->usedma)
559                 pci9118_amcc_dma_ena(dev, false);
560         pci9118_exttrg_enable(dev, false);
561         pci9118_start_pacer(dev, 0);    /* stop 8254 counters */
562         /* set default config (disable burst and triggers) */
563         devpriv->ai_cfg = PCI9118_AI_CFG_PDTRG | PCI9118_AI_CFG_PETRG;
564         outl(devpriv->ai_cfg, dev->iobase + PCI9118_AI_CFG_REG);
565         /* reset acqusition control */
566         devpriv->ai_ctrl = 0;
567         outl(devpriv->ai_ctrl, dev->iobase + PCI9118_AI_CTRL_REG);
568         outl(0, dev->iobase + PCI9118_AI_BURST_NUM_REG);
569         /* reset scan queue */
570         outl(1, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
571         outl(2, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
572         pci9118_ai_reset_fifo(dev);
573 
574         devpriv->int_ctrl = 0;
575         outl(devpriv->int_ctrl, dev->iobase + PCI9118_INT_CTRL_REG);
576         pci9118_amcc_int_ena(dev, false);
577 
578         devpriv->ai_do = 0;
579         devpriv->usedma = 0;
580 
581         devpriv->ai_act_scan = 0;
582         devpriv->ai_act_dmapos = 0;
583         s->async->cur_chan = 0;
584         s->async->inttrig = NULL;
585         devpriv->ai_neverending = 0;
586         devpriv->dma_actbuf = 0;
587 
588         return 0;
589 }
590 
591 static void pci9118_ai_munge(struct comedi_device *dev,
592                              struct comedi_subdevice *s, void *data,
593                              unsigned int num_bytes,
594                              unsigned int start_chan_index)
595 {
596         struct pci9118_private *devpriv = dev->private;
597         unsigned int i, num_samples = num_bytes / sizeof(short);
598         unsigned short *array = data;
599 
600         for (i = 0; i < num_samples; i++) {
601                 if (devpriv->usedma)
602                         array[i] = be16_to_cpu(array[i]);
603                 if (s->maxdata == 0xffff)
604                         array[i] ^= 0x8000;
605                 else
606                         array[i] = (array[i] >> 4) & 0x0fff;
607 
608         }
609 }
610 
611 static void interrupt_pci9118_ai_onesample(struct comedi_device *dev,
612                                            struct comedi_subdevice *s)
613 {
614         struct pci9118_private *devpriv = dev->private;
615         struct comedi_cmd *cmd = &s->async->cmd;
616         unsigned short sampl;
617 
618         sampl = inl(dev->iobase + PCI9118_AI_FIFO_REG);
619 
620         cfc_write_to_buffer(s, sampl);
621         s->async->cur_chan++;
622         if (s->async->cur_chan >= cmd->scan_end_arg) {
623                                                         /* one scan done */
624                 s->async->cur_chan %= cmd->scan_end_arg;
625                 devpriv->ai_act_scan++;
626                 if (!devpriv->ai_neverending) {
627                         /* all data sampled? */
628                         if (devpriv->ai_act_scan >= cmd->stop_arg)
629                                 s->async->events |= COMEDI_CB_EOA;
630                 }
631         }
632 }
633 
634 static void interrupt_pci9118_ai_dma(struct comedi_device *dev,
635                                      struct comedi_subdevice *s)
636 {
637         struct pci9118_private *devpriv = dev->private;
638         struct comedi_cmd *cmd = &s->async->cmd;
639         struct pci9118_dmabuf *dmabuf = &devpriv->dmabuf[devpriv->dma_actbuf];
640         unsigned int next_dma_buf, samplesinbuf, sampls, m;
641 
642         samplesinbuf = dmabuf->use_size >> 1;   /* number of received samples */
643 
644         if (devpriv->dma_doublebuf) {   /*
645                                          * switch DMA buffers if is used
646                                          * double buffering
647                                          */
648                 next_dma_buf = 1 - devpriv->dma_actbuf;
649                 pci9118_amcc_setup_dma(dev, next_dma_buf);
650                 if (devpriv->ai_do == 4)
651                         interrupt_pci9118_ai_mode4_switch(dev, next_dma_buf);
652         }
653 
654         if (samplesinbuf) {
655                 /* how many samples is to end of buffer */
656                 m = s->async->prealloc_bufsz >> 1;
657                 sampls = m;
658                 move_block_from_dma(dev, s, dmabuf->virt, samplesinbuf);
659                 m = m - sampls;         /* m=how many samples was transferred */
660         }
661 
662         if (!devpriv->ai_neverending) {
663                 /* all data sampled? */
664                 if (devpriv->ai_act_scan >= cmd->stop_arg)
665                         s->async->events |= COMEDI_CB_EOA;
666         }
667 
668         if (devpriv->dma_doublebuf) {
669                 /* switch dma buffers */
670                 devpriv->dma_actbuf = 1 - devpriv->dma_actbuf;
671         } else {
672                 /* restart DMA if is not used double buffering */
673                 pci9118_amcc_setup_dma(dev, 0);
674                 if (devpriv->ai_do == 4)
675                         interrupt_pci9118_ai_mode4_switch(dev, 0);
676         }
677 }
678 
679 static irqreturn_t pci9118_interrupt(int irq, void *d)
680 {
681         struct comedi_device *dev = d;
682         struct comedi_subdevice *s = dev->read_subdev;
683         struct pci9118_private *devpriv = dev->private;
684         unsigned int intsrc;    /* IRQ reasons from card */
685         unsigned int intcsr;    /* INT register from AMCC chip */
686         unsigned int adstat;    /* STATUS register */
687 
688         if (!dev->attached)
689                 return IRQ_NONE;
690 
691         intsrc = inl(dev->iobase + PCI9118_INT_CTRL_REG) & 0xf;
692         intcsr = inl(devpriv->iobase_a + AMCC_OP_REG_INTCSR);
693 
694         if (!intsrc && !(intcsr & ANY_S593X_INT))
695                 return IRQ_NONE;
696 
697         outl(intcsr | 0x00ff0000, devpriv->iobase_a + AMCC_OP_REG_INTCSR);
698 
699         if (intcsr & MASTER_ABORT_INT) {
700                 dev_err(dev->class_dev, "AMCC IRQ - MASTER DMA ABORT!\n");
701                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
702                 goto interrupt_exit;
703         }
704 
705         if (intcsr & TARGET_ABORT_INT) {
706                 dev_err(dev->class_dev, "AMCC IRQ - TARGET DMA ABORT!\n");
707                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
708                 goto interrupt_exit;
709         }
710 
711         adstat = inl(dev->iobase + PCI9118_AI_STATUS_REG);
712         if ((adstat & PCI9118_AI_STATUS_NFULL) == 0) {
713                 dev_err(dev->class_dev,
714                         "A/D FIFO Full status (Fatal Error!)\n");
715                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW;
716                 goto interrupt_exit;
717         }
718         if (adstat & PCI9118_AI_STATUS_BOVER) {
719                 dev_err(dev->class_dev,
720                         "A/D Burst Mode Overrun Status (Fatal Error!)\n");
721                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW;
722                 goto interrupt_exit;
723         }
724         if (adstat & PCI9118_AI_STATUS_ADOS) {
725                 dev_err(dev->class_dev, "A/D Over Speed Status (Warning!)\n");
726                 s->async->events |= COMEDI_CB_ERROR;
727                 goto interrupt_exit;
728         }
729         if (adstat & PCI9118_AI_STATUS_ADOR) {
730                 dev_err(dev->class_dev, "A/D Overrun Status (Fatal Error!)\n");
731                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW;
732                 goto interrupt_exit;
733         }
734 
735         if (!devpriv->ai_do)
736                 return IRQ_HANDLED;
737 
738         if (devpriv->ai12_startstop) {
739                 if ((adstat & PCI9118_AI_STATUS_DTH) &&
740                     (intsrc & PCI9118_INT_CTRL_DTRG)) {
741                         /* start/stop of measure */
742                         if (devpriv->ai12_startstop & START_AI_EXT) {
743                                 /* deactivate EXT trigger */
744                                 devpriv->ai12_startstop &= ~START_AI_EXT;
745                                 if (!(devpriv->ai12_startstop & STOP_AI_EXT))
746                                         pci9118_exttrg_enable(dev, false);
747 
748                                 /* start pacer */
749                                 pci9118_start_pacer(dev, devpriv->ai_do);
750                                 outl(devpriv->ai_ctrl,
751                                      dev->iobase + PCI9118_AI_CTRL_REG);
752                         } else if (devpriv->ai12_startstop & STOP_AI_EXT) {
753                                 /* deactivate EXT trigger */
754                                 devpriv->ai12_startstop &= ~STOP_AI_EXT;
755                                 pci9118_exttrg_enable(dev, false);
756 
757                                 /* on next interrupt measure will stop */
758                                 devpriv->ai_neverending = 0;
759                         }
760                 }
761         }
762 
763         if (devpriv->usedma)
764                 interrupt_pci9118_ai_dma(dev, s);
765         else
766                 interrupt_pci9118_ai_onesample(dev, s);
767 
768 interrupt_exit:
769         cfc_handle_events(dev, s);
770         return IRQ_HANDLED;
771 }
772 
773 static void pci9118_ai_cmd_start(struct comedi_device *dev)
774 {
775         struct pci9118_private *devpriv = dev->private;
776 
777         outl(devpriv->int_ctrl, dev->iobase + PCI9118_INT_CTRL_REG);
778         outl(devpriv->ai_cfg, dev->iobase + PCI9118_AI_CFG_REG);
779         if (devpriv->ai_do != 3) {
780                 pci9118_start_pacer(dev, devpriv->ai_do);
781                 devpriv->ai_ctrl |= PCI9118_AI_CTRL_SOFTG;
782         }
783         outl(devpriv->ai_ctrl, dev->iobase + PCI9118_AI_CTRL_REG);
784 }
785 
786 static int pci9118_ai_inttrig(struct comedi_device *dev,
787                               struct comedi_subdevice *s,
788                               unsigned int trig_num)
789 {
790         struct comedi_cmd *cmd = &s->async->cmd;
791 
792         if (trig_num != cmd->start_arg)
793                 return -EINVAL;
794 
795         s->async->inttrig = NULL;
796         pci9118_ai_cmd_start(dev);
797 
798         return 1;
799 }
800 
801 static int Compute_and_setup_dma(struct comedi_device *dev,
802                                  struct comedi_subdevice *s)
803 {
804         struct pci9118_private *devpriv = dev->private;
805         struct comedi_cmd *cmd = &s->async->cmd;
806         struct pci9118_dmabuf *dmabuf0 = &devpriv->dmabuf[0];
807         struct pci9118_dmabuf *dmabuf1 = &devpriv->dmabuf[1];
808         unsigned int dmalen0, dmalen1, i;
809 
810         dmalen0 = dmabuf0->size;
811         dmalen1 = dmabuf1->size;
812         /* isn't output buff smaller that our DMA buff? */
813         if (dmalen0 > s->async->prealloc_bufsz) {
814                 /* align to 32bit down */
815                 dmalen0 = s->async->prealloc_bufsz & ~3L;
816         }
817         if (dmalen1 > s->async->prealloc_bufsz) {
818                 /* align to 32bit down */
819                 dmalen1 = s->async->prealloc_bufsz & ~3L;
820         }
821 
822         /* we want wake up every scan? */
823         if (devpriv->ai_flags & CMDF_WAKE_EOS) {
824                 if (dmalen0 < (devpriv->ai_n_realscanlen << 1)) {
825                         /* uff, too short DMA buffer, disable EOS support! */
826                         devpriv->ai_flags &= (~CMDF_WAKE_EOS);
827                         dev_info(dev->class_dev,
828                                  "WAR: DMA0 buf too short, can't support CMDF_WAKE_EOS (%d<%d)\n",
829                                   dmalen0, devpriv->ai_n_realscanlen << 1);
830                 } else {
831                         /* short first DMA buffer to one scan */
832                         dmalen0 = devpriv->ai_n_realscanlen << 1;
833                         if (dmalen0 < 4) {
834                                 dev_info(dev->class_dev,
835                                          "ERR: DMA0 buf len bug? (%d<4)\n",
836                                          dmalen0);
837                                 dmalen0 = 4;
838                         }
839                 }
840         }
841         if (devpriv->ai_flags & CMDF_WAKE_EOS) {
842                 if (dmalen1 < (devpriv->ai_n_realscanlen << 1)) {
843                         /* uff, too short DMA buffer, disable EOS support! */
844                         devpriv->ai_flags &= (~CMDF_WAKE_EOS);
845                         dev_info(dev->class_dev,
846                                  "WAR: DMA1 buf too short, can't support CMDF_WAKE_EOS (%d<%d)\n",
847                                  dmalen1, devpriv->ai_n_realscanlen << 1);
848                 } else {
849                         /* short second DMA buffer to one scan */
850                         dmalen1 = devpriv->ai_n_realscanlen << 1;
851                         if (dmalen1 < 4) {
852                                 dev_info(dev->class_dev,
853                                          "ERR: DMA1 buf len bug? (%d<4)\n",
854                                          dmalen1);
855                                 dmalen1 = 4;
856                         }
857                 }
858         }
859 
860         /* transfer without CMDF_WAKE_EOS */
861         if (!(devpriv->ai_flags & CMDF_WAKE_EOS)) {
862                 /* if it's possible then align DMA buffers to length of scan */
863                 i = dmalen0;
864                 dmalen0 =
865                     (dmalen0 / (devpriv->ai_n_realscanlen << 1)) *
866                     (devpriv->ai_n_realscanlen << 1);
867                 dmalen0 &= ~3L;
868                 if (!dmalen0)
869                         dmalen0 = i;    /* uff. very long scan? */
870                 i = dmalen1;
871                 dmalen1 =
872                     (dmalen1 / (devpriv->ai_n_realscanlen << 1)) *
873                     (devpriv->ai_n_realscanlen << 1);
874                 dmalen1 &= ~3L;
875                 if (!dmalen1)
876                         dmalen1 = i;    /* uff. very long scan? */
877                 /*
878                  * if measure isn't neverending then test, if it fits whole
879                  * into one or two DMA buffers
880                  */
881                 if (!devpriv->ai_neverending) {
882                         /* fits whole measure into one DMA buffer? */
883                         if (dmalen0 >
884                             ((devpriv->ai_n_realscanlen << 1) *
885                              cmd->stop_arg)) {
886                                 dmalen0 =
887                                     (devpriv->ai_n_realscanlen << 1) *
888                                     cmd->stop_arg;
889                                 dmalen0 &= ~3L;
890                         } else {        /*
891                                          * fits whole measure into
892                                          * two DMA buffer?
893                                          */
894                                 if (dmalen1 >
895                                     ((devpriv->ai_n_realscanlen << 1) *
896                                      cmd->stop_arg - dmalen0))
897                                         dmalen1 =
898                                             (devpriv->ai_n_realscanlen << 1) *
899                                             cmd->stop_arg - dmalen0;
900                                 dmalen1 &= ~3L;
901                         }
902                 }
903         }
904 
905         /* these DMA buffer size will be used */
906         devpriv->dma_actbuf = 0;
907         dmabuf0->use_size = dmalen0;
908         dmabuf1->use_size = dmalen1;
909 
910         pci9118_amcc_dma_ena(dev, false);
911         pci9118_amcc_setup_dma(dev, 0);
912         /* init DMA transfer */
913         outl(0x00000000 | AINT_WRITE_COMPL,
914              devpriv->iobase_a + AMCC_OP_REG_INTCSR);
915 /* outl(0x02000000|AINT_WRITE_COMPL, devpriv->iobase_a+AMCC_OP_REG_INTCSR); */
916         pci9118_amcc_dma_ena(dev, true);
917         outl(inl(devpriv->iobase_a + AMCC_OP_REG_INTCSR) | EN_A2P_TRANSFERS,
918                         devpriv->iobase_a + AMCC_OP_REG_INTCSR);
919                                                 /* allow bus mastering */
920 
921         return 0;
922 }
923 
924 static int pci9118_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
925 {
926         struct pci9118_private *devpriv = dev->private;
927         struct comedi_cmd *cmd = &s->async->cmd;
928         unsigned int addchans = 0;
929 
930         devpriv->ai12_startstop = 0;
931         devpriv->ai_flags = cmd->flags;
932         devpriv->ai_add_front = 0;
933         devpriv->ai_add_back = 0;
934 
935         /* prepare for start/stop conditions */
936         if (cmd->start_src == TRIG_EXT)
937                 devpriv->ai12_startstop |= START_AI_EXT;
938         if (cmd->stop_src == TRIG_EXT) {
939                 devpriv->ai_neverending = 1;
940                 devpriv->ai12_startstop |= STOP_AI_EXT;
941         }
942         if (cmd->stop_src == TRIG_NONE)
943                 devpriv->ai_neverending = 1;
944         if (cmd->stop_src == TRIG_COUNT)
945                 devpriv->ai_neverending = 0;
946 
947         /*
948          * use additional sample at end of every scan
949          * to satisty DMA 32 bit transfer?
950          */
951         devpriv->ai_add_front = 0;
952         devpriv->ai_add_back = 0;
953         if (devpriv->master) {
954                 devpriv->usedma = 1;
955                 if ((cmd->flags & CMDF_WAKE_EOS) &&
956                     (cmd->scan_end_arg == 1)) {
957                         if (cmd->convert_src == TRIG_NOW)
958                                 devpriv->ai_add_back = 1;
959                         if (cmd->convert_src == TRIG_TIMER) {
960                                 devpriv->usedma = 0;
961                                         /*
962                                          * use INT transfer if scanlist
963                                          * have only one channel
964                                          */
965                         }
966                 }
967                 if ((cmd->flags & CMDF_WAKE_EOS) &&
968                     (cmd->scan_end_arg & 1) &&
969                     (cmd->scan_end_arg > 1)) {
970                         if (cmd->scan_begin_src == TRIG_FOLLOW) {
971                                 devpriv->usedma = 0;
972                                 /*
973                                  * XXX maybe can be corrected to use 16 bit DMA
974                                  */
975                         } else {        /*
976                                          * well, we must insert one sample
977                                          * to end of EOS to meet 32 bit transfer
978                                          */
979                                 devpriv->ai_add_back = 1;
980                         }
981                 }
982         } else {        /* interrupt transfer don't need any correction */
983                 devpriv->usedma = 0;
984         }
985 
986         /*
987          * we need software S&H signal?
988          * It adds two samples before every scan as minimum
989          */
990         if (cmd->convert_src == TRIG_NOW && devpriv->softsshdelay) {
991                 devpriv->ai_add_front = 2;
992                 if ((devpriv->usedma == 1) && (devpriv->ai_add_back == 1)) {
993                                                         /* move it to front */
994                         devpriv->ai_add_front++;
995                         devpriv->ai_add_back = 0;
996                 }
997                 if (cmd->convert_arg < devpriv->ai_ns_min)
998                         cmd->convert_arg = devpriv->ai_ns_min;
999                 addchans = devpriv->softsshdelay / cmd->convert_arg;
1000                 if (devpriv->softsshdelay % cmd->convert_arg)
1001                         addchans++;
1002                 if (addchans > (devpriv->ai_add_front - 1)) {
1003                                                         /* uff, still short */
1004                         devpriv->ai_add_front = addchans + 1;
1005                         if (devpriv->usedma == 1)
1006                                 if ((devpriv->ai_add_front +
1007                                      cmd->chanlist_len +
1008                                      devpriv->ai_add_back) & 1)
1009                                         devpriv->ai_add_front++;
1010                                                         /* round up to 32 bit */
1011                 }
1012         }
1013         /* well, we now know what must be all added */
1014         devpriv->ai_n_realscanlen =     /*
1015                                          * what we must take from card in real
1016                                          * to have cmd->scan_end_arg on output?
1017                                          */
1018             (devpriv->ai_add_front + cmd->chanlist_len +
1019              devpriv->ai_add_back) * (cmd->scan_end_arg /
1020                                       cmd->chanlist_len);
1021 
1022         /* check and setup channel list */
1023         if (!check_channel_list(dev, s, cmd->chanlist_len,
1024                                 cmd->chanlist, devpriv->ai_add_front,
1025                                 devpriv->ai_add_back))
1026                 return -EINVAL;
1027 
1028         /*
1029          * Configure analog input and load the chanlist.
1030          * The acqusition control bits are enabled later.
1031          */
1032         pci9118_set_chanlist(dev, s, cmd->chanlist_len, cmd->chanlist,
1033                              devpriv->ai_add_front, devpriv->ai_add_back);
1034 
1035         /* Determine acqusition mode and calculate timing */
1036         devpriv->ai_do = 0;
1037         if (cmd->scan_begin_src != TRIG_TIMER &&
1038             cmd->convert_src == TRIG_TIMER) {
1039                 /* cascaded timers 1 and 2 are used for convert timing */
1040                 if (cmd->scan_begin_src == TRIG_EXT)
1041                         devpriv->ai_do = 4;
1042                 else
1043                         devpriv->ai_do = 1;
1044 
1045                 i8253_cascade_ns_to_timer(I8254_OSC_BASE_4MHZ,
1046                                           &devpriv->ai_divisor1,
1047                                           &devpriv->ai_divisor2,
1048                                           &cmd->convert_arg,
1049                                           devpriv->ai_flags &
1050                                           CMDF_ROUND_NEAREST);
1051 
1052                 devpriv->ai_ctrl |= PCI9118_AI_CTRL_TMRTR;
1053 
1054                 if (!devpriv->usedma) {
1055                         devpriv->ai_ctrl |= PCI9118_AI_CTRL_INT;
1056                         devpriv->int_ctrl |= PCI9118_INT_CTRL_TIMER;
1057                 }
1058 
1059                 if (cmd->scan_begin_src == TRIG_EXT) {
1060                         struct pci9118_dmabuf *dmabuf = &devpriv->dmabuf[0];
1061 
1062                         devpriv->ai_cfg |= PCI9118_AI_CFG_AM;
1063                         outl(devpriv->ai_cfg, dev->iobase + PCI9118_AI_CFG_REG);
1064                         pci9118_timer_set_mode(dev, 0, I8254_MODE0);
1065                         pci9118_timer_write(dev, 0, dmabuf->hw >> 1);
1066                         devpriv->ai_cfg |= PCI9118_AI_CFG_START;
1067                 }
1068         }
1069 
1070         if (cmd->scan_begin_src == TRIG_TIMER &&
1071             cmd->convert_src != TRIG_EXT) {
1072                 if (!devpriv->usedma) {
1073                         dev_err(dev->class_dev,
1074                                 "cmd->scan_begin_src=TRIG_TIMER works only with bus mastering!\n");
1075                         return -EIO;
1076                 }
1077 
1078                 /* double timed action */
1079                 devpriv->ai_do = 2;
1080 
1081                 pci9118_calc_divisors(dev, s,
1082                                       &cmd->scan_begin_arg, &cmd->convert_arg,
1083                                       devpriv->ai_flags,
1084                                       devpriv->ai_n_realscanlen,
1085                                       &devpriv->ai_divisor1,
1086                                       &devpriv->ai_divisor2,
1087                                       devpriv->ai_add_front);
1088 
1089                 devpriv->ai_ctrl |= PCI9118_AI_CTRL_TMRTR;
1090                 devpriv->ai_cfg |= PCI9118_AI_CFG_BM | PCI9118_AI_CFG_BS;
1091                 if (cmd->convert_src == TRIG_NOW && !devpriv->softsshdelay)
1092                         devpriv->ai_cfg |= PCI9118_AI_CFG_BSSH;
1093                 outl(devpriv->ai_n_realscanlen,
1094                      dev->iobase + PCI9118_AI_BURST_NUM_REG);
1095         }
1096 
1097         if (cmd->scan_begin_src == TRIG_FOLLOW &&
1098             cmd->convert_src == TRIG_EXT) {
1099                 /* external trigger conversion */
1100                 devpriv->ai_do = 3;
1101 
1102                 devpriv->ai_ctrl |= PCI9118_AI_CTRL_EXTM;
1103         }
1104 
1105         if (devpriv->ai_do == 0) {
1106                 dev_err(dev->class_dev,
1107                         "Unable to determine acqusition mode! BUG in (*do_cmdtest)?\n");
1108                 return -EINVAL;
1109         }
1110 
1111         if (devpriv->usedma)
1112                 devpriv->ai_ctrl |= PCI9118_AI_CTRL_DMA;
1113 
1114         pci9118_start_pacer(dev, -1);   /* stop pacer */
1115 
1116         /* set default config (disable burst and triggers) */
1117         devpriv->ai_cfg = PCI9118_AI_CFG_PDTRG | PCI9118_AI_CFG_PETRG;
1118         outl(devpriv->ai_cfg, dev->iobase + PCI9118_AI_CFG_REG);
1119         udelay(1);
1120         pci9118_ai_reset_fifo(dev);
1121 
1122         /* clear A/D and INT status registers */
1123         inl(dev->iobase + PCI9118_AI_STATUS_REG);
1124         inl(dev->iobase + PCI9118_INT_CTRL_REG);
1125 
1126         devpriv->ai_act_scan = 0;
1127         devpriv->ai_act_dmapos = 0;
1128         s->async->cur_chan = 0;
1129 
1130         if (devpriv->usedma) {
1131                 Compute_and_setup_dma(dev, s);
1132 
1133                 outl(0x02000000 | AINT_WRITE_COMPL,
1134                      devpriv->iobase_a + AMCC_OP_REG_INTCSR);
1135         } else {
1136                 pci9118_amcc_int_ena(dev, true);
1137         }
1138 
1139         /* start async command now or wait for internal trigger */
1140         if (cmd->start_src == TRIG_NOW)
1141                 pci9118_ai_cmd_start(dev);
1142         else if (cmd->start_src == TRIG_INT)
1143                 s->async->inttrig = pci9118_ai_inttrig;
1144 
1145         /* enable external trigger for command start/stop */
1146         if (cmd->start_src == TRIG_EXT || cmd->stop_src == TRIG_EXT)
1147                 pci9118_exttrg_enable(dev, true);
1148 
1149         return 0;
1150 }
1151 
1152 static int pci9118_ai_cmdtest(struct comedi_device *dev,
1153                               struct comedi_subdevice *s,
1154                               struct comedi_cmd *cmd)
1155 {
1156         struct pci9118_private *devpriv = dev->private;
1157         int err = 0;
1158         unsigned int flags;
1159         unsigned int arg;
1160         unsigned int divisor1 = 0, divisor2 = 0;
1161 
1162         /* Step 1 : check if triggers are trivially valid */
1163 
1164         err |= cfc_check_trigger_src(&cmd->start_src,
1165                                         TRIG_NOW | TRIG_EXT | TRIG_INT);
1166 
1167         flags = TRIG_FOLLOW;
1168         if (devpriv->master)
1169                 flags |= TRIG_TIMER | TRIG_EXT;
1170         err |= cfc_check_trigger_src(&cmd->scan_begin_src, flags);
1171 
1172         flags = TRIG_TIMER | TRIG_EXT;
1173         if (devpriv->master)
1174                 flags |= TRIG_NOW;
1175         err |= cfc_check_trigger_src(&cmd->convert_src, flags);
1176 
1177         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
1178         err |= cfc_check_trigger_src(&cmd->stop_src,
1179                                         TRIG_COUNT | TRIG_NONE | TRIG_EXT);
1180 
1181         if (err)
1182                 return 1;
1183 
1184         /* Step 2a : make sure trigger sources are unique */
1185 
1186         err |= cfc_check_trigger_is_unique(cmd->start_src);
1187         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
1188         err |= cfc_check_trigger_is_unique(cmd->convert_src);
1189         err |= cfc_check_trigger_is_unique(cmd->stop_src);
1190 
1191         /* Step 2b : and mutually compatible */
1192 
1193         if (cmd->start_src == TRIG_EXT && cmd->scan_begin_src == TRIG_EXT)
1194                 err |= -EINVAL;
1195 
1196         if (cmd->start_src == TRIG_INT && cmd->scan_begin_src == TRIG_INT)
1197                 err |= -EINVAL;
1198 
1199         if ((cmd->scan_begin_src & (TRIG_TIMER | TRIG_EXT)) &&
1200             (!(cmd->convert_src & (TRIG_TIMER | TRIG_NOW))))
1201                 err |= -EINVAL;
1202 
1203         if ((cmd->scan_begin_src == TRIG_FOLLOW) &&
1204             (!(cmd->convert_src & (TRIG_TIMER | TRIG_EXT))))
1205                 err |= -EINVAL;
1206 
1207         if (cmd->stop_src == TRIG_EXT && cmd->scan_begin_src == TRIG_EXT)
1208                 err |= -EINVAL;
1209 
1210         if (err)
1211                 return 2;
1212 
1213         /* Step 3: check if arguments are trivially valid */
1214 
1215         switch (cmd->start_src) {
1216         case TRIG_NOW:
1217         case TRIG_EXT:
1218                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
1219                 break;
1220         case TRIG_INT:
1221                 /* start_arg is the internal trigger (any value) */
1222                 break;
1223         }
1224 
1225         if (cmd->scan_begin_src & (TRIG_FOLLOW | TRIG_EXT))
1226                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
1227 
1228         if ((cmd->scan_begin_src == TRIG_TIMER) &&
1229             (cmd->convert_src == TRIG_TIMER) && (cmd->scan_end_arg == 1)) {
1230                 cmd->scan_begin_src = TRIG_FOLLOW;
1231                 cmd->convert_arg = cmd->scan_begin_arg;
1232                 cmd->scan_begin_arg = 0;
1233         }
1234 
1235         if (cmd->scan_begin_src == TRIG_TIMER)
1236                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
1237                                                  devpriv->ai_ns_min);
1238 
1239         if (cmd->scan_begin_src == TRIG_EXT)
1240                 if (cmd->scan_begin_arg) {
1241                         cmd->scan_begin_arg = 0;
1242                         err |= -EINVAL;
1243                         err |= cfc_check_trigger_arg_max(&cmd->scan_end_arg,
1244                                                          65535);
1245                 }
1246 
1247         if (cmd->convert_src & (TRIG_TIMER | TRIG_NOW))
1248                 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
1249                                                  devpriv->ai_ns_min);
1250 
1251         if (cmd->convert_src == TRIG_EXT)
1252                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
1253 
1254         if (cmd->stop_src == TRIG_COUNT)
1255                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
1256         else    /* TRIG_NONE */
1257                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
1258 
1259         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
1260 
1261         err |= cfc_check_trigger_arg_min(&cmd->scan_end_arg,
1262                                          cmd->chanlist_len);
1263 
1264         if ((cmd->scan_end_arg % cmd->chanlist_len)) {
1265                 cmd->scan_end_arg =
1266                     cmd->chanlist_len * (cmd->scan_end_arg / cmd->chanlist_len);
1267                 err |= -EINVAL;
1268         }
1269 
1270         if (err)
1271                 return 3;
1272 
1273         /* step 4: fix up any arguments */
1274 
1275         if (cmd->scan_begin_src == TRIG_TIMER) {
1276                 arg = cmd->scan_begin_arg;
1277                 i8253_cascade_ns_to_timer(I8254_OSC_BASE_4MHZ,
1278                                           &divisor1, &divisor2,
1279                                           &arg, cmd->flags);
1280                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
1281         }
1282 
1283         if (cmd->convert_src & (TRIG_TIMER | TRIG_NOW)) {
1284                 arg = cmd->convert_arg;
1285                 i8253_cascade_ns_to_timer(I8254_OSC_BASE_4MHZ,
1286                                           &divisor1, &divisor2,
1287                                           &arg, cmd->flags);
1288                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, arg);
1289 
1290                 if (cmd->scan_begin_src == TRIG_TIMER &&
1291                     cmd->convert_src == TRIG_NOW) {
1292                         if (cmd->convert_arg == 0) {
1293                                 arg = devpriv->ai_ns_min *
1294                                       (cmd->scan_end_arg + 2);
1295                         } else {
1296                                 arg = cmd->convert_arg * cmd->chanlist_len;
1297                         }
1298                         err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
1299                                                          arg);
1300                 }
1301         }
1302 
1303         if (err)
1304                 return 4;
1305 
1306         if (cmd->chanlist)
1307                 if (!check_channel_list(dev, s, cmd->chanlist_len,
1308                                         cmd->chanlist, 0, 0))
1309                         return 5;       /* incorrect channels list */
1310 
1311         return 0;
1312 }
1313 
1314 static int pci9118_ai_eoc(struct comedi_device *dev,
1315                           struct comedi_subdevice *s,
1316                           struct comedi_insn *insn,
1317                           unsigned long context)
1318 {
1319         unsigned int status;
1320 
1321         status = inl(dev->iobase + PCI9118_AI_STATUS_REG);
1322         if (status & PCI9118_AI_STATUS_ADRDY)
1323                 return 0;
1324         return -EBUSY;
1325 }
1326 
1327 static void pci9118_ai_start_conv(struct comedi_device *dev)
1328 {
1329         /* writing any value triggers an A/D conversion */
1330         outl(0, dev->iobase + PCI9118_SOFTTRG_REG);
1331 }
1332 
1333 static int pci9118_ai_insn_read(struct comedi_device *dev,
1334                                 struct comedi_subdevice *s,
1335                                 struct comedi_insn *insn,
1336                                 unsigned int *data)
1337 {
1338         struct pci9118_private *devpriv = dev->private;
1339         unsigned int val;
1340         int ret;
1341         int i;
1342 
1343        /*
1344         * Configure analog input based on the chanspec.
1345         * Acqusition is software controlled without interrupts.
1346         */
1347         pci9118_set_chanlist(dev, s, 1, &insn->chanspec, 0, 0);
1348 
1349         /* set default config (disable burst and triggers) */
1350         devpriv->ai_cfg = PCI9118_AI_CFG_PDTRG | PCI9118_AI_CFG_PETRG;
1351         outl(devpriv->ai_cfg, dev->iobase + PCI9118_AI_CFG_REG);
1352 
1353         pci9118_ai_reset_fifo(dev);
1354 
1355         for (i = 0; i < insn->n; i++) {
1356                 pci9118_ai_start_conv(dev);
1357 
1358                 ret = comedi_timeout(dev, s, insn, pci9118_ai_eoc, 0);
1359                 if (ret)
1360                         return ret;
1361 
1362                 val = inl(dev->iobase + PCI9118_AI_FIFO_REG);
1363                 if (s->maxdata == 0xffff)
1364                         data[i] = (val & 0xffff) ^ 0x8000;
1365                 else
1366                         data[i] = (val >> 4) & 0xfff;
1367         }
1368 
1369         return insn->n;
1370 }
1371 
1372 static int pci9118_ao_insn_write(struct comedi_device *dev,
1373                                  struct comedi_subdevice *s,
1374                                  struct comedi_insn *insn,
1375                                  unsigned int *data)
1376 {
1377         unsigned int chan = CR_CHAN(insn->chanspec);
1378         unsigned int val = s->readback[chan];
1379         int i;
1380 
1381         for (i = 0; i < insn->n; i++) {
1382                 val = data[i];
1383                 outl(val, dev->iobase + PCI9118_AO_REG(chan));
1384         }
1385         s->readback[chan] = val;
1386 
1387         return insn->n;
1388 }
1389 
1390 static int pci9118_di_insn_bits(struct comedi_device *dev,
1391                                 struct comedi_subdevice *s,
1392                                 struct comedi_insn *insn,
1393                                 unsigned int *data)
1394 {
1395         /*
1396          * The digital inputs and outputs share the read register.
1397          * bits [7:4] are the digital outputs
1398          * bits [3:0] are the digital inputs
1399          */
1400         data[1] = inl(dev->iobase + PCI9118_DIO_REG) & 0xf;
1401 
1402         return insn->n;
1403 }
1404 
1405 static int pci9118_do_insn_bits(struct comedi_device *dev,
1406                                 struct comedi_subdevice *s,
1407                                 struct comedi_insn *insn,
1408                                 unsigned int *data)
1409 {
1410         /*
1411          * The digital outputs are set with the same register that
1412          * the digital inputs and outputs are read from. But the
1413          * outputs are set with bits [3:0] so we can simply write
1414          * the s->state to set them.
1415          */
1416         if (comedi_dio_update_state(s, data))
1417                 outl(s->state, dev->iobase + PCI9118_DIO_REG);
1418 
1419         data[1] = s->state;
1420 
1421         return insn->n;
1422 }
1423 
1424 static void pci9118_reset(struct comedi_device *dev)
1425 {
1426         /* reset analog input subsystem */
1427         outl(0, dev->iobase + PCI9118_INT_CTRL_REG);
1428         outl(0, dev->iobase + PCI9118_AI_CTRL_REG);
1429         outl(0, dev->iobase + PCI9118_AI_CFG_REG);
1430         pci9118_ai_reset_fifo(dev);
1431 
1432         /* clear any pending interrupts and status */
1433         inl(dev->iobase + PCI9118_INT_CTRL_REG);
1434         inl(dev->iobase + PCI9118_AI_STATUS_REG);
1435 
1436         /* reset and stop counters */
1437         pci9118_timer_set_mode(dev, 0, I8254_MODE0);
1438         pci9118_start_pacer(dev, 0);
1439 
1440         /* reset DMA and scan queue */
1441         outl(0, dev->iobase + PCI9118_AI_BURST_NUM_REG);
1442         outl(1, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
1443         outl(2, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
1444 
1445         /* reset analog outputs to 0V */
1446         outl(2047, dev->iobase + PCI9118_AO_REG(0));
1447         outl(2047, dev->iobase + PCI9118_AO_REG(1));
1448 }
1449 
1450 static struct pci_dev *pci9118_find_pci(struct comedi_device *dev,
1451                                         struct comedi_devconfig *it)
1452 {
1453         struct pci_dev *pcidev = NULL;
1454         int bus = it->options[0];
1455         int slot = it->options[1];
1456 
1457         for_each_pci_dev(pcidev) {
1458                 if (pcidev->vendor != PCI_VENDOR_ID_AMCC)
1459                         continue;
1460                 if (pcidev->device != 0x80d9)
1461                         continue;
1462                 if (bus || slot) {
1463                         /* requested particular bus/slot */
1464                         if (pcidev->bus->number != bus ||
1465                             PCI_SLOT(pcidev->devfn) != slot)
1466                                 continue;
1467                 }
1468                 return pcidev;
1469         }
1470         dev_err(dev->class_dev,
1471                 "no supported board found! (req. bus/slot : %d/%d)\n",
1472                 bus, slot);
1473         return NULL;
1474 }
1475 
1476 static void pci9118_alloc_dma(struct comedi_device *dev)
1477 {
1478         struct pci9118_private *devpriv = dev->private;
1479         struct pci9118_dmabuf *dmabuf;
1480         int order;
1481         int i;
1482 
1483         for (i = 0; i < 2; i++) {
1484                 dmabuf = &devpriv->dmabuf[i];
1485                 for (order = 2; order >= 0; order--) {
1486                         dmabuf->virt =
1487                             dma_alloc_coherent(dev->hw_dev, PAGE_SIZE << order,
1488                                                &dmabuf->hw, GFP_KERNEL);
1489                         if (dmabuf->virt)
1490                                 break;
1491                 }
1492                 if (!dmabuf->virt)
1493                         break;
1494                 dmabuf->size = PAGE_SIZE << order;
1495 
1496                 if (i == 0)
1497                         devpriv->master = 1;
1498                 if (i == 1)
1499                         devpriv->dma_doublebuf = 1;
1500         }
1501 }
1502 
1503 static void pci9118_free_dma(struct comedi_device *dev)
1504 {
1505         struct pci9118_private *devpriv = dev->private;
1506         struct pci9118_dmabuf *dmabuf;
1507         int i;
1508 
1509         if (!devpriv)
1510                 return;
1511 
1512         for (i = 0; i < 2; i++) {
1513                 dmabuf = &devpriv->dmabuf[i];
1514                 if (dmabuf->virt) {
1515                         dma_free_coherent(dev->hw_dev, dmabuf->size,
1516                                           dmabuf->virt, dmabuf->hw);
1517                 }
1518         }
1519 }
1520 
1521 static int pci9118_common_attach(struct comedi_device *dev,
1522                                  int ext_mux, int softsshdelay)
1523 {
1524         const struct pci9118_boardinfo *board = dev->board_ptr;
1525         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1526         struct pci9118_private *devpriv;
1527         struct comedi_subdevice *s;
1528         int ret;
1529         int i;
1530         u16 u16w;
1531 
1532         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
1533         if (!devpriv)
1534                 return -ENOMEM;
1535 
1536         ret = comedi_pci_enable(dev);
1537         if (ret)
1538                 return ret;
1539         pci_set_master(pcidev);
1540 
1541         devpriv->iobase_a = pci_resource_start(pcidev, 0);
1542         dev->iobase = pci_resource_start(pcidev, 2);
1543 
1544         pci9118_reset(dev);
1545 
1546         if (pcidev->irq) {
1547                 ret = request_irq(pcidev->irq, pci9118_interrupt, IRQF_SHARED,
1548                                   dev->board_name, dev);
1549                 if (ret == 0) {
1550                         dev->irq = pcidev->irq;
1551 
1552                         pci9118_alloc_dma(dev);
1553                 }
1554         }
1555 
1556         if (ext_mux > 0) {
1557                 if (ext_mux > 256)
1558                         ext_mux = 256;  /* max 256 channels! */
1559                 if (softsshdelay > 0)
1560                         if (ext_mux > 128)
1561                                 ext_mux = 128;
1562                 devpriv->usemux = 1;
1563         } else {
1564                 devpriv->usemux = 0;
1565         }
1566 
1567         if (softsshdelay < 0) {
1568                 /* select sample&hold signal polarity */
1569                 devpriv->softsshdelay = -softsshdelay;
1570                 devpriv->softsshsample = 0x80;
1571                 devpriv->softsshhold = 0x00;
1572         } else {
1573                 devpriv->softsshdelay = softsshdelay;
1574                 devpriv->softsshsample = 0x00;
1575                 devpriv->softsshhold = 0x80;
1576         }
1577 
1578         pci_read_config_word(pcidev, PCI_COMMAND, &u16w);
1579         pci_write_config_word(pcidev, PCI_COMMAND, u16w | 64);
1580                                 /* Enable parity check for parity error */
1581 
1582         ret = comedi_alloc_subdevices(dev, 4);
1583         if (ret)
1584                 return ret;
1585 
1586         /* Analog Input subdevice */
1587         s = &dev->subdevices[0];
1588         s->type         = COMEDI_SUBD_AI;
1589         s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_GROUND | SDF_DIFF;
1590         s->n_chan       = (devpriv->usemux) ? ext_mux : 16;
1591         s->maxdata      = board->ai_is_16bit ? 0xffff : 0x0fff;
1592         s->range_table  = board->is_hg ? &pci9118hg_ai_range
1593                                        : &pci9118_ai_range;
1594         s->insn_read    = pci9118_ai_insn_read;
1595         if (dev->irq) {
1596                 dev->read_subdev = s;
1597                 s->subdev_flags |= SDF_CMD_READ;
1598                 s->len_chanlist = PCI9118_CHANLEN;
1599                 s->do_cmdtest   = pci9118_ai_cmdtest;
1600                 s->do_cmd       = pci9118_ai_cmd;
1601                 s->cancel       = pci9118_ai_cancel;
1602                 s->munge        = pci9118_ai_munge;
1603         }
1604 
1605         if (s->maxdata == 0xffff) {
1606                 /*
1607                  * 16-bit samples are from an ADS7805 A/D converter.
1608                  * Minimum sampling rate is 10us.
1609                  */
1610                 devpriv->ai_ns_min = 10000;
1611         } else {
1612                 /*
1613                  * 12-bit samples are from an ADS7800 A/D converter.
1614                  * Minimum sampling rate is 3us.
1615                  */
1616                 devpriv->ai_ns_min = 3000;
1617         }
1618 
1619         /* Analog Output subdevice */
1620         s = &dev->subdevices[1];
1621         s->type         = COMEDI_SUBD_AO;
1622         s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
1623         s->n_chan       = 2;
1624         s->maxdata      = 0x0fff;
1625         s->range_table  = &range_bipolar10;
1626         s->insn_write   = pci9118_ao_insn_write;
1627         s->insn_read    = comedi_readback_insn_read;
1628 
1629         ret = comedi_alloc_subdev_readback(s);
1630         if (ret)
1631                 return ret;
1632 
1633         /* the analog outputs were reset to 0V, make the readback match */
1634         for (i = 0; i < s->n_chan; i++)
1635                 s->readback[i] = 2047;
1636 
1637         /* Digital Input subdevice */
1638         s = &dev->subdevices[2];
1639         s->type         = COMEDI_SUBD_DI;
1640         s->subdev_flags = SDF_READABLE;
1641         s->n_chan       = 4;
1642         s->maxdata      = 1;
1643         s->range_table  = &range_digital;
1644         s->insn_bits    = pci9118_di_insn_bits;
1645 
1646         /* Digital Output subdevice */
1647         s = &dev->subdevices[3];
1648         s->type         = COMEDI_SUBD_DO;
1649         s->subdev_flags = SDF_WRITABLE;
1650         s->n_chan       = 4;
1651         s->maxdata      = 1;
1652         s->range_table  = &range_digital;
1653         s->insn_bits    = pci9118_do_insn_bits;
1654 
1655         /* get the current state of the digital outputs */
1656         s->state = inl(dev->iobase + PCI9118_DIO_REG) >> 4;
1657 
1658         return 0;
1659 }
1660 
1661 static int pci9118_attach(struct comedi_device *dev,
1662                           struct comedi_devconfig *it)
1663 {
1664         struct pci_dev *pcidev;
1665         int ext_mux, softsshdelay;
1666 
1667         ext_mux = it->options[2];
1668         softsshdelay = it->options[4];
1669 
1670         pcidev = pci9118_find_pci(dev, it);
1671         if (!pcidev)
1672                 return -EIO;
1673         comedi_set_hw_dev(dev, &pcidev->dev);
1674 
1675         return pci9118_common_attach(dev, ext_mux, softsshdelay);
1676 }
1677 
1678 static int pci9118_auto_attach(struct comedi_device *dev,
1679                                unsigned long context)
1680 {
1681         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1682         const struct pci9118_boardinfo *board = NULL;
1683 
1684         if (context < ARRAY_SIZE(pci9118_boards))
1685                 board = &pci9118_boards[context];
1686         if (!board)
1687                 return -ENODEV;
1688         dev->board_ptr = board;
1689         dev->board_name = board->name;
1690 
1691         /*
1692          * Need to 'get' the PCI device to match the 'put' in pci9118_detach().
1693          * (The 'put' also matches the implicit 'get' by pci9118_find_pci().)
1694          */
1695         pci_dev_get(pcidev);
1696         /* no external mux, no sample-hold delay */
1697         return pci9118_common_attach(dev, 0, 0);
1698 }
1699 
1700 static void pci9118_detach(struct comedi_device *dev)
1701 {
1702         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1703 
1704         if (dev->iobase)
1705                 pci9118_reset(dev);
1706         comedi_pci_detach(dev);
1707         pci9118_free_dma(dev);
1708         if (pcidev)
1709                 pci_dev_put(pcidev);
1710 }
1711 
1712 static struct comedi_driver adl_pci9118_driver = {
1713         .driver_name    = "adl_pci9118",
1714         .module         = THIS_MODULE,
1715         .attach         = pci9118_attach,
1716         .auto_attach    = pci9118_auto_attach,
1717         .detach         = pci9118_detach,
1718         .num_names      = ARRAY_SIZE(pci9118_boards),
1719         .board_name     = &pci9118_boards[0].name,
1720         .offset         = sizeof(struct pci9118_boardinfo),
1721 };
1722 
1723 static int adl_pci9118_pci_probe(struct pci_dev *dev,
1724                                  const struct pci_device_id *id)
1725 {
1726         return comedi_pci_auto_config(dev, &adl_pci9118_driver,
1727                                       id->driver_data);
1728 }
1729 
1730 /* FIXME: All the supported board types have the same device ID! */
1731 static const struct pci_device_id adl_pci9118_pci_table[] = {
1732         { PCI_VDEVICE(AMCC, 0x80d9), BOARD_PCI9118DG },
1733 /*      { PCI_VDEVICE(AMCC, 0x80d9), BOARD_PCI9118HG }, */
1734 /*      { PCI_VDEVICE(AMCC, 0x80d9), BOARD_PCI9118HR }, */
1735         { 0 }
1736 };
1737 MODULE_DEVICE_TABLE(pci, adl_pci9118_pci_table);
1738 
1739 static struct pci_driver adl_pci9118_pci_driver = {
1740         .name           = "adl_pci9118",
1741         .id_table       = adl_pci9118_pci_table,
1742         .probe          = adl_pci9118_pci_probe,
1743         .remove         = comedi_pci_auto_unconfig,
1744 };
1745 module_comedi_pci_driver(adl_pci9118_driver, adl_pci9118_pci_driver);
1746 
1747 MODULE_AUTHOR("Comedi http://www.comedi.org");
1748 MODULE_DESCRIPTION("Comedi low-level driver");
1749 MODULE_LICENSE("GPL");
1750 

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