Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/staging/comedi/drivers/addi_apci_1500.c

  1 /*
  2  * addi_apci_1500.c
  3  * Copyright (C) 2004,2005  ADDI-DATA GmbH for the source code of this module.
  4  *
  5  *      ADDI-DATA GmbH
  6  *      Dieselstrasse 3
  7  *      D-77833 Ottersweier
  8  *      Tel: +19(0)7223/9493-0
  9  *      Fax: +49(0)7223/9493-92
 10  *      http://www.addi-data.com
 11  *      info@addi-data.com
 12  *
 13  * This program is free software; you can redistribute it and/or modify it
 14  * under the terms of the GNU General Public License as published by the
 15  * Free Software Foundation; either version 2 of the License, or (at your
 16  * option) any later version.
 17  *
 18  * This program is distributed in the hope that it will be useful, but WITHOUT
 19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 20  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 21  * more details.
 22  */
 23 
 24 #include <linux/module.h>
 25 #include <linux/pci.h>
 26 #include <linux/interrupt.h>
 27 
 28 #include "../comedidev.h"
 29 #include "comedi_fc.h"
 30 #include "amcc_s5933.h"
 31 #include "z8536.h"
 32 
 33 /*
 34  * PCI Bar 0 Register map (devpriv->amcc)
 35  * see amcc_s5933.h for register and bit defines
 36  */
 37 
 38 /*
 39  * PCI Bar 1 Register map (dev->iobase)
 40  * see z8536.h for Z8536 internal registers and bit defines
 41  */
 42 #define APCI1500_Z8536_PORTC_REG        0x00
 43 #define APCI1500_Z8536_PORTB_REG        0x01
 44 #define APCI1500_Z8536_PORTA_REG        0x02
 45 #define APCI1500_Z8536_CTRL_REG         0x03
 46 
 47 /*
 48  * PCI Bar 2 Register map (devpriv->addon)
 49  */
 50 #define APCI1500_CLK_SEL_REG            0x00
 51 #define APCI1500_DI_REG                 0x00
 52 #define APCI1500_DO_REG                 0x02
 53 
 54 struct apci1500_private {
 55         unsigned long amcc;
 56         unsigned long addon;
 57 
 58         unsigned int clk_src;
 59 
 60         /* Digital trigger configuration [0]=AND [1]=OR */
 61         unsigned int pm[2];     /* Pattern Mask */
 62         unsigned int pt[2];     /* Pattern Transition */
 63         unsigned int pp[2];     /* Pattern Polarity */
 64 };
 65 
 66 static unsigned int z8536_read(struct comedi_device *dev, unsigned int reg)
 67 {
 68         unsigned long flags;
 69         unsigned int val;
 70 
 71         spin_lock_irqsave(&dev->spinlock, flags);
 72         outb(reg, dev->iobase + APCI1500_Z8536_CTRL_REG);
 73         val = inb(dev->iobase + APCI1500_Z8536_CTRL_REG);
 74         spin_unlock_irqrestore(&dev->spinlock, flags);
 75 
 76         return val;
 77 }
 78 
 79 static void z8536_write(struct comedi_device *dev,
 80                         unsigned int val, unsigned int reg)
 81 {
 82         unsigned long flags;
 83 
 84         spin_lock_irqsave(&dev->spinlock, flags);
 85         outb(reg, dev->iobase + APCI1500_Z8536_CTRL_REG);
 86         outb(val, dev->iobase + APCI1500_Z8536_CTRL_REG);
 87         spin_unlock_irqrestore(&dev->spinlock, flags);
 88 }
 89 
 90 static void z8536_reset(struct comedi_device *dev)
 91 {
 92         unsigned long flags;
 93 
 94         /*
 95          * Even if the state of the Z8536 is not known, the following
 96          * sequence will reset it and put it in State 0.
 97          */
 98         spin_lock_irqsave(&dev->spinlock, flags);
 99         inb(dev->iobase + APCI1500_Z8536_CTRL_REG);
100         outb(0, dev->iobase + APCI1500_Z8536_CTRL_REG);
101         inb(dev->iobase + APCI1500_Z8536_CTRL_REG);
102         outb(0, dev->iobase + APCI1500_Z8536_CTRL_REG);
103         outb(1, dev->iobase + APCI1500_Z8536_CTRL_REG);
104         outb(0, dev->iobase + APCI1500_Z8536_CTRL_REG);
105         spin_unlock_irqrestore(&dev->spinlock, flags);
106 
107         /* Disable all Ports and Counter/Timers */
108         z8536_write(dev, 0x00, Z8536_CFG_CTRL_REG);
109 
110         /*
111          * Port A is connected to Ditial Input channels 0-7.
112          * Configure the port to allow interrupt detection.
113          */
114         z8536_write(dev, Z8536_PAB_MODE_PTS_BIT |
115                          Z8536_PAB_MODE_SB |
116                          Z8536_PAB_MODE_PMS_DISABLE,
117                     Z8536_PA_MODE_REG);
118         z8536_write(dev, 0xff, Z8536_PB_DPP_REG);
119         z8536_write(dev, 0xff, Z8536_PA_DD_REG);
120 
121         /*
122          * Port B is connected to Ditial Input channels 8-13.
123          * Configure the port to allow interrupt detection.
124          *
125          * NOTE: Bits 7 and 6 of Port B are connected to internal
126          * diagnostic signals and bit 7 is inverted.
127          */
128         z8536_write(dev, Z8536_PAB_MODE_PTS_BIT |
129                          Z8536_PAB_MODE_SB |
130                          Z8536_PAB_MODE_PMS_DISABLE,
131                     Z8536_PB_MODE_REG);
132         z8536_write(dev, 0x7f, Z8536_PB_DPP_REG);
133         z8536_write(dev, 0xff, Z8536_PB_DD_REG);
134 
135         /*
136          * Not sure what Port C is connected to...
137          */
138         z8536_write(dev, 0x09, Z8536_PC_DPP_REG);
139         z8536_write(dev, 0x0e, Z8536_PC_DD_REG);
140 
141         /*
142          * Clear and disable all interrupt sources.
143          *
144          * Just in case, the reset of the Z8536 should have already
145          * done this.
146          */
147         z8536_write(dev, Z8536_CMD_CLR_IP_IUS, Z8536_PA_CMDSTAT_REG);
148         z8536_write(dev, Z8536_CMD_CLR_IE, Z8536_PA_CMDSTAT_REG);
149 
150         z8536_write(dev, Z8536_CMD_CLR_IP_IUS, Z8536_PB_CMDSTAT_REG);
151         z8536_write(dev, Z8536_CMD_CLR_IE, Z8536_PB_CMDSTAT_REG);
152 
153         z8536_write(dev, Z8536_CMD_CLR_IP_IUS, Z8536_CT_CMDSTAT_REG(0));
154         z8536_write(dev, Z8536_CMD_CLR_IE, Z8536_CT_CMDSTAT_REG(0));
155 
156         z8536_write(dev, Z8536_CMD_CLR_IP_IUS, Z8536_CT_CMDSTAT_REG(1));
157         z8536_write(dev, Z8536_CMD_CLR_IE, Z8536_CT_CMDSTAT_REG(1));
158 
159         z8536_write(dev, Z8536_CMD_CLR_IP_IUS, Z8536_CT_CMDSTAT_REG(2));
160         z8536_write(dev, Z8536_CMD_CLR_IE, Z8536_CT_CMDSTAT_REG(2));
161 
162         /* Disable all interrupts */
163         z8536_write(dev, 0x00, Z8536_INT_CTRL_REG);
164 }
165 
166 static void apci1500_port_enable(struct comedi_device *dev, bool enable)
167 {
168         unsigned int cfg;
169 
170         cfg = z8536_read(dev, Z8536_CFG_CTRL_REG);
171         if (enable)
172                 cfg |= (Z8536_CFG_CTRL_PAE | Z8536_CFG_CTRL_PBE);
173         else
174                 cfg &= ~(Z8536_CFG_CTRL_PAE | Z8536_CFG_CTRL_PBE);
175         z8536_write(dev, cfg, Z8536_CFG_CTRL_REG);
176 }
177 
178 static void apci1500_timer_enable(struct comedi_device *dev,
179                                   unsigned int chan, bool enable)
180 {
181         unsigned int bit;
182         unsigned int cfg;
183 
184         if (chan == 0)
185                 bit = Z8536_CFG_CTRL_CT1E;
186         else if (chan == 1)
187                 bit = Z8536_CFG_CTRL_CT2E;
188         else
189                 bit = Z8536_CFG_CTRL_PCE_CT3E;
190 
191         cfg = z8536_read(dev, Z8536_CFG_CTRL_REG);
192         if (enable) {
193                 cfg |= bit;
194         } else {
195                 cfg &= ~bit;
196                 z8536_write(dev, 0x00, Z8536_CT_CMDSTAT_REG(chan));
197         }
198         z8536_write(dev, cfg, Z8536_CFG_CTRL_REG);
199 }
200 
201 static bool apci1500_ack_irq(struct comedi_device *dev,
202                              unsigned int reg)
203 {
204         unsigned int val;
205 
206         val = z8536_read(dev, reg);
207         if ((val & Z8536_STAT_IE_IP) == Z8536_STAT_IE_IP) {
208                 val &= 0x0f;                    /* preserve any write bits */
209                 val |= Z8536_CMD_CLR_IP_IUS;
210                 z8536_write(dev, val, reg);
211 
212                 return true;
213         }
214         return false;
215 }
216 
217 static irqreturn_t apci1500_interrupt(int irq, void *d)
218 {
219         struct comedi_device *dev = d;
220         struct apci1500_private *devpriv = dev->private;
221         struct comedi_subdevice *s = dev->read_subdev;
222         unsigned int status = 0;
223         unsigned int val;
224 
225         val = inl(devpriv->amcc + AMCC_OP_REG_INTCSR);
226         if (!(val & INTCSR_INTR_ASSERTED))
227                 return IRQ_NONE;
228 
229         if (apci1500_ack_irq(dev, Z8536_PA_CMDSTAT_REG))
230                 status |= 0x01; /* port a event (inputs 0-7) */
231 
232         if (apci1500_ack_irq(dev, Z8536_PB_CMDSTAT_REG)) {
233                 /* Tests if this is an external error */
234                 val = inb(dev->iobase + APCI1500_Z8536_PORTB_REG);
235                 val &= 0xc0;
236                 if (val) {
237                         if (val & 0x80) /* voltage error */
238                                 status |= 0x40;
239                         if (val & 0x40) /* short circuit error */
240                                 status |= 0x80;
241                 } else {
242                         status |= 0x02; /* port b event (inputs 8-13) */
243                 }
244         }
245 
246         /*
247          * NOTE: The 'status' returned by the sample matches the
248          * interrupt mask information from the APCI-1500 Users Manual.
249          *
250          *    Mask     Meaning
251          * ----------  ------------------------------------------
252          * 0x00000001  Event 1 has occured
253          * 0x00000010  Event 2 has occured
254          * 0x00000100  Counter/timer 1 has run down (not implemented)
255          * 0x00001000  Counter/timer 2 has run down (not implemented)
256          * 0x00010000  Counter 3 has run down (not implemented)
257          * 0x00100000  Watchdog has run down (not implemented)
258          * 0x01000000  Voltage error
259          * 0x10000000  Short-circuit error
260          */
261         comedi_buf_write_samples(s, &status, 1);
262         comedi_handle_events(dev, s);
263 
264         return IRQ_HANDLED;
265 }
266 
267 static int apci1500_di_cancel(struct comedi_device *dev,
268                               struct comedi_subdevice *s)
269 {
270         /* Disables the main interrupt on the board */
271         z8536_write(dev, 0x00, Z8536_INT_CTRL_REG);
272 
273         /* Disable Ports A & B */
274         apci1500_port_enable(dev, false);
275 
276         /* Ack any pending interrupts */
277         apci1500_ack_irq(dev, Z8536_PA_CMDSTAT_REG);
278         apci1500_ack_irq(dev, Z8536_PB_CMDSTAT_REG);
279 
280         /* Disable pattern interrupts */
281         z8536_write(dev, Z8536_CMD_CLR_IE, Z8536_PA_CMDSTAT_REG);
282         z8536_write(dev, Z8536_CMD_CLR_IE, Z8536_PB_CMDSTAT_REG);
283 
284         /* Enable Ports A & B */
285         apci1500_port_enable(dev, true);
286 
287         return 0;
288 }
289 
290 static int apci1500_di_inttrig_start(struct comedi_device *dev,
291                                      struct comedi_subdevice *s,
292                                      unsigned int trig_num)
293 {
294         struct apci1500_private *devpriv = dev->private;
295         struct comedi_cmd *cmd = &s->async->cmd;
296         unsigned int pa_mode = Z8536_PAB_MODE_PMS_DISABLE;
297         unsigned int pb_mode = Z8536_PAB_MODE_PMS_DISABLE;
298         unsigned int pa_trig = trig_num & 0x01;
299         unsigned int pb_trig = (trig_num >> 1) & 0x01;
300         bool valid_trig = false;
301         unsigned int val;
302 
303         if (trig_num != cmd->start_arg)
304                 return -EINVAL;
305 
306         /* Disable Ports A & B */
307         apci1500_port_enable(dev, false);
308 
309         /* Set Port A for selected trigger pattern */
310         z8536_write(dev, devpriv->pm[pa_trig] & 0xff, Z8536_PA_PM_REG);
311         z8536_write(dev, devpriv->pt[pa_trig] & 0xff, Z8536_PA_PT_REG);
312         z8536_write(dev, devpriv->pp[pa_trig] & 0xff, Z8536_PA_PP_REG);
313 
314         /* Set Port B for selected trigger pattern */
315         z8536_write(dev, (devpriv->pm[pb_trig] >> 8) & 0xff, Z8536_PB_PM_REG);
316         z8536_write(dev, (devpriv->pt[pb_trig] >> 8) & 0xff, Z8536_PB_PT_REG);
317         z8536_write(dev, (devpriv->pp[pb_trig] >> 8) & 0xff, Z8536_PB_PP_REG);
318 
319         /* Set Port A trigger mode (if enabled) and enable interrupt */
320         if (devpriv->pm[pa_trig] & 0xff) {
321                 pa_mode = pa_trig ? Z8536_PAB_MODE_PMS_AND
322                                   : Z8536_PAB_MODE_PMS_OR;
323 
324                 val = z8536_read(dev, Z8536_PA_MODE_REG);
325                 val &= ~Z8536_PAB_MODE_PMS_MASK;
326                 val |= (pa_mode | Z8536_PAB_MODE_IMO);
327                 z8536_write(dev, val, Z8536_PA_MODE_REG);
328 
329                 z8536_write(dev, Z8536_CMD_SET_IE, Z8536_PA_CMDSTAT_REG);
330 
331                 valid_trig = true;
332 
333                 dev_dbg(dev->class_dev,
334                         "Port A configured for %s mode pattern detection\n",
335                         pa_trig ? "AND" : "OR");
336         }
337 
338         /* Set Port B trigger mode (if enabled) and enable interrupt */
339         if (devpriv->pm[pb_trig] & 0xff00) {
340                 pb_mode = pb_trig ? Z8536_PAB_MODE_PMS_AND
341                                   : Z8536_PAB_MODE_PMS_OR;
342 
343                 val = z8536_read(dev, Z8536_PB_MODE_REG);
344                 val &= ~Z8536_PAB_MODE_PMS_MASK;
345                 val |= (pb_mode | Z8536_PAB_MODE_IMO);
346                 z8536_write(dev, val, Z8536_PB_MODE_REG);
347 
348                 z8536_write(dev, Z8536_CMD_SET_IE, Z8536_PB_CMDSTAT_REG);
349 
350                 valid_trig = true;
351 
352                 dev_dbg(dev->class_dev,
353                         "Port B configured for %s mode pattern detection\n",
354                         pb_trig ? "AND" : "OR");
355         }
356 
357         /* Enable Ports A & B */
358         apci1500_port_enable(dev, true);
359 
360         if (!valid_trig) {
361                 dev_dbg(dev->class_dev,
362                         "digital trigger %d is not configured\n", trig_num);
363                 return -EINVAL;
364         }
365 
366         /* Authorizes the main interrupt on the board */
367         z8536_write(dev, Z8536_INT_CTRL_MIE | Z8536_INT_CTRL_DLC,
368                     Z8536_INT_CTRL_REG);
369 
370         return 0;
371 }
372 
373 static int apci1500_di_cmd(struct comedi_device *dev,
374                            struct comedi_subdevice *s)
375 {
376         s->async->inttrig = apci1500_di_inttrig_start;
377 
378         return 0;
379 }
380 
381 static int apci1500_di_cmdtest(struct comedi_device *dev,
382                                struct comedi_subdevice *s,
383                                struct comedi_cmd *cmd)
384 {
385         int err = 0;
386 
387         /* Step 1 : check if triggers are trivially valid */
388 
389         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
390         err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
391         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
392         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
393         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
394 
395         if (err)
396                 return 1;
397 
398         /* Step 2a : make sure trigger sources are unique */
399         /* Step 2b : and mutually compatible */
400 
401         /* Step 3: check if arguments are trivially valid */
402 
403         /*
404          * Internal start source triggers:
405          *
406          *   0  AND mode for Port A (digital inputs 0-7)
407          *      AND mode for Port B (digital inputs 8-13 and internal signals)
408          *
409          *   1  OR mode for Port A (digital inputs 0-7)
410          *      AND mode for Port B (digital inputs 8-13 and internal signals)
411          *
412          *   2  AND mode for Port A (digital inputs 0-7)
413          *      OR mode for Port B (digital inputs 8-13 and internal signals)
414          *
415          *   3  OR mode for Port A (digital inputs 0-7)
416          *      OR mode for Port B (digital inputs 8-13 and internal signals)
417          */
418         err |= cfc_check_trigger_arg_max(&cmd->start_arg, 3);
419 
420         err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
421         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
422         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
423         err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
424 
425         if (err)
426                 return 3;
427 
428         /* Step 4: fix up any arguments */
429 
430         /* Step 5: check channel list if it exists */
431 
432         return 0;
433 }
434 
435 /*
436  * The pattern-recognition logic must be configured before the digital
437  * input async command is started.
438  *
439  * Digital input channels 0 to 13 can generate interrupts. Channels 14
440  * and 15 are connected to internal board status/diagnostic signals.
441  *
442  * Channel 14 - Voltage error (the external supply is < 5V)
443  * Channel 15 - Short-circuit/overtemperature error
444  *
445  *      data[0] : INSN_CONFIG_DIGITAL_TRIG
446  *      data[1] : trigger number
447  *                0 = AND mode
448  *                1 = OR mode
449  *      data[2] : configuration operation:
450  *                COMEDI_DIGITAL_TRIG_DISABLE = no interrupts
451  *                COMEDI_DIGITAL_TRIG_ENABLE_EDGES = edge interrupts
452  *                COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = level interrupts
453  *      data[3] : left-shift for data[4] and data[5]
454  *      data[4] : rising-edge/high level channels
455  *      data[5] : falling-edge/low level channels
456  */
457 static int apci1500_di_cfg_trig(struct comedi_device *dev,
458                                 struct comedi_subdevice *s,
459                                 struct comedi_insn *insn,
460                                 unsigned int *data)
461 {
462         struct apci1500_private *devpriv = dev->private;
463         unsigned int trig = data[1];
464         unsigned int shift = data[3];
465         unsigned int hi_mask = data[4] << shift;
466         unsigned int lo_mask = data[5] << shift;
467         unsigned int chan_mask = hi_mask | lo_mask;
468         unsigned int old_mask = (1 << shift) - 1;
469         unsigned int pm = devpriv->pm[trig] & old_mask;
470         unsigned int pt = devpriv->pt[trig] & old_mask;
471         unsigned int pp = devpriv->pp[trig] & old_mask;
472 
473         if (trig > 1) {
474                 dev_dbg(dev->class_dev,
475                         "invalid digital trigger number (0=AND, 1=OR)\n");
476                 return -EINVAL;
477         }
478 
479         if (chan_mask > 0xffff) {
480                 dev_dbg(dev->class_dev, "invalid digital trigger channel\n");
481                 return -EINVAL;
482         }
483 
484         switch (data[2]) {
485         case COMEDI_DIGITAL_TRIG_DISABLE:
486                 /* clear trigger configuration */
487                 pm = 0;
488                 pt = 0;
489                 pp = 0;
490                 break;
491         case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
492                 pm |= chan_mask;        /* enable channels */
493                 pt |= chan_mask;        /* enable edge detection */
494                 pp |= hi_mask;          /* rising-edge channels */
495                 pp &= ~lo_mask;         /* falling-edge channels */
496                 break;
497         case COMEDI_DIGITAL_TRIG_ENABLE_LEVELS:
498                 pm |= chan_mask;        /* enable channels */
499                 pt &= ~chan_mask;       /* enable level detection */
500                 pp |= hi_mask;          /* high level channels */
501                 pp &= ~lo_mask;         /* low level channels */
502                 break;
503         default:
504                 return -EINVAL;
505         }
506 
507         /*
508          * The AND mode trigger can only have one channel (max) enabled
509          * for edge detection.
510          */
511         if (trig == 0) {
512                 int ret = 0;
513                 unsigned int src;
514 
515                 src = pt & 0xff;
516                 if (src)
517                         ret |= cfc_check_trigger_is_unique(src);
518 
519                 src = (pt >> 8) & 0xff;
520                 if (src)
521                         ret |= cfc_check_trigger_is_unique(src);
522 
523                 if (ret) {
524                         dev_dbg(dev->class_dev,
525                                 "invalid AND trigger configuration\n");
526                         return ret;
527                 }
528         }
529 
530         /* save the trigger configuration */
531         devpriv->pm[trig] = pm;
532         devpriv->pt[trig] = pt;
533         devpriv->pp[trig] = pp;
534 
535         return insn->n;
536 }
537 
538 static int apci1500_di_insn_config(struct comedi_device *dev,
539                                    struct comedi_subdevice *s,
540                                    struct comedi_insn *insn,
541                                    unsigned int *data)
542 {
543         switch (data[0]) {
544         case INSN_CONFIG_DIGITAL_TRIG:
545                 return apci1500_di_cfg_trig(dev, s, insn, data);
546         default:
547                 return -EINVAL;
548         }
549 }
550 
551 static int apci1500_di_insn_bits(struct comedi_device *dev,
552                                  struct comedi_subdevice *s,
553                                  struct comedi_insn *insn,
554                                  unsigned int *data)
555 {
556         struct apci1500_private *devpriv = dev->private;
557 
558         data[1] = inw(devpriv->addon + APCI1500_DI_REG);
559 
560         return insn->n;
561 }
562 
563 static int apci1500_do_insn_bits(struct comedi_device *dev,
564                                  struct comedi_subdevice *s,
565                                  struct comedi_insn *insn,
566                                  unsigned int *data)
567 {
568         struct apci1500_private *devpriv = dev->private;
569 
570         if (comedi_dio_update_state(s, data))
571                 outw(s->state, devpriv->addon + APCI1500_DO_REG);
572 
573         data[1] = s->state;
574 
575         return insn->n;
576 }
577 
578 static int apci1500_timer_insn_config(struct comedi_device *dev,
579                                       struct comedi_subdevice *s,
580                                       struct comedi_insn *insn,
581                                       unsigned int *data)
582 {
583         struct apci1500_private *devpriv = dev->private;
584         unsigned int chan = CR_CHAN(insn->chanspec);
585         unsigned int val;
586 
587         switch (data[0]) {
588         case INSN_CONFIG_ARM:
589                 val = data[1] & s->maxdata;
590                 z8536_write(dev, val & 0xff, Z8536_CT_RELOAD_LSB_REG(chan));
591                 z8536_write(dev, (val >> 8) & 0xff,
592                             Z8536_CT_RELOAD_MSB_REG(chan));
593 
594                 apci1500_timer_enable(dev, chan, true);
595                 z8536_write(dev, Z8536_CT_CMDSTAT_GCB,
596                             Z8536_CT_CMDSTAT_REG(chan));
597                 break;
598         case INSN_CONFIG_DISARM:
599                 apci1500_timer_enable(dev, chan, false);
600                 break;
601 
602         case INSN_CONFIG_GET_COUNTER_STATUS:
603                 data[1] = 0;
604                 val = z8536_read(dev, Z8536_CT_CMDSTAT_REG(chan));
605                 if (val & Z8536_CT_STAT_CIP)
606                         data[1] |= COMEDI_COUNTER_COUNTING;
607                 if (val & Z8536_CT_CMDSTAT_GCB)
608                         data[1] |= COMEDI_COUNTER_ARMED;
609                 if (val & Z8536_STAT_IP) {
610                         data[1] |= COMEDI_COUNTER_TERMINAL_COUNT;
611                         apci1500_ack_irq(dev, Z8536_CT_CMDSTAT_REG(chan));
612                 }
613                 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING |
614                           COMEDI_COUNTER_TERMINAL_COUNT;
615                 break;
616 
617         case INSN_CONFIG_SET_COUNTER_MODE:
618                 /* Simulate the 8254 timer modes */
619                 switch (data[1]) {
620                 case I8254_MODE0:
621                         /* Interrupt on Terminal Count */
622                         val = Z8536_CT_MODE_ECE |
623                               Z8536_CT_MODE_DCS_ONESHOT;
624                         break;
625                 case I8254_MODE1:
626                         /* Hardware Retriggerable One-Shot */
627                         val = Z8536_CT_MODE_ETE |
628                               Z8536_CT_MODE_DCS_ONESHOT;
629                         break;
630                 case I8254_MODE2:
631                         /* Rate Generator */
632                         val = Z8536_CT_MODE_CSC |
633                               Z8536_CT_MODE_DCS_PULSE;
634                         break;
635                 case I8254_MODE3:
636                         /* Square Wave Mode */
637                         val = Z8536_CT_MODE_CSC |
638                               Z8536_CT_MODE_DCS_SQRWAVE;
639                         break;
640                 case I8254_MODE4:
641                         /* Software Triggered Strobe */
642                         val = Z8536_CT_MODE_REB |
643                               Z8536_CT_MODE_DCS_PULSE;
644                         break;
645                 case I8254_MODE5:
646                         /* Hardware Triggered Strobe (watchdog) */
647                         val = Z8536_CT_MODE_EOE |
648                               Z8536_CT_MODE_ETE |
649                               Z8536_CT_MODE_REB |
650                               Z8536_CT_MODE_DCS_PULSE;
651                         break;
652                 default:
653                         return -EINVAL;
654                 }
655                 apci1500_timer_enable(dev, chan, false);
656                 z8536_write(dev, val, Z8536_CT_MODE_REG(chan));
657                 break;
658 
659         case INSN_CONFIG_SET_CLOCK_SRC:
660                 if (data[1] > 2)
661                         return -EINVAL;
662                 devpriv->clk_src = data[1];
663                 if (devpriv->clk_src == 2)
664                         devpriv->clk_src = 3;
665                 outw(devpriv->clk_src, devpriv->addon + APCI1500_CLK_SEL_REG);
666                 break;
667         case INSN_CONFIG_GET_CLOCK_SRC:
668                 switch (devpriv->clk_src) {
669                 case 0:
670                         data[1] = 0;            /* 111.86 kHz / 2 */
671                         data[2] = 17879;        /* 17879 ns (approx) */
672                         break;
673                 case 1:
674                         data[1] = 1;            /* 3.49 kHz / 2 */
675                         data[2] = 573066;       /* 573066 ns (approx) */
676                         break;
677                 case 3:
678                         data[1] = 2;            /* 1.747 kHz / 2 */
679                         data[2] = 1164822;      /* 1164822 ns (approx) */
680                         break;
681                 default:
682                         return -EINVAL;
683                 }
684                 break;
685 
686         case INSN_CONFIG_SET_GATE_SRC:
687                 if (chan == 0)
688                         return -EINVAL;
689 
690                 val = z8536_read(dev, Z8536_CT_MODE_REG(chan));
691                 val &= Z8536_CT_MODE_EGE;
692                 if (data[1] == 1)
693                         val |= Z8536_CT_MODE_EGE;
694                 else if (data[1] > 1)
695                         return -EINVAL;
696                 z8536_write(dev, val, Z8536_CT_MODE_REG(chan));
697                 break;
698         case INSN_CONFIG_GET_GATE_SRC:
699                 if (chan == 0)
700                         return -EINVAL;
701                 break;
702 
703         default:
704                 return -EINVAL;
705         }
706         return insn->n;
707 }
708 
709 static int apci1500_timer_insn_write(struct comedi_device *dev,
710                                      struct comedi_subdevice *s,
711                                      struct comedi_insn *insn,
712                                      unsigned int *data)
713 {
714         unsigned int chan = CR_CHAN(insn->chanspec);
715         unsigned int cmd;
716 
717         cmd = z8536_read(dev, Z8536_CT_CMDSTAT_REG(chan));
718         cmd &= Z8536_CT_CMDSTAT_GCB;    /* preserve gate */
719         cmd |= Z8536_CT_CMD_TCB;        /* set trigger */
720 
721         /* software trigger a timer, it only makes sense to do one write */
722         if (insn->n)
723                 z8536_write(dev, cmd, Z8536_CT_CMDSTAT_REG(chan));
724 
725         return insn->n;
726 }
727 
728 static int apci1500_timer_insn_read(struct comedi_device *dev,
729                                     struct comedi_subdevice *s,
730                                     struct comedi_insn *insn,
731                                     unsigned int *data)
732 {
733         unsigned int chan = CR_CHAN(insn->chanspec);
734         unsigned int cmd;
735         unsigned int val;
736         int i;
737 
738         cmd = z8536_read(dev, Z8536_CT_CMDSTAT_REG(chan));
739         cmd &= Z8536_CT_CMDSTAT_GCB;    /* preserve gate */
740         cmd |= Z8536_CT_CMD_RCC;        /* set RCC */
741 
742         for (i = 0; i < insn->n; i++) {
743                 z8536_write(dev, cmd, Z8536_CT_CMDSTAT_REG(chan));
744 
745                 val = z8536_read(dev, Z8536_CT_VAL_MSB_REG(chan)) << 8;
746                 val |= z8536_read(dev, Z8536_CT_VAL_LSB_REG(chan));
747 
748                 data[i] = val;
749         }
750 
751         return insn->n;
752 }
753 
754 static int apci1500_auto_attach(struct comedi_device *dev,
755                                 unsigned long context)
756 {
757         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
758         struct apci1500_private *devpriv;
759         struct comedi_subdevice *s;
760         int ret;
761 
762         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
763         if (!devpriv)
764                 return -ENOMEM;
765 
766         ret = comedi_pci_enable(dev);
767         if (ret)
768                 return ret;
769 
770         dev->iobase = pci_resource_start(pcidev, 1);
771         devpriv->amcc = pci_resource_start(pcidev, 0);
772         devpriv->addon = pci_resource_start(pcidev, 2);
773 
774         z8536_reset(dev);
775 
776         if (pcidev->irq > 0) {
777                 ret = request_irq(pcidev->irq, apci1500_interrupt, IRQF_SHARED,
778                                   dev->board_name, dev);
779                 if (ret == 0)
780                         dev->irq = pcidev->irq;
781         }
782 
783         ret = comedi_alloc_subdevices(dev, 3);
784         if (ret)
785                 return ret;
786 
787         /* Digital Input subdevice */
788         s = &dev->subdevices[0];
789         s->type         = COMEDI_SUBD_DI;
790         s->subdev_flags = SDF_READABLE;
791         s->n_chan       = 16;
792         s->maxdata      = 1;
793         s->range_table  = &range_digital;
794         s->insn_bits    = apci1500_di_insn_bits;
795         if (dev->irq) {
796                 dev->read_subdev = s;
797                 s->subdev_flags |= SDF_CMD_READ;
798                 s->len_chanlist = 1;
799                 s->insn_config  = apci1500_di_insn_config;
800                 s->do_cmdtest   = apci1500_di_cmdtest;
801                 s->do_cmd       = apci1500_di_cmd;
802                 s->cancel       = apci1500_di_cancel;
803         }
804 
805         /* Digital Output subdevice */
806         s = &dev->subdevices[1];
807         s->type         = COMEDI_SUBD_DO;
808         s->subdev_flags = SDF_WRITABLE;
809         s->n_chan       = 16;
810         s->maxdata      = 1;
811         s->range_table  = &range_digital;
812         s->insn_bits    = apci1500_do_insn_bits;
813 
814         /* reset all the digital outputs */
815         outw(0x0, devpriv->addon + APCI1500_DO_REG);
816 
817         /* Counter/Timer(Watchdog) subdevice */
818         s = &dev->subdevices[2];
819         s->type         = COMEDI_SUBD_TIMER;
820         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
821         s->n_chan       = 3;
822         s->maxdata      = 0xffff;
823         s->range_table  = &range_unknown;
824         s->insn_config  = apci1500_timer_insn_config;
825         s->insn_write   = apci1500_timer_insn_write;
826         s->insn_read    = apci1500_timer_insn_read;
827 
828         /* Enable the PCI interrupt */
829         if (dev->irq) {
830                 outl(0x2000 | INTCSR_INBOX_FULL_INT,
831                      devpriv->amcc + AMCC_OP_REG_INTCSR);
832                 inl(devpriv->amcc + AMCC_OP_REG_IMB1);
833                 inl(devpriv->amcc + AMCC_OP_REG_INTCSR);
834                 outl(INTCSR_INBOX_INTR_STATUS | 0x2000 | INTCSR_INBOX_FULL_INT,
835                      devpriv->amcc + AMCC_OP_REG_INTCSR);
836         }
837 
838         return 0;
839 }
840 
841 static void apci1500_detach(struct comedi_device *dev)
842 {
843         struct apci1500_private *devpriv = dev->private;
844 
845         if (devpriv->amcc)
846                 outl(0x0, devpriv->amcc + AMCC_OP_REG_INTCSR);
847         comedi_pci_detach(dev);
848 }
849 
850 static struct comedi_driver apci1500_driver = {
851         .driver_name    = "addi_apci_1500",
852         .module         = THIS_MODULE,
853         .auto_attach    = apci1500_auto_attach,
854         .detach         = apci1500_detach,
855 };
856 
857 static int apci1500_pci_probe(struct pci_dev *dev,
858                               const struct pci_device_id *id)
859 {
860         return comedi_pci_auto_config(dev, &apci1500_driver, id->driver_data);
861 }
862 
863 static const struct pci_device_id apci1500_pci_table[] = {
864         { PCI_DEVICE(PCI_VENDOR_ID_AMCC, 0x80fc) },
865         { 0 }
866 };
867 MODULE_DEVICE_TABLE(pci, apci1500_pci_table);
868 
869 static struct pci_driver apci1500_pci_driver = {
870         .name           = "addi_apci_1500",
871         .id_table       = apci1500_pci_table,
872         .probe          = apci1500_pci_probe,
873         .remove         = comedi_pci_auto_unconfig,
874 };
875 module_comedi_pci_driver(apci1500_driver, apci1500_pci_driver);
876 
877 MODULE_AUTHOR("Comedi http://www.comedi.org");
878 MODULE_DESCRIPTION("ADDI-DATA APCI-1500, 16 channel DI / 16 channel DO boards");
879 MODULE_LICENSE("GPL");
880 

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