Version:  2.0.40 2.2.26 2.4.37 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6

Linux/drivers/spi/spi-xilinx.c

  1 /*
  2  * Xilinx SPI controller driver (master mode only)
  3  *
  4  * Author: MontaVista Software, Inc.
  5  *      source@mvista.com
  6  *
  7  * Copyright (c) 2010 Secret Lab Technologies, Ltd.
  8  * Copyright (c) 2009 Intel Corporation
  9  * 2002-2007 (c) MontaVista Software, Inc.
 10 
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License version 2 as
 13  * published by the Free Software Foundation.
 14  */
 15 
 16 #include <linux/module.h>
 17 #include <linux/interrupt.h>
 18 #include <linux/of.h>
 19 #include <linux/platform_device.h>
 20 #include <linux/spi/spi.h>
 21 #include <linux/spi/spi_bitbang.h>
 22 #include <linux/spi/xilinx_spi.h>
 23 #include <linux/io.h>
 24 
 25 #define XILINX_SPI_MAX_CS       32
 26 
 27 #define XILINX_SPI_NAME "xilinx_spi"
 28 
 29 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
 30  * Product Specification", DS464
 31  */
 32 #define XSPI_CR_OFFSET          0x60    /* Control Register */
 33 
 34 #define XSPI_CR_LOOP            0x01
 35 #define XSPI_CR_ENABLE          0x02
 36 #define XSPI_CR_MASTER_MODE     0x04
 37 #define XSPI_CR_CPOL            0x08
 38 #define XSPI_CR_CPHA            0x10
 39 #define XSPI_CR_MODE_MASK       (XSPI_CR_CPHA | XSPI_CR_CPOL | \
 40                                  XSPI_CR_LSB_FIRST | XSPI_CR_LOOP)
 41 #define XSPI_CR_TXFIFO_RESET    0x20
 42 #define XSPI_CR_RXFIFO_RESET    0x40
 43 #define XSPI_CR_MANUAL_SSELECT  0x80
 44 #define XSPI_CR_TRANS_INHIBIT   0x100
 45 #define XSPI_CR_LSB_FIRST       0x200
 46 
 47 #define XSPI_SR_OFFSET          0x64    /* Status Register */
 48 
 49 #define XSPI_SR_RX_EMPTY_MASK   0x01    /* Receive FIFO is empty */
 50 #define XSPI_SR_RX_FULL_MASK    0x02    /* Receive FIFO is full */
 51 #define XSPI_SR_TX_EMPTY_MASK   0x04    /* Transmit FIFO is empty */
 52 #define XSPI_SR_TX_FULL_MASK    0x08    /* Transmit FIFO is full */
 53 #define XSPI_SR_MODE_FAULT_MASK 0x10    /* Mode fault error */
 54 
 55 #define XSPI_TXD_OFFSET         0x68    /* Data Transmit Register */
 56 #define XSPI_RXD_OFFSET         0x6c    /* Data Receive Register */
 57 
 58 #define XSPI_SSR_OFFSET         0x70    /* 32-bit Slave Select Register */
 59 
 60 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
 61  * IPIF registers are 32 bit
 62  */
 63 #define XIPIF_V123B_DGIER_OFFSET        0x1c    /* IPIF global int enable reg */
 64 #define XIPIF_V123B_GINTR_ENABLE        0x80000000
 65 
 66 #define XIPIF_V123B_IISR_OFFSET         0x20    /* IPIF interrupt status reg */
 67 #define XIPIF_V123B_IIER_OFFSET         0x28    /* IPIF interrupt enable reg */
 68 
 69 #define XSPI_INTR_MODE_FAULT            0x01    /* Mode fault error */
 70 #define XSPI_INTR_SLAVE_MODE_FAULT      0x02    /* Selected as slave while
 71                                                  * disabled */
 72 #define XSPI_INTR_TX_EMPTY              0x04    /* TxFIFO is empty */
 73 #define XSPI_INTR_TX_UNDERRUN           0x08    /* TxFIFO was underrun */
 74 #define XSPI_INTR_RX_FULL               0x10    /* RxFIFO is full */
 75 #define XSPI_INTR_RX_OVERRUN            0x20    /* RxFIFO was overrun */
 76 #define XSPI_INTR_TX_HALF_EMPTY         0x40    /* TxFIFO is half empty */
 77 
 78 #define XIPIF_V123B_RESETR_OFFSET       0x40    /* IPIF reset register */
 79 #define XIPIF_V123B_RESET_MASK          0x0a    /* the value to write */
 80 
 81 struct xilinx_spi {
 82         /* bitbang has to be first */
 83         struct spi_bitbang bitbang;
 84         struct completion done;
 85         void __iomem    *regs;  /* virt. address of the control registers */
 86 
 87         int             irq;
 88 
 89         u8 *rx_ptr;             /* pointer in the Tx buffer */
 90         const u8 *tx_ptr;       /* pointer in the Rx buffer */
 91         u8 bytes_per_word;
 92         int buffer_size;        /* buffer size in words */
 93         u32 cs_inactive;        /* Level of the CS pins when inactive*/
 94         unsigned int (*read_fn)(void __iomem *);
 95         void (*write_fn)(u32, void __iomem *);
 96 };
 97 
 98 static void xspi_write32(u32 val, void __iomem *addr)
 99 {
100         iowrite32(val, addr);
101 }
102 
103 static unsigned int xspi_read32(void __iomem *addr)
104 {
105         return ioread32(addr);
106 }
107 
108 static void xspi_write32_be(u32 val, void __iomem *addr)
109 {
110         iowrite32be(val, addr);
111 }
112 
113 static unsigned int xspi_read32_be(void __iomem *addr)
114 {
115         return ioread32be(addr);
116 }
117 
118 static void xilinx_spi_tx(struct xilinx_spi *xspi)
119 {
120         u32 data = 0;
121 
122         if (!xspi->tx_ptr) {
123                 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
124                 return;
125         }
126 
127         switch (xspi->bytes_per_word) {
128         case 1:
129                 data = *(u8 *)(xspi->tx_ptr);
130                 break;
131         case 2:
132                 data = *(u16 *)(xspi->tx_ptr);
133                 break;
134         case 4:
135                 data = *(u32 *)(xspi->tx_ptr);
136                 break;
137         }
138 
139         xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET);
140         xspi->tx_ptr += xspi->bytes_per_word;
141 }
142 
143 static void xilinx_spi_rx(struct xilinx_spi *xspi)
144 {
145         u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
146 
147         if (!xspi->rx_ptr)
148                 return;
149 
150         switch (xspi->bytes_per_word) {
151         case 1:
152                 *(u8 *)(xspi->rx_ptr) = data;
153                 break;
154         case 2:
155                 *(u16 *)(xspi->rx_ptr) = data;
156                 break;
157         case 4:
158                 *(u32 *)(xspi->rx_ptr) = data;
159                 break;
160         }
161 
162         xspi->rx_ptr += xspi->bytes_per_word;
163 }
164 
165 static void xspi_init_hw(struct xilinx_spi *xspi)
166 {
167         void __iomem *regs_base = xspi->regs;
168 
169         /* Reset the SPI device */
170         xspi->write_fn(XIPIF_V123B_RESET_MASK,
171                 regs_base + XIPIF_V123B_RESETR_OFFSET);
172         /* Enable the transmit empty interrupt, which we use to determine
173          * progress on the transmission.
174          */
175         xspi->write_fn(XSPI_INTR_TX_EMPTY,
176                         regs_base + XIPIF_V123B_IIER_OFFSET);
177         /* Disable the global IPIF interrupt */
178         xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
179         /* Deselect the slave on the SPI bus */
180         xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
181         /* Disable the transmitter, enable Manual Slave Select Assertion,
182          * put SPI controller into master mode, and enable it */
183         xspi->write_fn(XSPI_CR_MANUAL_SSELECT | XSPI_CR_MASTER_MODE |
184                 XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | XSPI_CR_RXFIFO_RESET,
185                 regs_base + XSPI_CR_OFFSET);
186 }
187 
188 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
189 {
190         struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
191         u16 cr;
192         u32 cs;
193 
194         if (is_on == BITBANG_CS_INACTIVE) {
195                 /* Deselect the slave on the SPI bus */
196                 xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET);
197                 return;
198         }
199 
200         /* Set the SPI clock phase and polarity */
201         cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK;
202         if (spi->mode & SPI_CPHA)
203                 cr |= XSPI_CR_CPHA;
204         if (spi->mode & SPI_CPOL)
205                 cr |= XSPI_CR_CPOL;
206         if (spi->mode & SPI_LSB_FIRST)
207                 cr |= XSPI_CR_LSB_FIRST;
208         if (spi->mode & SPI_LOOP)
209                 cr |= XSPI_CR_LOOP;
210         xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
211 
212         /* We do not check spi->max_speed_hz here as the SPI clock
213          * frequency is not software programmable (the IP block design
214          * parameter)
215          */
216 
217         cs = xspi->cs_inactive;
218         cs ^= BIT(spi->chip_select);
219 
220         /* Activate the chip select */
221         xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET);
222 }
223 
224 /* spi_bitbang requires custom setup_transfer() to be defined if there is a
225  * custom txrx_bufs().
226  */
227 static int xilinx_spi_setup_transfer(struct spi_device *spi,
228                 struct spi_transfer *t)
229 {
230         struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
231 
232         if (spi->mode & SPI_CS_HIGH)
233                 xspi->cs_inactive &= ~BIT(spi->chip_select);
234         else
235                 xspi->cs_inactive |= BIT(spi->chip_select);
236 
237         return 0;
238 }
239 
240 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
241 {
242         struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
243         int remaining_words;    /* the number of words left to transfer */
244         bool use_irq = false;
245         u16 cr = 0;
246 
247         /* We get here with transmitter inhibited */
248 
249         xspi->tx_ptr = t->tx_buf;
250         xspi->rx_ptr = t->rx_buf;
251         remaining_words = t->len / xspi->bytes_per_word;
252 
253         if (xspi->irq >= 0 &&  remaining_words > xspi->buffer_size) {
254                 u32 isr;
255                 use_irq = true;
256                 /* Inhibit irq to avoid spurious irqs on tx_empty*/
257                 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
258                 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
259                                xspi->regs + XSPI_CR_OFFSET);
260                 /* ACK old irqs (if any) */
261                 isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
262                 if (isr)
263                         xspi->write_fn(isr,
264                                        xspi->regs + XIPIF_V123B_IISR_OFFSET);
265                 /* Enable the global IPIF interrupt */
266                 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
267                                 xspi->regs + XIPIF_V123B_DGIER_OFFSET);
268                 reinit_completion(&xspi->done);
269         }
270 
271         while (remaining_words) {
272                 int n_words, tx_words, rx_words;
273                 u32 sr;
274 
275                 n_words = min(remaining_words, xspi->buffer_size);
276 
277                 tx_words = n_words;
278                 while (tx_words--)
279                         xilinx_spi_tx(xspi);
280 
281                 /* Start the transfer by not inhibiting the transmitter any
282                  * longer
283                  */
284 
285                 if (use_irq) {
286                         xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
287                         wait_for_completion(&xspi->done);
288                         /* A transmit has just completed. Process received data
289                          * and check for more data to transmit. Always inhibit
290                          * the transmitter while the Isr refills the transmit
291                          * register/FIFO, or make sure it is stopped if we're
292                          * done.
293                          */
294                         xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
295                                        xspi->regs + XSPI_CR_OFFSET);
296                         sr = XSPI_SR_TX_EMPTY_MASK;
297                 } else
298                         sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
299 
300                 /* Read out all the data from the Rx FIFO */
301                 rx_words = n_words;
302                 while (rx_words) {
303                         if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) {
304                                 xilinx_spi_rx(xspi);
305                                 rx_words--;
306                                 continue;
307                         }
308 
309                         sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
310                         if (!(sr & XSPI_SR_RX_EMPTY_MASK)) {
311                                 xilinx_spi_rx(xspi);
312                                 rx_words--;
313                         }
314                 }
315 
316                 remaining_words -= n_words;
317         }
318 
319         if (use_irq) {
320                 xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET);
321                 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
322         }
323 
324         return t->len;
325 }
326 
327 
328 /* This driver supports single master mode only. Hence Tx FIFO Empty
329  * is the only interrupt we care about.
330  * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
331  * Fault are not to happen.
332  */
333 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
334 {
335         struct xilinx_spi *xspi = dev_id;
336         u32 ipif_isr;
337 
338         /* Get the IPIF interrupts, and clear them immediately */
339         ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
340         xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
341 
342         if (ipif_isr & XSPI_INTR_TX_EMPTY) {    /* Transmission completed */
343                 complete(&xspi->done);
344         }
345 
346         return IRQ_HANDLED;
347 }
348 
349 static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi)
350 {
351         u8 sr;
352         int n_words = 0;
353 
354         /*
355          * Before the buffer_size detection we reset the core
356          * to make sure we start with a clean state.
357          */
358         xspi->write_fn(XIPIF_V123B_RESET_MASK,
359                 xspi->regs + XIPIF_V123B_RESETR_OFFSET);
360 
361         /* Fill the Tx FIFO with as many words as possible */
362         do {
363                 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
364                 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
365                 n_words++;
366         } while (!(sr & XSPI_SR_TX_FULL_MASK));
367 
368         return n_words;
369 }
370 
371 static const struct of_device_id xilinx_spi_of_match[] = {
372         { .compatible = "xlnx,xps-spi-2.00.a", },
373         { .compatible = "xlnx,xps-spi-2.00.b", },
374         {}
375 };
376 MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
377 
378 static int xilinx_spi_probe(struct platform_device *pdev)
379 {
380         struct xilinx_spi *xspi;
381         struct xspi_platform_data *pdata;
382         struct resource *res;
383         int ret, num_cs = 0, bits_per_word = 8;
384         struct spi_master *master;
385         u32 tmp;
386         u8 i;
387 
388         pdata = dev_get_platdata(&pdev->dev);
389         if (pdata) {
390                 num_cs = pdata->num_chipselect;
391                 bits_per_word = pdata->bits_per_word;
392         } else {
393                 of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
394                                           &num_cs);
395         }
396 
397         if (!num_cs) {
398                 dev_err(&pdev->dev,
399                         "Missing slave select configuration data\n");
400                 return -EINVAL;
401         }
402 
403         if (num_cs > XILINX_SPI_MAX_CS) {
404                 dev_err(&pdev->dev, "Invalid number of spi slaves\n");
405                 return -EINVAL;
406         }
407 
408         master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
409         if (!master)
410                 return -ENODEV;
411 
412         /* the spi->mode bits understood by this driver: */
413         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP |
414                             SPI_CS_HIGH;
415 
416         xspi = spi_master_get_devdata(master);
417         xspi->cs_inactive = 0xffffffff;
418         xspi->bitbang.master = master;
419         xspi->bitbang.chipselect = xilinx_spi_chipselect;
420         xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
421         xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
422         init_completion(&xspi->done);
423 
424         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
425         xspi->regs = devm_ioremap_resource(&pdev->dev, res);
426         if (IS_ERR(xspi->regs)) {
427                 ret = PTR_ERR(xspi->regs);
428                 goto put_master;
429         }
430 
431         master->bus_num = pdev->id;
432         master->num_chipselect = num_cs;
433         master->dev.of_node = pdev->dev.of_node;
434 
435         /*
436          * Detect endianess on the IP via loop bit in CR. Detection
437          * must be done before reset is sent because incorrect reset
438          * value generates error interrupt.
439          * Setup little endian helper functions first and try to use them
440          * and check if bit was correctly setup or not.
441          */
442         xspi->read_fn = xspi_read32;
443         xspi->write_fn = xspi_write32;
444 
445         xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
446         tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
447         tmp &= XSPI_CR_LOOP;
448         if (tmp != XSPI_CR_LOOP) {
449                 xspi->read_fn = xspi_read32_be;
450                 xspi->write_fn = xspi_write32_be;
451         }
452 
453         master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
454         xspi->bytes_per_word = bits_per_word / 8;
455         xspi->buffer_size = xilinx_spi_find_buffer_size(xspi);
456 
457         xspi->irq = platform_get_irq(pdev, 0);
458         if (xspi->irq >= 0) {
459                 /* Register for SPI Interrupt */
460                 ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
461                                 dev_name(&pdev->dev), xspi);
462                 if (ret)
463                         goto put_master;
464         }
465 
466         /* SPI controller initializations */
467         xspi_init_hw(xspi);
468 
469         ret = spi_bitbang_start(&xspi->bitbang);
470         if (ret) {
471                 dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
472                 goto put_master;
473         }
474 
475         dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
476                 (unsigned long long)res->start, xspi->regs, xspi->irq);
477 
478         if (pdata) {
479                 for (i = 0; i < pdata->num_devices; i++)
480                         spi_new_device(master, pdata->devices + i);
481         }
482 
483         platform_set_drvdata(pdev, master);
484         return 0;
485 
486 put_master:
487         spi_master_put(master);
488 
489         return ret;
490 }
491 
492 static int xilinx_spi_remove(struct platform_device *pdev)
493 {
494         struct spi_master *master = platform_get_drvdata(pdev);
495         struct xilinx_spi *xspi = spi_master_get_devdata(master);
496         void __iomem *regs_base = xspi->regs;
497 
498         spi_bitbang_stop(&xspi->bitbang);
499 
500         /* Disable all the interrupts just in case */
501         xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
502         /* Disable the global IPIF interrupt */
503         xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
504 
505         spi_master_put(xspi->bitbang.master);
506 
507         return 0;
508 }
509 
510 /* work with hotplug and coldplug */
511 MODULE_ALIAS("platform:" XILINX_SPI_NAME);
512 
513 static struct platform_driver xilinx_spi_driver = {
514         .probe = xilinx_spi_probe,
515         .remove = xilinx_spi_remove,
516         .driver = {
517                 .name = XILINX_SPI_NAME,
518                 .of_match_table = xilinx_spi_of_match,
519         },
520 };
521 module_platform_driver(xilinx_spi_driver);
522 
523 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
524 MODULE_DESCRIPTION("Xilinx SPI driver");
525 MODULE_LICENSE("GPL");
526 

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