Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/spi/spi-xilinx.c

  1 /*
  2  * Xilinx SPI controller driver (master mode only)
  3  *
  4  * Author: MontaVista Software, Inc.
  5  *      source@mvista.com
  6  *
  7  * Copyright (c) 2010 Secret Lab Technologies, Ltd.
  8  * Copyright (c) 2009 Intel Corporation
  9  * 2002-2007 (c) MontaVista Software, Inc.
 10 
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License version 2 as
 13  * published by the Free Software Foundation.
 14  */
 15 
 16 #include <linux/module.h>
 17 #include <linux/interrupt.h>
 18 #include <linux/of.h>
 19 #include <linux/platform_device.h>
 20 #include <linux/spi/spi.h>
 21 #include <linux/spi/spi_bitbang.h>
 22 #include <linux/spi/xilinx_spi.h>
 23 #include <linux/io.h>
 24 
 25 #define XILINX_SPI_NAME "xilinx_spi"
 26 
 27 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
 28  * Product Specification", DS464
 29  */
 30 #define XSPI_CR_OFFSET          0x60    /* Control Register */
 31 
 32 #define XSPI_CR_LOOP            0x01
 33 #define XSPI_CR_ENABLE          0x02
 34 #define XSPI_CR_MASTER_MODE     0x04
 35 #define XSPI_CR_CPOL            0x08
 36 #define XSPI_CR_CPHA            0x10
 37 #define XSPI_CR_MODE_MASK       (XSPI_CR_CPHA | XSPI_CR_CPOL)
 38 #define XSPI_CR_TXFIFO_RESET    0x20
 39 #define XSPI_CR_RXFIFO_RESET    0x40
 40 #define XSPI_CR_MANUAL_SSELECT  0x80
 41 #define XSPI_CR_TRANS_INHIBIT   0x100
 42 #define XSPI_CR_LSB_FIRST       0x200
 43 
 44 #define XSPI_SR_OFFSET          0x64    /* Status Register */
 45 
 46 #define XSPI_SR_RX_EMPTY_MASK   0x01    /* Receive FIFO is empty */
 47 #define XSPI_SR_RX_FULL_MASK    0x02    /* Receive FIFO is full */
 48 #define XSPI_SR_TX_EMPTY_MASK   0x04    /* Transmit FIFO is empty */
 49 #define XSPI_SR_TX_FULL_MASK    0x08    /* Transmit FIFO is full */
 50 #define XSPI_SR_MODE_FAULT_MASK 0x10    /* Mode fault error */
 51 
 52 #define XSPI_TXD_OFFSET         0x68    /* Data Transmit Register */
 53 #define XSPI_RXD_OFFSET         0x6c    /* Data Receive Register */
 54 
 55 #define XSPI_SSR_OFFSET         0x70    /* 32-bit Slave Select Register */
 56 
 57 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
 58  * IPIF registers are 32 bit
 59  */
 60 #define XIPIF_V123B_DGIER_OFFSET        0x1c    /* IPIF global int enable reg */
 61 #define XIPIF_V123B_GINTR_ENABLE        0x80000000
 62 
 63 #define XIPIF_V123B_IISR_OFFSET         0x20    /* IPIF interrupt status reg */
 64 #define XIPIF_V123B_IIER_OFFSET         0x28    /* IPIF interrupt enable reg */
 65 
 66 #define XSPI_INTR_MODE_FAULT            0x01    /* Mode fault error */
 67 #define XSPI_INTR_SLAVE_MODE_FAULT      0x02    /* Selected as slave while
 68                                                  * disabled */
 69 #define XSPI_INTR_TX_EMPTY              0x04    /* TxFIFO is empty */
 70 #define XSPI_INTR_TX_UNDERRUN           0x08    /* TxFIFO was underrun */
 71 #define XSPI_INTR_RX_FULL               0x10    /* RxFIFO is full */
 72 #define XSPI_INTR_RX_OVERRUN            0x20    /* RxFIFO was overrun */
 73 #define XSPI_INTR_TX_HALF_EMPTY         0x40    /* TxFIFO is half empty */
 74 
 75 #define XIPIF_V123B_RESETR_OFFSET       0x40    /* IPIF reset register */
 76 #define XIPIF_V123B_RESET_MASK          0x0a    /* the value to write */
 77 
 78 struct xilinx_spi {
 79         /* bitbang has to be first */
 80         struct spi_bitbang bitbang;
 81         struct completion done;
 82         void __iomem    *regs;  /* virt. address of the control registers */
 83 
 84         int             irq;
 85 
 86         u8 *rx_ptr;             /* pointer in the Tx buffer */
 87         const u8 *tx_ptr;       /* pointer in the Rx buffer */
 88         int remaining_bytes;    /* the number of bytes left to transfer */
 89         u8 bits_per_word;
 90         unsigned int (*read_fn)(void __iomem *);
 91         void (*write_fn)(u32, void __iomem *);
 92         void (*tx_fn)(struct xilinx_spi *);
 93         void (*rx_fn)(struct xilinx_spi *);
 94 };
 95 
 96 static void xspi_write32(u32 val, void __iomem *addr)
 97 {
 98         iowrite32(val, addr);
 99 }
100 
101 static unsigned int xspi_read32(void __iomem *addr)
102 {
103         return ioread32(addr);
104 }
105 
106 static void xspi_write32_be(u32 val, void __iomem *addr)
107 {
108         iowrite32be(val, addr);
109 }
110 
111 static unsigned int xspi_read32_be(void __iomem *addr)
112 {
113         return ioread32be(addr);
114 }
115 
116 static void xspi_tx8(struct xilinx_spi *xspi)
117 {
118         xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET);
119         xspi->tx_ptr++;
120 }
121 
122 static void xspi_tx16(struct xilinx_spi *xspi)
123 {
124         xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
125         xspi->tx_ptr += 2;
126 }
127 
128 static void xspi_tx32(struct xilinx_spi *xspi)
129 {
130         xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
131         xspi->tx_ptr += 4;
132 }
133 
134 static void xspi_rx8(struct xilinx_spi *xspi)
135 {
136         u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
137         if (xspi->rx_ptr) {
138                 *xspi->rx_ptr = data & 0xff;
139                 xspi->rx_ptr++;
140         }
141 }
142 
143 static void xspi_rx16(struct xilinx_spi *xspi)
144 {
145         u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
146         if (xspi->rx_ptr) {
147                 *(u16 *)(xspi->rx_ptr) = data & 0xffff;
148                 xspi->rx_ptr += 2;
149         }
150 }
151 
152 static void xspi_rx32(struct xilinx_spi *xspi)
153 {
154         u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
155         if (xspi->rx_ptr) {
156                 *(u32 *)(xspi->rx_ptr) = data;
157                 xspi->rx_ptr += 4;
158         }
159 }
160 
161 static void xspi_init_hw(struct xilinx_spi *xspi)
162 {
163         void __iomem *regs_base = xspi->regs;
164 
165         /* Reset the SPI device */
166         xspi->write_fn(XIPIF_V123B_RESET_MASK,
167                 regs_base + XIPIF_V123B_RESETR_OFFSET);
168         /* Disable all the interrupts just in case */
169         xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
170         /* Enable the global IPIF interrupt */
171         xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
172                 regs_base + XIPIF_V123B_DGIER_OFFSET);
173         /* Deselect the slave on the SPI bus */
174         xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
175         /* Disable the transmitter, enable Manual Slave Select Assertion,
176          * put SPI controller into master mode, and enable it */
177         xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT |
178                 XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |
179                 XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
180 }
181 
182 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
183 {
184         struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
185 
186         if (is_on == BITBANG_CS_INACTIVE) {
187                 /* Deselect the slave on the SPI bus */
188                 xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
189         } else if (is_on == BITBANG_CS_ACTIVE) {
190                 /* Set the SPI clock phase and polarity */
191                 u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
192                          & ~XSPI_CR_MODE_MASK;
193                 if (spi->mode & SPI_CPHA)
194                         cr |= XSPI_CR_CPHA;
195                 if (spi->mode & SPI_CPOL)
196                         cr |= XSPI_CR_CPOL;
197                 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
198 
199                 /* We do not check spi->max_speed_hz here as the SPI clock
200                  * frequency is not software programmable (the IP block design
201                  * parameter)
202                  */
203 
204                 /* Activate the chip select */
205                 xspi->write_fn(~(0x0001 << spi->chip_select),
206                         xspi->regs + XSPI_SSR_OFFSET);
207         }
208 }
209 
210 /* spi_bitbang requires custom setup_transfer() to be defined if there is a
211  * custom txrx_bufs().
212  */
213 static int xilinx_spi_setup_transfer(struct spi_device *spi,
214                 struct spi_transfer *t)
215 {
216         return 0;
217 }
218 
219 static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
220 {
221         u8 sr;
222 
223         /* Fill the Tx FIFO with as many bytes as possible */
224         sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
225         while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
226                 if (xspi->tx_ptr)
227                         xspi->tx_fn(xspi);
228                 else
229                         xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
230                 xspi->remaining_bytes -= xspi->bits_per_word / 8;
231                 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
232         }
233 }
234 
235 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
236 {
237         struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
238         u32 ipif_ier;
239 
240         /* We get here with transmitter inhibited */
241 
242         xspi->tx_ptr = t->tx_buf;
243         xspi->rx_ptr = t->rx_buf;
244         xspi->remaining_bytes = t->len;
245         reinit_completion(&xspi->done);
246 
247 
248         /* Enable the transmit empty interrupt, which we use to determine
249          * progress on the transmission.
250          */
251         ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
252         xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
253                 xspi->regs + XIPIF_V123B_IIER_OFFSET);
254 
255         for (;;) {
256                 u16 cr;
257                 u8 sr;
258 
259                 xilinx_spi_fill_tx_fifo(xspi);
260 
261                 /* Start the transfer by not inhibiting the transmitter any
262                  * longer
263                  */
264                 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
265                                                         ~XSPI_CR_TRANS_INHIBIT;
266                 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
267 
268                 wait_for_completion(&xspi->done);
269 
270                 /* A transmit has just completed. Process received data and
271                  * check for more data to transmit. Always inhibit the
272                  * transmitter while the Isr refills the transmit register/FIFO,
273                  * or make sure it is stopped if we're done.
274                  */
275                 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
276                 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
277                                xspi->regs + XSPI_CR_OFFSET);
278 
279                 /* Read out all the data from the Rx FIFO */
280                 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
281                 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
282                         xspi->rx_fn(xspi);
283                         sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
284                 }
285 
286                 /* See if there is more data to send */
287                 if (xspi->remaining_bytes <= 0)
288                         break;
289         }
290 
291         /* Disable the transmit empty interrupt */
292         xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
293 
294         return t->len - xspi->remaining_bytes;
295 }
296 
297 
298 /* This driver supports single master mode only. Hence Tx FIFO Empty
299  * is the only interrupt we care about.
300  * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
301  * Fault are not to happen.
302  */
303 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
304 {
305         struct xilinx_spi *xspi = dev_id;
306         u32 ipif_isr;
307 
308         /* Get the IPIF interrupts, and clear them immediately */
309         ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
310         xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
311 
312         if (ipif_isr & XSPI_INTR_TX_EMPTY) {    /* Transmission completed */
313                 complete(&xspi->done);
314         }
315 
316         return IRQ_HANDLED;
317 }
318 
319 static const struct of_device_id xilinx_spi_of_match[] = {
320         { .compatible = "xlnx,xps-spi-2.00.a", },
321         { .compatible = "xlnx,xps-spi-2.00.b", },
322         {}
323 };
324 MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
325 
326 static int xilinx_spi_probe(struct platform_device *pdev)
327 {
328         struct xilinx_spi *xspi;
329         struct xspi_platform_data *pdata;
330         struct resource *res;
331         int ret, num_cs = 0, bits_per_word = 8;
332         struct spi_master *master;
333         u32 tmp;
334         u8 i;
335 
336         pdata = dev_get_platdata(&pdev->dev);
337         if (pdata) {
338                 num_cs = pdata->num_chipselect;
339                 bits_per_word = pdata->bits_per_word;
340         } else {
341                 of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
342                                           &num_cs);
343         }
344 
345         if (!num_cs) {
346                 dev_err(&pdev->dev,
347                         "Missing slave select configuration data\n");
348                 return -EINVAL;
349         }
350 
351         master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
352         if (!master)
353                 return -ENODEV;
354 
355         /* the spi->mode bits understood by this driver: */
356         master->mode_bits = SPI_CPOL | SPI_CPHA;
357 
358         xspi = spi_master_get_devdata(master);
359         xspi->bitbang.master = master;
360         xspi->bitbang.chipselect = xilinx_spi_chipselect;
361         xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
362         xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
363         init_completion(&xspi->done);
364 
365         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
366         xspi->regs = devm_ioremap_resource(&pdev->dev, res);
367         if (IS_ERR(xspi->regs)) {
368                 ret = PTR_ERR(xspi->regs);
369                 goto put_master;
370         }
371 
372         master->bus_num = pdev->id;
373         master->num_chipselect = num_cs;
374         master->dev.of_node = pdev->dev.of_node;
375 
376         /*
377          * Detect endianess on the IP via loop bit in CR. Detection
378          * must be done before reset is sent because incorrect reset
379          * value generates error interrupt.
380          * Setup little endian helper functions first and try to use them
381          * and check if bit was correctly setup or not.
382          */
383         xspi->read_fn = xspi_read32;
384         xspi->write_fn = xspi_write32;
385 
386         xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
387         tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
388         tmp &= XSPI_CR_LOOP;
389         if (tmp != XSPI_CR_LOOP) {
390                 xspi->read_fn = xspi_read32_be;
391                 xspi->write_fn = xspi_write32_be;
392         }
393 
394         master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
395         xspi->bits_per_word = bits_per_word;
396         if (xspi->bits_per_word == 8) {
397                 xspi->tx_fn = xspi_tx8;
398                 xspi->rx_fn = xspi_rx8;
399         } else if (xspi->bits_per_word == 16) {
400                 xspi->tx_fn = xspi_tx16;
401                 xspi->rx_fn = xspi_rx16;
402         } else if (xspi->bits_per_word == 32) {
403                 xspi->tx_fn = xspi_tx32;
404                 xspi->rx_fn = xspi_rx32;
405         } else {
406                 ret = -EINVAL;
407                 goto put_master;
408         }
409 
410         /* SPI controller initializations */
411         xspi_init_hw(xspi);
412 
413         xspi->irq = platform_get_irq(pdev, 0);
414         if (xspi->irq < 0) {
415                 ret = xspi->irq;
416                 goto put_master;
417         }
418 
419         /* Register for SPI Interrupt */
420         ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
421                                dev_name(&pdev->dev), xspi);
422         if (ret)
423                 goto put_master;
424 
425         ret = spi_bitbang_start(&xspi->bitbang);
426         if (ret) {
427                 dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
428                 goto put_master;
429         }
430 
431         dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
432                 (unsigned long long)res->start, xspi->regs, xspi->irq);
433 
434         if (pdata) {
435                 for (i = 0; i < pdata->num_devices; i++)
436                         spi_new_device(master, pdata->devices + i);
437         }
438 
439         platform_set_drvdata(pdev, master);
440         return 0;
441 
442 put_master:
443         spi_master_put(master);
444 
445         return ret;
446 }
447 
448 static int xilinx_spi_remove(struct platform_device *pdev)
449 {
450         struct spi_master *master = platform_get_drvdata(pdev);
451         struct xilinx_spi *xspi = spi_master_get_devdata(master);
452         void __iomem *regs_base = xspi->regs;
453 
454         spi_bitbang_stop(&xspi->bitbang);
455 
456         /* Disable all the interrupts just in case */
457         xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
458         /* Disable the global IPIF interrupt */
459         xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
460 
461         spi_master_put(xspi->bitbang.master);
462 
463         return 0;
464 }
465 
466 /* work with hotplug and coldplug */
467 MODULE_ALIAS("platform:" XILINX_SPI_NAME);
468 
469 static struct platform_driver xilinx_spi_driver = {
470         .probe = xilinx_spi_probe,
471         .remove = xilinx_spi_remove,
472         .driver = {
473                 .name = XILINX_SPI_NAME,
474                 .owner = THIS_MODULE,
475                 .of_match_table = xilinx_spi_of_match,
476         },
477 };
478 module_platform_driver(xilinx_spi_driver);
479 
480 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
481 MODULE_DESCRIPTION("Xilinx SPI driver");
482 MODULE_LICENSE("GPL");
483 

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