Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/spi/spi-txx9.c

  1 /*
  2  * TXx9 SPI controller driver.
  3  *
  4  * Based on linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
  5  * Copyright (C) 2000-2001 Toshiba Corporation
  6  *
  7  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
  8  * terms of the GNU General Public License version 2. This program is
  9  * licensed "as is" without any warranty of any kind, whether express
 10  * or implied.
 11  *
 12  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
 13  *
 14  * Convert to generic SPI framework - Atsushi Nemoto (anemo@mba.ocn.ne.jp)
 15  */
 16 #include <linux/init.h>
 17 #include <linux/delay.h>
 18 #include <linux/errno.h>
 19 #include <linux/interrupt.h>
 20 #include <linux/platform_device.h>
 21 #include <linux/sched.h>
 22 #include <linux/spinlock.h>
 23 #include <linux/workqueue.h>
 24 #include <linux/spi/spi.h>
 25 #include <linux/err.h>
 26 #include <linux/clk.h>
 27 #include <linux/io.h>
 28 #include <linux/module.h>
 29 #include <linux/gpio.h>
 30 
 31 
 32 #define SPI_FIFO_SIZE 4
 33 #define SPI_MAX_DIVIDER 0xff    /* Max. value for SPCR1.SER */
 34 #define SPI_MIN_DIVIDER 1       /* Min. value for SPCR1.SER */
 35 
 36 #define TXx9_SPMCR              0x00
 37 #define TXx9_SPCR0              0x04
 38 #define TXx9_SPCR1              0x08
 39 #define TXx9_SPFS               0x0c
 40 #define TXx9_SPSR               0x14
 41 #define TXx9_SPDR               0x18
 42 
 43 /* SPMCR : SPI Master Control */
 44 #define TXx9_SPMCR_OPMODE       0xc0
 45 #define TXx9_SPMCR_CONFIG       0x40
 46 #define TXx9_SPMCR_ACTIVE       0x80
 47 #define TXx9_SPMCR_SPSTP        0x02
 48 #define TXx9_SPMCR_BCLR         0x01
 49 
 50 /* SPCR0 : SPI Control 0 */
 51 #define TXx9_SPCR0_TXIFL_MASK   0xc000
 52 #define TXx9_SPCR0_RXIFL_MASK   0x3000
 53 #define TXx9_SPCR0_SIDIE        0x0800
 54 #define TXx9_SPCR0_SOEIE        0x0400
 55 #define TXx9_SPCR0_RBSIE        0x0200
 56 #define TXx9_SPCR0_TBSIE        0x0100
 57 #define TXx9_SPCR0_IFSPSE       0x0010
 58 #define TXx9_SPCR0_SBOS         0x0004
 59 #define TXx9_SPCR0_SPHA         0x0002
 60 #define TXx9_SPCR0_SPOL         0x0001
 61 
 62 /* SPSR : SPI Status */
 63 #define TXx9_SPSR_TBSI          0x8000
 64 #define TXx9_SPSR_RBSI          0x4000
 65 #define TXx9_SPSR_TBS_MASK      0x3800
 66 #define TXx9_SPSR_RBS_MASK      0x0700
 67 #define TXx9_SPSR_SPOE          0x0080
 68 #define TXx9_SPSR_IFSD          0x0008
 69 #define TXx9_SPSR_SIDLE         0x0004
 70 #define TXx9_SPSR_STRDY         0x0002
 71 #define TXx9_SPSR_SRRDY         0x0001
 72 
 73 
 74 struct txx9spi {
 75         struct workqueue_struct *workqueue;
 76         struct work_struct work;
 77         spinlock_t lock;        /* protect 'queue' */
 78         struct list_head queue;
 79         wait_queue_head_t waitq;
 80         void __iomem *membase;
 81         int baseclk;
 82         struct clk *clk;
 83         int last_chipselect;
 84         int last_chipselect_val;
 85 };
 86 
 87 static u32 txx9spi_rd(struct txx9spi *c, int reg)
 88 {
 89         return __raw_readl(c->membase + reg);
 90 }
 91 static void txx9spi_wr(struct txx9spi *c, u32 val, int reg)
 92 {
 93         __raw_writel(val, c->membase + reg);
 94 }
 95 
 96 static void txx9spi_cs_func(struct spi_device *spi, struct txx9spi *c,
 97                 int on, unsigned int cs_delay)
 98 {
 99         int val = (spi->mode & SPI_CS_HIGH) ? on : !on;
100         if (on) {
101                 /* deselect the chip with cs_change hint in last transfer */
102                 if (c->last_chipselect >= 0)
103                         gpio_set_value(c->last_chipselect,
104                                         !c->last_chipselect_val);
105                 c->last_chipselect = spi->chip_select;
106                 c->last_chipselect_val = val;
107         } else {
108                 c->last_chipselect = -1;
109                 ndelay(cs_delay);       /* CS Hold Time */
110         }
111         gpio_set_value(spi->chip_select, val);
112         ndelay(cs_delay);       /* CS Setup Time / CS Recovery Time */
113 }
114 
115 static int txx9spi_setup(struct spi_device *spi)
116 {
117         struct txx9spi *c = spi_master_get_devdata(spi->master);
118 
119         if (!spi->max_speed_hz)
120                 return -EINVAL;
121 
122         if (gpio_direction_output(spi->chip_select,
123                         !(spi->mode & SPI_CS_HIGH))) {
124                 dev_err(&spi->dev, "Cannot setup GPIO for chipselect.\n");
125                 return -EINVAL;
126         }
127 
128         /* deselect chip */
129         spin_lock(&c->lock);
130         txx9spi_cs_func(spi, c, 0, (NSEC_PER_SEC / 2) / spi->max_speed_hz);
131         spin_unlock(&c->lock);
132 
133         return 0;
134 }
135 
136 static irqreturn_t txx9spi_interrupt(int irq, void *dev_id)
137 {
138         struct txx9spi *c = dev_id;
139 
140         /* disable rx intr */
141         txx9spi_wr(c, txx9spi_rd(c, TXx9_SPCR0) & ~TXx9_SPCR0_RBSIE,
142                         TXx9_SPCR0);
143         wake_up(&c->waitq);
144         return IRQ_HANDLED;
145 }
146 
147 static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m)
148 {
149         struct spi_device *spi = m->spi;
150         struct spi_transfer *t;
151         unsigned int cs_delay;
152         unsigned int cs_change = 1;
153         int status = 0;
154         u32 mcr;
155         u32 prev_speed_hz = 0;
156         u8 prev_bits_per_word = 0;
157 
158         /* CS setup/hold/recovery time in nsec */
159         cs_delay = 100 + (NSEC_PER_SEC / 2) / spi->max_speed_hz;
160 
161         mcr = txx9spi_rd(c, TXx9_SPMCR);
162         if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) {
163                 dev_err(&spi->dev, "Bad mode.\n");
164                 status = -EIO;
165                 goto exit;
166         }
167         mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
168 
169         /* enter config mode */
170         txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
171         txx9spi_wr(c, TXx9_SPCR0_SBOS
172                         | ((spi->mode & SPI_CPOL) ? TXx9_SPCR0_SPOL : 0)
173                         | ((spi->mode & SPI_CPHA) ? TXx9_SPCR0_SPHA : 0)
174                         | 0x08,
175                         TXx9_SPCR0);
176 
177         list_for_each_entry(t, &m->transfers, transfer_list) {
178                 const void *txbuf = t->tx_buf;
179                 void *rxbuf = t->rx_buf;
180                 u32 data;
181                 unsigned int len = t->len;
182                 unsigned int wsize;
183                 u32 speed_hz = t->speed_hz ? : spi->max_speed_hz;
184                 u8 bits_per_word = t->bits_per_word;
185 
186                 wsize = bits_per_word >> 3; /* in bytes */
187 
188                 if (prev_speed_hz != speed_hz
189                                 || prev_bits_per_word != bits_per_word) {
190                         int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1;
191                         n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER);
192                         /* enter config mode */
193                         txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR,
194                                         TXx9_SPMCR);
195                         txx9spi_wr(c, (n << 8) | bits_per_word, TXx9_SPCR1);
196                         /* enter active mode */
197                         txx9spi_wr(c, mcr | TXx9_SPMCR_ACTIVE, TXx9_SPMCR);
198 
199                         prev_speed_hz = speed_hz;
200                         prev_bits_per_word = bits_per_word;
201                 }
202 
203                 if (cs_change)
204                         txx9spi_cs_func(spi, c, 1, cs_delay);
205                 cs_change = t->cs_change;
206                 while (len) {
207                         unsigned int count = SPI_FIFO_SIZE;
208                         int i;
209                         u32 cr0;
210 
211                         if (len < count * wsize)
212                                 count = len / wsize;
213                         /* now tx must be idle... */
214                         while (!(txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_SIDLE))
215                                 cpu_relax();
216                         cr0 = txx9spi_rd(c, TXx9_SPCR0);
217                         cr0 &= ~TXx9_SPCR0_RXIFL_MASK;
218                         cr0 |= (count - 1) << 12;
219                         /* enable rx intr */
220                         cr0 |= TXx9_SPCR0_RBSIE;
221                         txx9spi_wr(c, cr0, TXx9_SPCR0);
222                         /* send */
223                         for (i = 0; i < count; i++) {
224                                 if (txbuf) {
225                                         data = (wsize == 1)
226                                                 ? *(const u8 *)txbuf
227                                                 : *(const u16 *)txbuf;
228                                         txx9spi_wr(c, data, TXx9_SPDR);
229                                         txbuf += wsize;
230                                 } else
231                                         txx9spi_wr(c, 0, TXx9_SPDR);
232                         }
233                         /* wait all rx data */
234                         wait_event(c->waitq,
235                                 txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_RBSI);
236                         /* receive */
237                         for (i = 0; i < count; i++) {
238                                 data = txx9spi_rd(c, TXx9_SPDR);
239                                 if (rxbuf) {
240                                         if (wsize == 1)
241                                                 *(u8 *)rxbuf = data;
242                                         else
243                                                 *(u16 *)rxbuf = data;
244                                         rxbuf += wsize;
245                                 }
246                         }
247                         len -= count * wsize;
248                 }
249                 m->actual_length += t->len;
250                 if (t->delay_usecs)
251                         udelay(t->delay_usecs);
252 
253                 if (!cs_change)
254                         continue;
255                 if (t->transfer_list.next == &m->transfers)
256                         break;
257                 /* sometimes a short mid-message deselect of the chip
258                  * may be needed to terminate a mode or command
259                  */
260                 txx9spi_cs_func(spi, c, 0, cs_delay);
261         }
262 
263 exit:
264         m->status = status;
265         if (m->complete)
266                 m->complete(m->context);
267 
268         /* normally deactivate chipselect ... unless no error and
269          * cs_change has hinted that the next message will probably
270          * be for this chip too.
271          */
272         if (!(status == 0 && cs_change))
273                 txx9spi_cs_func(spi, c, 0, cs_delay);
274 
275         /* enter config mode */
276         txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
277 }
278 
279 static void txx9spi_work(struct work_struct *work)
280 {
281         struct txx9spi *c = container_of(work, struct txx9spi, work);
282         unsigned long flags;
283 
284         spin_lock_irqsave(&c->lock, flags);
285         while (!list_empty(&c->queue)) {
286                 struct spi_message *m;
287 
288                 m = container_of(c->queue.next, struct spi_message, queue);
289                 list_del_init(&m->queue);
290                 spin_unlock_irqrestore(&c->lock, flags);
291 
292                 txx9spi_work_one(c, m);
293 
294                 spin_lock_irqsave(&c->lock, flags);
295         }
296         spin_unlock_irqrestore(&c->lock, flags);
297 }
298 
299 static int txx9spi_transfer(struct spi_device *spi, struct spi_message *m)
300 {
301         struct spi_master *master = spi->master;
302         struct txx9spi *c = spi_master_get_devdata(master);
303         struct spi_transfer *t;
304         unsigned long flags;
305 
306         m->actual_length = 0;
307 
308         /* check each transfer's parameters */
309         list_for_each_entry(t, &m->transfers, transfer_list) {
310                 if (!t->tx_buf && !t->rx_buf && t->len)
311                         return -EINVAL;
312         }
313 
314         spin_lock_irqsave(&c->lock, flags);
315         list_add_tail(&m->queue, &c->queue);
316         queue_work(c->workqueue, &c->work);
317         spin_unlock_irqrestore(&c->lock, flags);
318 
319         return 0;
320 }
321 
322 static int txx9spi_probe(struct platform_device *dev)
323 {
324         struct spi_master *master;
325         struct txx9spi *c;
326         struct resource *res;
327         int ret = -ENODEV;
328         u32 mcr;
329         int irq;
330 
331         master = spi_alloc_master(&dev->dev, sizeof(*c));
332         if (!master)
333                 return ret;
334         c = spi_master_get_devdata(master);
335         platform_set_drvdata(dev, master);
336 
337         INIT_WORK(&c->work, txx9spi_work);
338         spin_lock_init(&c->lock);
339         INIT_LIST_HEAD(&c->queue);
340         init_waitqueue_head(&c->waitq);
341 
342         c->clk = devm_clk_get(&dev->dev, "spi-baseclk");
343         if (IS_ERR(c->clk)) {
344                 ret = PTR_ERR(c->clk);
345                 c->clk = NULL;
346                 goto exit;
347         }
348         ret = clk_enable(c->clk);
349         if (ret) {
350                 c->clk = NULL;
351                 goto exit;
352         }
353         c->baseclk = clk_get_rate(c->clk);
354         master->min_speed_hz = DIV_ROUND_UP(c->baseclk, SPI_MAX_DIVIDER + 1);
355         master->max_speed_hz = c->baseclk / (SPI_MIN_DIVIDER + 1);
356 
357         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
358         c->membase = devm_ioremap_resource(&dev->dev, res);
359         if (IS_ERR(c->membase))
360                 goto exit_busy;
361 
362         /* enter config mode */
363         mcr = txx9spi_rd(c, TXx9_SPMCR);
364         mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
365         txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
366 
367         irq = platform_get_irq(dev, 0);
368         if (irq < 0)
369                 goto exit_busy;
370         ret = devm_request_irq(&dev->dev, irq, txx9spi_interrupt, 0,
371                                "spi_txx9", c);
372         if (ret)
373                 goto exit;
374 
375         c->workqueue = create_singlethread_workqueue(
376                                 dev_name(master->dev.parent));
377         if (!c->workqueue)
378                 goto exit_busy;
379         c->last_chipselect = -1;
380 
381         dev_info(&dev->dev, "at %#llx, irq %d, %dMHz\n",
382                  (unsigned long long)res->start, irq,
383                  (c->baseclk + 500000) / 1000000);
384 
385         /* the spi->mode bits understood by this driver: */
386         master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
387 
388         master->bus_num = dev->id;
389         master->setup = txx9spi_setup;
390         master->transfer = txx9spi_transfer;
391         master->num_chipselect = (u16)UINT_MAX; /* any GPIO numbers */
392         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
393 
394         ret = devm_spi_register_master(&dev->dev, master);
395         if (ret)
396                 goto exit;
397         return 0;
398 exit_busy:
399         ret = -EBUSY;
400 exit:
401         if (c->workqueue)
402                 destroy_workqueue(c->workqueue);
403         if (c->clk)
404                 clk_disable(c->clk);
405         spi_master_put(master);
406         return ret;
407 }
408 
409 static int txx9spi_remove(struct platform_device *dev)
410 {
411         struct spi_master *master = platform_get_drvdata(dev);
412         struct txx9spi *c = spi_master_get_devdata(master);
413 
414         destroy_workqueue(c->workqueue);
415         clk_disable(c->clk);
416         return 0;
417 }
418 
419 /* work with hotplug and coldplug */
420 MODULE_ALIAS("platform:spi_txx9");
421 
422 static struct platform_driver txx9spi_driver = {
423         .probe = txx9spi_probe,
424         .remove = txx9spi_remove,
425         .driver = {
426                 .name = "spi_txx9",
427                 .owner = THIS_MODULE,
428         },
429 };
430 
431 static int __init txx9spi_init(void)
432 {
433         return platform_driver_register(&txx9spi_driver);
434 }
435 subsys_initcall(txx9spi_init);
436 
437 static void __exit txx9spi_exit(void)
438 {
439         platform_driver_unregister(&txx9spi_driver);
440 }
441 module_exit(txx9spi_exit);
442 
443 MODULE_DESCRIPTION("TXx9 SPI Driver");
444 MODULE_LICENSE("GPL");
445 

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