Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/drivers/spi/spi-topcliff-pch.c

  1 /*
  2  * SPI bus driver for the Topcliff PCH used by Intel SoCs
  3  *
  4  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation; version 2 of the License.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  */
 15 
 16 #include <linux/delay.h>
 17 #include <linux/pci.h>
 18 #include <linux/wait.h>
 19 #include <linux/spi/spi.h>
 20 #include <linux/interrupt.h>
 21 #include <linux/sched.h>
 22 #include <linux/spi/spidev.h>
 23 #include <linux/module.h>
 24 #include <linux/device.h>
 25 #include <linux/platform_device.h>
 26 
 27 #include <linux/dmaengine.h>
 28 #include <linux/pch_dma.h>
 29 
 30 /* Register offsets */
 31 #define PCH_SPCR                0x00    /* SPI control register */
 32 #define PCH_SPBRR               0x04    /* SPI baud rate register */
 33 #define PCH_SPSR                0x08    /* SPI status register */
 34 #define PCH_SPDWR               0x0C    /* SPI write data register */
 35 #define PCH_SPDRR               0x10    /* SPI read data register */
 36 #define PCH_SSNXCR              0x18    /* SSN Expand Control Register */
 37 #define PCH_SRST                0x1C    /* SPI reset register */
 38 #define PCH_ADDRESS_SIZE        0x20
 39 
 40 #define PCH_SPSR_TFD            0x000007C0
 41 #define PCH_SPSR_RFD            0x0000F800
 42 
 43 #define PCH_READABLE(x)         (((x) & PCH_SPSR_RFD)>>11)
 44 #define PCH_WRITABLE(x)         (((x) & PCH_SPSR_TFD)>>6)
 45 
 46 #define PCH_RX_THOLD            7
 47 #define PCH_RX_THOLD_MAX        15
 48 
 49 #define PCH_TX_THOLD            2
 50 
 51 #define PCH_MAX_BAUDRATE        5000000
 52 #define PCH_MAX_FIFO_DEPTH      16
 53 
 54 #define STATUS_RUNNING          1
 55 #define STATUS_EXITING          2
 56 #define PCH_SLEEP_TIME          10
 57 
 58 #define SSN_LOW                 0x02U
 59 #define SSN_HIGH                0x03U
 60 #define SSN_NO_CONTROL          0x00U
 61 #define PCH_MAX_CS              0xFF
 62 #define PCI_DEVICE_ID_GE_SPI    0x8816
 63 
 64 #define SPCR_SPE_BIT            (1 << 0)
 65 #define SPCR_MSTR_BIT           (1 << 1)
 66 #define SPCR_LSBF_BIT           (1 << 4)
 67 #define SPCR_CPHA_BIT           (1 << 5)
 68 #define SPCR_CPOL_BIT           (1 << 6)
 69 #define SPCR_TFIE_BIT           (1 << 8)
 70 #define SPCR_RFIE_BIT           (1 << 9)
 71 #define SPCR_FIE_BIT            (1 << 10)
 72 #define SPCR_ORIE_BIT           (1 << 11)
 73 #define SPCR_MDFIE_BIT          (1 << 12)
 74 #define SPCR_FICLR_BIT          (1 << 24)
 75 #define SPSR_TFI_BIT            (1 << 0)
 76 #define SPSR_RFI_BIT            (1 << 1)
 77 #define SPSR_FI_BIT             (1 << 2)
 78 #define SPSR_ORF_BIT            (1 << 3)
 79 #define SPBRR_SIZE_BIT          (1 << 10)
 80 
 81 #define PCH_ALL                 (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
 82                                 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
 83 
 84 #define SPCR_RFIC_FIELD         20
 85 #define SPCR_TFIC_FIELD         16
 86 
 87 #define MASK_SPBRR_SPBR_BITS    ((1 << 10) - 1)
 88 #define MASK_RFIC_SPCR_BITS     (0xf << SPCR_RFIC_FIELD)
 89 #define MASK_TFIC_SPCR_BITS     (0xf << SPCR_TFIC_FIELD)
 90 
 91 #define PCH_CLOCK_HZ            50000000
 92 #define PCH_MAX_SPBR            1023
 93 
 94 /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
 95 #define PCI_VENDOR_ID_ROHM              0x10DB
 96 #define PCI_DEVICE_ID_ML7213_SPI        0x802c
 97 #define PCI_DEVICE_ID_ML7223_SPI        0x800F
 98 #define PCI_DEVICE_ID_ML7831_SPI        0x8816
 99 
100 /*
101  * Set the number of SPI instance max
102  * Intel EG20T PCH :            1ch
103  * LAPIS Semiconductor ML7213 IOH :     2ch
104  * LAPIS Semiconductor ML7223 IOH :     1ch
105  * LAPIS Semiconductor ML7831 IOH :     1ch
106 */
107 #define PCH_SPI_MAX_DEV                 2
108 
109 #define PCH_BUF_SIZE            4096
110 #define PCH_DMA_TRANS_SIZE      12
111 
112 static int use_dma = 1;
113 
114 struct pch_spi_dma_ctrl {
115         struct dma_async_tx_descriptor  *desc_tx;
116         struct dma_async_tx_descriptor  *desc_rx;
117         struct pch_dma_slave            param_tx;
118         struct pch_dma_slave            param_rx;
119         struct dma_chan         *chan_tx;
120         struct dma_chan         *chan_rx;
121         struct scatterlist              *sg_tx_p;
122         struct scatterlist              *sg_rx_p;
123         struct scatterlist              sg_tx;
124         struct scatterlist              sg_rx;
125         int                             nent;
126         void                            *tx_buf_virt;
127         void                            *rx_buf_virt;
128         dma_addr_t                      tx_buf_dma;
129         dma_addr_t                      rx_buf_dma;
130 };
131 /**
132  * struct pch_spi_data - Holds the SPI channel specific details
133  * @io_remap_addr:              The remapped PCI base address
134  * @master:                     Pointer to the SPI master structure
135  * @work:                       Reference to work queue handler
136  * @wait:                       Wait queue for waking up upon receiving an
137  *                              interrupt.
138  * @transfer_complete:          Status of SPI Transfer
139  * @bcurrent_msg_processing:    Status flag for message processing
140  * @lock:                       Lock for protecting this structure
141  * @queue:                      SPI Message queue
142  * @status:                     Status of the SPI driver
143  * @bpw_len:                    Length of data to be transferred in bits per
144  *                              word
145  * @transfer_active:            Flag showing active transfer
146  * @tx_index:                   Transmit data count; for bookkeeping during
147  *                              transfer
148  * @rx_index:                   Receive data count; for bookkeeping during
149  *                              transfer
150  * @tx_buff:                    Buffer for data to be transmitted
151  * @rx_index:                   Buffer for Received data
152  * @n_curnt_chip:               The chip number that this SPI driver currently
153  *                              operates on
154  * @current_chip:               Reference to the current chip that this SPI
155  *                              driver currently operates on
156  * @current_msg:                The current message that this SPI driver is
157  *                              handling
158  * @cur_trans:                  The current transfer that this SPI driver is
159  *                              handling
160  * @board_dat:                  Reference to the SPI device data structure
161  * @plat_dev:                   platform_device structure
162  * @ch:                         SPI channel number
163  * @irq_reg_sts:                Status of IRQ registration
164  */
165 struct pch_spi_data {
166         void __iomem *io_remap_addr;
167         unsigned long io_base_addr;
168         struct spi_master *master;
169         struct work_struct work;
170         wait_queue_head_t wait;
171         u8 transfer_complete;
172         u8 bcurrent_msg_processing;
173         spinlock_t lock;
174         struct list_head queue;
175         u8 status;
176         u32 bpw_len;
177         u8 transfer_active;
178         u32 tx_index;
179         u32 rx_index;
180         u16 *pkt_tx_buff;
181         u16 *pkt_rx_buff;
182         u8 n_curnt_chip;
183         struct spi_device *current_chip;
184         struct spi_message *current_msg;
185         struct spi_transfer *cur_trans;
186         struct pch_spi_board_data *board_dat;
187         struct platform_device  *plat_dev;
188         int ch;
189         struct pch_spi_dma_ctrl dma;
190         int use_dma;
191         u8 irq_reg_sts;
192         int save_total_len;
193 };
194 
195 /**
196  * struct pch_spi_board_data - Holds the SPI device specific details
197  * @pdev:               Pointer to the PCI device
198  * @suspend_sts:        Status of suspend
199  * @num:                The number of SPI device instance
200  */
201 struct pch_spi_board_data {
202         struct pci_dev *pdev;
203         u8 suspend_sts;
204         int num;
205 };
206 
207 struct pch_pd_dev_save {
208         int num;
209         struct platform_device *pd_save[PCH_SPI_MAX_DEV];
210         struct pch_spi_board_data *board_dat;
211 };
212 
213 static const struct pci_device_id pch_spi_pcidev_id[] = {
214         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI),    1, },
215         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
216         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
217         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, },
218         { }
219 };
220 
221 /**
222  * pch_spi_writereg() - Performs  register writes
223  * @master:     Pointer to struct spi_master.
224  * @idx:        Register offset.
225  * @val:        Value to be written to register.
226  */
227 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
228 {
229         struct pch_spi_data *data = spi_master_get_devdata(master);
230         iowrite32(val, (data->io_remap_addr + idx));
231 }
232 
233 /**
234  * pch_spi_readreg() - Performs register reads
235  * @master:     Pointer to struct spi_master.
236  * @idx:        Register offset.
237  */
238 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
239 {
240         struct pch_spi_data *data = spi_master_get_devdata(master);
241         return ioread32(data->io_remap_addr + idx);
242 }
243 
244 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
245                                       u32 set, u32 clr)
246 {
247         u32 tmp = pch_spi_readreg(master, idx);
248         tmp = (tmp & ~clr) | set;
249         pch_spi_writereg(master, idx, tmp);
250 }
251 
252 static void pch_spi_set_master_mode(struct spi_master *master)
253 {
254         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
255 }
256 
257 /**
258  * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
259  * @master:     Pointer to struct spi_master.
260  */
261 static void pch_spi_clear_fifo(struct spi_master *master)
262 {
263         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
264         pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
265 }
266 
267 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
268                                 void __iomem *io_remap_addr)
269 {
270         u32 n_read, tx_index, rx_index, bpw_len;
271         u16 *pkt_rx_buffer, *pkt_tx_buff;
272         int read_cnt;
273         u32 reg_spcr_val;
274         void __iomem *spsr;
275         void __iomem *spdrr;
276         void __iomem *spdwr;
277 
278         spsr = io_remap_addr + PCH_SPSR;
279         iowrite32(reg_spsr_val, spsr);
280 
281         if (data->transfer_active) {
282                 rx_index = data->rx_index;
283                 tx_index = data->tx_index;
284                 bpw_len = data->bpw_len;
285                 pkt_rx_buffer = data->pkt_rx_buff;
286                 pkt_tx_buff = data->pkt_tx_buff;
287 
288                 spdrr = io_remap_addr + PCH_SPDRR;
289                 spdwr = io_remap_addr + PCH_SPDWR;
290 
291                 n_read = PCH_READABLE(reg_spsr_val);
292 
293                 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
294                         pkt_rx_buffer[rx_index++] = ioread32(spdrr);
295                         if (tx_index < bpw_len)
296                                 iowrite32(pkt_tx_buff[tx_index++], spdwr);
297                 }
298 
299                 /* disable RFI if not needed */
300                 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
301                         reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
302                         reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
303 
304                         /* reset rx threshold */
305                         reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
306                         reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
307 
308                         iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
309                 }
310 
311                 /* update counts */
312                 data->tx_index = tx_index;
313                 data->rx_index = rx_index;
314 
315                 /* if transfer complete interrupt */
316                 if (reg_spsr_val & SPSR_FI_BIT) {
317                         if ((tx_index == bpw_len) && (rx_index == tx_index)) {
318                                 /* disable interrupts */
319                                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
320                                                    PCH_ALL);
321 
322                                 /* transfer is completed;
323                                    inform pch_spi_process_messages */
324                                 data->transfer_complete = true;
325                                 data->transfer_active = false;
326                                 wake_up(&data->wait);
327                         } else {
328                                 dev_vdbg(&data->master->dev,
329                                         "%s : Transfer is not completed",
330                                         __func__);
331                         }
332                 }
333         }
334 }
335 
336 /**
337  * pch_spi_handler() - Interrupt handler
338  * @irq:        The interrupt number.
339  * @dev_id:     Pointer to struct pch_spi_board_data.
340  */
341 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
342 {
343         u32 reg_spsr_val;
344         void __iomem *spsr;
345         void __iomem *io_remap_addr;
346         irqreturn_t ret = IRQ_NONE;
347         struct pch_spi_data *data = dev_id;
348         struct pch_spi_board_data *board_dat = data->board_dat;
349 
350         if (board_dat->suspend_sts) {
351                 dev_dbg(&board_dat->pdev->dev,
352                         "%s returning due to suspend\n", __func__);
353                 return IRQ_NONE;
354         }
355 
356         io_remap_addr = data->io_remap_addr;
357         spsr = io_remap_addr + PCH_SPSR;
358 
359         reg_spsr_val = ioread32(spsr);
360 
361         if (reg_spsr_val & SPSR_ORF_BIT) {
362                 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
363                 if (data->current_msg->complete) {
364                         data->transfer_complete = true;
365                         data->current_msg->status = -EIO;
366                         data->current_msg->complete(data->current_msg->context);
367                         data->bcurrent_msg_processing = false;
368                         data->current_msg = NULL;
369                         data->cur_trans = NULL;
370                 }
371         }
372 
373         if (data->use_dma)
374                 return IRQ_NONE;
375 
376         /* Check if the interrupt is for SPI device */
377         if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
378                 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
379                 ret = IRQ_HANDLED;
380         }
381 
382         dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
383                 __func__, ret);
384 
385         return ret;
386 }
387 
388 /**
389  * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
390  * @master:     Pointer to struct spi_master.
391  * @speed_hz:   Baud rate.
392  */
393 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
394 {
395         u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
396 
397         /* if baud rate is less than we can support limit it */
398         if (n_spbr > PCH_MAX_SPBR)
399                 n_spbr = PCH_MAX_SPBR;
400 
401         pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
402 }
403 
404 /**
405  * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
406  * @master:             Pointer to struct spi_master.
407  * @bits_per_word:      Bits per word for SPI transfer.
408  */
409 static void pch_spi_set_bits_per_word(struct spi_master *master,
410                                       u8 bits_per_word)
411 {
412         if (bits_per_word == 8)
413                 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
414         else
415                 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
416 }
417 
418 /**
419  * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
420  * @spi:        Pointer to struct spi_device.
421  */
422 static void pch_spi_setup_transfer(struct spi_device *spi)
423 {
424         u32 flags = 0;
425 
426         dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
427                 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
428                 spi->max_speed_hz);
429         pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
430 
431         /* set bits per word */
432         pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
433 
434         if (!(spi->mode & SPI_LSB_FIRST))
435                 flags |= SPCR_LSBF_BIT;
436         if (spi->mode & SPI_CPOL)
437                 flags |= SPCR_CPOL_BIT;
438         if (spi->mode & SPI_CPHA)
439                 flags |= SPCR_CPHA_BIT;
440         pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
441                            (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
442 
443         /* Clear the FIFO by toggling  FICLR to 1 and back to 0 */
444         pch_spi_clear_fifo(spi->master);
445 }
446 
447 /**
448  * pch_spi_reset() - Clears SPI registers
449  * @master:     Pointer to struct spi_master.
450  */
451 static void pch_spi_reset(struct spi_master *master)
452 {
453         /* write 1 to reset SPI */
454         pch_spi_writereg(master, PCH_SRST, 0x1);
455 
456         /* clear reset */
457         pch_spi_writereg(master, PCH_SRST, 0x0);
458 }
459 
460 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
461 {
462 
463         struct spi_transfer *transfer;
464         struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
465         int retval;
466         unsigned long flags;
467 
468         spin_lock_irqsave(&data->lock, flags);
469         /* validate Tx/Rx buffers and Transfer length */
470         list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
471                 if (!transfer->tx_buf && !transfer->rx_buf) {
472                         dev_err(&pspi->dev,
473                                 "%s Tx and Rx buffer NULL\n", __func__);
474                         retval = -EINVAL;
475                         goto err_return_spinlock;
476                 }
477 
478                 if (!transfer->len) {
479                         dev_err(&pspi->dev, "%s Transfer length invalid\n",
480                                 __func__);
481                         retval = -EINVAL;
482                         goto err_return_spinlock;
483                 }
484 
485                 dev_dbg(&pspi->dev,
486                         "%s Tx/Rx buffer valid. Transfer length valid\n",
487                         __func__);
488         }
489         spin_unlock_irqrestore(&data->lock, flags);
490 
491         /* We won't process any messages if we have been asked to terminate */
492         if (data->status == STATUS_EXITING) {
493                 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
494                 retval = -ESHUTDOWN;
495                 goto err_out;
496         }
497 
498         /* If suspended ,return -EINVAL */
499         if (data->board_dat->suspend_sts) {
500                 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
501                 retval = -EINVAL;
502                 goto err_out;
503         }
504 
505         /* set status of message */
506         pmsg->actual_length = 0;
507         dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
508 
509         pmsg->status = -EINPROGRESS;
510         spin_lock_irqsave(&data->lock, flags);
511         /* add message to queue */
512         list_add_tail(&pmsg->queue, &data->queue);
513         spin_unlock_irqrestore(&data->lock, flags);
514 
515         dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
516 
517         schedule_work(&data->work);
518         dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
519 
520         retval = 0;
521 
522 err_out:
523         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
524         return retval;
525 err_return_spinlock:
526         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
527         spin_unlock_irqrestore(&data->lock, flags);
528         return retval;
529 }
530 
531 static inline void pch_spi_select_chip(struct pch_spi_data *data,
532                                        struct spi_device *pspi)
533 {
534         if (data->current_chip != NULL) {
535                 if (pspi->chip_select != data->n_curnt_chip) {
536                         dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
537                         data->current_chip = NULL;
538                 }
539         }
540 
541         data->current_chip = pspi;
542 
543         data->n_curnt_chip = data->current_chip->chip_select;
544 
545         dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
546         pch_spi_setup_transfer(pspi);
547 }
548 
549 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
550 {
551         int size;
552         u32 n_writes;
553         int j;
554         struct spi_message *pmsg, *tmp;
555         const u8 *tx_buf;
556         const u16 *tx_sbuf;
557 
558         /* set baud rate if needed */
559         if (data->cur_trans->speed_hz) {
560                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
561                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
562         }
563 
564         /* set bits per word if needed */
565         if (data->cur_trans->bits_per_word &&
566             (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
567                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
568                 pch_spi_set_bits_per_word(data->master,
569                                           data->cur_trans->bits_per_word);
570                 *bpw = data->cur_trans->bits_per_word;
571         } else {
572                 *bpw = data->current_msg->spi->bits_per_word;
573         }
574 
575         /* reset Tx/Rx index */
576         data->tx_index = 0;
577         data->rx_index = 0;
578 
579         data->bpw_len = data->cur_trans->len / (*bpw / 8);
580 
581         /* find alloc size */
582         size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
583 
584         /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
585         data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
586         if (data->pkt_tx_buff != NULL) {
587                 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
588                 if (!data->pkt_rx_buff)
589                         kfree(data->pkt_tx_buff);
590         }
591 
592         if (!data->pkt_rx_buff) {
593                 /* flush queue and set status of all transfers to -ENOMEM */
594                 dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__);
595                 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
596                         pmsg->status = -ENOMEM;
597 
598                         if (pmsg->complete)
599                                 pmsg->complete(pmsg->context);
600 
601                         /* delete from queue */
602                         list_del_init(&pmsg->queue);
603                 }
604                 return;
605         }
606 
607         /* copy Tx Data */
608         if (data->cur_trans->tx_buf != NULL) {
609                 if (*bpw == 8) {
610                         tx_buf = data->cur_trans->tx_buf;
611                         for (j = 0; j < data->bpw_len; j++)
612                                 data->pkt_tx_buff[j] = *tx_buf++;
613                 } else {
614                         tx_sbuf = data->cur_trans->tx_buf;
615                         for (j = 0; j < data->bpw_len; j++)
616                                 data->pkt_tx_buff[j] = *tx_sbuf++;
617                 }
618         }
619 
620         /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
621         n_writes = data->bpw_len;
622         if (n_writes > PCH_MAX_FIFO_DEPTH)
623                 n_writes = PCH_MAX_FIFO_DEPTH;
624 
625         dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
626                 "0x2 to SSNXCR\n", __func__);
627         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
628 
629         for (j = 0; j < n_writes; j++)
630                 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
631 
632         /* update tx_index */
633         data->tx_index = j;
634 
635         /* reset transfer complete flag */
636         data->transfer_complete = false;
637         data->transfer_active = true;
638 }
639 
640 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
641 {
642         struct spi_message *pmsg, *tmp;
643         dev_dbg(&data->master->dev, "%s called\n", __func__);
644         /* Invoke complete callback
645          * [To the spi core..indicating end of transfer] */
646         data->current_msg->status = 0;
647 
648         if (data->current_msg->complete) {
649                 dev_dbg(&data->master->dev,
650                         "%s:Invoking callback of SPI core\n", __func__);
651                 data->current_msg->complete(data->current_msg->context);
652         }
653 
654         /* update status in global variable */
655         data->bcurrent_msg_processing = false;
656 
657         dev_dbg(&data->master->dev,
658                 "%s:data->bcurrent_msg_processing = false\n", __func__);
659 
660         data->current_msg = NULL;
661         data->cur_trans = NULL;
662 
663         /* check if we have items in list and not suspending
664          * return 1 if list empty */
665         if ((list_empty(&data->queue) == 0) &&
666             (!data->board_dat->suspend_sts) &&
667             (data->status != STATUS_EXITING)) {
668                 /* We have some more work to do (either there is more tranint
669                  * bpw;sfer requests in the current message or there are
670                  *more messages)
671                  */
672                 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
673                 schedule_work(&data->work);
674         } else if (data->board_dat->suspend_sts ||
675                    data->status == STATUS_EXITING) {
676                 dev_dbg(&data->master->dev,
677                         "%s suspend/remove initiated, flushing queue\n",
678                         __func__);
679                 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
680                         pmsg->status = -EIO;
681 
682                         if (pmsg->complete)
683                                 pmsg->complete(pmsg->context);
684 
685                         /* delete from queue */
686                         list_del_init(&pmsg->queue);
687                 }
688         }
689 }
690 
691 static void pch_spi_set_ir(struct pch_spi_data *data)
692 {
693         /* enable interrupts, set threshold, enable SPI */
694         if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
695                 /* set receive threshold to PCH_RX_THOLD */
696                 pch_spi_setclr_reg(data->master, PCH_SPCR,
697                                    PCH_RX_THOLD << SPCR_RFIC_FIELD |
698                                    SPCR_FIE_BIT | SPCR_RFIE_BIT |
699                                    SPCR_ORIE_BIT | SPCR_SPE_BIT,
700                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
701         else
702                 /* set receive threshold to maximum */
703                 pch_spi_setclr_reg(data->master, PCH_SPCR,
704                                    PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
705                                    SPCR_FIE_BIT | SPCR_ORIE_BIT |
706                                    SPCR_SPE_BIT,
707                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
708 
709         /* Wait until the transfer completes; go to sleep after
710                                  initiating the transfer. */
711         dev_dbg(&data->master->dev,
712                 "%s:waiting for transfer to get over\n", __func__);
713 
714         wait_event_interruptible(data->wait, data->transfer_complete);
715 
716         /* clear all interrupts */
717         pch_spi_writereg(data->master, PCH_SPSR,
718                          pch_spi_readreg(data->master, PCH_SPSR));
719         /* Disable interrupts and SPI transfer */
720         pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
721         /* clear FIFO */
722         pch_spi_clear_fifo(data->master);
723 }
724 
725 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
726 {
727         int j;
728         u8 *rx_buf;
729         u16 *rx_sbuf;
730 
731         /* copy Rx Data */
732         if (!data->cur_trans->rx_buf)
733                 return;
734 
735         if (bpw == 8) {
736                 rx_buf = data->cur_trans->rx_buf;
737                 for (j = 0; j < data->bpw_len; j++)
738                         *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
739         } else {
740                 rx_sbuf = data->cur_trans->rx_buf;
741                 for (j = 0; j < data->bpw_len; j++)
742                         *rx_sbuf++ = data->pkt_rx_buff[j];
743         }
744 }
745 
746 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
747 {
748         int j;
749         u8 *rx_buf;
750         u16 *rx_sbuf;
751         const u8 *rx_dma_buf;
752         const u16 *rx_dma_sbuf;
753 
754         /* copy Rx Data */
755         if (!data->cur_trans->rx_buf)
756                 return;
757 
758         if (bpw == 8) {
759                 rx_buf = data->cur_trans->rx_buf;
760                 rx_dma_buf = data->dma.rx_buf_virt;
761                 for (j = 0; j < data->bpw_len; j++)
762                         *rx_buf++ = *rx_dma_buf++ & 0xFF;
763                 data->cur_trans->rx_buf = rx_buf;
764         } else {
765                 rx_sbuf = data->cur_trans->rx_buf;
766                 rx_dma_sbuf = data->dma.rx_buf_virt;
767                 for (j = 0; j < data->bpw_len; j++)
768                         *rx_sbuf++ = *rx_dma_sbuf++;
769                 data->cur_trans->rx_buf = rx_sbuf;
770         }
771 }
772 
773 static int pch_spi_start_transfer(struct pch_spi_data *data)
774 {
775         struct pch_spi_dma_ctrl *dma;
776         unsigned long flags;
777         int rtn;
778 
779         dma = &data->dma;
780 
781         spin_lock_irqsave(&data->lock, flags);
782 
783         /* disable interrupts, SPI set enable */
784         pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
785 
786         spin_unlock_irqrestore(&data->lock, flags);
787 
788         /* Wait until the transfer completes; go to sleep after
789                                  initiating the transfer. */
790         dev_dbg(&data->master->dev,
791                 "%s:waiting for transfer to get over\n", __func__);
792         rtn = wait_event_interruptible_timeout(data->wait,
793                                                data->transfer_complete,
794                                                msecs_to_jiffies(2 * HZ));
795         if (!rtn)
796                 dev_err(&data->master->dev,
797                         "%s wait-event timeout\n", __func__);
798 
799         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
800                             DMA_FROM_DEVICE);
801 
802         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
803                             DMA_FROM_DEVICE);
804         memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
805 
806         async_tx_ack(dma->desc_rx);
807         async_tx_ack(dma->desc_tx);
808         kfree(dma->sg_tx_p);
809         kfree(dma->sg_rx_p);
810 
811         spin_lock_irqsave(&data->lock, flags);
812 
813         /* clear fifo threshold, disable interrupts, disable SPI transfer */
814         pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
815                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
816                            SPCR_SPE_BIT);
817         /* clear all interrupts */
818         pch_spi_writereg(data->master, PCH_SPSR,
819                          pch_spi_readreg(data->master, PCH_SPSR));
820         /* clear FIFO */
821         pch_spi_clear_fifo(data->master);
822 
823         spin_unlock_irqrestore(&data->lock, flags);
824 
825         return rtn;
826 }
827 
828 static void pch_dma_rx_complete(void *arg)
829 {
830         struct pch_spi_data *data = arg;
831 
832         /* transfer is completed;inform pch_spi_process_messages_dma */
833         data->transfer_complete = true;
834         wake_up_interruptible(&data->wait);
835 }
836 
837 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
838 {
839         struct pch_dma_slave *param = slave;
840 
841         if ((chan->chan_id == param->chan_id) &&
842             (param->dma_dev == chan->device->dev)) {
843                 chan->private = param;
844                 return true;
845         } else {
846                 return false;
847         }
848 }
849 
850 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
851 {
852         dma_cap_mask_t mask;
853         struct dma_chan *chan;
854         struct pci_dev *dma_dev;
855         struct pch_dma_slave *param;
856         struct pch_spi_dma_ctrl *dma;
857         unsigned int width;
858 
859         if (bpw == 8)
860                 width = PCH_DMA_WIDTH_1_BYTE;
861         else
862                 width = PCH_DMA_WIDTH_2_BYTES;
863 
864         dma = &data->dma;
865         dma_cap_zero(mask);
866         dma_cap_set(DMA_SLAVE, mask);
867 
868         /* Get DMA's dev information */
869         dma_dev = pci_get_slot(data->board_dat->pdev->bus,
870                         PCI_DEVFN(PCI_SLOT(data->board_dat->pdev->devfn), 0));
871 
872         /* Set Tx DMA */
873         param = &dma->param_tx;
874         param->dma_dev = &dma_dev->dev;
875         param->chan_id = data->ch * 2; /* Tx = 0, 2 */;
876         param->tx_reg = data->io_base_addr + PCH_SPDWR;
877         param->width = width;
878         chan = dma_request_channel(mask, pch_spi_filter, param);
879         if (!chan) {
880                 dev_err(&data->master->dev,
881                         "ERROR: dma_request_channel FAILS(Tx)\n");
882                 data->use_dma = 0;
883                 return;
884         }
885         dma->chan_tx = chan;
886 
887         /* Set Rx DMA */
888         param = &dma->param_rx;
889         param->dma_dev = &dma_dev->dev;
890         param->chan_id = data->ch * 2 + 1; /* Rx = Tx + 1 */;
891         param->rx_reg = data->io_base_addr + PCH_SPDRR;
892         param->width = width;
893         chan = dma_request_channel(mask, pch_spi_filter, param);
894         if (!chan) {
895                 dev_err(&data->master->dev,
896                         "ERROR: dma_request_channel FAILS(Rx)\n");
897                 dma_release_channel(dma->chan_tx);
898                 dma->chan_tx = NULL;
899                 data->use_dma = 0;
900                 return;
901         }
902         dma->chan_rx = chan;
903 }
904 
905 static void pch_spi_release_dma(struct pch_spi_data *data)
906 {
907         struct pch_spi_dma_ctrl *dma;
908 
909         dma = &data->dma;
910         if (dma->chan_tx) {
911                 dma_release_channel(dma->chan_tx);
912                 dma->chan_tx = NULL;
913         }
914         if (dma->chan_rx) {
915                 dma_release_channel(dma->chan_rx);
916                 dma->chan_rx = NULL;
917         }
918         return;
919 }
920 
921 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
922 {
923         const u8 *tx_buf;
924         const u16 *tx_sbuf;
925         u8 *tx_dma_buf;
926         u16 *tx_dma_sbuf;
927         struct scatterlist *sg;
928         struct dma_async_tx_descriptor *desc_tx;
929         struct dma_async_tx_descriptor *desc_rx;
930         int num;
931         int i;
932         int size;
933         int rem;
934         int head;
935         unsigned long flags;
936         struct pch_spi_dma_ctrl *dma;
937 
938         dma = &data->dma;
939 
940         /* set baud rate if needed */
941         if (data->cur_trans->speed_hz) {
942                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
943                 spin_lock_irqsave(&data->lock, flags);
944                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
945                 spin_unlock_irqrestore(&data->lock, flags);
946         }
947 
948         /* set bits per word if needed */
949         if (data->cur_trans->bits_per_word &&
950             (data->current_msg->spi->bits_per_word !=
951              data->cur_trans->bits_per_word)) {
952                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
953                 spin_lock_irqsave(&data->lock, flags);
954                 pch_spi_set_bits_per_word(data->master,
955                                           data->cur_trans->bits_per_word);
956                 spin_unlock_irqrestore(&data->lock, flags);
957                 *bpw = data->cur_trans->bits_per_word;
958         } else {
959                 *bpw = data->current_msg->spi->bits_per_word;
960         }
961         data->bpw_len = data->cur_trans->len / (*bpw / 8);
962 
963         if (data->bpw_len > PCH_BUF_SIZE) {
964                 data->bpw_len = PCH_BUF_SIZE;
965                 data->cur_trans->len -= PCH_BUF_SIZE;
966         }
967 
968         /* copy Tx Data */
969         if (data->cur_trans->tx_buf != NULL) {
970                 if (*bpw == 8) {
971                         tx_buf = data->cur_trans->tx_buf;
972                         tx_dma_buf = dma->tx_buf_virt;
973                         for (i = 0; i < data->bpw_len; i++)
974                                 *tx_dma_buf++ = *tx_buf++;
975                 } else {
976                         tx_sbuf = data->cur_trans->tx_buf;
977                         tx_dma_sbuf = dma->tx_buf_virt;
978                         for (i = 0; i < data->bpw_len; i++)
979                                 *tx_dma_sbuf++ = *tx_sbuf++;
980                 }
981         }
982 
983         /* Calculate Rx parameter for DMA transmitting */
984         if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
985                 if (data->bpw_len % PCH_DMA_TRANS_SIZE) {
986                         num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
987                         rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
988                 } else {
989                         num = data->bpw_len / PCH_DMA_TRANS_SIZE;
990                         rem = PCH_DMA_TRANS_SIZE;
991                 }
992                 size = PCH_DMA_TRANS_SIZE;
993         } else {
994                 num = 1;
995                 size = data->bpw_len;
996                 rem = data->bpw_len;
997         }
998         dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
999                 __func__, num, size, rem);
1000         spin_lock_irqsave(&data->lock, flags);
1001 
1002         /* set receive fifo threshold and transmit fifo threshold */
1003         pch_spi_setclr_reg(data->master, PCH_SPCR,
1004                            ((size - 1) << SPCR_RFIC_FIELD) |
1005                            (PCH_TX_THOLD << SPCR_TFIC_FIELD),
1006                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1007 
1008         spin_unlock_irqrestore(&data->lock, flags);
1009 
1010         /* RX */
1011         dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1012         sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1013         /* offset, length setting */
1014         sg = dma->sg_rx_p;
1015         for (i = 0; i < num; i++, sg++) {
1016                 if (i == (num - 2)) {
1017                         sg->offset = size * i;
1018                         sg->offset = sg->offset * (*bpw / 8);
1019                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1020                                     sg->offset);
1021                         sg_dma_len(sg) = rem;
1022                 } else if (i == (num - 1)) {
1023                         sg->offset = size * (i - 1) + rem;
1024                         sg->offset = sg->offset * (*bpw / 8);
1025                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1026                                     sg->offset);
1027                         sg_dma_len(sg) = size;
1028                 } else {
1029                         sg->offset = size * i;
1030                         sg->offset = sg->offset * (*bpw / 8);
1031                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1032                                     sg->offset);
1033                         sg_dma_len(sg) = size;
1034                 }
1035                 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1036         }
1037         sg = dma->sg_rx_p;
1038         desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg,
1039                                         num, DMA_DEV_TO_MEM,
1040                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1041         if (!desc_rx) {
1042                 dev_err(&data->master->dev,
1043                         "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1044                 return;
1045         }
1046         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1047         desc_rx->callback = pch_dma_rx_complete;
1048         desc_rx->callback_param = data;
1049         dma->nent = num;
1050         dma->desc_rx = desc_rx;
1051 
1052         /* Calculate Tx parameter for DMA transmitting */
1053         if (data->bpw_len > PCH_MAX_FIFO_DEPTH) {
1054                 head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE;
1055                 if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) {
1056                         num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1057                         rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head;
1058                 } else {
1059                         num = data->bpw_len / PCH_DMA_TRANS_SIZE;
1060                         rem = data->bpw_len % PCH_DMA_TRANS_SIZE +
1061                               PCH_DMA_TRANS_SIZE - head;
1062                 }
1063                 size = PCH_DMA_TRANS_SIZE;
1064         } else {
1065                 num = 1;
1066                 size = data->bpw_len;
1067                 rem = data->bpw_len;
1068                 head = 0;
1069         }
1070 
1071         dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1072         sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1073         /* offset, length setting */
1074         sg = dma->sg_tx_p;
1075         for (i = 0; i < num; i++, sg++) {
1076                 if (i == 0) {
1077                         sg->offset = 0;
1078                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head,
1079                                     sg->offset);
1080                         sg_dma_len(sg) = size + head;
1081                 } else if (i == (num - 1)) {
1082                         sg->offset = head + size * i;
1083                         sg->offset = sg->offset * (*bpw / 8);
1084                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1085                                     sg->offset);
1086                         sg_dma_len(sg) = rem;
1087                 } else {
1088                         sg->offset = head + size * i;
1089                         sg->offset = sg->offset * (*bpw / 8);
1090                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1091                                     sg->offset);
1092                         sg_dma_len(sg) = size;
1093                 }
1094                 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1095         }
1096         sg = dma->sg_tx_p;
1097         desc_tx = dmaengine_prep_slave_sg(dma->chan_tx,
1098                                         sg, num, DMA_MEM_TO_DEV,
1099                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1100         if (!desc_tx) {
1101                 dev_err(&data->master->dev,
1102                         "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1103                 return;
1104         }
1105         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1106         desc_tx->callback = NULL;
1107         desc_tx->callback_param = data;
1108         dma->nent = num;
1109         dma->desc_tx = desc_tx;
1110 
1111         dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__);
1112 
1113         spin_lock_irqsave(&data->lock, flags);
1114         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1115         desc_rx->tx_submit(desc_rx);
1116         desc_tx->tx_submit(desc_tx);
1117         spin_unlock_irqrestore(&data->lock, flags);
1118 
1119         /* reset transfer complete flag */
1120         data->transfer_complete = false;
1121 }
1122 
1123 static void pch_spi_process_messages(struct work_struct *pwork)
1124 {
1125         struct spi_message *pmsg, *tmp;
1126         struct pch_spi_data *data;
1127         int bpw;
1128 
1129         data = container_of(pwork, struct pch_spi_data, work);
1130         dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1131 
1132         spin_lock(&data->lock);
1133         /* check if suspend has been initiated;if yes flush queue */
1134         if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1135                 dev_dbg(&data->master->dev,
1136                         "%s suspend/remove initiated, flushing queue\n", __func__);
1137                 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
1138                         pmsg->status = -EIO;
1139 
1140                         if (pmsg->complete) {
1141                                 spin_unlock(&data->lock);
1142                                 pmsg->complete(pmsg->context);
1143                                 spin_lock(&data->lock);
1144                         }
1145 
1146                         /* delete from queue */
1147                         list_del_init(&pmsg->queue);
1148                 }
1149 
1150                 spin_unlock(&data->lock);
1151                 return;
1152         }
1153 
1154         data->bcurrent_msg_processing = true;
1155         dev_dbg(&data->master->dev,
1156                 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1157 
1158         /* Get the message from the queue and delete it from there. */
1159         data->current_msg = list_entry(data->queue.next, struct spi_message,
1160                                         queue);
1161 
1162         list_del_init(&data->current_msg->queue);
1163 
1164         data->current_msg->status = 0;
1165 
1166         pch_spi_select_chip(data, data->current_msg->spi);
1167 
1168         spin_unlock(&data->lock);
1169 
1170         if (data->use_dma)
1171                 pch_spi_request_dma(data,
1172                                     data->current_msg->spi->bits_per_word);
1173         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1174         do {
1175                 int cnt;
1176                 /* If we are already processing a message get the next
1177                 transfer structure from the message otherwise retrieve
1178                 the 1st transfer request from the message. */
1179                 spin_lock(&data->lock);
1180                 if (data->cur_trans == NULL) {
1181                         data->cur_trans =
1182                                 list_entry(data->current_msg->transfers.next,
1183                                            struct spi_transfer, transfer_list);
1184                         dev_dbg(&data->master->dev, "%s "
1185                                 ":Getting 1st transfer message\n", __func__);
1186                 } else {
1187                         data->cur_trans =
1188                                 list_entry(data->cur_trans->transfer_list.next,
1189                                            struct spi_transfer, transfer_list);
1190                         dev_dbg(&data->master->dev, "%s "
1191                                 ":Getting next transfer message\n", __func__);
1192                 }
1193                 spin_unlock(&data->lock);
1194 
1195                 if (!data->cur_trans->len)
1196                         goto out;
1197                 cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1;
1198                 data->save_total_len = data->cur_trans->len;
1199                 if (data->use_dma) {
1200                         int i;
1201                         char *save_rx_buf = data->cur_trans->rx_buf;
1202                         for (i = 0; i < cnt; i ++) {
1203                                 pch_spi_handle_dma(data, &bpw);
1204                                 if (!pch_spi_start_transfer(data)) {
1205                                         data->transfer_complete = true;
1206                                         data->current_msg->status = -EIO;
1207                                         data->current_msg->complete
1208                                                    (data->current_msg->context);
1209                                         data->bcurrent_msg_processing = false;
1210                                         data->current_msg = NULL;
1211                                         data->cur_trans = NULL;
1212                                         goto out;
1213                                 }
1214                                 pch_spi_copy_rx_data_for_dma(data, bpw);
1215                         }
1216                         data->cur_trans->rx_buf = save_rx_buf;
1217                 } else {
1218                         pch_spi_set_tx(data, &bpw);
1219                         pch_spi_set_ir(data);
1220                         pch_spi_copy_rx_data(data, bpw);
1221                         kfree(data->pkt_rx_buff);
1222                         data->pkt_rx_buff = NULL;
1223                         kfree(data->pkt_tx_buff);
1224                         data->pkt_tx_buff = NULL;
1225                 }
1226                 /* increment message count */
1227                 data->cur_trans->len = data->save_total_len;
1228                 data->current_msg->actual_length += data->cur_trans->len;
1229 
1230                 dev_dbg(&data->master->dev,
1231                         "%s:data->current_msg->actual_length=%d\n",
1232                         __func__, data->current_msg->actual_length);
1233 
1234                 /* check for delay */
1235                 if (data->cur_trans->delay_usecs) {
1236                         dev_dbg(&data->master->dev, "%s:"
1237                                 "delay in usec=%d\n", __func__,
1238                                 data->cur_trans->delay_usecs);
1239                         udelay(data->cur_trans->delay_usecs);
1240                 }
1241 
1242                 spin_lock(&data->lock);
1243 
1244                 /* No more transfer in this message. */
1245                 if ((data->cur_trans->transfer_list.next) ==
1246                     &(data->current_msg->transfers)) {
1247                         pch_spi_nomore_transfer(data);
1248                 }
1249 
1250                 spin_unlock(&data->lock);
1251 
1252         } while (data->cur_trans != NULL);
1253 
1254 out:
1255         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1256         if (data->use_dma)
1257                 pch_spi_release_dma(data);
1258 }
1259 
1260 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1261                                    struct pch_spi_data *data)
1262 {
1263         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1264 
1265         flush_work(&data->work);
1266 }
1267 
1268 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1269                                  struct pch_spi_data *data)
1270 {
1271         int retval = 0;
1272 
1273         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1274 
1275 
1276         /* reset PCH SPI h/w */
1277         pch_spi_reset(data->master);
1278         dev_dbg(&board_dat->pdev->dev,
1279                 "%s pch_spi_reset invoked successfully\n", __func__);
1280 
1281         dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1282 
1283         if (retval != 0) {
1284                 dev_err(&board_dat->pdev->dev,
1285                         "%s FAIL:invoking pch_spi_free_resources\n", __func__);
1286                 pch_spi_free_resources(board_dat, data);
1287         }
1288 
1289         dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval);
1290 
1291         return retval;
1292 }
1293 
1294 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1295                              struct pch_spi_data *data)
1296 {
1297         struct pch_spi_dma_ctrl *dma;
1298 
1299         dma = &data->dma;
1300         if (dma->tx_buf_dma)
1301                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1302                                   dma->tx_buf_virt, dma->tx_buf_dma);
1303         if (dma->rx_buf_dma)
1304                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1305                                   dma->rx_buf_virt, dma->rx_buf_dma);
1306         return;
1307 }
1308 
1309 static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1310                               struct pch_spi_data *data)
1311 {
1312         struct pch_spi_dma_ctrl *dma;
1313 
1314         dma = &data->dma;
1315         /* Get Consistent memory for Tx DMA */
1316         dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1317                                 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1318         /* Get Consistent memory for Rx DMA */
1319         dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1320                                 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1321 }
1322 
1323 static int pch_spi_pd_probe(struct platform_device *plat_dev)
1324 {
1325         int ret;
1326         struct spi_master *master;
1327         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1328         struct pch_spi_data *data;
1329 
1330         dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1331 
1332         master = spi_alloc_master(&board_dat->pdev->dev,
1333                                   sizeof(struct pch_spi_data));
1334         if (!master) {
1335                 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1336                         plat_dev->id);
1337                 return -ENOMEM;
1338         }
1339 
1340         data = spi_master_get_devdata(master);
1341         data->master = master;
1342 
1343         platform_set_drvdata(plat_dev, data);
1344 
1345         /* baseaddress + address offset) */
1346         data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1347                                          PCH_ADDRESS_SIZE * plat_dev->id;
1348         data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0);
1349         if (!data->io_remap_addr) {
1350                 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1351                 ret = -ENOMEM;
1352                 goto err_pci_iomap;
1353         }
1354         data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id;
1355 
1356         dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1357                 plat_dev->id, data->io_remap_addr);
1358 
1359         /* initialize members of SPI master */
1360         master->num_chipselect = PCH_MAX_CS;
1361         master->transfer = pch_spi_transfer;
1362         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1363         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1364         master->max_speed_hz = PCH_MAX_BAUDRATE;
1365 
1366         data->board_dat = board_dat;
1367         data->plat_dev = plat_dev;
1368         data->n_curnt_chip = 255;
1369         data->status = STATUS_RUNNING;
1370         data->ch = plat_dev->id;
1371         data->use_dma = use_dma;
1372 
1373         INIT_LIST_HEAD(&data->queue);
1374         spin_lock_init(&data->lock);
1375         INIT_WORK(&data->work, pch_spi_process_messages);
1376         init_waitqueue_head(&data->wait);
1377 
1378         ret = pch_spi_get_resources(board_dat, data);
1379         if (ret) {
1380                 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1381                 goto err_spi_get_resources;
1382         }
1383 
1384         ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1385                           IRQF_SHARED, KBUILD_MODNAME, data);
1386         if (ret) {
1387                 dev_err(&plat_dev->dev,
1388                         "%s request_irq failed\n", __func__);
1389                 goto err_request_irq;
1390         }
1391         data->irq_reg_sts = true;
1392 
1393         pch_spi_set_master_mode(master);
1394 
1395         if (use_dma) {
1396                 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1397                 pch_alloc_dma_buf(board_dat, data);
1398         }
1399 
1400         ret = spi_register_master(master);
1401         if (ret != 0) {
1402                 dev_err(&plat_dev->dev,
1403                         "%s spi_register_master FAILED\n", __func__);
1404                 goto err_spi_register_master;
1405         }
1406 
1407         return 0;
1408 
1409 err_spi_register_master:
1410         pch_free_dma_buf(board_dat, data);
1411         free_irq(board_dat->pdev->irq, data);
1412 err_request_irq:
1413         pch_spi_free_resources(board_dat, data);
1414 err_spi_get_resources:
1415         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1416 err_pci_iomap:
1417         spi_master_put(master);
1418 
1419         return ret;
1420 }
1421 
1422 static int pch_spi_pd_remove(struct platform_device *plat_dev)
1423 {
1424         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1425         struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1426         int count;
1427         unsigned long flags;
1428 
1429         dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1430                 __func__, plat_dev->id, board_dat->pdev->irq);
1431 
1432         if (use_dma)
1433                 pch_free_dma_buf(board_dat, data);
1434 
1435         /* check for any pending messages; no action is taken if the queue
1436          * is still full; but at least we tried.  Unload anyway */
1437         count = 500;
1438         spin_lock_irqsave(&data->lock, flags);
1439         data->status = STATUS_EXITING;
1440         while ((list_empty(&data->queue) == 0) && --count) {
1441                 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1442                         __func__);
1443                 spin_unlock_irqrestore(&data->lock, flags);
1444                 msleep(PCH_SLEEP_TIME);
1445                 spin_lock_irqsave(&data->lock, flags);
1446         }
1447         spin_unlock_irqrestore(&data->lock, flags);
1448 
1449         pch_spi_free_resources(board_dat, data);
1450         /* disable interrupts & free IRQ */
1451         if (data->irq_reg_sts) {
1452                 /* disable interrupts */
1453                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1454                 data->irq_reg_sts = false;
1455                 free_irq(board_dat->pdev->irq, data);
1456         }
1457 
1458         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1459         spi_unregister_master(data->master);
1460 
1461         return 0;
1462 }
1463 #ifdef CONFIG_PM
1464 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1465                               pm_message_t state)
1466 {
1467         u8 count;
1468         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1469         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1470 
1471         dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1472 
1473         if (!board_dat) {
1474                 dev_err(&pd_dev->dev,
1475                         "%s pci_get_drvdata returned NULL\n", __func__);
1476                 return -EFAULT;
1477         }
1478 
1479         /* check if the current message is processed:
1480            Only after thats done the transfer will be suspended */
1481         count = 255;
1482         while ((--count) > 0) {
1483                 if (!(data->bcurrent_msg_processing))
1484                         break;
1485                 msleep(PCH_SLEEP_TIME);
1486         }
1487 
1488         /* Free IRQ */
1489         if (data->irq_reg_sts) {
1490                 /* disable all interrupts */
1491                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1492                 pch_spi_reset(data->master);
1493                 free_irq(board_dat->pdev->irq, data);
1494 
1495                 data->irq_reg_sts = false;
1496                 dev_dbg(&pd_dev->dev,
1497                         "%s free_irq invoked successfully.\n", __func__);
1498         }
1499 
1500         return 0;
1501 }
1502 
1503 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1504 {
1505         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1506         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1507         int retval;
1508 
1509         if (!board_dat) {
1510                 dev_err(&pd_dev->dev,
1511                         "%s pci_get_drvdata returned NULL\n", __func__);
1512                 return -EFAULT;
1513         }
1514 
1515         if (!data->irq_reg_sts) {
1516                 /* register IRQ */
1517                 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1518                                      IRQF_SHARED, KBUILD_MODNAME, data);
1519                 if (retval < 0) {
1520                         dev_err(&pd_dev->dev,
1521                                 "%s request_irq failed\n", __func__);
1522                         return retval;
1523                 }
1524 
1525                 /* reset PCH SPI h/w */
1526                 pch_spi_reset(data->master);
1527                 pch_spi_set_master_mode(data->master);
1528                 data->irq_reg_sts = true;
1529         }
1530         return 0;
1531 }
1532 #else
1533 #define pch_spi_pd_suspend NULL
1534 #define pch_spi_pd_resume NULL
1535 #endif
1536 
1537 static struct platform_driver pch_spi_pd_driver = {
1538         .driver = {
1539                 .name = "pch-spi",
1540         },
1541         .probe = pch_spi_pd_probe,
1542         .remove = pch_spi_pd_remove,
1543         .suspend = pch_spi_pd_suspend,
1544         .resume = pch_spi_pd_resume
1545 };
1546 
1547 static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1548 {
1549         struct pch_spi_board_data *board_dat;
1550         struct platform_device *pd_dev = NULL;
1551         int retval;
1552         int i;
1553         struct pch_pd_dev_save *pd_dev_save;
1554 
1555         pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL);
1556         if (!pd_dev_save)
1557                 return -ENOMEM;
1558 
1559         board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL);
1560         if (!board_dat) {
1561                 retval = -ENOMEM;
1562                 goto err_no_mem;
1563         }
1564 
1565         retval = pci_request_regions(pdev, KBUILD_MODNAME);
1566         if (retval) {
1567                 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1568                 goto pci_request_regions;
1569         }
1570 
1571         board_dat->pdev = pdev;
1572         board_dat->num = id->driver_data;
1573         pd_dev_save->num = id->driver_data;
1574         pd_dev_save->board_dat = board_dat;
1575 
1576         retval = pci_enable_device(pdev);
1577         if (retval) {
1578                 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1579                 goto pci_enable_device;
1580         }
1581 
1582         for (i = 0; i < board_dat->num; i++) {
1583                 pd_dev = platform_device_alloc("pch-spi", i);
1584                 if (!pd_dev) {
1585                         dev_err(&pdev->dev, "platform_device_alloc failed\n");
1586                         retval = -ENOMEM;
1587                         goto err_platform_device;
1588                 }
1589                 pd_dev_save->pd_save[i] = pd_dev;
1590                 pd_dev->dev.parent = &pdev->dev;
1591 
1592                 retval = platform_device_add_data(pd_dev, board_dat,
1593                                                   sizeof(*board_dat));
1594                 if (retval) {
1595                         dev_err(&pdev->dev,
1596                                 "platform_device_add_data failed\n");
1597                         platform_device_put(pd_dev);
1598                         goto err_platform_device;
1599                 }
1600 
1601                 retval = platform_device_add(pd_dev);
1602                 if (retval) {
1603                         dev_err(&pdev->dev, "platform_device_add failed\n");
1604                         platform_device_put(pd_dev);
1605                         goto err_platform_device;
1606                 }
1607         }
1608 
1609         pci_set_drvdata(pdev, pd_dev_save);
1610 
1611         return 0;
1612 
1613 err_platform_device:
1614         while (--i >= 0)
1615                 platform_device_unregister(pd_dev_save->pd_save[i]);
1616         pci_disable_device(pdev);
1617 pci_enable_device:
1618         pci_release_regions(pdev);
1619 pci_request_regions:
1620         kfree(board_dat);
1621 err_no_mem:
1622         kfree(pd_dev_save);
1623 
1624         return retval;
1625 }
1626 
1627 static void pch_spi_remove(struct pci_dev *pdev)
1628 {
1629         int i;
1630         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1631 
1632         dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1633 
1634         for (i = 0; i < pd_dev_save->num; i++)
1635                 platform_device_unregister(pd_dev_save->pd_save[i]);
1636 
1637         pci_disable_device(pdev);
1638         pci_release_regions(pdev);
1639         kfree(pd_dev_save->board_dat);
1640         kfree(pd_dev_save);
1641 }
1642 
1643 #ifdef CONFIG_PM
1644 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1645 {
1646         int retval;
1647         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1648 
1649         dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1650 
1651         pd_dev_save->board_dat->suspend_sts = true;
1652 
1653         /* save config space */
1654         retval = pci_save_state(pdev);
1655         if (retval == 0) {
1656                 pci_enable_wake(pdev, PCI_D3hot, 0);
1657                 pci_disable_device(pdev);
1658                 pci_set_power_state(pdev, PCI_D3hot);
1659         } else {
1660                 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1661         }
1662 
1663         return retval;
1664 }
1665 
1666 static int pch_spi_resume(struct pci_dev *pdev)
1667 {
1668         int retval;
1669         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1670         dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1671 
1672         pci_set_power_state(pdev, PCI_D0);
1673         pci_restore_state(pdev);
1674 
1675         retval = pci_enable_device(pdev);
1676         if (retval < 0) {
1677                 dev_err(&pdev->dev,
1678                         "%s pci_enable_device failed\n", __func__);
1679         } else {
1680                 pci_enable_wake(pdev, PCI_D3hot, 0);
1681 
1682                 /* set suspend status to false */
1683                 pd_dev_save->board_dat->suspend_sts = false;
1684         }
1685 
1686         return retval;
1687 }
1688 #else
1689 #define pch_spi_suspend NULL
1690 #define pch_spi_resume NULL
1691 
1692 #endif
1693 
1694 static struct pci_driver pch_spi_pcidev_driver = {
1695         .name = "pch_spi",
1696         .id_table = pch_spi_pcidev_id,
1697         .probe = pch_spi_probe,
1698         .remove = pch_spi_remove,
1699         .suspend = pch_spi_suspend,
1700         .resume = pch_spi_resume,
1701 };
1702 
1703 static int __init pch_spi_init(void)
1704 {
1705         int ret;
1706         ret = platform_driver_register(&pch_spi_pd_driver);
1707         if (ret)
1708                 return ret;
1709 
1710         ret = pci_register_driver(&pch_spi_pcidev_driver);
1711         if (ret) {
1712                 platform_driver_unregister(&pch_spi_pd_driver);
1713                 return ret;
1714         }
1715 
1716         return 0;
1717 }
1718 module_init(pch_spi_init);
1719 
1720 static void __exit pch_spi_exit(void)
1721 {
1722         pci_unregister_driver(&pch_spi_pcidev_driver);
1723         platform_driver_unregister(&pch_spi_pd_driver);
1724 }
1725 module_exit(pch_spi_exit);
1726 
1727 module_param(use_dma, int, 0644);
1728 MODULE_PARM_DESC(use_dma,
1729                  "to use DMA for data transfers pass 1 else 0; default 1");
1730 
1731 MODULE_LICENSE("GPL");
1732 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver");
1733 MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id);
1734 
1735 

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