Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/drivers/spi/spi-ti-qspi.c

  1 /*
  2  * TI QSPI driver
  3  *
  4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
  5  * Author: Sourav Poddar <sourav.poddar@ti.com>
  6  *
  7  * This program is free software; you can redistribute it and/or
  8  * modify it under the terms of the GPLv2.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  */
 15 
 16 #include <linux/kernel.h>
 17 #include <linux/init.h>
 18 #include <linux/interrupt.h>
 19 #include <linux/module.h>
 20 #include <linux/device.h>
 21 #include <linux/delay.h>
 22 #include <linux/dma-mapping.h>
 23 #include <linux/dmaengine.h>
 24 #include <linux/omap-dma.h>
 25 #include <linux/platform_device.h>
 26 #include <linux/err.h>
 27 #include <linux/clk.h>
 28 #include <linux/io.h>
 29 #include <linux/slab.h>
 30 #include <linux/pm_runtime.h>
 31 #include <linux/of.h>
 32 #include <linux/of_device.h>
 33 #include <linux/pinctrl/consumer.h>
 34 #include <linux/mfd/syscon.h>
 35 #include <linux/regmap.h>
 36 
 37 #include <linux/spi/spi.h>
 38 
 39 struct ti_qspi_regs {
 40         u32 clkctrl;
 41 };
 42 
 43 struct ti_qspi {
 44         struct completion       transfer_complete;
 45 
 46         /* list synchronization */
 47         struct mutex            list_lock;
 48 
 49         struct spi_master       *master;
 50         void __iomem            *base;
 51         void __iomem            *mmap_base;
 52         struct regmap           *ctrl_base;
 53         unsigned int            ctrl_reg;
 54         struct clk              *fclk;
 55         struct device           *dev;
 56 
 57         struct ti_qspi_regs     ctx_reg;
 58 
 59         dma_addr_t              mmap_phys_base;
 60         struct dma_chan         *rx_chan;
 61 
 62         u32 spi_max_frequency;
 63         u32 cmd;
 64         u32 dc;
 65 
 66         bool mmap_enabled;
 67 };
 68 
 69 #define QSPI_PID                        (0x0)
 70 #define QSPI_SYSCONFIG                  (0x10)
 71 #define QSPI_SPI_CLOCK_CNTRL_REG        (0x40)
 72 #define QSPI_SPI_DC_REG                 (0x44)
 73 #define QSPI_SPI_CMD_REG                (0x48)
 74 #define QSPI_SPI_STATUS_REG             (0x4c)
 75 #define QSPI_SPI_DATA_REG               (0x50)
 76 #define QSPI_SPI_SETUP_REG(n)           ((0x54 + 4 * n))
 77 #define QSPI_SPI_SWITCH_REG             (0x64)
 78 #define QSPI_SPI_DATA_REG_1             (0x68)
 79 #define QSPI_SPI_DATA_REG_2             (0x6c)
 80 #define QSPI_SPI_DATA_REG_3             (0x70)
 81 
 82 #define QSPI_COMPLETION_TIMEOUT         msecs_to_jiffies(2000)
 83 
 84 #define QSPI_FCLK                       192000000
 85 
 86 /* Clock Control */
 87 #define QSPI_CLK_EN                     (1 << 31)
 88 #define QSPI_CLK_DIV_MAX                0xffff
 89 
 90 /* Command */
 91 #define QSPI_EN_CS(n)                   (n << 28)
 92 #define QSPI_WLEN(n)                    ((n - 1) << 19)
 93 #define QSPI_3_PIN                      (1 << 18)
 94 #define QSPI_RD_SNGL                    (1 << 16)
 95 #define QSPI_WR_SNGL                    (2 << 16)
 96 #define QSPI_RD_DUAL                    (3 << 16)
 97 #define QSPI_RD_QUAD                    (7 << 16)
 98 #define QSPI_INVAL                      (4 << 16)
 99 #define QSPI_FLEN(n)                    ((n - 1) << 0)
100 #define QSPI_WLEN_MAX_BITS              128
101 #define QSPI_WLEN_MAX_BYTES             16
102 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
103 
104 /* STATUS REGISTER */
105 #define BUSY                            0x01
106 #define WC                              0x02
107 
108 /* Device Control */
109 #define QSPI_DD(m, n)                   (m << (3 + n * 8))
110 #define QSPI_CKPHA(n)                   (1 << (2 + n * 8))
111 #define QSPI_CSPOL(n)                   (1 << (1 + n * 8))
112 #define QSPI_CKPOL(n)                   (1 << (n * 8))
113 
114 #define QSPI_FRAME                      4096
115 
116 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
117 
118 #define MEM_CS_EN(n)                    ((n + 1) << 8)
119 #define MEM_CS_MASK                     (7 << 8)
120 
121 #define MM_SWITCH                       0x1
122 
123 #define QSPI_SETUP_RD_NORMAL            (0x0 << 12)
124 #define QSPI_SETUP_RD_DUAL              (0x1 << 12)
125 #define QSPI_SETUP_RD_QUAD              (0x3 << 12)
126 #define QSPI_SETUP_ADDR_SHIFT           8
127 #define QSPI_SETUP_DUMMY_SHIFT          10
128 
129 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
130                 unsigned long reg)
131 {
132         return readl(qspi->base + reg);
133 }
134 
135 static inline void ti_qspi_write(struct ti_qspi *qspi,
136                 unsigned long val, unsigned long reg)
137 {
138         writel(val, qspi->base + reg);
139 }
140 
141 static int ti_qspi_setup(struct spi_device *spi)
142 {
143         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
144         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
145         int clk_div = 0, ret;
146         u32 clk_ctrl_reg, clk_rate, clk_mask;
147 
148         if (spi->master->busy) {
149                 dev_dbg(qspi->dev, "master busy doing other transfers\n");
150                 return -EBUSY;
151         }
152 
153         if (!qspi->spi_max_frequency) {
154                 dev_err(qspi->dev, "spi max frequency not defined\n");
155                 return -EINVAL;
156         }
157 
158         clk_rate = clk_get_rate(qspi->fclk);
159 
160         clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
161 
162         if (clk_div < 0) {
163                 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
164                 return -EINVAL;
165         }
166 
167         if (clk_div > QSPI_CLK_DIV_MAX) {
168                 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
169                                 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
170                 return -EINVAL;
171         }
172 
173         dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
174                         qspi->spi_max_frequency, clk_div);
175 
176         ret = pm_runtime_get_sync(qspi->dev);
177         if (ret < 0) {
178                 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
179                 return ret;
180         }
181 
182         clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
183 
184         clk_ctrl_reg &= ~QSPI_CLK_EN;
185 
186         /* disable SCLK */
187         ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
188 
189         /* enable SCLK */
190         clk_mask = QSPI_CLK_EN | clk_div;
191         ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
192         ctx_reg->clkctrl = clk_mask;
193 
194         pm_runtime_mark_last_busy(qspi->dev);
195         ret = pm_runtime_put_autosuspend(qspi->dev);
196         if (ret < 0) {
197                 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
198                 return ret;
199         }
200 
201         return 0;
202 }
203 
204 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
205 {
206         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
207 
208         ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
209 }
210 
211 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
212 {
213         u32 stat;
214         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
215 
216         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
217         while ((stat & BUSY) && time_after(timeout, jiffies)) {
218                 cpu_relax();
219                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
220         }
221 
222         WARN(stat & BUSY, "qspi busy\n");
223         return stat & BUSY;
224 }
225 
226 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
227 {
228         u32 stat;
229         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
230 
231         do {
232                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
233                 if (stat & WC)
234                         return 0;
235                 cpu_relax();
236         } while (time_after(timeout, jiffies));
237 
238         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
239         if (stat & WC)
240                 return 0;
241         return  -ETIMEDOUT;
242 }
243 
244 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
245                           int count)
246 {
247         int wlen, xfer_len;
248         unsigned int cmd;
249         const u8 *txbuf;
250         u32 data;
251 
252         txbuf = t->tx_buf;
253         cmd = qspi->cmd | QSPI_WR_SNGL;
254         wlen = t->bits_per_word >> 3;   /* in bytes */
255         xfer_len = wlen;
256 
257         while (count) {
258                 if (qspi_is_busy(qspi))
259                         return -EBUSY;
260 
261                 switch (wlen) {
262                 case 1:
263                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
264                                         cmd, qspi->dc, *txbuf);
265                         if (count >= QSPI_WLEN_MAX_BYTES) {
266                                 u32 *txp = (u32 *)txbuf;
267 
268                                 data = cpu_to_be32(*txp++);
269                                 writel(data, qspi->base +
270                                        QSPI_SPI_DATA_REG_3);
271                                 data = cpu_to_be32(*txp++);
272                                 writel(data, qspi->base +
273                                        QSPI_SPI_DATA_REG_2);
274                                 data = cpu_to_be32(*txp++);
275                                 writel(data, qspi->base +
276                                        QSPI_SPI_DATA_REG_1);
277                                 data = cpu_to_be32(*txp++);
278                                 writel(data, qspi->base +
279                                        QSPI_SPI_DATA_REG);
280                                 xfer_len = QSPI_WLEN_MAX_BYTES;
281                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
282                         } else {
283                                 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
284                                 cmd = qspi->cmd | QSPI_WR_SNGL;
285                                 xfer_len = wlen;
286                                 cmd |= QSPI_WLEN(wlen);
287                         }
288                         break;
289                 case 2:
290                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
291                                         cmd, qspi->dc, *txbuf);
292                         writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
293                         break;
294                 case 4:
295                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
296                                         cmd, qspi->dc, *txbuf);
297                         writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
298                         break;
299                 }
300 
301                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
302                 if (ti_qspi_poll_wc(qspi)) {
303                         dev_err(qspi->dev, "write timed out\n");
304                         return -ETIMEDOUT;
305                 }
306                 txbuf += xfer_len;
307                 count -= xfer_len;
308         }
309 
310         return 0;
311 }
312 
313 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
314                          int count)
315 {
316         int wlen;
317         unsigned int cmd;
318         u8 *rxbuf;
319 
320         rxbuf = t->rx_buf;
321         cmd = qspi->cmd;
322         switch (t->rx_nbits) {
323         case SPI_NBITS_DUAL:
324                 cmd |= QSPI_RD_DUAL;
325                 break;
326         case SPI_NBITS_QUAD:
327                 cmd |= QSPI_RD_QUAD;
328                 break;
329         default:
330                 cmd |= QSPI_RD_SNGL;
331                 break;
332         }
333         wlen = t->bits_per_word >> 3;   /* in bytes */
334 
335         while (count) {
336                 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
337                 if (qspi_is_busy(qspi))
338                         return -EBUSY;
339 
340                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
341                 if (ti_qspi_poll_wc(qspi)) {
342                         dev_err(qspi->dev, "read timed out\n");
343                         return -ETIMEDOUT;
344                 }
345                 switch (wlen) {
346                 case 1:
347                         *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
348                         break;
349                 case 2:
350                         *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
351                         break;
352                 case 4:
353                         *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
354                         break;
355                 }
356                 rxbuf += wlen;
357                 count -= wlen;
358         }
359 
360         return 0;
361 }
362 
363 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
364                              int count)
365 {
366         int ret;
367 
368         if (t->tx_buf) {
369                 ret = qspi_write_msg(qspi, t, count);
370                 if (ret) {
371                         dev_dbg(qspi->dev, "Error while writing\n");
372                         return ret;
373                 }
374         }
375 
376         if (t->rx_buf) {
377                 ret = qspi_read_msg(qspi, t, count);
378                 if (ret) {
379                         dev_dbg(qspi->dev, "Error while reading\n");
380                         return ret;
381                 }
382         }
383 
384         return 0;
385 }
386 
387 static void ti_qspi_dma_callback(void *param)
388 {
389         struct ti_qspi *qspi = param;
390 
391         complete(&qspi->transfer_complete);
392 }
393 
394 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
395                             dma_addr_t dma_src, size_t len)
396 {
397         struct dma_chan *chan = qspi->rx_chan;
398         struct dma_device *dma_dev = chan->device;
399         dma_cookie_t cookie;
400         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
401         struct dma_async_tx_descriptor *tx;
402         int ret;
403 
404         tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
405                                              len, flags);
406         if (!tx) {
407                 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
408                 return -EIO;
409         }
410 
411         tx->callback = ti_qspi_dma_callback;
412         tx->callback_param = qspi;
413         cookie = tx->tx_submit(tx);
414         reinit_completion(&qspi->transfer_complete);
415 
416         ret = dma_submit_error(cookie);
417         if (ret) {
418                 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
419                 return -EIO;
420         }
421 
422         dma_async_issue_pending(chan);
423         ret = wait_for_completion_timeout(&qspi->transfer_complete,
424                                           msecs_to_jiffies(len));
425         if (ret <= 0) {
426                 dmaengine_terminate_sync(chan);
427                 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
428                 return -ETIMEDOUT;
429         }
430 
431         return 0;
432 }
433 
434 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
435                                loff_t from)
436 {
437         struct scatterlist *sg;
438         dma_addr_t dma_src = qspi->mmap_phys_base + from;
439         dma_addr_t dma_dst;
440         int i, len, ret;
441 
442         for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
443                 dma_dst = sg_dma_address(sg);
444                 len = sg_dma_len(sg);
445                 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
446                 if (ret)
447                         return ret;
448                 dma_src += len;
449         }
450 
451         return 0;
452 }
453 
454 static void ti_qspi_enable_memory_map(struct spi_device *spi)
455 {
456         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
457 
458         ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
459         if (qspi->ctrl_base) {
460                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
461                                    MEM_CS_EN(spi->chip_select),
462                                    MEM_CS_MASK);
463         }
464         qspi->mmap_enabled = true;
465 }
466 
467 static void ti_qspi_disable_memory_map(struct spi_device *spi)
468 {
469         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
470 
471         ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
472         if (qspi->ctrl_base)
473                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
474                                    0, MEM_CS_MASK);
475         qspi->mmap_enabled = false;
476 }
477 
478 static void ti_qspi_setup_mmap_read(struct spi_device *spi,
479                                     struct spi_flash_read_message *msg)
480 {
481         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
482         u32 memval = msg->read_opcode;
483 
484         switch (msg->data_nbits) {
485         case SPI_NBITS_QUAD:
486                 memval |= QSPI_SETUP_RD_QUAD;
487                 break;
488         case SPI_NBITS_DUAL:
489                 memval |= QSPI_SETUP_RD_DUAL;
490                 break;
491         default:
492                 memval |= QSPI_SETUP_RD_NORMAL;
493                 break;
494         }
495         memval |= ((msg->addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
496                    msg->dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
497         ti_qspi_write(qspi, memval,
498                       QSPI_SPI_SETUP_REG(spi->chip_select));
499 }
500 
501 static int ti_qspi_spi_flash_read(struct spi_device *spi,
502                                   struct spi_flash_read_message *msg)
503 {
504         struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
505         int ret = 0;
506 
507         mutex_lock(&qspi->list_lock);
508 
509         if (!qspi->mmap_enabled)
510                 ti_qspi_enable_memory_map(spi);
511         ti_qspi_setup_mmap_read(spi, msg);
512 
513         if (qspi->rx_chan) {
514                 if (msg->cur_msg_mapped) {
515                         ret = ti_qspi_dma_xfer_sg(qspi, msg->rx_sg, msg->from);
516                         if (ret)
517                                 goto err_unlock;
518                 } else {
519                         dev_err(qspi->dev, "Invalid address for DMA\n");
520                         ret = -EIO;
521                         goto err_unlock;
522                 }
523         } else {
524                 memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len);
525         }
526         msg->retlen = msg->len;
527 
528 err_unlock:
529         mutex_unlock(&qspi->list_lock);
530 
531         return ret;
532 }
533 
534 static int ti_qspi_start_transfer_one(struct spi_master *master,
535                 struct spi_message *m)
536 {
537         struct ti_qspi *qspi = spi_master_get_devdata(master);
538         struct spi_device *spi = m->spi;
539         struct spi_transfer *t;
540         int status = 0, ret;
541         unsigned int frame_len_words, transfer_len_words;
542         int wlen;
543 
544         /* setup device control reg */
545         qspi->dc = 0;
546 
547         if (spi->mode & SPI_CPHA)
548                 qspi->dc |= QSPI_CKPHA(spi->chip_select);
549         if (spi->mode & SPI_CPOL)
550                 qspi->dc |= QSPI_CKPOL(spi->chip_select);
551         if (spi->mode & SPI_CS_HIGH)
552                 qspi->dc |= QSPI_CSPOL(spi->chip_select);
553 
554         frame_len_words = 0;
555         list_for_each_entry(t, &m->transfers, transfer_list)
556                 frame_len_words += t->len / (t->bits_per_word >> 3);
557         frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
558 
559         /* setup command reg */
560         qspi->cmd = 0;
561         qspi->cmd |= QSPI_EN_CS(spi->chip_select);
562         qspi->cmd |= QSPI_FLEN(frame_len_words);
563 
564         ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
565 
566         mutex_lock(&qspi->list_lock);
567 
568         if (qspi->mmap_enabled)
569                 ti_qspi_disable_memory_map(spi);
570 
571         list_for_each_entry(t, &m->transfers, transfer_list) {
572                 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
573                              QSPI_WLEN(t->bits_per_word));
574 
575                 wlen = t->bits_per_word >> 3;
576                 transfer_len_words = min(t->len / wlen, frame_len_words);
577 
578                 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
579                 if (ret) {
580                         dev_dbg(qspi->dev, "transfer message failed\n");
581                         mutex_unlock(&qspi->list_lock);
582                         return -EINVAL;
583                 }
584 
585                 m->actual_length += transfer_len_words * wlen;
586                 frame_len_words -= transfer_len_words;
587                 if (frame_len_words == 0)
588                         break;
589         }
590 
591         mutex_unlock(&qspi->list_lock);
592 
593         ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
594         m->status = status;
595         spi_finalize_current_message(master);
596 
597         return status;
598 }
599 
600 static int ti_qspi_runtime_resume(struct device *dev)
601 {
602         struct ti_qspi      *qspi;
603 
604         qspi = dev_get_drvdata(dev);
605         ti_qspi_restore_ctx(qspi);
606 
607         return 0;
608 }
609 
610 static const struct of_device_id ti_qspi_match[] = {
611         {.compatible = "ti,dra7xxx-qspi" },
612         {.compatible = "ti,am4372-qspi" },
613         {},
614 };
615 MODULE_DEVICE_TABLE(of, ti_qspi_match);
616 
617 static int ti_qspi_probe(struct platform_device *pdev)
618 {
619         struct  ti_qspi *qspi;
620         struct spi_master *master;
621         struct resource         *r, *res_mmap;
622         struct device_node *np = pdev->dev.of_node;
623         u32 max_freq;
624         int ret = 0, num_cs, irq;
625         dma_cap_mask_t mask;
626 
627         master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
628         if (!master)
629                 return -ENOMEM;
630 
631         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
632 
633         master->flags = SPI_MASTER_HALF_DUPLEX;
634         master->setup = ti_qspi_setup;
635         master->auto_runtime_pm = true;
636         master->transfer_one_message = ti_qspi_start_transfer_one;
637         master->dev.of_node = pdev->dev.of_node;
638         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
639                                      SPI_BPW_MASK(8);
640         master->spi_flash_read = ti_qspi_spi_flash_read;
641 
642         if (!of_property_read_u32(np, "num-cs", &num_cs))
643                 master->num_chipselect = num_cs;
644 
645         qspi = spi_master_get_devdata(master);
646         qspi->master = master;
647         qspi->dev = &pdev->dev;
648         platform_set_drvdata(pdev, qspi);
649 
650         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
651         if (r == NULL) {
652                 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
653                 if (r == NULL) {
654                         dev_err(&pdev->dev, "missing platform data\n");
655                         return -ENODEV;
656                 }
657         }
658 
659         res_mmap = platform_get_resource_byname(pdev,
660                         IORESOURCE_MEM, "qspi_mmap");
661         if (res_mmap == NULL) {
662                 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
663                 if (res_mmap == NULL) {
664                         dev_err(&pdev->dev,
665                                 "memory mapped resource not required\n");
666                 }
667         }
668 
669         irq = platform_get_irq(pdev, 0);
670         if (irq < 0) {
671                 dev_err(&pdev->dev, "no irq resource?\n");
672                 return irq;
673         }
674 
675         mutex_init(&qspi->list_lock);
676 
677         qspi->base = devm_ioremap_resource(&pdev->dev, r);
678         if (IS_ERR(qspi->base)) {
679                 ret = PTR_ERR(qspi->base);
680                 goto free_master;
681         }
682 
683 
684         if (of_property_read_bool(np, "syscon-chipselects")) {
685                 qspi->ctrl_base =
686                 syscon_regmap_lookup_by_phandle(np,
687                                                 "syscon-chipselects");
688                 if (IS_ERR(qspi->ctrl_base))
689                         return PTR_ERR(qspi->ctrl_base);
690                 ret = of_property_read_u32_index(np,
691                                                  "syscon-chipselects",
692                                                  1, &qspi->ctrl_reg);
693                 if (ret) {
694                         dev_err(&pdev->dev,
695                                 "couldn't get ctrl_mod reg index\n");
696                         return ret;
697                 }
698         }
699 
700         qspi->fclk = devm_clk_get(&pdev->dev, "fck");
701         if (IS_ERR(qspi->fclk)) {
702                 ret = PTR_ERR(qspi->fclk);
703                 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
704         }
705 
706         pm_runtime_use_autosuspend(&pdev->dev);
707         pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
708         pm_runtime_enable(&pdev->dev);
709 
710         if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
711                 qspi->spi_max_frequency = max_freq;
712 
713         dma_cap_zero(mask);
714         dma_cap_set(DMA_MEMCPY, mask);
715 
716         qspi->rx_chan = dma_request_chan_by_mask(&mask);
717         if (!qspi->rx_chan) {
718                 dev_err(qspi->dev,
719                         "No Rx DMA available, trying mmap mode\n");
720                 ret = 0;
721                 goto no_dma;
722         }
723         master->dma_rx = qspi->rx_chan;
724         init_completion(&qspi->transfer_complete);
725         if (res_mmap)
726                 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
727 
728 no_dma:
729         if (!qspi->rx_chan && res_mmap) {
730                 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
731                 if (IS_ERR(qspi->mmap_base)) {
732                         dev_info(&pdev->dev,
733                                  "mmap failed with error %ld using PIO mode\n",
734                                  PTR_ERR(qspi->mmap_base));
735                         qspi->mmap_base = NULL;
736                         master->spi_flash_read = NULL;
737                 }
738         }
739         qspi->mmap_enabled = false;
740 
741         ret = devm_spi_register_master(&pdev->dev, master);
742         if (!ret)
743                 return 0;
744 
745 free_master:
746         spi_master_put(master);
747         return ret;
748 }
749 
750 static int ti_qspi_remove(struct platform_device *pdev)
751 {
752         struct ti_qspi *qspi = platform_get_drvdata(pdev);
753         int rc;
754 
755         rc = spi_master_suspend(qspi->master);
756         if (rc)
757                 return rc;
758 
759         pm_runtime_put_sync(&pdev->dev);
760         pm_runtime_disable(&pdev->dev);
761 
762         if (qspi->rx_chan)
763                 dma_release_channel(qspi->rx_chan);
764 
765         return 0;
766 }
767 
768 static const struct dev_pm_ops ti_qspi_pm_ops = {
769         .runtime_resume = ti_qspi_runtime_resume,
770 };
771 
772 static struct platform_driver ti_qspi_driver = {
773         .probe  = ti_qspi_probe,
774         .remove = ti_qspi_remove,
775         .driver = {
776                 .name   = "ti-qspi",
777                 .pm =   &ti_qspi_pm_ops,
778                 .of_match_table = ti_qspi_match,
779         }
780 };
781 
782 module_platform_driver(ti_qspi_driver);
783 
784 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
785 MODULE_LICENSE("GPL v2");
786 MODULE_DESCRIPTION("TI QSPI controller driver");
787 MODULE_ALIAS("platform:ti-qspi");
788 

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