Version:  2.0.40 2.2.26 2.4.37 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6

Linux/drivers/spi/spi-ti-qspi.c

  1 /*
  2  * TI QSPI driver
  3  *
  4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
  5  * Author: Sourav Poddar <sourav.poddar@ti.com>
  6  *
  7  * This program is free software; you can redistribute it and/or
  8  * modify it under the terms of the GPLv2.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  */
 15 
 16 #include <linux/kernel.h>
 17 #include <linux/init.h>
 18 #include <linux/interrupt.h>
 19 #include <linux/module.h>
 20 #include <linux/device.h>
 21 #include <linux/delay.h>
 22 #include <linux/dma-mapping.h>
 23 #include <linux/dmaengine.h>
 24 #include <linux/omap-dma.h>
 25 #include <linux/platform_device.h>
 26 #include <linux/err.h>
 27 #include <linux/clk.h>
 28 #include <linux/io.h>
 29 #include <linux/slab.h>
 30 #include <linux/pm_runtime.h>
 31 #include <linux/of.h>
 32 #include <linux/of_device.h>
 33 #include <linux/pinctrl/consumer.h>
 34 #include <linux/mfd/syscon.h>
 35 #include <linux/regmap.h>
 36 
 37 #include <linux/spi/spi.h>
 38 
 39 struct ti_qspi_regs {
 40         u32 clkctrl;
 41 };
 42 
 43 struct ti_qspi {
 44         /* list synchronization */
 45         struct mutex            list_lock;
 46 
 47         struct spi_master       *master;
 48         void __iomem            *base;
 49         void __iomem            *mmap_base;
 50         struct regmap           *ctrl_base;
 51         unsigned int            ctrl_reg;
 52         struct clk              *fclk;
 53         struct device           *dev;
 54 
 55         struct ti_qspi_regs     ctx_reg;
 56 
 57         u32 spi_max_frequency;
 58         u32 cmd;
 59         u32 dc;
 60 
 61         bool mmap_enabled;
 62 };
 63 
 64 #define QSPI_PID                        (0x0)
 65 #define QSPI_SYSCONFIG                  (0x10)
 66 #define QSPI_SPI_CLOCK_CNTRL_REG        (0x40)
 67 #define QSPI_SPI_DC_REG                 (0x44)
 68 #define QSPI_SPI_CMD_REG                (0x48)
 69 #define QSPI_SPI_STATUS_REG             (0x4c)
 70 #define QSPI_SPI_DATA_REG               (0x50)
 71 #define QSPI_SPI_SETUP_REG(n)           ((0x54 + 4 * n))
 72 #define QSPI_SPI_SWITCH_REG             (0x64)
 73 #define QSPI_SPI_DATA_REG_1             (0x68)
 74 #define QSPI_SPI_DATA_REG_2             (0x6c)
 75 #define QSPI_SPI_DATA_REG_3             (0x70)
 76 
 77 #define QSPI_COMPLETION_TIMEOUT         msecs_to_jiffies(2000)
 78 
 79 #define QSPI_FCLK                       192000000
 80 
 81 /* Clock Control */
 82 #define QSPI_CLK_EN                     (1 << 31)
 83 #define QSPI_CLK_DIV_MAX                0xffff
 84 
 85 /* Command */
 86 #define QSPI_EN_CS(n)                   (n << 28)
 87 #define QSPI_WLEN(n)                    ((n - 1) << 19)
 88 #define QSPI_3_PIN                      (1 << 18)
 89 #define QSPI_RD_SNGL                    (1 << 16)
 90 #define QSPI_WR_SNGL                    (2 << 16)
 91 #define QSPI_RD_DUAL                    (3 << 16)
 92 #define QSPI_RD_QUAD                    (7 << 16)
 93 #define QSPI_INVAL                      (4 << 16)
 94 #define QSPI_FLEN(n)                    ((n - 1) << 0)
 95 #define QSPI_WLEN_MAX_BITS              128
 96 #define QSPI_WLEN_MAX_BYTES             16
 97 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
 98 
 99 /* STATUS REGISTER */
100 #define BUSY                            0x01
101 #define WC                              0x02
102 
103 /* Device Control */
104 #define QSPI_DD(m, n)                   (m << (3 + n * 8))
105 #define QSPI_CKPHA(n)                   (1 << (2 + n * 8))
106 #define QSPI_CSPOL(n)                   (1 << (1 + n * 8))
107 #define QSPI_CKPOL(n)                   (1 << (n * 8))
108 
109 #define QSPI_FRAME                      4096
110 
111 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
112 
113 #define MEM_CS_EN(n)                    ((n + 1) << 8)
114 #define MEM_CS_MASK                     (7 << 8)
115 
116 #define MM_SWITCH                       0x1
117 
118 #define QSPI_SETUP_RD_NORMAL            (0x0 << 12)
119 #define QSPI_SETUP_RD_DUAL              (0x1 << 12)
120 #define QSPI_SETUP_RD_QUAD              (0x3 << 12)
121 #define QSPI_SETUP_ADDR_SHIFT           8
122 #define QSPI_SETUP_DUMMY_SHIFT          10
123 
124 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
125                 unsigned long reg)
126 {
127         return readl(qspi->base + reg);
128 }
129 
130 static inline void ti_qspi_write(struct ti_qspi *qspi,
131                 unsigned long val, unsigned long reg)
132 {
133         writel(val, qspi->base + reg);
134 }
135 
136 static int ti_qspi_setup(struct spi_device *spi)
137 {
138         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
139         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
140         int clk_div = 0, ret;
141         u32 clk_ctrl_reg, clk_rate, clk_mask;
142 
143         if (spi->master->busy) {
144                 dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
145                 return -EBUSY;
146         }
147 
148         if (!qspi->spi_max_frequency) {
149                 dev_err(qspi->dev, "spi max frequency not defined\n");
150                 return -EINVAL;
151         }
152 
153         clk_rate = clk_get_rate(qspi->fclk);
154 
155         clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
156 
157         if (clk_div < 0) {
158                 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
159                 return -EINVAL;
160         }
161 
162         if (clk_div > QSPI_CLK_DIV_MAX) {
163                 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
164                                 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
165                 return -EINVAL;
166         }
167 
168         dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
169                         qspi->spi_max_frequency, clk_div);
170 
171         ret = pm_runtime_get_sync(qspi->dev);
172         if (ret < 0) {
173                 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
174                 return ret;
175         }
176 
177         clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
178 
179         clk_ctrl_reg &= ~QSPI_CLK_EN;
180 
181         /* disable SCLK */
182         ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
183 
184         /* enable SCLK */
185         clk_mask = QSPI_CLK_EN | clk_div;
186         ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
187         ctx_reg->clkctrl = clk_mask;
188 
189         pm_runtime_mark_last_busy(qspi->dev);
190         ret = pm_runtime_put_autosuspend(qspi->dev);
191         if (ret < 0) {
192                 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
193                 return ret;
194         }
195 
196         return 0;
197 }
198 
199 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
200 {
201         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
202 
203         ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
204 }
205 
206 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
207 {
208         u32 stat;
209         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
210 
211         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
212         while ((stat & BUSY) && time_after(timeout, jiffies)) {
213                 cpu_relax();
214                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
215         }
216 
217         WARN(stat & BUSY, "qspi busy\n");
218         return stat & BUSY;
219 }
220 
221 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
222 {
223         u32 stat;
224         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
225 
226         do {
227                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
228                 if (stat & WC)
229                         return 0;
230                 cpu_relax();
231         } while (time_after(timeout, jiffies));
232 
233         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
234         if (stat & WC)
235                 return 0;
236         return  -ETIMEDOUT;
237 }
238 
239 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
240                           int count)
241 {
242         int wlen, xfer_len;
243         unsigned int cmd;
244         const u8 *txbuf;
245         u32 data;
246 
247         txbuf = t->tx_buf;
248         cmd = qspi->cmd | QSPI_WR_SNGL;
249         wlen = t->bits_per_word >> 3;   /* in bytes */
250         xfer_len = wlen;
251 
252         while (count) {
253                 if (qspi_is_busy(qspi))
254                         return -EBUSY;
255 
256                 switch (wlen) {
257                 case 1:
258                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
259                                         cmd, qspi->dc, *txbuf);
260                         if (count >= QSPI_WLEN_MAX_BYTES) {
261                                 u32 *txp = (u32 *)txbuf;
262 
263                                 data = cpu_to_be32(*txp++);
264                                 writel(data, qspi->base +
265                                        QSPI_SPI_DATA_REG_3);
266                                 data = cpu_to_be32(*txp++);
267                                 writel(data, qspi->base +
268                                        QSPI_SPI_DATA_REG_2);
269                                 data = cpu_to_be32(*txp++);
270                                 writel(data, qspi->base +
271                                        QSPI_SPI_DATA_REG_1);
272                                 data = cpu_to_be32(*txp++);
273                                 writel(data, qspi->base +
274                                        QSPI_SPI_DATA_REG);
275                                 xfer_len = QSPI_WLEN_MAX_BYTES;
276                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
277                         } else {
278                                 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
279                                 cmd = qspi->cmd | QSPI_WR_SNGL;
280                                 xfer_len = wlen;
281                                 cmd |= QSPI_WLEN(wlen);
282                         }
283                         break;
284                 case 2:
285                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
286                                         cmd, qspi->dc, *txbuf);
287                         writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
288                         break;
289                 case 4:
290                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
291                                         cmd, qspi->dc, *txbuf);
292                         writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
293                         break;
294                 }
295 
296                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
297                 if (ti_qspi_poll_wc(qspi)) {
298                         dev_err(qspi->dev, "write timed out\n");
299                         return -ETIMEDOUT;
300                 }
301                 txbuf += xfer_len;
302                 count -= xfer_len;
303         }
304 
305         return 0;
306 }
307 
308 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
309                          int count)
310 {
311         int wlen;
312         unsigned int cmd;
313         u8 *rxbuf;
314 
315         rxbuf = t->rx_buf;
316         cmd = qspi->cmd;
317         switch (t->rx_nbits) {
318         case SPI_NBITS_DUAL:
319                 cmd |= QSPI_RD_DUAL;
320                 break;
321         case SPI_NBITS_QUAD:
322                 cmd |= QSPI_RD_QUAD;
323                 break;
324         default:
325                 cmd |= QSPI_RD_SNGL;
326                 break;
327         }
328         wlen = t->bits_per_word >> 3;   /* in bytes */
329 
330         while (count) {
331                 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
332                 if (qspi_is_busy(qspi))
333                         return -EBUSY;
334 
335                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
336                 if (ti_qspi_poll_wc(qspi)) {
337                         dev_err(qspi->dev, "read timed out\n");
338                         return -ETIMEDOUT;
339                 }
340                 switch (wlen) {
341                 case 1:
342                         *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
343                         break;
344                 case 2:
345                         *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
346                         break;
347                 case 4:
348                         *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
349                         break;
350                 }
351                 rxbuf += wlen;
352                 count -= wlen;
353         }
354 
355         return 0;
356 }
357 
358 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
359                              int count)
360 {
361         int ret;
362 
363         if (t->tx_buf) {
364                 ret = qspi_write_msg(qspi, t, count);
365                 if (ret) {
366                         dev_dbg(qspi->dev, "Error while writing\n");
367                         return ret;
368                 }
369         }
370 
371         if (t->rx_buf) {
372                 ret = qspi_read_msg(qspi, t, count);
373                 if (ret) {
374                         dev_dbg(qspi->dev, "Error while reading\n");
375                         return ret;
376                 }
377         }
378 
379         return 0;
380 }
381 
382 static void ti_qspi_enable_memory_map(struct spi_device *spi)
383 {
384         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
385 
386         ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
387         if (qspi->ctrl_base) {
388                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
389                                    MEM_CS_EN(spi->chip_select),
390                                    MEM_CS_MASK);
391         }
392         qspi->mmap_enabled = true;
393 }
394 
395 static void ti_qspi_disable_memory_map(struct spi_device *spi)
396 {
397         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
398 
399         ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
400         if (qspi->ctrl_base)
401                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
402                                    0, MEM_CS_MASK);
403         qspi->mmap_enabled = false;
404 }
405 
406 static void ti_qspi_setup_mmap_read(struct spi_device *spi,
407                                     struct spi_flash_read_message *msg)
408 {
409         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
410         u32 memval = msg->read_opcode;
411 
412         switch (msg->data_nbits) {
413         case SPI_NBITS_QUAD:
414                 memval |= QSPI_SETUP_RD_QUAD;
415                 break;
416         case SPI_NBITS_DUAL:
417                 memval |= QSPI_SETUP_RD_DUAL;
418                 break;
419         default:
420                 memval |= QSPI_SETUP_RD_NORMAL;
421                 break;
422         }
423         memval |= ((msg->addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
424                    msg->dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
425         ti_qspi_write(qspi, memval,
426                       QSPI_SPI_SETUP_REG(spi->chip_select));
427 }
428 
429 static int ti_qspi_spi_flash_read(struct  spi_device *spi,
430                                   struct spi_flash_read_message *msg)
431 {
432         struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
433         int ret = 0;
434 
435         mutex_lock(&qspi->list_lock);
436 
437         if (!qspi->mmap_enabled)
438                 ti_qspi_enable_memory_map(spi);
439         ti_qspi_setup_mmap_read(spi, msg);
440         memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len);
441         msg->retlen = msg->len;
442 
443         mutex_unlock(&qspi->list_lock);
444 
445         return ret;
446 }
447 
448 static int ti_qspi_start_transfer_one(struct spi_master *master,
449                 struct spi_message *m)
450 {
451         struct ti_qspi *qspi = spi_master_get_devdata(master);
452         struct spi_device *spi = m->spi;
453         struct spi_transfer *t;
454         int status = 0, ret;
455         unsigned int frame_len_words, transfer_len_words;
456         int wlen;
457 
458         /* setup device control reg */
459         qspi->dc = 0;
460 
461         if (spi->mode & SPI_CPHA)
462                 qspi->dc |= QSPI_CKPHA(spi->chip_select);
463         if (spi->mode & SPI_CPOL)
464                 qspi->dc |= QSPI_CKPOL(spi->chip_select);
465         if (spi->mode & SPI_CS_HIGH)
466                 qspi->dc |= QSPI_CSPOL(spi->chip_select);
467 
468         frame_len_words = 0;
469         list_for_each_entry(t, &m->transfers, transfer_list)
470                 frame_len_words += t->len / (t->bits_per_word >> 3);
471         frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
472 
473         /* setup command reg */
474         qspi->cmd = 0;
475         qspi->cmd |= QSPI_EN_CS(spi->chip_select);
476         qspi->cmd |= QSPI_FLEN(frame_len_words);
477 
478         ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
479 
480         mutex_lock(&qspi->list_lock);
481 
482         if (qspi->mmap_enabled)
483                 ti_qspi_disable_memory_map(spi);
484 
485         list_for_each_entry(t, &m->transfers, transfer_list) {
486                 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
487                              QSPI_WLEN(t->bits_per_word));
488 
489                 wlen = t->bits_per_word >> 3;
490                 transfer_len_words = min(t->len / wlen, frame_len_words);
491 
492                 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
493                 if (ret) {
494                         dev_dbg(qspi->dev, "transfer message failed\n");
495                         mutex_unlock(&qspi->list_lock);
496                         return -EINVAL;
497                 }
498 
499                 m->actual_length += transfer_len_words * wlen;
500                 frame_len_words -= transfer_len_words;
501                 if (frame_len_words == 0)
502                         break;
503         }
504 
505         mutex_unlock(&qspi->list_lock);
506 
507         ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
508         m->status = status;
509         spi_finalize_current_message(master);
510 
511         return status;
512 }
513 
514 static int ti_qspi_runtime_resume(struct device *dev)
515 {
516         struct ti_qspi      *qspi;
517 
518         qspi = dev_get_drvdata(dev);
519         ti_qspi_restore_ctx(qspi);
520 
521         return 0;
522 }
523 
524 static const struct of_device_id ti_qspi_match[] = {
525         {.compatible = "ti,dra7xxx-qspi" },
526         {.compatible = "ti,am4372-qspi" },
527         {},
528 };
529 MODULE_DEVICE_TABLE(of, ti_qspi_match);
530 
531 static int ti_qspi_probe(struct platform_device *pdev)
532 {
533         struct  ti_qspi *qspi;
534         struct spi_master *master;
535         struct resource         *r, *res_mmap;
536         struct device_node *np = pdev->dev.of_node;
537         u32 max_freq;
538         int ret = 0, num_cs, irq;
539 
540         master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
541         if (!master)
542                 return -ENOMEM;
543 
544         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
545 
546         master->flags = SPI_MASTER_HALF_DUPLEX;
547         master->setup = ti_qspi_setup;
548         master->auto_runtime_pm = true;
549         master->transfer_one_message = ti_qspi_start_transfer_one;
550         master->dev.of_node = pdev->dev.of_node;
551         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
552                                      SPI_BPW_MASK(8);
553 
554         if (!of_property_read_u32(np, "num-cs", &num_cs))
555                 master->num_chipselect = num_cs;
556 
557         qspi = spi_master_get_devdata(master);
558         qspi->master = master;
559         qspi->dev = &pdev->dev;
560         platform_set_drvdata(pdev, qspi);
561 
562         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
563         if (r == NULL) {
564                 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
565                 if (r == NULL) {
566                         dev_err(&pdev->dev, "missing platform data\n");
567                         return -ENODEV;
568                 }
569         }
570 
571         res_mmap = platform_get_resource_byname(pdev,
572                         IORESOURCE_MEM, "qspi_mmap");
573         if (res_mmap == NULL) {
574                 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
575                 if (res_mmap == NULL) {
576                         dev_err(&pdev->dev,
577                                 "memory mapped resource not required\n");
578                 }
579         }
580 
581         irq = platform_get_irq(pdev, 0);
582         if (irq < 0) {
583                 dev_err(&pdev->dev, "no irq resource?\n");
584                 return irq;
585         }
586 
587         mutex_init(&qspi->list_lock);
588 
589         qspi->base = devm_ioremap_resource(&pdev->dev, r);
590         if (IS_ERR(qspi->base)) {
591                 ret = PTR_ERR(qspi->base);
592                 goto free_master;
593         }
594 
595         if (res_mmap) {
596                 qspi->mmap_base = devm_ioremap_resource(&pdev->dev,
597                                                         res_mmap);
598                 master->spi_flash_read = ti_qspi_spi_flash_read;
599                 if (IS_ERR(qspi->mmap_base)) {
600                         dev_err(&pdev->dev,
601                                 "falling back to PIO mode\n");
602                         master->spi_flash_read = NULL;
603                 }
604         }
605         qspi->mmap_enabled = false;
606 
607         if (of_property_read_bool(np, "syscon-chipselects")) {
608                 qspi->ctrl_base =
609                 syscon_regmap_lookup_by_phandle(np,
610                                                 "syscon-chipselects");
611                 if (IS_ERR(qspi->ctrl_base))
612                         return PTR_ERR(qspi->ctrl_base);
613                 ret = of_property_read_u32_index(np,
614                                                  "syscon-chipselects",
615                                                  1, &qspi->ctrl_reg);
616                 if (ret) {
617                         dev_err(&pdev->dev,
618                                 "couldn't get ctrl_mod reg index\n");
619                         return ret;
620                 }
621         }
622 
623         qspi->fclk = devm_clk_get(&pdev->dev, "fck");
624         if (IS_ERR(qspi->fclk)) {
625                 ret = PTR_ERR(qspi->fclk);
626                 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
627         }
628 
629         pm_runtime_use_autosuspend(&pdev->dev);
630         pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
631         pm_runtime_enable(&pdev->dev);
632 
633         if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
634                 qspi->spi_max_frequency = max_freq;
635 
636         ret = devm_spi_register_master(&pdev->dev, master);
637         if (ret)
638                 goto free_master;
639 
640         return 0;
641 
642 free_master:
643         spi_master_put(master);
644         return ret;
645 }
646 
647 static int ti_qspi_remove(struct platform_device *pdev)
648 {
649         pm_runtime_put_sync(&pdev->dev);
650         pm_runtime_disable(&pdev->dev);
651 
652         return 0;
653 }
654 
655 static const struct dev_pm_ops ti_qspi_pm_ops = {
656         .runtime_resume = ti_qspi_runtime_resume,
657 };
658 
659 static struct platform_driver ti_qspi_driver = {
660         .probe  = ti_qspi_probe,
661         .remove = ti_qspi_remove,
662         .driver = {
663                 .name   = "ti-qspi",
664                 .pm =   &ti_qspi_pm_ops,
665                 .of_match_table = ti_qspi_match,
666         }
667 };
668 
669 module_platform_driver(ti_qspi_driver);
670 
671 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
672 MODULE_LICENSE("GPL v2");
673 MODULE_DESCRIPTION("TI QSPI controller driver");
674 MODULE_ALIAS("platform:ti-qspi");
675 

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