Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/spi/spi-sun6i.c

  1 /*
  2  * Copyright (C) 2012 - 2014 Allwinner Tech
  3  * Pan Nan <pannan@allwinnertech.com>
  4  *
  5  * Copyright (C) 2014 Maxime Ripard
  6  * Maxime Ripard <maxime.ripard@free-electrons.com>
  7  *
  8  * This program is free software; you can redistribute it and/or
  9  * modify it under the terms of the GNU General Public License as
 10  * published by the Free Software Foundation; either version 2 of
 11  * the License, or (at your option) any later version.
 12  */
 13 
 14 #include <linux/clk.h>
 15 #include <linux/delay.h>
 16 #include <linux/device.h>
 17 #include <linux/interrupt.h>
 18 #include <linux/io.h>
 19 #include <linux/module.h>
 20 #include <linux/platform_device.h>
 21 #include <linux/pm_runtime.h>
 22 #include <linux/reset.h>
 23 #include <linux/workqueue.h>
 24 
 25 #include <linux/spi/spi.h>
 26 
 27 #define SUN6I_FIFO_DEPTH                128
 28 
 29 #define SUN6I_GBL_CTL_REG               0x04
 30 #define SUN6I_GBL_CTL_BUS_ENABLE                BIT(0)
 31 #define SUN6I_GBL_CTL_MASTER                    BIT(1)
 32 #define SUN6I_GBL_CTL_TP                        BIT(7)
 33 #define SUN6I_GBL_CTL_RST                       BIT(31)
 34 
 35 #define SUN6I_TFR_CTL_REG               0x08
 36 #define SUN6I_TFR_CTL_CPHA                      BIT(0)
 37 #define SUN6I_TFR_CTL_CPOL                      BIT(1)
 38 #define SUN6I_TFR_CTL_SPOL                      BIT(2)
 39 #define SUN6I_TFR_CTL_CS_MASK                   0x30
 40 #define SUN6I_TFR_CTL_CS(cs)                    (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
 41 #define SUN6I_TFR_CTL_CS_MANUAL                 BIT(6)
 42 #define SUN6I_TFR_CTL_CS_LEVEL                  BIT(7)
 43 #define SUN6I_TFR_CTL_DHB                       BIT(8)
 44 #define SUN6I_TFR_CTL_FBS                       BIT(12)
 45 #define SUN6I_TFR_CTL_XCH                       BIT(31)
 46 
 47 #define SUN6I_INT_CTL_REG               0x10
 48 #define SUN6I_INT_CTL_RF_OVF                    BIT(8)
 49 #define SUN6I_INT_CTL_TC                        BIT(12)
 50 
 51 #define SUN6I_INT_STA_REG               0x14
 52 
 53 #define SUN6I_FIFO_CTL_REG              0x18
 54 #define SUN6I_FIFO_CTL_RF_RST                   BIT(15)
 55 #define SUN6I_FIFO_CTL_TF_RST                   BIT(31)
 56 
 57 #define SUN6I_FIFO_STA_REG              0x1c
 58 #define SUN6I_FIFO_STA_RF_CNT_MASK              0x7f
 59 #define SUN6I_FIFO_STA_RF_CNT_BITS              0
 60 #define SUN6I_FIFO_STA_TF_CNT_MASK              0x7f
 61 #define SUN6I_FIFO_STA_TF_CNT_BITS              16
 62 
 63 #define SUN6I_CLK_CTL_REG               0x24
 64 #define SUN6I_CLK_CTL_CDR2_MASK                 0xff
 65 #define SUN6I_CLK_CTL_CDR2(div)                 (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
 66 #define SUN6I_CLK_CTL_CDR1_MASK                 0xf
 67 #define SUN6I_CLK_CTL_CDR1(div)                 (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
 68 #define SUN6I_CLK_CTL_DRS                       BIT(12)
 69 
 70 #define SUN6I_BURST_CNT_REG             0x30
 71 #define SUN6I_BURST_CNT(cnt)                    ((cnt) & 0xffffff)
 72 
 73 #define SUN6I_XMIT_CNT_REG              0x34
 74 #define SUN6I_XMIT_CNT(cnt)                     ((cnt) & 0xffffff)
 75 
 76 #define SUN6I_BURST_CTL_CNT_REG         0x38
 77 #define SUN6I_BURST_CTL_CNT_STC(cnt)            ((cnt) & 0xffffff)
 78 
 79 #define SUN6I_TXDATA_REG                0x200
 80 #define SUN6I_RXDATA_REG                0x300
 81 
 82 struct sun6i_spi {
 83         struct spi_master       *master;
 84         void __iomem            *base_addr;
 85         struct clk              *hclk;
 86         struct clk              *mclk;
 87         struct reset_control    *rstc;
 88 
 89         struct completion       done;
 90 
 91         const u8                *tx_buf;
 92         u8                      *rx_buf;
 93         int                     len;
 94 };
 95 
 96 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
 97 {
 98         return readl(sspi->base_addr + reg);
 99 }
100 
101 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
102 {
103         writel(value, sspi->base_addr + reg);
104 }
105 
106 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
107 {
108         u32 reg, cnt;
109         u8 byte;
110 
111         /* See how much data is available */
112         reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
113         reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
114         cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
115 
116         if (len > cnt)
117                 len = cnt;
118 
119         while (len--) {
120                 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
121                 if (sspi->rx_buf)
122                         *sspi->rx_buf++ = byte;
123         }
124 }
125 
126 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
127 {
128         u8 byte;
129 
130         if (len > sspi->len)
131                 len = sspi->len;
132 
133         while (len--) {
134                 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
135                 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
136                 sspi->len--;
137         }
138 }
139 
140 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
141 {
142         struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
143         u32 reg;
144 
145         reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
146         reg &= ~SUN6I_TFR_CTL_CS_MASK;
147         reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
148 
149         if (enable)
150                 reg |= SUN6I_TFR_CTL_CS_LEVEL;
151         else
152                 reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
153 
154         sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
155 }
156 
157 
158 static int sun6i_spi_transfer_one(struct spi_master *master,
159                                   struct spi_device *spi,
160                                   struct spi_transfer *tfr)
161 {
162         struct sun6i_spi *sspi = spi_master_get_devdata(master);
163         unsigned int mclk_rate, div, timeout;
164         unsigned int tx_len = 0;
165         int ret = 0;
166         u32 reg;
167 
168         /* We don't support transfer larger than the FIFO */
169         if (tfr->len > SUN6I_FIFO_DEPTH)
170                 return -EINVAL;
171 
172         reinit_completion(&sspi->done);
173         sspi->tx_buf = tfr->tx_buf;
174         sspi->rx_buf = tfr->rx_buf;
175         sspi->len = tfr->len;
176 
177         /* Clear pending interrupts */
178         sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
179 
180         /* Reset FIFO */
181         sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
182                         SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
183 
184         /*
185          * Setup the transfer control register: Chip Select,
186          * polarities, etc.
187          */
188         reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
189 
190         if (spi->mode & SPI_CPOL)
191                 reg |= SUN6I_TFR_CTL_CPOL;
192         else
193                 reg &= ~SUN6I_TFR_CTL_CPOL;
194 
195         if (spi->mode & SPI_CPHA)
196                 reg |= SUN6I_TFR_CTL_CPHA;
197         else
198                 reg &= ~SUN6I_TFR_CTL_CPHA;
199 
200         if (spi->mode & SPI_LSB_FIRST)
201                 reg |= SUN6I_TFR_CTL_FBS;
202         else
203                 reg &= ~SUN6I_TFR_CTL_FBS;
204 
205         /*
206          * If it's a TX only transfer, we don't want to fill the RX
207          * FIFO with bogus data
208          */
209         if (sspi->rx_buf)
210                 reg &= ~SUN6I_TFR_CTL_DHB;
211         else
212                 reg |= SUN6I_TFR_CTL_DHB;
213 
214         /* We want to control the chip select manually */
215         reg |= SUN6I_TFR_CTL_CS_MANUAL;
216 
217         sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
218 
219         /* Ensure that we have a parent clock fast enough */
220         mclk_rate = clk_get_rate(sspi->mclk);
221         if (mclk_rate < (2 * spi->max_speed_hz)) {
222                 clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
223                 mclk_rate = clk_get_rate(sspi->mclk);
224         }
225 
226         /*
227          * Setup clock divider.
228          *
229          * We have two choices there. Either we can use the clock
230          * divide rate 1, which is calculated thanks to this formula:
231          * SPI_CLK = MOD_CLK / (2 ^ cdr)
232          * Or we can use CDR2, which is calculated with the formula:
233          * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
234          * Wether we use the former or the latter is set through the
235          * DRS bit.
236          *
237          * First try CDR2, and if we can't reach the expected
238          * frequency, fall back to CDR1.
239          */
240         div = mclk_rate / (2 * spi->max_speed_hz);
241         if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
242                 if (div > 0)
243                         div--;
244 
245                 reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
246         } else {
247                 div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
248                 reg = SUN6I_CLK_CTL_CDR1(div);
249         }
250 
251         sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
252 
253         /* Setup the transfer now... */
254         if (sspi->tx_buf)
255                 tx_len = tfr->len;
256 
257         /* Setup the counters */
258         sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
259         sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
260         sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
261                         SUN6I_BURST_CTL_CNT_STC(tx_len));
262 
263         /* Fill the TX FIFO */
264         sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
265 
266         /* Enable the interrupts */
267         sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
268 
269         /* Start the transfer */
270         reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
271         sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
272 
273         timeout = wait_for_completion_timeout(&sspi->done,
274                                               msecs_to_jiffies(1000));
275         if (!timeout) {
276                 ret = -ETIMEDOUT;
277                 goto out;
278         }
279 
280         sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
281 
282 out:
283         sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
284 
285         return ret;
286 }
287 
288 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
289 {
290         struct sun6i_spi *sspi = dev_id;
291         u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
292 
293         /* Transfer complete */
294         if (status & SUN6I_INT_CTL_TC) {
295                 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
296                 complete(&sspi->done);
297                 return IRQ_HANDLED;
298         }
299 
300         return IRQ_NONE;
301 }
302 
303 static int sun6i_spi_runtime_resume(struct device *dev)
304 {
305         struct spi_master *master = dev_get_drvdata(dev);
306         struct sun6i_spi *sspi = spi_master_get_devdata(master);
307         int ret;
308 
309         ret = clk_prepare_enable(sspi->hclk);
310         if (ret) {
311                 dev_err(dev, "Couldn't enable AHB clock\n");
312                 goto out;
313         }
314 
315         ret = clk_prepare_enable(sspi->mclk);
316         if (ret) {
317                 dev_err(dev, "Couldn't enable module clock\n");
318                 goto err;
319         }
320 
321         ret = reset_control_deassert(sspi->rstc);
322         if (ret) {
323                 dev_err(dev, "Couldn't deassert the device from reset\n");
324                 goto err2;
325         }
326 
327         sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
328                         SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
329 
330         return 0;
331 
332 err2:
333         clk_disable_unprepare(sspi->mclk);
334 err:
335         clk_disable_unprepare(sspi->hclk);
336 out:
337         return ret;
338 }
339 
340 static int sun6i_spi_runtime_suspend(struct device *dev)
341 {
342         struct spi_master *master = dev_get_drvdata(dev);
343         struct sun6i_spi *sspi = spi_master_get_devdata(master);
344 
345         reset_control_assert(sspi->rstc);
346         clk_disable_unprepare(sspi->mclk);
347         clk_disable_unprepare(sspi->hclk);
348 
349         return 0;
350 }
351 
352 static int sun6i_spi_probe(struct platform_device *pdev)
353 {
354         struct spi_master *master;
355         struct sun6i_spi *sspi;
356         struct resource *res;
357         int ret = 0, irq;
358 
359         master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
360         if (!master) {
361                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
362                 return -ENOMEM;
363         }
364 
365         platform_set_drvdata(pdev, master);
366         sspi = spi_master_get_devdata(master);
367 
368         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
369         sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
370         if (IS_ERR(sspi->base_addr)) {
371                 ret = PTR_ERR(sspi->base_addr);
372                 goto err_free_master;
373         }
374 
375         irq = platform_get_irq(pdev, 0);
376         if (irq < 0) {
377                 dev_err(&pdev->dev, "No spi IRQ specified\n");
378                 ret = -ENXIO;
379                 goto err_free_master;
380         }
381 
382         ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
383                                0, "sun6i-spi", sspi);
384         if (ret) {
385                 dev_err(&pdev->dev, "Cannot request IRQ\n");
386                 goto err_free_master;
387         }
388 
389         sspi->master = master;
390         master->set_cs = sun6i_spi_set_cs;
391         master->transfer_one = sun6i_spi_transfer_one;
392         master->num_chipselect = 4;
393         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
394         master->bits_per_word_mask = SPI_BPW_MASK(8);
395         master->dev.of_node = pdev->dev.of_node;
396         master->auto_runtime_pm = true;
397 
398         sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
399         if (IS_ERR(sspi->hclk)) {
400                 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
401                 ret = PTR_ERR(sspi->hclk);
402                 goto err_free_master;
403         }
404 
405         sspi->mclk = devm_clk_get(&pdev->dev, "mod");
406         if (IS_ERR(sspi->mclk)) {
407                 dev_err(&pdev->dev, "Unable to acquire module clock\n");
408                 ret = PTR_ERR(sspi->mclk);
409                 goto err_free_master;
410         }
411 
412         init_completion(&sspi->done);
413 
414         sspi->rstc = devm_reset_control_get(&pdev->dev, NULL);
415         if (IS_ERR(sspi->rstc)) {
416                 dev_err(&pdev->dev, "Couldn't get reset controller\n");
417                 ret = PTR_ERR(sspi->rstc);
418                 goto err_free_master;
419         }
420 
421         /*
422          * This wake-up/shutdown pattern is to be able to have the
423          * device woken up, even if runtime_pm is disabled
424          */
425         ret = sun6i_spi_runtime_resume(&pdev->dev);
426         if (ret) {
427                 dev_err(&pdev->dev, "Couldn't resume the device\n");
428                 goto err_free_master;
429         }
430 
431         pm_runtime_set_active(&pdev->dev);
432         pm_runtime_enable(&pdev->dev);
433         pm_runtime_idle(&pdev->dev);
434 
435         ret = devm_spi_register_master(&pdev->dev, master);
436         if (ret) {
437                 dev_err(&pdev->dev, "cannot register SPI master\n");
438                 goto err_pm_disable;
439         }
440 
441         return 0;
442 
443 err_pm_disable:
444         pm_runtime_disable(&pdev->dev);
445         sun6i_spi_runtime_suspend(&pdev->dev);
446 err_free_master:
447         spi_master_put(master);
448         return ret;
449 }
450 
451 static int sun6i_spi_remove(struct platform_device *pdev)
452 {
453         pm_runtime_disable(&pdev->dev);
454 
455         return 0;
456 }
457 
458 static const struct of_device_id sun6i_spi_match[] = {
459         { .compatible = "allwinner,sun6i-a31-spi", },
460         {}
461 };
462 MODULE_DEVICE_TABLE(of, sun6i_spi_match);
463 
464 static const struct dev_pm_ops sun6i_spi_pm_ops = {
465         .runtime_resume         = sun6i_spi_runtime_resume,
466         .runtime_suspend        = sun6i_spi_runtime_suspend,
467 };
468 
469 static struct platform_driver sun6i_spi_driver = {
470         .probe  = sun6i_spi_probe,
471         .remove = sun6i_spi_remove,
472         .driver = {
473                 .name           = "sun6i-spi",
474                 .owner          = THIS_MODULE,
475                 .of_match_table = sun6i_spi_match,
476                 .pm             = &sun6i_spi_pm_ops,
477         },
478 };
479 module_platform_driver(sun6i_spi_driver);
480 
481 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
482 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
483 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
484 MODULE_LICENSE("GPL");
485 

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