Version:  2.0.40 2.2.26 2.4.37 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7

Linux/drivers/spi/spi-sun6i.c

  1 /*
  2  * Copyright (C) 2012 - 2014 Allwinner Tech
  3  * Pan Nan <pannan@allwinnertech.com>
  4  *
  5  * Copyright (C) 2014 Maxime Ripard
  6  * Maxime Ripard <maxime.ripard@free-electrons.com>
  7  *
  8  * This program is free software; you can redistribute it and/or
  9  * modify it under the terms of the GNU General Public License as
 10  * published by the Free Software Foundation; either version 2 of
 11  * the License, or (at your option) any later version.
 12  */
 13 
 14 #include <linux/clk.h>
 15 #include <linux/delay.h>
 16 #include <linux/device.h>
 17 #include <linux/interrupt.h>
 18 #include <linux/io.h>
 19 #include <linux/module.h>
 20 #include <linux/platform_device.h>
 21 #include <linux/pm_runtime.h>
 22 #include <linux/reset.h>
 23 
 24 #include <linux/spi/spi.h>
 25 
 26 #define SUN6I_FIFO_DEPTH                128
 27 
 28 #define SUN6I_GBL_CTL_REG               0x04
 29 #define SUN6I_GBL_CTL_BUS_ENABLE                BIT(0)
 30 #define SUN6I_GBL_CTL_MASTER                    BIT(1)
 31 #define SUN6I_GBL_CTL_TP                        BIT(7)
 32 #define SUN6I_GBL_CTL_RST                       BIT(31)
 33 
 34 #define SUN6I_TFR_CTL_REG               0x08
 35 #define SUN6I_TFR_CTL_CPHA                      BIT(0)
 36 #define SUN6I_TFR_CTL_CPOL                      BIT(1)
 37 #define SUN6I_TFR_CTL_SPOL                      BIT(2)
 38 #define SUN6I_TFR_CTL_CS_MASK                   0x30
 39 #define SUN6I_TFR_CTL_CS(cs)                    (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
 40 #define SUN6I_TFR_CTL_CS_MANUAL                 BIT(6)
 41 #define SUN6I_TFR_CTL_CS_LEVEL                  BIT(7)
 42 #define SUN6I_TFR_CTL_DHB                       BIT(8)
 43 #define SUN6I_TFR_CTL_FBS                       BIT(12)
 44 #define SUN6I_TFR_CTL_XCH                       BIT(31)
 45 
 46 #define SUN6I_INT_CTL_REG               0x10
 47 #define SUN6I_INT_CTL_RF_OVF                    BIT(8)
 48 #define SUN6I_INT_CTL_TC                        BIT(12)
 49 
 50 #define SUN6I_INT_STA_REG               0x14
 51 
 52 #define SUN6I_FIFO_CTL_REG              0x18
 53 #define SUN6I_FIFO_CTL_RF_RST                   BIT(15)
 54 #define SUN6I_FIFO_CTL_TF_RST                   BIT(31)
 55 
 56 #define SUN6I_FIFO_STA_REG              0x1c
 57 #define SUN6I_FIFO_STA_RF_CNT_MASK              0x7f
 58 #define SUN6I_FIFO_STA_RF_CNT_BITS              0
 59 #define SUN6I_FIFO_STA_TF_CNT_MASK              0x7f
 60 #define SUN6I_FIFO_STA_TF_CNT_BITS              16
 61 
 62 #define SUN6I_CLK_CTL_REG               0x24
 63 #define SUN6I_CLK_CTL_CDR2_MASK                 0xff
 64 #define SUN6I_CLK_CTL_CDR2(div)                 (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
 65 #define SUN6I_CLK_CTL_CDR1_MASK                 0xf
 66 #define SUN6I_CLK_CTL_CDR1(div)                 (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
 67 #define SUN6I_CLK_CTL_DRS                       BIT(12)
 68 
 69 #define SUN6I_BURST_CNT_REG             0x30
 70 #define SUN6I_BURST_CNT(cnt)                    ((cnt) & 0xffffff)
 71 
 72 #define SUN6I_XMIT_CNT_REG              0x34
 73 #define SUN6I_XMIT_CNT(cnt)                     ((cnt) & 0xffffff)
 74 
 75 #define SUN6I_BURST_CTL_CNT_REG         0x38
 76 #define SUN6I_BURST_CTL_CNT_STC(cnt)            ((cnt) & 0xffffff)
 77 
 78 #define SUN6I_TXDATA_REG                0x200
 79 #define SUN6I_RXDATA_REG                0x300
 80 
 81 struct sun6i_spi {
 82         struct spi_master       *master;
 83         void __iomem            *base_addr;
 84         struct clk              *hclk;
 85         struct clk              *mclk;
 86         struct reset_control    *rstc;
 87 
 88         struct completion       done;
 89 
 90         const u8                *tx_buf;
 91         u8                      *rx_buf;
 92         int                     len;
 93 };
 94 
 95 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
 96 {
 97         return readl(sspi->base_addr + reg);
 98 }
 99 
100 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
101 {
102         writel(value, sspi->base_addr + reg);
103 }
104 
105 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
106 {
107         u32 reg, cnt;
108         u8 byte;
109 
110         /* See how much data is available */
111         reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
112         reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
113         cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
114 
115         if (len > cnt)
116                 len = cnt;
117 
118         while (len--) {
119                 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
120                 if (sspi->rx_buf)
121                         *sspi->rx_buf++ = byte;
122         }
123 }
124 
125 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
126 {
127         u8 byte;
128 
129         if (len > sspi->len)
130                 len = sspi->len;
131 
132         while (len--) {
133                 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
134                 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
135                 sspi->len--;
136         }
137 }
138 
139 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
140 {
141         struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
142         u32 reg;
143 
144         reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
145         reg &= ~SUN6I_TFR_CTL_CS_MASK;
146         reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
147 
148         if (enable)
149                 reg |= SUN6I_TFR_CTL_CS_LEVEL;
150         else
151                 reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
152 
153         sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
154 }
155 
156 
157 static int sun6i_spi_transfer_one(struct spi_master *master,
158                                   struct spi_device *spi,
159                                   struct spi_transfer *tfr)
160 {
161         struct sun6i_spi *sspi = spi_master_get_devdata(master);
162         unsigned int mclk_rate, div, timeout;
163         unsigned int start, end, tx_time;
164         unsigned int tx_len = 0;
165         int ret = 0;
166         u32 reg;
167 
168         /* We don't support transfer larger than the FIFO */
169         if (tfr->len > SUN6I_FIFO_DEPTH)
170                 return -EINVAL;
171 
172         reinit_completion(&sspi->done);
173         sspi->tx_buf = tfr->tx_buf;
174         sspi->rx_buf = tfr->rx_buf;
175         sspi->len = tfr->len;
176 
177         /* Clear pending interrupts */
178         sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
179 
180         /* Reset FIFO */
181         sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
182                         SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
183 
184         /*
185          * Setup the transfer control register: Chip Select,
186          * polarities, etc.
187          */
188         reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
189 
190         if (spi->mode & SPI_CPOL)
191                 reg |= SUN6I_TFR_CTL_CPOL;
192         else
193                 reg &= ~SUN6I_TFR_CTL_CPOL;
194 
195         if (spi->mode & SPI_CPHA)
196                 reg |= SUN6I_TFR_CTL_CPHA;
197         else
198                 reg &= ~SUN6I_TFR_CTL_CPHA;
199 
200         if (spi->mode & SPI_LSB_FIRST)
201                 reg |= SUN6I_TFR_CTL_FBS;
202         else
203                 reg &= ~SUN6I_TFR_CTL_FBS;
204 
205         /*
206          * If it's a TX only transfer, we don't want to fill the RX
207          * FIFO with bogus data
208          */
209         if (sspi->rx_buf)
210                 reg &= ~SUN6I_TFR_CTL_DHB;
211         else
212                 reg |= SUN6I_TFR_CTL_DHB;
213 
214         /* We want to control the chip select manually */
215         reg |= SUN6I_TFR_CTL_CS_MANUAL;
216 
217         sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
218 
219         /* Ensure that we have a parent clock fast enough */
220         mclk_rate = clk_get_rate(sspi->mclk);
221         if (mclk_rate < (2 * tfr->speed_hz)) {
222                 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
223                 mclk_rate = clk_get_rate(sspi->mclk);
224         }
225 
226         /*
227          * Setup clock divider.
228          *
229          * We have two choices there. Either we can use the clock
230          * divide rate 1, which is calculated thanks to this formula:
231          * SPI_CLK = MOD_CLK / (2 ^ cdr)
232          * Or we can use CDR2, which is calculated with the formula:
233          * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
234          * Wether we use the former or the latter is set through the
235          * DRS bit.
236          *
237          * First try CDR2, and if we can't reach the expected
238          * frequency, fall back to CDR1.
239          */
240         div = mclk_rate / (2 * tfr->speed_hz);
241         if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
242                 if (div > 0)
243                         div--;
244 
245                 reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
246         } else {
247                 div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
248                 reg = SUN6I_CLK_CTL_CDR1(div);
249         }
250 
251         sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
252 
253         /* Setup the transfer now... */
254         if (sspi->tx_buf)
255                 tx_len = tfr->len;
256 
257         /* Setup the counters */
258         sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
259         sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
260         sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
261                         SUN6I_BURST_CTL_CNT_STC(tx_len));
262 
263         /* Fill the TX FIFO */
264         sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
265 
266         /* Enable the interrupts */
267         sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
268 
269         /* Start the transfer */
270         reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
271         sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
272 
273         tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
274         start = jiffies;
275         timeout = wait_for_completion_timeout(&sspi->done,
276                                               msecs_to_jiffies(tx_time));
277         end = jiffies;
278         if (!timeout) {
279                 dev_warn(&master->dev,
280                          "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
281                          dev_name(&spi->dev), tfr->len, tfr->speed_hz,
282                          jiffies_to_msecs(end - start), tx_time);
283                 ret = -ETIMEDOUT;
284                 goto out;
285         }
286 
287         sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
288 
289 out:
290         sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
291 
292         return ret;
293 }
294 
295 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
296 {
297         struct sun6i_spi *sspi = dev_id;
298         u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
299 
300         /* Transfer complete */
301         if (status & SUN6I_INT_CTL_TC) {
302                 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
303                 complete(&sspi->done);
304                 return IRQ_HANDLED;
305         }
306 
307         return IRQ_NONE;
308 }
309 
310 static int sun6i_spi_runtime_resume(struct device *dev)
311 {
312         struct spi_master *master = dev_get_drvdata(dev);
313         struct sun6i_spi *sspi = spi_master_get_devdata(master);
314         int ret;
315 
316         ret = clk_prepare_enable(sspi->hclk);
317         if (ret) {
318                 dev_err(dev, "Couldn't enable AHB clock\n");
319                 goto out;
320         }
321 
322         ret = clk_prepare_enable(sspi->mclk);
323         if (ret) {
324                 dev_err(dev, "Couldn't enable module clock\n");
325                 goto err;
326         }
327 
328         ret = reset_control_deassert(sspi->rstc);
329         if (ret) {
330                 dev_err(dev, "Couldn't deassert the device from reset\n");
331                 goto err2;
332         }
333 
334         sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
335                         SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
336 
337         return 0;
338 
339 err2:
340         clk_disable_unprepare(sspi->mclk);
341 err:
342         clk_disable_unprepare(sspi->hclk);
343 out:
344         return ret;
345 }
346 
347 static int sun6i_spi_runtime_suspend(struct device *dev)
348 {
349         struct spi_master *master = dev_get_drvdata(dev);
350         struct sun6i_spi *sspi = spi_master_get_devdata(master);
351 
352         reset_control_assert(sspi->rstc);
353         clk_disable_unprepare(sspi->mclk);
354         clk_disable_unprepare(sspi->hclk);
355 
356         return 0;
357 }
358 
359 static int sun6i_spi_probe(struct platform_device *pdev)
360 {
361         struct spi_master *master;
362         struct sun6i_spi *sspi;
363         struct resource *res;
364         int ret = 0, irq;
365 
366         master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
367         if (!master) {
368                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
369                 return -ENOMEM;
370         }
371 
372         platform_set_drvdata(pdev, master);
373         sspi = spi_master_get_devdata(master);
374 
375         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
376         sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
377         if (IS_ERR(sspi->base_addr)) {
378                 ret = PTR_ERR(sspi->base_addr);
379                 goto err_free_master;
380         }
381 
382         irq = platform_get_irq(pdev, 0);
383         if (irq < 0) {
384                 dev_err(&pdev->dev, "No spi IRQ specified\n");
385                 ret = -ENXIO;
386                 goto err_free_master;
387         }
388 
389         ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
390                                0, "sun6i-spi", sspi);
391         if (ret) {
392                 dev_err(&pdev->dev, "Cannot request IRQ\n");
393                 goto err_free_master;
394         }
395 
396         sspi->master = master;
397         master->set_cs = sun6i_spi_set_cs;
398         master->transfer_one = sun6i_spi_transfer_one;
399         master->num_chipselect = 4;
400         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
401         master->bits_per_word_mask = SPI_BPW_MASK(8);
402         master->dev.of_node = pdev->dev.of_node;
403         master->auto_runtime_pm = true;
404 
405         sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
406         if (IS_ERR(sspi->hclk)) {
407                 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
408                 ret = PTR_ERR(sspi->hclk);
409                 goto err_free_master;
410         }
411 
412         sspi->mclk = devm_clk_get(&pdev->dev, "mod");
413         if (IS_ERR(sspi->mclk)) {
414                 dev_err(&pdev->dev, "Unable to acquire module clock\n");
415                 ret = PTR_ERR(sspi->mclk);
416                 goto err_free_master;
417         }
418 
419         init_completion(&sspi->done);
420 
421         sspi->rstc = devm_reset_control_get(&pdev->dev, NULL);
422         if (IS_ERR(sspi->rstc)) {
423                 dev_err(&pdev->dev, "Couldn't get reset controller\n");
424                 ret = PTR_ERR(sspi->rstc);
425                 goto err_free_master;
426         }
427 
428         /*
429          * This wake-up/shutdown pattern is to be able to have the
430          * device woken up, even if runtime_pm is disabled
431          */
432         ret = sun6i_spi_runtime_resume(&pdev->dev);
433         if (ret) {
434                 dev_err(&pdev->dev, "Couldn't resume the device\n");
435                 goto err_free_master;
436         }
437 
438         pm_runtime_set_active(&pdev->dev);
439         pm_runtime_enable(&pdev->dev);
440         pm_runtime_idle(&pdev->dev);
441 
442         ret = devm_spi_register_master(&pdev->dev, master);
443         if (ret) {
444                 dev_err(&pdev->dev, "cannot register SPI master\n");
445                 goto err_pm_disable;
446         }
447 
448         return 0;
449 
450 err_pm_disable:
451         pm_runtime_disable(&pdev->dev);
452         sun6i_spi_runtime_suspend(&pdev->dev);
453 err_free_master:
454         spi_master_put(master);
455         return ret;
456 }
457 
458 static int sun6i_spi_remove(struct platform_device *pdev)
459 {
460         pm_runtime_disable(&pdev->dev);
461 
462         return 0;
463 }
464 
465 static const struct of_device_id sun6i_spi_match[] = {
466         { .compatible = "allwinner,sun6i-a31-spi", },
467         {}
468 };
469 MODULE_DEVICE_TABLE(of, sun6i_spi_match);
470 
471 static const struct dev_pm_ops sun6i_spi_pm_ops = {
472         .runtime_resume         = sun6i_spi_runtime_resume,
473         .runtime_suspend        = sun6i_spi_runtime_suspend,
474 };
475 
476 static struct platform_driver sun6i_spi_driver = {
477         .probe  = sun6i_spi_probe,
478         .remove = sun6i_spi_remove,
479         .driver = {
480                 .name           = "sun6i-spi",
481                 .of_match_table = sun6i_spi_match,
482                 .pm             = &sun6i_spi_pm_ops,
483         },
484 };
485 module_platform_driver(sun6i_spi_driver);
486 
487 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
488 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
489 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
490 MODULE_LICENSE("GPL");
491 

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