Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/spi/spi-sun4i.c

  1 /*
  2  * Copyright (C) 2012 - 2014 Allwinner Tech
  3  * Pan Nan <pannan@allwinnertech.com>
  4  *
  5  * Copyright (C) 2014 Maxime Ripard
  6  * Maxime Ripard <maxime.ripard@free-electrons.com>
  7  *
  8  * This program is free software; you can redistribute it and/or
  9  * modify it under the terms of the GNU General Public License as
 10  * published by the Free Software Foundation; either version 2 of
 11  * the License, or (at your option) any later version.
 12  */
 13 
 14 #include <linux/clk.h>
 15 #include <linux/delay.h>
 16 #include <linux/device.h>
 17 #include <linux/interrupt.h>
 18 #include <linux/io.h>
 19 #include <linux/module.h>
 20 #include <linux/platform_device.h>
 21 #include <linux/pm_runtime.h>
 22 
 23 #include <linux/spi/spi.h>
 24 
 25 #define SUN4I_FIFO_DEPTH                64
 26 
 27 #define SUN4I_RXDATA_REG                0x00
 28 
 29 #define SUN4I_TXDATA_REG                0x04
 30 
 31 #define SUN4I_CTL_REG                   0x08
 32 #define SUN4I_CTL_ENABLE                        BIT(0)
 33 #define SUN4I_CTL_MASTER                        BIT(1)
 34 #define SUN4I_CTL_CPHA                          BIT(2)
 35 #define SUN4I_CTL_CPOL                          BIT(3)
 36 #define SUN4I_CTL_CS_ACTIVE_LOW                 BIT(4)
 37 #define SUN4I_CTL_LMTF                          BIT(6)
 38 #define SUN4I_CTL_TF_RST                        BIT(8)
 39 #define SUN4I_CTL_RF_RST                        BIT(9)
 40 #define SUN4I_CTL_XCH                           BIT(10)
 41 #define SUN4I_CTL_CS_MASK                       0x3000
 42 #define SUN4I_CTL_CS(cs)                        (((cs) << 12) & SUN4I_CTL_CS_MASK)
 43 #define SUN4I_CTL_DHB                           BIT(15)
 44 #define SUN4I_CTL_CS_MANUAL                     BIT(16)
 45 #define SUN4I_CTL_CS_LEVEL                      BIT(17)
 46 #define SUN4I_CTL_TP                            BIT(18)
 47 
 48 #define SUN4I_INT_CTL_REG               0x0c
 49 #define SUN4I_INT_CTL_TC                        BIT(16)
 50 
 51 #define SUN4I_INT_STA_REG               0x10
 52 
 53 #define SUN4I_DMA_CTL_REG               0x14
 54 
 55 #define SUN4I_WAIT_REG                  0x18
 56 
 57 #define SUN4I_CLK_CTL_REG               0x1c
 58 #define SUN4I_CLK_CTL_CDR2_MASK                 0xff
 59 #define SUN4I_CLK_CTL_CDR2(div)                 ((div) & SUN4I_CLK_CTL_CDR2_MASK)
 60 #define SUN4I_CLK_CTL_CDR1_MASK                 0xf
 61 #define SUN4I_CLK_CTL_CDR1(div)                 (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
 62 #define SUN4I_CLK_CTL_DRS                       BIT(12)
 63 
 64 #define SUN4I_BURST_CNT_REG             0x20
 65 #define SUN4I_BURST_CNT(cnt)                    ((cnt) & 0xffffff)
 66 
 67 #define SUN4I_XMIT_CNT_REG              0x24
 68 #define SUN4I_XMIT_CNT(cnt)                     ((cnt) & 0xffffff)
 69 
 70 #define SUN4I_FIFO_STA_REG              0x28
 71 #define SUN4I_FIFO_STA_RF_CNT_MASK              0x7f
 72 #define SUN4I_FIFO_STA_RF_CNT_BITS              0
 73 #define SUN4I_FIFO_STA_TF_CNT_MASK              0x7f
 74 #define SUN4I_FIFO_STA_TF_CNT_BITS              16
 75 
 76 struct sun4i_spi {
 77         struct spi_master       *master;
 78         void __iomem            *base_addr;
 79         struct clk              *hclk;
 80         struct clk              *mclk;
 81 
 82         struct completion       done;
 83 
 84         const u8                *tx_buf;
 85         u8                      *rx_buf;
 86         int                     len;
 87 };
 88 
 89 static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
 90 {
 91         return readl(sspi->base_addr + reg);
 92 }
 93 
 94 static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value)
 95 {
 96         writel(value, sspi->base_addr + reg);
 97 }
 98 
 99 static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
100 {
101         u32 reg, cnt;
102         u8 byte;
103 
104         /* See how much data is available */
105         reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
106         reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
107         cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
108 
109         if (len > cnt)
110                 len = cnt;
111 
112         while (len--) {
113                 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
114                 if (sspi->rx_buf)
115                         *sspi->rx_buf++ = byte;
116         }
117 }
118 
119 static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
120 {
121         u8 byte;
122 
123         if (len > sspi->len)
124                 len = sspi->len;
125 
126         while (len--) {
127                 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
128                 writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG);
129                 sspi->len--;
130         }
131 }
132 
133 static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
134 {
135         struct sun4i_spi *sspi = spi_master_get_devdata(spi->master);
136         u32 reg;
137 
138         reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
139 
140         reg &= ~SUN4I_CTL_CS_MASK;
141         reg |= SUN4I_CTL_CS(spi->chip_select);
142 
143         if (enable)
144                 reg |= SUN4I_CTL_CS_LEVEL;
145         else
146                 reg &= ~SUN4I_CTL_CS_LEVEL;
147 
148         /*
149          * Even though this looks irrelevant since we are supposed to
150          * be controlling the chip select manually, this bit also
151          * controls the levels of the chip select for inactive
152          * devices.
153          *
154          * If we don't set it, the chip select level will go low by
155          * default when the device is idle, which is not really
156          * expected in the common case where the chip select is active
157          * low.
158          */
159         if (spi->mode & SPI_CS_HIGH)
160                 reg &= ~SUN4I_CTL_CS_ACTIVE_LOW;
161         else
162                 reg |= SUN4I_CTL_CS_ACTIVE_LOW;
163 
164         sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
165 }
166 
167 static int sun4i_spi_transfer_one(struct spi_master *master,
168                                   struct spi_device *spi,
169                                   struct spi_transfer *tfr)
170 {
171         struct sun4i_spi *sspi = spi_master_get_devdata(master);
172         unsigned int mclk_rate, div, timeout;
173         unsigned int tx_len = 0;
174         int ret = 0;
175         u32 reg;
176 
177         /* We don't support transfer larger than the FIFO */
178         if (tfr->len > SUN4I_FIFO_DEPTH)
179                 return -EINVAL;
180 
181         reinit_completion(&sspi->done);
182         sspi->tx_buf = tfr->tx_buf;
183         sspi->rx_buf = tfr->rx_buf;
184         sspi->len = tfr->len;
185 
186         /* Clear pending interrupts */
187         sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
188 
189 
190         reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
191 
192         /* Reset FIFOs */
193         sun4i_spi_write(sspi, SUN4I_CTL_REG,
194                         reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST);
195 
196         /*
197          * Setup the transfer control register: Chip Select,
198          * polarities, etc.
199          */
200         if (spi->mode & SPI_CPOL)
201                 reg |= SUN4I_CTL_CPOL;
202         else
203                 reg &= ~SUN4I_CTL_CPOL;
204 
205         if (spi->mode & SPI_CPHA)
206                 reg |= SUN4I_CTL_CPHA;
207         else
208                 reg &= ~SUN4I_CTL_CPHA;
209 
210         if (spi->mode & SPI_LSB_FIRST)
211                 reg |= SUN4I_CTL_LMTF;
212         else
213                 reg &= ~SUN4I_CTL_LMTF;
214 
215 
216         /*
217          * If it's a TX only transfer, we don't want to fill the RX
218          * FIFO with bogus data
219          */
220         if (sspi->rx_buf)
221                 reg &= ~SUN4I_CTL_DHB;
222         else
223                 reg |= SUN4I_CTL_DHB;
224 
225         /* We want to control the chip select manually */
226         reg |= SUN4I_CTL_CS_MANUAL;
227 
228         sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
229 
230         /* Ensure that we have a parent clock fast enough */
231         mclk_rate = clk_get_rate(sspi->mclk);
232         if (mclk_rate < (2 * spi->max_speed_hz)) {
233                 clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
234                 mclk_rate = clk_get_rate(sspi->mclk);
235         }
236 
237         /*
238          * Setup clock divider.
239          *
240          * We have two choices there. Either we can use the clock
241          * divide rate 1, which is calculated thanks to this formula:
242          * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
243          * Or we can use CDR2, which is calculated with the formula:
244          * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
245          * Wether we use the former or the latter is set through the
246          * DRS bit.
247          *
248          * First try CDR2, and if we can't reach the expected
249          * frequency, fall back to CDR1.
250          */
251         div = mclk_rate / (2 * spi->max_speed_hz);
252         if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
253                 if (div > 0)
254                         div--;
255 
256                 reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
257         } else {
258                 div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
259                 reg = SUN4I_CLK_CTL_CDR1(div);
260         }
261 
262         sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg);
263 
264         /* Setup the transfer now... */
265         if (sspi->tx_buf)
266                 tx_len = tfr->len;
267 
268         /* Setup the counters */
269         sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
270         sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
271 
272         /* Fill the TX FIFO */
273         sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
274 
275         /* Enable the interrupts */
276         sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
277 
278         /* Start the transfer */
279         reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
280         sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
281 
282         timeout = wait_for_completion_timeout(&sspi->done,
283                                               msecs_to_jiffies(1000));
284         if (!timeout) {
285                 ret = -ETIMEDOUT;
286                 goto out;
287         }
288 
289         sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
290 
291 out:
292         sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
293 
294         return ret;
295 }
296 
297 static irqreturn_t sun4i_spi_handler(int irq, void *dev_id)
298 {
299         struct sun4i_spi *sspi = dev_id;
300         u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG);
301 
302         /* Transfer complete */
303         if (status & SUN4I_INT_CTL_TC) {
304                 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);
305                 complete(&sspi->done);
306                 return IRQ_HANDLED;
307         }
308 
309         return IRQ_NONE;
310 }
311 
312 static int sun4i_spi_runtime_resume(struct device *dev)
313 {
314         struct spi_master *master = dev_get_drvdata(dev);
315         struct sun4i_spi *sspi = spi_master_get_devdata(master);
316         int ret;
317 
318         ret = clk_prepare_enable(sspi->hclk);
319         if (ret) {
320                 dev_err(dev, "Couldn't enable AHB clock\n");
321                 goto out;
322         }
323 
324         ret = clk_prepare_enable(sspi->mclk);
325         if (ret) {
326                 dev_err(dev, "Couldn't enable module clock\n");
327                 goto err;
328         }
329 
330         sun4i_spi_write(sspi, SUN4I_CTL_REG,
331                         SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);
332 
333         return 0;
334 
335 err:
336         clk_disable_unprepare(sspi->hclk);
337 out:
338         return ret;
339 }
340 
341 static int sun4i_spi_runtime_suspend(struct device *dev)
342 {
343         struct spi_master *master = dev_get_drvdata(dev);
344         struct sun4i_spi *sspi = spi_master_get_devdata(master);
345 
346         clk_disable_unprepare(sspi->mclk);
347         clk_disable_unprepare(sspi->hclk);
348 
349         return 0;
350 }
351 
352 static int sun4i_spi_probe(struct platform_device *pdev)
353 {
354         struct spi_master *master;
355         struct sun4i_spi *sspi;
356         struct resource *res;
357         int ret = 0, irq;
358 
359         master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi));
360         if (!master) {
361                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
362                 return -ENOMEM;
363         }
364 
365         platform_set_drvdata(pdev, master);
366         sspi = spi_master_get_devdata(master);
367 
368         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
369         sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
370         if (IS_ERR(sspi->base_addr)) {
371                 ret = PTR_ERR(sspi->base_addr);
372                 goto err_free_master;
373         }
374 
375         irq = platform_get_irq(pdev, 0);
376         if (irq < 0) {
377                 dev_err(&pdev->dev, "No spi IRQ specified\n");
378                 ret = -ENXIO;
379                 goto err_free_master;
380         }
381 
382         ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler,
383                                0, "sun4i-spi", sspi);
384         if (ret) {
385                 dev_err(&pdev->dev, "Cannot request IRQ\n");
386                 goto err_free_master;
387         }
388 
389         sspi->master = master;
390         master->set_cs = sun4i_spi_set_cs;
391         master->transfer_one = sun4i_spi_transfer_one;
392         master->num_chipselect = 4;
393         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
394         master->bits_per_word_mask = SPI_BPW_MASK(8);
395         master->dev.of_node = pdev->dev.of_node;
396         master->auto_runtime_pm = true;
397 
398         sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
399         if (IS_ERR(sspi->hclk)) {
400                 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
401                 ret = PTR_ERR(sspi->hclk);
402                 goto err_free_master;
403         }
404 
405         sspi->mclk = devm_clk_get(&pdev->dev, "mod");
406         if (IS_ERR(sspi->mclk)) {
407                 dev_err(&pdev->dev, "Unable to acquire module clock\n");
408                 ret = PTR_ERR(sspi->mclk);
409                 goto err_free_master;
410         }
411 
412         init_completion(&sspi->done);
413 
414         /*
415          * This wake-up/shutdown pattern is to be able to have the
416          * device woken up, even if runtime_pm is disabled
417          */
418         ret = sun4i_spi_runtime_resume(&pdev->dev);
419         if (ret) {
420                 dev_err(&pdev->dev, "Couldn't resume the device\n");
421                 goto err_free_master;
422         }
423 
424         pm_runtime_set_active(&pdev->dev);
425         pm_runtime_enable(&pdev->dev);
426         pm_runtime_idle(&pdev->dev);
427 
428         ret = devm_spi_register_master(&pdev->dev, master);
429         if (ret) {
430                 dev_err(&pdev->dev, "cannot register SPI master\n");
431                 goto err_pm_disable;
432         }
433 
434         return 0;
435 
436 err_pm_disable:
437         pm_runtime_disable(&pdev->dev);
438         sun4i_spi_runtime_suspend(&pdev->dev);
439 err_free_master:
440         spi_master_put(master);
441         return ret;
442 }
443 
444 static int sun4i_spi_remove(struct platform_device *pdev)
445 {
446         pm_runtime_disable(&pdev->dev);
447 
448         return 0;
449 }
450 
451 static const struct of_device_id sun4i_spi_match[] = {
452         { .compatible = "allwinner,sun4i-a10-spi", },
453         {}
454 };
455 MODULE_DEVICE_TABLE(of, sun4i_spi_match);
456 
457 static const struct dev_pm_ops sun4i_spi_pm_ops = {
458         .runtime_resume         = sun4i_spi_runtime_resume,
459         .runtime_suspend        = sun4i_spi_runtime_suspend,
460 };
461 
462 static struct platform_driver sun4i_spi_driver = {
463         .probe  = sun4i_spi_probe,
464         .remove = sun4i_spi_remove,
465         .driver = {
466                 .name           = "sun4i-spi",
467                 .owner          = THIS_MODULE,
468                 .of_match_table = sun4i_spi_match,
469                 .pm             = &sun4i_spi_pm_ops,
470         },
471 };
472 module_platform_driver(sun4i_spi_driver);
473 
474 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
475 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
476 MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver");
477 MODULE_LICENSE("GPL");
478 

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