Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/drivers/spi/spi-s3c64xx.c

  1 /*
  2  * Copyright (C) 2009 Samsung Electronics Ltd.
  3  *      Jaswinder Singh <jassi.brar@samsung.com>
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License as published by
  7  * the Free Software Foundation; either version 2 of the License, or
  8  * (at your option) any later version.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  */
 15 
 16 #include <linux/init.h>
 17 #include <linux/module.h>
 18 #include <linux/interrupt.h>
 19 #include <linux/delay.h>
 20 #include <linux/clk.h>
 21 #include <linux/dma-mapping.h>
 22 #include <linux/dmaengine.h>
 23 #include <linux/platform_device.h>
 24 #include <linux/pm_runtime.h>
 25 #include <linux/spi/spi.h>
 26 #include <linux/gpio.h>
 27 #include <linux/of.h>
 28 #include <linux/of_gpio.h>
 29 
 30 #include <linux/platform_data/spi-s3c64xx.h>
 31 
 32 #define MAX_SPI_PORTS           6
 33 #define S3C64XX_SPI_QUIRK_POLL          (1 << 0)
 34 #define S3C64XX_SPI_QUIRK_CS_AUTO       (1 << 1)
 35 #define AUTOSUSPEND_TIMEOUT     2000
 36 
 37 /* Registers and bit-fields */
 38 
 39 #define S3C64XX_SPI_CH_CFG              0x00
 40 #define S3C64XX_SPI_CLK_CFG             0x04
 41 #define S3C64XX_SPI_MODE_CFG    0x08
 42 #define S3C64XX_SPI_SLAVE_SEL   0x0C
 43 #define S3C64XX_SPI_INT_EN              0x10
 44 #define S3C64XX_SPI_STATUS              0x14
 45 #define S3C64XX_SPI_TX_DATA             0x18
 46 #define S3C64XX_SPI_RX_DATA             0x1C
 47 #define S3C64XX_SPI_PACKET_CNT  0x20
 48 #define S3C64XX_SPI_PENDING_CLR 0x24
 49 #define S3C64XX_SPI_SWAP_CFG    0x28
 50 #define S3C64XX_SPI_FB_CLK              0x2C
 51 
 52 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
 53 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
 54 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
 55 #define S3C64XX_SPI_CPOL_L              (1<<3)
 56 #define S3C64XX_SPI_CPHA_B              (1<<2)
 57 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
 58 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
 59 
 60 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
 61 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
 62 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
 63 #define S3C64XX_SPI_PSR_MASK            0xff
 64 
 65 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
 66 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
 67 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
 68 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
 69 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
 70 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
 71 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
 72 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
 73 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
 74 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
 75 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
 76 
 77 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
 78 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
 79 #define S3C64XX_SPI_SLAVE_NSC_CNT_2             (2<<4)
 80 
 81 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
 82 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
 83 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
 84 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
 85 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
 86 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
 87 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
 88 
 89 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
 90 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
 91 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
 92 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
 93 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
 94 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
 95 
 96 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
 97 
 98 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
 99 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
100 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
101 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
102 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
103 
104 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
105 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
106 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
107 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
108 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
109 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
110 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
111 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
112 
113 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
114 
115 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
116 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
117                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
118 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
119 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
120                                         FIFO_LVL_MASK(i))
121 
122 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
123 #define S3C64XX_SPI_TRAILCNT_OFF        19
124 
125 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
126 
127 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
128 #define is_polling(x)   (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
129 
130 #define RXBUSY    (1<<2)
131 #define TXBUSY    (1<<3)
132 
133 struct s3c64xx_spi_dma_data {
134         struct dma_chan *ch;
135         enum dma_transfer_direction direction;
136 };
137 
138 /**
139  * struct s3c64xx_spi_info - SPI Controller hardware info
140  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
141  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
142  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
143  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
144  * @clk_from_cmu: True, if the controller does not include a clock mux and
145  *      prescaler unit.
146  *
147  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
148  * differ in some aspects such as the size of the fifo and spi bus clock
149  * setup. Such differences are specified to the driver using this structure
150  * which is provided as driver data to the driver.
151  */
152 struct s3c64xx_spi_port_config {
153         int     fifo_lvl_mask[MAX_SPI_PORTS];
154         int     rx_lvl_offset;
155         int     tx_st_done;
156         int     quirks;
157         bool    high_speed;
158         bool    clk_from_cmu;
159         bool    clk_ioclk;
160 };
161 
162 /**
163  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
164  * @clk: Pointer to the spi clock.
165  * @src_clk: Pointer to the clock used to generate SPI signals.
166  * @ioclk: Pointer to the i/o clock between master and slave
167  * @master: Pointer to the SPI Protocol master.
168  * @cntrlr_info: Platform specific data for the controller this driver manages.
169  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
170  * @lock: Controller specific lock.
171  * @state: Set of FLAGS to indicate status.
172  * @rx_dmach: Controller's DMA channel for Rx.
173  * @tx_dmach: Controller's DMA channel for Tx.
174  * @sfr_start: BUS address of SPI controller regs.
175  * @regs: Pointer to ioremap'ed controller registers.
176  * @irq: interrupt
177  * @xfer_completion: To indicate completion of xfer task.
178  * @cur_mode: Stores the active configuration of the controller.
179  * @cur_bpw: Stores the active bits per word settings.
180  * @cur_speed: Stores the active xfer clock speed.
181  */
182 struct s3c64xx_spi_driver_data {
183         void __iomem                    *regs;
184         struct clk                      *clk;
185         struct clk                      *src_clk;
186         struct clk                      *ioclk;
187         struct platform_device          *pdev;
188         struct spi_master               *master;
189         struct s3c64xx_spi_info  *cntrlr_info;
190         struct spi_device               *tgl_spi;
191         spinlock_t                      lock;
192         unsigned long                   sfr_start;
193         struct completion               xfer_completion;
194         unsigned                        state;
195         unsigned                        cur_mode, cur_bpw;
196         unsigned                        cur_speed;
197         struct s3c64xx_spi_dma_data     rx_dma;
198         struct s3c64xx_spi_dma_data     tx_dma;
199         struct s3c64xx_spi_port_config  *port_conf;
200         unsigned int                    port_id;
201 };
202 
203 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
204 {
205         void __iomem *regs = sdd->regs;
206         unsigned long loops;
207         u32 val;
208 
209         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
210 
211         val = readl(regs + S3C64XX_SPI_CH_CFG);
212         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
213         writel(val, regs + S3C64XX_SPI_CH_CFG);
214 
215         val = readl(regs + S3C64XX_SPI_CH_CFG);
216         val |= S3C64XX_SPI_CH_SW_RST;
217         val &= ~S3C64XX_SPI_CH_HS_EN;
218         writel(val, regs + S3C64XX_SPI_CH_CFG);
219 
220         /* Flush TxFIFO*/
221         loops = msecs_to_loops(1);
222         do {
223                 val = readl(regs + S3C64XX_SPI_STATUS);
224         } while (TX_FIFO_LVL(val, sdd) && loops--);
225 
226         if (loops == 0)
227                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
228 
229         /* Flush RxFIFO*/
230         loops = msecs_to_loops(1);
231         do {
232                 val = readl(regs + S3C64XX_SPI_STATUS);
233                 if (RX_FIFO_LVL(val, sdd))
234                         readl(regs + S3C64XX_SPI_RX_DATA);
235                 else
236                         break;
237         } while (loops--);
238 
239         if (loops == 0)
240                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
241 
242         val = readl(regs + S3C64XX_SPI_CH_CFG);
243         val &= ~S3C64XX_SPI_CH_SW_RST;
244         writel(val, regs + S3C64XX_SPI_CH_CFG);
245 
246         val = readl(regs + S3C64XX_SPI_MODE_CFG);
247         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
248         writel(val, regs + S3C64XX_SPI_MODE_CFG);
249 }
250 
251 static void s3c64xx_spi_dmacb(void *data)
252 {
253         struct s3c64xx_spi_driver_data *sdd;
254         struct s3c64xx_spi_dma_data *dma = data;
255         unsigned long flags;
256 
257         if (dma->direction == DMA_DEV_TO_MEM)
258                 sdd = container_of(data,
259                         struct s3c64xx_spi_driver_data, rx_dma);
260         else
261                 sdd = container_of(data,
262                         struct s3c64xx_spi_driver_data, tx_dma);
263 
264         spin_lock_irqsave(&sdd->lock, flags);
265 
266         if (dma->direction == DMA_DEV_TO_MEM) {
267                 sdd->state &= ~RXBUSY;
268                 if (!(sdd->state & TXBUSY))
269                         complete(&sdd->xfer_completion);
270         } else {
271                 sdd->state &= ~TXBUSY;
272                 if (!(sdd->state & RXBUSY))
273                         complete(&sdd->xfer_completion);
274         }
275 
276         spin_unlock_irqrestore(&sdd->lock, flags);
277 }
278 
279 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
280                         struct sg_table *sgt)
281 {
282         struct s3c64xx_spi_driver_data *sdd;
283         struct dma_slave_config config;
284         struct dma_async_tx_descriptor *desc;
285 
286         memset(&config, 0, sizeof(config));
287 
288         if (dma->direction == DMA_DEV_TO_MEM) {
289                 sdd = container_of((void *)dma,
290                         struct s3c64xx_spi_driver_data, rx_dma);
291                 config.direction = dma->direction;
292                 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
293                 config.src_addr_width = sdd->cur_bpw / 8;
294                 config.src_maxburst = 1;
295                 dmaengine_slave_config(dma->ch, &config);
296         } else {
297                 sdd = container_of((void *)dma,
298                         struct s3c64xx_spi_driver_data, tx_dma);
299                 config.direction = dma->direction;
300                 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
301                 config.dst_addr_width = sdd->cur_bpw / 8;
302                 config.dst_maxburst = 1;
303                 dmaengine_slave_config(dma->ch, &config);
304         }
305 
306         desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
307                                        dma->direction, DMA_PREP_INTERRUPT);
308 
309         desc->callback = s3c64xx_spi_dmacb;
310         desc->callback_param = dma;
311 
312         dmaengine_submit(desc);
313         dma_async_issue_pending(dma->ch);
314 }
315 
316 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
317 {
318         struct s3c64xx_spi_driver_data *sdd =
319                                         spi_master_get_devdata(spi->master);
320 
321         if (sdd->cntrlr_info->no_cs)
322                 return;
323 
324         if (enable) {
325                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
326                         writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
327                 } else {
328                         u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL);
329 
330                         ssel |= (S3C64XX_SPI_SLAVE_AUTO |
331                                                 S3C64XX_SPI_SLAVE_NSC_CNT_2);
332                         writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
333                 }
334         } else {
335                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
336                         writel(S3C64XX_SPI_SLAVE_SIG_INACT,
337                                sdd->regs + S3C64XX_SPI_SLAVE_SEL);
338         }
339 }
340 
341 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
342 {
343         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
344         dma_filter_fn filter = sdd->cntrlr_info->filter;
345         struct device *dev = &sdd->pdev->dev;
346         dma_cap_mask_t mask;
347 
348         if (is_polling(sdd))
349                 return 0;
350 
351         dma_cap_zero(mask);
352         dma_cap_set(DMA_SLAVE, mask);
353 
354         /* Acquire DMA channels */
355         sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
356                            sdd->cntrlr_info->dma_rx, dev, "rx");
357         if (!sdd->rx_dma.ch) {
358                 dev_err(dev, "Failed to get RX DMA channel\n");
359                 return -EBUSY;
360         }
361         spi->dma_rx = sdd->rx_dma.ch;
362 
363         sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
364                            sdd->cntrlr_info->dma_tx, dev, "tx");
365         if (!sdd->tx_dma.ch) {
366                 dev_err(dev, "Failed to get TX DMA channel\n");
367                 dma_release_channel(sdd->rx_dma.ch);
368                 return -EBUSY;
369         }
370         spi->dma_tx = sdd->tx_dma.ch;
371 
372         return 0;
373 }
374 
375 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
376 {
377         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
378 
379         /* Free DMA channels */
380         if (!is_polling(sdd)) {
381                 dma_release_channel(sdd->rx_dma.ch);
382                 dma_release_channel(sdd->tx_dma.ch);
383         }
384 
385         return 0;
386 }
387 
388 static bool s3c64xx_spi_can_dma(struct spi_master *master,
389                                 struct spi_device *spi,
390                                 struct spi_transfer *xfer)
391 {
392         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
393 
394         return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
395 }
396 
397 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
398                                 struct spi_device *spi,
399                                 struct spi_transfer *xfer, int dma_mode)
400 {
401         void __iomem *regs = sdd->regs;
402         u32 modecfg, chcfg;
403 
404         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
405         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
406 
407         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
408         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
409 
410         if (dma_mode) {
411                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
412         } else {
413                 /* Always shift in data in FIFO, even if xfer is Tx only,
414                  * this helps setting PCKT_CNT value for generating clocks
415                  * as exactly needed.
416                  */
417                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
418                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
419                                         | S3C64XX_SPI_PACKET_CNT_EN,
420                                         regs + S3C64XX_SPI_PACKET_CNT);
421         }
422 
423         if (xfer->tx_buf != NULL) {
424                 sdd->state |= TXBUSY;
425                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
426                 if (dma_mode) {
427                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
428                         prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
429                 } else {
430                         switch (sdd->cur_bpw) {
431                         case 32:
432                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
433                                         xfer->tx_buf, xfer->len / 4);
434                                 break;
435                         case 16:
436                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
437                                         xfer->tx_buf, xfer->len / 2);
438                                 break;
439                         default:
440                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
441                                         xfer->tx_buf, xfer->len);
442                                 break;
443                         }
444                 }
445         }
446 
447         if (xfer->rx_buf != NULL) {
448                 sdd->state |= RXBUSY;
449 
450                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
451                                         && !(sdd->cur_mode & SPI_CPHA))
452                         chcfg |= S3C64XX_SPI_CH_HS_EN;
453 
454                 if (dma_mode) {
455                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
456                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
457                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
458                                         | S3C64XX_SPI_PACKET_CNT_EN,
459                                         regs + S3C64XX_SPI_PACKET_CNT);
460                         prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
461                 }
462         }
463 
464         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
465         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
466 }
467 
468 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
469                                         int timeout_ms)
470 {
471         void __iomem *regs = sdd->regs;
472         unsigned long val = 1;
473         u32 status;
474 
475         /* max fifo depth available */
476         u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
477 
478         if (timeout_ms)
479                 val = msecs_to_loops(timeout_ms);
480 
481         do {
482                 status = readl(regs + S3C64XX_SPI_STATUS);
483         } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
484 
485         /* return the actual received data length */
486         return RX_FIFO_LVL(status, sdd);
487 }
488 
489 static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
490                         struct spi_transfer *xfer)
491 {
492         void __iomem *regs = sdd->regs;
493         unsigned long val;
494         u32 status;
495         int ms;
496 
497         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
498         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
499         ms += 10; /* some tolerance */
500 
501         val = msecs_to_jiffies(ms) + 10;
502         val = wait_for_completion_timeout(&sdd->xfer_completion, val);
503 
504         /*
505          * If the previous xfer was completed within timeout, then
506          * proceed further else return -EIO.
507          * DmaTx returns after simply writing data in the FIFO,
508          * w/o waiting for real transmission on the bus to finish.
509          * DmaRx returns only after Dma read data from FIFO which
510          * needs bus transmission to finish, so we don't worry if
511          * Xfer involved Rx(with or without Tx).
512          */
513         if (val && !xfer->rx_buf) {
514                 val = msecs_to_loops(10);
515                 status = readl(regs + S3C64XX_SPI_STATUS);
516                 while ((TX_FIFO_LVL(status, sdd)
517                         || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
518                        && --val) {
519                         cpu_relax();
520                         status = readl(regs + S3C64XX_SPI_STATUS);
521                 }
522 
523         }
524 
525         /* If timed out while checking rx/tx status return error */
526         if (!val)
527                 return -EIO;
528 
529         return 0;
530 }
531 
532 static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
533                         struct spi_transfer *xfer)
534 {
535         void __iomem *regs = sdd->regs;
536         unsigned long val;
537         u32 status;
538         int loops;
539         u32 cpy_len;
540         u8 *buf;
541         int ms;
542 
543         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
544         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
545         ms += 10; /* some tolerance */
546 
547         val = msecs_to_loops(ms);
548         do {
549                 status = readl(regs + S3C64XX_SPI_STATUS);
550         } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
551 
552 
553         /* If it was only Tx */
554         if (!xfer->rx_buf) {
555                 sdd->state &= ~TXBUSY;
556                 return 0;
557         }
558 
559         /*
560          * If the receive length is bigger than the controller fifo
561          * size, calculate the loops and read the fifo as many times.
562          * loops = length / max fifo size (calculated by using the
563          * fifo mask).
564          * For any size less than the fifo size the below code is
565          * executed atleast once.
566          */
567         loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
568         buf = xfer->rx_buf;
569         do {
570                 /* wait for data to be received in the fifo */
571                 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
572                                                        (loops ? ms : 0));
573 
574                 switch (sdd->cur_bpw) {
575                 case 32:
576                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
577                                      buf, cpy_len / 4);
578                         break;
579                 case 16:
580                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
581                                      buf, cpy_len / 2);
582                         break;
583                 default:
584                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
585                                     buf, cpy_len);
586                         break;
587                 }
588 
589                 buf = buf + cpy_len;
590         } while (loops--);
591         sdd->state &= ~RXBUSY;
592 
593         return 0;
594 }
595 
596 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
597 {
598         void __iomem *regs = sdd->regs;
599         u32 val;
600 
601         /* Disable Clock */
602         if (!sdd->port_conf->clk_from_cmu) {
603                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
604                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
605                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
606         }
607 
608         /* Set Polarity and Phase */
609         val = readl(regs + S3C64XX_SPI_CH_CFG);
610         val &= ~(S3C64XX_SPI_CH_SLAVE |
611                         S3C64XX_SPI_CPOL_L |
612                         S3C64XX_SPI_CPHA_B);
613 
614         if (sdd->cur_mode & SPI_CPOL)
615                 val |= S3C64XX_SPI_CPOL_L;
616 
617         if (sdd->cur_mode & SPI_CPHA)
618                 val |= S3C64XX_SPI_CPHA_B;
619 
620         writel(val, regs + S3C64XX_SPI_CH_CFG);
621 
622         /* Set Channel & DMA Mode */
623         val = readl(regs + S3C64XX_SPI_MODE_CFG);
624         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
625                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
626 
627         switch (sdd->cur_bpw) {
628         case 32:
629                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
630                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
631                 break;
632         case 16:
633                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
634                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
635                 break;
636         default:
637                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
638                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
639                 break;
640         }
641 
642         writel(val, regs + S3C64XX_SPI_MODE_CFG);
643 
644         if (sdd->port_conf->clk_from_cmu) {
645                 /* The src_clk clock is divided internally by 2 */
646                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
647         } else {
648                 /* Configure Clock */
649                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
650                 val &= ~S3C64XX_SPI_PSR_MASK;
651                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
652                                 & S3C64XX_SPI_PSR_MASK);
653                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
654 
655                 /* Enable Clock */
656                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
657                 val |= S3C64XX_SPI_ENCLK_ENABLE;
658                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
659         }
660 }
661 
662 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
663 
664 static int s3c64xx_spi_prepare_message(struct spi_master *master,
665                                        struct spi_message *msg)
666 {
667         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
668         struct spi_device *spi = msg->spi;
669         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
670 
671         /* Configure feedback delay */
672         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
673 
674         return 0;
675 }
676 
677 static int s3c64xx_spi_transfer_one(struct spi_master *master,
678                                     struct spi_device *spi,
679                                     struct spi_transfer *xfer)
680 {
681         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
682         int status;
683         u32 speed;
684         u8 bpw;
685         unsigned long flags;
686         int use_dma;
687 
688         reinit_completion(&sdd->xfer_completion);
689 
690         /* Only BPW and Speed may change across transfers */
691         bpw = xfer->bits_per_word;
692         speed = xfer->speed_hz;
693 
694         if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
695                 sdd->cur_bpw = bpw;
696                 sdd->cur_speed = speed;
697                 sdd->cur_mode = spi->mode;
698                 s3c64xx_spi_config(sdd);
699         }
700 
701         /* Polling method for xfers not bigger than FIFO capacity */
702         use_dma = 0;
703         if (!is_polling(sdd) &&
704             (sdd->rx_dma.ch && sdd->tx_dma.ch &&
705              (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
706                 use_dma = 1;
707 
708         spin_lock_irqsave(&sdd->lock, flags);
709 
710         /* Pending only which is to be done */
711         sdd->state &= ~RXBUSY;
712         sdd->state &= ~TXBUSY;
713 
714         enable_datapath(sdd, spi, xfer, use_dma);
715 
716         /* Start the signals */
717         s3c64xx_spi_set_cs(spi, true);
718 
719         spin_unlock_irqrestore(&sdd->lock, flags);
720 
721         if (use_dma)
722                 status = wait_for_dma(sdd, xfer);
723         else
724                 status = wait_for_pio(sdd, xfer);
725 
726         if (status) {
727                 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
728                         xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
729                         (sdd->state & RXBUSY) ? 'f' : 'p',
730                         (sdd->state & TXBUSY) ? 'f' : 'p',
731                         xfer->len);
732 
733                 if (use_dma) {
734                         if (xfer->tx_buf != NULL
735                             && (sdd->state & TXBUSY))
736                                 dmaengine_terminate_all(sdd->tx_dma.ch);
737                         if (xfer->rx_buf != NULL
738                             && (sdd->state & RXBUSY))
739                                 dmaengine_terminate_all(sdd->rx_dma.ch);
740                 }
741         } else {
742                 flush_fifo(sdd);
743         }
744 
745         return status;
746 }
747 
748 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
749                                 struct spi_device *spi)
750 {
751         struct s3c64xx_spi_csinfo *cs;
752         struct device_node *slave_np, *data_np = NULL;
753         u32 fb_delay = 0;
754 
755         slave_np = spi->dev.of_node;
756         if (!slave_np) {
757                 dev_err(&spi->dev, "device node not found\n");
758                 return ERR_PTR(-EINVAL);
759         }
760 
761         data_np = of_get_child_by_name(slave_np, "controller-data");
762         if (!data_np) {
763                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
764                 return ERR_PTR(-EINVAL);
765         }
766 
767         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
768         if (!cs) {
769                 of_node_put(data_np);
770                 return ERR_PTR(-ENOMEM);
771         }
772 
773         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
774         cs->fb_delay = fb_delay;
775         of_node_put(data_np);
776         return cs;
777 }
778 
779 /*
780  * Here we only check the validity of requested configuration
781  * and save the configuration in a local data-structure.
782  * The controller is actually configured only just before we
783  * get a message to transfer.
784  */
785 static int s3c64xx_spi_setup(struct spi_device *spi)
786 {
787         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
788         struct s3c64xx_spi_driver_data *sdd;
789         struct s3c64xx_spi_info *sci;
790         int err;
791 
792         sdd = spi_master_get_devdata(spi->master);
793         if (spi->dev.of_node) {
794                 cs = s3c64xx_get_slave_ctrldata(spi);
795                 spi->controller_data = cs;
796         } else if (cs) {
797                 /* On non-DT platforms the SPI core will set spi->cs_gpio
798                  * to -ENOENT. The GPIO pin used to drive the chip select
799                  * is defined by using platform data so spi->cs_gpio value
800                  * has to be override to have the proper GPIO pin number.
801                  */
802                 spi->cs_gpio = cs->line;
803         }
804 
805         if (IS_ERR_OR_NULL(cs)) {
806                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
807                 return -ENODEV;
808         }
809 
810         if (!spi_get_ctldata(spi)) {
811                 if (gpio_is_valid(spi->cs_gpio)) {
812                         err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
813                                                dev_name(&spi->dev));
814                         if (err) {
815                                 dev_err(&spi->dev,
816                                         "Failed to get /CS gpio [%d]: %d\n",
817                                         spi->cs_gpio, err);
818                                 goto err_gpio_req;
819                         }
820                 }
821 
822                 spi_set_ctldata(spi, cs);
823         }
824 
825         sci = sdd->cntrlr_info;
826 
827         pm_runtime_get_sync(&sdd->pdev->dev);
828 
829         /* Check if we can provide the requested rate */
830         if (!sdd->port_conf->clk_from_cmu) {
831                 u32 psr, speed;
832 
833                 /* Max possible */
834                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
835 
836                 if (spi->max_speed_hz > speed)
837                         spi->max_speed_hz = speed;
838 
839                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
840                 psr &= S3C64XX_SPI_PSR_MASK;
841                 if (psr == S3C64XX_SPI_PSR_MASK)
842                         psr--;
843 
844                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
845                 if (spi->max_speed_hz < speed) {
846                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
847                                 psr++;
848                         } else {
849                                 err = -EINVAL;
850                                 goto setup_exit;
851                         }
852                 }
853 
854                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
855                 if (spi->max_speed_hz >= speed) {
856                         spi->max_speed_hz = speed;
857                 } else {
858                         dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
859                                 spi->max_speed_hz);
860                         err = -EINVAL;
861                         goto setup_exit;
862                 }
863         }
864 
865         pm_runtime_mark_last_busy(&sdd->pdev->dev);
866         pm_runtime_put_autosuspend(&sdd->pdev->dev);
867         s3c64xx_spi_set_cs(spi, false);
868 
869         return 0;
870 
871 setup_exit:
872         pm_runtime_mark_last_busy(&sdd->pdev->dev);
873         pm_runtime_put_autosuspend(&sdd->pdev->dev);
874         /* setup() returns with device de-selected */
875         s3c64xx_spi_set_cs(spi, false);
876 
877         if (gpio_is_valid(spi->cs_gpio))
878                 gpio_free(spi->cs_gpio);
879         spi_set_ctldata(spi, NULL);
880 
881 err_gpio_req:
882         if (spi->dev.of_node)
883                 kfree(cs);
884 
885         return err;
886 }
887 
888 static void s3c64xx_spi_cleanup(struct spi_device *spi)
889 {
890         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
891 
892         if (gpio_is_valid(spi->cs_gpio)) {
893                 gpio_free(spi->cs_gpio);
894                 if (spi->dev.of_node)
895                         kfree(cs);
896                 else {
897                         /* On non-DT platforms, the SPI core sets
898                          * spi->cs_gpio to -ENOENT and .setup()
899                          * overrides it with the GPIO pin value
900                          * passed using platform data.
901                          */
902                         spi->cs_gpio = -ENOENT;
903                 }
904         }
905 
906         spi_set_ctldata(spi, NULL);
907 }
908 
909 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
910 {
911         struct s3c64xx_spi_driver_data *sdd = data;
912         struct spi_master *spi = sdd->master;
913         unsigned int val, clr = 0;
914 
915         val = readl(sdd->regs + S3C64XX_SPI_STATUS);
916 
917         if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
918                 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
919                 dev_err(&spi->dev, "RX overrun\n");
920         }
921         if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
922                 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
923                 dev_err(&spi->dev, "RX underrun\n");
924         }
925         if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
926                 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
927                 dev_err(&spi->dev, "TX overrun\n");
928         }
929         if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
930                 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
931                 dev_err(&spi->dev, "TX underrun\n");
932         }
933 
934         /* Clear the pending irq by setting and then clearing it */
935         writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
936         writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
937 
938         return IRQ_HANDLED;
939 }
940 
941 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
942 {
943         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
944         void __iomem *regs = sdd->regs;
945         unsigned int val;
946 
947         sdd->cur_speed = 0;
948 
949         if (sci->no_cs)
950                 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
951         else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
952                 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
953 
954         /* Disable Interrupts - we use Polling if not DMA mode */
955         writel(0, regs + S3C64XX_SPI_INT_EN);
956 
957         if (!sdd->port_conf->clk_from_cmu)
958                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
959                                 regs + S3C64XX_SPI_CLK_CFG);
960         writel(0, regs + S3C64XX_SPI_MODE_CFG);
961         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
962 
963         /* Clear any irq pending bits, should set and clear the bits */
964         val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
965                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
966                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
967                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
968         writel(val, regs + S3C64XX_SPI_PENDING_CLR);
969         writel(0, regs + S3C64XX_SPI_PENDING_CLR);
970 
971         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
972 
973         val = readl(regs + S3C64XX_SPI_MODE_CFG);
974         val &= ~S3C64XX_SPI_MODE_4BURST;
975         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
976         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
977         writel(val, regs + S3C64XX_SPI_MODE_CFG);
978 
979         flush_fifo(sdd);
980 }
981 
982 #ifdef CONFIG_OF
983 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
984 {
985         struct s3c64xx_spi_info *sci;
986         u32 temp;
987 
988         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
989         if (!sci)
990                 return ERR_PTR(-ENOMEM);
991 
992         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
993                 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
994                 sci->src_clk_nr = 0;
995         } else {
996                 sci->src_clk_nr = temp;
997         }
998 
999         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1000                 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1001                 sci->num_cs = 1;
1002         } else {
1003                 sci->num_cs = temp;
1004         }
1005 
1006         sci->no_cs = of_property_read_bool(dev->of_node, "broken-cs");
1007 
1008         return sci;
1009 }
1010 #else
1011 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1012 {
1013         return dev_get_platdata(dev);
1014 }
1015 #endif
1016 
1017 static const struct of_device_id s3c64xx_spi_dt_match[];
1018 
1019 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1020                                                 struct platform_device *pdev)
1021 {
1022 #ifdef CONFIG_OF
1023         if (pdev->dev.of_node) {
1024                 const struct of_device_id *match;
1025                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1026                 return (struct s3c64xx_spi_port_config *)match->data;
1027         }
1028 #endif
1029         return (struct s3c64xx_spi_port_config *)
1030                          platform_get_device_id(pdev)->driver_data;
1031 }
1032 
1033 static int s3c64xx_spi_probe(struct platform_device *pdev)
1034 {
1035         struct resource *mem_res;
1036         struct s3c64xx_spi_driver_data *sdd;
1037         struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1038         struct spi_master *master;
1039         int ret, irq;
1040         char clk_name[16];
1041 
1042         if (!sci && pdev->dev.of_node) {
1043                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1044                 if (IS_ERR(sci))
1045                         return PTR_ERR(sci);
1046         }
1047 
1048         if (!sci) {
1049                 dev_err(&pdev->dev, "platform_data missing!\n");
1050                 return -ENODEV;
1051         }
1052 
1053         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1054         if (mem_res == NULL) {
1055                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1056                 return -ENXIO;
1057         }
1058 
1059         irq = platform_get_irq(pdev, 0);
1060         if (irq < 0) {
1061                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1062                 return irq;
1063         }
1064 
1065         master = spi_alloc_master(&pdev->dev,
1066                                 sizeof(struct s3c64xx_spi_driver_data));
1067         if (master == NULL) {
1068                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1069                 return -ENOMEM;
1070         }
1071 
1072         platform_set_drvdata(pdev, master);
1073 
1074         sdd = spi_master_get_devdata(master);
1075         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1076         sdd->master = master;
1077         sdd->cntrlr_info = sci;
1078         sdd->pdev = pdev;
1079         sdd->sfr_start = mem_res->start;
1080         if (pdev->dev.of_node) {
1081                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1082                 if (ret < 0) {
1083                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1084                                 ret);
1085                         goto err_deref_master;
1086                 }
1087                 sdd->port_id = ret;
1088         } else {
1089                 sdd->port_id = pdev->id;
1090         }
1091 
1092         sdd->cur_bpw = 8;
1093 
1094         if (!sdd->pdev->dev.of_node && (!sci->dma_tx || !sci->dma_rx)) {
1095                 dev_warn(&pdev->dev, "Unable to get SPI tx/rx DMA data. Switching to poll mode\n");
1096                 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1097         }
1098 
1099         sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1100         sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1101 
1102         master->dev.of_node = pdev->dev.of_node;
1103         master->bus_num = sdd->port_id;
1104         master->setup = s3c64xx_spi_setup;
1105         master->cleanup = s3c64xx_spi_cleanup;
1106         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1107         master->prepare_message = s3c64xx_spi_prepare_message;
1108         master->transfer_one = s3c64xx_spi_transfer_one;
1109         master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1110         master->num_chipselect = sci->num_cs;
1111         master->dma_alignment = 8;
1112         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1113                                         SPI_BPW_MASK(8);
1114         /* the spi->mode bits understood by this driver: */
1115         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1116         master->auto_runtime_pm = true;
1117         if (!is_polling(sdd))
1118                 master->can_dma = s3c64xx_spi_can_dma;
1119 
1120         sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1121         if (IS_ERR(sdd->regs)) {
1122                 ret = PTR_ERR(sdd->regs);
1123                 goto err_deref_master;
1124         }
1125 
1126         if (sci->cfg_gpio && sci->cfg_gpio()) {
1127                 dev_err(&pdev->dev, "Unable to config gpio\n");
1128                 ret = -EBUSY;
1129                 goto err_deref_master;
1130         }
1131 
1132         /* Setup clocks */
1133         sdd->clk = devm_clk_get(&pdev->dev, "spi");
1134         if (IS_ERR(sdd->clk)) {
1135                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1136                 ret = PTR_ERR(sdd->clk);
1137                 goto err_deref_master;
1138         }
1139 
1140         ret = clk_prepare_enable(sdd->clk);
1141         if (ret) {
1142                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1143                 goto err_deref_master;
1144         }
1145 
1146         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1147         sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1148         if (IS_ERR(sdd->src_clk)) {
1149                 dev_err(&pdev->dev,
1150                         "Unable to acquire clock '%s'\n", clk_name);
1151                 ret = PTR_ERR(sdd->src_clk);
1152                 goto err_disable_clk;
1153         }
1154 
1155         ret = clk_prepare_enable(sdd->src_clk);
1156         if (ret) {
1157                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1158                 goto err_disable_clk;
1159         }
1160 
1161         if (sdd->port_conf->clk_ioclk) {
1162                 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
1163                 if (IS_ERR(sdd->ioclk)) {
1164                         dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
1165                         ret = PTR_ERR(sdd->ioclk);
1166                         goto err_disable_src_clk;
1167                 }
1168 
1169                 ret = clk_prepare_enable(sdd->ioclk);
1170                 if (ret) {
1171                         dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
1172                         goto err_disable_src_clk;
1173                 }
1174         }
1175 
1176         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1177         pm_runtime_use_autosuspend(&pdev->dev);
1178         pm_runtime_set_active(&pdev->dev);
1179         pm_runtime_enable(&pdev->dev);
1180         pm_runtime_get_sync(&pdev->dev);
1181 
1182         /* Setup Deufult Mode */
1183         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1184 
1185         spin_lock_init(&sdd->lock);
1186         init_completion(&sdd->xfer_completion);
1187 
1188         ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1189                                 "spi-s3c64xx", sdd);
1190         if (ret != 0) {
1191                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1192                         irq, ret);
1193                 goto err_pm_put;
1194         }
1195 
1196         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1197                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1198                sdd->regs + S3C64XX_SPI_INT_EN);
1199 
1200         ret = devm_spi_register_master(&pdev->dev, master);
1201         if (ret != 0) {
1202                 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1203                 goto err_pm_put;
1204         }
1205 
1206         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1207                                         sdd->port_id, master->num_chipselect);
1208         dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\tDMA=[Rx-%p, Tx-%p]\n",
1209                                         mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1,
1210                                         sci->dma_rx, sci->dma_tx);
1211 
1212         pm_runtime_mark_last_busy(&pdev->dev);
1213         pm_runtime_put_autosuspend(&pdev->dev);
1214 
1215         return 0;
1216 
1217 err_pm_put:
1218         pm_runtime_put_noidle(&pdev->dev);
1219         pm_runtime_disable(&pdev->dev);
1220         pm_runtime_set_suspended(&pdev->dev);
1221 
1222         clk_disable_unprepare(sdd->ioclk);
1223 err_disable_src_clk:
1224         clk_disable_unprepare(sdd->src_clk);
1225 err_disable_clk:
1226         clk_disable_unprepare(sdd->clk);
1227 err_deref_master:
1228         spi_master_put(master);
1229 
1230         return ret;
1231 }
1232 
1233 static int s3c64xx_spi_remove(struct platform_device *pdev)
1234 {
1235         struct spi_master *master = platform_get_drvdata(pdev);
1236         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1237 
1238         pm_runtime_get_sync(&pdev->dev);
1239 
1240         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1241 
1242         clk_disable_unprepare(sdd->ioclk);
1243 
1244         clk_disable_unprepare(sdd->src_clk);
1245 
1246         clk_disable_unprepare(sdd->clk);
1247 
1248         pm_runtime_put_noidle(&pdev->dev);
1249         pm_runtime_disable(&pdev->dev);
1250         pm_runtime_set_suspended(&pdev->dev);
1251 
1252         return 0;
1253 }
1254 
1255 #ifdef CONFIG_PM_SLEEP
1256 static int s3c64xx_spi_suspend(struct device *dev)
1257 {
1258         struct spi_master *master = dev_get_drvdata(dev);
1259         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1260 
1261         int ret = spi_master_suspend(master);
1262         if (ret)
1263                 return ret;
1264 
1265         ret = pm_runtime_force_suspend(dev);
1266         if (ret < 0)
1267                 return ret;
1268 
1269         sdd->cur_speed = 0; /* Output Clock is stopped */
1270 
1271         return 0;
1272 }
1273 
1274 static int s3c64xx_spi_resume(struct device *dev)
1275 {
1276         struct spi_master *master = dev_get_drvdata(dev);
1277         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1278         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1279         int ret;
1280 
1281         if (sci->cfg_gpio)
1282                 sci->cfg_gpio();
1283 
1284         ret = pm_runtime_force_resume(dev);
1285         if (ret < 0)
1286                 return ret;
1287 
1288         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1289 
1290         return spi_master_resume(master);
1291 }
1292 #endif /* CONFIG_PM_SLEEP */
1293 
1294 #ifdef CONFIG_PM
1295 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1296 {
1297         struct spi_master *master = dev_get_drvdata(dev);
1298         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1299 
1300         clk_disable_unprepare(sdd->clk);
1301         clk_disable_unprepare(sdd->src_clk);
1302         clk_disable_unprepare(sdd->ioclk);
1303 
1304         return 0;
1305 }
1306 
1307 static int s3c64xx_spi_runtime_resume(struct device *dev)
1308 {
1309         struct spi_master *master = dev_get_drvdata(dev);
1310         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1311         int ret;
1312 
1313         if (sdd->port_conf->clk_ioclk) {
1314                 ret = clk_prepare_enable(sdd->ioclk);
1315                 if (ret != 0)
1316                         return ret;
1317         }
1318 
1319         ret = clk_prepare_enable(sdd->src_clk);
1320         if (ret != 0)
1321                 goto err_disable_ioclk;
1322 
1323         ret = clk_prepare_enable(sdd->clk);
1324         if (ret != 0)
1325                 goto err_disable_src_clk;
1326 
1327         return 0;
1328 
1329 err_disable_src_clk:
1330         clk_disable_unprepare(sdd->src_clk);
1331 err_disable_ioclk:
1332         clk_disable_unprepare(sdd->ioclk);
1333 
1334         return ret;
1335 }
1336 #endif /* CONFIG_PM */
1337 
1338 static const struct dev_pm_ops s3c64xx_spi_pm = {
1339         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1340         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1341                            s3c64xx_spi_runtime_resume, NULL)
1342 };
1343 
1344 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1345         .fifo_lvl_mask  = { 0x7f },
1346         .rx_lvl_offset  = 13,
1347         .tx_st_done     = 21,
1348         .high_speed     = true,
1349 };
1350 
1351 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1352         .fifo_lvl_mask  = { 0x7f, 0x7F },
1353         .rx_lvl_offset  = 13,
1354         .tx_st_done     = 21,
1355 };
1356 
1357 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1358         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1359         .rx_lvl_offset  = 15,
1360         .tx_st_done     = 25,
1361         .high_speed     = true,
1362 };
1363 
1364 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1365         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1366         .rx_lvl_offset  = 15,
1367         .tx_st_done     = 25,
1368         .high_speed     = true,
1369         .clk_from_cmu   = true,
1370 };
1371 
1372 static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1373         .fifo_lvl_mask  = { 0x1ff },
1374         .rx_lvl_offset  = 15,
1375         .tx_st_done     = 25,
1376         .high_speed     = true,
1377         .clk_from_cmu   = true,
1378         .quirks         = S3C64XX_SPI_QUIRK_POLL,
1379 };
1380 
1381 static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1382         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1383         .rx_lvl_offset  = 15,
1384         .tx_st_done     = 25,
1385         .high_speed     = true,
1386         .clk_from_cmu   = true,
1387         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1388 };
1389 
1390 static struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1391         .fifo_lvl_mask  = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1392         .rx_lvl_offset  = 15,
1393         .tx_st_done     = 25,
1394         .high_speed     = true,
1395         .clk_from_cmu   = true,
1396         .clk_ioclk      = true,
1397         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1398 };
1399 
1400 static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1401         {
1402                 .name           = "s3c2443-spi",
1403                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1404         }, {
1405                 .name           = "s3c6410-spi",
1406                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1407         },
1408         { },
1409 };
1410 
1411 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1412         { .compatible = "samsung,s3c2443-spi",
1413                         .data = (void *)&s3c2443_spi_port_config,
1414         },
1415         { .compatible = "samsung,s3c6410-spi",
1416                         .data = (void *)&s3c6410_spi_port_config,
1417         },
1418         { .compatible = "samsung,s5pv210-spi",
1419                         .data = (void *)&s5pv210_spi_port_config,
1420         },
1421         { .compatible = "samsung,exynos4210-spi",
1422                         .data = (void *)&exynos4_spi_port_config,
1423         },
1424         { .compatible = "samsung,exynos5440-spi",
1425                         .data = (void *)&exynos5440_spi_port_config,
1426         },
1427         { .compatible = "samsung,exynos7-spi",
1428                         .data = (void *)&exynos7_spi_port_config,
1429         },
1430         { .compatible = "samsung,exynos5433-spi",
1431                         .data = (void *)&exynos5433_spi_port_config,
1432         },
1433         { },
1434 };
1435 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1436 
1437 static struct platform_driver s3c64xx_spi_driver = {
1438         .driver = {
1439                 .name   = "s3c64xx-spi",
1440                 .pm = &s3c64xx_spi_pm,
1441                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1442         },
1443         .probe = s3c64xx_spi_probe,
1444         .remove = s3c64xx_spi_remove,
1445         .id_table = s3c64xx_spi_driver_ids,
1446 };
1447 MODULE_ALIAS("platform:s3c64xx-spi");
1448 
1449 module_platform_driver(s3c64xx_spi_driver);
1450 
1451 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1452 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1453 MODULE_LICENSE("GPL");
1454 

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