Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4

Linux/drivers/spi/spi-s3c64xx.c

  1 /*
  2  * Copyright (C) 2009 Samsung Electronics Ltd.
  3  *      Jaswinder Singh <jassi.brar@samsung.com>
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License as published by
  7  * the Free Software Foundation; either version 2 of the License, or
  8  * (at your option) any later version.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  */
 15 
 16 #include <linux/init.h>
 17 #include <linux/module.h>
 18 #include <linux/interrupt.h>
 19 #include <linux/delay.h>
 20 #include <linux/clk.h>
 21 #include <linux/dma-mapping.h>
 22 #include <linux/dmaengine.h>
 23 #include <linux/platform_device.h>
 24 #include <linux/pm_runtime.h>
 25 #include <linux/spi/spi.h>
 26 #include <linux/gpio.h>
 27 #include <linux/of.h>
 28 #include <linux/of_gpio.h>
 29 
 30 #include <linux/platform_data/spi-s3c64xx.h>
 31 
 32 #define MAX_SPI_PORTS           6
 33 #define S3C64XX_SPI_QUIRK_POLL          (1 << 0)
 34 #define S3C64XX_SPI_QUIRK_CS_AUTO       (1 << 1)
 35 #define AUTOSUSPEND_TIMEOUT     2000
 36 
 37 /* Registers and bit-fields */
 38 
 39 #define S3C64XX_SPI_CH_CFG              0x00
 40 #define S3C64XX_SPI_CLK_CFG             0x04
 41 #define S3C64XX_SPI_MODE_CFG    0x08
 42 #define S3C64XX_SPI_SLAVE_SEL   0x0C
 43 #define S3C64XX_SPI_INT_EN              0x10
 44 #define S3C64XX_SPI_STATUS              0x14
 45 #define S3C64XX_SPI_TX_DATA             0x18
 46 #define S3C64XX_SPI_RX_DATA             0x1C
 47 #define S3C64XX_SPI_PACKET_CNT  0x20
 48 #define S3C64XX_SPI_PENDING_CLR 0x24
 49 #define S3C64XX_SPI_SWAP_CFG    0x28
 50 #define S3C64XX_SPI_FB_CLK              0x2C
 51 
 52 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
 53 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
 54 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
 55 #define S3C64XX_SPI_CPOL_L              (1<<3)
 56 #define S3C64XX_SPI_CPHA_B              (1<<2)
 57 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
 58 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
 59 
 60 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
 61 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
 62 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
 63 #define S3C64XX_SPI_PSR_MASK            0xff
 64 
 65 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
 66 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
 67 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
 68 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
 69 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
 70 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
 71 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
 72 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
 73 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
 74 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
 75 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
 76 
 77 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
 78 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
 79 #define S3C64XX_SPI_SLAVE_NSC_CNT_2             (2<<4)
 80 
 81 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
 82 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
 83 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
 84 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
 85 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
 86 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
 87 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
 88 
 89 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
 90 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
 91 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
 92 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
 93 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
 94 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
 95 
 96 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
 97 
 98 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
 99 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
100 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
101 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
102 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
103 
104 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
105 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
106 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
107 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
108 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
109 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
110 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
111 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
112 
113 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
114 
115 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
116 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
117                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
118 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
119 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
120                                         FIFO_LVL_MASK(i))
121 
122 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
123 #define S3C64XX_SPI_TRAILCNT_OFF        19
124 
125 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
126 
127 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
128 #define is_polling(x)   (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
129 
130 #define RXBUSY    (1<<2)
131 #define TXBUSY    (1<<3)
132 
133 struct s3c64xx_spi_dma_data {
134         struct dma_chan *ch;
135         enum dma_transfer_direction direction;
136         unsigned int dmach;
137 };
138 
139 /**
140  * struct s3c64xx_spi_info - SPI Controller hardware info
141  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
142  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
143  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
144  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
145  * @clk_from_cmu: True, if the controller does not include a clock mux and
146  *      prescaler unit.
147  *
148  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
149  * differ in some aspects such as the size of the fifo and spi bus clock
150  * setup. Such differences are specified to the driver using this structure
151  * which is provided as driver data to the driver.
152  */
153 struct s3c64xx_spi_port_config {
154         int     fifo_lvl_mask[MAX_SPI_PORTS];
155         int     rx_lvl_offset;
156         int     tx_st_done;
157         int     quirks;
158         bool    high_speed;
159         bool    clk_from_cmu;
160 };
161 
162 /**
163  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
164  * @clk: Pointer to the spi clock.
165  * @src_clk: Pointer to the clock used to generate SPI signals.
166  * @master: Pointer to the SPI Protocol master.
167  * @cntrlr_info: Platform specific data for the controller this driver manages.
168  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
169  * @lock: Controller specific lock.
170  * @state: Set of FLAGS to indicate status.
171  * @rx_dmach: Controller's DMA channel for Rx.
172  * @tx_dmach: Controller's DMA channel for Tx.
173  * @sfr_start: BUS address of SPI controller regs.
174  * @regs: Pointer to ioremap'ed controller registers.
175  * @irq: interrupt
176  * @xfer_completion: To indicate completion of xfer task.
177  * @cur_mode: Stores the active configuration of the controller.
178  * @cur_bpw: Stores the active bits per word settings.
179  * @cur_speed: Stores the active xfer clock speed.
180  */
181 struct s3c64xx_spi_driver_data {
182         void __iomem                    *regs;
183         struct clk                      *clk;
184         struct clk                      *src_clk;
185         struct platform_device          *pdev;
186         struct spi_master               *master;
187         struct s3c64xx_spi_info  *cntrlr_info;
188         struct spi_device               *tgl_spi;
189         spinlock_t                      lock;
190         unsigned long                   sfr_start;
191         struct completion               xfer_completion;
192         unsigned                        state;
193         unsigned                        cur_mode, cur_bpw;
194         unsigned                        cur_speed;
195         struct s3c64xx_spi_dma_data     rx_dma;
196         struct s3c64xx_spi_dma_data     tx_dma;
197         struct s3c64xx_spi_port_config  *port_conf;
198         unsigned int                    port_id;
199 };
200 
201 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
202 {
203         void __iomem *regs = sdd->regs;
204         unsigned long loops;
205         u32 val;
206 
207         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
208 
209         val = readl(regs + S3C64XX_SPI_CH_CFG);
210         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
211         writel(val, regs + S3C64XX_SPI_CH_CFG);
212 
213         val = readl(regs + S3C64XX_SPI_CH_CFG);
214         val |= S3C64XX_SPI_CH_SW_RST;
215         val &= ~S3C64XX_SPI_CH_HS_EN;
216         writel(val, regs + S3C64XX_SPI_CH_CFG);
217 
218         /* Flush TxFIFO*/
219         loops = msecs_to_loops(1);
220         do {
221                 val = readl(regs + S3C64XX_SPI_STATUS);
222         } while (TX_FIFO_LVL(val, sdd) && loops--);
223 
224         if (loops == 0)
225                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
226 
227         /* Flush RxFIFO*/
228         loops = msecs_to_loops(1);
229         do {
230                 val = readl(regs + S3C64XX_SPI_STATUS);
231                 if (RX_FIFO_LVL(val, sdd))
232                         readl(regs + S3C64XX_SPI_RX_DATA);
233                 else
234                         break;
235         } while (loops--);
236 
237         if (loops == 0)
238                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
239 
240         val = readl(regs + S3C64XX_SPI_CH_CFG);
241         val &= ~S3C64XX_SPI_CH_SW_RST;
242         writel(val, regs + S3C64XX_SPI_CH_CFG);
243 
244         val = readl(regs + S3C64XX_SPI_MODE_CFG);
245         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
246         writel(val, regs + S3C64XX_SPI_MODE_CFG);
247 }
248 
249 static void s3c64xx_spi_dmacb(void *data)
250 {
251         struct s3c64xx_spi_driver_data *sdd;
252         struct s3c64xx_spi_dma_data *dma = data;
253         unsigned long flags;
254 
255         if (dma->direction == DMA_DEV_TO_MEM)
256                 sdd = container_of(data,
257                         struct s3c64xx_spi_driver_data, rx_dma);
258         else
259                 sdd = container_of(data,
260                         struct s3c64xx_spi_driver_data, tx_dma);
261 
262         spin_lock_irqsave(&sdd->lock, flags);
263 
264         if (dma->direction == DMA_DEV_TO_MEM) {
265                 sdd->state &= ~RXBUSY;
266                 if (!(sdd->state & TXBUSY))
267                         complete(&sdd->xfer_completion);
268         } else {
269                 sdd->state &= ~TXBUSY;
270                 if (!(sdd->state & RXBUSY))
271                         complete(&sdd->xfer_completion);
272         }
273 
274         spin_unlock_irqrestore(&sdd->lock, flags);
275 }
276 
277 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
278                         struct sg_table *sgt)
279 {
280         struct s3c64xx_spi_driver_data *sdd;
281         struct dma_slave_config config;
282         struct dma_async_tx_descriptor *desc;
283 
284         memset(&config, 0, sizeof(config));
285 
286         if (dma->direction == DMA_DEV_TO_MEM) {
287                 sdd = container_of((void *)dma,
288                         struct s3c64xx_spi_driver_data, rx_dma);
289                 config.direction = dma->direction;
290                 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
291                 config.src_addr_width = sdd->cur_bpw / 8;
292                 config.src_maxburst = 1;
293                 dmaengine_slave_config(dma->ch, &config);
294         } else {
295                 sdd = container_of((void *)dma,
296                         struct s3c64xx_spi_driver_data, tx_dma);
297                 config.direction = dma->direction;
298                 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
299                 config.dst_addr_width = sdd->cur_bpw / 8;
300                 config.dst_maxburst = 1;
301                 dmaengine_slave_config(dma->ch, &config);
302         }
303 
304         desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
305                                        dma->direction, DMA_PREP_INTERRUPT);
306 
307         desc->callback = s3c64xx_spi_dmacb;
308         desc->callback_param = dma;
309 
310         dmaengine_submit(desc);
311         dma_async_issue_pending(dma->ch);
312 }
313 
314 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
315 {
316         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
317         dma_filter_fn filter = sdd->cntrlr_info->filter;
318         struct device *dev = &sdd->pdev->dev;
319         dma_cap_mask_t mask;
320         int ret;
321 
322         if (!is_polling(sdd)) {
323                 dma_cap_zero(mask);
324                 dma_cap_set(DMA_SLAVE, mask);
325 
326                 /* Acquire DMA channels */
327                 sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
328                                    (void *)(long)sdd->rx_dma.dmach, dev, "rx");
329                 if (!sdd->rx_dma.ch) {
330                         dev_err(dev, "Failed to get RX DMA channel\n");
331                         ret = -EBUSY;
332                         goto out;
333                 }
334                 spi->dma_rx = sdd->rx_dma.ch;
335 
336                 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
337                                    (void *)(long)sdd->tx_dma.dmach, dev, "tx");
338                 if (!sdd->tx_dma.ch) {
339                         dev_err(dev, "Failed to get TX DMA channel\n");
340                         ret = -EBUSY;
341                         goto out_rx;
342                 }
343                 spi->dma_tx = sdd->tx_dma.ch;
344         }
345 
346         return 0;
347 
348 out_rx:
349         dma_release_channel(sdd->rx_dma.ch);
350 out:
351         return ret;
352 }
353 
354 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
355 {
356         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
357 
358         /* Free DMA channels */
359         if (!is_polling(sdd)) {
360                 dma_release_channel(sdd->rx_dma.ch);
361                 dma_release_channel(sdd->tx_dma.ch);
362         }
363 
364         return 0;
365 }
366 
367 static bool s3c64xx_spi_can_dma(struct spi_master *master,
368                                 struct spi_device *spi,
369                                 struct spi_transfer *xfer)
370 {
371         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
372 
373         return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
374 }
375 
376 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
377                                 struct spi_device *spi,
378                                 struct spi_transfer *xfer, int dma_mode)
379 {
380         void __iomem *regs = sdd->regs;
381         u32 modecfg, chcfg;
382 
383         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
384         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
385 
386         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
387         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
388 
389         if (dma_mode) {
390                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
391         } else {
392                 /* Always shift in data in FIFO, even if xfer is Tx only,
393                  * this helps setting PCKT_CNT value for generating clocks
394                  * as exactly needed.
395                  */
396                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
397                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
398                                         | S3C64XX_SPI_PACKET_CNT_EN,
399                                         regs + S3C64XX_SPI_PACKET_CNT);
400         }
401 
402         if (xfer->tx_buf != NULL) {
403                 sdd->state |= TXBUSY;
404                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
405                 if (dma_mode) {
406                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
407                         prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
408                 } else {
409                         switch (sdd->cur_bpw) {
410                         case 32:
411                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
412                                         xfer->tx_buf, xfer->len / 4);
413                                 break;
414                         case 16:
415                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
416                                         xfer->tx_buf, xfer->len / 2);
417                                 break;
418                         default:
419                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
420                                         xfer->tx_buf, xfer->len);
421                                 break;
422                         }
423                 }
424         }
425 
426         if (xfer->rx_buf != NULL) {
427                 sdd->state |= RXBUSY;
428 
429                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
430                                         && !(sdd->cur_mode & SPI_CPHA))
431                         chcfg |= S3C64XX_SPI_CH_HS_EN;
432 
433                 if (dma_mode) {
434                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
435                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
436                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
437                                         | S3C64XX_SPI_PACKET_CNT_EN,
438                                         regs + S3C64XX_SPI_PACKET_CNT);
439                         prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
440                 }
441         }
442 
443         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
444         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
445 }
446 
447 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
448                                         int timeout_ms)
449 {
450         void __iomem *regs = sdd->regs;
451         unsigned long val = 1;
452         u32 status;
453 
454         /* max fifo depth available */
455         u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
456 
457         if (timeout_ms)
458                 val = msecs_to_loops(timeout_ms);
459 
460         do {
461                 status = readl(regs + S3C64XX_SPI_STATUS);
462         } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
463 
464         /* return the actual received data length */
465         return RX_FIFO_LVL(status, sdd);
466 }
467 
468 static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
469                         struct spi_transfer *xfer)
470 {
471         void __iomem *regs = sdd->regs;
472         unsigned long val;
473         u32 status;
474         int ms;
475 
476         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
477         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
478         ms += 10; /* some tolerance */
479 
480         val = msecs_to_jiffies(ms) + 10;
481         val = wait_for_completion_timeout(&sdd->xfer_completion, val);
482 
483         /*
484          * If the previous xfer was completed within timeout, then
485          * proceed further else return -EIO.
486          * DmaTx returns after simply writing data in the FIFO,
487          * w/o waiting for real transmission on the bus to finish.
488          * DmaRx returns only after Dma read data from FIFO which
489          * needs bus transmission to finish, so we don't worry if
490          * Xfer involved Rx(with or without Tx).
491          */
492         if (val && !xfer->rx_buf) {
493                 val = msecs_to_loops(10);
494                 status = readl(regs + S3C64XX_SPI_STATUS);
495                 while ((TX_FIFO_LVL(status, sdd)
496                         || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
497                        && --val) {
498                         cpu_relax();
499                         status = readl(regs + S3C64XX_SPI_STATUS);
500                 }
501 
502         }
503 
504         /* If timed out while checking rx/tx status return error */
505         if (!val)
506                 return -EIO;
507 
508         return 0;
509 }
510 
511 static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
512                         struct spi_transfer *xfer)
513 {
514         void __iomem *regs = sdd->regs;
515         unsigned long val;
516         u32 status;
517         int loops;
518         u32 cpy_len;
519         u8 *buf;
520         int ms;
521 
522         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
523         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
524         ms += 10; /* some tolerance */
525 
526         val = msecs_to_loops(ms);
527         do {
528                 status = readl(regs + S3C64XX_SPI_STATUS);
529         } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
530 
531 
532         /* If it was only Tx */
533         if (!xfer->rx_buf) {
534                 sdd->state &= ~TXBUSY;
535                 return 0;
536         }
537 
538         /*
539          * If the receive length is bigger than the controller fifo
540          * size, calculate the loops and read the fifo as many times.
541          * loops = length / max fifo size (calculated by using the
542          * fifo mask).
543          * For any size less than the fifo size the below code is
544          * executed atleast once.
545          */
546         loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
547         buf = xfer->rx_buf;
548         do {
549                 /* wait for data to be received in the fifo */
550                 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
551                                                        (loops ? ms : 0));
552 
553                 switch (sdd->cur_bpw) {
554                 case 32:
555                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
556                                      buf, cpy_len / 4);
557                         break;
558                 case 16:
559                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
560                                      buf, cpy_len / 2);
561                         break;
562                 default:
563                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
564                                     buf, cpy_len);
565                         break;
566                 }
567 
568                 buf = buf + cpy_len;
569         } while (loops--);
570         sdd->state &= ~RXBUSY;
571 
572         return 0;
573 }
574 
575 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
576 {
577         void __iomem *regs = sdd->regs;
578         u32 val;
579 
580         /* Disable Clock */
581         if (sdd->port_conf->clk_from_cmu) {
582                 clk_disable_unprepare(sdd->src_clk);
583         } else {
584                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
585                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
586                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
587         }
588 
589         /* Set Polarity and Phase */
590         val = readl(regs + S3C64XX_SPI_CH_CFG);
591         val &= ~(S3C64XX_SPI_CH_SLAVE |
592                         S3C64XX_SPI_CPOL_L |
593                         S3C64XX_SPI_CPHA_B);
594 
595         if (sdd->cur_mode & SPI_CPOL)
596                 val |= S3C64XX_SPI_CPOL_L;
597 
598         if (sdd->cur_mode & SPI_CPHA)
599                 val |= S3C64XX_SPI_CPHA_B;
600 
601         writel(val, regs + S3C64XX_SPI_CH_CFG);
602 
603         /* Set Channel & DMA Mode */
604         val = readl(regs + S3C64XX_SPI_MODE_CFG);
605         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
606                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
607 
608         switch (sdd->cur_bpw) {
609         case 32:
610                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
611                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
612                 break;
613         case 16:
614                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
615                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
616                 break;
617         default:
618                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
619                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
620                 break;
621         }
622 
623         writel(val, regs + S3C64XX_SPI_MODE_CFG);
624 
625         if (sdd->port_conf->clk_from_cmu) {
626                 /* Configure Clock */
627                 /* There is half-multiplier before the SPI */
628                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
629                 /* Enable Clock */
630                 clk_prepare_enable(sdd->src_clk);
631         } else {
632                 /* Configure Clock */
633                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
634                 val &= ~S3C64XX_SPI_PSR_MASK;
635                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
636                                 & S3C64XX_SPI_PSR_MASK);
637                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
638 
639                 /* Enable Clock */
640                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
641                 val |= S3C64XX_SPI_ENCLK_ENABLE;
642                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
643         }
644 }
645 
646 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
647 
648 static int s3c64xx_spi_prepare_message(struct spi_master *master,
649                                        struct spi_message *msg)
650 {
651         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
652         struct spi_device *spi = msg->spi;
653         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
654 
655         /* If Master's(controller) state differs from that needed by Slave */
656         if (sdd->cur_speed != spi->max_speed_hz
657                         || sdd->cur_mode != spi->mode
658                         || sdd->cur_bpw != spi->bits_per_word) {
659                 sdd->cur_bpw = spi->bits_per_word;
660                 sdd->cur_speed = spi->max_speed_hz;
661                 sdd->cur_mode = spi->mode;
662                 s3c64xx_spi_config(sdd);
663         }
664 
665         /* Configure feedback delay */
666         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
667 
668         return 0;
669 }
670 
671 static int s3c64xx_spi_transfer_one(struct spi_master *master,
672                                     struct spi_device *spi,
673                                     struct spi_transfer *xfer)
674 {
675         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
676         int status;
677         u32 speed;
678         u8 bpw;
679         unsigned long flags;
680         int use_dma;
681 
682         reinit_completion(&sdd->xfer_completion);
683 
684         /* Only BPW and Speed may change across transfers */
685         bpw = xfer->bits_per_word;
686         speed = xfer->speed_hz;
687 
688         if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
689                 sdd->cur_bpw = bpw;
690                 sdd->cur_speed = speed;
691                 s3c64xx_spi_config(sdd);
692         }
693 
694         /* Polling method for xfers not bigger than FIFO capacity */
695         use_dma = 0;
696         if (!is_polling(sdd) &&
697             (sdd->rx_dma.ch && sdd->tx_dma.ch &&
698              (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
699                 use_dma = 1;
700 
701         spin_lock_irqsave(&sdd->lock, flags);
702 
703         /* Pending only which is to be done */
704         sdd->state &= ~RXBUSY;
705         sdd->state &= ~TXBUSY;
706 
707         enable_datapath(sdd, spi, xfer, use_dma);
708 
709         /* Start the signals */
710         if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
711                 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
712         else
713                 writel(readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL)
714                         | S3C64XX_SPI_SLAVE_AUTO | S3C64XX_SPI_SLAVE_NSC_CNT_2,
715                         sdd->regs + S3C64XX_SPI_SLAVE_SEL);
716 
717         spin_unlock_irqrestore(&sdd->lock, flags);
718 
719         if (use_dma)
720                 status = wait_for_dma(sdd, xfer);
721         else
722                 status = wait_for_pio(sdd, xfer);
723 
724         if (status) {
725                 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
726                         xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
727                         (sdd->state & RXBUSY) ? 'f' : 'p',
728                         (sdd->state & TXBUSY) ? 'f' : 'p',
729                         xfer->len);
730 
731                 if (use_dma) {
732                         if (xfer->tx_buf != NULL
733                             && (sdd->state & TXBUSY))
734                                 dmaengine_terminate_all(sdd->tx_dma.ch);
735                         if (xfer->rx_buf != NULL
736                             && (sdd->state & RXBUSY))
737                                 dmaengine_terminate_all(sdd->rx_dma.ch);
738                 }
739         } else {
740                 flush_fifo(sdd);
741         }
742 
743         return status;
744 }
745 
746 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
747                                 struct spi_device *spi)
748 {
749         struct s3c64xx_spi_csinfo *cs;
750         struct device_node *slave_np, *data_np = NULL;
751         u32 fb_delay = 0;
752 
753         slave_np = spi->dev.of_node;
754         if (!slave_np) {
755                 dev_err(&spi->dev, "device node not found\n");
756                 return ERR_PTR(-EINVAL);
757         }
758 
759         data_np = of_get_child_by_name(slave_np, "controller-data");
760         if (!data_np) {
761                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
762                 return ERR_PTR(-EINVAL);
763         }
764 
765         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
766         if (!cs) {
767                 of_node_put(data_np);
768                 return ERR_PTR(-ENOMEM);
769         }
770 
771         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
772         cs->fb_delay = fb_delay;
773         of_node_put(data_np);
774         return cs;
775 }
776 
777 /*
778  * Here we only check the validity of requested configuration
779  * and save the configuration in a local data-structure.
780  * The controller is actually configured only just before we
781  * get a message to transfer.
782  */
783 static int s3c64xx_spi_setup(struct spi_device *spi)
784 {
785         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
786         struct s3c64xx_spi_driver_data *sdd;
787         struct s3c64xx_spi_info *sci;
788         int err;
789 
790         sdd = spi_master_get_devdata(spi->master);
791         if (spi->dev.of_node) {
792                 cs = s3c64xx_get_slave_ctrldata(spi);
793                 spi->controller_data = cs;
794         } else if (cs) {
795                 /* On non-DT platforms the SPI core will set spi->cs_gpio
796                  * to -ENOENT. The GPIO pin used to drive the chip select
797                  * is defined by using platform data so spi->cs_gpio value
798                  * has to be override to have the proper GPIO pin number.
799                  */
800                 spi->cs_gpio = cs->line;
801         }
802 
803         if (IS_ERR_OR_NULL(cs)) {
804                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
805                 return -ENODEV;
806         }
807 
808         if (!spi_get_ctldata(spi)) {
809                 if (gpio_is_valid(spi->cs_gpio)) {
810                         err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
811                                                dev_name(&spi->dev));
812                         if (err) {
813                                 dev_err(&spi->dev,
814                                         "Failed to get /CS gpio [%d]: %d\n",
815                                         spi->cs_gpio, err);
816                                 goto err_gpio_req;
817                         }
818                 }
819 
820                 spi_set_ctldata(spi, cs);
821         }
822 
823         sci = sdd->cntrlr_info;
824 
825         pm_runtime_get_sync(&sdd->pdev->dev);
826 
827         /* Check if we can provide the requested rate */
828         if (!sdd->port_conf->clk_from_cmu) {
829                 u32 psr, speed;
830 
831                 /* Max possible */
832                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
833 
834                 if (spi->max_speed_hz > speed)
835                         spi->max_speed_hz = speed;
836 
837                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
838                 psr &= S3C64XX_SPI_PSR_MASK;
839                 if (psr == S3C64XX_SPI_PSR_MASK)
840                         psr--;
841 
842                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
843                 if (spi->max_speed_hz < speed) {
844                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
845                                 psr++;
846                         } else {
847                                 err = -EINVAL;
848                                 goto setup_exit;
849                         }
850                 }
851 
852                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
853                 if (spi->max_speed_hz >= speed) {
854                         spi->max_speed_hz = speed;
855                 } else {
856                         dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
857                                 spi->max_speed_hz);
858                         err = -EINVAL;
859                         goto setup_exit;
860                 }
861         }
862 
863         pm_runtime_mark_last_busy(&sdd->pdev->dev);
864         pm_runtime_put_autosuspend(&sdd->pdev->dev);
865         if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
866                 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
867         return 0;
868 
869 setup_exit:
870         pm_runtime_mark_last_busy(&sdd->pdev->dev);
871         pm_runtime_put_autosuspend(&sdd->pdev->dev);
872         /* setup() returns with device de-selected */
873         if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
874                 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
875 
876         if (gpio_is_valid(spi->cs_gpio))
877                 gpio_free(spi->cs_gpio);
878         spi_set_ctldata(spi, NULL);
879 
880 err_gpio_req:
881         if (spi->dev.of_node)
882                 kfree(cs);
883 
884         return err;
885 }
886 
887 static void s3c64xx_spi_cleanup(struct spi_device *spi)
888 {
889         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
890 
891         if (gpio_is_valid(spi->cs_gpio)) {
892                 gpio_free(spi->cs_gpio);
893                 if (spi->dev.of_node)
894                         kfree(cs);
895                 else {
896                         /* On non-DT platforms, the SPI core sets
897                          * spi->cs_gpio to -ENOENT and .setup()
898                          * overrides it with the GPIO pin value
899                          * passed using platform data.
900                          */
901                         spi->cs_gpio = -ENOENT;
902                 }
903         }
904 
905         spi_set_ctldata(spi, NULL);
906 }
907 
908 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
909 {
910         struct s3c64xx_spi_driver_data *sdd = data;
911         struct spi_master *spi = sdd->master;
912         unsigned int val, clr = 0;
913 
914         val = readl(sdd->regs + S3C64XX_SPI_STATUS);
915 
916         if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
917                 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
918                 dev_err(&spi->dev, "RX overrun\n");
919         }
920         if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
921                 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
922                 dev_err(&spi->dev, "RX underrun\n");
923         }
924         if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
925                 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
926                 dev_err(&spi->dev, "TX overrun\n");
927         }
928         if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
929                 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
930                 dev_err(&spi->dev, "TX underrun\n");
931         }
932 
933         /* Clear the pending irq by setting and then clearing it */
934         writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
935         writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
936 
937         return IRQ_HANDLED;
938 }
939 
940 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
941 {
942         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
943         void __iomem *regs = sdd->regs;
944         unsigned int val;
945 
946         sdd->cur_speed = 0;
947 
948         if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
949                 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
950 
951         /* Disable Interrupts - we use Polling if not DMA mode */
952         writel(0, regs + S3C64XX_SPI_INT_EN);
953 
954         if (!sdd->port_conf->clk_from_cmu)
955                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
956                                 regs + S3C64XX_SPI_CLK_CFG);
957         writel(0, regs + S3C64XX_SPI_MODE_CFG);
958         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
959 
960         /* Clear any irq pending bits, should set and clear the bits */
961         val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
962                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
963                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
964                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
965         writel(val, regs + S3C64XX_SPI_PENDING_CLR);
966         writel(0, regs + S3C64XX_SPI_PENDING_CLR);
967 
968         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
969 
970         val = readl(regs + S3C64XX_SPI_MODE_CFG);
971         val &= ~S3C64XX_SPI_MODE_4BURST;
972         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
973         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
974         writel(val, regs + S3C64XX_SPI_MODE_CFG);
975 
976         flush_fifo(sdd);
977 }
978 
979 #ifdef CONFIG_OF
980 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
981 {
982         struct s3c64xx_spi_info *sci;
983         u32 temp;
984 
985         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
986         if (!sci)
987                 return ERR_PTR(-ENOMEM);
988 
989         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
990                 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
991                 sci->src_clk_nr = 0;
992         } else {
993                 sci->src_clk_nr = temp;
994         }
995 
996         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
997                 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
998                 sci->num_cs = 1;
999         } else {
1000                 sci->num_cs = temp;
1001         }
1002 
1003         return sci;
1004 }
1005 #else
1006 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1007 {
1008         return dev_get_platdata(dev);
1009 }
1010 #endif
1011 
1012 static const struct of_device_id s3c64xx_spi_dt_match[];
1013 
1014 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1015                                                 struct platform_device *pdev)
1016 {
1017 #ifdef CONFIG_OF
1018         if (pdev->dev.of_node) {
1019                 const struct of_device_id *match;
1020                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1021                 return (struct s3c64xx_spi_port_config *)match->data;
1022         }
1023 #endif
1024         return (struct s3c64xx_spi_port_config *)
1025                          platform_get_device_id(pdev)->driver_data;
1026 }
1027 
1028 static int s3c64xx_spi_probe(struct platform_device *pdev)
1029 {
1030         struct resource *mem_res;
1031         struct resource *res;
1032         struct s3c64xx_spi_driver_data *sdd;
1033         struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1034         struct spi_master *master;
1035         int ret, irq;
1036         char clk_name[16];
1037 
1038         if (!sci && pdev->dev.of_node) {
1039                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1040                 if (IS_ERR(sci))
1041                         return PTR_ERR(sci);
1042         }
1043 
1044         if (!sci) {
1045                 dev_err(&pdev->dev, "platform_data missing!\n");
1046                 return -ENODEV;
1047         }
1048 
1049         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1050         if (mem_res == NULL) {
1051                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1052                 return -ENXIO;
1053         }
1054 
1055         irq = platform_get_irq(pdev, 0);
1056         if (irq < 0) {
1057                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1058                 return irq;
1059         }
1060 
1061         master = spi_alloc_master(&pdev->dev,
1062                                 sizeof(struct s3c64xx_spi_driver_data));
1063         if (master == NULL) {
1064                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1065                 return -ENOMEM;
1066         }
1067 
1068         platform_set_drvdata(pdev, master);
1069 
1070         sdd = spi_master_get_devdata(master);
1071         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1072         sdd->master = master;
1073         sdd->cntrlr_info = sci;
1074         sdd->pdev = pdev;
1075         sdd->sfr_start = mem_res->start;
1076         if (pdev->dev.of_node) {
1077                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1078                 if (ret < 0) {
1079                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1080                                 ret);
1081                         goto err0;
1082                 }
1083                 sdd->port_id = ret;
1084         } else {
1085                 sdd->port_id = pdev->id;
1086         }
1087 
1088         sdd->cur_bpw = 8;
1089 
1090         if (!sdd->pdev->dev.of_node) {
1091                 res = platform_get_resource(pdev, IORESOURCE_DMA,  0);
1092                 if (!res) {
1093                         dev_warn(&pdev->dev, "Unable to get SPI tx dma resource. Switching to poll mode\n");
1094                         sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1095                 } else
1096                         sdd->tx_dma.dmach = res->start;
1097 
1098                 res = platform_get_resource(pdev, IORESOURCE_DMA,  1);
1099                 if (!res) {
1100                         dev_warn(&pdev->dev, "Unable to get SPI rx dma resource. Switching to poll mode\n");
1101                         sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1102                 } else
1103                         sdd->rx_dma.dmach = res->start;
1104         }
1105 
1106         sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1107         sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1108 
1109         master->dev.of_node = pdev->dev.of_node;
1110         master->bus_num = sdd->port_id;
1111         master->setup = s3c64xx_spi_setup;
1112         master->cleanup = s3c64xx_spi_cleanup;
1113         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1114         master->prepare_message = s3c64xx_spi_prepare_message;
1115         master->transfer_one = s3c64xx_spi_transfer_one;
1116         master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1117         master->num_chipselect = sci->num_cs;
1118         master->dma_alignment = 8;
1119         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1120                                         SPI_BPW_MASK(8);
1121         /* the spi->mode bits understood by this driver: */
1122         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1123         master->auto_runtime_pm = true;
1124         if (!is_polling(sdd))
1125                 master->can_dma = s3c64xx_spi_can_dma;
1126 
1127         sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1128         if (IS_ERR(sdd->regs)) {
1129                 ret = PTR_ERR(sdd->regs);
1130                 goto err0;
1131         }
1132 
1133         if (sci->cfg_gpio && sci->cfg_gpio()) {
1134                 dev_err(&pdev->dev, "Unable to config gpio\n");
1135                 ret = -EBUSY;
1136                 goto err0;
1137         }
1138 
1139         /* Setup clocks */
1140         sdd->clk = devm_clk_get(&pdev->dev, "spi");
1141         if (IS_ERR(sdd->clk)) {
1142                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1143                 ret = PTR_ERR(sdd->clk);
1144                 goto err0;
1145         }
1146 
1147         if (clk_prepare_enable(sdd->clk)) {
1148                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1149                 ret = -EBUSY;
1150                 goto err0;
1151         }
1152 
1153         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1154         sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1155         if (IS_ERR(sdd->src_clk)) {
1156                 dev_err(&pdev->dev,
1157                         "Unable to acquire clock '%s'\n", clk_name);
1158                 ret = PTR_ERR(sdd->src_clk);
1159                 goto err2;
1160         }
1161 
1162         if (clk_prepare_enable(sdd->src_clk)) {
1163                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1164                 ret = -EBUSY;
1165                 goto err2;
1166         }
1167 
1168         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1169         pm_runtime_use_autosuspend(&pdev->dev);
1170         pm_runtime_set_active(&pdev->dev);
1171         pm_runtime_enable(&pdev->dev);
1172         pm_runtime_get_sync(&pdev->dev);
1173 
1174         /* Setup Deufult Mode */
1175         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1176 
1177         spin_lock_init(&sdd->lock);
1178         init_completion(&sdd->xfer_completion);
1179 
1180         ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1181                                 "spi-s3c64xx", sdd);
1182         if (ret != 0) {
1183                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1184                         irq, ret);
1185                 goto err3;
1186         }
1187 
1188         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1189                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1190                sdd->regs + S3C64XX_SPI_INT_EN);
1191 
1192         ret = devm_spi_register_master(&pdev->dev, master);
1193         if (ret != 0) {
1194                 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1195                 goto err3;
1196         }
1197 
1198         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1199                                         sdd->port_id, master->num_chipselect);
1200         dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\tDMA=[Rx-%d, Tx-%d]\n",
1201                                         mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1,
1202                                         sdd->rx_dma.dmach, sdd->tx_dma.dmach);
1203 
1204         pm_runtime_mark_last_busy(&pdev->dev);
1205         pm_runtime_put_autosuspend(&pdev->dev);
1206 
1207         return 0;
1208 
1209 err3:
1210         pm_runtime_put_noidle(&pdev->dev);
1211         pm_runtime_disable(&pdev->dev);
1212         pm_runtime_set_suspended(&pdev->dev);
1213 
1214         clk_disable_unprepare(sdd->src_clk);
1215 err2:
1216         clk_disable_unprepare(sdd->clk);
1217 err0:
1218         spi_master_put(master);
1219 
1220         return ret;
1221 }
1222 
1223 static int s3c64xx_spi_remove(struct platform_device *pdev)
1224 {
1225         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1226         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1227 
1228         pm_runtime_get_sync(&pdev->dev);
1229 
1230         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1231 
1232         clk_disable_unprepare(sdd->src_clk);
1233 
1234         clk_disable_unprepare(sdd->clk);
1235 
1236         pm_runtime_put_noidle(&pdev->dev);
1237         pm_runtime_disable(&pdev->dev);
1238         pm_runtime_set_suspended(&pdev->dev);
1239 
1240         return 0;
1241 }
1242 
1243 #ifdef CONFIG_PM_SLEEP
1244 static int s3c64xx_spi_suspend(struct device *dev)
1245 {
1246         struct spi_master *master = dev_get_drvdata(dev);
1247         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1248 
1249         int ret = spi_master_suspend(master);
1250         if (ret)
1251                 return ret;
1252 
1253         ret = pm_runtime_force_suspend(dev);
1254         if (ret < 0)
1255                 return ret;
1256 
1257         sdd->cur_speed = 0; /* Output Clock is stopped */
1258 
1259         return 0;
1260 }
1261 
1262 static int s3c64xx_spi_resume(struct device *dev)
1263 {
1264         struct spi_master *master = dev_get_drvdata(dev);
1265         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1266         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1267         int ret;
1268 
1269         if (sci->cfg_gpio)
1270                 sci->cfg_gpio();
1271 
1272         ret = pm_runtime_force_resume(dev);
1273         if (ret < 0)
1274                 return ret;
1275 
1276         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1277 
1278         return spi_master_resume(master);
1279 }
1280 #endif /* CONFIG_PM_SLEEP */
1281 
1282 #ifdef CONFIG_PM
1283 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1284 {
1285         struct spi_master *master = dev_get_drvdata(dev);
1286         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1287 
1288         clk_disable_unprepare(sdd->clk);
1289         clk_disable_unprepare(sdd->src_clk);
1290 
1291         return 0;
1292 }
1293 
1294 static int s3c64xx_spi_runtime_resume(struct device *dev)
1295 {
1296         struct spi_master *master = dev_get_drvdata(dev);
1297         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1298         int ret;
1299 
1300         ret = clk_prepare_enable(sdd->src_clk);
1301         if (ret != 0)
1302                 return ret;
1303 
1304         ret = clk_prepare_enable(sdd->clk);
1305         if (ret != 0) {
1306                 clk_disable_unprepare(sdd->src_clk);
1307                 return ret;
1308         }
1309 
1310         return 0;
1311 }
1312 #endif /* CONFIG_PM */
1313 
1314 static const struct dev_pm_ops s3c64xx_spi_pm = {
1315         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1316         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1317                            s3c64xx_spi_runtime_resume, NULL)
1318 };
1319 
1320 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1321         .fifo_lvl_mask  = { 0x7f },
1322         .rx_lvl_offset  = 13,
1323         .tx_st_done     = 21,
1324         .high_speed     = true,
1325 };
1326 
1327 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1328         .fifo_lvl_mask  = { 0x7f, 0x7F },
1329         .rx_lvl_offset  = 13,
1330         .tx_st_done     = 21,
1331 };
1332 
1333 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1334         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1335         .rx_lvl_offset  = 15,
1336         .tx_st_done     = 25,
1337         .high_speed     = true,
1338 };
1339 
1340 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1341         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1342         .rx_lvl_offset  = 15,
1343         .tx_st_done     = 25,
1344         .high_speed     = true,
1345         .clk_from_cmu   = true,
1346 };
1347 
1348 static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1349         .fifo_lvl_mask  = { 0x1ff },
1350         .rx_lvl_offset  = 15,
1351         .tx_st_done     = 25,
1352         .high_speed     = true,
1353         .clk_from_cmu   = true,
1354         .quirks         = S3C64XX_SPI_QUIRK_POLL,
1355 };
1356 
1357 static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1358         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1359         .rx_lvl_offset  = 15,
1360         .tx_st_done     = 25,
1361         .high_speed     = true,
1362         .clk_from_cmu   = true,
1363         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1364 };
1365 
1366 static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1367         {
1368                 .name           = "s3c2443-spi",
1369                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1370         }, {
1371                 .name           = "s3c6410-spi",
1372                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1373         }, {
1374                 .name           = "s5pv210-spi",
1375                 .driver_data    = (kernel_ulong_t)&s5pv210_spi_port_config,
1376         }, {
1377                 .name           = "exynos4210-spi",
1378                 .driver_data    = (kernel_ulong_t)&exynos4_spi_port_config,
1379         },
1380         { },
1381 };
1382 
1383 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1384         { .compatible = "samsung,s3c2443-spi",
1385                         .data = (void *)&s3c2443_spi_port_config,
1386         },
1387         { .compatible = "samsung,s3c6410-spi",
1388                         .data = (void *)&s3c6410_spi_port_config,
1389         },
1390         { .compatible = "samsung,s5pv210-spi",
1391                         .data = (void *)&s5pv210_spi_port_config,
1392         },
1393         { .compatible = "samsung,exynos4210-spi",
1394                         .data = (void *)&exynos4_spi_port_config,
1395         },
1396         { .compatible = "samsung,exynos5440-spi",
1397                         .data = (void *)&exynos5440_spi_port_config,
1398         },
1399         { .compatible = "samsung,exynos7-spi",
1400                         .data = (void *)&exynos7_spi_port_config,
1401         },
1402         { },
1403 };
1404 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1405 
1406 static struct platform_driver s3c64xx_spi_driver = {
1407         .driver = {
1408                 .name   = "s3c64xx-spi",
1409                 .pm = &s3c64xx_spi_pm,
1410                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1411         },
1412         .probe = s3c64xx_spi_probe,
1413         .remove = s3c64xx_spi_remove,
1414         .id_table = s3c64xx_spi_driver_ids,
1415 };
1416 MODULE_ALIAS("platform:s3c64xx-spi");
1417 
1418 module_platform_driver(s3c64xx_spi_driver);
1419 
1420 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1421 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1422 MODULE_LICENSE("GPL");
1423 

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