Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/spi/spi-s3c24xx.c

  1 /*
  2  * Copyright (c) 2006 Ben Dooks
  3  * Copyright 2006-2009 Simtec Electronics
  4  *      Ben Dooks <ben@simtec.co.uk>
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  *
 10 */
 11 
 12 #include <linux/spinlock.h>
 13 #include <linux/interrupt.h>
 14 #include <linux/delay.h>
 15 #include <linux/errno.h>
 16 #include <linux/err.h>
 17 #include <linux/clk.h>
 18 #include <linux/platform_device.h>
 19 #include <linux/gpio.h>
 20 #include <linux/io.h>
 21 #include <linux/slab.h>
 22 
 23 #include <linux/spi/spi.h>
 24 #include <linux/spi/spi_bitbang.h>
 25 #include <linux/spi/s3c24xx.h>
 26 #include <linux/module.h>
 27 
 28 #include <plat/regs-spi.h>
 29 
 30 #include <asm/fiq.h>
 31 
 32 #include "spi-s3c24xx-fiq.h"
 33 
 34 /**
 35  * s3c24xx_spi_devstate - per device data
 36  * @hz: Last frequency calculated for @sppre field.
 37  * @mode: Last mode setting for the @spcon field.
 38  * @spcon: Value to write to the SPCON register.
 39  * @sppre: Value to write to the SPPRE register.
 40  */
 41 struct s3c24xx_spi_devstate {
 42         unsigned int    hz;
 43         unsigned int    mode;
 44         u8              spcon;
 45         u8              sppre;
 46 };
 47 
 48 enum spi_fiq_mode {
 49         FIQ_MODE_NONE   = 0,
 50         FIQ_MODE_TX     = 1,
 51         FIQ_MODE_RX     = 2,
 52         FIQ_MODE_TXRX   = 3,
 53 };
 54 
 55 struct s3c24xx_spi {
 56         /* bitbang has to be first */
 57         struct spi_bitbang       bitbang;
 58         struct completion        done;
 59 
 60         void __iomem            *regs;
 61         int                      irq;
 62         int                      len;
 63         int                      count;
 64 
 65         struct fiq_handler       fiq_handler;
 66         enum spi_fiq_mode        fiq_mode;
 67         unsigned char            fiq_inuse;
 68         unsigned char            fiq_claimed;
 69 
 70         void                    (*set_cs)(struct s3c2410_spi_info *spi,
 71                                           int cs, int pol);
 72 
 73         /* data buffers */
 74         const unsigned char     *tx;
 75         unsigned char           *rx;
 76 
 77         struct clk              *clk;
 78         struct spi_master       *master;
 79         struct spi_device       *curdev;
 80         struct device           *dev;
 81         struct s3c2410_spi_info *pdata;
 82 };
 83 
 84 #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
 85 #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
 86 
 87 static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
 88 {
 89         return spi_master_get_devdata(sdev->master);
 90 }
 91 
 92 static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
 93 {
 94         gpio_set_value(spi->pin_cs, pol);
 95 }
 96 
 97 static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
 98 {
 99         struct s3c24xx_spi_devstate *cs = spi->controller_state;
100         struct s3c24xx_spi *hw = to_hw(spi);
101         unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
102 
103         /* change the chipselect state and the state of the spi engine clock */
104 
105         switch (value) {
106         case BITBANG_CS_INACTIVE:
107                 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
108                 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
109                 break;
110 
111         case BITBANG_CS_ACTIVE:
112                 writeb(cs->spcon | S3C2410_SPCON_ENSCK,
113                        hw->regs + S3C2410_SPCON);
114                 hw->set_cs(hw->pdata, spi->chip_select, cspol);
115                 break;
116         }
117 }
118 
119 static int s3c24xx_spi_update_state(struct spi_device *spi,
120                                     struct spi_transfer *t)
121 {
122         struct s3c24xx_spi *hw = to_hw(spi);
123         struct s3c24xx_spi_devstate *cs = spi->controller_state;
124         unsigned int hz;
125         unsigned int div;
126         unsigned long clk;
127 
128         hz  = t ? t->speed_hz : spi->max_speed_hz;
129 
130         if (!hz)
131                 hz = spi->max_speed_hz;
132 
133         if (spi->mode != cs->mode) {
134                 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
135 
136                 if (spi->mode & SPI_CPHA)
137                         spcon |= S3C2410_SPCON_CPHA_FMTB;
138 
139                 if (spi->mode & SPI_CPOL)
140                         spcon |= S3C2410_SPCON_CPOL_HIGH;
141 
142                 cs->mode = spi->mode;
143                 cs->spcon = spcon;
144         }
145 
146         if (cs->hz != hz) {
147                 clk = clk_get_rate(hw->clk);
148                 div = DIV_ROUND_UP(clk, hz * 2) - 1;
149 
150                 if (div > 255)
151                         div = 255;
152 
153                 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
154                         div, hz, clk / (2 * (div + 1)));
155 
156                 cs->hz = hz;
157                 cs->sppre = div;
158         }
159 
160         return 0;
161 }
162 
163 static int s3c24xx_spi_setupxfer(struct spi_device *spi,
164                                  struct spi_transfer *t)
165 {
166         struct s3c24xx_spi_devstate *cs = spi->controller_state;
167         struct s3c24xx_spi *hw = to_hw(spi);
168         int ret;
169 
170         ret = s3c24xx_spi_update_state(spi, t);
171         if (!ret)
172                 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
173 
174         return ret;
175 }
176 
177 static int s3c24xx_spi_setup(struct spi_device *spi)
178 {
179         struct s3c24xx_spi_devstate *cs = spi->controller_state;
180         struct s3c24xx_spi *hw = to_hw(spi);
181         int ret;
182 
183         /* allocate settings on the first call */
184         if (!cs) {
185                 cs = devm_kzalloc(&spi->dev,
186                                   sizeof(struct s3c24xx_spi_devstate),
187                                   GFP_KERNEL);
188                 if (!cs)
189                         return -ENOMEM;
190 
191                 cs->spcon = SPCON_DEFAULT;
192                 cs->hz = -1;
193                 spi->controller_state = cs;
194         }
195 
196         /* initialise the state from the device */
197         ret = s3c24xx_spi_update_state(spi, NULL);
198         if (ret)
199                 return ret;
200 
201         spin_lock(&hw->bitbang.lock);
202         if (!hw->bitbang.busy) {
203                 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
204                 /* need to ndelay for 0.5 clocktick ? */
205         }
206         spin_unlock(&hw->bitbang.lock);
207 
208         return 0;
209 }
210 
211 static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
212 {
213         return hw->tx ? hw->tx[count] : 0;
214 }
215 
216 #ifdef CONFIG_SPI_S3C24XX_FIQ
217 /* Support for FIQ based pseudo-DMA to improve the transfer speed.
218  *
219  * This code uses the assembly helper in spi_s3c24xx_spi.S which is
220  * used by the FIQ core to move data between main memory and the peripheral
221  * block. Since this is code running on the processor, there is no problem
222  * with cache coherency of the buffers, so we can use any buffer we like.
223  */
224 
225 /**
226  * struct spi_fiq_code - FIQ code and header
227  * @length: The length of the code fragment, excluding this header.
228  * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
229  * @data: The code itself to install as a FIQ handler.
230  */
231 struct spi_fiq_code {
232         u32     length;
233         u32     ack_offset;
234         u8      data[0];
235 };
236 
237 extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
238 extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
239 extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
240 
241 /**
242  * ack_bit - turn IRQ into IRQ acknowledgement bit
243  * @irq: The interrupt number
244  *
245  * Returns the bit to write to the interrupt acknowledge register.
246  */
247 static inline u32 ack_bit(unsigned int irq)
248 {
249         return 1 << (irq - IRQ_EINT0);
250 }
251 
252 /**
253  * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
254  * @hw: The hardware state.
255  *
256  * Claim the FIQ handler (only one can be active at any one time) and
257  * then setup the correct transfer code for this transfer.
258  *
259  * This call updates all the necessary state information if successful,
260  * so the caller does not need to do anything more than start the transfer
261  * as normal, since the IRQ will have been re-routed to the FIQ handler.
262 */
263 static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
264 {
265         struct pt_regs regs;
266         enum spi_fiq_mode mode;
267         struct spi_fiq_code *code;
268         int ret;
269 
270         if (!hw->fiq_claimed) {
271                 /* try and claim fiq if we haven't got it, and if not
272                  * then return and simply use another transfer method */
273 
274                 ret = claim_fiq(&hw->fiq_handler);
275                 if (ret)
276                         return;
277         }
278 
279         if (hw->tx && !hw->rx)
280                 mode = FIQ_MODE_TX;
281         else if (hw->rx && !hw->tx)
282                 mode = FIQ_MODE_RX;
283         else
284                 mode = FIQ_MODE_TXRX;
285 
286         regs.uregs[fiq_rspi] = (long)hw->regs;
287         regs.uregs[fiq_rrx]  = (long)hw->rx;
288         regs.uregs[fiq_rtx]  = (long)hw->tx + 1;
289         regs.uregs[fiq_rcount] = hw->len - 1;
290         regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
291 
292         set_fiq_regs(&regs);
293 
294         if (hw->fiq_mode != mode) {
295                 u32 *ack_ptr;
296 
297                 hw->fiq_mode = mode;
298 
299                 switch (mode) {
300                 case FIQ_MODE_TX:
301                         code = &s3c24xx_spi_fiq_tx;
302                         break;
303                 case FIQ_MODE_RX:
304                         code = &s3c24xx_spi_fiq_rx;
305                         break;
306                 case FIQ_MODE_TXRX:
307                         code = &s3c24xx_spi_fiq_txrx;
308                         break;
309                 default:
310                         code = NULL;
311                 }
312 
313                 BUG_ON(!code);
314 
315                 ack_ptr = (u32 *)&code->data[code->ack_offset];
316                 *ack_ptr = ack_bit(hw->irq);
317 
318                 set_fiq_handler(&code->data, code->length);
319         }
320 
321         s3c24xx_set_fiq(hw->irq, true);
322 
323         hw->fiq_mode = mode;
324         hw->fiq_inuse = 1;
325 }
326 
327 /**
328  * s3c24xx_spi_fiqop - FIQ core code callback
329  * @pw: Data registered with the handler
330  * @release: Whether this is a release or a return.
331  *
332  * Called by the FIQ code when another module wants to use the FIQ, so
333  * return whether we are currently using this or not and then update our
334  * internal state.
335  */
336 static int s3c24xx_spi_fiqop(void *pw, int release)
337 {
338         struct s3c24xx_spi *hw = pw;
339         int ret = 0;
340 
341         if (release) {
342                 if (hw->fiq_inuse)
343                         ret = -EBUSY;
344 
345                 /* note, we do not need to unroute the FIQ, as the FIQ
346                  * vector code de-routes it to signal the end of transfer */
347 
348                 hw->fiq_mode = FIQ_MODE_NONE;
349                 hw->fiq_claimed = 0;
350         } else {
351                 hw->fiq_claimed = 1;
352         }
353 
354         return ret;
355 }
356 
357 /**
358  * s3c24xx_spi_initfiq - setup the information for the FIQ core
359  * @hw: The hardware state.
360  *
361  * Setup the fiq_handler block to pass to the FIQ core.
362  */
363 static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
364 {
365         hw->fiq_handler.dev_id = hw;
366         hw->fiq_handler.name = dev_name(hw->dev);
367         hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
368 }
369 
370 /**
371  * s3c24xx_spi_usefiq - return if we should be using FIQ.
372  * @hw: The hardware state.
373  *
374  * Return true if the platform data specifies whether this channel is
375  * allowed to use the FIQ.
376  */
377 static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
378 {
379         return hw->pdata->use_fiq;
380 }
381 
382 /**
383  * s3c24xx_spi_usingfiq - return if channel is using FIQ
384  * @spi: The hardware state.
385  *
386  * Return whether the channel is currently using the FIQ (separate from
387  * whether the FIQ is claimed).
388  */
389 static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
390 {
391         return spi->fiq_inuse;
392 }
393 #else
394 
395 static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
396 static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
397 static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
398 static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
399 
400 #endif /* CONFIG_SPI_S3C24XX_FIQ */
401 
402 static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
403 {
404         struct s3c24xx_spi *hw = to_hw(spi);
405 
406         hw->tx = t->tx_buf;
407         hw->rx = t->rx_buf;
408         hw->len = t->len;
409         hw->count = 0;
410 
411         init_completion(&hw->done);
412 
413         hw->fiq_inuse = 0;
414         if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
415                 s3c24xx_spi_tryfiq(hw);
416 
417         /* send the first byte */
418         writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
419 
420         wait_for_completion(&hw->done);
421         return hw->count;
422 }
423 
424 static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
425 {
426         struct s3c24xx_spi *hw = dev;
427         unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
428         unsigned int count = hw->count;
429 
430         if (spsta & S3C2410_SPSTA_DCOL) {
431                 dev_dbg(hw->dev, "data-collision\n");
432                 complete(&hw->done);
433                 goto irq_done;
434         }
435 
436         if (!(spsta & S3C2410_SPSTA_READY)) {
437                 dev_dbg(hw->dev, "spi not ready for tx?\n");
438                 complete(&hw->done);
439                 goto irq_done;
440         }
441 
442         if (!s3c24xx_spi_usingfiq(hw)) {
443                 hw->count++;
444 
445                 if (hw->rx)
446                         hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
447 
448                 count++;
449 
450                 if (count < hw->len)
451                         writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
452                 else
453                         complete(&hw->done);
454         } else {
455                 hw->count = hw->len;
456                 hw->fiq_inuse = 0;
457 
458                 if (hw->rx)
459                         hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
460 
461                 complete(&hw->done);
462         }
463 
464  irq_done:
465         return IRQ_HANDLED;
466 }
467 
468 static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
469 {
470         /* for the moment, permanently enable the clock */
471 
472         clk_enable(hw->clk);
473 
474         /* program defaults into the registers */
475 
476         writeb(0xff, hw->regs + S3C2410_SPPRE);
477         writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
478         writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
479 
480         if (hw->pdata) {
481                 if (hw->set_cs == s3c24xx_spi_gpiocs)
482                         gpio_direction_output(hw->pdata->pin_cs, 1);
483 
484                 if (hw->pdata->gpio_setup)
485                         hw->pdata->gpio_setup(hw->pdata, 1);
486         }
487 }
488 
489 static int s3c24xx_spi_probe(struct platform_device *pdev)
490 {
491         struct s3c2410_spi_info *pdata;
492         struct s3c24xx_spi *hw;
493         struct spi_master *master;
494         struct resource *res;
495         int err = 0;
496 
497         master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
498         if (master == NULL) {
499                 dev_err(&pdev->dev, "No memory for spi_master\n");
500                 return -ENOMEM;
501         }
502 
503         hw = spi_master_get_devdata(master);
504         memset(hw, 0, sizeof(struct s3c24xx_spi));
505 
506         hw->master = master;
507         hw->pdata = pdata = dev_get_platdata(&pdev->dev);
508         hw->dev = &pdev->dev;
509 
510         if (pdata == NULL) {
511                 dev_err(&pdev->dev, "No platform data supplied\n");
512                 err = -ENOENT;
513                 goto err_no_pdata;
514         }
515 
516         platform_set_drvdata(pdev, hw);
517         init_completion(&hw->done);
518 
519         /* initialise fiq handler */
520 
521         s3c24xx_spi_initfiq(hw);
522 
523         /* setup the master state. */
524 
525         /* the spi->mode bits understood by this driver: */
526         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
527 
528         master->num_chipselect = hw->pdata->num_cs;
529         master->bus_num = pdata->bus_num;
530         master->bits_per_word_mask = SPI_BPW_MASK(8);
531 
532         /* setup the state for the bitbang driver */
533 
534         hw->bitbang.master         = hw->master;
535         hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
536         hw->bitbang.chipselect     = s3c24xx_spi_chipsel;
537         hw->bitbang.txrx_bufs      = s3c24xx_spi_txrx;
538 
539         hw->master->setup  = s3c24xx_spi_setup;
540 
541         dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
542 
543         /* find and map our resources */
544         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
545         hw->regs = devm_ioremap_resource(&pdev->dev, res);
546         if (IS_ERR(hw->regs)) {
547                 err = PTR_ERR(hw->regs);
548                 goto err_no_pdata;
549         }
550 
551         hw->irq = platform_get_irq(pdev, 0);
552         if (hw->irq < 0) {
553                 dev_err(&pdev->dev, "No IRQ specified\n");
554                 err = -ENOENT;
555                 goto err_no_pdata;
556         }
557 
558         err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
559                                 pdev->name, hw);
560         if (err) {
561                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
562                 goto err_no_pdata;
563         }
564 
565         hw->clk = devm_clk_get(&pdev->dev, "spi");
566         if (IS_ERR(hw->clk)) {
567                 dev_err(&pdev->dev, "No clock for device\n");
568                 err = PTR_ERR(hw->clk);
569                 goto err_no_pdata;
570         }
571 
572         /* setup any gpio we can */
573 
574         if (!pdata->set_cs) {
575                 if (pdata->pin_cs < 0) {
576                         dev_err(&pdev->dev, "No chipselect pin\n");
577                         err = -EINVAL;
578                         goto err_register;
579                 }
580 
581                 err = devm_gpio_request(&pdev->dev, pdata->pin_cs,
582                                         dev_name(&pdev->dev));
583                 if (err) {
584                         dev_err(&pdev->dev, "Failed to get gpio for cs\n");
585                         goto err_register;
586                 }
587 
588                 hw->set_cs = s3c24xx_spi_gpiocs;
589                 gpio_direction_output(pdata->pin_cs, 1);
590         } else
591                 hw->set_cs = pdata->set_cs;
592 
593         s3c24xx_spi_initialsetup(hw);
594 
595         /* register our spi controller */
596 
597         err = spi_bitbang_start(&hw->bitbang);
598         if (err) {
599                 dev_err(&pdev->dev, "Failed to register SPI master\n");
600                 goto err_register;
601         }
602 
603         return 0;
604 
605  err_register:
606         clk_disable(hw->clk);
607 
608  err_no_pdata:
609         spi_master_put(hw->master);
610         return err;
611 }
612 
613 static int s3c24xx_spi_remove(struct platform_device *dev)
614 {
615         struct s3c24xx_spi *hw = platform_get_drvdata(dev);
616 
617         spi_bitbang_stop(&hw->bitbang);
618         clk_disable(hw->clk);
619         spi_master_put(hw->master);
620         return 0;
621 }
622 
623 
624 #ifdef CONFIG_PM
625 
626 static int s3c24xx_spi_suspend(struct device *dev)
627 {
628         struct s3c24xx_spi *hw = dev_get_drvdata(dev);
629         int ret;
630 
631         ret = spi_master_suspend(hw->master);
632         if (ret)
633                 return ret;
634 
635         if (hw->pdata && hw->pdata->gpio_setup)
636                 hw->pdata->gpio_setup(hw->pdata, 0);
637 
638         clk_disable(hw->clk);
639         return 0;
640 }
641 
642 static int s3c24xx_spi_resume(struct device *dev)
643 {
644         struct s3c24xx_spi *hw = dev_get_drvdata(dev);
645 
646         s3c24xx_spi_initialsetup(hw);
647         return spi_master_resume(hw->master);
648 }
649 
650 static const struct dev_pm_ops s3c24xx_spi_pmops = {
651         .suspend        = s3c24xx_spi_suspend,
652         .resume         = s3c24xx_spi_resume,
653 };
654 
655 #define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
656 #else
657 #define S3C24XX_SPI_PMOPS NULL
658 #endif /* CONFIG_PM */
659 
660 MODULE_ALIAS("platform:s3c2410-spi");
661 static struct platform_driver s3c24xx_spi_driver = {
662         .probe          = s3c24xx_spi_probe,
663         .remove         = s3c24xx_spi_remove,
664         .driver         = {
665                 .name   = "s3c2410-spi",
666                 .owner  = THIS_MODULE,
667                 .pm     = S3C24XX_SPI_PMOPS,
668         },
669 };
670 module_platform_driver(s3c24xx_spi_driver);
671 
672 MODULE_DESCRIPTION("S3C24XX SPI Driver");
673 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
674 MODULE_LICENSE("GPL");
675 

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