Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/spi/spi-rspi.c

  1 /*
  2  * SH RSPI driver
  3  *
  4  * Copyright (C) 2012, 2013  Renesas Solutions Corp.
  5  * Copyright (C) 2014 Glider bvba
  6  *
  7  * Based on spi-sh.c:
  8  * Copyright (C) 2011 Renesas Solutions Corp.
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License as published by
 12  * the Free Software Foundation; version 2 of the License.
 13  *
 14  * This program is distributed in the hope that it will be useful,
 15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17  * GNU General Public License for more details.
 18  *
 19  * You should have received a copy of the GNU General Public License
 20  * along with this program; if not, write to the Free Software
 21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 22  *
 23  */
 24 
 25 #include <linux/module.h>
 26 #include <linux/kernel.h>
 27 #include <linux/sched.h>
 28 #include <linux/errno.h>
 29 #include <linux/interrupt.h>
 30 #include <linux/platform_device.h>
 31 #include <linux/io.h>
 32 #include <linux/clk.h>
 33 #include <linux/dmaengine.h>
 34 #include <linux/dma-mapping.h>
 35 #include <linux/of_device.h>
 36 #include <linux/pm_runtime.h>
 37 #include <linux/sh_dma.h>
 38 #include <linux/spi/spi.h>
 39 #include <linux/spi/rspi.h>
 40 
 41 #define RSPI_SPCR               0x00    /* Control Register */
 42 #define RSPI_SSLP               0x01    /* Slave Select Polarity Register */
 43 #define RSPI_SPPCR              0x02    /* Pin Control Register */
 44 #define RSPI_SPSR               0x03    /* Status Register */
 45 #define RSPI_SPDR               0x04    /* Data Register */
 46 #define RSPI_SPSCR              0x08    /* Sequence Control Register */
 47 #define RSPI_SPSSR              0x09    /* Sequence Status Register */
 48 #define RSPI_SPBR               0x0a    /* Bit Rate Register */
 49 #define RSPI_SPDCR              0x0b    /* Data Control Register */
 50 #define RSPI_SPCKD              0x0c    /* Clock Delay Register */
 51 #define RSPI_SSLND              0x0d    /* Slave Select Negation Delay Register */
 52 #define RSPI_SPND               0x0e    /* Next-Access Delay Register */
 53 #define RSPI_SPCR2              0x0f    /* Control Register 2 (SH only) */
 54 #define RSPI_SPCMD0             0x10    /* Command Register 0 */
 55 #define RSPI_SPCMD1             0x12    /* Command Register 1 */
 56 #define RSPI_SPCMD2             0x14    /* Command Register 2 */
 57 #define RSPI_SPCMD3             0x16    /* Command Register 3 */
 58 #define RSPI_SPCMD4             0x18    /* Command Register 4 */
 59 #define RSPI_SPCMD5             0x1a    /* Command Register 5 */
 60 #define RSPI_SPCMD6             0x1c    /* Command Register 6 */
 61 #define RSPI_SPCMD7             0x1e    /* Command Register 7 */
 62 #define RSPI_SPCMD(i)           (RSPI_SPCMD0 + (i) * 2)
 63 #define RSPI_NUM_SPCMD          8
 64 #define RSPI_RZ_NUM_SPCMD       4
 65 #define QSPI_NUM_SPCMD          4
 66 
 67 /* RSPI on RZ only */
 68 #define RSPI_SPBFCR             0x20    /* Buffer Control Register */
 69 #define RSPI_SPBFDR             0x22    /* Buffer Data Count Setting Register */
 70 
 71 /* QSPI only */
 72 #define QSPI_SPBFCR             0x18    /* Buffer Control Register */
 73 #define QSPI_SPBDCR             0x1a    /* Buffer Data Count Register */
 74 #define QSPI_SPBMUL0            0x1c    /* Transfer Data Length Multiplier Setting Register 0 */
 75 #define QSPI_SPBMUL1            0x20    /* Transfer Data Length Multiplier Setting Register 1 */
 76 #define QSPI_SPBMUL2            0x24    /* Transfer Data Length Multiplier Setting Register 2 */
 77 #define QSPI_SPBMUL3            0x28    /* Transfer Data Length Multiplier Setting Register 3 */
 78 #define QSPI_SPBMUL(i)          (QSPI_SPBMUL0 + (i) * 4)
 79 
 80 /* SPCR - Control Register */
 81 #define SPCR_SPRIE              0x80    /* Receive Interrupt Enable */
 82 #define SPCR_SPE                0x40    /* Function Enable */
 83 #define SPCR_SPTIE              0x20    /* Transmit Interrupt Enable */
 84 #define SPCR_SPEIE              0x10    /* Error Interrupt Enable */
 85 #define SPCR_MSTR               0x08    /* Master/Slave Mode Select */
 86 #define SPCR_MODFEN             0x04    /* Mode Fault Error Detection Enable */
 87 /* RSPI on SH only */
 88 #define SPCR_TXMD               0x02    /* TX Only Mode (vs. Full Duplex) */
 89 #define SPCR_SPMS               0x01    /* 3-wire Mode (vs. 4-wire) */
 90 /* QSPI on R-Car M2 only */
 91 #define SPCR_WSWAP              0x02    /* Word Swap of read-data for DMAC */
 92 #define SPCR_BSWAP              0x01    /* Byte Swap of read-data for DMAC */
 93 
 94 /* SSLP - Slave Select Polarity Register */
 95 #define SSLP_SSL1P              0x02    /* SSL1 Signal Polarity Setting */
 96 #define SSLP_SSL0P              0x01    /* SSL0 Signal Polarity Setting */
 97 
 98 /* SPPCR - Pin Control Register */
 99 #define SPPCR_MOIFE             0x20    /* MOSI Idle Value Fixing Enable */
100 #define SPPCR_MOIFV             0x10    /* MOSI Idle Fixed Value */
101 #define SPPCR_SPOM              0x04
102 #define SPPCR_SPLP2             0x02    /* Loopback Mode 2 (non-inverting) */
103 #define SPPCR_SPLP              0x01    /* Loopback Mode (inverting) */
104 
105 #define SPPCR_IO3FV             0x04    /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
106 #define SPPCR_IO2FV             0x04    /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
107 
108 /* SPSR - Status Register */
109 #define SPSR_SPRF               0x80    /* Receive Buffer Full Flag */
110 #define SPSR_TEND               0x40    /* Transmit End */
111 #define SPSR_SPTEF              0x20    /* Transmit Buffer Empty Flag */
112 #define SPSR_PERF               0x08    /* Parity Error Flag */
113 #define SPSR_MODF               0x04    /* Mode Fault Error Flag */
114 #define SPSR_IDLNF              0x02    /* RSPI Idle Flag */
115 #define SPSR_OVRF               0x01    /* Overrun Error Flag (RSPI only) */
116 
117 /* SPSCR - Sequence Control Register */
118 #define SPSCR_SPSLN_MASK        0x07    /* Sequence Length Specification */
119 
120 /* SPSSR - Sequence Status Register */
121 #define SPSSR_SPECM_MASK        0x70    /* Command Error Mask */
122 #define SPSSR_SPCP_MASK         0x07    /* Command Pointer Mask */
123 
124 /* SPDCR - Data Control Register */
125 #define SPDCR_TXDMY             0x80    /* Dummy Data Transmission Enable */
126 #define SPDCR_SPLW1             0x40    /* Access Width Specification (RZ) */
127 #define SPDCR_SPLW0             0x20    /* Access Width Specification (RZ) */
128 #define SPDCR_SPLLWORD          (SPDCR_SPLW1 | SPDCR_SPLW0)
129 #define SPDCR_SPLWORD           SPDCR_SPLW1
130 #define SPDCR_SPLBYTE           SPDCR_SPLW0
131 #define SPDCR_SPLW              0x20    /* Access Width Specification (SH) */
132 #define SPDCR_SPRDTD            0x10    /* Receive Transmit Data Select (SH) */
133 #define SPDCR_SLSEL1            0x08
134 #define SPDCR_SLSEL0            0x04
135 #define SPDCR_SLSEL_MASK        0x0c    /* SSL1 Output Select (SH) */
136 #define SPDCR_SPFC1             0x02
137 #define SPDCR_SPFC0             0x01
138 #define SPDCR_SPFC_MASK         0x03    /* Frame Count Setting (1-4) (SH) */
139 
140 /* SPCKD - Clock Delay Register */
141 #define SPCKD_SCKDL_MASK        0x07    /* Clock Delay Setting (1-8) */
142 
143 /* SSLND - Slave Select Negation Delay Register */
144 #define SSLND_SLNDL_MASK        0x07    /* SSL Negation Delay Setting (1-8) */
145 
146 /* SPND - Next-Access Delay Register */
147 #define SPND_SPNDL_MASK         0x07    /* Next-Access Delay Setting (1-8) */
148 
149 /* SPCR2 - Control Register 2 */
150 #define SPCR2_PTE               0x08    /* Parity Self-Test Enable */
151 #define SPCR2_SPIE              0x04    /* Idle Interrupt Enable */
152 #define SPCR2_SPOE              0x02    /* Odd Parity Enable (vs. Even) */
153 #define SPCR2_SPPE              0x01    /* Parity Enable */
154 
155 /* SPCMDn - Command Registers */
156 #define SPCMD_SCKDEN            0x8000  /* Clock Delay Setting Enable */
157 #define SPCMD_SLNDEN            0x4000  /* SSL Negation Delay Setting Enable */
158 #define SPCMD_SPNDEN            0x2000  /* Next-Access Delay Enable */
159 #define SPCMD_LSBF              0x1000  /* LSB First */
160 #define SPCMD_SPB_MASK          0x0f00  /* Data Length Setting */
161 #define SPCMD_SPB_8_TO_16(bit)  (((bit - 1) << 8) & SPCMD_SPB_MASK)
162 #define SPCMD_SPB_8BIT          0x0000  /* QSPI only */
163 #define SPCMD_SPB_16BIT         0x0100
164 #define SPCMD_SPB_20BIT         0x0000
165 #define SPCMD_SPB_24BIT         0x0100
166 #define SPCMD_SPB_32BIT         0x0200
167 #define SPCMD_SSLKP             0x0080  /* SSL Signal Level Keeping */
168 #define SPCMD_SPIMOD_MASK       0x0060  /* SPI Operating Mode (QSPI only) */
169 #define SPCMD_SPIMOD1           0x0040
170 #define SPCMD_SPIMOD0           0x0020
171 #define SPCMD_SPIMOD_SINGLE     0
172 #define SPCMD_SPIMOD_DUAL       SPCMD_SPIMOD0
173 #define SPCMD_SPIMOD_QUAD       SPCMD_SPIMOD1
174 #define SPCMD_SPRW              0x0010  /* SPI Read/Write Access (Dual/Quad) */
175 #define SPCMD_SSLA_MASK         0x0030  /* SSL Assert Signal Setting (RSPI) */
176 #define SPCMD_BRDV_MASK         0x000c  /* Bit Rate Division Setting */
177 #define SPCMD_CPOL              0x0002  /* Clock Polarity Setting */
178 #define SPCMD_CPHA              0x0001  /* Clock Phase Setting */
179 
180 /* SPBFCR - Buffer Control Register */
181 #define SPBFCR_TXRST            0x80    /* Transmit Buffer Data Reset */
182 #define SPBFCR_RXRST            0x40    /* Receive Buffer Data Reset */
183 #define SPBFCR_TXTRG_MASK       0x30    /* Transmit Buffer Data Triggering Number */
184 #define SPBFCR_RXTRG_MASK       0x07    /* Receive Buffer Data Triggering Number */
185 
186 struct rspi_data {
187         void __iomem *addr;
188         u32 max_speed_hz;
189         struct spi_master *master;
190         wait_queue_head_t wait;
191         struct clk *clk;
192         u16 spcmd;
193         u8 spsr;
194         u8 sppcr;
195         int rx_irq, tx_irq;
196         const struct spi_ops *ops;
197 
198         unsigned dma_callbacked:1;
199         unsigned byte_access:1;
200 };
201 
202 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
203 {
204         iowrite8(data, rspi->addr + offset);
205 }
206 
207 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
208 {
209         iowrite16(data, rspi->addr + offset);
210 }
211 
212 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
213 {
214         iowrite32(data, rspi->addr + offset);
215 }
216 
217 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
218 {
219         return ioread8(rspi->addr + offset);
220 }
221 
222 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
223 {
224         return ioread16(rspi->addr + offset);
225 }
226 
227 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
228 {
229         if (rspi->byte_access)
230                 rspi_write8(rspi, data, RSPI_SPDR);
231         else /* 16 bit */
232                 rspi_write16(rspi, data, RSPI_SPDR);
233 }
234 
235 static u16 rspi_read_data(const struct rspi_data *rspi)
236 {
237         if (rspi->byte_access)
238                 return rspi_read8(rspi, RSPI_SPDR);
239         else /* 16 bit */
240                 return rspi_read16(rspi, RSPI_SPDR);
241 }
242 
243 /* optional functions */
244 struct spi_ops {
245         int (*set_config_register)(struct rspi_data *rspi, int access_size);
246         int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
247                             struct spi_transfer *xfer);
248         u16 mode_bits;
249         u16 flags;
250         u16 fifo_size;
251 };
252 
253 /*
254  * functions for RSPI on legacy SH
255  */
256 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
257 {
258         int spbr;
259 
260         /* Sets output mode, MOSI signal, and (optionally) loopback */
261         rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
262 
263         /* Sets transfer bit rate */
264         spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
265                             2 * rspi->max_speed_hz) - 1;
266         rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
267 
268         /* Disable dummy transmission, set 16-bit word access, 1 frame */
269         rspi_write8(rspi, 0, RSPI_SPDCR);
270         rspi->byte_access = 0;
271 
272         /* Sets RSPCK, SSL, next-access delay value */
273         rspi_write8(rspi, 0x00, RSPI_SPCKD);
274         rspi_write8(rspi, 0x00, RSPI_SSLND);
275         rspi_write8(rspi, 0x00, RSPI_SPND);
276 
277         /* Sets parity, interrupt mask */
278         rspi_write8(rspi, 0x00, RSPI_SPCR2);
279 
280         /* Sets SPCMD */
281         rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
282         rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
283 
284         /* Sets RSPI mode */
285         rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
286 
287         return 0;
288 }
289 
290 /*
291  * functions for RSPI on RZ
292  */
293 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
294 {
295         int spbr;
296 
297         /* Sets output mode, MOSI signal, and (optionally) loopback */
298         rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
299 
300         /* Sets transfer bit rate */
301         spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
302                             2 * rspi->max_speed_hz) - 1;
303         rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
304 
305         /* Disable dummy transmission, set byte access */
306         rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
307         rspi->byte_access = 1;
308 
309         /* Sets RSPCK, SSL, next-access delay value */
310         rspi_write8(rspi, 0x00, RSPI_SPCKD);
311         rspi_write8(rspi, 0x00, RSPI_SSLND);
312         rspi_write8(rspi, 0x00, RSPI_SPND);
313 
314         /* Sets SPCMD */
315         rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
316         rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
317 
318         /* Sets RSPI mode */
319         rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
320 
321         return 0;
322 }
323 
324 /*
325  * functions for QSPI
326  */
327 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
328 {
329         int spbr;
330 
331         /* Sets output mode, MOSI signal, and (optionally) loopback */
332         rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
333 
334         /* Sets transfer bit rate */
335         spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz);
336         rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
337 
338         /* Disable dummy transmission, set byte access */
339         rspi_write8(rspi, 0, RSPI_SPDCR);
340         rspi->byte_access = 1;
341 
342         /* Sets RSPCK, SSL, next-access delay value */
343         rspi_write8(rspi, 0x00, RSPI_SPCKD);
344         rspi_write8(rspi, 0x00, RSPI_SSLND);
345         rspi_write8(rspi, 0x00, RSPI_SPND);
346 
347         /* Data Length Setting */
348         if (access_size == 8)
349                 rspi->spcmd |= SPCMD_SPB_8BIT;
350         else if (access_size == 16)
351                 rspi->spcmd |= SPCMD_SPB_16BIT;
352         else
353                 rspi->spcmd |= SPCMD_SPB_32BIT;
354 
355         rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
356 
357         /* Resets transfer data length */
358         rspi_write32(rspi, 0, QSPI_SPBMUL0);
359 
360         /* Resets transmit and receive buffer */
361         rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
362         /* Sets buffer to allow normal operation */
363         rspi_write8(rspi, 0x00, QSPI_SPBFCR);
364 
365         /* Sets SPCMD */
366         rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
367 
368         /* Enables SPI function in master mode */
369         rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
370 
371         return 0;
372 }
373 
374 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
375 
376 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
377 {
378         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
379 }
380 
381 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
382 {
383         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
384 }
385 
386 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
387                                    u8 enable_bit)
388 {
389         int ret;
390 
391         rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
392         if (rspi->spsr & wait_mask)
393                 return 0;
394 
395         rspi_enable_irq(rspi, enable_bit);
396         ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
397         if (ret == 0 && !(rspi->spsr & wait_mask))
398                 return -ETIMEDOUT;
399 
400         return 0;
401 }
402 
403 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
404 {
405         return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
406 }
407 
408 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
409 {
410         return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
411 }
412 
413 static int rspi_data_out(struct rspi_data *rspi, u8 data)
414 {
415         int error = rspi_wait_for_tx_empty(rspi);
416         if (error < 0) {
417                 dev_err(&rspi->master->dev, "transmit timeout\n");
418                 return error;
419         }
420         rspi_write_data(rspi, data);
421         return 0;
422 }
423 
424 static int rspi_data_in(struct rspi_data *rspi)
425 {
426         int error;
427         u8 data;
428 
429         error = rspi_wait_for_rx_full(rspi);
430         if (error < 0) {
431                 dev_err(&rspi->master->dev, "receive timeout\n");
432                 return error;
433         }
434         data = rspi_read_data(rspi);
435         return data;
436 }
437 
438 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
439                              unsigned int n)
440 {
441         while (n-- > 0) {
442                 if (tx) {
443                         int ret = rspi_data_out(rspi, *tx++);
444                         if (ret < 0)
445                                 return ret;
446                 }
447                 if (rx) {
448                         int ret = rspi_data_in(rspi);
449                         if (ret < 0)
450                                 return ret;
451                         *rx++ = ret;
452                 }
453         }
454 
455         return 0;
456 }
457 
458 static void rspi_dma_complete(void *arg)
459 {
460         struct rspi_data *rspi = arg;
461 
462         rspi->dma_callbacked = 1;
463         wake_up_interruptible(&rspi->wait);
464 }
465 
466 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
467                              struct sg_table *rx)
468 {
469         struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
470         u8 irq_mask = 0;
471         unsigned int other_irq = 0;
472         dma_cookie_t cookie;
473         int ret;
474 
475         /* First prepare and submit the DMA request(s), as this may fail */
476         if (rx) {
477                 desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx,
478                                         rx->sgl, rx->nents, DMA_FROM_DEVICE,
479                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
480                 if (!desc_rx) {
481                         ret = -EAGAIN;
482                         goto no_dma_rx;
483                 }
484 
485                 desc_rx->callback = rspi_dma_complete;
486                 desc_rx->callback_param = rspi;
487                 cookie = dmaengine_submit(desc_rx);
488                 if (dma_submit_error(cookie)) {
489                         ret = cookie;
490                         goto no_dma_rx;
491                 }
492 
493                 irq_mask |= SPCR_SPRIE;
494         }
495 
496         if (tx) {
497                 desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx,
498                                         tx->sgl, tx->nents, DMA_TO_DEVICE,
499                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
500                 if (!desc_tx) {
501                         ret = -EAGAIN;
502                         goto no_dma_tx;
503                 }
504 
505                 if (rx) {
506                         /* No callback */
507                         desc_tx->callback = NULL;
508                 } else {
509                         desc_tx->callback = rspi_dma_complete;
510                         desc_tx->callback_param = rspi;
511                 }
512                 cookie = dmaengine_submit(desc_tx);
513                 if (dma_submit_error(cookie)) {
514                         ret = cookie;
515                         goto no_dma_tx;
516                 }
517 
518                 irq_mask |= SPCR_SPTIE;
519         }
520 
521         /*
522          * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be
523          * called. So, this driver disables the IRQ while DMA transfer.
524          */
525         if (tx)
526                 disable_irq(other_irq = rspi->tx_irq);
527         if (rx && rspi->rx_irq != other_irq)
528                 disable_irq(rspi->rx_irq);
529 
530         rspi_enable_irq(rspi, irq_mask);
531         rspi->dma_callbacked = 0;
532 
533         /* Now start DMA */
534         if (rx)
535                 dma_async_issue_pending(rspi->master->dma_rx);
536         if (tx)
537                 dma_async_issue_pending(rspi->master->dma_tx);
538 
539         ret = wait_event_interruptible_timeout(rspi->wait,
540                                                rspi->dma_callbacked, HZ);
541         if (ret > 0 && rspi->dma_callbacked)
542                 ret = 0;
543         else if (!ret) {
544                 dev_err(&rspi->master->dev, "DMA timeout\n");
545                 ret = -ETIMEDOUT;
546                 if (tx)
547                         dmaengine_terminate_all(rspi->master->dma_tx);
548                 if (rx)
549                         dmaengine_terminate_all(rspi->master->dma_rx);
550         }
551 
552         rspi_disable_irq(rspi, irq_mask);
553 
554         if (tx)
555                 enable_irq(rspi->tx_irq);
556         if (rx && rspi->rx_irq != other_irq)
557                 enable_irq(rspi->rx_irq);
558 
559         return ret;
560 
561 no_dma_tx:
562         if (rx)
563                 dmaengine_terminate_all(rspi->master->dma_rx);
564 no_dma_rx:
565         if (ret == -EAGAIN) {
566                 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
567                              dev_driver_string(&rspi->master->dev),
568                              dev_name(&rspi->master->dev));
569         }
570         return ret;
571 }
572 
573 static void rspi_receive_init(const struct rspi_data *rspi)
574 {
575         u8 spsr;
576 
577         spsr = rspi_read8(rspi, RSPI_SPSR);
578         if (spsr & SPSR_SPRF)
579                 rspi_read_data(rspi);   /* dummy read */
580         if (spsr & SPSR_OVRF)
581                 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
582                             RSPI_SPSR);
583 }
584 
585 static void rspi_rz_receive_init(const struct rspi_data *rspi)
586 {
587         rspi_receive_init(rspi);
588         rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
589         rspi_write8(rspi, 0, RSPI_SPBFCR);
590 }
591 
592 static void qspi_receive_init(const struct rspi_data *rspi)
593 {
594         u8 spsr;
595 
596         spsr = rspi_read8(rspi, RSPI_SPSR);
597         if (spsr & SPSR_SPRF)
598                 rspi_read_data(rspi);   /* dummy read */
599         rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
600         rspi_write8(rspi, 0, QSPI_SPBFCR);
601 }
602 
603 static bool __rspi_can_dma(const struct rspi_data *rspi,
604                            const struct spi_transfer *xfer)
605 {
606         return xfer->len > rspi->ops->fifo_size;
607 }
608 
609 static bool rspi_can_dma(struct spi_master *master, struct spi_device *spi,
610                          struct spi_transfer *xfer)
611 {
612         struct rspi_data *rspi = spi_master_get_devdata(master);
613 
614         return __rspi_can_dma(rspi, xfer);
615 }
616 
617 static int rspi_common_transfer(struct rspi_data *rspi,
618                                 struct spi_transfer *xfer)
619 {
620         int ret;
621 
622         if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
623                 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
624                 ret = rspi_dma_transfer(rspi, &xfer->tx_sg,
625                                         xfer->rx_buf ? &xfer->rx_sg : NULL);
626                 if (ret != -EAGAIN)
627                         return ret;
628         }
629 
630         ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
631         if (ret < 0)
632                 return ret;
633 
634         /* Wait for the last transmission */
635         rspi_wait_for_tx_empty(rspi);
636 
637         return 0;
638 }
639 
640 static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi,
641                              struct spi_transfer *xfer)
642 {
643         struct rspi_data *rspi = spi_master_get_devdata(master);
644         u8 spcr;
645 
646         spcr = rspi_read8(rspi, RSPI_SPCR);
647         if (xfer->rx_buf) {
648                 rspi_receive_init(rspi);
649                 spcr &= ~SPCR_TXMD;
650         } else {
651                 spcr |= SPCR_TXMD;
652         }
653         rspi_write8(rspi, spcr, RSPI_SPCR);
654 
655         return rspi_common_transfer(rspi, xfer);
656 }
657 
658 static int rspi_rz_transfer_one(struct spi_master *master,
659                                 struct spi_device *spi,
660                                 struct spi_transfer *xfer)
661 {
662         struct rspi_data *rspi = spi_master_get_devdata(master);
663 
664         rspi_rz_receive_init(rspi);
665 
666         return rspi_common_transfer(rspi, xfer);
667 }
668 
669 static int qspi_transfer_out_in(struct rspi_data *rspi,
670                                 struct spi_transfer *xfer)
671 {
672         qspi_receive_init(rspi);
673 
674         return rspi_common_transfer(rspi, xfer);
675 }
676 
677 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
678 {
679         int ret;
680 
681         if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
682                 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
683                 if (ret != -EAGAIN)
684                         return ret;
685         }
686 
687         ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len);
688         if (ret < 0)
689                 return ret;
690 
691         /* Wait for the last transmission */
692         rspi_wait_for_tx_empty(rspi);
693 
694         return 0;
695 }
696 
697 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
698 {
699         if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
700                 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
701                 if (ret != -EAGAIN)
702                         return ret;
703         }
704 
705         return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len);
706 }
707 
708 static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
709                              struct spi_transfer *xfer)
710 {
711         struct rspi_data *rspi = spi_master_get_devdata(master);
712 
713         if (spi->mode & SPI_LOOP) {
714                 return qspi_transfer_out_in(rspi, xfer);
715         } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
716                 /* Quad or Dual SPI Write */
717                 return qspi_transfer_out(rspi, xfer);
718         } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
719                 /* Quad or Dual SPI Read */
720                 return qspi_transfer_in(rspi, xfer);
721         } else {
722                 /* Single SPI Transfer */
723                 return qspi_transfer_out_in(rspi, xfer);
724         }
725 }
726 
727 static int rspi_setup(struct spi_device *spi)
728 {
729         struct rspi_data *rspi = spi_master_get_devdata(spi->master);
730 
731         rspi->max_speed_hz = spi->max_speed_hz;
732 
733         rspi->spcmd = SPCMD_SSLKP;
734         if (spi->mode & SPI_CPOL)
735                 rspi->spcmd |= SPCMD_CPOL;
736         if (spi->mode & SPI_CPHA)
737                 rspi->spcmd |= SPCMD_CPHA;
738 
739         /* CMOS output mode and MOSI signal from previous transfer */
740         rspi->sppcr = 0;
741         if (spi->mode & SPI_LOOP)
742                 rspi->sppcr |= SPPCR_SPLP;
743 
744         set_config_register(rspi, 8);
745 
746         return 0;
747 }
748 
749 static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
750 {
751         if (xfer->tx_buf)
752                 switch (xfer->tx_nbits) {
753                 case SPI_NBITS_QUAD:
754                         return SPCMD_SPIMOD_QUAD;
755                 case SPI_NBITS_DUAL:
756                         return SPCMD_SPIMOD_DUAL;
757                 default:
758                         return 0;
759                 }
760         if (xfer->rx_buf)
761                 switch (xfer->rx_nbits) {
762                 case SPI_NBITS_QUAD:
763                         return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
764                 case SPI_NBITS_DUAL:
765                         return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
766                 default:
767                         return 0;
768                 }
769 
770         return 0;
771 }
772 
773 static int qspi_setup_sequencer(struct rspi_data *rspi,
774                                 const struct spi_message *msg)
775 {
776         const struct spi_transfer *xfer;
777         unsigned int i = 0, len = 0;
778         u16 current_mode = 0xffff, mode;
779 
780         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
781                 mode = qspi_transfer_mode(xfer);
782                 if (mode == current_mode) {
783                         len += xfer->len;
784                         continue;
785                 }
786 
787                 /* Transfer mode change */
788                 if (i) {
789                         /* Set transfer data length of previous transfer */
790                         rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
791                 }
792 
793                 if (i >= QSPI_NUM_SPCMD) {
794                         dev_err(&msg->spi->dev,
795                                 "Too many different transfer modes");
796                         return -EINVAL;
797                 }
798 
799                 /* Program transfer mode for this transfer */
800                 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
801                 current_mode = mode;
802                 len = xfer->len;
803                 i++;
804         }
805         if (i) {
806                 /* Set final transfer data length and sequence length */
807                 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
808                 rspi_write8(rspi, i - 1, RSPI_SPSCR);
809         }
810 
811         return 0;
812 }
813 
814 static int rspi_prepare_message(struct spi_master *master,
815                                 struct spi_message *msg)
816 {
817         struct rspi_data *rspi = spi_master_get_devdata(master);
818         int ret;
819 
820         if (msg->spi->mode &
821             (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
822                 /* Setup sequencer for messages with multiple transfer modes */
823                 ret = qspi_setup_sequencer(rspi, msg);
824                 if (ret < 0)
825                         return ret;
826         }
827 
828         /* Enable SPI function in master mode */
829         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
830         return 0;
831 }
832 
833 static int rspi_unprepare_message(struct spi_master *master,
834                                   struct spi_message *msg)
835 {
836         struct rspi_data *rspi = spi_master_get_devdata(master);
837 
838         /* Disable SPI function */
839         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
840 
841         /* Reset sequencer for Single SPI Transfers */
842         rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
843         rspi_write8(rspi, 0, RSPI_SPSCR);
844         return 0;
845 }
846 
847 static irqreturn_t rspi_irq_mux(int irq, void *_sr)
848 {
849         struct rspi_data *rspi = _sr;
850         u8 spsr;
851         irqreturn_t ret = IRQ_NONE;
852         u8 disable_irq = 0;
853 
854         rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
855         if (spsr & SPSR_SPRF)
856                 disable_irq |= SPCR_SPRIE;
857         if (spsr & SPSR_SPTEF)
858                 disable_irq |= SPCR_SPTIE;
859 
860         if (disable_irq) {
861                 ret = IRQ_HANDLED;
862                 rspi_disable_irq(rspi, disable_irq);
863                 wake_up(&rspi->wait);
864         }
865 
866         return ret;
867 }
868 
869 static irqreturn_t rspi_irq_rx(int irq, void *_sr)
870 {
871         struct rspi_data *rspi = _sr;
872         u8 spsr;
873 
874         rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
875         if (spsr & SPSR_SPRF) {
876                 rspi_disable_irq(rspi, SPCR_SPRIE);
877                 wake_up(&rspi->wait);
878                 return IRQ_HANDLED;
879         }
880 
881         return 0;
882 }
883 
884 static irqreturn_t rspi_irq_tx(int irq, void *_sr)
885 {
886         struct rspi_data *rspi = _sr;
887         u8 spsr;
888 
889         rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
890         if (spsr & SPSR_SPTEF) {
891                 rspi_disable_irq(rspi, SPCR_SPTIE);
892                 wake_up(&rspi->wait);
893                 return IRQ_HANDLED;
894         }
895 
896         return 0;
897 }
898 
899 static struct dma_chan *rspi_request_dma_chan(struct device *dev,
900                                               enum dma_transfer_direction dir,
901                                               unsigned int id,
902                                               dma_addr_t port_addr)
903 {
904         dma_cap_mask_t mask;
905         struct dma_chan *chan;
906         struct dma_slave_config cfg;
907         int ret;
908 
909         dma_cap_zero(mask);
910         dma_cap_set(DMA_SLAVE, mask);
911 
912         chan = dma_request_channel(mask, shdma_chan_filter,
913                                    (void *)(unsigned long)id);
914         if (!chan) {
915                 dev_warn(dev, "dma_request_channel failed\n");
916                 return NULL;
917         }
918 
919         memset(&cfg, 0, sizeof(cfg));
920         cfg.slave_id = id;
921         cfg.direction = dir;
922         if (dir == DMA_MEM_TO_DEV)
923                 cfg.dst_addr = port_addr;
924         else
925                 cfg.src_addr = port_addr;
926 
927         ret = dmaengine_slave_config(chan, &cfg);
928         if (ret) {
929                 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
930                 dma_release_channel(chan);
931                 return NULL;
932         }
933 
934         return chan;
935 }
936 
937 static int rspi_request_dma(struct device *dev, struct spi_master *master,
938                             const struct resource *res)
939 {
940         const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
941 
942         if (!rspi_pd || !rspi_pd->dma_rx_id || !rspi_pd->dma_tx_id)
943                 return 0;       /* The driver assumes no error. */
944 
945         master->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM,
946                                                rspi_pd->dma_rx_id,
947                                                res->start + RSPI_SPDR);
948         if (!master->dma_rx)
949                 return -ENODEV;
950 
951         master->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV,
952                                                rspi_pd->dma_tx_id,
953                                                res->start + RSPI_SPDR);
954         if (!master->dma_tx) {
955                 dma_release_channel(master->dma_rx);
956                 master->dma_rx = NULL;
957                 return -ENODEV;
958         }
959 
960         master->can_dma = rspi_can_dma;
961         dev_info(dev, "DMA available");
962         return 0;
963 }
964 
965 static void rspi_release_dma(struct spi_master *master)
966 {
967         if (master->dma_tx)
968                 dma_release_channel(master->dma_tx);
969         if (master->dma_rx)
970                 dma_release_channel(master->dma_rx);
971 }
972 
973 static int rspi_remove(struct platform_device *pdev)
974 {
975         struct rspi_data *rspi = platform_get_drvdata(pdev);
976 
977         rspi_release_dma(rspi->master);
978         pm_runtime_disable(&pdev->dev);
979 
980         return 0;
981 }
982 
983 static const struct spi_ops rspi_ops = {
984         .set_config_register =  rspi_set_config_register,
985         .transfer_one =         rspi_transfer_one,
986         .mode_bits =            SPI_CPHA | SPI_CPOL | SPI_LOOP,
987         .flags =                SPI_MASTER_MUST_TX,
988         .fifo_size =            8,
989 };
990 
991 static const struct spi_ops rspi_rz_ops = {
992         .set_config_register =  rspi_rz_set_config_register,
993         .transfer_one =         rspi_rz_transfer_one,
994         .mode_bits =            SPI_CPHA | SPI_CPOL | SPI_LOOP,
995         .flags =                SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
996         .fifo_size =            8,      /* 8 for TX, 32 for RX */
997 };
998 
999 static const struct spi_ops qspi_ops = {
1000         .set_config_register =  qspi_set_config_register,
1001         .transfer_one =         qspi_transfer_one,
1002         .mode_bits =            SPI_CPHA | SPI_CPOL | SPI_LOOP |
1003                                 SPI_TX_DUAL | SPI_TX_QUAD |
1004                                 SPI_RX_DUAL | SPI_RX_QUAD,
1005         .flags =                SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1006         .fifo_size =            32,
1007 };
1008 
1009 #ifdef CONFIG_OF
1010 static const struct of_device_id rspi_of_match[] = {
1011         /* RSPI on legacy SH */
1012         { .compatible = "renesas,rspi", .data = &rspi_ops },
1013         /* RSPI on RZ/A1H */
1014         { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1015         /* QSPI on R-Car Gen2 */
1016         { .compatible = "renesas,qspi", .data = &qspi_ops },
1017         { /* sentinel */ }
1018 };
1019 
1020 MODULE_DEVICE_TABLE(of, rspi_of_match);
1021 
1022 static int rspi_parse_dt(struct device *dev, struct spi_master *master)
1023 {
1024         u32 num_cs;
1025         int error;
1026 
1027         /* Parse DT properties */
1028         error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1029         if (error) {
1030                 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1031                 return error;
1032         }
1033 
1034         master->num_chipselect = num_cs;
1035         return 0;
1036 }
1037 #else
1038 #define rspi_of_match   NULL
1039 static inline int rspi_parse_dt(struct device *dev, struct spi_master *master)
1040 {
1041         return -EINVAL;
1042 }
1043 #endif /* CONFIG_OF */
1044 
1045 static int rspi_request_irq(struct device *dev, unsigned int irq,
1046                             irq_handler_t handler, const char *suffix,
1047                             void *dev_id)
1048 {
1049         const char *base = dev_name(dev);
1050         size_t len = strlen(base) + strlen(suffix) + 2;
1051         char *name = devm_kzalloc(dev, len, GFP_KERNEL);
1052         if (!name)
1053                 return -ENOMEM;
1054         snprintf(name, len, "%s:%s", base, suffix);
1055         return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1056 }
1057 
1058 static int rspi_probe(struct platform_device *pdev)
1059 {
1060         struct resource *res;
1061         struct spi_master *master;
1062         struct rspi_data *rspi;
1063         int ret;
1064         const struct of_device_id *of_id;
1065         const struct rspi_plat_data *rspi_pd;
1066         const struct spi_ops *ops;
1067 
1068         master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1069         if (master == NULL) {
1070                 dev_err(&pdev->dev, "spi_alloc_master error.\n");
1071                 return -ENOMEM;
1072         }
1073 
1074         of_id = of_match_device(rspi_of_match, &pdev->dev);
1075         if (of_id) {
1076                 ops = of_id->data;
1077                 ret = rspi_parse_dt(&pdev->dev, master);
1078                 if (ret)
1079                         goto error1;
1080         } else {
1081                 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1082                 rspi_pd = dev_get_platdata(&pdev->dev);
1083                 if (rspi_pd && rspi_pd->num_chipselect)
1084                         master->num_chipselect = rspi_pd->num_chipselect;
1085                 else
1086                         master->num_chipselect = 2; /* default */
1087         };
1088 
1089         /* ops parameter check */
1090         if (!ops->set_config_register) {
1091                 dev_err(&pdev->dev, "there is no set_config_register\n");
1092                 ret = -ENODEV;
1093                 goto error1;
1094         }
1095 
1096         rspi = spi_master_get_devdata(master);
1097         platform_set_drvdata(pdev, rspi);
1098         rspi->ops = ops;
1099         rspi->master = master;
1100 
1101         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1102         rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1103         if (IS_ERR(rspi->addr)) {
1104                 ret = PTR_ERR(rspi->addr);
1105                 goto error1;
1106         }
1107 
1108         rspi->clk = devm_clk_get(&pdev->dev, NULL);
1109         if (IS_ERR(rspi->clk)) {
1110                 dev_err(&pdev->dev, "cannot get clock\n");
1111                 ret = PTR_ERR(rspi->clk);
1112                 goto error1;
1113         }
1114 
1115         pm_runtime_enable(&pdev->dev);
1116 
1117         init_waitqueue_head(&rspi->wait);
1118 
1119         master->bus_num = pdev->id;
1120         master->setup = rspi_setup;
1121         master->auto_runtime_pm = true;
1122         master->transfer_one = ops->transfer_one;
1123         master->prepare_message = rspi_prepare_message;
1124         master->unprepare_message = rspi_unprepare_message;
1125         master->mode_bits = ops->mode_bits;
1126         master->flags = ops->flags;
1127         master->dev.of_node = pdev->dev.of_node;
1128 
1129         ret = platform_get_irq_byname(pdev, "rx");
1130         if (ret < 0) {
1131                 ret = platform_get_irq_byname(pdev, "mux");
1132                 if (ret < 0)
1133                         ret = platform_get_irq(pdev, 0);
1134                 if (ret >= 0)
1135                         rspi->rx_irq = rspi->tx_irq = ret;
1136         } else {
1137                 rspi->rx_irq = ret;
1138                 ret = platform_get_irq_byname(pdev, "tx");
1139                 if (ret >= 0)
1140                         rspi->tx_irq = ret;
1141         }
1142         if (ret < 0) {
1143                 dev_err(&pdev->dev, "platform_get_irq error\n");
1144                 goto error2;
1145         }
1146 
1147         if (rspi->rx_irq == rspi->tx_irq) {
1148                 /* Single multiplexed interrupt */
1149                 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1150                                        "mux", rspi);
1151         } else {
1152                 /* Multi-interrupt mode, only SPRI and SPTI are used */
1153                 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1154                                        "rx", rspi);
1155                 if (!ret)
1156                         ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1157                                                rspi_irq_tx, "tx", rspi);
1158         }
1159         if (ret < 0) {
1160                 dev_err(&pdev->dev, "request_irq error\n");
1161                 goto error2;
1162         }
1163 
1164         ret = rspi_request_dma(&pdev->dev, master, res);
1165         if (ret < 0)
1166                 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1167 
1168         ret = devm_spi_register_master(&pdev->dev, master);
1169         if (ret < 0) {
1170                 dev_err(&pdev->dev, "spi_register_master error.\n");
1171                 goto error3;
1172         }
1173 
1174         dev_info(&pdev->dev, "probed\n");
1175 
1176         return 0;
1177 
1178 error3:
1179         rspi_release_dma(master);
1180 error2:
1181         pm_runtime_disable(&pdev->dev);
1182 error1:
1183         spi_master_put(master);
1184 
1185         return ret;
1186 }
1187 
1188 static struct platform_device_id spi_driver_ids[] = {
1189         { "rspi",       (kernel_ulong_t)&rspi_ops },
1190         { "rspi-rz",    (kernel_ulong_t)&rspi_rz_ops },
1191         { "qspi",       (kernel_ulong_t)&qspi_ops },
1192         {},
1193 };
1194 
1195 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1196 
1197 static struct platform_driver rspi_driver = {
1198         .probe =        rspi_probe,
1199         .remove =       rspi_remove,
1200         .id_table =     spi_driver_ids,
1201         .driver         = {
1202                 .name = "renesas_spi",
1203                 .owner  = THIS_MODULE,
1204                 .of_match_table = of_match_ptr(rspi_of_match),
1205         },
1206 };
1207 module_platform_driver(rspi_driver);
1208 
1209 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1210 MODULE_LICENSE("GPL v2");
1211 MODULE_AUTHOR("Yoshihiro Shimoda");
1212 MODULE_ALIAS("platform:rspi");
1213 

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