Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/spi/spi-rspi.c

  1 /*
  2  * SH RSPI driver
  3  *
  4  * Copyright (C) 2012, 2013  Renesas Solutions Corp.
  5  * Copyright (C) 2014 Glider bvba
  6  *
  7  * Based on spi-sh.c:
  8  * Copyright (C) 2011 Renesas Solutions Corp.
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License as published by
 12  * the Free Software Foundation; version 2 of the License.
 13  *
 14  * This program is distributed in the hope that it will be useful,
 15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17  * GNU General Public License for more details.
 18  *
 19  * You should have received a copy of the GNU General Public License
 20  * along with this program; if not, write to the Free Software
 21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 22  *
 23  */
 24 
 25 #include <linux/module.h>
 26 #include <linux/kernel.h>
 27 #include <linux/sched.h>
 28 #include <linux/errno.h>
 29 #include <linux/interrupt.h>
 30 #include <linux/platform_device.h>
 31 #include <linux/io.h>
 32 #include <linux/clk.h>
 33 #include <linux/dmaengine.h>
 34 #include <linux/dma-mapping.h>
 35 #include <linux/of_device.h>
 36 #include <linux/pm_runtime.h>
 37 #include <linux/sh_dma.h>
 38 #include <linux/spi/spi.h>
 39 #include <linux/spi/rspi.h>
 40 
 41 #define RSPI_SPCR               0x00    /* Control Register */
 42 #define RSPI_SSLP               0x01    /* Slave Select Polarity Register */
 43 #define RSPI_SPPCR              0x02    /* Pin Control Register */
 44 #define RSPI_SPSR               0x03    /* Status Register */
 45 #define RSPI_SPDR               0x04    /* Data Register */
 46 #define RSPI_SPSCR              0x08    /* Sequence Control Register */
 47 #define RSPI_SPSSR              0x09    /* Sequence Status Register */
 48 #define RSPI_SPBR               0x0a    /* Bit Rate Register */
 49 #define RSPI_SPDCR              0x0b    /* Data Control Register */
 50 #define RSPI_SPCKD              0x0c    /* Clock Delay Register */
 51 #define RSPI_SSLND              0x0d    /* Slave Select Negation Delay Register */
 52 #define RSPI_SPND               0x0e    /* Next-Access Delay Register */
 53 #define RSPI_SPCR2              0x0f    /* Control Register 2 (SH only) */
 54 #define RSPI_SPCMD0             0x10    /* Command Register 0 */
 55 #define RSPI_SPCMD1             0x12    /* Command Register 1 */
 56 #define RSPI_SPCMD2             0x14    /* Command Register 2 */
 57 #define RSPI_SPCMD3             0x16    /* Command Register 3 */
 58 #define RSPI_SPCMD4             0x18    /* Command Register 4 */
 59 #define RSPI_SPCMD5             0x1a    /* Command Register 5 */
 60 #define RSPI_SPCMD6             0x1c    /* Command Register 6 */
 61 #define RSPI_SPCMD7             0x1e    /* Command Register 7 */
 62 #define RSPI_SPCMD(i)           (RSPI_SPCMD0 + (i) * 2)
 63 #define RSPI_NUM_SPCMD          8
 64 #define RSPI_RZ_NUM_SPCMD       4
 65 #define QSPI_NUM_SPCMD          4
 66 
 67 /* RSPI on RZ only */
 68 #define RSPI_SPBFCR             0x20    /* Buffer Control Register */
 69 #define RSPI_SPBFDR             0x22    /* Buffer Data Count Setting Register */
 70 
 71 /* QSPI only */
 72 #define QSPI_SPBFCR             0x18    /* Buffer Control Register */
 73 #define QSPI_SPBDCR             0x1a    /* Buffer Data Count Register */
 74 #define QSPI_SPBMUL0            0x1c    /* Transfer Data Length Multiplier Setting Register 0 */
 75 #define QSPI_SPBMUL1            0x20    /* Transfer Data Length Multiplier Setting Register 1 */
 76 #define QSPI_SPBMUL2            0x24    /* Transfer Data Length Multiplier Setting Register 2 */
 77 #define QSPI_SPBMUL3            0x28    /* Transfer Data Length Multiplier Setting Register 3 */
 78 #define QSPI_SPBMUL(i)          (QSPI_SPBMUL0 + (i) * 4)
 79 
 80 /* SPCR - Control Register */
 81 #define SPCR_SPRIE              0x80    /* Receive Interrupt Enable */
 82 #define SPCR_SPE                0x40    /* Function Enable */
 83 #define SPCR_SPTIE              0x20    /* Transmit Interrupt Enable */
 84 #define SPCR_SPEIE              0x10    /* Error Interrupt Enable */
 85 #define SPCR_MSTR               0x08    /* Master/Slave Mode Select */
 86 #define SPCR_MODFEN             0x04    /* Mode Fault Error Detection Enable */
 87 /* RSPI on SH only */
 88 #define SPCR_TXMD               0x02    /* TX Only Mode (vs. Full Duplex) */
 89 #define SPCR_SPMS               0x01    /* 3-wire Mode (vs. 4-wire) */
 90 /* QSPI on R-Car M2 only */
 91 #define SPCR_WSWAP              0x02    /* Word Swap of read-data for DMAC */
 92 #define SPCR_BSWAP              0x01    /* Byte Swap of read-data for DMAC */
 93 
 94 /* SSLP - Slave Select Polarity Register */
 95 #define SSLP_SSL1P              0x02    /* SSL1 Signal Polarity Setting */
 96 #define SSLP_SSL0P              0x01    /* SSL0 Signal Polarity Setting */
 97 
 98 /* SPPCR - Pin Control Register */
 99 #define SPPCR_MOIFE             0x20    /* MOSI Idle Value Fixing Enable */
100 #define SPPCR_MOIFV             0x10    /* MOSI Idle Fixed Value */
101 #define SPPCR_SPOM              0x04
102 #define SPPCR_SPLP2             0x02    /* Loopback Mode 2 (non-inverting) */
103 #define SPPCR_SPLP              0x01    /* Loopback Mode (inverting) */
104 
105 #define SPPCR_IO3FV             0x04    /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
106 #define SPPCR_IO2FV             0x04    /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
107 
108 /* SPSR - Status Register */
109 #define SPSR_SPRF               0x80    /* Receive Buffer Full Flag */
110 #define SPSR_TEND               0x40    /* Transmit End */
111 #define SPSR_SPTEF              0x20    /* Transmit Buffer Empty Flag */
112 #define SPSR_PERF               0x08    /* Parity Error Flag */
113 #define SPSR_MODF               0x04    /* Mode Fault Error Flag */
114 #define SPSR_IDLNF              0x02    /* RSPI Idle Flag */
115 #define SPSR_OVRF               0x01    /* Overrun Error Flag (RSPI only) */
116 
117 /* SPSCR - Sequence Control Register */
118 #define SPSCR_SPSLN_MASK        0x07    /* Sequence Length Specification */
119 
120 /* SPSSR - Sequence Status Register */
121 #define SPSSR_SPECM_MASK        0x70    /* Command Error Mask */
122 #define SPSSR_SPCP_MASK         0x07    /* Command Pointer Mask */
123 
124 /* SPDCR - Data Control Register */
125 #define SPDCR_TXDMY             0x80    /* Dummy Data Transmission Enable */
126 #define SPDCR_SPLW1             0x40    /* Access Width Specification (RZ) */
127 #define SPDCR_SPLW0             0x20    /* Access Width Specification (RZ) */
128 #define SPDCR_SPLLWORD          (SPDCR_SPLW1 | SPDCR_SPLW0)
129 #define SPDCR_SPLWORD           SPDCR_SPLW1
130 #define SPDCR_SPLBYTE           SPDCR_SPLW0
131 #define SPDCR_SPLW              0x20    /* Access Width Specification (SH) */
132 #define SPDCR_SPRDTD            0x10    /* Receive Transmit Data Select (SH) */
133 #define SPDCR_SLSEL1            0x08
134 #define SPDCR_SLSEL0            0x04
135 #define SPDCR_SLSEL_MASK        0x0c    /* SSL1 Output Select (SH) */
136 #define SPDCR_SPFC1             0x02
137 #define SPDCR_SPFC0             0x01
138 #define SPDCR_SPFC_MASK         0x03    /* Frame Count Setting (1-4) (SH) */
139 
140 /* SPCKD - Clock Delay Register */
141 #define SPCKD_SCKDL_MASK        0x07    /* Clock Delay Setting (1-8) */
142 
143 /* SSLND - Slave Select Negation Delay Register */
144 #define SSLND_SLNDL_MASK        0x07    /* SSL Negation Delay Setting (1-8) */
145 
146 /* SPND - Next-Access Delay Register */
147 #define SPND_SPNDL_MASK         0x07    /* Next-Access Delay Setting (1-8) */
148 
149 /* SPCR2 - Control Register 2 */
150 #define SPCR2_PTE               0x08    /* Parity Self-Test Enable */
151 #define SPCR2_SPIE              0x04    /* Idle Interrupt Enable */
152 #define SPCR2_SPOE              0x02    /* Odd Parity Enable (vs. Even) */
153 #define SPCR2_SPPE              0x01    /* Parity Enable */
154 
155 /* SPCMDn - Command Registers */
156 #define SPCMD_SCKDEN            0x8000  /* Clock Delay Setting Enable */
157 #define SPCMD_SLNDEN            0x4000  /* SSL Negation Delay Setting Enable */
158 #define SPCMD_SPNDEN            0x2000  /* Next-Access Delay Enable */
159 #define SPCMD_LSBF              0x1000  /* LSB First */
160 #define SPCMD_SPB_MASK          0x0f00  /* Data Length Setting */
161 #define SPCMD_SPB_8_TO_16(bit)  (((bit - 1) << 8) & SPCMD_SPB_MASK)
162 #define SPCMD_SPB_8BIT          0x0000  /* QSPI only */
163 #define SPCMD_SPB_16BIT         0x0100
164 #define SPCMD_SPB_20BIT         0x0000
165 #define SPCMD_SPB_24BIT         0x0100
166 #define SPCMD_SPB_32BIT         0x0200
167 #define SPCMD_SSLKP             0x0080  /* SSL Signal Level Keeping */
168 #define SPCMD_SPIMOD_MASK       0x0060  /* SPI Operating Mode (QSPI only) */
169 #define SPCMD_SPIMOD1           0x0040
170 #define SPCMD_SPIMOD0           0x0020
171 #define SPCMD_SPIMOD_SINGLE     0
172 #define SPCMD_SPIMOD_DUAL       SPCMD_SPIMOD0
173 #define SPCMD_SPIMOD_QUAD       SPCMD_SPIMOD1
174 #define SPCMD_SPRW              0x0010  /* SPI Read/Write Access (Dual/Quad) */
175 #define SPCMD_SSLA_MASK         0x0030  /* SSL Assert Signal Setting (RSPI) */
176 #define SPCMD_BRDV_MASK         0x000c  /* Bit Rate Division Setting */
177 #define SPCMD_CPOL              0x0002  /* Clock Polarity Setting */
178 #define SPCMD_CPHA              0x0001  /* Clock Phase Setting */
179 
180 /* SPBFCR - Buffer Control Register */
181 #define SPBFCR_TXRST            0x80    /* Transmit Buffer Data Reset */
182 #define SPBFCR_RXRST            0x40    /* Receive Buffer Data Reset */
183 #define SPBFCR_TXTRG_MASK       0x30    /* Transmit Buffer Data Triggering Number */
184 #define SPBFCR_RXTRG_MASK       0x07    /* Receive Buffer Data Triggering Number */
185 
186 struct rspi_data {
187         void __iomem *addr;
188         u32 max_speed_hz;
189         struct spi_master *master;
190         wait_queue_head_t wait;
191         struct clk *clk;
192         u16 spcmd;
193         u8 spsr;
194         u8 sppcr;
195         int rx_irq, tx_irq;
196         const struct spi_ops *ops;
197 
198         unsigned dma_callbacked:1;
199         unsigned byte_access:1;
200 };
201 
202 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
203 {
204         iowrite8(data, rspi->addr + offset);
205 }
206 
207 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
208 {
209         iowrite16(data, rspi->addr + offset);
210 }
211 
212 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
213 {
214         iowrite32(data, rspi->addr + offset);
215 }
216 
217 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
218 {
219         return ioread8(rspi->addr + offset);
220 }
221 
222 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
223 {
224         return ioread16(rspi->addr + offset);
225 }
226 
227 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
228 {
229         if (rspi->byte_access)
230                 rspi_write8(rspi, data, RSPI_SPDR);
231         else /* 16 bit */
232                 rspi_write16(rspi, data, RSPI_SPDR);
233 }
234 
235 static u16 rspi_read_data(const struct rspi_data *rspi)
236 {
237         if (rspi->byte_access)
238                 return rspi_read8(rspi, RSPI_SPDR);
239         else /* 16 bit */
240                 return rspi_read16(rspi, RSPI_SPDR);
241 }
242 
243 /* optional functions */
244 struct spi_ops {
245         int (*set_config_register)(struct rspi_data *rspi, int access_size);
246         int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
247                             struct spi_transfer *xfer);
248         u16 mode_bits;
249         u16 flags;
250         u16 fifo_size;
251 };
252 
253 /*
254  * functions for RSPI on legacy SH
255  */
256 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
257 {
258         int spbr;
259 
260         /* Sets output mode, MOSI signal, and (optionally) loopback */
261         rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
262 
263         /* Sets transfer bit rate */
264         spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
265                             2 * rspi->max_speed_hz) - 1;
266         rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
267 
268         /* Disable dummy transmission, set 16-bit word access, 1 frame */
269         rspi_write8(rspi, 0, RSPI_SPDCR);
270         rspi->byte_access = 0;
271 
272         /* Sets RSPCK, SSL, next-access delay value */
273         rspi_write8(rspi, 0x00, RSPI_SPCKD);
274         rspi_write8(rspi, 0x00, RSPI_SSLND);
275         rspi_write8(rspi, 0x00, RSPI_SPND);
276 
277         /* Sets parity, interrupt mask */
278         rspi_write8(rspi, 0x00, RSPI_SPCR2);
279 
280         /* Sets SPCMD */
281         rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
282         rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
283 
284         /* Sets RSPI mode */
285         rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
286 
287         return 0;
288 }
289 
290 /*
291  * functions for RSPI on RZ
292  */
293 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
294 {
295         int spbr;
296 
297         /* Sets output mode, MOSI signal, and (optionally) loopback */
298         rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
299 
300         /* Sets transfer bit rate */
301         spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
302                             2 * rspi->max_speed_hz) - 1;
303         rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
304 
305         /* Disable dummy transmission, set byte access */
306         rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
307         rspi->byte_access = 1;
308 
309         /* Sets RSPCK, SSL, next-access delay value */
310         rspi_write8(rspi, 0x00, RSPI_SPCKD);
311         rspi_write8(rspi, 0x00, RSPI_SSLND);
312         rspi_write8(rspi, 0x00, RSPI_SPND);
313 
314         /* Sets SPCMD */
315         rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
316         rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
317 
318         /* Sets RSPI mode */
319         rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
320 
321         return 0;
322 }
323 
324 /*
325  * functions for QSPI
326  */
327 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
328 {
329         int spbr;
330 
331         /* Sets output mode, MOSI signal, and (optionally) loopback */
332         rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
333 
334         /* Sets transfer bit rate */
335         spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz);
336         rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
337 
338         /* Disable dummy transmission, set byte access */
339         rspi_write8(rspi, 0, RSPI_SPDCR);
340         rspi->byte_access = 1;
341 
342         /* Sets RSPCK, SSL, next-access delay value */
343         rspi_write8(rspi, 0x00, RSPI_SPCKD);
344         rspi_write8(rspi, 0x00, RSPI_SSLND);
345         rspi_write8(rspi, 0x00, RSPI_SPND);
346 
347         /* Data Length Setting */
348         if (access_size == 8)
349                 rspi->spcmd |= SPCMD_SPB_8BIT;
350         else if (access_size == 16)
351                 rspi->spcmd |= SPCMD_SPB_16BIT;
352         else
353                 rspi->spcmd |= SPCMD_SPB_32BIT;
354 
355         rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
356 
357         /* Resets transfer data length */
358         rspi_write32(rspi, 0, QSPI_SPBMUL0);
359 
360         /* Resets transmit and receive buffer */
361         rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
362         /* Sets buffer to allow normal operation */
363         rspi_write8(rspi, 0x00, QSPI_SPBFCR);
364 
365         /* Sets SPCMD */
366         rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
367 
368         /* Enables SPI function in master mode */
369         rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
370 
371         return 0;
372 }
373 
374 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
375 
376 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
377 {
378         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
379 }
380 
381 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
382 {
383         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
384 }
385 
386 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
387                                    u8 enable_bit)
388 {
389         int ret;
390 
391         rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
392         if (rspi->spsr & wait_mask)
393                 return 0;
394 
395         rspi_enable_irq(rspi, enable_bit);
396         ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
397         if (ret == 0 && !(rspi->spsr & wait_mask))
398                 return -ETIMEDOUT;
399 
400         return 0;
401 }
402 
403 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
404 {
405         return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
406 }
407 
408 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
409 {
410         return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
411 }
412 
413 static int rspi_data_out(struct rspi_data *rspi, u8 data)
414 {
415         int error = rspi_wait_for_tx_empty(rspi);
416         if (error < 0) {
417                 dev_err(&rspi->master->dev, "transmit timeout\n");
418                 return error;
419         }
420         rspi_write_data(rspi, data);
421         return 0;
422 }
423 
424 static int rspi_data_in(struct rspi_data *rspi)
425 {
426         int error;
427         u8 data;
428 
429         error = rspi_wait_for_rx_full(rspi);
430         if (error < 0) {
431                 dev_err(&rspi->master->dev, "receive timeout\n");
432                 return error;
433         }
434         data = rspi_read_data(rspi);
435         return data;
436 }
437 
438 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
439                              unsigned int n)
440 {
441         while (n-- > 0) {
442                 if (tx) {
443                         int ret = rspi_data_out(rspi, *tx++);
444                         if (ret < 0)
445                                 return ret;
446                 }
447                 if (rx) {
448                         int ret = rspi_data_in(rspi);
449                         if (ret < 0)
450                                 return ret;
451                         *rx++ = ret;
452                 }
453         }
454 
455         return 0;
456 }
457 
458 static void rspi_dma_complete(void *arg)
459 {
460         struct rspi_data *rspi = arg;
461 
462         rspi->dma_callbacked = 1;
463         wake_up_interruptible(&rspi->wait);
464 }
465 
466 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
467                              struct sg_table *rx)
468 {
469         struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
470         u8 irq_mask = 0;
471         unsigned int other_irq = 0;
472         dma_cookie_t cookie;
473         int ret;
474 
475         if (tx) {
476                 desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx,
477                                         tx->sgl, tx->nents, DMA_TO_DEVICE,
478                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
479                 if (!desc_tx)
480                         return -EIO;
481 
482                 irq_mask |= SPCR_SPTIE;
483         }
484         if (rx) {
485                 desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx,
486                                         rx->sgl, rx->nents, DMA_FROM_DEVICE,
487                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
488                 if (!desc_rx)
489                         return -EIO;
490 
491                 irq_mask |= SPCR_SPRIE;
492         }
493 
494         /*
495          * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be
496          * called. So, this driver disables the IRQ while DMA transfer.
497          */
498         if (tx)
499                 disable_irq(other_irq = rspi->tx_irq);
500         if (rx && rspi->rx_irq != other_irq)
501                 disable_irq(rspi->rx_irq);
502 
503         rspi_enable_irq(rspi, irq_mask);
504         rspi->dma_callbacked = 0;
505 
506         if (rx) {
507                 desc_rx->callback = rspi_dma_complete;
508                 desc_rx->callback_param = rspi;
509                 cookie = dmaengine_submit(desc_rx);
510                 if (dma_submit_error(cookie))
511                         return cookie;
512                 dma_async_issue_pending(rspi->master->dma_rx);
513         }
514         if (tx) {
515                 if (rx) {
516                         /* No callback */
517                         desc_tx->callback = NULL;
518                 } else {
519                         desc_tx->callback = rspi_dma_complete;
520                         desc_tx->callback_param = rspi;
521                 }
522                 cookie = dmaengine_submit(desc_tx);
523                 if (dma_submit_error(cookie))
524                         return cookie;
525                 dma_async_issue_pending(rspi->master->dma_tx);
526         }
527 
528         ret = wait_event_interruptible_timeout(rspi->wait,
529                                                rspi->dma_callbacked, HZ);
530         if (ret > 0 && rspi->dma_callbacked)
531                 ret = 0;
532         else if (!ret)
533                 ret = -ETIMEDOUT;
534 
535         rspi_disable_irq(rspi, irq_mask);
536 
537         if (tx)
538                 enable_irq(rspi->tx_irq);
539         if (rx && rspi->rx_irq != other_irq)
540                 enable_irq(rspi->rx_irq);
541 
542         return ret;
543 }
544 
545 static void rspi_receive_init(const struct rspi_data *rspi)
546 {
547         u8 spsr;
548 
549         spsr = rspi_read8(rspi, RSPI_SPSR);
550         if (spsr & SPSR_SPRF)
551                 rspi_read_data(rspi);   /* dummy read */
552         if (spsr & SPSR_OVRF)
553                 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
554                             RSPI_SPSR);
555 }
556 
557 static void rspi_rz_receive_init(const struct rspi_data *rspi)
558 {
559         rspi_receive_init(rspi);
560         rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
561         rspi_write8(rspi, 0, RSPI_SPBFCR);
562 }
563 
564 static void qspi_receive_init(const struct rspi_data *rspi)
565 {
566         u8 spsr;
567 
568         spsr = rspi_read8(rspi, RSPI_SPSR);
569         if (spsr & SPSR_SPRF)
570                 rspi_read_data(rspi);   /* dummy read */
571         rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
572         rspi_write8(rspi, 0, QSPI_SPBFCR);
573 }
574 
575 static bool __rspi_can_dma(const struct rspi_data *rspi,
576                            const struct spi_transfer *xfer)
577 {
578         return xfer->len > rspi->ops->fifo_size;
579 }
580 
581 static bool rspi_can_dma(struct spi_master *master, struct spi_device *spi,
582                          struct spi_transfer *xfer)
583 {
584         struct rspi_data *rspi = spi_master_get_devdata(master);
585 
586         return __rspi_can_dma(rspi, xfer);
587 }
588 
589 static int rspi_common_transfer(struct rspi_data *rspi,
590                                 struct spi_transfer *xfer)
591 {
592         int ret;
593 
594         if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
595                 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
596                 return rspi_dma_transfer(rspi, &xfer->tx_sg,
597                                          xfer->rx_buf ? &xfer->rx_sg : NULL);
598         }
599 
600         ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
601         if (ret < 0)
602                 return ret;
603 
604         /* Wait for the last transmission */
605         rspi_wait_for_tx_empty(rspi);
606 
607         return 0;
608 }
609 
610 static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi,
611                              struct spi_transfer *xfer)
612 {
613         struct rspi_data *rspi = spi_master_get_devdata(master);
614         u8 spcr;
615 
616         spcr = rspi_read8(rspi, RSPI_SPCR);
617         if (xfer->rx_buf) {
618                 rspi_receive_init(rspi);
619                 spcr &= ~SPCR_TXMD;
620         } else {
621                 spcr |= SPCR_TXMD;
622         }
623         rspi_write8(rspi, spcr, RSPI_SPCR);
624 
625         return rspi_common_transfer(rspi, xfer);
626 }
627 
628 static int rspi_rz_transfer_one(struct spi_master *master,
629                                 struct spi_device *spi,
630                                 struct spi_transfer *xfer)
631 {
632         struct rspi_data *rspi = spi_master_get_devdata(master);
633         int ret;
634 
635         rspi_rz_receive_init(rspi);
636 
637         return rspi_common_transfer(rspi, xfer);
638 }
639 
640 static int qspi_transfer_out_in(struct rspi_data *rspi,
641                                 struct spi_transfer *xfer)
642 {
643         qspi_receive_init(rspi);
644 
645         return rspi_common_transfer(rspi, xfer);
646 }
647 
648 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
649 {
650         int ret;
651 
652         if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer))
653                 return rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
654 
655         ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len);
656         if (ret < 0)
657                 return ret;
658 
659         /* Wait for the last transmission */
660         rspi_wait_for_tx_empty(rspi);
661 
662         return 0;
663 }
664 
665 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
666 {
667         if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer))
668                 return rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
669 
670         return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len);
671 }
672 
673 static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
674                              struct spi_transfer *xfer)
675 {
676         struct rspi_data *rspi = spi_master_get_devdata(master);
677 
678         if (spi->mode & SPI_LOOP) {
679                 return qspi_transfer_out_in(rspi, xfer);
680         } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
681                 /* Quad or Dual SPI Write */
682                 return qspi_transfer_out(rspi, xfer);
683         } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
684                 /* Quad or Dual SPI Read */
685                 return qspi_transfer_in(rspi, xfer);
686         } else {
687                 /* Single SPI Transfer */
688                 return qspi_transfer_out_in(rspi, xfer);
689         }
690 }
691 
692 static int rspi_setup(struct spi_device *spi)
693 {
694         struct rspi_data *rspi = spi_master_get_devdata(spi->master);
695 
696         rspi->max_speed_hz = spi->max_speed_hz;
697 
698         rspi->spcmd = SPCMD_SSLKP;
699         if (spi->mode & SPI_CPOL)
700                 rspi->spcmd |= SPCMD_CPOL;
701         if (spi->mode & SPI_CPHA)
702                 rspi->spcmd |= SPCMD_CPHA;
703 
704         /* CMOS output mode and MOSI signal from previous transfer */
705         rspi->sppcr = 0;
706         if (spi->mode & SPI_LOOP)
707                 rspi->sppcr |= SPPCR_SPLP;
708 
709         set_config_register(rspi, 8);
710 
711         return 0;
712 }
713 
714 static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
715 {
716         if (xfer->tx_buf)
717                 switch (xfer->tx_nbits) {
718                 case SPI_NBITS_QUAD:
719                         return SPCMD_SPIMOD_QUAD;
720                 case SPI_NBITS_DUAL:
721                         return SPCMD_SPIMOD_DUAL;
722                 default:
723                         return 0;
724                 }
725         if (xfer->rx_buf)
726                 switch (xfer->rx_nbits) {
727                 case SPI_NBITS_QUAD:
728                         return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
729                 case SPI_NBITS_DUAL:
730                         return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
731                 default:
732                         return 0;
733                 }
734 
735         return 0;
736 }
737 
738 static int qspi_setup_sequencer(struct rspi_data *rspi,
739                                 const struct spi_message *msg)
740 {
741         const struct spi_transfer *xfer;
742         unsigned int i = 0, len = 0;
743         u16 current_mode = 0xffff, mode;
744 
745         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
746                 mode = qspi_transfer_mode(xfer);
747                 if (mode == current_mode) {
748                         len += xfer->len;
749                         continue;
750                 }
751 
752                 /* Transfer mode change */
753                 if (i) {
754                         /* Set transfer data length of previous transfer */
755                         rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
756                 }
757 
758                 if (i >= QSPI_NUM_SPCMD) {
759                         dev_err(&msg->spi->dev,
760                                 "Too many different transfer modes");
761                         return -EINVAL;
762                 }
763 
764                 /* Program transfer mode for this transfer */
765                 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
766                 current_mode = mode;
767                 len = xfer->len;
768                 i++;
769         }
770         if (i) {
771                 /* Set final transfer data length and sequence length */
772                 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
773                 rspi_write8(rspi, i - 1, RSPI_SPSCR);
774         }
775 
776         return 0;
777 }
778 
779 static int rspi_prepare_message(struct spi_master *master,
780                                 struct spi_message *msg)
781 {
782         struct rspi_data *rspi = spi_master_get_devdata(master);
783         int ret;
784 
785         if (msg->spi->mode &
786             (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
787                 /* Setup sequencer for messages with multiple transfer modes */
788                 ret = qspi_setup_sequencer(rspi, msg);
789                 if (ret < 0)
790                         return ret;
791         }
792 
793         /* Enable SPI function in master mode */
794         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
795         return 0;
796 }
797 
798 static int rspi_unprepare_message(struct spi_master *master,
799                                   struct spi_message *msg)
800 {
801         struct rspi_data *rspi = spi_master_get_devdata(master);
802 
803         /* Disable SPI function */
804         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
805 
806         /* Reset sequencer for Single SPI Transfers */
807         rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
808         rspi_write8(rspi, 0, RSPI_SPSCR);
809         return 0;
810 }
811 
812 static irqreturn_t rspi_irq_mux(int irq, void *_sr)
813 {
814         struct rspi_data *rspi = _sr;
815         u8 spsr;
816         irqreturn_t ret = IRQ_NONE;
817         u8 disable_irq = 0;
818 
819         rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
820         if (spsr & SPSR_SPRF)
821                 disable_irq |= SPCR_SPRIE;
822         if (spsr & SPSR_SPTEF)
823                 disable_irq |= SPCR_SPTIE;
824 
825         if (disable_irq) {
826                 ret = IRQ_HANDLED;
827                 rspi_disable_irq(rspi, disable_irq);
828                 wake_up(&rspi->wait);
829         }
830 
831         return ret;
832 }
833 
834 static irqreturn_t rspi_irq_rx(int irq, void *_sr)
835 {
836         struct rspi_data *rspi = _sr;
837         u8 spsr;
838 
839         rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
840         if (spsr & SPSR_SPRF) {
841                 rspi_disable_irq(rspi, SPCR_SPRIE);
842                 wake_up(&rspi->wait);
843                 return IRQ_HANDLED;
844         }
845 
846         return 0;
847 }
848 
849 static irqreturn_t rspi_irq_tx(int irq, void *_sr)
850 {
851         struct rspi_data *rspi = _sr;
852         u8 spsr;
853 
854         rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
855         if (spsr & SPSR_SPTEF) {
856                 rspi_disable_irq(rspi, SPCR_SPTIE);
857                 wake_up(&rspi->wait);
858                 return IRQ_HANDLED;
859         }
860 
861         return 0;
862 }
863 
864 static struct dma_chan *rspi_request_dma_chan(struct device *dev,
865                                               enum dma_transfer_direction dir,
866                                               unsigned int id,
867                                               dma_addr_t port_addr)
868 {
869         dma_cap_mask_t mask;
870         struct dma_chan *chan;
871         struct dma_slave_config cfg;
872         int ret;
873 
874         dma_cap_zero(mask);
875         dma_cap_set(DMA_SLAVE, mask);
876 
877         chan = dma_request_channel(mask, shdma_chan_filter,
878                                    (void *)(unsigned long)id);
879         if (!chan) {
880                 dev_warn(dev, "dma_request_channel failed\n");
881                 return NULL;
882         }
883 
884         memset(&cfg, 0, sizeof(cfg));
885         cfg.slave_id = id;
886         cfg.direction = dir;
887         if (dir == DMA_MEM_TO_DEV)
888                 cfg.dst_addr = port_addr;
889         else
890                 cfg.src_addr = port_addr;
891 
892         ret = dmaengine_slave_config(chan, &cfg);
893         if (ret) {
894                 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
895                 dma_release_channel(chan);
896                 return NULL;
897         }
898 
899         return chan;
900 }
901 
902 static int rspi_request_dma(struct device *dev, struct spi_master *master,
903                             const struct resource *res)
904 {
905         const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
906 
907         if (!rspi_pd || !rspi_pd->dma_rx_id || !rspi_pd->dma_tx_id)
908                 return 0;       /* The driver assumes no error. */
909 
910         master->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM,
911                                                rspi_pd->dma_rx_id,
912                                                res->start + RSPI_SPDR);
913         if (!master->dma_rx)
914                 return -ENODEV;
915 
916         master->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV,
917                                                rspi_pd->dma_tx_id,
918                                                res->start + RSPI_SPDR);
919         if (!master->dma_tx) {
920                 dma_release_channel(master->dma_rx);
921                 master->dma_rx = NULL;
922                 return -ENODEV;
923         }
924 
925         master->can_dma = rspi_can_dma;
926         dev_info(dev, "DMA available");
927         return 0;
928 }
929 
930 static void rspi_release_dma(struct rspi_data *rspi)
931 {
932         if (rspi->master->dma_tx)
933                 dma_release_channel(rspi->master->dma_tx);
934         if (rspi->master->dma_rx)
935                 dma_release_channel(rspi->master->dma_rx);
936 }
937 
938 static int rspi_remove(struct platform_device *pdev)
939 {
940         struct rspi_data *rspi = platform_get_drvdata(pdev);
941 
942         rspi_release_dma(rspi);
943         pm_runtime_disable(&pdev->dev);
944 
945         return 0;
946 }
947 
948 static const struct spi_ops rspi_ops = {
949         .set_config_register =  rspi_set_config_register,
950         .transfer_one =         rspi_transfer_one,
951         .mode_bits =            SPI_CPHA | SPI_CPOL | SPI_LOOP,
952         .flags =                SPI_MASTER_MUST_TX,
953         .fifo_size =            8,
954 };
955 
956 static const struct spi_ops rspi_rz_ops = {
957         .set_config_register =  rspi_rz_set_config_register,
958         .transfer_one =         rspi_rz_transfer_one,
959         .mode_bits =            SPI_CPHA | SPI_CPOL | SPI_LOOP,
960         .flags =                SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
961         .fifo_size =            8,      /* 8 for TX, 32 for RX */
962 };
963 
964 static const struct spi_ops qspi_ops = {
965         .set_config_register =  qspi_set_config_register,
966         .transfer_one =         qspi_transfer_one,
967         .mode_bits =            SPI_CPHA | SPI_CPOL | SPI_LOOP |
968                                 SPI_TX_DUAL | SPI_TX_QUAD |
969                                 SPI_RX_DUAL | SPI_RX_QUAD,
970         .flags =                SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
971         .fifo_size =            32,
972 };
973 
974 #ifdef CONFIG_OF
975 static const struct of_device_id rspi_of_match[] = {
976         /* RSPI on legacy SH */
977         { .compatible = "renesas,rspi", .data = &rspi_ops },
978         /* RSPI on RZ/A1H */
979         { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
980         /* QSPI on R-Car Gen2 */
981         { .compatible = "renesas,qspi", .data = &qspi_ops },
982         { /* sentinel */ }
983 };
984 
985 MODULE_DEVICE_TABLE(of, rspi_of_match);
986 
987 static int rspi_parse_dt(struct device *dev, struct spi_master *master)
988 {
989         u32 num_cs;
990         int error;
991 
992         /* Parse DT properties */
993         error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
994         if (error) {
995                 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
996                 return error;
997         }
998 
999         master->num_chipselect = num_cs;
1000         return 0;
1001 }
1002 #else
1003 #define rspi_of_match   NULL
1004 static inline int rspi_parse_dt(struct device *dev, struct spi_master *master)
1005 {
1006         return -EINVAL;
1007 }
1008 #endif /* CONFIG_OF */
1009 
1010 static int rspi_request_irq(struct device *dev, unsigned int irq,
1011                             irq_handler_t handler, const char *suffix,
1012                             void *dev_id)
1013 {
1014         const char *base = dev_name(dev);
1015         size_t len = strlen(base) + strlen(suffix) + 2;
1016         char *name = devm_kzalloc(dev, len, GFP_KERNEL);
1017         if (!name)
1018                 return -ENOMEM;
1019         snprintf(name, len, "%s:%s", base, suffix);
1020         return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1021 }
1022 
1023 static int rspi_probe(struct platform_device *pdev)
1024 {
1025         struct resource *res;
1026         struct spi_master *master;
1027         struct rspi_data *rspi;
1028         int ret;
1029         const struct of_device_id *of_id;
1030         const struct rspi_plat_data *rspi_pd;
1031         const struct spi_ops *ops;
1032 
1033         master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1034         if (master == NULL) {
1035                 dev_err(&pdev->dev, "spi_alloc_master error.\n");
1036                 return -ENOMEM;
1037         }
1038 
1039         of_id = of_match_device(rspi_of_match, &pdev->dev);
1040         if (of_id) {
1041                 ops = of_id->data;
1042                 ret = rspi_parse_dt(&pdev->dev, master);
1043                 if (ret)
1044                         goto error1;
1045         } else {
1046                 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1047                 rspi_pd = dev_get_platdata(&pdev->dev);
1048                 if (rspi_pd && rspi_pd->num_chipselect)
1049                         master->num_chipselect = rspi_pd->num_chipselect;
1050                 else
1051                         master->num_chipselect = 2; /* default */
1052         };
1053 
1054         /* ops parameter check */
1055         if (!ops->set_config_register) {
1056                 dev_err(&pdev->dev, "there is no set_config_register\n");
1057                 ret = -ENODEV;
1058                 goto error1;
1059         }
1060 
1061         rspi = spi_master_get_devdata(master);
1062         platform_set_drvdata(pdev, rspi);
1063         rspi->ops = ops;
1064         rspi->master = master;
1065 
1066         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1067         rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1068         if (IS_ERR(rspi->addr)) {
1069                 ret = PTR_ERR(rspi->addr);
1070                 goto error1;
1071         }
1072 
1073         rspi->clk = devm_clk_get(&pdev->dev, NULL);
1074         if (IS_ERR(rspi->clk)) {
1075                 dev_err(&pdev->dev, "cannot get clock\n");
1076                 ret = PTR_ERR(rspi->clk);
1077                 goto error1;
1078         }
1079 
1080         pm_runtime_enable(&pdev->dev);
1081 
1082         init_waitqueue_head(&rspi->wait);
1083 
1084         master->bus_num = pdev->id;
1085         master->setup = rspi_setup;
1086         master->auto_runtime_pm = true;
1087         master->transfer_one = ops->transfer_one;
1088         master->prepare_message = rspi_prepare_message;
1089         master->unprepare_message = rspi_unprepare_message;
1090         master->mode_bits = ops->mode_bits;
1091         master->flags = ops->flags;
1092         master->dev.of_node = pdev->dev.of_node;
1093 
1094         ret = platform_get_irq_byname(pdev, "rx");
1095         if (ret < 0) {
1096                 ret = platform_get_irq_byname(pdev, "mux");
1097                 if (ret < 0)
1098                         ret = platform_get_irq(pdev, 0);
1099                 if (ret >= 0)
1100                         rspi->rx_irq = rspi->tx_irq = ret;
1101         } else {
1102                 rspi->rx_irq = ret;
1103                 ret = platform_get_irq_byname(pdev, "tx");
1104                 if (ret >= 0)
1105                         rspi->tx_irq = ret;
1106         }
1107         if (ret < 0) {
1108                 dev_err(&pdev->dev, "platform_get_irq error\n");
1109                 goto error2;
1110         }
1111 
1112         if (rspi->rx_irq == rspi->tx_irq) {
1113                 /* Single multiplexed interrupt */
1114                 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1115                                        "mux", rspi);
1116         } else {
1117                 /* Multi-interrupt mode, only SPRI and SPTI are used */
1118                 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1119                                        "rx", rspi);
1120                 if (!ret)
1121                         ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1122                                                rspi_irq_tx, "tx", rspi);
1123         }
1124         if (ret < 0) {
1125                 dev_err(&pdev->dev, "request_irq error\n");
1126                 goto error2;
1127         }
1128 
1129         ret = rspi_request_dma(&pdev->dev, master, res);
1130         if (ret < 0)
1131                 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1132 
1133         ret = devm_spi_register_master(&pdev->dev, master);
1134         if (ret < 0) {
1135                 dev_err(&pdev->dev, "spi_register_master error.\n");
1136                 goto error3;
1137         }
1138 
1139         dev_info(&pdev->dev, "probed\n");
1140 
1141         return 0;
1142 
1143 error3:
1144         rspi_release_dma(rspi);
1145 error2:
1146         pm_runtime_disable(&pdev->dev);
1147 error1:
1148         spi_master_put(master);
1149 
1150         return ret;
1151 }
1152 
1153 static struct platform_device_id spi_driver_ids[] = {
1154         { "rspi",       (kernel_ulong_t)&rspi_ops },
1155         { "rspi-rz",    (kernel_ulong_t)&rspi_rz_ops },
1156         { "qspi",       (kernel_ulong_t)&qspi_ops },
1157         {},
1158 };
1159 
1160 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1161 
1162 static struct platform_driver rspi_driver = {
1163         .probe =        rspi_probe,
1164         .remove =       rspi_remove,
1165         .id_table =     spi_driver_ids,
1166         .driver         = {
1167                 .name = "renesas_spi",
1168                 .owner  = THIS_MODULE,
1169                 .of_match_table = of_match_ptr(rspi_of_match),
1170         },
1171 };
1172 module_platform_driver(rspi_driver);
1173 
1174 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1175 MODULE_LICENSE("GPL v2");
1176 MODULE_AUTHOR("Yoshihiro Shimoda");
1177 MODULE_ALIAS("platform:rspi");
1178 

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