Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/spi/spi-pxa2xx.c

  1 /*
  2  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
  3  * Copyright (C) 2013, Intel Corporation
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License as published by
  7  * the Free Software Foundation; either version 2 of the License, or
  8  * (at your option) any later version.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  *
 15  * You should have received a copy of the GNU General Public License
 16  * along with this program; if not, write to the Free Software
 17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 18  */
 19 
 20 #include <linux/init.h>
 21 #include <linux/module.h>
 22 #include <linux/device.h>
 23 #include <linux/ioport.h>
 24 #include <linux/errno.h>
 25 #include <linux/err.h>
 26 #include <linux/interrupt.h>
 27 #include <linux/platform_device.h>
 28 #include <linux/spi/pxa2xx_spi.h>
 29 #include <linux/spi/spi.h>
 30 #include <linux/delay.h>
 31 #include <linux/gpio.h>
 32 #include <linux/slab.h>
 33 #include <linux/clk.h>
 34 #include <linux/pm_runtime.h>
 35 #include <linux/acpi.h>
 36 
 37 #include <asm/io.h>
 38 #include <asm/irq.h>
 39 #include <asm/delay.h>
 40 
 41 #include "spi-pxa2xx.h"
 42 
 43 MODULE_AUTHOR("Stephen Street");
 44 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
 45 MODULE_LICENSE("GPL");
 46 MODULE_ALIAS("platform:pxa2xx-spi");
 47 
 48 #define MAX_BUSES 3
 49 
 50 #define TIMOUT_DFLT             1000
 51 
 52 /*
 53  * for testing SSCR1 changes that require SSP restart, basically
 54  * everything except the service and interrupt enables, the pxa270 developer
 55  * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
 56  * list, but the PXA255 dev man says all bits without really meaning the
 57  * service and interrupt enables
 58  */
 59 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
 60                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
 61                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
 62                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
 63                                 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
 64                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
 65 
 66 #define LPSS_RX_THRESH_DFLT     64
 67 #define LPSS_TX_LOTHRESH_DFLT   160
 68 #define LPSS_TX_HITHRESH_DFLT   224
 69 
 70 /* Offset from drv_data->lpss_base */
 71 #define GENERAL_REG             0x08
 72 #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
 73 #define SSP_REG                 0x0c
 74 #define SPI_CS_CONTROL          0x18
 75 #define SPI_CS_CONTROL_SW_MODE  BIT(0)
 76 #define SPI_CS_CONTROL_CS_HIGH  BIT(1)
 77 
 78 static bool is_lpss_ssp(const struct driver_data *drv_data)
 79 {
 80         return drv_data->ssp_type == LPSS_SSP;
 81 }
 82 
 83 /*
 84  * Read and write LPSS SSP private registers. Caller must first check that
 85  * is_lpss_ssp() returns true before these can be called.
 86  */
 87 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
 88 {
 89         WARN_ON(!drv_data->lpss_base);
 90         return readl(drv_data->lpss_base + offset);
 91 }
 92 
 93 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
 94                                   unsigned offset, u32 value)
 95 {
 96         WARN_ON(!drv_data->lpss_base);
 97         writel(value, drv_data->lpss_base + offset);
 98 }
 99 
100 /*
101  * lpss_ssp_setup - perform LPSS SSP specific setup
102  * @drv_data: pointer to the driver private data
103  *
104  * Perform LPSS SSP specific setup. This function must be called first if
105  * one is going to use LPSS SSP private registers.
106  */
107 static void lpss_ssp_setup(struct driver_data *drv_data)
108 {
109         unsigned offset = 0x400;
110         u32 value, orig;
111 
112         if (!is_lpss_ssp(drv_data))
113                 return;
114 
115         /*
116          * Perform auto-detection of the LPSS SSP private registers. They
117          * can be either at 1k or 2k offset from the base address.
118          */
119         orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
120 
121         /* Test SPI_CS_CONTROL_SW_MODE bit enabling */
122         value = orig | SPI_CS_CONTROL_SW_MODE;
123         writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
124         value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
125         if (value != (orig | SPI_CS_CONTROL_SW_MODE)) {
126                 offset = 0x800;
127                 goto detection_done;
128         }
129 
130         orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
131 
132         /* Test SPI_CS_CONTROL_SW_MODE bit disabling */
133         value = orig & ~SPI_CS_CONTROL_SW_MODE;
134         writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
135         value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
136         if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) {
137                 offset = 0x800;
138                 goto detection_done;
139         }
140 
141 detection_done:
142         /* Now set the LPSS base */
143         drv_data->lpss_base = drv_data->ioaddr + offset;
144 
145         /* Enable software chip select control */
146         value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
147         __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
148 
149         /* Enable multiblock DMA transfers */
150         if (drv_data->master_info->enable_dma) {
151                 __lpss_ssp_write_priv(drv_data, SSP_REG, 1);
152 
153                 value = __lpss_ssp_read_priv(drv_data, GENERAL_REG);
154                 value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE;
155                 __lpss_ssp_write_priv(drv_data, GENERAL_REG, value);
156         }
157 }
158 
159 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
160 {
161         u32 value;
162 
163         if (!is_lpss_ssp(drv_data))
164                 return;
165 
166         value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL);
167         if (enable)
168                 value &= ~SPI_CS_CONTROL_CS_HIGH;
169         else
170                 value |= SPI_CS_CONTROL_CS_HIGH;
171         __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
172 }
173 
174 static void cs_assert(struct driver_data *drv_data)
175 {
176         struct chip_data *chip = drv_data->cur_chip;
177 
178         if (drv_data->ssp_type == CE4100_SSP) {
179                 write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
180                 return;
181         }
182 
183         if (chip->cs_control) {
184                 chip->cs_control(PXA2XX_CS_ASSERT);
185                 return;
186         }
187 
188         if (gpio_is_valid(chip->gpio_cs)) {
189                 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
190                 return;
191         }
192 
193         lpss_ssp_cs_control(drv_data, true);
194 }
195 
196 static void cs_deassert(struct driver_data *drv_data)
197 {
198         struct chip_data *chip = drv_data->cur_chip;
199 
200         if (drv_data->ssp_type == CE4100_SSP)
201                 return;
202 
203         if (chip->cs_control) {
204                 chip->cs_control(PXA2XX_CS_DEASSERT);
205                 return;
206         }
207 
208         if (gpio_is_valid(chip->gpio_cs)) {
209                 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
210                 return;
211         }
212 
213         lpss_ssp_cs_control(drv_data, false);
214 }
215 
216 int pxa2xx_spi_flush(struct driver_data *drv_data)
217 {
218         unsigned long limit = loops_per_jiffy << 1;
219 
220         void __iomem *reg = drv_data->ioaddr;
221 
222         do {
223                 while (read_SSSR(reg) & SSSR_RNE) {
224                         read_SSDR(reg);
225                 }
226         } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
227         write_SSSR_CS(drv_data, SSSR_ROR);
228 
229         return limit;
230 }
231 
232 static int null_writer(struct driver_data *drv_data)
233 {
234         void __iomem *reg = drv_data->ioaddr;
235         u8 n_bytes = drv_data->n_bytes;
236 
237         if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
238                 || (drv_data->tx == drv_data->tx_end))
239                 return 0;
240 
241         write_SSDR(0, reg);
242         drv_data->tx += n_bytes;
243 
244         return 1;
245 }
246 
247 static int null_reader(struct driver_data *drv_data)
248 {
249         void __iomem *reg = drv_data->ioaddr;
250         u8 n_bytes = drv_data->n_bytes;
251 
252         while ((read_SSSR(reg) & SSSR_RNE)
253                 && (drv_data->rx < drv_data->rx_end)) {
254                 read_SSDR(reg);
255                 drv_data->rx += n_bytes;
256         }
257 
258         return drv_data->rx == drv_data->rx_end;
259 }
260 
261 static int u8_writer(struct driver_data *drv_data)
262 {
263         void __iomem *reg = drv_data->ioaddr;
264 
265         if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
266                 || (drv_data->tx == drv_data->tx_end))
267                 return 0;
268 
269         write_SSDR(*(u8 *)(drv_data->tx), reg);
270         ++drv_data->tx;
271 
272         return 1;
273 }
274 
275 static int u8_reader(struct driver_data *drv_data)
276 {
277         void __iomem *reg = drv_data->ioaddr;
278 
279         while ((read_SSSR(reg) & SSSR_RNE)
280                 && (drv_data->rx < drv_data->rx_end)) {
281                 *(u8 *)(drv_data->rx) = read_SSDR(reg);
282                 ++drv_data->rx;
283         }
284 
285         return drv_data->rx == drv_data->rx_end;
286 }
287 
288 static int u16_writer(struct driver_data *drv_data)
289 {
290         void __iomem *reg = drv_data->ioaddr;
291 
292         if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
293                 || (drv_data->tx == drv_data->tx_end))
294                 return 0;
295 
296         write_SSDR(*(u16 *)(drv_data->tx), reg);
297         drv_data->tx += 2;
298 
299         return 1;
300 }
301 
302 static int u16_reader(struct driver_data *drv_data)
303 {
304         void __iomem *reg = drv_data->ioaddr;
305 
306         while ((read_SSSR(reg) & SSSR_RNE)
307                 && (drv_data->rx < drv_data->rx_end)) {
308                 *(u16 *)(drv_data->rx) = read_SSDR(reg);
309                 drv_data->rx += 2;
310         }
311 
312         return drv_data->rx == drv_data->rx_end;
313 }
314 
315 static int u32_writer(struct driver_data *drv_data)
316 {
317         void __iomem *reg = drv_data->ioaddr;
318 
319         if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
320                 || (drv_data->tx == drv_data->tx_end))
321                 return 0;
322 
323         write_SSDR(*(u32 *)(drv_data->tx), reg);
324         drv_data->tx += 4;
325 
326         return 1;
327 }
328 
329 static int u32_reader(struct driver_data *drv_data)
330 {
331         void __iomem *reg = drv_data->ioaddr;
332 
333         while ((read_SSSR(reg) & SSSR_RNE)
334                 && (drv_data->rx < drv_data->rx_end)) {
335                 *(u32 *)(drv_data->rx) = read_SSDR(reg);
336                 drv_data->rx += 4;
337         }
338 
339         return drv_data->rx == drv_data->rx_end;
340 }
341 
342 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
343 {
344         struct spi_message *msg = drv_data->cur_msg;
345         struct spi_transfer *trans = drv_data->cur_transfer;
346 
347         /* Move to next transfer */
348         if (trans->transfer_list.next != &msg->transfers) {
349                 drv_data->cur_transfer =
350                         list_entry(trans->transfer_list.next,
351                                         struct spi_transfer,
352                                         transfer_list);
353                 return RUNNING_STATE;
354         } else
355                 return DONE_STATE;
356 }
357 
358 /* caller already set message->status; dma and pio irqs are blocked */
359 static void giveback(struct driver_data *drv_data)
360 {
361         struct spi_transfer* last_transfer;
362         struct spi_message *msg;
363 
364         msg = drv_data->cur_msg;
365         drv_data->cur_msg = NULL;
366         drv_data->cur_transfer = NULL;
367 
368         last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
369                                         transfer_list);
370 
371         /* Delay if requested before any change in chip select */
372         if (last_transfer->delay_usecs)
373                 udelay(last_transfer->delay_usecs);
374 
375         /* Drop chip select UNLESS cs_change is true or we are returning
376          * a message with an error, or next message is for another chip
377          */
378         if (!last_transfer->cs_change)
379                 cs_deassert(drv_data);
380         else {
381                 struct spi_message *next_msg;
382 
383                 /* Holding of cs was hinted, but we need to make sure
384                  * the next message is for the same chip.  Don't waste
385                  * time with the following tests unless this was hinted.
386                  *
387                  * We cannot postpone this until pump_messages, because
388                  * after calling msg->complete (below) the driver that
389                  * sent the current message could be unloaded, which
390                  * could invalidate the cs_control() callback...
391                  */
392 
393                 /* get a pointer to the next message, if any */
394                 next_msg = spi_get_next_queued_message(drv_data->master);
395 
396                 /* see if the next and current messages point
397                  * to the same chip
398                  */
399                 if (next_msg && next_msg->spi != msg->spi)
400                         next_msg = NULL;
401                 if (!next_msg || msg->state == ERROR_STATE)
402                         cs_deassert(drv_data);
403         }
404 
405         spi_finalize_current_message(drv_data->master);
406         drv_data->cur_chip = NULL;
407 }
408 
409 static void reset_sccr1(struct driver_data *drv_data)
410 {
411         void __iomem *reg = drv_data->ioaddr;
412         struct chip_data *chip = drv_data->cur_chip;
413         u32 sccr1_reg;
414 
415         sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
416         sccr1_reg &= ~SSCR1_RFT;
417         sccr1_reg |= chip->threshold;
418         write_SSCR1(sccr1_reg, reg);
419 }
420 
421 static void int_error_stop(struct driver_data *drv_data, const char* msg)
422 {
423         void __iomem *reg = drv_data->ioaddr;
424 
425         /* Stop and reset SSP */
426         write_SSSR_CS(drv_data, drv_data->clear_sr);
427         reset_sccr1(drv_data);
428         if (!pxa25x_ssp_comp(drv_data))
429                 write_SSTO(0, reg);
430         pxa2xx_spi_flush(drv_data);
431         write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
432 
433         dev_err(&drv_data->pdev->dev, "%s\n", msg);
434 
435         drv_data->cur_msg->state = ERROR_STATE;
436         tasklet_schedule(&drv_data->pump_transfers);
437 }
438 
439 static void int_transfer_complete(struct driver_data *drv_data)
440 {
441         void __iomem *reg = drv_data->ioaddr;
442 
443         /* Stop SSP */
444         write_SSSR_CS(drv_data, drv_data->clear_sr);
445         reset_sccr1(drv_data);
446         if (!pxa25x_ssp_comp(drv_data))
447                 write_SSTO(0, reg);
448 
449         /* Update total byte transferred return count actual bytes read */
450         drv_data->cur_msg->actual_length += drv_data->len -
451                                 (drv_data->rx_end - drv_data->rx);
452 
453         /* Transfer delays and chip select release are
454          * handled in pump_transfers or giveback
455          */
456 
457         /* Move to next transfer */
458         drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
459 
460         /* Schedule transfer tasklet */
461         tasklet_schedule(&drv_data->pump_transfers);
462 }
463 
464 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
465 {
466         void __iomem *reg = drv_data->ioaddr;
467 
468         u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
469                         drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
470 
471         u32 irq_status = read_SSSR(reg) & irq_mask;
472 
473         if (irq_status & SSSR_ROR) {
474                 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
475                 return IRQ_HANDLED;
476         }
477 
478         if (irq_status & SSSR_TINT) {
479                 write_SSSR(SSSR_TINT, reg);
480                 if (drv_data->read(drv_data)) {
481                         int_transfer_complete(drv_data);
482                         return IRQ_HANDLED;
483                 }
484         }
485 
486         /* Drain rx fifo, Fill tx fifo and prevent overruns */
487         do {
488                 if (drv_data->read(drv_data)) {
489                         int_transfer_complete(drv_data);
490                         return IRQ_HANDLED;
491                 }
492         } while (drv_data->write(drv_data));
493 
494         if (drv_data->read(drv_data)) {
495                 int_transfer_complete(drv_data);
496                 return IRQ_HANDLED;
497         }
498 
499         if (drv_data->tx == drv_data->tx_end) {
500                 u32 bytes_left;
501                 u32 sccr1_reg;
502 
503                 sccr1_reg = read_SSCR1(reg);
504                 sccr1_reg &= ~SSCR1_TIE;
505 
506                 /*
507                  * PXA25x_SSP has no timeout, set up rx threshould for the
508                  * remaining RX bytes.
509                  */
510                 if (pxa25x_ssp_comp(drv_data)) {
511 
512                         sccr1_reg &= ~SSCR1_RFT;
513 
514                         bytes_left = drv_data->rx_end - drv_data->rx;
515                         switch (drv_data->n_bytes) {
516                         case 4:
517                                 bytes_left >>= 1;
518                         case 2:
519                                 bytes_left >>= 1;
520                         }
521 
522                         if (bytes_left > RX_THRESH_DFLT)
523                                 bytes_left = RX_THRESH_DFLT;
524 
525                         sccr1_reg |= SSCR1_RxTresh(bytes_left);
526                 }
527                 write_SSCR1(sccr1_reg, reg);
528         }
529 
530         /* We did something */
531         return IRQ_HANDLED;
532 }
533 
534 static irqreturn_t ssp_int(int irq, void *dev_id)
535 {
536         struct driver_data *drv_data = dev_id;
537         void __iomem *reg = drv_data->ioaddr;
538         u32 sccr1_reg;
539         u32 mask = drv_data->mask_sr;
540         u32 status;
541 
542         /*
543          * The IRQ might be shared with other peripherals so we must first
544          * check that are we RPM suspended or not. If we are we assume that
545          * the IRQ was not for us (we shouldn't be RPM suspended when the
546          * interrupt is enabled).
547          */
548         if (pm_runtime_suspended(&drv_data->pdev->dev))
549                 return IRQ_NONE;
550 
551         /*
552          * If the device is not yet in RPM suspended state and we get an
553          * interrupt that is meant for another device, check if status bits
554          * are all set to one. That means that the device is already
555          * powered off.
556          */
557         status = read_SSSR(reg);
558         if (status == ~0)
559                 return IRQ_NONE;
560 
561         sccr1_reg = read_SSCR1(reg);
562 
563         /* Ignore possible writes if we don't need to write */
564         if (!(sccr1_reg & SSCR1_TIE))
565                 mask &= ~SSSR_TFS;
566 
567         if (!(status & mask))
568                 return IRQ_NONE;
569 
570         if (!drv_data->cur_msg) {
571 
572                 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
573                 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
574                 if (!pxa25x_ssp_comp(drv_data))
575                         write_SSTO(0, reg);
576                 write_SSSR_CS(drv_data, drv_data->clear_sr);
577 
578                 dev_err(&drv_data->pdev->dev,
579                         "bad message state in interrupt handler\n");
580 
581                 /* Never fail */
582                 return IRQ_HANDLED;
583         }
584 
585         return drv_data->transfer_handler(drv_data);
586 }
587 
588 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
589 {
590         unsigned long ssp_clk = drv_data->max_clk_rate;
591         const struct ssp_device *ssp = drv_data->ssp;
592 
593         rate = min_t(int, ssp_clk, rate);
594 
595         if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
596                 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
597         else
598                 return ((ssp_clk / rate - 1) & 0xfff) << 8;
599 }
600 
601 static void pump_transfers(unsigned long data)
602 {
603         struct driver_data *drv_data = (struct driver_data *)data;
604         struct spi_message *message = NULL;
605         struct spi_transfer *transfer = NULL;
606         struct spi_transfer *previous = NULL;
607         struct chip_data *chip = NULL;
608         void __iomem *reg = drv_data->ioaddr;
609         u32 clk_div = 0;
610         u8 bits = 0;
611         u32 speed = 0;
612         u32 cr0;
613         u32 cr1;
614         u32 dma_thresh = drv_data->cur_chip->dma_threshold;
615         u32 dma_burst = drv_data->cur_chip->dma_burst_size;
616 
617         /* Get current state information */
618         message = drv_data->cur_msg;
619         transfer = drv_data->cur_transfer;
620         chip = drv_data->cur_chip;
621 
622         /* Handle for abort */
623         if (message->state == ERROR_STATE) {
624                 message->status = -EIO;
625                 giveback(drv_data);
626                 return;
627         }
628 
629         /* Handle end of message */
630         if (message->state == DONE_STATE) {
631                 message->status = 0;
632                 giveback(drv_data);
633                 return;
634         }
635 
636         /* Delay if requested at end of transfer before CS change */
637         if (message->state == RUNNING_STATE) {
638                 previous = list_entry(transfer->transfer_list.prev,
639                                         struct spi_transfer,
640                                         transfer_list);
641                 if (previous->delay_usecs)
642                         udelay(previous->delay_usecs);
643 
644                 /* Drop chip select only if cs_change is requested */
645                 if (previous->cs_change)
646                         cs_deassert(drv_data);
647         }
648 
649         /* Check if we can DMA this transfer */
650         if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
651 
652                 /* reject already-mapped transfers; PIO won't always work */
653                 if (message->is_dma_mapped
654                                 || transfer->rx_dma || transfer->tx_dma) {
655                         dev_err(&drv_data->pdev->dev,
656                                 "pump_transfers: mapped transfer length of "
657                                 "%u is greater than %d\n",
658                                 transfer->len, MAX_DMA_LEN);
659                         message->status = -EINVAL;
660                         giveback(drv_data);
661                         return;
662                 }
663 
664                 /* warn ... we force this to PIO mode */
665                 dev_warn_ratelimited(&message->spi->dev,
666                                      "pump_transfers: DMA disabled for transfer length %ld "
667                                      "greater than %d\n",
668                                      (long)drv_data->len, MAX_DMA_LEN);
669         }
670 
671         /* Setup the transfer state based on the type of transfer */
672         if (pxa2xx_spi_flush(drv_data) == 0) {
673                 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
674                 message->status = -EIO;
675                 giveback(drv_data);
676                 return;
677         }
678         drv_data->n_bytes = chip->n_bytes;
679         drv_data->tx = (void *)transfer->tx_buf;
680         drv_data->tx_end = drv_data->tx + transfer->len;
681         drv_data->rx = transfer->rx_buf;
682         drv_data->rx_end = drv_data->rx + transfer->len;
683         drv_data->rx_dma = transfer->rx_dma;
684         drv_data->tx_dma = transfer->tx_dma;
685         drv_data->len = transfer->len;
686         drv_data->write = drv_data->tx ? chip->write : null_writer;
687         drv_data->read = drv_data->rx ? chip->read : null_reader;
688 
689         /* Change speed and bit per word on a per transfer */
690         cr0 = chip->cr0;
691         if (transfer->speed_hz || transfer->bits_per_word) {
692 
693                 bits = chip->bits_per_word;
694                 speed = chip->speed_hz;
695 
696                 if (transfer->speed_hz)
697                         speed = transfer->speed_hz;
698 
699                 if (transfer->bits_per_word)
700                         bits = transfer->bits_per_word;
701 
702                 clk_div = ssp_get_clk_div(drv_data, speed);
703 
704                 if (bits <= 8) {
705                         drv_data->n_bytes = 1;
706                         drv_data->read = drv_data->read != null_reader ?
707                                                 u8_reader : null_reader;
708                         drv_data->write = drv_data->write != null_writer ?
709                                                 u8_writer : null_writer;
710                 } else if (bits <= 16) {
711                         drv_data->n_bytes = 2;
712                         drv_data->read = drv_data->read != null_reader ?
713                                                 u16_reader : null_reader;
714                         drv_data->write = drv_data->write != null_writer ?
715                                                 u16_writer : null_writer;
716                 } else if (bits <= 32) {
717                         drv_data->n_bytes = 4;
718                         drv_data->read = drv_data->read != null_reader ?
719                                                 u32_reader : null_reader;
720                         drv_data->write = drv_data->write != null_writer ?
721                                                 u32_writer : null_writer;
722                 }
723                 /* if bits/word is changed in dma mode, then must check the
724                  * thresholds and burst also */
725                 if (chip->enable_dma) {
726                         if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
727                                                         message->spi,
728                                                         bits, &dma_burst,
729                                                         &dma_thresh))
730                                 dev_warn_ratelimited(&message->spi->dev,
731                                                      "pump_transfers: DMA burst size reduced to match bits_per_word\n");
732                 }
733 
734                 cr0 = clk_div
735                         | SSCR0_Motorola
736                         | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
737                         | SSCR0_SSE
738                         | (bits > 16 ? SSCR0_EDSS : 0);
739         }
740 
741         message->state = RUNNING_STATE;
742 
743         drv_data->dma_mapped = 0;
744         if (pxa2xx_spi_dma_is_possible(drv_data->len))
745                 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
746         if (drv_data->dma_mapped) {
747 
748                 /* Ensure we have the correct interrupt handler */
749                 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
750 
751                 pxa2xx_spi_dma_prepare(drv_data, dma_burst);
752 
753                 /* Clear status and start DMA engine */
754                 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
755                 write_SSSR(drv_data->clear_sr, reg);
756 
757                 pxa2xx_spi_dma_start(drv_data);
758         } else {
759                 /* Ensure we have the correct interrupt handler */
760                 drv_data->transfer_handler = interrupt_transfer;
761 
762                 /* Clear status  */
763                 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
764                 write_SSSR_CS(drv_data, drv_data->clear_sr);
765         }
766 
767         if (is_lpss_ssp(drv_data)) {
768                 if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold)
769                         write_SSIRF(chip->lpss_rx_threshold, reg);
770                 if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold)
771                         write_SSITF(chip->lpss_tx_threshold, reg);
772         }
773 
774         /* see if we need to reload the config registers */
775         if ((read_SSCR0(reg) != cr0)
776                 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
777                         (cr1 & SSCR1_CHANGE_MASK)) {
778 
779                 /* stop the SSP, and update the other bits */
780                 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
781                 if (!pxa25x_ssp_comp(drv_data))
782                         write_SSTO(chip->timeout, reg);
783                 /* first set CR1 without interrupt and service enables */
784                 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
785                 /* restart the SSP */
786                 write_SSCR0(cr0, reg);
787 
788         } else {
789                 if (!pxa25x_ssp_comp(drv_data))
790                         write_SSTO(chip->timeout, reg);
791         }
792 
793         cs_assert(drv_data);
794 
795         /* after chip select, release the data by enabling service
796          * requests and interrupts, without changing any mode bits */
797         write_SSCR1(cr1, reg);
798 }
799 
800 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
801                                            struct spi_message *msg)
802 {
803         struct driver_data *drv_data = spi_master_get_devdata(master);
804 
805         drv_data->cur_msg = msg;
806         /* Initial message state*/
807         drv_data->cur_msg->state = START_STATE;
808         drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
809                                                 struct spi_transfer,
810                                                 transfer_list);
811 
812         /* prepare to setup the SSP, in pump_transfers, using the per
813          * chip configuration */
814         drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
815 
816         /* Mark as busy and launch transfers */
817         tasklet_schedule(&drv_data->pump_transfers);
818         return 0;
819 }
820 
821 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
822 {
823         struct driver_data *drv_data = spi_master_get_devdata(master);
824 
825         /* Disable the SSP now */
826         write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE,
827                     drv_data->ioaddr);
828 
829         return 0;
830 }
831 
832 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
833                     struct pxa2xx_spi_chip *chip_info)
834 {
835         int err = 0;
836 
837         if (chip == NULL || chip_info == NULL)
838                 return 0;
839 
840         /* NOTE: setup() can be called multiple times, possibly with
841          * different chip_info, release previously requested GPIO
842          */
843         if (gpio_is_valid(chip->gpio_cs))
844                 gpio_free(chip->gpio_cs);
845 
846         /* If (*cs_control) is provided, ignore GPIO chip select */
847         if (chip_info->cs_control) {
848                 chip->cs_control = chip_info->cs_control;
849                 return 0;
850         }
851 
852         if (gpio_is_valid(chip_info->gpio_cs)) {
853                 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
854                 if (err) {
855                         dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
856                                 chip_info->gpio_cs);
857                         return err;
858                 }
859 
860                 chip->gpio_cs = chip_info->gpio_cs;
861                 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
862 
863                 err = gpio_direction_output(chip->gpio_cs,
864                                         !chip->gpio_cs_inverted);
865         }
866 
867         return err;
868 }
869 
870 static int setup(struct spi_device *spi)
871 {
872         struct pxa2xx_spi_chip *chip_info = NULL;
873         struct chip_data *chip;
874         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
875         unsigned int clk_div;
876         uint tx_thres, tx_hi_thres, rx_thres;
877 
878         if (is_lpss_ssp(drv_data)) {
879                 tx_thres = LPSS_TX_LOTHRESH_DFLT;
880                 tx_hi_thres = LPSS_TX_HITHRESH_DFLT;
881                 rx_thres = LPSS_RX_THRESH_DFLT;
882         } else {
883                 tx_thres = TX_THRESH_DFLT;
884                 tx_hi_thres = 0;
885                 rx_thres = RX_THRESH_DFLT;
886         }
887 
888         /* Only alloc on first setup */
889         chip = spi_get_ctldata(spi);
890         if (!chip) {
891                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
892                 if (!chip)
893                         return -ENOMEM;
894 
895                 if (drv_data->ssp_type == CE4100_SSP) {
896                         if (spi->chip_select > 4) {
897                                 dev_err(&spi->dev,
898                                         "failed setup: cs number must not be > 4.\n");
899                                 kfree(chip);
900                                 return -EINVAL;
901                         }
902 
903                         chip->frm = spi->chip_select;
904                 } else
905                         chip->gpio_cs = -1;
906                 chip->enable_dma = 0;
907                 chip->timeout = TIMOUT_DFLT;
908         }
909 
910         /* protocol drivers may change the chip settings, so...
911          * if chip_info exists, use it */
912         chip_info = spi->controller_data;
913 
914         /* chip_info isn't always needed */
915         chip->cr1 = 0;
916         if (chip_info) {
917                 if (chip_info->timeout)
918                         chip->timeout = chip_info->timeout;
919                 if (chip_info->tx_threshold)
920                         tx_thres = chip_info->tx_threshold;
921                 if (chip_info->tx_hi_threshold)
922                         tx_hi_thres = chip_info->tx_hi_threshold;
923                 if (chip_info->rx_threshold)
924                         rx_thres = chip_info->rx_threshold;
925                 chip->enable_dma = drv_data->master_info->enable_dma;
926                 chip->dma_threshold = 0;
927                 if (chip_info->enable_loopback)
928                         chip->cr1 = SSCR1_LBM;
929         } else if (ACPI_HANDLE(&spi->dev)) {
930                 /*
931                  * Slave devices enumerated from ACPI namespace don't
932                  * usually have chip_info but we still might want to use
933                  * DMA with them.
934                  */
935                 chip->enable_dma = drv_data->master_info->enable_dma;
936         }
937 
938         chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
939                         (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
940 
941         chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
942         chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
943                                 | SSITF_TxHiThresh(tx_hi_thres);
944 
945         /* set dma burst and threshold outside of chip_info path so that if
946          * chip_info goes away after setting chip->enable_dma, the
947          * burst and threshold can still respond to changes in bits_per_word */
948         if (chip->enable_dma) {
949                 /* set up legal burst and threshold for dma */
950                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
951                                                 spi->bits_per_word,
952                                                 &chip->dma_burst_size,
953                                                 &chip->dma_threshold)) {
954                         dev_warn(&spi->dev,
955                                  "in setup: DMA burst size reduced to match bits_per_word\n");
956                 }
957         }
958 
959         clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz);
960         chip->speed_hz = spi->max_speed_hz;
961 
962         chip->cr0 = clk_div
963                         | SSCR0_Motorola
964                         | SSCR0_DataSize(spi->bits_per_word > 16 ?
965                                 spi->bits_per_word - 16 : spi->bits_per_word)
966                         | SSCR0_SSE
967                         | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
968         chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
969         chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
970                         | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
971 
972         if (spi->mode & SPI_LOOP)
973                 chip->cr1 |= SSCR1_LBM;
974 
975         /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
976         if (!pxa25x_ssp_comp(drv_data))
977                 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
978                         drv_data->max_clk_rate
979                                 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
980                         chip->enable_dma ? "DMA" : "PIO");
981         else
982                 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
983                         drv_data->max_clk_rate / 2
984                                 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
985                         chip->enable_dma ? "DMA" : "PIO");
986 
987         if (spi->bits_per_word <= 8) {
988                 chip->n_bytes = 1;
989                 chip->read = u8_reader;
990                 chip->write = u8_writer;
991         } else if (spi->bits_per_word <= 16) {
992                 chip->n_bytes = 2;
993                 chip->read = u16_reader;
994                 chip->write = u16_writer;
995         } else if (spi->bits_per_word <= 32) {
996                 chip->cr0 |= SSCR0_EDSS;
997                 chip->n_bytes = 4;
998                 chip->read = u32_reader;
999                 chip->write = u32_writer;
1000         }
1001         chip->bits_per_word = spi->bits_per_word;
1002 
1003         spi_set_ctldata(spi, chip);
1004 
1005         if (drv_data->ssp_type == CE4100_SSP)
1006                 return 0;
1007 
1008         return setup_cs(spi, chip, chip_info);
1009 }
1010 
1011 static void cleanup(struct spi_device *spi)
1012 {
1013         struct chip_data *chip = spi_get_ctldata(spi);
1014         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1015 
1016         if (!chip)
1017                 return;
1018 
1019         if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1020                 gpio_free(chip->gpio_cs);
1021 
1022         kfree(chip);
1023 }
1024 
1025 #ifdef CONFIG_ACPI
1026 static struct pxa2xx_spi_master *
1027 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1028 {
1029         struct pxa2xx_spi_master *pdata;
1030         struct acpi_device *adev;
1031         struct ssp_device *ssp;
1032         struct resource *res;
1033         int devid;
1034 
1035         if (!ACPI_HANDLE(&pdev->dev) ||
1036             acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
1037                 return NULL;
1038 
1039         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1040         if (!pdata)
1041                 return NULL;
1042 
1043         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1044         if (!res)
1045                 return NULL;
1046 
1047         ssp = &pdata->ssp;
1048 
1049         ssp->phys_base = res->start;
1050         ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1051         if (IS_ERR(ssp->mmio_base))
1052                 return NULL;
1053 
1054         ssp->clk = devm_clk_get(&pdev->dev, NULL);
1055         ssp->irq = platform_get_irq(pdev, 0);
1056         ssp->type = LPSS_SSP;
1057         ssp->pdev = pdev;
1058 
1059         ssp->port_id = -1;
1060         if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid))
1061                 ssp->port_id = devid;
1062 
1063         pdata->num_chipselect = 1;
1064         pdata->enable_dma = true;
1065         pdata->tx_chan_id = -1;
1066         pdata->rx_chan_id = -1;
1067 
1068         return pdata;
1069 }
1070 
1071 static struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1072         { "INT33C0", 0 },
1073         { "INT33C1", 0 },
1074         { "INT3430", 0 },
1075         { "INT3431", 0 },
1076         { "80860F0E", 0 },
1077         { },
1078 };
1079 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1080 #else
1081 static inline struct pxa2xx_spi_master *
1082 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1083 {
1084         return NULL;
1085 }
1086 #endif
1087 
1088 static int pxa2xx_spi_probe(struct platform_device *pdev)
1089 {
1090         struct device *dev = &pdev->dev;
1091         struct pxa2xx_spi_master *platform_info;
1092         struct spi_master *master;
1093         struct driver_data *drv_data;
1094         struct ssp_device *ssp;
1095         int status;
1096 
1097         platform_info = dev_get_platdata(dev);
1098         if (!platform_info) {
1099                 platform_info = pxa2xx_spi_acpi_get_pdata(pdev);
1100                 if (!platform_info) {
1101                         dev_err(&pdev->dev, "missing platform data\n");
1102                         return -ENODEV;
1103                 }
1104         }
1105 
1106         ssp = pxa_ssp_request(pdev->id, pdev->name);
1107         if (!ssp)
1108                 ssp = &platform_info->ssp;
1109 
1110         if (!ssp->mmio_base) {
1111                 dev_err(&pdev->dev, "failed to get ssp\n");
1112                 return -ENODEV;
1113         }
1114 
1115         /* Allocate master with space for drv_data and null dma buffer */
1116         master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1117         if (!master) {
1118                 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1119                 pxa_ssp_free(ssp);
1120                 return -ENOMEM;
1121         }
1122         drv_data = spi_master_get_devdata(master);
1123         drv_data->master = master;
1124         drv_data->master_info = platform_info;
1125         drv_data->pdev = pdev;
1126         drv_data->ssp = ssp;
1127 
1128         master->dev.parent = &pdev->dev;
1129         master->dev.of_node = pdev->dev.of_node;
1130         /* the spi->mode bits understood by this driver: */
1131         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1132 
1133         master->bus_num = ssp->port_id;
1134         master->num_chipselect = platform_info->num_chipselect;
1135         master->dma_alignment = DMA_ALIGNMENT;
1136         master->cleanup = cleanup;
1137         master->setup = setup;
1138         master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1139         master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1140         master->auto_runtime_pm = true;
1141 
1142         drv_data->ssp_type = ssp->type;
1143         drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT);
1144 
1145         drv_data->ioaddr = ssp->mmio_base;
1146         drv_data->ssdr_physical = ssp->phys_base + SSDR;
1147         if (pxa25x_ssp_comp(drv_data)) {
1148                 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1149                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1150                 drv_data->dma_cr1 = 0;
1151                 drv_data->clear_sr = SSSR_ROR;
1152                 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1153         } else {
1154                 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1155                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1156                 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1157                 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1158                 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1159         }
1160 
1161         status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1162                         drv_data);
1163         if (status < 0) {
1164                 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1165                 goto out_error_master_alloc;
1166         }
1167 
1168         /* Setup DMA if requested */
1169         drv_data->tx_channel = -1;
1170         drv_data->rx_channel = -1;
1171         if (platform_info->enable_dma) {
1172                 status = pxa2xx_spi_dma_setup(drv_data);
1173                 if (status) {
1174                         dev_dbg(dev, "no DMA channels available, using PIO\n");
1175                         platform_info->enable_dma = false;
1176                 }
1177         }
1178 
1179         /* Enable SOC clock */
1180         clk_prepare_enable(ssp->clk);
1181 
1182         drv_data->max_clk_rate = clk_get_rate(ssp->clk);
1183 
1184         /* Load default SSP configuration */
1185         write_SSCR0(0, drv_data->ioaddr);
1186         write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1187                                 SSCR1_TxTresh(TX_THRESH_DFLT),
1188                                 drv_data->ioaddr);
1189         write_SSCR0(SSCR0_SCR(2)
1190                         | SSCR0_Motorola
1191                         | SSCR0_DataSize(8),
1192                         drv_data->ioaddr);
1193         if (!pxa25x_ssp_comp(drv_data))
1194                 write_SSTO(0, drv_data->ioaddr);
1195         write_SSPSP(0, drv_data->ioaddr);
1196 
1197         lpss_ssp_setup(drv_data);
1198 
1199         tasklet_init(&drv_data->pump_transfers, pump_transfers,
1200                      (unsigned long)drv_data);
1201 
1202         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1203         pm_runtime_use_autosuspend(&pdev->dev);
1204         pm_runtime_set_active(&pdev->dev);
1205         pm_runtime_enable(&pdev->dev);
1206 
1207         /* Register with the SPI framework */
1208         platform_set_drvdata(pdev, drv_data);
1209         status = devm_spi_register_master(&pdev->dev, master);
1210         if (status != 0) {
1211                 dev_err(&pdev->dev, "problem registering spi master\n");
1212                 goto out_error_clock_enabled;
1213         }
1214 
1215         return status;
1216 
1217 out_error_clock_enabled:
1218         clk_disable_unprepare(ssp->clk);
1219         pxa2xx_spi_dma_release(drv_data);
1220         free_irq(ssp->irq, drv_data);
1221 
1222 out_error_master_alloc:
1223         spi_master_put(master);
1224         pxa_ssp_free(ssp);
1225         return status;
1226 }
1227 
1228 static int pxa2xx_spi_remove(struct platform_device *pdev)
1229 {
1230         struct driver_data *drv_data = platform_get_drvdata(pdev);
1231         struct ssp_device *ssp;
1232 
1233         if (!drv_data)
1234                 return 0;
1235         ssp = drv_data->ssp;
1236 
1237         pm_runtime_get_sync(&pdev->dev);
1238 
1239         /* Disable the SSP at the peripheral and SOC level */
1240         write_SSCR0(0, drv_data->ioaddr);
1241         clk_disable_unprepare(ssp->clk);
1242 
1243         /* Release DMA */
1244         if (drv_data->master_info->enable_dma)
1245                 pxa2xx_spi_dma_release(drv_data);
1246 
1247         pm_runtime_put_noidle(&pdev->dev);
1248         pm_runtime_disable(&pdev->dev);
1249 
1250         /* Release IRQ */
1251         free_irq(ssp->irq, drv_data);
1252 
1253         /* Release SSP */
1254         pxa_ssp_free(ssp);
1255 
1256         return 0;
1257 }
1258 
1259 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1260 {
1261         int status = 0;
1262 
1263         if ((status = pxa2xx_spi_remove(pdev)) != 0)
1264                 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1265 }
1266 
1267 #ifdef CONFIG_PM_SLEEP
1268 static int pxa2xx_spi_suspend(struct device *dev)
1269 {
1270         struct driver_data *drv_data = dev_get_drvdata(dev);
1271         struct ssp_device *ssp = drv_data->ssp;
1272         int status = 0;
1273 
1274         status = spi_master_suspend(drv_data->master);
1275         if (status != 0)
1276                 return status;
1277         write_SSCR0(0, drv_data->ioaddr);
1278         clk_disable_unprepare(ssp->clk);
1279 
1280         return 0;
1281 }
1282 
1283 static int pxa2xx_spi_resume(struct device *dev)
1284 {
1285         struct driver_data *drv_data = dev_get_drvdata(dev);
1286         struct ssp_device *ssp = drv_data->ssp;
1287         int status = 0;
1288 
1289         pxa2xx_spi_dma_resume(drv_data);
1290 
1291         /* Enable the SSP clock */
1292         clk_prepare_enable(ssp->clk);
1293 
1294         /* Restore LPSS private register bits */
1295         lpss_ssp_setup(drv_data);
1296 
1297         /* Start the queue running */
1298         status = spi_master_resume(drv_data->master);
1299         if (status != 0) {
1300                 dev_err(dev, "problem starting queue (%d)\n", status);
1301                 return status;
1302         }
1303 
1304         return 0;
1305 }
1306 #endif
1307 
1308 #ifdef CONFIG_PM_RUNTIME
1309 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1310 {
1311         struct driver_data *drv_data = dev_get_drvdata(dev);
1312 
1313         clk_disable_unprepare(drv_data->ssp->clk);
1314         return 0;
1315 }
1316 
1317 static int pxa2xx_spi_runtime_resume(struct device *dev)
1318 {
1319         struct driver_data *drv_data = dev_get_drvdata(dev);
1320 
1321         clk_prepare_enable(drv_data->ssp->clk);
1322         return 0;
1323 }
1324 #endif
1325 
1326 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1327         SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1328         SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1329                            pxa2xx_spi_runtime_resume, NULL)
1330 };
1331 
1332 static struct platform_driver driver = {
1333         .driver = {
1334                 .name   = "pxa2xx-spi",
1335                 .owner  = THIS_MODULE,
1336                 .pm     = &pxa2xx_spi_pm_ops,
1337                 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1338         },
1339         .probe = pxa2xx_spi_probe,
1340         .remove = pxa2xx_spi_remove,
1341         .shutdown = pxa2xx_spi_shutdown,
1342 };
1343 
1344 static int __init pxa2xx_spi_init(void)
1345 {
1346         return platform_driver_register(&driver);
1347 }
1348 subsys_initcall(pxa2xx_spi_init);
1349 
1350 static void __exit pxa2xx_spi_exit(void)
1351 {
1352         platform_driver_unregister(&driver);
1353 }
1354 module_exit(pxa2xx_spi_exit);
1355 

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