Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/spi/spi-pxa2xx.c

  1 /*
  2  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
  3  * Copyright (C) 2013, Intel Corporation
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License as published by
  7  * the Free Software Foundation; either version 2 of the License, or
  8  * (at your option) any later version.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  */
 15 
 16 #include <linux/init.h>
 17 #include <linux/module.h>
 18 #include <linux/device.h>
 19 #include <linux/ioport.h>
 20 #include <linux/errno.h>
 21 #include <linux/err.h>
 22 #include <linux/interrupt.h>
 23 #include <linux/platform_device.h>
 24 #include <linux/spi/pxa2xx_spi.h>
 25 #include <linux/spi/spi.h>
 26 #include <linux/delay.h>
 27 #include <linux/gpio.h>
 28 #include <linux/slab.h>
 29 #include <linux/clk.h>
 30 #include <linux/pm_runtime.h>
 31 #include <linux/acpi.h>
 32 
 33 #include <asm/io.h>
 34 #include <asm/irq.h>
 35 #include <asm/delay.h>
 36 
 37 #include "spi-pxa2xx.h"
 38 
 39 MODULE_AUTHOR("Stephen Street");
 40 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
 41 MODULE_LICENSE("GPL");
 42 MODULE_ALIAS("platform:pxa2xx-spi");
 43 
 44 #define TIMOUT_DFLT             1000
 45 
 46 /*
 47  * for testing SSCR1 changes that require SSP restart, basically
 48  * everything except the service and interrupt enables, the pxa270 developer
 49  * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
 50  * list, but the PXA255 dev man says all bits without really meaning the
 51  * service and interrupt enables
 52  */
 53 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
 54                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
 55                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
 56                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
 57                                 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
 58                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
 59 
 60 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF   \
 61                                 | QUARK_X1000_SSCR1_EFWR        \
 62                                 | QUARK_X1000_SSCR1_RFT         \
 63                                 | QUARK_X1000_SSCR1_TFT         \
 64                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
 65 
 66 #define LPSS_RX_THRESH_DFLT     64
 67 #define LPSS_TX_LOTHRESH_DFLT   160
 68 #define LPSS_TX_HITHRESH_DFLT   224
 69 
 70 struct quark_spi_rate {
 71         u32 bitrate;
 72         u32 dds_clk_rate;
 73         u32 clk_div;
 74 };
 75 
 76 /*
 77  * 'rate', 'dds', 'clk_div' lookup table, which is defined in
 78  * the Quark SPI datasheet.
 79  */
 80 static const struct quark_spi_rate quark_spi_rate_table[] = {
 81 /*      bitrate,        dds_clk_rate,   clk_div */
 82         {50000000,      0x800000,       0},
 83         {40000000,      0x666666,       0},
 84         {25000000,      0x400000,       0},
 85         {20000000,      0x666666,       1},
 86         {16667000,      0x800000,       2},
 87         {13333000,      0x666666,       2},
 88         {12500000,      0x200000,       0},
 89         {10000000,      0x800000,       4},
 90         {8000000,       0x666666,       4},
 91         {6250000,       0x400000,       3},
 92         {5000000,       0x400000,       4},
 93         {4000000,       0x666666,       9},
 94         {3125000,       0x80000,        0},
 95         {2500000,       0x400000,       9},
 96         {2000000,       0x666666,       19},
 97         {1563000,       0x40000,        0},
 98         {1250000,       0x200000,       9},
 99         {1000000,       0x400000,       24},
100         {800000,        0x666666,       49},
101         {781250,        0x20000,        0},
102         {625000,        0x200000,       19},
103         {500000,        0x400000,       49},
104         {400000,        0x666666,       99},
105         {390625,        0x10000,        0},
106         {250000,        0x400000,       99},
107         {200000,        0x666666,       199},
108         {195313,        0x8000,         0},
109         {125000,        0x100000,       49},
110         {100000,        0x200000,       124},
111         {50000,         0x100000,       124},
112         {25000,         0x80000,        124},
113         {10016,         0x20000,        77},
114         {5040,          0x20000,        154},
115         {1002,          0x8000,         194},
116 };
117 
118 /* Offset from drv_data->lpss_base */
119 #define GENERAL_REG             0x08
120 #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
121 #define SSP_REG                 0x0c
122 #define SPI_CS_CONTROL          0x18
123 #define SPI_CS_CONTROL_SW_MODE  BIT(0)
124 #define SPI_CS_CONTROL_CS_HIGH  BIT(1)
125 
126 static bool is_lpss_ssp(const struct driver_data *drv_data)
127 {
128         return drv_data->ssp_type == LPSS_SSP;
129 }
130 
131 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
132 {
133         return drv_data->ssp_type == QUARK_X1000_SSP;
134 }
135 
136 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
137 {
138         switch (drv_data->ssp_type) {
139         case QUARK_X1000_SSP:
140                 return QUARK_X1000_SSCR1_CHANGE_MASK;
141         default:
142                 return SSCR1_CHANGE_MASK;
143         }
144 }
145 
146 static u32
147 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
148 {
149         switch (drv_data->ssp_type) {
150         case QUARK_X1000_SSP:
151                 return RX_THRESH_QUARK_X1000_DFLT;
152         default:
153                 return RX_THRESH_DFLT;
154         }
155 }
156 
157 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
158 {
159         u32 mask;
160 
161         switch (drv_data->ssp_type) {
162         case QUARK_X1000_SSP:
163                 mask = QUARK_X1000_SSSR_TFL_MASK;
164                 break;
165         default:
166                 mask = SSSR_TFL_MASK;
167                 break;
168         }
169 
170         return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
171 }
172 
173 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
174                                      u32 *sccr1_reg)
175 {
176         u32 mask;
177 
178         switch (drv_data->ssp_type) {
179         case QUARK_X1000_SSP:
180                 mask = QUARK_X1000_SSCR1_RFT;
181                 break;
182         default:
183                 mask = SSCR1_RFT;
184                 break;
185         }
186         *sccr1_reg &= ~mask;
187 }
188 
189 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
190                                    u32 *sccr1_reg, u32 threshold)
191 {
192         switch (drv_data->ssp_type) {
193         case QUARK_X1000_SSP:
194                 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
195                 break;
196         default:
197                 *sccr1_reg |= SSCR1_RxTresh(threshold);
198                 break;
199         }
200 }
201 
202 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
203                                   u32 clk_div, u8 bits)
204 {
205         switch (drv_data->ssp_type) {
206         case QUARK_X1000_SSP:
207                 return clk_div
208                         | QUARK_X1000_SSCR0_Motorola
209                         | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
210                         | SSCR0_SSE;
211         default:
212                 return clk_div
213                         | SSCR0_Motorola
214                         | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
215                         | SSCR0_SSE
216                         | (bits > 16 ? SSCR0_EDSS : 0);
217         }
218 }
219 
220 /*
221  * Read and write LPSS SSP private registers. Caller must first check that
222  * is_lpss_ssp() returns true before these can be called.
223  */
224 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
225 {
226         WARN_ON(!drv_data->lpss_base);
227         return readl(drv_data->lpss_base + offset);
228 }
229 
230 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
231                                   unsigned offset, u32 value)
232 {
233         WARN_ON(!drv_data->lpss_base);
234         writel(value, drv_data->lpss_base + offset);
235 }
236 
237 /*
238  * lpss_ssp_setup - perform LPSS SSP specific setup
239  * @drv_data: pointer to the driver private data
240  *
241  * Perform LPSS SSP specific setup. This function must be called first if
242  * one is going to use LPSS SSP private registers.
243  */
244 static void lpss_ssp_setup(struct driver_data *drv_data)
245 {
246         unsigned offset = 0x400;
247         u32 value, orig;
248 
249         /*
250          * Perform auto-detection of the LPSS SSP private registers. They
251          * can be either at 1k or 2k offset from the base address.
252          */
253         orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
254 
255         /* Test SPI_CS_CONTROL_SW_MODE bit enabling */
256         value = orig | SPI_CS_CONTROL_SW_MODE;
257         writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
258         value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
259         if (value != (orig | SPI_CS_CONTROL_SW_MODE)) {
260                 offset = 0x800;
261                 goto detection_done;
262         }
263 
264         orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
265 
266         /* Test SPI_CS_CONTROL_SW_MODE bit disabling */
267         value = orig & ~SPI_CS_CONTROL_SW_MODE;
268         writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
269         value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
270         if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) {
271                 offset = 0x800;
272                 goto detection_done;
273         }
274 
275 detection_done:
276         /* Now set the LPSS base */
277         drv_data->lpss_base = drv_data->ioaddr + offset;
278 
279         /* Enable software chip select control */
280         value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
281         __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
282 
283         /* Enable multiblock DMA transfers */
284         if (drv_data->master_info->enable_dma) {
285                 __lpss_ssp_write_priv(drv_data, SSP_REG, 1);
286 
287                 value = __lpss_ssp_read_priv(drv_data, GENERAL_REG);
288                 value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE;
289                 __lpss_ssp_write_priv(drv_data, GENERAL_REG, value);
290         }
291 }
292 
293 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
294 {
295         u32 value;
296 
297         value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL);
298         if (enable)
299                 value &= ~SPI_CS_CONTROL_CS_HIGH;
300         else
301                 value |= SPI_CS_CONTROL_CS_HIGH;
302         __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
303 }
304 
305 static void cs_assert(struct driver_data *drv_data)
306 {
307         struct chip_data *chip = drv_data->cur_chip;
308 
309         if (drv_data->ssp_type == CE4100_SSP) {
310                 pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
311                 return;
312         }
313 
314         if (chip->cs_control) {
315                 chip->cs_control(PXA2XX_CS_ASSERT);
316                 return;
317         }
318 
319         if (gpio_is_valid(chip->gpio_cs)) {
320                 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
321                 return;
322         }
323 
324         if (is_lpss_ssp(drv_data))
325                 lpss_ssp_cs_control(drv_data, true);
326 }
327 
328 static void cs_deassert(struct driver_data *drv_data)
329 {
330         struct chip_data *chip = drv_data->cur_chip;
331 
332         if (drv_data->ssp_type == CE4100_SSP)
333                 return;
334 
335         if (chip->cs_control) {
336                 chip->cs_control(PXA2XX_CS_DEASSERT);
337                 return;
338         }
339 
340         if (gpio_is_valid(chip->gpio_cs)) {
341                 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
342                 return;
343         }
344 
345         if (is_lpss_ssp(drv_data))
346                 lpss_ssp_cs_control(drv_data, false);
347 }
348 
349 int pxa2xx_spi_flush(struct driver_data *drv_data)
350 {
351         unsigned long limit = loops_per_jiffy << 1;
352 
353         do {
354                 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
355                         pxa2xx_spi_read(drv_data, SSDR);
356         } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
357         write_SSSR_CS(drv_data, SSSR_ROR);
358 
359         return limit;
360 }
361 
362 static int null_writer(struct driver_data *drv_data)
363 {
364         u8 n_bytes = drv_data->n_bytes;
365 
366         if (pxa2xx_spi_txfifo_full(drv_data)
367                 || (drv_data->tx == drv_data->tx_end))
368                 return 0;
369 
370         pxa2xx_spi_write(drv_data, SSDR, 0);
371         drv_data->tx += n_bytes;
372 
373         return 1;
374 }
375 
376 static int null_reader(struct driver_data *drv_data)
377 {
378         u8 n_bytes = drv_data->n_bytes;
379 
380         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
381                && (drv_data->rx < drv_data->rx_end)) {
382                 pxa2xx_spi_read(drv_data, SSDR);
383                 drv_data->rx += n_bytes;
384         }
385 
386         return drv_data->rx == drv_data->rx_end;
387 }
388 
389 static int u8_writer(struct driver_data *drv_data)
390 {
391         if (pxa2xx_spi_txfifo_full(drv_data)
392                 || (drv_data->tx == drv_data->tx_end))
393                 return 0;
394 
395         pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
396         ++drv_data->tx;
397 
398         return 1;
399 }
400 
401 static int u8_reader(struct driver_data *drv_data)
402 {
403         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
404                && (drv_data->rx < drv_data->rx_end)) {
405                 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
406                 ++drv_data->rx;
407         }
408 
409         return drv_data->rx == drv_data->rx_end;
410 }
411 
412 static int u16_writer(struct driver_data *drv_data)
413 {
414         if (pxa2xx_spi_txfifo_full(drv_data)
415                 || (drv_data->tx == drv_data->tx_end))
416                 return 0;
417 
418         pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
419         drv_data->tx += 2;
420 
421         return 1;
422 }
423 
424 static int u16_reader(struct driver_data *drv_data)
425 {
426         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
427                && (drv_data->rx < drv_data->rx_end)) {
428                 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
429                 drv_data->rx += 2;
430         }
431 
432         return drv_data->rx == drv_data->rx_end;
433 }
434 
435 static int u32_writer(struct driver_data *drv_data)
436 {
437         if (pxa2xx_spi_txfifo_full(drv_data)
438                 || (drv_data->tx == drv_data->tx_end))
439                 return 0;
440 
441         pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
442         drv_data->tx += 4;
443 
444         return 1;
445 }
446 
447 static int u32_reader(struct driver_data *drv_data)
448 {
449         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
450                && (drv_data->rx < drv_data->rx_end)) {
451                 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
452                 drv_data->rx += 4;
453         }
454 
455         return drv_data->rx == drv_data->rx_end;
456 }
457 
458 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
459 {
460         struct spi_message *msg = drv_data->cur_msg;
461         struct spi_transfer *trans = drv_data->cur_transfer;
462 
463         /* Move to next transfer */
464         if (trans->transfer_list.next != &msg->transfers) {
465                 drv_data->cur_transfer =
466                         list_entry(trans->transfer_list.next,
467                                         struct spi_transfer,
468                                         transfer_list);
469                 return RUNNING_STATE;
470         } else
471                 return DONE_STATE;
472 }
473 
474 /* caller already set message->status; dma and pio irqs are blocked */
475 static void giveback(struct driver_data *drv_data)
476 {
477         struct spi_transfer* last_transfer;
478         struct spi_message *msg;
479 
480         msg = drv_data->cur_msg;
481         drv_data->cur_msg = NULL;
482         drv_data->cur_transfer = NULL;
483 
484         last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
485                                         transfer_list);
486 
487         /* Delay if requested before any change in chip select */
488         if (last_transfer->delay_usecs)
489                 udelay(last_transfer->delay_usecs);
490 
491         /* Drop chip select UNLESS cs_change is true or we are returning
492          * a message with an error, or next message is for another chip
493          */
494         if (!last_transfer->cs_change)
495                 cs_deassert(drv_data);
496         else {
497                 struct spi_message *next_msg;
498 
499                 /* Holding of cs was hinted, but we need to make sure
500                  * the next message is for the same chip.  Don't waste
501                  * time with the following tests unless this was hinted.
502                  *
503                  * We cannot postpone this until pump_messages, because
504                  * after calling msg->complete (below) the driver that
505                  * sent the current message could be unloaded, which
506                  * could invalidate the cs_control() callback...
507                  */
508 
509                 /* get a pointer to the next message, if any */
510                 next_msg = spi_get_next_queued_message(drv_data->master);
511 
512                 /* see if the next and current messages point
513                  * to the same chip
514                  */
515                 if (next_msg && next_msg->spi != msg->spi)
516                         next_msg = NULL;
517                 if (!next_msg || msg->state == ERROR_STATE)
518                         cs_deassert(drv_data);
519         }
520 
521         drv_data->cur_chip = NULL;
522         spi_finalize_current_message(drv_data->master);
523 }
524 
525 static void reset_sccr1(struct driver_data *drv_data)
526 {
527         struct chip_data *chip = drv_data->cur_chip;
528         u32 sccr1_reg;
529 
530         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
531         sccr1_reg &= ~SSCR1_RFT;
532         sccr1_reg |= chip->threshold;
533         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
534 }
535 
536 static void int_error_stop(struct driver_data *drv_data, const char* msg)
537 {
538         /* Stop and reset SSP */
539         write_SSSR_CS(drv_data, drv_data->clear_sr);
540         reset_sccr1(drv_data);
541         if (!pxa25x_ssp_comp(drv_data))
542                 pxa2xx_spi_write(drv_data, SSTO, 0);
543         pxa2xx_spi_flush(drv_data);
544         pxa2xx_spi_write(drv_data, SSCR0,
545                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
546 
547         dev_err(&drv_data->pdev->dev, "%s\n", msg);
548 
549         drv_data->cur_msg->state = ERROR_STATE;
550         tasklet_schedule(&drv_data->pump_transfers);
551 }
552 
553 static void int_transfer_complete(struct driver_data *drv_data)
554 {
555         /* Stop SSP */
556         write_SSSR_CS(drv_data, drv_data->clear_sr);
557         reset_sccr1(drv_data);
558         if (!pxa25x_ssp_comp(drv_data))
559                 pxa2xx_spi_write(drv_data, SSTO, 0);
560 
561         /* Update total byte transferred return count actual bytes read */
562         drv_data->cur_msg->actual_length += drv_data->len -
563                                 (drv_data->rx_end - drv_data->rx);
564 
565         /* Transfer delays and chip select release are
566          * handled in pump_transfers or giveback
567          */
568 
569         /* Move to next transfer */
570         drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
571 
572         /* Schedule transfer tasklet */
573         tasklet_schedule(&drv_data->pump_transfers);
574 }
575 
576 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
577 {
578         u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
579                        drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
580 
581         u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
582 
583         if (irq_status & SSSR_ROR) {
584                 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
585                 return IRQ_HANDLED;
586         }
587 
588         if (irq_status & SSSR_TINT) {
589                 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
590                 if (drv_data->read(drv_data)) {
591                         int_transfer_complete(drv_data);
592                         return IRQ_HANDLED;
593                 }
594         }
595 
596         /* Drain rx fifo, Fill tx fifo and prevent overruns */
597         do {
598                 if (drv_data->read(drv_data)) {
599                         int_transfer_complete(drv_data);
600                         return IRQ_HANDLED;
601                 }
602         } while (drv_data->write(drv_data));
603 
604         if (drv_data->read(drv_data)) {
605                 int_transfer_complete(drv_data);
606                 return IRQ_HANDLED;
607         }
608 
609         if (drv_data->tx == drv_data->tx_end) {
610                 u32 bytes_left;
611                 u32 sccr1_reg;
612 
613                 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
614                 sccr1_reg &= ~SSCR1_TIE;
615 
616                 /*
617                  * PXA25x_SSP has no timeout, set up rx threshould for the
618                  * remaining RX bytes.
619                  */
620                 if (pxa25x_ssp_comp(drv_data)) {
621                         u32 rx_thre;
622 
623                         pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
624 
625                         bytes_left = drv_data->rx_end - drv_data->rx;
626                         switch (drv_data->n_bytes) {
627                         case 4:
628                                 bytes_left >>= 1;
629                         case 2:
630                                 bytes_left >>= 1;
631                         }
632 
633                         rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
634                         if (rx_thre > bytes_left)
635                                 rx_thre = bytes_left;
636 
637                         pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
638                 }
639                 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
640         }
641 
642         /* We did something */
643         return IRQ_HANDLED;
644 }
645 
646 static irqreturn_t ssp_int(int irq, void *dev_id)
647 {
648         struct driver_data *drv_data = dev_id;
649         u32 sccr1_reg;
650         u32 mask = drv_data->mask_sr;
651         u32 status;
652 
653         /*
654          * The IRQ might be shared with other peripherals so we must first
655          * check that are we RPM suspended or not. If we are we assume that
656          * the IRQ was not for us (we shouldn't be RPM suspended when the
657          * interrupt is enabled).
658          */
659         if (pm_runtime_suspended(&drv_data->pdev->dev))
660                 return IRQ_NONE;
661 
662         /*
663          * If the device is not yet in RPM suspended state and we get an
664          * interrupt that is meant for another device, check if status bits
665          * are all set to one. That means that the device is already
666          * powered off.
667          */
668         status = pxa2xx_spi_read(drv_data, SSSR);
669         if (status == ~0)
670                 return IRQ_NONE;
671 
672         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
673 
674         /* Ignore possible writes if we don't need to write */
675         if (!(sccr1_reg & SSCR1_TIE))
676                 mask &= ~SSSR_TFS;
677 
678         if (!(status & mask))
679                 return IRQ_NONE;
680 
681         if (!drv_data->cur_msg) {
682 
683                 pxa2xx_spi_write(drv_data, SSCR0,
684                                  pxa2xx_spi_read(drv_data, SSCR0)
685                                  & ~SSCR0_SSE);
686                 pxa2xx_spi_write(drv_data, SSCR1,
687                                  pxa2xx_spi_read(drv_data, SSCR1)
688                                  & ~drv_data->int_cr1);
689                 if (!pxa25x_ssp_comp(drv_data))
690                         pxa2xx_spi_write(drv_data, SSTO, 0);
691                 write_SSSR_CS(drv_data, drv_data->clear_sr);
692 
693                 dev_err(&drv_data->pdev->dev,
694                         "bad message state in interrupt handler\n");
695 
696                 /* Never fail */
697                 return IRQ_HANDLED;
698         }
699 
700         return drv_data->transfer_handler(drv_data);
701 }
702 
703 /*
704  * The Quark SPI data sheet gives a table, and for the given 'rate',
705  * the 'dds' and 'clk_div' can be found in the table.
706  */
707 static u32 quark_x1000_set_clk_regvals(u32 rate, u32 *dds, u32 *clk_div)
708 {
709         unsigned int i;
710 
711         for (i = 0; i < ARRAY_SIZE(quark_spi_rate_table); i++) {
712                 if (rate >= quark_spi_rate_table[i].bitrate) {
713                         *dds = quark_spi_rate_table[i].dds_clk_rate;
714                         *clk_div = quark_spi_rate_table[i].clk_div;
715                         return quark_spi_rate_table[i].bitrate;
716                 }
717         }
718 
719         *dds = quark_spi_rate_table[i-1].dds_clk_rate;
720         *clk_div = quark_spi_rate_table[i-1].clk_div;
721 
722         return quark_spi_rate_table[i-1].bitrate;
723 }
724 
725 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
726 {
727         unsigned long ssp_clk = drv_data->max_clk_rate;
728         const struct ssp_device *ssp = drv_data->ssp;
729 
730         rate = min_t(int, ssp_clk, rate);
731 
732         if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
733                 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
734         else
735                 return ((ssp_clk / rate - 1) & 0xfff) << 8;
736 }
737 
738 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
739                                            struct chip_data *chip, int rate)
740 {
741         u32 clk_div;
742 
743         switch (drv_data->ssp_type) {
744         case QUARK_X1000_SSP:
745                 quark_x1000_set_clk_regvals(rate, &chip->dds_rate, &clk_div);
746                 return clk_div << 8;
747         default:
748                 return ssp_get_clk_div(drv_data, rate);
749         }
750 }
751 
752 static void pump_transfers(unsigned long data)
753 {
754         struct driver_data *drv_data = (struct driver_data *)data;
755         struct spi_message *message = NULL;
756         struct spi_transfer *transfer = NULL;
757         struct spi_transfer *previous = NULL;
758         struct chip_data *chip = NULL;
759         u32 clk_div = 0;
760         u8 bits = 0;
761         u32 speed = 0;
762         u32 cr0;
763         u32 cr1;
764         u32 dma_thresh = drv_data->cur_chip->dma_threshold;
765         u32 dma_burst = drv_data->cur_chip->dma_burst_size;
766         u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
767 
768         /* Get current state information */
769         message = drv_data->cur_msg;
770         transfer = drv_data->cur_transfer;
771         chip = drv_data->cur_chip;
772 
773         /* Handle for abort */
774         if (message->state == ERROR_STATE) {
775                 message->status = -EIO;
776                 giveback(drv_data);
777                 return;
778         }
779 
780         /* Handle end of message */
781         if (message->state == DONE_STATE) {
782                 message->status = 0;
783                 giveback(drv_data);
784                 return;
785         }
786 
787         /* Delay if requested at end of transfer before CS change */
788         if (message->state == RUNNING_STATE) {
789                 previous = list_entry(transfer->transfer_list.prev,
790                                         struct spi_transfer,
791                                         transfer_list);
792                 if (previous->delay_usecs)
793                         udelay(previous->delay_usecs);
794 
795                 /* Drop chip select only if cs_change is requested */
796                 if (previous->cs_change)
797                         cs_deassert(drv_data);
798         }
799 
800         /* Check if we can DMA this transfer */
801         if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
802 
803                 /* reject already-mapped transfers; PIO won't always work */
804                 if (message->is_dma_mapped
805                                 || transfer->rx_dma || transfer->tx_dma) {
806                         dev_err(&drv_data->pdev->dev,
807                                 "pump_transfers: mapped transfer length of "
808                                 "%u is greater than %d\n",
809                                 transfer->len, MAX_DMA_LEN);
810                         message->status = -EINVAL;
811                         giveback(drv_data);
812                         return;
813                 }
814 
815                 /* warn ... we force this to PIO mode */
816                 dev_warn_ratelimited(&message->spi->dev,
817                                      "pump_transfers: DMA disabled for transfer length %ld "
818                                      "greater than %d\n",
819                                      (long)drv_data->len, MAX_DMA_LEN);
820         }
821 
822         /* Setup the transfer state based on the type of transfer */
823         if (pxa2xx_spi_flush(drv_data) == 0) {
824                 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
825                 message->status = -EIO;
826                 giveback(drv_data);
827                 return;
828         }
829         drv_data->n_bytes = chip->n_bytes;
830         drv_data->tx = (void *)transfer->tx_buf;
831         drv_data->tx_end = drv_data->tx + transfer->len;
832         drv_data->rx = transfer->rx_buf;
833         drv_data->rx_end = drv_data->rx + transfer->len;
834         drv_data->rx_dma = transfer->rx_dma;
835         drv_data->tx_dma = transfer->tx_dma;
836         drv_data->len = transfer->len;
837         drv_data->write = drv_data->tx ? chip->write : null_writer;
838         drv_data->read = drv_data->rx ? chip->read : null_reader;
839 
840         /* Change speed and bit per word on a per transfer */
841         cr0 = chip->cr0;
842         if (transfer->speed_hz || transfer->bits_per_word) {
843 
844                 bits = chip->bits_per_word;
845                 speed = chip->speed_hz;
846 
847                 if (transfer->speed_hz)
848                         speed = transfer->speed_hz;
849 
850                 if (transfer->bits_per_word)
851                         bits = transfer->bits_per_word;
852 
853                 clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, speed);
854 
855                 if (bits <= 8) {
856                         drv_data->n_bytes = 1;
857                         drv_data->read = drv_data->read != null_reader ?
858                                                 u8_reader : null_reader;
859                         drv_data->write = drv_data->write != null_writer ?
860                                                 u8_writer : null_writer;
861                 } else if (bits <= 16) {
862                         drv_data->n_bytes = 2;
863                         drv_data->read = drv_data->read != null_reader ?
864                                                 u16_reader : null_reader;
865                         drv_data->write = drv_data->write != null_writer ?
866                                                 u16_writer : null_writer;
867                 } else if (bits <= 32) {
868                         drv_data->n_bytes = 4;
869                         drv_data->read = drv_data->read != null_reader ?
870                                                 u32_reader : null_reader;
871                         drv_data->write = drv_data->write != null_writer ?
872                                                 u32_writer : null_writer;
873                 }
874                 /* if bits/word is changed in dma mode, then must check the
875                  * thresholds and burst also */
876                 if (chip->enable_dma) {
877                         if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
878                                                         message->spi,
879                                                         bits, &dma_burst,
880                                                         &dma_thresh))
881                                 dev_warn_ratelimited(&message->spi->dev,
882                                                      "pump_transfers: DMA burst size reduced to match bits_per_word\n");
883                 }
884 
885                 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
886         }
887 
888         message->state = RUNNING_STATE;
889 
890         drv_data->dma_mapped = 0;
891         if (pxa2xx_spi_dma_is_possible(drv_data->len))
892                 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
893         if (drv_data->dma_mapped) {
894 
895                 /* Ensure we have the correct interrupt handler */
896                 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
897 
898                 pxa2xx_spi_dma_prepare(drv_data, dma_burst);
899 
900                 /* Clear status and start DMA engine */
901                 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
902                 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
903 
904                 pxa2xx_spi_dma_start(drv_data);
905         } else {
906                 /* Ensure we have the correct interrupt handler */
907                 drv_data->transfer_handler = interrupt_transfer;
908 
909                 /* Clear status  */
910                 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
911                 write_SSSR_CS(drv_data, drv_data->clear_sr);
912         }
913 
914         if (is_lpss_ssp(drv_data)) {
915                 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
916                     != chip->lpss_rx_threshold)
917                         pxa2xx_spi_write(drv_data, SSIRF,
918                                          chip->lpss_rx_threshold);
919                 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
920                     != chip->lpss_tx_threshold)
921                         pxa2xx_spi_write(drv_data, SSITF,
922                                          chip->lpss_tx_threshold);
923         }
924 
925         if (is_quark_x1000_ssp(drv_data) &&
926             (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
927                 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
928 
929         /* see if we need to reload the config registers */
930         if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
931             || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
932             != (cr1 & change_mask)) {
933                 /* stop the SSP, and update the other bits */
934                 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
935                 if (!pxa25x_ssp_comp(drv_data))
936                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
937                 /* first set CR1 without interrupt and service enables */
938                 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
939                 /* restart the SSP */
940                 pxa2xx_spi_write(drv_data, SSCR0, cr0);
941 
942         } else {
943                 if (!pxa25x_ssp_comp(drv_data))
944                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
945         }
946 
947         cs_assert(drv_data);
948 
949         /* after chip select, release the data by enabling service
950          * requests and interrupts, without changing any mode bits */
951         pxa2xx_spi_write(drv_data, SSCR1, cr1);
952 }
953 
954 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
955                                            struct spi_message *msg)
956 {
957         struct driver_data *drv_data = spi_master_get_devdata(master);
958 
959         drv_data->cur_msg = msg;
960         /* Initial message state*/
961         drv_data->cur_msg->state = START_STATE;
962         drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
963                                                 struct spi_transfer,
964                                                 transfer_list);
965 
966         /* prepare to setup the SSP, in pump_transfers, using the per
967          * chip configuration */
968         drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
969 
970         /* Mark as busy and launch transfers */
971         tasklet_schedule(&drv_data->pump_transfers);
972         return 0;
973 }
974 
975 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
976 {
977         struct driver_data *drv_data = spi_master_get_devdata(master);
978 
979         /* Disable the SSP now */
980         pxa2xx_spi_write(drv_data, SSCR0,
981                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
982 
983         return 0;
984 }
985 
986 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
987                     struct pxa2xx_spi_chip *chip_info)
988 {
989         int err = 0;
990 
991         if (chip == NULL || chip_info == NULL)
992                 return 0;
993 
994         /* NOTE: setup() can be called multiple times, possibly with
995          * different chip_info, release previously requested GPIO
996          */
997         if (gpio_is_valid(chip->gpio_cs))
998                 gpio_free(chip->gpio_cs);
999 
1000         /* If (*cs_control) is provided, ignore GPIO chip select */
1001         if (chip_info->cs_control) {
1002                 chip->cs_control = chip_info->cs_control;
1003                 return 0;
1004         }
1005 
1006         if (gpio_is_valid(chip_info->gpio_cs)) {
1007                 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1008                 if (err) {
1009                         dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1010                                 chip_info->gpio_cs);
1011                         return err;
1012                 }
1013 
1014                 chip->gpio_cs = chip_info->gpio_cs;
1015                 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1016 
1017                 err = gpio_direction_output(chip->gpio_cs,
1018                                         !chip->gpio_cs_inverted);
1019         }
1020 
1021         return err;
1022 }
1023 
1024 static int setup(struct spi_device *spi)
1025 {
1026         struct pxa2xx_spi_chip *chip_info = NULL;
1027         struct chip_data *chip;
1028         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1029         unsigned int clk_div;
1030         uint tx_thres, tx_hi_thres, rx_thres;
1031 
1032         switch (drv_data->ssp_type) {
1033         case QUARK_X1000_SSP:
1034                 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1035                 tx_hi_thres = 0;
1036                 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1037                 break;
1038         case LPSS_SSP:
1039                 tx_thres = LPSS_TX_LOTHRESH_DFLT;
1040                 tx_hi_thres = LPSS_TX_HITHRESH_DFLT;
1041                 rx_thres = LPSS_RX_THRESH_DFLT;
1042                 break;
1043         default:
1044                 tx_thres = TX_THRESH_DFLT;
1045                 tx_hi_thres = 0;
1046                 rx_thres = RX_THRESH_DFLT;
1047                 break;
1048         }
1049 
1050         /* Only alloc on first setup */
1051         chip = spi_get_ctldata(spi);
1052         if (!chip) {
1053                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1054                 if (!chip)
1055                         return -ENOMEM;
1056 
1057                 if (drv_data->ssp_type == CE4100_SSP) {
1058                         if (spi->chip_select > 4) {
1059                                 dev_err(&spi->dev,
1060                                         "failed setup: cs number must not be > 4.\n");
1061                                 kfree(chip);
1062                                 return -EINVAL;
1063                         }
1064 
1065                         chip->frm = spi->chip_select;
1066                 } else
1067                         chip->gpio_cs = -1;
1068                 chip->enable_dma = 0;
1069                 chip->timeout = TIMOUT_DFLT;
1070         }
1071 
1072         /* protocol drivers may change the chip settings, so...
1073          * if chip_info exists, use it */
1074         chip_info = spi->controller_data;
1075 
1076         /* chip_info isn't always needed */
1077         chip->cr1 = 0;
1078         if (chip_info) {
1079                 if (chip_info->timeout)
1080                         chip->timeout = chip_info->timeout;
1081                 if (chip_info->tx_threshold)
1082                         tx_thres = chip_info->tx_threshold;
1083                 if (chip_info->tx_hi_threshold)
1084                         tx_hi_thres = chip_info->tx_hi_threshold;
1085                 if (chip_info->rx_threshold)
1086                         rx_thres = chip_info->rx_threshold;
1087                 chip->enable_dma = drv_data->master_info->enable_dma;
1088                 chip->dma_threshold = 0;
1089                 if (chip_info->enable_loopback)
1090                         chip->cr1 = SSCR1_LBM;
1091         } else if (ACPI_HANDLE(&spi->dev)) {
1092                 /*
1093                  * Slave devices enumerated from ACPI namespace don't
1094                  * usually have chip_info but we still might want to use
1095                  * DMA with them.
1096                  */
1097                 chip->enable_dma = drv_data->master_info->enable_dma;
1098         }
1099 
1100         chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1101         chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1102                                 | SSITF_TxHiThresh(tx_hi_thres);
1103 
1104         /* set dma burst and threshold outside of chip_info path so that if
1105          * chip_info goes away after setting chip->enable_dma, the
1106          * burst and threshold can still respond to changes in bits_per_word */
1107         if (chip->enable_dma) {
1108                 /* set up legal burst and threshold for dma */
1109                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1110                                                 spi->bits_per_word,
1111                                                 &chip->dma_burst_size,
1112                                                 &chip->dma_threshold)) {
1113                         dev_warn(&spi->dev,
1114                                  "in setup: DMA burst size reduced to match bits_per_word\n");
1115                 }
1116         }
1117 
1118         clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, spi->max_speed_hz);
1119         chip->speed_hz = spi->max_speed_hz;
1120 
1121         chip->cr0 = pxa2xx_configure_sscr0(drv_data, clk_div,
1122                                            spi->bits_per_word);
1123         switch (drv_data->ssp_type) {
1124         case QUARK_X1000_SSP:
1125                 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1126                                    & QUARK_X1000_SSCR1_RFT)
1127                                    | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1128                                    & QUARK_X1000_SSCR1_TFT);
1129                 break;
1130         default:
1131                 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1132                         (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1133                 break;
1134         }
1135 
1136         chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1137         chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1138                         | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1139 
1140         if (spi->mode & SPI_LOOP)
1141                 chip->cr1 |= SSCR1_LBM;
1142 
1143         /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
1144         if (!pxa25x_ssp_comp(drv_data))
1145                 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1146                         drv_data->max_clk_rate
1147                                 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
1148                         chip->enable_dma ? "DMA" : "PIO");
1149         else
1150                 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1151                         drv_data->max_clk_rate / 2
1152                                 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1153                         chip->enable_dma ? "DMA" : "PIO");
1154 
1155         if (spi->bits_per_word <= 8) {
1156                 chip->n_bytes = 1;
1157                 chip->read = u8_reader;
1158                 chip->write = u8_writer;
1159         } else if (spi->bits_per_word <= 16) {
1160                 chip->n_bytes = 2;
1161                 chip->read = u16_reader;
1162                 chip->write = u16_writer;
1163         } else if (spi->bits_per_word <= 32) {
1164                 if (!is_quark_x1000_ssp(drv_data))
1165                         chip->cr0 |= SSCR0_EDSS;
1166                 chip->n_bytes = 4;
1167                 chip->read = u32_reader;
1168                 chip->write = u32_writer;
1169         }
1170         chip->bits_per_word = spi->bits_per_word;
1171 
1172         spi_set_ctldata(spi, chip);
1173 
1174         if (drv_data->ssp_type == CE4100_SSP)
1175                 return 0;
1176 
1177         return setup_cs(spi, chip, chip_info);
1178 }
1179 
1180 static void cleanup(struct spi_device *spi)
1181 {
1182         struct chip_data *chip = spi_get_ctldata(spi);
1183         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1184 
1185         if (!chip)
1186                 return;
1187 
1188         if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1189                 gpio_free(chip->gpio_cs);
1190 
1191         kfree(chip);
1192 }
1193 
1194 #ifdef CONFIG_ACPI
1195 static struct pxa2xx_spi_master *
1196 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1197 {
1198         struct pxa2xx_spi_master *pdata;
1199         struct acpi_device *adev;
1200         struct ssp_device *ssp;
1201         struct resource *res;
1202         int devid;
1203 
1204         if (!ACPI_HANDLE(&pdev->dev) ||
1205             acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
1206                 return NULL;
1207 
1208         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1209         if (!pdata)
1210                 return NULL;
1211 
1212         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1213         if (!res)
1214                 return NULL;
1215 
1216         ssp = &pdata->ssp;
1217 
1218         ssp->phys_base = res->start;
1219         ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1220         if (IS_ERR(ssp->mmio_base))
1221                 return NULL;
1222 
1223         ssp->clk = devm_clk_get(&pdev->dev, NULL);
1224         ssp->irq = platform_get_irq(pdev, 0);
1225         ssp->type = LPSS_SSP;
1226         ssp->pdev = pdev;
1227 
1228         ssp->port_id = -1;
1229         if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid))
1230                 ssp->port_id = devid;
1231 
1232         pdata->num_chipselect = 1;
1233         pdata->enable_dma = true;
1234 
1235         return pdata;
1236 }
1237 
1238 static struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1239         { "INT33C0", 0 },
1240         { "INT33C1", 0 },
1241         { "INT3430", 0 },
1242         { "INT3431", 0 },
1243         { "80860F0E", 0 },
1244         { "8086228E", 0 },
1245         { },
1246 };
1247 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1248 #else
1249 static inline struct pxa2xx_spi_master *
1250 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1251 {
1252         return NULL;
1253 }
1254 #endif
1255 
1256 static int pxa2xx_spi_probe(struct platform_device *pdev)
1257 {
1258         struct device *dev = &pdev->dev;
1259         struct pxa2xx_spi_master *platform_info;
1260         struct spi_master *master;
1261         struct driver_data *drv_data;
1262         struct ssp_device *ssp;
1263         int status;
1264         u32 tmp;
1265 
1266         platform_info = dev_get_platdata(dev);
1267         if (!platform_info) {
1268                 platform_info = pxa2xx_spi_acpi_get_pdata(pdev);
1269                 if (!platform_info) {
1270                         dev_err(&pdev->dev, "missing platform data\n");
1271                         return -ENODEV;
1272                 }
1273         }
1274 
1275         ssp = pxa_ssp_request(pdev->id, pdev->name);
1276         if (!ssp)
1277                 ssp = &platform_info->ssp;
1278 
1279         if (!ssp->mmio_base) {
1280                 dev_err(&pdev->dev, "failed to get ssp\n");
1281                 return -ENODEV;
1282         }
1283 
1284         /* Allocate master with space for drv_data and null dma buffer */
1285         master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1286         if (!master) {
1287                 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1288                 pxa_ssp_free(ssp);
1289                 return -ENOMEM;
1290         }
1291         drv_data = spi_master_get_devdata(master);
1292         drv_data->master = master;
1293         drv_data->master_info = platform_info;
1294         drv_data->pdev = pdev;
1295         drv_data->ssp = ssp;
1296 
1297         master->dev.parent = &pdev->dev;
1298         master->dev.of_node = pdev->dev.of_node;
1299         /* the spi->mode bits understood by this driver: */
1300         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1301 
1302         master->bus_num = ssp->port_id;
1303         master->num_chipselect = platform_info->num_chipselect;
1304         master->dma_alignment = DMA_ALIGNMENT;
1305         master->cleanup = cleanup;
1306         master->setup = setup;
1307         master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1308         master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1309         master->auto_runtime_pm = true;
1310 
1311         drv_data->ssp_type = ssp->type;
1312         drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT);
1313 
1314         drv_data->ioaddr = ssp->mmio_base;
1315         drv_data->ssdr_physical = ssp->phys_base + SSDR;
1316         if (pxa25x_ssp_comp(drv_data)) {
1317                 switch (drv_data->ssp_type) {
1318                 case QUARK_X1000_SSP:
1319                         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1320                         break;
1321                 default:
1322                         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1323                         break;
1324                 }
1325 
1326                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1327                 drv_data->dma_cr1 = 0;
1328                 drv_data->clear_sr = SSSR_ROR;
1329                 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1330         } else {
1331                 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1332                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1333                 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1334                 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1335                 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1336         }
1337 
1338         status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1339                         drv_data);
1340         if (status < 0) {
1341                 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1342                 goto out_error_master_alloc;
1343         }
1344 
1345         /* Setup DMA if requested */
1346         drv_data->tx_channel = -1;
1347         drv_data->rx_channel = -1;
1348         if (platform_info->enable_dma) {
1349                 status = pxa2xx_spi_dma_setup(drv_data);
1350                 if (status) {
1351                         dev_dbg(dev, "no DMA channels available, using PIO\n");
1352                         platform_info->enable_dma = false;
1353                 }
1354         }
1355 
1356         /* Enable SOC clock */
1357         clk_prepare_enable(ssp->clk);
1358 
1359         drv_data->max_clk_rate = clk_get_rate(ssp->clk);
1360 
1361         /* Load default SSP configuration */
1362         pxa2xx_spi_write(drv_data, SSCR0, 0);
1363         switch (drv_data->ssp_type) {
1364         case QUARK_X1000_SSP:
1365                 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
1366                       | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1367                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1368 
1369                 /* using the Motorola SPI protocol and use 8 bit frame */
1370                 pxa2xx_spi_write(drv_data, SSCR0,
1371                                  QUARK_X1000_SSCR0_Motorola
1372                                  | QUARK_X1000_SSCR0_DataSize(8));
1373                 break;
1374         default:
1375                 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1376                       SSCR1_TxTresh(TX_THRESH_DFLT);
1377                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1378                 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1379                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1380                 break;
1381         }
1382 
1383         if (!pxa25x_ssp_comp(drv_data))
1384                 pxa2xx_spi_write(drv_data, SSTO, 0);
1385 
1386         if (!is_quark_x1000_ssp(drv_data))
1387                 pxa2xx_spi_write(drv_data, SSPSP, 0);
1388 
1389         if (is_lpss_ssp(drv_data))
1390                 lpss_ssp_setup(drv_data);
1391 
1392         tasklet_init(&drv_data->pump_transfers, pump_transfers,
1393                      (unsigned long)drv_data);
1394 
1395         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1396         pm_runtime_use_autosuspend(&pdev->dev);
1397         pm_runtime_set_active(&pdev->dev);
1398         pm_runtime_enable(&pdev->dev);
1399 
1400         /* Register with the SPI framework */
1401         platform_set_drvdata(pdev, drv_data);
1402         status = devm_spi_register_master(&pdev->dev, master);
1403         if (status != 0) {
1404                 dev_err(&pdev->dev, "problem registering spi master\n");
1405                 goto out_error_clock_enabled;
1406         }
1407 
1408         return status;
1409 
1410 out_error_clock_enabled:
1411         clk_disable_unprepare(ssp->clk);
1412         pxa2xx_spi_dma_release(drv_data);
1413         free_irq(ssp->irq, drv_data);
1414 
1415 out_error_master_alloc:
1416         spi_master_put(master);
1417         pxa_ssp_free(ssp);
1418         return status;
1419 }
1420 
1421 static int pxa2xx_spi_remove(struct platform_device *pdev)
1422 {
1423         struct driver_data *drv_data = platform_get_drvdata(pdev);
1424         struct ssp_device *ssp;
1425 
1426         if (!drv_data)
1427                 return 0;
1428         ssp = drv_data->ssp;
1429 
1430         pm_runtime_get_sync(&pdev->dev);
1431 
1432         /* Disable the SSP at the peripheral and SOC level */
1433         pxa2xx_spi_write(drv_data, SSCR0, 0);
1434         clk_disable_unprepare(ssp->clk);
1435 
1436         /* Release DMA */
1437         if (drv_data->master_info->enable_dma)
1438                 pxa2xx_spi_dma_release(drv_data);
1439 
1440         pm_runtime_put_noidle(&pdev->dev);
1441         pm_runtime_disable(&pdev->dev);
1442 
1443         /* Release IRQ */
1444         free_irq(ssp->irq, drv_data);
1445 
1446         /* Release SSP */
1447         pxa_ssp_free(ssp);
1448 
1449         return 0;
1450 }
1451 
1452 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1453 {
1454         int status = 0;
1455 
1456         if ((status = pxa2xx_spi_remove(pdev)) != 0)
1457                 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1458 }
1459 
1460 #ifdef CONFIG_PM_SLEEP
1461 static int pxa2xx_spi_suspend(struct device *dev)
1462 {
1463         struct driver_data *drv_data = dev_get_drvdata(dev);
1464         struct ssp_device *ssp = drv_data->ssp;
1465         int status = 0;
1466 
1467         status = spi_master_suspend(drv_data->master);
1468         if (status != 0)
1469                 return status;
1470         pxa2xx_spi_write(drv_data, SSCR0, 0);
1471 
1472         if (!pm_runtime_suspended(dev))
1473                 clk_disable_unprepare(ssp->clk);
1474 
1475         return 0;
1476 }
1477 
1478 static int pxa2xx_spi_resume(struct device *dev)
1479 {
1480         struct driver_data *drv_data = dev_get_drvdata(dev);
1481         struct ssp_device *ssp = drv_data->ssp;
1482         int status = 0;
1483 
1484         pxa2xx_spi_dma_resume(drv_data);
1485 
1486         /* Enable the SSP clock */
1487         if (!pm_runtime_suspended(dev))
1488                 clk_prepare_enable(ssp->clk);
1489 
1490         /* Restore LPSS private register bits */
1491         if (is_lpss_ssp(drv_data))
1492                 lpss_ssp_setup(drv_data);
1493 
1494         /* Start the queue running */
1495         status = spi_master_resume(drv_data->master);
1496         if (status != 0) {
1497                 dev_err(dev, "problem starting queue (%d)\n", status);
1498                 return status;
1499         }
1500 
1501         return 0;
1502 }
1503 #endif
1504 
1505 #ifdef CONFIG_PM
1506 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1507 {
1508         struct driver_data *drv_data = dev_get_drvdata(dev);
1509 
1510         clk_disable_unprepare(drv_data->ssp->clk);
1511         return 0;
1512 }
1513 
1514 static int pxa2xx_spi_runtime_resume(struct device *dev)
1515 {
1516         struct driver_data *drv_data = dev_get_drvdata(dev);
1517 
1518         clk_prepare_enable(drv_data->ssp->clk);
1519         return 0;
1520 }
1521 #endif
1522 
1523 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1524         SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1525         SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1526                            pxa2xx_spi_runtime_resume, NULL)
1527 };
1528 
1529 static struct platform_driver driver = {
1530         .driver = {
1531                 .name   = "pxa2xx-spi",
1532                 .pm     = &pxa2xx_spi_pm_ops,
1533                 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1534         },
1535         .probe = pxa2xx_spi_probe,
1536         .remove = pxa2xx_spi_remove,
1537         .shutdown = pxa2xx_spi_shutdown,
1538 };
1539 
1540 static int __init pxa2xx_spi_init(void)
1541 {
1542         return platform_driver_register(&driver);
1543 }
1544 subsys_initcall(pxa2xx_spi_init);
1545 
1546 static void __exit pxa2xx_spi_exit(void)
1547 {
1548         platform_driver_unregister(&driver);
1549 }
1550 module_exit(pxa2xx_spi_exit);
1551 

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