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Linux/drivers/spi/spi-pxa2xx.c

  1 /*
  2  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
  3  * Copyright (C) 2013, Intel Corporation
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License as published by
  7  * the Free Software Foundation; either version 2 of the License, or
  8  * (at your option) any later version.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  */
 15 
 16 #include <linux/bitops.h>
 17 #include <linux/init.h>
 18 #include <linux/module.h>
 19 #include <linux/device.h>
 20 #include <linux/ioport.h>
 21 #include <linux/errno.h>
 22 #include <linux/err.h>
 23 #include <linux/interrupt.h>
 24 #include <linux/kernel.h>
 25 #include <linux/pci.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/spi/pxa2xx_spi.h>
 28 #include <linux/spi/spi.h>
 29 #include <linux/delay.h>
 30 #include <linux/gpio.h>
 31 #include <linux/gpio/consumer.h>
 32 #include <linux/slab.h>
 33 #include <linux/clk.h>
 34 #include <linux/pm_runtime.h>
 35 #include <linux/acpi.h>
 36 
 37 #include "spi-pxa2xx.h"
 38 
 39 MODULE_AUTHOR("Stephen Street");
 40 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
 41 MODULE_LICENSE("GPL");
 42 MODULE_ALIAS("platform:pxa2xx-spi");
 43 
 44 #define TIMOUT_DFLT             1000
 45 
 46 /*
 47  * for testing SSCR1 changes that require SSP restart, basically
 48  * everything except the service and interrupt enables, the pxa270 developer
 49  * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
 50  * list, but the PXA255 dev man says all bits without really meaning the
 51  * service and interrupt enables
 52  */
 53 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
 54                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
 55                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
 56                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
 57                                 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
 58                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
 59 
 60 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF   \
 61                                 | QUARK_X1000_SSCR1_EFWR        \
 62                                 | QUARK_X1000_SSCR1_RFT         \
 63                                 | QUARK_X1000_SSCR1_TFT         \
 64                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
 65 
 66 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
 67                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
 68                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
 69                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
 70                                 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
 71                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
 72 
 73 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE   BIT(24)
 74 #define LPSS_CS_CONTROL_SW_MODE                 BIT(0)
 75 #define LPSS_CS_CONTROL_CS_HIGH                 BIT(1)
 76 #define LPSS_CAPS_CS_EN_SHIFT                   9
 77 #define LPSS_CAPS_CS_EN_MASK                    (0xf << LPSS_CAPS_CS_EN_SHIFT)
 78 
 79 struct lpss_config {
 80         /* LPSS offset from drv_data->ioaddr */
 81         unsigned offset;
 82         /* Register offsets from drv_data->lpss_base or -1 */
 83         int reg_general;
 84         int reg_ssp;
 85         int reg_cs_ctrl;
 86         int reg_capabilities;
 87         /* FIFO thresholds */
 88         u32 rx_threshold;
 89         u32 tx_threshold_lo;
 90         u32 tx_threshold_hi;
 91         /* Chip select control */
 92         unsigned cs_sel_shift;
 93         unsigned cs_sel_mask;
 94         unsigned cs_num;
 95 };
 96 
 97 /* Keep these sorted with enum pxa_ssp_type */
 98 static const struct lpss_config lpss_platforms[] = {
 99         {       /* LPSS_LPT_SSP */
100                 .offset = 0x800,
101                 .reg_general = 0x08,
102                 .reg_ssp = 0x0c,
103                 .reg_cs_ctrl = 0x18,
104                 .reg_capabilities = -1,
105                 .rx_threshold = 64,
106                 .tx_threshold_lo = 160,
107                 .tx_threshold_hi = 224,
108         },
109         {       /* LPSS_BYT_SSP */
110                 .offset = 0x400,
111                 .reg_general = 0x08,
112                 .reg_ssp = 0x0c,
113                 .reg_cs_ctrl = 0x18,
114                 .reg_capabilities = -1,
115                 .rx_threshold = 64,
116                 .tx_threshold_lo = 160,
117                 .tx_threshold_hi = 224,
118         },
119         {       /* LPSS_BSW_SSP */
120                 .offset = 0x400,
121                 .reg_general = 0x08,
122                 .reg_ssp = 0x0c,
123                 .reg_cs_ctrl = 0x18,
124                 .reg_capabilities = -1,
125                 .rx_threshold = 64,
126                 .tx_threshold_lo = 160,
127                 .tx_threshold_hi = 224,
128                 .cs_sel_shift = 2,
129                 .cs_sel_mask = 1 << 2,
130                 .cs_num = 2,
131         },
132         {       /* LPSS_SPT_SSP */
133                 .offset = 0x200,
134                 .reg_general = -1,
135                 .reg_ssp = 0x20,
136                 .reg_cs_ctrl = 0x24,
137                 .reg_capabilities = -1,
138                 .rx_threshold = 1,
139                 .tx_threshold_lo = 32,
140                 .tx_threshold_hi = 56,
141         },
142         {       /* LPSS_BXT_SSP */
143                 .offset = 0x200,
144                 .reg_general = -1,
145                 .reg_ssp = 0x20,
146                 .reg_cs_ctrl = 0x24,
147                 .reg_capabilities = 0xfc,
148                 .rx_threshold = 1,
149                 .tx_threshold_lo = 16,
150                 .tx_threshold_hi = 48,
151                 .cs_sel_shift = 8,
152                 .cs_sel_mask = 3 << 8,
153         },
154 };
155 
156 static inline const struct lpss_config
157 *lpss_get_config(const struct driver_data *drv_data)
158 {
159         return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
160 }
161 
162 static bool is_lpss_ssp(const struct driver_data *drv_data)
163 {
164         switch (drv_data->ssp_type) {
165         case LPSS_LPT_SSP:
166         case LPSS_BYT_SSP:
167         case LPSS_BSW_SSP:
168         case LPSS_SPT_SSP:
169         case LPSS_BXT_SSP:
170                 return true;
171         default:
172                 return false;
173         }
174 }
175 
176 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
177 {
178         return drv_data->ssp_type == QUARK_X1000_SSP;
179 }
180 
181 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
182 {
183         switch (drv_data->ssp_type) {
184         case QUARK_X1000_SSP:
185                 return QUARK_X1000_SSCR1_CHANGE_MASK;
186         case CE4100_SSP:
187                 return CE4100_SSCR1_CHANGE_MASK;
188         default:
189                 return SSCR1_CHANGE_MASK;
190         }
191 }
192 
193 static u32
194 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
195 {
196         switch (drv_data->ssp_type) {
197         case QUARK_X1000_SSP:
198                 return RX_THRESH_QUARK_X1000_DFLT;
199         case CE4100_SSP:
200                 return RX_THRESH_CE4100_DFLT;
201         default:
202                 return RX_THRESH_DFLT;
203         }
204 }
205 
206 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
207 {
208         u32 mask;
209 
210         switch (drv_data->ssp_type) {
211         case QUARK_X1000_SSP:
212                 mask = QUARK_X1000_SSSR_TFL_MASK;
213                 break;
214         case CE4100_SSP:
215                 mask = CE4100_SSSR_TFL_MASK;
216                 break;
217         default:
218                 mask = SSSR_TFL_MASK;
219                 break;
220         }
221 
222         return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
223 }
224 
225 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
226                                      u32 *sccr1_reg)
227 {
228         u32 mask;
229 
230         switch (drv_data->ssp_type) {
231         case QUARK_X1000_SSP:
232                 mask = QUARK_X1000_SSCR1_RFT;
233                 break;
234         case CE4100_SSP:
235                 mask = CE4100_SSCR1_RFT;
236                 break;
237         default:
238                 mask = SSCR1_RFT;
239                 break;
240         }
241         *sccr1_reg &= ~mask;
242 }
243 
244 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
245                                    u32 *sccr1_reg, u32 threshold)
246 {
247         switch (drv_data->ssp_type) {
248         case QUARK_X1000_SSP:
249                 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
250                 break;
251         case CE4100_SSP:
252                 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
253                 break;
254         default:
255                 *sccr1_reg |= SSCR1_RxTresh(threshold);
256                 break;
257         }
258 }
259 
260 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
261                                   u32 clk_div, u8 bits)
262 {
263         switch (drv_data->ssp_type) {
264         case QUARK_X1000_SSP:
265                 return clk_div
266                         | QUARK_X1000_SSCR0_Motorola
267                         | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
268                         | SSCR0_SSE;
269         default:
270                 return clk_div
271                         | SSCR0_Motorola
272                         | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
273                         | SSCR0_SSE
274                         | (bits > 16 ? SSCR0_EDSS : 0);
275         }
276 }
277 
278 /*
279  * Read and write LPSS SSP private registers. Caller must first check that
280  * is_lpss_ssp() returns true before these can be called.
281  */
282 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
283 {
284         WARN_ON(!drv_data->lpss_base);
285         return readl(drv_data->lpss_base + offset);
286 }
287 
288 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
289                                   unsigned offset, u32 value)
290 {
291         WARN_ON(!drv_data->lpss_base);
292         writel(value, drv_data->lpss_base + offset);
293 }
294 
295 /*
296  * lpss_ssp_setup - perform LPSS SSP specific setup
297  * @drv_data: pointer to the driver private data
298  *
299  * Perform LPSS SSP specific setup. This function must be called first if
300  * one is going to use LPSS SSP private registers.
301  */
302 static void lpss_ssp_setup(struct driver_data *drv_data)
303 {
304         const struct lpss_config *config;
305         u32 value;
306 
307         config = lpss_get_config(drv_data);
308         drv_data->lpss_base = drv_data->ioaddr + config->offset;
309 
310         /* Enable software chip select control */
311         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
312         value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
313         value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
314         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
315 
316         /* Enable multiblock DMA transfers */
317         if (drv_data->master_info->enable_dma) {
318                 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
319 
320                 if (config->reg_general >= 0) {
321                         value = __lpss_ssp_read_priv(drv_data,
322                                                      config->reg_general);
323                         value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
324                         __lpss_ssp_write_priv(drv_data,
325                                               config->reg_general, value);
326                 }
327         }
328 }
329 
330 static void lpss_ssp_select_cs(struct driver_data *drv_data,
331                                const struct lpss_config *config)
332 {
333         u32 value, cs;
334 
335         if (!config->cs_sel_mask)
336                 return;
337 
338         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
339 
340         cs = drv_data->master->cur_msg->spi->chip_select;
341         cs <<= config->cs_sel_shift;
342         if (cs != (value & config->cs_sel_mask)) {
343                 /*
344                  * When switching another chip select output active the
345                  * output must be selected first and wait 2 ssp_clk cycles
346                  * before changing state to active. Otherwise a short
347                  * glitch will occur on the previous chip select since
348                  * output select is latched but state control is not.
349                  */
350                 value &= ~config->cs_sel_mask;
351                 value |= cs;
352                 __lpss_ssp_write_priv(drv_data,
353                                       config->reg_cs_ctrl, value);
354                 ndelay(1000000000 /
355                        (drv_data->master->max_speed_hz / 2));
356         }
357 }
358 
359 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
360 {
361         const struct lpss_config *config;
362         u32 value;
363 
364         config = lpss_get_config(drv_data);
365 
366         if (enable)
367                 lpss_ssp_select_cs(drv_data, config);
368 
369         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
370         if (enable)
371                 value &= ~LPSS_CS_CONTROL_CS_HIGH;
372         else
373                 value |= LPSS_CS_CONTROL_CS_HIGH;
374         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
375 }
376 
377 static void cs_assert(struct driver_data *drv_data)
378 {
379         struct chip_data *chip =
380                 spi_get_ctldata(drv_data->master->cur_msg->spi);
381 
382         if (drv_data->ssp_type == CE4100_SSP) {
383                 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
384                 return;
385         }
386 
387         if (chip->cs_control) {
388                 chip->cs_control(PXA2XX_CS_ASSERT);
389                 return;
390         }
391 
392         if (gpio_is_valid(chip->gpio_cs)) {
393                 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
394                 return;
395         }
396 
397         if (is_lpss_ssp(drv_data))
398                 lpss_ssp_cs_control(drv_data, true);
399 }
400 
401 static void cs_deassert(struct driver_data *drv_data)
402 {
403         struct chip_data *chip =
404                 spi_get_ctldata(drv_data->master->cur_msg->spi);
405 
406         if (drv_data->ssp_type == CE4100_SSP)
407                 return;
408 
409         if (chip->cs_control) {
410                 chip->cs_control(PXA2XX_CS_DEASSERT);
411                 return;
412         }
413 
414         if (gpio_is_valid(chip->gpio_cs)) {
415                 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
416                 return;
417         }
418 
419         if (is_lpss_ssp(drv_data))
420                 lpss_ssp_cs_control(drv_data, false);
421 }
422 
423 int pxa2xx_spi_flush(struct driver_data *drv_data)
424 {
425         unsigned long limit = loops_per_jiffy << 1;
426 
427         do {
428                 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
429                         pxa2xx_spi_read(drv_data, SSDR);
430         } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
431         write_SSSR_CS(drv_data, SSSR_ROR);
432 
433         return limit;
434 }
435 
436 static int null_writer(struct driver_data *drv_data)
437 {
438         u8 n_bytes = drv_data->n_bytes;
439 
440         if (pxa2xx_spi_txfifo_full(drv_data)
441                 || (drv_data->tx == drv_data->tx_end))
442                 return 0;
443 
444         pxa2xx_spi_write(drv_data, SSDR, 0);
445         drv_data->tx += n_bytes;
446 
447         return 1;
448 }
449 
450 static int null_reader(struct driver_data *drv_data)
451 {
452         u8 n_bytes = drv_data->n_bytes;
453 
454         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
455                && (drv_data->rx < drv_data->rx_end)) {
456                 pxa2xx_spi_read(drv_data, SSDR);
457                 drv_data->rx += n_bytes;
458         }
459 
460         return drv_data->rx == drv_data->rx_end;
461 }
462 
463 static int u8_writer(struct driver_data *drv_data)
464 {
465         if (pxa2xx_spi_txfifo_full(drv_data)
466                 || (drv_data->tx == drv_data->tx_end))
467                 return 0;
468 
469         pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
470         ++drv_data->tx;
471 
472         return 1;
473 }
474 
475 static int u8_reader(struct driver_data *drv_data)
476 {
477         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
478                && (drv_data->rx < drv_data->rx_end)) {
479                 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
480                 ++drv_data->rx;
481         }
482 
483         return drv_data->rx == drv_data->rx_end;
484 }
485 
486 static int u16_writer(struct driver_data *drv_data)
487 {
488         if (pxa2xx_spi_txfifo_full(drv_data)
489                 || (drv_data->tx == drv_data->tx_end))
490                 return 0;
491 
492         pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
493         drv_data->tx += 2;
494 
495         return 1;
496 }
497 
498 static int u16_reader(struct driver_data *drv_data)
499 {
500         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
501                && (drv_data->rx < drv_data->rx_end)) {
502                 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
503                 drv_data->rx += 2;
504         }
505 
506         return drv_data->rx == drv_data->rx_end;
507 }
508 
509 static int u32_writer(struct driver_data *drv_data)
510 {
511         if (pxa2xx_spi_txfifo_full(drv_data)
512                 || (drv_data->tx == drv_data->tx_end))
513                 return 0;
514 
515         pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
516         drv_data->tx += 4;
517 
518         return 1;
519 }
520 
521 static int u32_reader(struct driver_data *drv_data)
522 {
523         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
524                && (drv_data->rx < drv_data->rx_end)) {
525                 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
526                 drv_data->rx += 4;
527         }
528 
529         return drv_data->rx == drv_data->rx_end;
530 }
531 
532 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
533 {
534         struct spi_message *msg = drv_data->master->cur_msg;
535         struct spi_transfer *trans = drv_data->cur_transfer;
536 
537         /* Move to next transfer */
538         if (trans->transfer_list.next != &msg->transfers) {
539                 drv_data->cur_transfer =
540                         list_entry(trans->transfer_list.next,
541                                         struct spi_transfer,
542                                         transfer_list);
543                 return RUNNING_STATE;
544         } else
545                 return DONE_STATE;
546 }
547 
548 /* caller already set message->status; dma and pio irqs are blocked */
549 static void giveback(struct driver_data *drv_data)
550 {
551         struct spi_transfer* last_transfer;
552         struct spi_message *msg;
553         unsigned long timeout;
554 
555         msg = drv_data->master->cur_msg;
556         drv_data->cur_transfer = NULL;
557 
558         last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
559                                         transfer_list);
560 
561         /* Delay if requested before any change in chip select */
562         if (last_transfer->delay_usecs)
563                 udelay(last_transfer->delay_usecs);
564 
565         /* Wait until SSP becomes idle before deasserting the CS */
566         timeout = jiffies + msecs_to_jiffies(10);
567         while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
568                !time_after(jiffies, timeout))
569                 cpu_relax();
570 
571         /* Drop chip select UNLESS cs_change is true or we are returning
572          * a message with an error, or next message is for another chip
573          */
574         if (!last_transfer->cs_change)
575                 cs_deassert(drv_data);
576         else {
577                 struct spi_message *next_msg;
578 
579                 /* Holding of cs was hinted, but we need to make sure
580                  * the next message is for the same chip.  Don't waste
581                  * time with the following tests unless this was hinted.
582                  *
583                  * We cannot postpone this until pump_messages, because
584                  * after calling msg->complete (below) the driver that
585                  * sent the current message could be unloaded, which
586                  * could invalidate the cs_control() callback...
587                  */
588 
589                 /* get a pointer to the next message, if any */
590                 next_msg = spi_get_next_queued_message(drv_data->master);
591 
592                 /* see if the next and current messages point
593                  * to the same chip
594                  */
595                 if ((next_msg && next_msg->spi != msg->spi) ||
596                     msg->state == ERROR_STATE)
597                         cs_deassert(drv_data);
598         }
599 
600         spi_finalize_current_message(drv_data->master);
601 }
602 
603 static void reset_sccr1(struct driver_data *drv_data)
604 {
605         struct chip_data *chip =
606                 spi_get_ctldata(drv_data->master->cur_msg->spi);
607         u32 sccr1_reg;
608 
609         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
610         switch (drv_data->ssp_type) {
611         case QUARK_X1000_SSP:
612                 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
613                 break;
614         case CE4100_SSP:
615                 sccr1_reg &= ~CE4100_SSCR1_RFT;
616                 break;
617         default:
618                 sccr1_reg &= ~SSCR1_RFT;
619                 break;
620         }
621         sccr1_reg |= chip->threshold;
622         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
623 }
624 
625 static void int_error_stop(struct driver_data *drv_data, const char* msg)
626 {
627         /* Stop and reset SSP */
628         write_SSSR_CS(drv_data, drv_data->clear_sr);
629         reset_sccr1(drv_data);
630         if (!pxa25x_ssp_comp(drv_data))
631                 pxa2xx_spi_write(drv_data, SSTO, 0);
632         pxa2xx_spi_flush(drv_data);
633         pxa2xx_spi_write(drv_data, SSCR0,
634                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
635 
636         dev_err(&drv_data->pdev->dev, "%s\n", msg);
637 
638         drv_data->master->cur_msg->state = ERROR_STATE;
639         tasklet_schedule(&drv_data->pump_transfers);
640 }
641 
642 static void int_transfer_complete(struct driver_data *drv_data)
643 {
644         /* Clear and disable interrupts */
645         write_SSSR_CS(drv_data, drv_data->clear_sr);
646         reset_sccr1(drv_data);
647         if (!pxa25x_ssp_comp(drv_data))
648                 pxa2xx_spi_write(drv_data, SSTO, 0);
649 
650         /* Update total byte transferred return count actual bytes read */
651         drv_data->master->cur_msg->actual_length += drv_data->len -
652                                 (drv_data->rx_end - drv_data->rx);
653 
654         /* Transfer delays and chip select release are
655          * handled in pump_transfers or giveback
656          */
657 
658         /* Move to next transfer */
659         drv_data->master->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
660 
661         /* Schedule transfer tasklet */
662         tasklet_schedule(&drv_data->pump_transfers);
663 }
664 
665 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
666 {
667         u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
668                        drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
669 
670         u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
671 
672         if (irq_status & SSSR_ROR) {
673                 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
674                 return IRQ_HANDLED;
675         }
676 
677         if (irq_status & SSSR_TINT) {
678                 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
679                 if (drv_data->read(drv_data)) {
680                         int_transfer_complete(drv_data);
681                         return IRQ_HANDLED;
682                 }
683         }
684 
685         /* Drain rx fifo, Fill tx fifo and prevent overruns */
686         do {
687                 if (drv_data->read(drv_data)) {
688                         int_transfer_complete(drv_data);
689                         return IRQ_HANDLED;
690                 }
691         } while (drv_data->write(drv_data));
692 
693         if (drv_data->read(drv_data)) {
694                 int_transfer_complete(drv_data);
695                 return IRQ_HANDLED;
696         }
697 
698         if (drv_data->tx == drv_data->tx_end) {
699                 u32 bytes_left;
700                 u32 sccr1_reg;
701 
702                 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
703                 sccr1_reg &= ~SSCR1_TIE;
704 
705                 /*
706                  * PXA25x_SSP has no timeout, set up rx threshould for the
707                  * remaining RX bytes.
708                  */
709                 if (pxa25x_ssp_comp(drv_data)) {
710                         u32 rx_thre;
711 
712                         pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
713 
714                         bytes_left = drv_data->rx_end - drv_data->rx;
715                         switch (drv_data->n_bytes) {
716                         case 4:
717                                 bytes_left >>= 1;
718                         case 2:
719                                 bytes_left >>= 1;
720                         }
721 
722                         rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
723                         if (rx_thre > bytes_left)
724                                 rx_thre = bytes_left;
725 
726                         pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
727                 }
728                 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
729         }
730 
731         /* We did something */
732         return IRQ_HANDLED;
733 }
734 
735 static irqreturn_t ssp_int(int irq, void *dev_id)
736 {
737         struct driver_data *drv_data = dev_id;
738         u32 sccr1_reg;
739         u32 mask = drv_data->mask_sr;
740         u32 status;
741 
742         /*
743          * The IRQ might be shared with other peripherals so we must first
744          * check that are we RPM suspended or not. If we are we assume that
745          * the IRQ was not for us (we shouldn't be RPM suspended when the
746          * interrupt is enabled).
747          */
748         if (pm_runtime_suspended(&drv_data->pdev->dev))
749                 return IRQ_NONE;
750 
751         /*
752          * If the device is not yet in RPM suspended state and we get an
753          * interrupt that is meant for another device, check if status bits
754          * are all set to one. That means that the device is already
755          * powered off.
756          */
757         status = pxa2xx_spi_read(drv_data, SSSR);
758         if (status == ~0)
759                 return IRQ_NONE;
760 
761         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
762 
763         /* Ignore possible writes if we don't need to write */
764         if (!(sccr1_reg & SSCR1_TIE))
765                 mask &= ~SSSR_TFS;
766 
767         /* Ignore RX timeout interrupt if it is disabled */
768         if (!(sccr1_reg & SSCR1_TINTE))
769                 mask &= ~SSSR_TINT;
770 
771         if (!(status & mask))
772                 return IRQ_NONE;
773 
774         if (!drv_data->master->cur_msg) {
775 
776                 pxa2xx_spi_write(drv_data, SSCR0,
777                                  pxa2xx_spi_read(drv_data, SSCR0)
778                                  & ~SSCR0_SSE);
779                 pxa2xx_spi_write(drv_data, SSCR1,
780                                  pxa2xx_spi_read(drv_data, SSCR1)
781                                  & ~drv_data->int_cr1);
782                 if (!pxa25x_ssp_comp(drv_data))
783                         pxa2xx_spi_write(drv_data, SSTO, 0);
784                 write_SSSR_CS(drv_data, drv_data->clear_sr);
785 
786                 dev_err(&drv_data->pdev->dev,
787                         "bad message state in interrupt handler\n");
788 
789                 /* Never fail */
790                 return IRQ_HANDLED;
791         }
792 
793         return drv_data->transfer_handler(drv_data);
794 }
795 
796 /*
797  * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
798  * input frequency by fractions of 2^24. It also has a divider by 5.
799  *
800  * There are formulas to get baud rate value for given input frequency and
801  * divider parameters, such as DDS_CLK_RATE and SCR:
802  *
803  * Fsys = 200MHz
804  *
805  * Fssp = Fsys * DDS_CLK_RATE / 2^24                    (1)
806  * Baud rate = Fsclk = Fssp / (2 * (SCR + 1))           (2)
807  *
808  * DDS_CLK_RATE either 2^n or 2^n / 5.
809  * SCR is in range 0 .. 255
810  *
811  * Divisor = 5^i * 2^j * 2 * k
812  *       i = [0, 1]      i = 1 iff j = 0 or j > 3
813  *       j = [0, 23]     j = 0 iff i = 1
814  *       k = [1, 256]
815  * Special case: j = 0, i = 1: Divisor = 2 / 5
816  *
817  * Accordingly to the specification the recommended values for DDS_CLK_RATE
818  * are:
819  *      Case 1:         2^n, n = [0, 23]
820  *      Case 2:         2^24 * 2 / 5 (0x666666)
821  *      Case 3:         less than or equal to 2^24 / 5 / 16 (0x33333)
822  *
823  * In all cases the lowest possible value is better.
824  *
825  * The function calculates parameters for all cases and chooses the one closest
826  * to the asked baud rate.
827  */
828 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
829 {
830         unsigned long xtal = 200000000;
831         unsigned long fref = xtal / 2;          /* mandatory division by 2,
832                                                    see (2) */
833                                                 /* case 3 */
834         unsigned long fref1 = fref / 2;         /* case 1 */
835         unsigned long fref2 = fref * 2 / 5;     /* case 2 */
836         unsigned long scale;
837         unsigned long q, q1, q2;
838         long r, r1, r2;
839         u32 mul;
840 
841         /* Case 1 */
842 
843         /* Set initial value for DDS_CLK_RATE */
844         mul = (1 << 24) >> 1;
845 
846         /* Calculate initial quot */
847         q1 = DIV_ROUND_UP(fref1, rate);
848 
849         /* Scale q1 if it's too big */
850         if (q1 > 256) {
851                 /* Scale q1 to range [1, 512] */
852                 scale = fls_long(q1 - 1);
853                 if (scale > 9) {
854                         q1 >>= scale - 9;
855                         mul >>= scale - 9;
856                 }
857 
858                 /* Round the result if we have a remainder */
859                 q1 += q1 & 1;
860         }
861 
862         /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
863         scale = __ffs(q1);
864         q1 >>= scale;
865         mul >>= scale;
866 
867         /* Get the remainder */
868         r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
869 
870         /* Case 2 */
871 
872         q2 = DIV_ROUND_UP(fref2, rate);
873         r2 = abs(fref2 / q2 - rate);
874 
875         /*
876          * Choose the best between two: less remainder we have the better. We
877          * can't go case 2 if q2 is greater than 256 since SCR register can
878          * hold only values 0 .. 255.
879          */
880         if (r2 >= r1 || q2 > 256) {
881                 /* case 1 is better */
882                 r = r1;
883                 q = q1;
884         } else {
885                 /* case 2 is better */
886                 r = r2;
887                 q = q2;
888                 mul = (1 << 24) * 2 / 5;
889         }
890 
891         /* Check case 3 only if the divisor is big enough */
892         if (fref / rate >= 80) {
893                 u64 fssp;
894                 u32 m;
895 
896                 /* Calculate initial quot */
897                 q1 = DIV_ROUND_UP(fref, rate);
898                 m = (1 << 24) / q1;
899 
900                 /* Get the remainder */
901                 fssp = (u64)fref * m;
902                 do_div(fssp, 1 << 24);
903                 r1 = abs(fssp - rate);
904 
905                 /* Choose this one if it suits better */
906                 if (r1 < r) {
907                         /* case 3 is better */
908                         q = 1;
909                         mul = m;
910                 }
911         }
912 
913         *dds = mul;
914         return q - 1;
915 }
916 
917 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
918 {
919         unsigned long ssp_clk = drv_data->master->max_speed_hz;
920         const struct ssp_device *ssp = drv_data->ssp;
921 
922         rate = min_t(int, ssp_clk, rate);
923 
924         if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
925                 return (ssp_clk / (2 * rate) - 1) & 0xff;
926         else
927                 return (ssp_clk / rate - 1) & 0xfff;
928 }
929 
930 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
931                                            int rate)
932 {
933         struct chip_data *chip =
934                 spi_get_ctldata(drv_data->master->cur_msg->spi);
935         unsigned int clk_div;
936 
937         switch (drv_data->ssp_type) {
938         case QUARK_X1000_SSP:
939                 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
940                 break;
941         default:
942                 clk_div = ssp_get_clk_div(drv_data, rate);
943                 break;
944         }
945         return clk_div << 8;
946 }
947 
948 static bool pxa2xx_spi_can_dma(struct spi_master *master,
949                                struct spi_device *spi,
950                                struct spi_transfer *xfer)
951 {
952         struct chip_data *chip = spi_get_ctldata(spi);
953 
954         return chip->enable_dma &&
955                xfer->len <= MAX_DMA_LEN &&
956                xfer->len >= chip->dma_burst_size;
957 }
958 
959 static void pump_transfers(unsigned long data)
960 {
961         struct driver_data *drv_data = (struct driver_data *)data;
962         struct spi_master *master = drv_data->master;
963         struct spi_message *message = master->cur_msg;
964         struct chip_data *chip = spi_get_ctldata(message->spi);
965         u32 dma_thresh = chip->dma_threshold;
966         u32 dma_burst = chip->dma_burst_size;
967         u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
968         struct spi_transfer *transfer;
969         struct spi_transfer *previous;
970         u32 clk_div;
971         u8 bits;
972         u32 speed;
973         u32 cr0;
974         u32 cr1;
975         int err;
976         int dma_mapped;
977 
978         /* Get current state information */
979         transfer = drv_data->cur_transfer;
980 
981         /* Handle for abort */
982         if (message->state == ERROR_STATE) {
983                 message->status = -EIO;
984                 giveback(drv_data);
985                 return;
986         }
987 
988         /* Handle end of message */
989         if (message->state == DONE_STATE) {
990                 message->status = 0;
991                 giveback(drv_data);
992                 return;
993         }
994 
995         /* Delay if requested at end of transfer before CS change */
996         if (message->state == RUNNING_STATE) {
997                 previous = list_entry(transfer->transfer_list.prev,
998                                         struct spi_transfer,
999                                         transfer_list);
1000                 if (previous->delay_usecs)
1001                         udelay(previous->delay_usecs);
1002 
1003                 /* Drop chip select only if cs_change is requested */
1004                 if (previous->cs_change)
1005                         cs_deassert(drv_data);
1006         }
1007 
1008         /* Check if we can DMA this transfer */
1009         if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
1010 
1011                 /* reject already-mapped transfers; PIO won't always work */
1012                 if (message->is_dma_mapped
1013                                 || transfer->rx_dma || transfer->tx_dma) {
1014                         dev_err(&drv_data->pdev->dev,
1015                                 "pump_transfers: mapped transfer length of "
1016                                 "%u is greater than %d\n",
1017                                 transfer->len, MAX_DMA_LEN);
1018                         message->status = -EINVAL;
1019                         giveback(drv_data);
1020                         return;
1021                 }
1022 
1023                 /* warn ... we force this to PIO mode */
1024                 dev_warn_ratelimited(&message->spi->dev,
1025                                      "pump_transfers: DMA disabled for transfer length %ld "
1026                                      "greater than %d\n",
1027                                      (long)drv_data->len, MAX_DMA_LEN);
1028         }
1029 
1030         /* Setup the transfer state based on the type of transfer */
1031         if (pxa2xx_spi_flush(drv_data) == 0) {
1032                 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
1033                 message->status = -EIO;
1034                 giveback(drv_data);
1035                 return;
1036         }
1037         drv_data->n_bytes = chip->n_bytes;
1038         drv_data->tx = (void *)transfer->tx_buf;
1039         drv_data->tx_end = drv_data->tx + transfer->len;
1040         drv_data->rx = transfer->rx_buf;
1041         drv_data->rx_end = drv_data->rx + transfer->len;
1042         drv_data->len = transfer->len;
1043         drv_data->write = drv_data->tx ? chip->write : null_writer;
1044         drv_data->read = drv_data->rx ? chip->read : null_reader;
1045 
1046         /* Change speed and bit per word on a per transfer */
1047         bits = transfer->bits_per_word;
1048         speed = transfer->speed_hz;
1049 
1050         clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
1051 
1052         if (bits <= 8) {
1053                 drv_data->n_bytes = 1;
1054                 drv_data->read = drv_data->read != null_reader ?
1055                                         u8_reader : null_reader;
1056                 drv_data->write = drv_data->write != null_writer ?
1057                                         u8_writer : null_writer;
1058         } else if (bits <= 16) {
1059                 drv_data->n_bytes = 2;
1060                 drv_data->read = drv_data->read != null_reader ?
1061                                         u16_reader : null_reader;
1062                 drv_data->write = drv_data->write != null_writer ?
1063                                         u16_writer : null_writer;
1064         } else if (bits <= 32) {
1065                 drv_data->n_bytes = 4;
1066                 drv_data->read = drv_data->read != null_reader ?
1067                                         u32_reader : null_reader;
1068                 drv_data->write = drv_data->write != null_writer ?
1069                                         u32_writer : null_writer;
1070         }
1071         /*
1072          * if bits/word is changed in dma mode, then must check the
1073          * thresholds and burst also
1074          */
1075         if (chip->enable_dma) {
1076                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1077                                                 message->spi,
1078                                                 bits, &dma_burst,
1079                                                 &dma_thresh))
1080                         dev_warn_ratelimited(&message->spi->dev,
1081                                              "pump_transfers: DMA burst size reduced to match bits_per_word\n");
1082         }
1083 
1084         message->state = RUNNING_STATE;
1085 
1086         dma_mapped = master->can_dma &&
1087                      master->can_dma(master, message->spi, transfer) &&
1088                      master->cur_msg_mapped;
1089         if (dma_mapped) {
1090 
1091                 /* Ensure we have the correct interrupt handler */
1092                 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1093 
1094                 err = pxa2xx_spi_dma_prepare(drv_data, dma_burst);
1095                 if (err) {
1096                         message->status = err;
1097                         giveback(drv_data);
1098                         return;
1099                 }
1100 
1101                 /* Clear status and start DMA engine */
1102                 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1103                 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1104 
1105                 pxa2xx_spi_dma_start(drv_data);
1106         } else {
1107                 /* Ensure we have the correct interrupt handler */
1108                 drv_data->transfer_handler = interrupt_transfer;
1109 
1110                 /* Clear status  */
1111                 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1112                 write_SSSR_CS(drv_data, drv_data->clear_sr);
1113         }
1114 
1115         /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
1116         cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1117         if (!pxa25x_ssp_comp(drv_data))
1118                 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1119                         master->max_speed_hz
1120                                 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1121                         dma_mapped ? "DMA" : "PIO");
1122         else
1123                 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1124                         master->max_speed_hz / 2
1125                                 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1126                         dma_mapped ? "DMA" : "PIO");
1127 
1128         if (is_lpss_ssp(drv_data)) {
1129                 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1130                     != chip->lpss_rx_threshold)
1131                         pxa2xx_spi_write(drv_data, SSIRF,
1132                                          chip->lpss_rx_threshold);
1133                 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1134                     != chip->lpss_tx_threshold)
1135                         pxa2xx_spi_write(drv_data, SSITF,
1136                                          chip->lpss_tx_threshold);
1137         }
1138 
1139         if (is_quark_x1000_ssp(drv_data) &&
1140             (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1141                 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1142 
1143         /* see if we need to reload the config registers */
1144         if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1145             || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1146             != (cr1 & change_mask)) {
1147                 /* stop the SSP, and update the other bits */
1148                 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1149                 if (!pxa25x_ssp_comp(drv_data))
1150                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1151                 /* first set CR1 without interrupt and service enables */
1152                 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1153                 /* restart the SSP */
1154                 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1155 
1156         } else {
1157                 if (!pxa25x_ssp_comp(drv_data))
1158                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1159         }
1160 
1161         cs_assert(drv_data);
1162 
1163         /* after chip select, release the data by enabling service
1164          * requests and interrupts, without changing any mode bits */
1165         pxa2xx_spi_write(drv_data, SSCR1, cr1);
1166 }
1167 
1168 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
1169                                            struct spi_message *msg)
1170 {
1171         struct driver_data *drv_data = spi_master_get_devdata(master);
1172 
1173         /* Initial message state*/
1174         msg->state = START_STATE;
1175         drv_data->cur_transfer = list_entry(msg->transfers.next,
1176                                                 struct spi_transfer,
1177                                                 transfer_list);
1178 
1179         /* Mark as busy and launch transfers */
1180         tasklet_schedule(&drv_data->pump_transfers);
1181         return 0;
1182 }
1183 
1184 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1185 {
1186         struct driver_data *drv_data = spi_master_get_devdata(master);
1187 
1188         /* Disable the SSP now */
1189         pxa2xx_spi_write(drv_data, SSCR0,
1190                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1191 
1192         return 0;
1193 }
1194 
1195 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1196                     struct pxa2xx_spi_chip *chip_info)
1197 {
1198         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1199         int err = 0;
1200 
1201         if (chip == NULL)
1202                 return 0;
1203 
1204         if (drv_data->cs_gpiods) {
1205                 struct gpio_desc *gpiod;
1206 
1207                 gpiod = drv_data->cs_gpiods[spi->chip_select];
1208                 if (gpiod) {
1209                         chip->gpio_cs = desc_to_gpio(gpiod);
1210                         chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1211                         gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1212                 }
1213 
1214                 return 0;
1215         }
1216 
1217         if (chip_info == NULL)
1218                 return 0;
1219 
1220         /* NOTE: setup() can be called multiple times, possibly with
1221          * different chip_info, release previously requested GPIO
1222          */
1223         if (gpio_is_valid(chip->gpio_cs))
1224                 gpio_free(chip->gpio_cs);
1225 
1226         /* If (*cs_control) is provided, ignore GPIO chip select */
1227         if (chip_info->cs_control) {
1228                 chip->cs_control = chip_info->cs_control;
1229                 return 0;
1230         }
1231 
1232         if (gpio_is_valid(chip_info->gpio_cs)) {
1233                 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1234                 if (err) {
1235                         dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1236                                 chip_info->gpio_cs);
1237                         return err;
1238                 }
1239 
1240                 chip->gpio_cs = chip_info->gpio_cs;
1241                 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1242 
1243                 err = gpio_direction_output(chip->gpio_cs,
1244                                         !chip->gpio_cs_inverted);
1245         }
1246 
1247         return err;
1248 }
1249 
1250 static int setup(struct spi_device *spi)
1251 {
1252         struct pxa2xx_spi_chip *chip_info;
1253         struct chip_data *chip;
1254         const struct lpss_config *config;
1255         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1256         uint tx_thres, tx_hi_thres, rx_thres;
1257 
1258         switch (drv_data->ssp_type) {
1259         case QUARK_X1000_SSP:
1260                 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1261                 tx_hi_thres = 0;
1262                 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1263                 break;
1264         case CE4100_SSP:
1265                 tx_thres = TX_THRESH_CE4100_DFLT;
1266                 tx_hi_thres = 0;
1267                 rx_thres = RX_THRESH_CE4100_DFLT;
1268                 break;
1269         case LPSS_LPT_SSP:
1270         case LPSS_BYT_SSP:
1271         case LPSS_BSW_SSP:
1272         case LPSS_SPT_SSP:
1273         case LPSS_BXT_SSP:
1274                 config = lpss_get_config(drv_data);
1275                 tx_thres = config->tx_threshold_lo;
1276                 tx_hi_thres = config->tx_threshold_hi;
1277                 rx_thres = config->rx_threshold;
1278                 break;
1279         default:
1280                 tx_thres = TX_THRESH_DFLT;
1281                 tx_hi_thres = 0;
1282                 rx_thres = RX_THRESH_DFLT;
1283                 break;
1284         }
1285 
1286         /* Only alloc on first setup */
1287         chip = spi_get_ctldata(spi);
1288         if (!chip) {
1289                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1290                 if (!chip)
1291                         return -ENOMEM;
1292 
1293                 if (drv_data->ssp_type == CE4100_SSP) {
1294                         if (spi->chip_select > 4) {
1295                                 dev_err(&spi->dev,
1296                                         "failed setup: cs number must not be > 4.\n");
1297                                 kfree(chip);
1298                                 return -EINVAL;
1299                         }
1300 
1301                         chip->frm = spi->chip_select;
1302                 } else
1303                         chip->gpio_cs = -1;
1304                 chip->enable_dma = drv_data->master_info->enable_dma;
1305                 chip->timeout = TIMOUT_DFLT;
1306         }
1307 
1308         /* protocol drivers may change the chip settings, so...
1309          * if chip_info exists, use it */
1310         chip_info = spi->controller_data;
1311 
1312         /* chip_info isn't always needed */
1313         chip->cr1 = 0;
1314         if (chip_info) {
1315                 if (chip_info->timeout)
1316                         chip->timeout = chip_info->timeout;
1317                 if (chip_info->tx_threshold)
1318                         tx_thres = chip_info->tx_threshold;
1319                 if (chip_info->tx_hi_threshold)
1320                         tx_hi_thres = chip_info->tx_hi_threshold;
1321                 if (chip_info->rx_threshold)
1322                         rx_thres = chip_info->rx_threshold;
1323                 chip->dma_threshold = 0;
1324                 if (chip_info->enable_loopback)
1325                         chip->cr1 = SSCR1_LBM;
1326         }
1327 
1328         chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1329         chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1330                                 | SSITF_TxHiThresh(tx_hi_thres);
1331 
1332         /* set dma burst and threshold outside of chip_info path so that if
1333          * chip_info goes away after setting chip->enable_dma, the
1334          * burst and threshold can still respond to changes in bits_per_word */
1335         if (chip->enable_dma) {
1336                 /* set up legal burst and threshold for dma */
1337                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1338                                                 spi->bits_per_word,
1339                                                 &chip->dma_burst_size,
1340                                                 &chip->dma_threshold)) {
1341                         dev_warn(&spi->dev,
1342                                  "in setup: DMA burst size reduced to match bits_per_word\n");
1343                 }
1344         }
1345 
1346         switch (drv_data->ssp_type) {
1347         case QUARK_X1000_SSP:
1348                 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1349                                    & QUARK_X1000_SSCR1_RFT)
1350                                    | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1351                                    & QUARK_X1000_SSCR1_TFT);
1352                 break;
1353         case CE4100_SSP:
1354                 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1355                         (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1356                 break;
1357         default:
1358                 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1359                         (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1360                 break;
1361         }
1362 
1363         chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1364         chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1365                         | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1366 
1367         if (spi->mode & SPI_LOOP)
1368                 chip->cr1 |= SSCR1_LBM;
1369 
1370         if (spi->bits_per_word <= 8) {
1371                 chip->n_bytes = 1;
1372                 chip->read = u8_reader;
1373                 chip->write = u8_writer;
1374         } else if (spi->bits_per_word <= 16) {
1375                 chip->n_bytes = 2;
1376                 chip->read = u16_reader;
1377                 chip->write = u16_writer;
1378         } else if (spi->bits_per_word <= 32) {
1379                 chip->n_bytes = 4;
1380                 chip->read = u32_reader;
1381                 chip->write = u32_writer;
1382         }
1383 
1384         spi_set_ctldata(spi, chip);
1385 
1386         if (drv_data->ssp_type == CE4100_SSP)
1387                 return 0;
1388 
1389         return setup_cs(spi, chip, chip_info);
1390 }
1391 
1392 static void cleanup(struct spi_device *spi)
1393 {
1394         struct chip_data *chip = spi_get_ctldata(spi);
1395         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1396 
1397         if (!chip)
1398                 return;
1399 
1400         if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1401             gpio_is_valid(chip->gpio_cs))
1402                 gpio_free(chip->gpio_cs);
1403 
1404         kfree(chip);
1405 }
1406 
1407 #ifdef CONFIG_PCI
1408 #ifdef CONFIG_ACPI
1409 
1410 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1411         { "INT33C0", LPSS_LPT_SSP },
1412         { "INT33C1", LPSS_LPT_SSP },
1413         { "INT3430", LPSS_LPT_SSP },
1414         { "INT3431", LPSS_LPT_SSP },
1415         { "80860F0E", LPSS_BYT_SSP },
1416         { "8086228E", LPSS_BSW_SSP },
1417         { },
1418 };
1419 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1420 
1421 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1422 {
1423         unsigned int devid;
1424         int port_id = -1;
1425 
1426         if (adev && adev->pnp.unique_id &&
1427             !kstrtouint(adev->pnp.unique_id, 0, &devid))
1428                 port_id = devid;
1429         return port_id;
1430 }
1431 #else /* !CONFIG_ACPI */
1432 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1433 {
1434         return -1;
1435 }
1436 #endif
1437 
1438 /*
1439  * PCI IDs of compound devices that integrate both host controller and private
1440  * integrated DMA engine. Please note these are not used in module
1441  * autoloading and probing in this module but matching the LPSS SSP type.
1442  */
1443 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1444         /* SPT-LP */
1445         { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1446         { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1447         /* SPT-H */
1448         { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1449         { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1450         /* KBL-H */
1451         { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1452         { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1453         /* BXT A-Step */
1454         { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1455         { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1456         { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1457         /* BXT B-Step */
1458         { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1459         { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1460         { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1461         /* APL */
1462         { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1463         { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1464         { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1465         { },
1466 };
1467 
1468 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1469 {
1470         struct device *dev = param;
1471 
1472         if (dev != chan->device->dev->parent)
1473                 return false;
1474 
1475         return true;
1476 }
1477 
1478 static struct pxa2xx_spi_master *
1479 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1480 {
1481         struct pxa2xx_spi_master *pdata;
1482         struct acpi_device *adev;
1483         struct ssp_device *ssp;
1484         struct resource *res;
1485         const struct acpi_device_id *adev_id = NULL;
1486         const struct pci_device_id *pcidev_id = NULL;
1487         int type;
1488 
1489         adev = ACPI_COMPANION(&pdev->dev);
1490 
1491         if (dev_is_pci(pdev->dev.parent))
1492                 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1493                                          to_pci_dev(pdev->dev.parent));
1494         else if (adev)
1495                 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1496                                             &pdev->dev);
1497         else
1498                 return NULL;
1499 
1500         if (adev_id)
1501                 type = (int)adev_id->driver_data;
1502         else if (pcidev_id)
1503                 type = (int)pcidev_id->driver_data;
1504         else
1505                 return NULL;
1506 
1507         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1508         if (!pdata)
1509                 return NULL;
1510 
1511         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1512         if (!res)
1513                 return NULL;
1514 
1515         ssp = &pdata->ssp;
1516 
1517         ssp->phys_base = res->start;
1518         ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1519         if (IS_ERR(ssp->mmio_base))
1520                 return NULL;
1521 
1522         if (pcidev_id) {
1523                 pdata->tx_param = pdev->dev.parent;
1524                 pdata->rx_param = pdev->dev.parent;
1525                 pdata->dma_filter = pxa2xx_spi_idma_filter;
1526         }
1527 
1528         ssp->clk = devm_clk_get(&pdev->dev, NULL);
1529         ssp->irq = platform_get_irq(pdev, 0);
1530         ssp->type = type;
1531         ssp->pdev = pdev;
1532         ssp->port_id = pxa2xx_spi_get_port_id(adev);
1533 
1534         pdata->num_chipselect = 1;
1535         pdata->enable_dma = true;
1536 
1537         return pdata;
1538 }
1539 
1540 #else /* !CONFIG_PCI */
1541 static inline struct pxa2xx_spi_master *
1542 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1543 {
1544         return NULL;
1545 }
1546 #endif
1547 
1548 static int pxa2xx_spi_fw_translate_cs(struct spi_master *master, unsigned cs)
1549 {
1550         struct driver_data *drv_data = spi_master_get_devdata(master);
1551 
1552         if (has_acpi_companion(&drv_data->pdev->dev)) {
1553                 switch (drv_data->ssp_type) {
1554                 /*
1555                  * For Atoms the ACPI DeviceSelection used by the Windows
1556                  * driver starts from 1 instead of 0 so translate it here
1557                  * to match what Linux expects.
1558                  */
1559                 case LPSS_BYT_SSP:
1560                 case LPSS_BSW_SSP:
1561                         return cs - 1;
1562 
1563                 default:
1564                         break;
1565                 }
1566         }
1567 
1568         return cs;
1569 }
1570 
1571 static int pxa2xx_spi_probe(struct platform_device *pdev)
1572 {
1573         struct device *dev = &pdev->dev;
1574         struct pxa2xx_spi_master *platform_info;
1575         struct spi_master *master;
1576         struct driver_data *drv_data;
1577         struct ssp_device *ssp;
1578         const struct lpss_config *config;
1579         int status, count;
1580         u32 tmp;
1581 
1582         platform_info = dev_get_platdata(dev);
1583         if (!platform_info) {
1584                 platform_info = pxa2xx_spi_init_pdata(pdev);
1585                 if (!platform_info) {
1586                         dev_err(&pdev->dev, "missing platform data\n");
1587                         return -ENODEV;
1588                 }
1589         }
1590 
1591         ssp = pxa_ssp_request(pdev->id, pdev->name);
1592         if (!ssp)
1593                 ssp = &platform_info->ssp;
1594 
1595         if (!ssp->mmio_base) {
1596                 dev_err(&pdev->dev, "failed to get ssp\n");
1597                 return -ENODEV;
1598         }
1599 
1600         master = spi_alloc_master(dev, sizeof(struct driver_data));
1601         if (!master) {
1602                 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1603                 pxa_ssp_free(ssp);
1604                 return -ENOMEM;
1605         }
1606         drv_data = spi_master_get_devdata(master);
1607         drv_data->master = master;
1608         drv_data->master_info = platform_info;
1609         drv_data->pdev = pdev;
1610         drv_data->ssp = ssp;
1611 
1612         master->dev.of_node = pdev->dev.of_node;
1613         /* the spi->mode bits understood by this driver: */
1614         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1615 
1616         master->bus_num = ssp->port_id;
1617         master->dma_alignment = DMA_ALIGNMENT;
1618         master->cleanup = cleanup;
1619         master->setup = setup;
1620         master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1621         master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1622         master->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1623         master->auto_runtime_pm = true;
1624         master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
1625 
1626         drv_data->ssp_type = ssp->type;
1627 
1628         drv_data->ioaddr = ssp->mmio_base;
1629         drv_data->ssdr_physical = ssp->phys_base + SSDR;
1630         if (pxa25x_ssp_comp(drv_data)) {
1631                 switch (drv_data->ssp_type) {
1632                 case QUARK_X1000_SSP:
1633                         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1634                         break;
1635                 default:
1636                         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1637                         break;
1638                 }
1639 
1640                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1641                 drv_data->dma_cr1 = 0;
1642                 drv_data->clear_sr = SSSR_ROR;
1643                 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1644         } else {
1645                 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1646                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1647                 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1648                 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1649                 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1650         }
1651 
1652         status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1653                         drv_data);
1654         if (status < 0) {
1655                 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1656                 goto out_error_master_alloc;
1657         }
1658 
1659         /* Setup DMA if requested */
1660         if (platform_info->enable_dma) {
1661                 status = pxa2xx_spi_dma_setup(drv_data);
1662                 if (status) {
1663                         dev_dbg(dev, "no DMA channels available, using PIO\n");
1664                         platform_info->enable_dma = false;
1665                 } else {
1666                         master->can_dma = pxa2xx_spi_can_dma;
1667                 }
1668         }
1669 
1670         /* Enable SOC clock */
1671         clk_prepare_enable(ssp->clk);
1672 
1673         master->max_speed_hz = clk_get_rate(ssp->clk);
1674 
1675         /* Load default SSP configuration */
1676         pxa2xx_spi_write(drv_data, SSCR0, 0);
1677         switch (drv_data->ssp_type) {
1678         case QUARK_X1000_SSP:
1679                 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1680                       QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1681                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1682 
1683                 /* using the Motorola SPI protocol and use 8 bit frame */
1684                 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1685                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1686                 break;
1687         case CE4100_SSP:
1688                 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1689                       CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1690                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1691                 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1692                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1693                 break;
1694         default:
1695                 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1696                       SSCR1_TxTresh(TX_THRESH_DFLT);
1697                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1698                 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1699                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1700                 break;
1701         }
1702 
1703         if (!pxa25x_ssp_comp(drv_data))
1704                 pxa2xx_spi_write(drv_data, SSTO, 0);
1705 
1706         if (!is_quark_x1000_ssp(drv_data))
1707                 pxa2xx_spi_write(drv_data, SSPSP, 0);
1708 
1709         if (is_lpss_ssp(drv_data)) {
1710                 lpss_ssp_setup(drv_data);
1711                 config = lpss_get_config(drv_data);
1712                 if (config->reg_capabilities >= 0) {
1713                         tmp = __lpss_ssp_read_priv(drv_data,
1714                                                    config->reg_capabilities);
1715                         tmp &= LPSS_CAPS_CS_EN_MASK;
1716                         tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1717                         platform_info->num_chipselect = ffz(tmp);
1718                 } else if (config->cs_num) {
1719                         platform_info->num_chipselect = config->cs_num;
1720                 }
1721         }
1722         master->num_chipselect = platform_info->num_chipselect;
1723 
1724         count = gpiod_count(&pdev->dev, "cs");
1725         if (count > 0) {
1726                 int i;
1727 
1728                 master->num_chipselect = max_t(int, count,
1729                         master->num_chipselect);
1730 
1731                 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1732                         master->num_chipselect, sizeof(struct gpio_desc *),
1733                         GFP_KERNEL);
1734                 if (!drv_data->cs_gpiods) {
1735                         status = -ENOMEM;
1736                         goto out_error_clock_enabled;
1737                 }
1738 
1739                 for (i = 0; i < master->num_chipselect; i++) {
1740                         struct gpio_desc *gpiod;
1741 
1742                         gpiod = devm_gpiod_get_index(dev, "cs", i,
1743                                                      GPIOD_OUT_HIGH);
1744                         if (IS_ERR(gpiod)) {
1745                                 /* Means use native chip select */
1746                                 if (PTR_ERR(gpiod) == -ENOENT)
1747                                         continue;
1748 
1749                                 status = (int)PTR_ERR(gpiod);
1750                                 goto out_error_clock_enabled;
1751                         } else {
1752                                 drv_data->cs_gpiods[i] = gpiod;
1753                         }
1754                 }
1755         }
1756 
1757         tasklet_init(&drv_data->pump_transfers, pump_transfers,
1758                      (unsigned long)drv_data);
1759 
1760         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1761         pm_runtime_use_autosuspend(&pdev->dev);
1762         pm_runtime_set_active(&pdev->dev);
1763         pm_runtime_enable(&pdev->dev);
1764 
1765         /* Register with the SPI framework */
1766         platform_set_drvdata(pdev, drv_data);
1767         status = devm_spi_register_master(&pdev->dev, master);
1768         if (status != 0) {
1769                 dev_err(&pdev->dev, "problem registering spi master\n");
1770                 goto out_error_clock_enabled;
1771         }
1772 
1773         return status;
1774 
1775 out_error_clock_enabled:
1776         clk_disable_unprepare(ssp->clk);
1777         pxa2xx_spi_dma_release(drv_data);
1778         free_irq(ssp->irq, drv_data);
1779 
1780 out_error_master_alloc:
1781         spi_master_put(master);
1782         pxa_ssp_free(ssp);
1783         return status;
1784 }
1785 
1786 static int pxa2xx_spi_remove(struct platform_device *pdev)
1787 {
1788         struct driver_data *drv_data = platform_get_drvdata(pdev);
1789         struct ssp_device *ssp;
1790 
1791         if (!drv_data)
1792                 return 0;
1793         ssp = drv_data->ssp;
1794 
1795         pm_runtime_get_sync(&pdev->dev);
1796 
1797         /* Disable the SSP at the peripheral and SOC level */
1798         pxa2xx_spi_write(drv_data, SSCR0, 0);
1799         clk_disable_unprepare(ssp->clk);
1800 
1801         /* Release DMA */
1802         if (drv_data->master_info->enable_dma)
1803                 pxa2xx_spi_dma_release(drv_data);
1804 
1805         pm_runtime_put_noidle(&pdev->dev);
1806         pm_runtime_disable(&pdev->dev);
1807 
1808         /* Release IRQ */
1809         free_irq(ssp->irq, drv_data);
1810 
1811         /* Release SSP */
1812         pxa_ssp_free(ssp);
1813 
1814         return 0;
1815 }
1816 
1817 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1818 {
1819         int status = 0;
1820 
1821         if ((status = pxa2xx_spi_remove(pdev)) != 0)
1822                 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1823 }
1824 
1825 #ifdef CONFIG_PM_SLEEP
1826 static int pxa2xx_spi_suspend(struct device *dev)
1827 {
1828         struct driver_data *drv_data = dev_get_drvdata(dev);
1829         struct ssp_device *ssp = drv_data->ssp;
1830         int status;
1831 
1832         status = spi_master_suspend(drv_data->master);
1833         if (status != 0)
1834                 return status;
1835         pxa2xx_spi_write(drv_data, SSCR0, 0);
1836 
1837         if (!pm_runtime_suspended(dev))
1838                 clk_disable_unprepare(ssp->clk);
1839 
1840         return 0;
1841 }
1842 
1843 static int pxa2xx_spi_resume(struct device *dev)
1844 {
1845         struct driver_data *drv_data = dev_get_drvdata(dev);
1846         struct ssp_device *ssp = drv_data->ssp;
1847         int status;
1848 
1849         /* Enable the SSP clock */
1850         if (!pm_runtime_suspended(dev))
1851                 clk_prepare_enable(ssp->clk);
1852 
1853         /* Restore LPSS private register bits */
1854         if (is_lpss_ssp(drv_data))
1855                 lpss_ssp_setup(drv_data);
1856 
1857         /* Start the queue running */
1858         status = spi_master_resume(drv_data->master);
1859         if (status != 0) {
1860                 dev_err(dev, "problem starting queue (%d)\n", status);
1861                 return status;
1862         }
1863 
1864         return 0;
1865 }
1866 #endif
1867 
1868 #ifdef CONFIG_PM
1869 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1870 {
1871         struct driver_data *drv_data = dev_get_drvdata(dev);
1872 
1873         clk_disable_unprepare(drv_data->ssp->clk);
1874         return 0;
1875 }
1876 
1877 static int pxa2xx_spi_runtime_resume(struct device *dev)
1878 {
1879         struct driver_data *drv_data = dev_get_drvdata(dev);
1880 
1881         clk_prepare_enable(drv_data->ssp->clk);
1882         return 0;
1883 }
1884 #endif
1885 
1886 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1887         SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1888         SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1889                            pxa2xx_spi_runtime_resume, NULL)
1890 };
1891 
1892 static struct platform_driver driver = {
1893         .driver = {
1894                 .name   = "pxa2xx-spi",
1895                 .pm     = &pxa2xx_spi_pm_ops,
1896                 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1897         },
1898         .probe = pxa2xx_spi_probe,
1899         .remove = pxa2xx_spi_remove,
1900         .shutdown = pxa2xx_spi_shutdown,
1901 };
1902 
1903 static int __init pxa2xx_spi_init(void)
1904 {
1905         return platform_driver_register(&driver);
1906 }
1907 subsys_initcall(pxa2xx_spi_init);
1908 
1909 static void __exit pxa2xx_spi_exit(void)
1910 {
1911         platform_driver_unregister(&driver);
1912 }
1913 module_exit(pxa2xx_spi_exit);
1914 

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