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Linux/drivers/spi/spi-ppc4xx.c

  1 /*
  2  * SPI_PPC4XX SPI controller driver.
  3  *
  4  * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
  5  * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
  6  * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
  7  *
  8  * Based in part on drivers/spi/spi_s3c24xx.c
  9  *
 10  * Copyright (c) 2006 Ben Dooks
 11  * Copyright (c) 2006 Simtec Electronics
 12  *      Ben Dooks <ben@simtec.co.uk>
 13  *
 14  * This program is free software; you can redistribute  it and/or modify it
 15  * under the terms of the GNU General Public License version 2 as published
 16  * by the Free Software Foundation.
 17  */
 18 
 19 /*
 20  * The PPC4xx SPI controller has no FIFO so each sent/received byte will
 21  * generate an interrupt to the CPU. This can cause high CPU utilization.
 22  * This driver allows platforms to reduce the interrupt load on the CPU
 23  * during SPI transfers by setting max_speed_hz via the device tree.
 24  */
 25 
 26 #include <linux/module.h>
 27 #include <linux/sched.h>
 28 #include <linux/slab.h>
 29 #include <linux/errno.h>
 30 #include <linux/wait.h>
 31 #include <linux/of_address.h>
 32 #include <linux/of_irq.h>
 33 #include <linux/of_platform.h>
 34 #include <linux/of_gpio.h>
 35 #include <linux/interrupt.h>
 36 #include <linux/delay.h>
 37 
 38 #include <linux/gpio.h>
 39 #include <linux/spi/spi.h>
 40 #include <linux/spi/spi_bitbang.h>
 41 
 42 #include <asm/io.h>
 43 #include <asm/dcr.h>
 44 #include <asm/dcr-regs.h>
 45 
 46 /* bits in mode register - bit 0 is MSb */
 47 
 48 /*
 49  * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
 50  * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
 51  * Note: This is the inverse of CPHA.
 52  */
 53 #define SPI_PPC4XX_MODE_SCP     (0x80 >> 3)
 54 
 55 /* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
 56 #define SPI_PPC4XX_MODE_SPE     (0x80 >> 4)
 57 
 58 /*
 59  * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
 60  * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
 61  * Note: This is identical to SPI_LSB_FIRST.
 62  */
 63 #define SPI_PPC4XX_MODE_RD      (0x80 >> 5)
 64 
 65 /*
 66  * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
 67  * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
 68  * Note: This is identical to CPOL.
 69  */
 70 #define SPI_PPC4XX_MODE_CI      (0x80 >> 6)
 71 
 72 /*
 73  * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
 74  * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
 75  */
 76 #define SPI_PPC4XX_MODE_IL      (0x80 >> 7)
 77 
 78 /* bits in control register */
 79 /* starts a transfer when set */
 80 #define SPI_PPC4XX_CR_STR       (0x80 >> 7)
 81 
 82 /* bits in status register */
 83 /* port is busy with a transfer */
 84 #define SPI_PPC4XX_SR_BSY       (0x80 >> 6)
 85 /* RxD ready */
 86 #define SPI_PPC4XX_SR_RBR       (0x80 >> 7)
 87 
 88 /* clock settings (SCP and CI) for various SPI modes */
 89 #define SPI_CLK_MODE0   (SPI_PPC4XX_MODE_SCP | 0)
 90 #define SPI_CLK_MODE1   (0 | 0)
 91 #define SPI_CLK_MODE2   (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
 92 #define SPI_CLK_MODE3   (0 | SPI_PPC4XX_MODE_CI)
 93 
 94 #define DRIVER_NAME     "spi_ppc4xx_of"
 95 
 96 struct spi_ppc4xx_regs {
 97         u8 mode;
 98         u8 rxd;
 99         u8 txd;
100         u8 cr;
101         u8 sr;
102         u8 dummy;
103         /*
104          * Clock divisor modulus register
105          * This uses the following formula:
106          *    SCPClkOut = OPBCLK/(4(CDM + 1))
107          * or
108          *    CDM = (OPBCLK/4*SCPClkOut) - 1
109          * bit 0 is the MSb!
110          */
111         u8 cdm;
112 };
113 
114 /* SPI Controller driver's private data. */
115 struct ppc4xx_spi {
116         /* bitbang has to be first */
117         struct spi_bitbang bitbang;
118         struct completion done;
119 
120         u64 mapbase;
121         u64 mapsize;
122         int irqnum;
123         /* need this to set the SPI clock */
124         unsigned int opb_freq;
125 
126         /* for transfers */
127         int len;
128         int count;
129         /* data buffers */
130         const unsigned char *tx;
131         unsigned char *rx;
132 
133         int *gpios;
134 
135         struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
136         struct spi_master *master;
137         struct device *dev;
138 };
139 
140 /* need this so we can set the clock in the chipselect routine */
141 struct spi_ppc4xx_cs {
142         u8 mode;
143 };
144 
145 static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
146 {
147         struct ppc4xx_spi *hw;
148         u8 data;
149 
150         dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
151                 t->tx_buf, t->rx_buf, t->len);
152 
153         hw = spi_master_get_devdata(spi->master);
154 
155         hw->tx = t->tx_buf;
156         hw->rx = t->rx_buf;
157         hw->len = t->len;
158         hw->count = 0;
159 
160         /* send the first byte */
161         data = hw->tx ? hw->tx[0] : 0;
162         out_8(&hw->regs->txd, data);
163         out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
164         wait_for_completion(&hw->done);
165 
166         return hw->count;
167 }
168 
169 static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
170 {
171         struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
172         struct spi_ppc4xx_cs *cs = spi->controller_state;
173         int scr;
174         u8 cdm = 0;
175         u32 speed;
176         u8 bits_per_word;
177 
178         /* Start with the generic configuration for this device. */
179         bits_per_word = spi->bits_per_word;
180         speed = spi->max_speed_hz;
181 
182         /*
183          * Modify the configuration if the transfer overrides it.  Do not allow
184          * the transfer to overwrite the generic configuration with zeros.
185          */
186         if (t) {
187                 if (t->bits_per_word)
188                         bits_per_word = t->bits_per_word;
189 
190                 if (t->speed_hz)
191                         speed = min(t->speed_hz, spi->max_speed_hz);
192         }
193 
194         if (!speed || (speed > spi->max_speed_hz)) {
195                 dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
196                 return -EINVAL;
197         }
198 
199         /* Write new configuration */
200         out_8(&hw->regs->mode, cs->mode);
201 
202         /* Set the clock */
203         /* opb_freq was already divided by 4 */
204         scr = (hw->opb_freq / speed) - 1;
205         if (scr > 0)
206                 cdm = min(scr, 0xff);
207 
208         dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
209 
210         if (in_8(&hw->regs->cdm) != cdm)
211                 out_8(&hw->regs->cdm, cdm);
212 
213         spin_lock(&hw->bitbang.lock);
214         if (!hw->bitbang.busy) {
215                 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
216                 /* Need to ndelay here? */
217         }
218         spin_unlock(&hw->bitbang.lock);
219 
220         return 0;
221 }
222 
223 static int spi_ppc4xx_setup(struct spi_device *spi)
224 {
225         struct spi_ppc4xx_cs *cs = spi->controller_state;
226 
227         if (!spi->max_speed_hz) {
228                 dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
229                 return -EINVAL;
230         }
231 
232         if (cs == NULL) {
233                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
234                 if (!cs)
235                         return -ENOMEM;
236                 spi->controller_state = cs;
237         }
238 
239         /*
240          * We set all bits of the SPI0_MODE register, so,
241          * no need to read-modify-write
242          */
243         cs->mode = SPI_PPC4XX_MODE_SPE;
244 
245         switch (spi->mode & (SPI_CPHA | SPI_CPOL)) {
246         case SPI_MODE_0:
247                 cs->mode |= SPI_CLK_MODE0;
248                 break;
249         case SPI_MODE_1:
250                 cs->mode |= SPI_CLK_MODE1;
251                 break;
252         case SPI_MODE_2:
253                 cs->mode |= SPI_CLK_MODE2;
254                 break;
255         case SPI_MODE_3:
256                 cs->mode |= SPI_CLK_MODE3;
257                 break;
258         }
259 
260         if (spi->mode & SPI_LSB_FIRST)
261                 cs->mode |= SPI_PPC4XX_MODE_RD;
262 
263         return 0;
264 }
265 
266 static void spi_ppc4xx_chipsel(struct spi_device *spi, int value)
267 {
268         struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
269         unsigned int cs = spi->chip_select;
270         unsigned int cspol;
271 
272         /*
273          * If there are no chip selects at all, or if this is the special
274          * case of a non-existent (dummy) chip select, do nothing.
275          */
276 
277         if (!hw->master->num_chipselect || hw->gpios[cs] == -EEXIST)
278                 return;
279 
280         cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
281         if (value == BITBANG_CS_INACTIVE)
282                 cspol = !cspol;
283 
284         gpio_set_value(hw->gpios[cs], cspol);
285 }
286 
287 static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
288 {
289         struct ppc4xx_spi *hw;
290         u8 status;
291         u8 data;
292         unsigned int count;
293 
294         hw = (struct ppc4xx_spi *)dev_id;
295 
296         status = in_8(&hw->regs->sr);
297         if (!status)
298                 return IRQ_NONE;
299 
300         /*
301          * BSY de-asserts one cycle after the transfer is complete.  The
302          * interrupt is asserted after the transfer is complete.  The exact
303          * relationship is not documented, hence this code.
304          */
305 
306         if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
307                 u8 lstatus;
308                 int cnt = 0;
309 
310                 dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
311                 do {
312                         ndelay(10);
313                         lstatus = in_8(&hw->regs->sr);
314                 } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
315 
316                 if (cnt >= 100) {
317                         dev_err(hw->dev, "busywait: too many loops!\n");
318                         complete(&hw->done);
319                         return IRQ_HANDLED;
320                 } else {
321                         /* status is always 1 (RBR) here */
322                         status = in_8(&hw->regs->sr);
323                         dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
324                 }
325         }
326 
327         count = hw->count;
328         hw->count++;
329 
330         /* RBR triggered this interrupt.  Therefore, data must be ready. */
331         data = in_8(&hw->regs->rxd);
332         if (hw->rx)
333                 hw->rx[count] = data;
334 
335         count++;
336 
337         if (count < hw->len) {
338                 data = hw->tx ? hw->tx[count] : 0;
339                 out_8(&hw->regs->txd, data);
340                 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
341         } else {
342                 complete(&hw->done);
343         }
344 
345         return IRQ_HANDLED;
346 }
347 
348 static void spi_ppc4xx_cleanup(struct spi_device *spi)
349 {
350         kfree(spi->controller_state);
351 }
352 
353 static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
354 {
355         /*
356          * On all 4xx PPC's the SPI bus is shared/multiplexed with
357          * the 2nd I2C bus. We need to enable the the SPI bus before
358          * using it.
359          */
360 
361         /* need to clear bit 14 to enable SPC */
362         dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
363 }
364 
365 static void free_gpios(struct ppc4xx_spi *hw)
366 {
367         if (hw->master->num_chipselect) {
368                 int i;
369                 for (i = 0; i < hw->master->num_chipselect; i++)
370                         if (gpio_is_valid(hw->gpios[i]))
371                                 gpio_free(hw->gpios[i]);
372 
373                 kfree(hw->gpios);
374                 hw->gpios = NULL;
375         }
376 }
377 
378 /*
379  * platform_device layer stuff...
380  */
381 static int spi_ppc4xx_of_probe(struct platform_device *op)
382 {
383         struct ppc4xx_spi *hw;
384         struct spi_master *master;
385         struct spi_bitbang *bbp;
386         struct resource resource;
387         struct device_node *np = op->dev.of_node;
388         struct device *dev = &op->dev;
389         struct device_node *opbnp;
390         int ret;
391         int num_gpios;
392         const unsigned int *clk;
393 
394         master = spi_alloc_master(dev, sizeof *hw);
395         if (master == NULL)
396                 return -ENOMEM;
397         master->dev.of_node = np;
398         platform_set_drvdata(op, master);
399         hw = spi_master_get_devdata(master);
400         hw->master = master;
401         hw->dev = dev;
402 
403         init_completion(&hw->done);
404 
405         /*
406          * A count of zero implies a single SPI device without any chip-select.
407          * Note that of_gpio_count counts all gpios assigned to this spi master.
408          * This includes both "null" gpio's and real ones.
409          */
410         num_gpios = of_gpio_count(np);
411         if (num_gpios > 0) {
412                 int i;
413 
414                 hw->gpios = kzalloc(sizeof(int) * num_gpios, GFP_KERNEL);
415                 if (!hw->gpios) {
416                         ret = -ENOMEM;
417                         goto free_master;
418                 }
419 
420                 for (i = 0; i < num_gpios; i++) {
421                         int gpio;
422                         enum of_gpio_flags flags;
423 
424                         gpio = of_get_gpio_flags(np, i, &flags);
425                         hw->gpios[i] = gpio;
426 
427                         if (gpio_is_valid(gpio)) {
428                                 /* Real CS - set the initial state. */
429                                 ret = gpio_request(gpio, np->name);
430                                 if (ret < 0) {
431                                         dev_err(dev, "can't request gpio "
432                                                         "#%d: %d\n", i, ret);
433                                         goto free_gpios;
434                                 }
435 
436                                 gpio_direction_output(gpio,
437                                                 !!(flags & OF_GPIO_ACTIVE_LOW));
438                         } else if (gpio == -EEXIST) {
439                                 ; /* No CS, but that's OK. */
440                         } else {
441                                 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
442                                 ret = -EINVAL;
443                                 goto free_gpios;
444                         }
445                 }
446         }
447 
448         /* Setup the state for the bitbang driver */
449         bbp = &hw->bitbang;
450         bbp->master = hw->master;
451         bbp->setup_transfer = spi_ppc4xx_setupxfer;
452         bbp->chipselect = spi_ppc4xx_chipsel;
453         bbp->txrx_bufs = spi_ppc4xx_txrx;
454         bbp->use_dma = 0;
455         bbp->master->setup = spi_ppc4xx_setup;
456         bbp->master->cleanup = spi_ppc4xx_cleanup;
457         bbp->master->bits_per_word_mask = SPI_BPW_MASK(8);
458 
459         /* the spi->mode bits understood by this driver: */
460         bbp->master->mode_bits =
461                 SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
462 
463         /* this many pins in all GPIO controllers */
464         bbp->master->num_chipselect = num_gpios > 0 ? num_gpios : 0;
465 
466         /* Get the clock for the OPB */
467         opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
468         if (opbnp == NULL) {
469                 dev_err(dev, "OPB: cannot find node\n");
470                 ret = -ENODEV;
471                 goto free_gpios;
472         }
473         /* Get the clock (Hz) for the OPB */
474         clk = of_get_property(opbnp, "clock-frequency", NULL);
475         if (clk == NULL) {
476                 dev_err(dev, "OPB: no clock-frequency property set\n");
477                 of_node_put(opbnp);
478                 ret = -ENODEV;
479                 goto free_gpios;
480         }
481         hw->opb_freq = *clk;
482         hw->opb_freq >>= 2;
483         of_node_put(opbnp);
484 
485         ret = of_address_to_resource(np, 0, &resource);
486         if (ret) {
487                 dev_err(dev, "error while parsing device node resource\n");
488                 goto free_gpios;
489         }
490         hw->mapbase = resource.start;
491         hw->mapsize = resource_size(&resource);
492 
493         /* Sanity check */
494         if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
495                 dev_err(dev, "too small to map registers\n");
496                 ret = -EINVAL;
497                 goto free_gpios;
498         }
499 
500         /* Request IRQ */
501         hw->irqnum = irq_of_parse_and_map(np, 0);
502         ret = request_irq(hw->irqnum, spi_ppc4xx_int,
503                           0, "spi_ppc4xx_of", (void *)hw);
504         if (ret) {
505                 dev_err(dev, "unable to allocate interrupt\n");
506                 goto free_gpios;
507         }
508 
509         if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
510                 dev_err(dev, "resource unavailable\n");
511                 ret = -EBUSY;
512                 goto request_mem_error;
513         }
514 
515         hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
516 
517         if (!hw->regs) {
518                 dev_err(dev, "unable to memory map registers\n");
519                 ret = -ENXIO;
520                 goto map_io_error;
521         }
522 
523         spi_ppc4xx_enable(hw);
524 
525         /* Finally register our spi controller */
526         dev->dma_mask = 0;
527         ret = spi_bitbang_start(bbp);
528         if (ret) {
529                 dev_err(dev, "failed to register SPI master\n");
530                 goto unmap_regs;
531         }
532 
533         dev_info(dev, "driver initialized\n");
534 
535         return 0;
536 
537 unmap_regs:
538         iounmap(hw->regs);
539 map_io_error:
540         release_mem_region(hw->mapbase, hw->mapsize);
541 request_mem_error:
542         free_irq(hw->irqnum, hw);
543 free_gpios:
544         free_gpios(hw);
545 free_master:
546         spi_master_put(master);
547 
548         dev_err(dev, "initialization failed\n");
549         return ret;
550 }
551 
552 static int spi_ppc4xx_of_remove(struct platform_device *op)
553 {
554         struct spi_master *master = platform_get_drvdata(op);
555         struct ppc4xx_spi *hw = spi_master_get_devdata(master);
556 
557         spi_bitbang_stop(&hw->bitbang);
558         release_mem_region(hw->mapbase, hw->mapsize);
559         free_irq(hw->irqnum, hw);
560         iounmap(hw->regs);
561         free_gpios(hw);
562         spi_master_put(master);
563         return 0;
564 }
565 
566 static const struct of_device_id spi_ppc4xx_of_match[] = {
567         { .compatible = "ibm,ppc4xx-spi", },
568         {},
569 };
570 
571 MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
572 
573 static struct platform_driver spi_ppc4xx_of_driver = {
574         .probe = spi_ppc4xx_of_probe,
575         .remove = spi_ppc4xx_of_remove,
576         .driver = {
577                 .name = DRIVER_NAME,
578                 .owner = THIS_MODULE,
579                 .of_match_table = spi_ppc4xx_of_match,
580         },
581 };
582 module_platform_driver(spi_ppc4xx_of_driver);
583 
584 MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
585 MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
586 MODULE_LICENSE("GPL");
587 

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