Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/spi/spi-orion.c

  1 /*
  2  * Marvell Orion SPI controller driver
  3  *
  4  * Author: Shadi Ammouri <shadi@marvell.com>
  5  * Copyright (C) 2007-2008 Marvell Ltd.
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License version 2 as
  9  * published by the Free Software Foundation.
 10  */
 11 
 12 #include <linux/interrupt.h>
 13 #include <linux/delay.h>
 14 #include <linux/platform_device.h>
 15 #include <linux/err.h>
 16 #include <linux/io.h>
 17 #include <linux/spi/spi.h>
 18 #include <linux/module.h>
 19 #include <linux/pm_runtime.h>
 20 #include <linux/of.h>
 21 #include <linux/of_device.h>
 22 #include <linux/clk.h>
 23 #include <linux/sizes.h>
 24 #include <asm/unaligned.h>
 25 
 26 #define DRIVER_NAME                     "orion_spi"
 27 
 28 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
 29 #define SPI_AUTOSUSPEND_TIMEOUT         200
 30 
 31 /* Some SoCs using this driver support up to 8 chip selects.
 32  * It is up to the implementer to only use the chip selects
 33  * that are available.
 34  */
 35 #define ORION_NUM_CHIPSELECTS           8
 36 
 37 #define ORION_SPI_WAIT_RDY_MAX_LOOP     2000 /* in usec */
 38 
 39 #define ORION_SPI_IF_CTRL_REG           0x00
 40 #define ORION_SPI_IF_CONFIG_REG         0x04
 41 #define ORION_SPI_DATA_OUT_REG          0x08
 42 #define ORION_SPI_DATA_IN_REG           0x0c
 43 #define ORION_SPI_INT_CAUSE_REG         0x10
 44 
 45 #define ORION_SPI_MODE_CPOL             (1 << 11)
 46 #define ORION_SPI_MODE_CPHA             (1 << 12)
 47 #define ORION_SPI_IF_8_16_BIT_MODE      (1 << 5)
 48 #define ORION_SPI_CLK_PRESCALE_MASK     0x1F
 49 #define ARMADA_SPI_CLK_PRESCALE_MASK    0xDF
 50 #define ORION_SPI_MODE_MASK             (ORION_SPI_MODE_CPOL | \
 51                                          ORION_SPI_MODE_CPHA)
 52 #define ORION_SPI_CS_MASK       0x1C
 53 #define ORION_SPI_CS_SHIFT      2
 54 #define ORION_SPI_CS(cs)        ((cs << ORION_SPI_CS_SHIFT) & \
 55                                         ORION_SPI_CS_MASK)
 56 
 57 enum orion_spi_type {
 58         ORION_SPI,
 59         ARMADA_SPI,
 60 };
 61 
 62 struct orion_spi_dev {
 63         enum orion_spi_type     typ;
 64         unsigned int            min_divisor;
 65         unsigned int            max_divisor;
 66         u32                     prescale_mask;
 67 };
 68 
 69 struct orion_spi {
 70         struct spi_master       *master;
 71         void __iomem            *base;
 72         struct clk              *clk;
 73         const struct orion_spi_dev *devdata;
 74 };
 75 
 76 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
 77 {
 78         return orion_spi->base + reg;
 79 }
 80 
 81 static inline void
 82 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
 83 {
 84         void __iomem *reg_addr = spi_reg(orion_spi, reg);
 85         u32 val;
 86 
 87         val = readl(reg_addr);
 88         val |= mask;
 89         writel(val, reg_addr);
 90 }
 91 
 92 static inline void
 93 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
 94 {
 95         void __iomem *reg_addr = spi_reg(orion_spi, reg);
 96         u32 val;
 97 
 98         val = readl(reg_addr);
 99         val &= ~mask;
100         writel(val, reg_addr);
101 }
102 
103 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
104 {
105         u32 tclk_hz;
106         u32 rate;
107         u32 prescale;
108         u32 reg;
109         struct orion_spi *orion_spi;
110         const struct orion_spi_dev *devdata;
111 
112         orion_spi = spi_master_get_devdata(spi->master);
113         devdata = orion_spi->devdata;
114 
115         tclk_hz = clk_get_rate(orion_spi->clk);
116 
117         if (devdata->typ == ARMADA_SPI) {
118                 unsigned int clk, spr, sppr, sppr2, err;
119                 unsigned int best_spr, best_sppr, best_err;
120 
121                 best_err = speed;
122                 best_spr = 0;
123                 best_sppr = 0;
124 
125                 /* Iterate over the valid range looking for best fit */
126                 for (sppr = 0; sppr < 8; sppr++) {
127                         sppr2 = 0x1 << sppr;
128 
129                         spr = tclk_hz / sppr2;
130                         spr = DIV_ROUND_UP(spr, speed);
131                         if ((spr == 0) || (spr > 15))
132                                 continue;
133 
134                         clk = tclk_hz / (spr * sppr2);
135                         err = speed - clk;
136 
137                         if (err < best_err) {
138                                 best_spr = spr;
139                                 best_sppr = sppr;
140                                 best_err = err;
141                         }
142                 }
143 
144                 if ((best_sppr == 0) && (best_spr == 0))
145                         return -EINVAL;
146 
147                 prescale = ((best_sppr & 0x6) << 5) |
148                         ((best_sppr & 0x1) << 4) | best_spr;
149         } else {
150                 /*
151                  * the supported rates are: 4,6,8...30
152                  * round up as we look for equal or less speed
153                  */
154                 rate = DIV_ROUND_UP(tclk_hz, speed);
155                 rate = roundup(rate, 2);
156 
157                 /* check if requested speed is too small */
158                 if (rate > 30)
159                         return -EINVAL;
160 
161                 if (rate < 4)
162                         rate = 4;
163 
164                 /* Convert the rate to SPI clock divisor value. */
165                 prescale = 0x10 + rate/2;
166         }
167 
168         reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
169         reg = ((reg & ~devdata->prescale_mask) | prescale);
170         writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
171 
172         return 0;
173 }
174 
175 static void
176 orion_spi_mode_set(struct spi_device *spi)
177 {
178         u32 reg;
179         struct orion_spi *orion_spi;
180 
181         orion_spi = spi_master_get_devdata(spi->master);
182 
183         reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
184         reg &= ~ORION_SPI_MODE_MASK;
185         if (spi->mode & SPI_CPOL)
186                 reg |= ORION_SPI_MODE_CPOL;
187         if (spi->mode & SPI_CPHA)
188                 reg |= ORION_SPI_MODE_CPHA;
189         writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
190 }
191 
192 /*
193  * called only when no transfer is active on the bus
194  */
195 static int
196 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
197 {
198         struct orion_spi *orion_spi;
199         unsigned int speed = spi->max_speed_hz;
200         unsigned int bits_per_word = spi->bits_per_word;
201         int     rc;
202 
203         orion_spi = spi_master_get_devdata(spi->master);
204 
205         if ((t != NULL) && t->speed_hz)
206                 speed = t->speed_hz;
207 
208         if ((t != NULL) && t->bits_per_word)
209                 bits_per_word = t->bits_per_word;
210 
211         orion_spi_mode_set(spi);
212 
213         rc = orion_spi_baudrate_set(spi, speed);
214         if (rc)
215                 return rc;
216 
217         if (bits_per_word == 16)
218                 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
219                                   ORION_SPI_IF_8_16_BIT_MODE);
220         else
221                 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
222                                   ORION_SPI_IF_8_16_BIT_MODE);
223 
224         return 0;
225 }
226 
227 static void orion_spi_set_cs(struct spi_device *spi, bool enable)
228 {
229         struct orion_spi *orion_spi;
230 
231         orion_spi = spi_master_get_devdata(spi->master);
232 
233         orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
234         orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
235                                 ORION_SPI_CS(spi->chip_select));
236 
237         /* Chip select logic is inverted from spi_set_cs */
238         if (!enable)
239                 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
240         else
241                 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
242 }
243 
244 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
245 {
246         int i;
247 
248         for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
249                 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
250                         return 1;
251 
252                 udelay(1);
253         }
254 
255         return -1;
256 }
257 
258 static inline int
259 orion_spi_write_read_8bit(struct spi_device *spi,
260                           const u8 **tx_buf, u8 **rx_buf)
261 {
262         void __iomem *tx_reg, *rx_reg, *int_reg;
263         struct orion_spi *orion_spi;
264 
265         orion_spi = spi_master_get_devdata(spi->master);
266         tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
267         rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
268         int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
269 
270         /* clear the interrupt cause register */
271         writel(0x0, int_reg);
272 
273         if (tx_buf && *tx_buf)
274                 writel(*(*tx_buf)++, tx_reg);
275         else
276                 writel(0, tx_reg);
277 
278         if (orion_spi_wait_till_ready(orion_spi) < 0) {
279                 dev_err(&spi->dev, "TXS timed out\n");
280                 return -1;
281         }
282 
283         if (rx_buf && *rx_buf)
284                 *(*rx_buf)++ = readl(rx_reg);
285 
286         return 1;
287 }
288 
289 static inline int
290 orion_spi_write_read_16bit(struct spi_device *spi,
291                            const u16 **tx_buf, u16 **rx_buf)
292 {
293         void __iomem *tx_reg, *rx_reg, *int_reg;
294         struct orion_spi *orion_spi;
295 
296         orion_spi = spi_master_get_devdata(spi->master);
297         tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
298         rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
299         int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
300 
301         /* clear the interrupt cause register */
302         writel(0x0, int_reg);
303 
304         if (tx_buf && *tx_buf)
305                 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
306         else
307                 writel(0, tx_reg);
308 
309         if (orion_spi_wait_till_ready(orion_spi) < 0) {
310                 dev_err(&spi->dev, "TXS timed out\n");
311                 return -1;
312         }
313 
314         if (rx_buf && *rx_buf)
315                 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
316 
317         return 1;
318 }
319 
320 static unsigned int
321 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
322 {
323         unsigned int count;
324         int word_len;
325 
326         word_len = spi->bits_per_word;
327         count = xfer->len;
328 
329         if (word_len == 8) {
330                 const u8 *tx = xfer->tx_buf;
331                 u8 *rx = xfer->rx_buf;
332 
333                 do {
334                         if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
335                                 goto out;
336                         count--;
337                 } while (count);
338         } else if (word_len == 16) {
339                 const u16 *tx = xfer->tx_buf;
340                 u16 *rx = xfer->rx_buf;
341 
342                 do {
343                         if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
344                                 goto out;
345                         count -= 2;
346                 } while (count);
347         }
348 
349 out:
350         return xfer->len - count;
351 }
352 
353 static int orion_spi_transfer_one(struct spi_master *master,
354                                         struct spi_device *spi,
355                                         struct spi_transfer *t)
356 {
357         int status = 0;
358 
359         status = orion_spi_setup_transfer(spi, t);
360         if (status < 0)
361                 return status;
362 
363         if (t->len)
364                 orion_spi_write_read(spi, t);
365 
366         return status;
367 }
368 
369 static int orion_spi_setup(struct spi_device *spi)
370 {
371         return orion_spi_setup_transfer(spi, NULL);
372 }
373 
374 static int orion_spi_reset(struct orion_spi *orion_spi)
375 {
376         /* Verify that the CS is deasserted */
377         orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
378         return 0;
379 }
380 
381 static const struct orion_spi_dev orion_spi_dev_data = {
382         .typ = ORION_SPI,
383         .min_divisor = 4,
384         .max_divisor = 30,
385         .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
386 };
387 
388 static const struct orion_spi_dev armada_spi_dev_data = {
389         .typ = ARMADA_SPI,
390         .min_divisor = 1,
391         .max_divisor = 1920,
392         .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
393 };
394 
395 static const struct of_device_id orion_spi_of_match_table[] = {
396         { .compatible = "marvell,orion-spi", .data = &orion_spi_dev_data, },
397         { .compatible = "marvell,armada-370-spi", .data = &armada_spi_dev_data, },
398         {}
399 };
400 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
401 
402 static int orion_spi_probe(struct platform_device *pdev)
403 {
404         const struct of_device_id *of_id;
405         const struct orion_spi_dev *devdata;
406         struct spi_master *master;
407         struct orion_spi *spi;
408         struct resource *r;
409         unsigned long tclk_hz;
410         int status = 0;
411 
412         master = spi_alloc_master(&pdev->dev, sizeof(*spi));
413         if (master == NULL) {
414                 dev_dbg(&pdev->dev, "master allocation failed\n");
415                 return -ENOMEM;
416         }
417 
418         if (pdev->id != -1)
419                 master->bus_num = pdev->id;
420         if (pdev->dev.of_node) {
421                 u32 cell_index;
422 
423                 if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
424                                           &cell_index))
425                         master->bus_num = cell_index;
426         }
427 
428         /* we support only mode 0, and no options */
429         master->mode_bits = SPI_CPHA | SPI_CPOL;
430         master->set_cs = orion_spi_set_cs;
431         master->transfer_one = orion_spi_transfer_one;
432         master->num_chipselect = ORION_NUM_CHIPSELECTS;
433         master->setup = orion_spi_setup;
434         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
435         master->auto_runtime_pm = true;
436 
437         platform_set_drvdata(pdev, master);
438 
439         spi = spi_master_get_devdata(master);
440         spi->master = master;
441 
442         of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
443         devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
444         spi->devdata = devdata;
445 
446         spi->clk = devm_clk_get(&pdev->dev, NULL);
447         if (IS_ERR(spi->clk)) {
448                 status = PTR_ERR(spi->clk);
449                 goto out;
450         }
451 
452         status = clk_prepare_enable(spi->clk);
453         if (status)
454                 goto out;
455 
456         tclk_hz = clk_get_rate(spi->clk);
457         master->max_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
458         master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
459 
460         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
461         spi->base = devm_ioremap_resource(&pdev->dev, r);
462         if (IS_ERR(spi->base)) {
463                 status = PTR_ERR(spi->base);
464                 goto out_rel_clk;
465         }
466 
467         pm_runtime_set_active(&pdev->dev);
468         pm_runtime_use_autosuspend(&pdev->dev);
469         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
470         pm_runtime_enable(&pdev->dev);
471 
472         status = orion_spi_reset(spi);
473         if (status < 0)
474                 goto out_rel_pm;
475 
476         pm_runtime_mark_last_busy(&pdev->dev);
477         pm_runtime_put_autosuspend(&pdev->dev);
478 
479         master->dev.of_node = pdev->dev.of_node;
480         status = spi_register_master(master);
481         if (status < 0)
482                 goto out_rel_pm;
483 
484         return status;
485 
486 out_rel_pm:
487         pm_runtime_disable(&pdev->dev);
488 out_rel_clk:
489         clk_disable_unprepare(spi->clk);
490 out:
491         spi_master_put(master);
492         return status;
493 }
494 
495 
496 static int orion_spi_remove(struct platform_device *pdev)
497 {
498         struct spi_master *master = platform_get_drvdata(pdev);
499         struct orion_spi *spi = spi_master_get_devdata(master);
500 
501         pm_runtime_get_sync(&pdev->dev);
502         clk_disable_unprepare(spi->clk);
503 
504         spi_unregister_master(master);
505         pm_runtime_disable(&pdev->dev);
506 
507         return 0;
508 }
509 
510 MODULE_ALIAS("platform:" DRIVER_NAME);
511 
512 #ifdef CONFIG_PM
513 static int orion_spi_runtime_suspend(struct device *dev)
514 {
515         struct spi_master *master = dev_get_drvdata(dev);
516         struct orion_spi *spi = spi_master_get_devdata(master);
517 
518         clk_disable_unprepare(spi->clk);
519         return 0;
520 }
521 
522 static int orion_spi_runtime_resume(struct device *dev)
523 {
524         struct spi_master *master = dev_get_drvdata(dev);
525         struct orion_spi *spi = spi_master_get_devdata(master);
526 
527         return clk_prepare_enable(spi->clk);
528 }
529 #endif
530 
531 static const struct dev_pm_ops orion_spi_pm_ops = {
532         SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
533                            orion_spi_runtime_resume,
534                            NULL)
535 };
536 
537 static struct platform_driver orion_spi_driver = {
538         .driver = {
539                 .name   = DRIVER_NAME,
540                 .pm     = &orion_spi_pm_ops,
541                 .of_match_table = of_match_ptr(orion_spi_of_match_table),
542         },
543         .probe          = orion_spi_probe,
544         .remove         = orion_spi_remove,
545 };
546 
547 module_platform_driver(orion_spi_driver);
548 
549 MODULE_DESCRIPTION("Orion SPI driver");
550 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
551 MODULE_LICENSE("GPL");
552 

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